src/mesa/drivers/dri/radeon/server/radeon.h

   1 /**
   2  * \file server/radeon.h
   3  * \brief Radeon 2D driver data structures.
   4  */
   5
   6 /*
   7  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   8  *                VA Linux Systems Inc., Fremont, California.
   9  *
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining
  13  * a copy of this software and associated documentation files (the
  14  * "Software"), to deal in the Software without restriction, including
  15  * without limitation on the rights to use, copy, modify, merge,
  16  * publish, distribute, sublicense, and/or sell copies of the Software,
  17  * and to permit persons to whom the Software is furnished to do so,
  18  * subject to the following conditions:
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial
  22  * portions of the Software.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  28  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  29  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  30  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34
  35 #ifndef _RADEON_H_
  36 #define _RADEON_H_
  37
  38 #include "xf86drm.h"            /* drm_handle_t, etc */
  39
  40 #       define RADEON_AGP_1X_MODE           0x01
  41 #       define RADEON_AGP_2X_MODE           0x02
  42 #       define RADEON_AGP_4X_MODE           0x04
  43 #       define RADEON_AGP_FW_MODE           0x10
  44 #       define RADEON_AGP_MODE_MASK         0x17
  45 #define RADEON_CP_CSQ_CNTL                  0x0740
  46 #       define RADEON_CSQ_CNT_PRIMARY_MASK     (0xff << 0)
  47 #       define RADEON_CSQ_PRIDIS_INDDIS        (0    << 28)
  48 #       define RADEON_CSQ_PRIPIO_INDDIS        (1    << 28)
  49 #       define RADEON_CSQ_PRIBM_INDDIS         (2    << 28)
  50 #       define RADEON_CSQ_PRIPIO_INDBM         (3    << 28)
  51 #       define RADEON_CSQ_PRIBM_INDBM          (4    << 28)
  52 #       define RADEON_CSQ_PRIPIO_INDPIO        (15   << 28)
  53
  54 #define RADEON_PCIGART_TABLE_SIZE       32768
  55
  56 #define PCI_CHIP_R200_BB                0x4242
  57 #define PCI_CHIP_RV250_Id               0x4964
  58 #define PCI_CHIP_RV250_Ie               0x4965
  59 #define PCI_CHIP_RV250_If               0x4966
  60 #define PCI_CHIP_RV250_Ig               0x4967
  61 #define PCI_CHIP_RADEON_LW              0x4C57
  62 #define PCI_CHIP_RADEON_LX              0x4C58
  63 #define PCI_CHIP_RADEON_LY              0x4C59
  64 #define PCI_CHIP_RADEON_LZ              0x4C5A
  65 #define PCI_CHIP_RV250_Ld               0x4C64
  66 #define PCI_CHIP_RV250_Le               0x4C65
  67 #define PCI_CHIP_RV250_Lf               0x4C66
  68 #define PCI_CHIP_RV250_Lg               0x4C67
  69 #define PCI_CHIP_R300_ND                0x4E44
  70 #define PCI_CHIP_R300_NE                0x4E45
  71 #define PCI_CHIP_R300_NF                0x4E46
  72 #define PCI_CHIP_R300_NG                0x4E47
  73 #define PCI_CHIP_RADEON_QD              0x5144
  74 #define PCI_CHIP_RADEON_QE              0x5145
  75 #define PCI_CHIP_RADEON_QF              0x5146
  76 #define PCI_CHIP_RADEON_QG              0x5147
  77 #define PCI_CHIP_R200_QL                0x514C
  78 #define PCI_CHIP_R200_QN                0x514E
  79 #define PCI_CHIP_R200_QO                0x514F
  80 #define PCI_CHIP_RV200_QW               0x5157
  81 #define PCI_CHIP_RV200_QX               0x5158
  82 #define PCI_CHIP_RADEON_QY              0x5159
  83 #define PCI_CHIP_RADEON_QZ              0x515A
  84 #define PCI_CHIP_R200_Ql                0x516C
  85 #define PCI_CHIP_RV370_5460             0x5460
  86 #define PCI_CHIP_RV280_Y_               0x5960
  87 #define PCI_CHIP_RV280_Ya               0x5961
  88 #define PCI_CHIP_RV280_Yb               0x5962
  89 #define PCI_CHIP_RV280_Yc               0x5963
  90
  91 /**
  92  * \brief Chip families.
  93  */
  94 typedef enum {
  95     CHIP_FAMILY_UNKNOW,
  96     CHIP_FAMILY_LEGACY,
  97     CHIP_FAMILY_R128,
  98     CHIP_FAMILY_M3,
  99     CHIP_FAMILY_RADEON,
 100     CHIP_FAMILY_VE,
 101     CHIP_FAMILY_M6,
 102     CHIP_FAMILY_RV200,
 103     CHIP_FAMILY_M7,
 104     CHIP_FAMILY_R200,
 105     CHIP_FAMILY_RV250,
 106     CHIP_FAMILY_M9,
 107     CHIP_FAMILY_RV280,
 108     CHIP_FAMILY_R300,
 109     CHIP_FAMILY_R350,
 110     CHIP_FAMILY_RV350,
 111     CHIP_FAMILY_RV380,  /* RV370/RV380/M22/M24 */
 112     CHIP_FAMILY_R420,   /* R420/R423/M18 */
 113 } RADEONChipFamily;
 114
 115
 116 typedef unsigned long memType;
 117
 118
 119 /**
 120  * \brief Radeon DDX driver private data.
 121  */
 122 typedef struct {
 123    int               Chipset;          /**< \brief Chipset number */
 124    RADEONChipFamily  ChipFamily;       /**< \brief Chip family */
 125
 126    unsigned long     LinearAddr;       /**< \brief Frame buffer physical address */
 127
 128
 129    drmSize           registerSize;     /**< \brief MMIO register map size */
 130    drm_handle_t         registerHandle;   /**< \brief MMIO register map handle */
 131
 132    int               IsPCI;            /* Current card is a PCI card */
 133
 134    /**
 135     * \name AGP
 136     */
 137    /*@{*/
 138    drmSize           gartSize;          /**< \brief AGP map size */
 139    drm_handle_t         gartMemHandle;     /**< \brief AGP map handle */
 140    unsigned long     gartOffset;        /**< \brief AGP offset */
 141    int               gartMode;          /**< \brief AGP mode */
 142    int               gartFastWrite;
 143    /*@}*/
 144
 145    /**
 146     * \name CP ring buffer data
 147     */
 148    /*@{*/
 149    unsigned long     ringStart;        /**< \brief Offset into AGP space */
 150    drm_handle_t         ringHandle;       /**< \brief Handle from drmAddMap() */
 151    drmSize           ringMapSize;      /**< \brief Size of map */
 152    int               ringSize;         /**< \brief Size of ring (in MB) */
 153
 154    unsigned long     ringReadOffset;   /**< \brief Read offset into AGP space */
 155    drm_handle_t         ringReadPtrHandle;/**< \brief Handle from drmAddMap() */
 156    drmSize           ringReadMapSize;  /**< \brief Size of map */
 157    /*@}*/
 158
 159    /**
 160     * \name CP vertex/indirect buffer data
 161     */
 162    /*@{*/
 163    unsigned long     bufStart;         /**< \brief Offset into AGP space */
 164    drm_handle_t         bufHandle;        /**< \brief Handle from drmAddMap() */
 165    drmSize           bufMapSize;       /**< \brief Size of map */
 166    int               bufSize;          /**< \brief Size of buffers (in MB) */
 167    int               bufNumBufs;       /**< \brief Number of buffers */
 168    /*@}*/
 169
 170    /**
 171     * \name CP AGP Texture data
 172     */
 173    /*@{*/
 174    unsigned long     gartTexStart;      /**< \brief Offset into AGP space */
 175    drm_handle_t         gartTexHandle;     /**< \brief Handle from drmAddMap() */
 176    drmSize           gartTexMapSize;    /**< \brief Size of map */
 177    int               gartTexSize;       /**< \brief Size of AGP tex space (in MB) */
 178    int               log2GARTTexGran;
 179    /*@}*/
 180
 181    int               drmMinor;         /**< \brief DRM device minor number */
 182
 183    int               frontOffset;      /**< \brief Front color buffer offset */
 184    int               frontPitch;       /**< \brief Front color buffer pitch */
 185    int               backOffset;       /**< \brief Back color buffer offset */
 186    int               backPitch;        /**< \brief Back color buffer pitch */
 187    int               depthOffset;      /**< \brief Depth buffer offset */
 188    int               depthPitch;       /**< \brief Depth buffer pitch */
 189    int               textureOffset;    /**< \brief Texture area offset */
 190    int               textureSize;      /**< \brief Texture area size */
 191    int               log2TexGran;      /**< \brief Texture granularity in base 2 log */
 192
 193    unsigned int      frontPitchOffset;
 194    unsigned int      backPitchOffset;
 195    unsigned int      depthPitchOffset;
 196
 197    int               colorTiling;      /**< \brief Enable color tiling */
 198
 199    int               irq;              /**< \brief IRQ number */
 200    int               page_flip_enable; /**< \brief Page Flip enable */
 201    unsigned int      gen_int_cntl;
 202    unsigned int      crtc_offset_cntl;
 203
 204    unsigned long     pcieGartTableOffset;
 205 } RADEONInfoRec, *RADEONInfoPtr;
 206
 207
 208 #endif /* _RADEON_H_ */