src/mesa/drivers/dri/radeon/server/radeon.h

   1 /**
   2  * \file server/radeon.h
   3  * \brief Radeon 2D driver data structures.
   4  */
   5
   6 /*
   7  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   8  *                VA Linux Systems Inc., Fremont, California.
   9  *
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining
  13  * a copy of this software and associated documentation files (the
  14  * "Software"), to deal in the Software without restriction, including
  15  * without limitation on the rights to use, copy, modify, merge,
  16  * publish, distribute, sublicense, and/or sell copies of the Software,
  17  * and to permit persons to whom the Software is furnished to do so,
  18  * subject to the following conditions:
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial
  22  * portions of the Software.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  28  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  29  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  30  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.29 2002/10/12 01:38:07 martin Exp $ */
  35
  36 #ifndef _RADEON_H_
  37 #define _RADEON_H_
  38
  39 #include "xf86drm.h"            /* drm_handle_t, etc */
  40
  41 #define PCI_CHIP_R200_BB                0x4242
  42 #define PCI_CHIP_RV250_Id               0x4964
  43 #define PCI_CHIP_RV250_Ie               0x4965
  44 #define PCI_CHIP_RV250_If               0x4966
  45 #define PCI_CHIP_RV250_Ig               0x4967
  46 #define PCI_CHIP_RADEON_LW              0x4C57
  47 #define PCI_CHIP_RADEON_LX              0x4C58
  48 #define PCI_CHIP_RADEON_LY              0x4C59
  49 #define PCI_CHIP_RADEON_LZ              0x4C5A
  50 #define PCI_CHIP_RV250_Ld               0x4C64
  51 #define PCI_CHIP_RV250_Le               0x4C65
  52 #define PCI_CHIP_RV250_Lf               0x4C66
  53 #define PCI_CHIP_RV250_Lg               0x4C67
  54 #define PCI_CHIP_R300_ND                0x4E44
  55 #define PCI_CHIP_R300_NE                0x4E45
  56 #define PCI_CHIP_R300_NF                0x4E46
  57 #define PCI_CHIP_R300_NG                0x4E47
  58 #define PCI_CHIP_RADEON_QD              0x5144
  59 #define PCI_CHIP_RADEON_QE              0x5145
  60 #define PCI_CHIP_RADEON_QF              0x5146
  61 #define PCI_CHIP_RADEON_QG              0x5147
  62 #define PCI_CHIP_R200_QL                0x514C
  63 #define PCI_CHIP_R200_QN                0x514E
  64 #define PCI_CHIP_R200_QO                0x514F
  65 #define PCI_CHIP_RV200_QW               0x5157
  66 #define PCI_CHIP_RV200_QX               0x5158
  67 #define PCI_CHIP_RADEON_QY              0x5159
  68 #define PCI_CHIP_RADEON_QZ              0x515A
  69 #define PCI_CHIP_R200_Ql                0x516C
  70 #define PCI_CHIP_RV280_Y_               0x5960
  71 #define PCI_CHIP_RV280_Ya               0x5961
  72 #define PCI_CHIP_RV280_Yb               0x5962
  73 #define PCI_CHIP_RV280_Yc               0x5963
  74
  75 /**
  76  * \brief Chip families.
  77  */
  78 typedef enum {
  79     CHIP_FAMILY_UNKNOW,
  80     CHIP_FAMILY_LEGACY,
  81     CHIP_FAMILY_R128,
  82     CHIP_FAMILY_M3,
  83     CHIP_FAMILY_RADEON,
  84     CHIP_FAMILY_VE,
  85     CHIP_FAMILY_M6,
  86     CHIP_FAMILY_RV200,
  87     CHIP_FAMILY_M7,
  88     CHIP_FAMILY_R200,
  89     CHIP_FAMILY_RV250,
  90     CHIP_FAMILY_M9,
  91     CHIP_FAMILY_RV280,
  92     CHIP_FAMILY_R300
  93 } RADEONChipFamily;
  94
  95
  96 typedef unsigned long memType;
  97
  98
  99 /**
 100  * \brief Radeon DDX driver private data.
 101  */
 102 typedef struct {
 103    int               Chipset;          /**< \brief Chipset number */
 104    RADEONChipFamily  ChipFamily;       /**< \brief Chip family */
 105
 106    unsigned long     LinearAddr;       /**< \brief Frame buffer physical address */
 107
 108
 109    drmSize           registerSize;     /**< \brief MMIO register map size */
 110    drm_handle_t         registerHandle;   /**< \brief MMIO register map handle */
 111
 112    int               IsPCI;            /* Current card is a PCI card */
 113
 114    /**
 115     * \name AGP
 116     */
 117    /*@{*/
 118    drmSize           gartSize;          /**< \brief AGP map size */
 119    drm_handle_t         gartMemHandle;     /**< \brief AGP map handle */
 120    unsigned long     gartOffset;        /**< \brief AGP offset */
 121    int               gartMode;          /**< \brief AGP mode */
 122    int               gartFastWrite;
 123    /*@}*/
 124
 125    /**
 126     * \name CP ring buffer data
 127     */
 128    /*@{*/
 129    unsigned long     ringStart;        /**< \brief Offset into AGP space */
 130    drm_handle_t         ringHandle;       /**< \brief Handle from drmAddMap() */
 131    drmSize           ringMapSize;      /**< \brief Size of map */
 132    int               ringSize;         /**< \brief Size of ring (in MB) */
 133
 134    unsigned long     ringReadOffset;   /**< \brief Read offset into AGP space */
 135    drm_handle_t         ringReadPtrHandle;/**< \brief Handle from drmAddMap() */
 136    drmSize           ringReadMapSize;  /**< \brief Size of map */
 137    /*@}*/
 138
 139    /**
 140     * \name CP vertex/indirect buffer data
 141     */
 142    /*@{*/
 143    unsigned long     bufStart;         /**< \brief Offset into AGP space */
 144    drm_handle_t         bufHandle;        /**< \brief Handle from drmAddMap() */
 145    drmSize           bufMapSize;       /**< \brief Size of map */
 146    int               bufSize;          /**< \brief Size of buffers (in MB) */
 147    int               bufNumBufs;       /**< \brief Number of buffers */
 148    /*@}*/
 149
 150    /**
 151     * \name CP AGP Texture data
 152     */
 153    /*@{*/
 154    unsigned long     gartTexStart;      /**< \brief Offset into AGP space */
 155    drm_handle_t         gartTexHandle;     /**< \brief Handle from drmAddMap() */
 156    drmSize           gartTexMapSize;    /**< \brief Size of map */
 157    int               gartTexSize;       /**< \brief Size of AGP tex space (in MB) */
 158    int               log2GARTTexGran;
 159    /*@}*/
 160
 161    int               drmMinor;         /**< \brief DRM device minor number */
 162
 163    int               frontOffset;      /**< \brief Front color buffer offset */
 164    int               frontPitch;       /**< \brief Front color buffer pitch */
 165    int               backOffset;       /**< \brief Back color buffer offset */
 166    int               backPitch;        /**< \brief Back color buffer pitch */
 167    int               depthOffset;      /**< \brief Depth buffer offset */
 168    int               depthPitch;       /**< \brief Depth buffer pitch */
 169    int               textureOffset;    /**< \brief Texture area offset */
 170    int               textureSize;      /**< \brief Texture area size */
 171    int               log2TexGran;      /**< \brief Texture granularity in base 2 log */
 172
 173    unsigned int      frontPitchOffset;
 174    unsigned int      backPitchOffset;
 175    unsigned int      depthPitchOffset;
 176
 177    int               colorTiling;      /**< \brief Enable color tiling */
 178
 179    int               irq;              /**< \brief IRQ number */
 180    int               page_flip_enable; /**< \brief Page Flip enable */
 181    unsigned int      gen_int_cntl;
 182    unsigned int      crtc_offset_cntl;
 183
 184 } RADEONInfoRec, *RADEONInfoPtr;
 185
 186
 187 #endif /* _RADEON_H_ */