2 * \file server/radeon_macros.h
3 * \brief Macros for Radeon MMIO operation.
5 * \authors Kevin E. Martin <martin@xfree86.org>
6 * \authors Rickard E. Faith <faith@valinux.com>
7 * \authors Alan Hourihane <alanh@fairlite.demon.co.uk>
11 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
12 * VA Linux Systems Inc., Fremont, California.
14 * All Rights Reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining
17 * a copy of this software and associated documentation files (the
18 * "Software"), to deal in the Software without restriction, including
19 * without limitation on the rights to use, copy, modify, merge,
20 * publish, distribute, sublicense, and/or sell copies of the Software,
21 * and to permit persons to whom the Software is furnished to do so,
22 * subject to the following conditions:
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial
26 * portions of the Software.
28 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
31 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
32 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
33 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
34 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
35 * DEALINGS IN THE SOFTWARE.
38 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */
40 #ifndef _RADEON_MACROS_H_
41 #define _RADEON_MACROS_H_
45 # define MMIO_IN8(base, offset) \
46 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
47 # define MMIO_IN32(base, offset) \
48 read_MMIO_LE32(base, offset)
49 # define MMIO_OUT8(base, offset, val) \
50 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
51 # define MMIO_OUT32(base, offset, val) \
52 *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
55 /* Memory mapped register access macros */
56 #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
57 #define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
58 #define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
59 #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)
61 #define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr)))
64 #define OUTREGP(addr, val, mask) \
66 GLuint tmp = INREG(addr); \
72 #define INPLL(dpy, addr) RADEONINPLL(dpy, addr)
74 #define OUTPLL(addr, val) \
76 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \
78 OUTREG(RADEON_CLOCK_CNTL_DATA, val); \
81 #define OUTPLLP(dpy, addr, val, mask) \
83 GLuint tmp = INPLL(dpy, addr); \
89 #define OUTPAL_START(idx) \
91 OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
94 #define OUTPAL_NEXT(r, g, b) \
96 OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
99 #define OUTPAL_NEXT_CARD32(v) \
101 OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
104 #define OUTPAL(idx, r, g, b) \
106 OUTPAL_START((idx)); \
107 OUTPAL_NEXT((r), (g), (b)); \
110 #define INPAL_START(idx) \
112 OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
115 #define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
117 #define PAL_SELECT(idx) \
120 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
121 (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \
123 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
124 RADEON_DAC2_PALETTE_ACC_CTL); \