src/mesa/drivers/dri/radeon/server/radeon_macros.h

   1 /**
   2  * \file server/radeon_macros.h
   3  * \brief Macros for Radeon MMIO operation.
   4  *
   5  * \authors Kevin E. Martin <martin@xfree86.org>
   6  * \authors Rickard E. Faith <faith@valinux.com>
   7  * \authors Alan Hourihane <alanh@fairlite.demon.co.uk>
   8  */
   9
  10 /*
  11  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  12  *                VA Linux Systems Inc., Fremont, California.
  13  *
  14  * All Rights Reserved.
  15  *
  16  * Permission is hereby granted, free of charge, to any person obtaining
  17  * a copy of this software and associated documentation files (the
  18  * "Software"), to deal in the Software without restriction, including
  19  * without limitation on the rights to use, copy, modify, merge,
  20  * publish, distribute, sublicense, and/or sell copies of the Software,
  21  * and to permit persons to whom the Software is furnished to do so,
  22  * subject to the following conditions:
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial
  26  * portions of the Software.
  27  *
  28  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  29  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  30  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  31  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  32  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  33  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  34  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  35  * DEALINGS IN THE SOFTWARE.
  36  */
  37
  38 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */
  39
  40 #ifndef _RADEON_MACROS_H_
  41 #define _RADEON_MACROS_H_
  42
  43 #include <mmio.h>
  44
  45 #  define MMIO_IN8(base, offset) \
  46         *(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
  47 #  define MMIO_IN32(base, offset) \
  48         read_MMIO_LE32(base, offset)
  49 #  define MMIO_OUT8(base, offset, val) \
  50         *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
  51 #  define MMIO_OUT32(base, offset, val) \
  52         *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
  53
  54
  55                                 /* Memory mapped register access macros */
  56 #define INREG8(addr)        MMIO_IN8(RADEONMMIO, addr)
  57 #define INREG(addr)         MMIO_IN32(RADEONMMIO, addr)
  58 #define OUTREG8(addr, val)  MMIO_OUT8(RADEONMMIO, addr, val)
  59 #define OUTREG(addr, val)   MMIO_OUT32(RADEONMMIO, addr, val)
  60
  61 #define ADDRREG(addr)       ((volatile GLuint *)(pointer)(RADEONMMIO + (addr)))
  62
  63
  64 #define OUTREGP(addr, val, mask)                                        \
  65 do {                                                                    \
  66     GLuint tmp = INREG(addr);                                           \
  67     tmp &= (mask);                                                      \
  68     tmp |= (val);                                                       \
  69     OUTREG(addr, tmp);                                                  \
  70 } while (0)
  71
  72 #define INPLL(dpy, addr) RADEONINPLL(dpy, addr)
  73
  74 #define OUTPLL(addr, val)                                               \
  75 do {                                                                    \
  76     OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |                 \
  77                                       RADEON_PLL_WR_EN));               \
  78     OUTREG(RADEON_CLOCK_CNTL_DATA, val);                                \
  79 } while (0)
  80
  81 #define OUTPLLP(dpy, addr, val, mask)                                   \
  82 do {                                                                    \
  83     GLuint tmp = INPLL(dpy, addr);                                      \
  84     tmp &= (mask);                                                      \
  85     tmp |= (val);                                                       \
  86     OUTPLL(addr, tmp);                                                  \
  87 } while (0)
  88
  89 #define OUTPAL_START(idx)                                               \
  90 do {                                                                    \
  91     OUTREG8(RADEON_PALETTE_INDEX, (idx));                               \
  92 } while (0)
  93
  94 #define OUTPAL_NEXT(r, g, b)                                            \
  95 do {                                                                    \
  96     OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));        \
  97 } while (0)
  98
  99 #define OUTPAL_NEXT_CARD32(v)                                           \
 100 do {                                                                    \
 101     OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff));                      \
 102 } while (0)
 103
 104 #define OUTPAL(idx, r, g, b)                                            \
 105 do {                                                                    \
 106     OUTPAL_START((idx));                                                \
 107     OUTPAL_NEXT((r), (g), (b));                                         \
 108 } while (0)
 109
 110 #define INPAL_START(idx)                                                \
 111 do {                                                                    \
 112     OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);                          \
 113 } while (0)
 114
 115 #define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
 116
 117 #define PAL_SELECT(idx)                                                 \
 118 do {                                                                    \
 119     if (!idx) {                                                         \
 120         OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &              \
 121                (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL);                   \
 122     } else {                                                            \
 123         OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |              \
 124                RADEON_DAC2_PALETTE_ACC_CTL);                            \
 125     }                                                                   \
 126 } while (0)
 127
 128
 129 #endif