src/mesa/drivers/dri/radeon/server/radeon_sarea.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.5 2002/10/30 12:52:14 alanh Exp $ */
   2 /*
   3  * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
   4  *                VA Linux Systems Inc., Fremont, California.
   5  *
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation on the rights to use, copy, modify, merge,
  12  * publish, distribute, sublicense, and/or sell copies of the Software,
  13  * and to permit persons to whom the Software is furnished to do so,
  14  * subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial
  18  * portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  23  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  24  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  25  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  26  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  27  * DEALINGS IN THE SOFTWARE.
  28  */
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@xfree86.org>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *
  35  */
  36
  37 #ifndef _RADEON_SAREA_H_
  38 #define _RADEON_SAREA_H_
  39
  40 /* WARNING: If you change any of these defines, make sure to change the
  41  * defines in the kernel file (radeon_drm.h)
  42  */
  43 #ifndef __RADEON_SAREA_DEFINES__
  44 #define __RADEON_SAREA_DEFINES__
  45
  46 /* What needs to be changed for the current vertex buffer? */
  47 #define RADEON_UPLOAD_CONTEXT           0x00000001
  48 #define RADEON_UPLOAD_VERTFMT           0x00000002
  49 #define RADEON_UPLOAD_LINE              0x00000004
  50 #define RADEON_UPLOAD_BUMPMAP           0x00000008
  51 #define RADEON_UPLOAD_MASKS             0x00000010
  52 #define RADEON_UPLOAD_VIEWPORT          0x00000020
  53 #define RADEON_UPLOAD_SETUP             0x00000040
  54 #define RADEON_UPLOAD_TCL               0x00000080
  55 #define RADEON_UPLOAD_MISC              0x00000100
  56 #define RADEON_UPLOAD_TEX0              0x00000200
  57 #define RADEON_UPLOAD_TEX1              0x00000400
  58 #define RADEON_UPLOAD_TEX2              0x00000800
  59 #define RADEON_UPLOAD_TEX0IMAGES        0x00001000
  60 #define RADEON_UPLOAD_TEX1IMAGES        0x00002000
  61 #define RADEON_UPLOAD_TEX2IMAGES        0x00004000
  62 #define RADEON_UPLOAD_CLIPRECTS         0x00008000 /* handled client-side */
  63 #define RADEON_REQUIRE_QUIESCENCE       0x00010000
  64 #define RADEON_UPLOAD_ZBIAS             0x00020000
  65 #define RADEON_UPLOAD_ALL               0x0002ffff
  66 #define RADEON_UPLOAD_CONTEXT_ALL       0x000201ff
  67
  68 #define RADEON_FRONT                    0x1
  69 #define RADEON_BACK                     0x2
  70 #define RADEON_DEPTH                    0x4
  71 #define RADEON_STENCIL                  0x8
  72
  73 /* Primitive types */
  74 #define RADEON_POINTS                   0x1
  75 #define RADEON_LINES                    0x2
  76 #define RADEON_LINE_STRIP               0x3
  77 #define RADEON_TRIANGLES                0x4
  78 #define RADEON_TRIANGLE_FAN             0x5
  79 #define RADEON_TRIANGLE_STRIP           0x6
  80 #define RADEON_3VTX_POINTS              0x9
  81 #define RADEON_3VTX_LINES               0xa
  82
  83 /* Vertex/indirect buffer size */
  84 #define RADEON_BUFFER_SIZE              65536
  85
  86 /* Byte offsets for indirect buffer data */
  87 #define RADEON_INDEX_PRIM_OFFSET        20
  88 #define RADEON_HOSTDATA_BLIT_OFFSET     32
  89
  90 #define RADEON_SCRATCH_REG_OFFSET       32
  91
  92 /* Keep these small for testing */
  93 #define RADEON_NR_SAREA_CLIPRECTS       12
  94
  95 /* There are 2 heaps (local/GART).  Each region within a heap is a
  96  * minimum of 64k, and there are at most 64 of them per heap.
  97  */
  98 #define RADEON_CARD_HEAP                0
  99 #define RADEON_GART_HEAP                1
 100 #define RADEON_NR_TEX_HEAPS             2
 101 #define RADEON_NR_TEX_REGIONS           64
 102 #define RADEON_LOG_TEX_GRANULARITY      16
 103
 104 #define RADEON_MAX_TEXTURE_LEVELS       12
 105 #define RADEON_MAX_TEXTURE_UNITS        3
 106
 107 /* Blits have strict offset rules.  All blit offset must be aligned on
 108  * a 1K-byte boundary.
 109  */
 110 #define RADEON_OFFSET_SHIFT             10
 111 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 112 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 113
 114 #endif /* __RADEON_SAREA_DEFINES__ */
 115
 116 typedef struct {
 117     unsigned int red;
 118     unsigned int green;
 119     unsigned int blue;
 120     unsigned int alpha;
 121 } radeon_color_regs_t;
 122
 123 typedef struct {
 124     /* Context state */
 125     unsigned int pp_misc;
 126     unsigned int pp_fog_color;
 127     unsigned int re_solid_color;
 128     unsigned int rb3d_blendcntl;
 129     unsigned int rb3d_depthoffset;
 130     unsigned int rb3d_depthpitch;
 131     unsigned int rb3d_zstencilcntl;
 132
 133     unsigned int pp_cntl;
 134     unsigned int rb3d_cntl;
 135     unsigned int rb3d_coloroffset;
 136     unsigned int re_width_height;
 137     unsigned int rb3d_colorpitch;
 138     unsigned int se_cntl;
 139
 140     /* Vertex format state */
 141     unsigned int se_coord_fmt;
 142
 143     /* Line state */
 144     unsigned int re_line_pattern;
 145     unsigned int re_line_state;
 146
 147     unsigned int se_line_width;
 148
 149     /* Bumpmap state */
 150     unsigned int pp_lum_matrix;
 151
 152     unsigned int pp_rot_matrix_0;
 153     unsigned int pp_rot_matrix_1;
 154
 155     /* Mask state */
 156     unsigned int rb3d_stencilrefmask;
 157     unsigned int rb3d_ropcntl;
 158     unsigned int rb3d_planemask;
 159
 160     /* Viewport state */
 161     unsigned int se_vport_xscale;
 162     unsigned int se_vport_xoffset;
 163     unsigned int se_vport_yscale;
 164     unsigned int se_vport_yoffset;
 165     unsigned int se_vport_zscale;
 166     unsigned int se_vport_zoffset;
 167
 168     /* Setup state */
 169     unsigned int se_cntl_status;
 170
 171     /* Misc state */
 172     unsigned int re_top_left;
 173     unsigned int re_misc;
 174 } radeon_context_regs_t;
 175
 176 /* Setup registers for each texture unit */
 177 typedef struct {
 178     unsigned int pp_txfilter;
 179     unsigned int pp_txformat;
 180     unsigned int pp_txoffset;
 181     unsigned int pp_txcblend;
 182     unsigned int pp_txablend;
 183     unsigned int pp_tfactor;
 184     unsigned int pp_border_color;
 185 } radeon_texture_regs_t;
 186
 187 typedef struct {
 188     /* The channel for communication of state information to the kernel
 189      * on firing a vertex buffer.
 190      */
 191     radeon_context_regs_t ContextState;
 192     radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
 193     unsigned int dirty;
 194     unsigned int vertsize;
 195     unsigned int vc_format;
 196
 197     /* The current cliprects, or a subset thereof */
 198     XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
 199     unsigned int nbox;
 200
 201     /* Counters for throttling of rendering clients */
 202     unsigned int last_frame;
 203     unsigned int last_dispatch;
 204     unsigned int last_clear;
 205
 206     /* Maintain an LRU of contiguous regions of texture space.  If you
 207      * think you own a region of texture memory, and it has an age
 208      * different to the one you set, then you are mistaken and it has
 209      * been stolen by another client.  If global texAge hasn't changed,
 210      * there is no need to walk the list.
 211      *
 212      * These regions can be used as a proxy for the fine-grained texture
 213      * information of other clients - by maintaining them in the same
 214      * lru which is used to age their own textures, clients have an
 215      * approximate lru for the whole of global texture space, and can
 216      * make informed decisions as to which areas to kick out.  There is
 217      * no need to choose whether to kick out your own texture or someone
 218      * else's - simply eject them all in LRU order.
 219      */
 220                                 /* Last elt is sentinal */
 221     drmTextureRegion texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
 222                                 /* last time texture was uploaded */
 223     unsigned int texAge[RADEON_NR_TEX_HEAPS];
 224
 225     int ctxOwner;               /* last context to upload state */
 226     int pfAllowPageFlip;        /* set by the 2d driver, read by the client */
 227     int pfCurrentPage;          /* set by kernel, read by others */
 228     int crtc2_base;             /* for pageflipping with CloneMode */
 229 } RADEONSAREAPriv, *RADEONSAREAPrivPtr;
 230
 231 #endif