src/mesa/drivers/dri/savage/savage_bci.h

   1 /*
   2  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25
  26 #ifndef SAVAGE_BCI_H
  27 #define SAVAGE_BCI_H
  28 /***********************
  29   3D and 2D command
  30 ************************/
  31
  32 typedef enum {
  33     AMO_BurstCmdData=   0x01010000,
  34     AMO_3DReg=          0x01048500,
  35     AMO_MotionCompReg=  0x01048900,
  36     AMO_VideoEngUnit=   0x01048A00,
  37     AMO_CmdBufAddr=     0x01048c14,
  38     AMO_TiledSurfReg0=  0x01048C40,
  39     AMO_TiledSurfReg1=  0x01048C44,
  40     AMO_TiledSurfReg2=  0x01048C48,
  41     AMO_TiledSurfReg3=  0x01048C4C,
  42     AMO_TiledSurfReg4=  0x01048C50,
  43     AMO_TiledSurfReg5=  0x01048C54,
  44     AMO_TiledSurfReg6=  0x01048C58,
  45     AMO_TiledSurfReg7=  0x01048C5C,
  46     AMO_LPBModeReg=     0x0100FF00,
  47     AMO_LPBFifoSat=     0x0100FF04,
  48     AMO_LPBIntFlag=     0x0100FF08,
  49     AMO_LPBFmBufA0=     0x0100FF0C,
  50     AMO_LPBFmBufA1=     0x0100FF10,
  51     AMO_LPBRdWtAdr=     0x0100FF14,
  52     AMO_LPBRdWtDat=     0x0100FF18,
  53     AMO_LPBIOPort =     0x0100FF1C,
  54     AMO_LPBSerPort=     0x0100FF20,
  55     AMO_LPBVidInWinSz=  0x0100FF24,
  56     AMO_LPBVidDatOffs=  0x0100FF28,
  57     AMO_LPBHorScalCtrl= 0x0100FF2C,
  58     AMO_LPBVerDeciCtrl= 0x0100FF30,
  59     AMO_LPBLnStride=    0x0100FF34,
  60     AMO_LPBFmBufAddr2=  0x0100FF38,
  61     AMO_LPBVidCapVDCtrl=0x0100FF3C,
  62
  63     AMO_LPBVidCapFdStAd=0x0100FF60,
  64     AMO_LPBVidCapFdMdAd=0x0100FF64,
  65     AMO_LPBVidCapFdBtAd=0x0100FF68,
  66     AMO_LPBVidCapFdSize=0x0100FF6C,
  67     AMO_LPBBilinDecim1= 0x0100FF70,
  68     AMO_LPBBilinDecim2= 0x0100FF74,
  69     AMO_LPBBilinDecim3= 0x0100FF78,
  70     AMO_LPBDspVEUHorSRR=0x0100FF7C,
  71     AMO_LPBDspVEUVerSRR=0x0100FF80,
  72     AMO_LPBDspVeuDnScDR=0x0100FF84,
  73     AMO_LPB_VEUERPReg=  0x0100FF88,
  74     AMO_LPB_VBISelReg=  0x0100FF8C,
  75     AMO_LPB_VBIBasAdReg=0x0100FF90,
  76     AMO_LPB_DatOffsReg= 0x0100FF94,
  77     AMO_LPB_VBIVerDcReg=0x0100FF98,
  78     AMO_LPB_VBICtrlReg= 0x0100FF9C,
  79     AMO_LPB_VIPXferCtrl=0x0100FFA0,
  80     AMO_LPB_FIFOWtMark= 0x0100FFA4,
  81     AMO_LPB_FIFOCount=  0x0100FFA8,
  82     AMO_LPBFdSkipPat=   0x0100FFAC,
  83     AMO_LPBCapVEUHorSRR=0x0100FFB0,
  84     AMO_LPBCapVEUVerSRR=0x0100FFB4,
  85     AMO_LPBCapVeuDnScDR=0x0100FFB8
  86
  87 }AddressMapOffset;
  88 /*more to add*/
  89
  90
  91 typedef enum {
  92   CMD_DrawPrim=0x10,          /*10000*/
  93   CMD_DrawIdxPrim=0x11,       /*10001*/
  94   CMD_SetRegister=0x12,       /*10010*/
  95   CMD_UpdateShadowStat=0x13 , /*10011*/
  96   CMD_PageFlip=0x14,          /* 10100*/
  97   CMD_BusMasterImgXfer=0x15,  /* 10101*/
  98   CMD_ScaledImgXfer=0x16,     /* 10110*/
  99   CMD_Macroblock=0x17,         /*10111*/
 100   CMD_Wait= 0x18,             /*11000*/
 101   CMD_2D_NOP=0x08,            /* 01000*/
 102   CMD_2D_RCT=0x09,            /*01001   rectangular fill*/
 103   CMD_2D_SCNL=0x0a,           /* 01010   scan line*/
 104   CMD_2D_LIN=0x0b,            /*01011   line*/
 105   CMD_2D_SMTXT=0x0c,          /*01100*/
 106   CMD_2D_BPTXT=0x0d,          /*01101*/
 107   CMD_InitFlag=0x1f           /*11111, for S/W initialization control*/
 108 }Command;
 109
 110
 111 typedef enum {
 112     VRR_List,
 113     VRR_Strip,
 114     VRR_Fan,
 115     VRR_QuadList
 116 }VertexReplaceRule;
 117
 118 /***********************
 119    Destination
 120 ************************/
 121
 122 typedef enum {
 123     DFT_RGB565 = 0,
 124     DFT_XRGB8888
 125 }DestinationFmt;
 126
 127
 128 /*************************
 129     Z Buffer / Alpha test
 130 *************************/
 131
 132 typedef enum {
 133     CF_Never,
 134     CF_Less,
 135     CF_Equal,
 136     CF_LessEqual,
 137     CF_Greater,
 138     CF_NotEqual,
 139     CF_GreaterEqual,
 140     CF_Always
 141 }ZCmpFunc;   /* same for Alpha test and Stencil test compare function */
 142
 143 typedef ZCmpFunc ACmpFunc;
 144
 145 typedef enum {
 146   ZDS_16i,    /* .16 fixed*/
 147   ZDS_32f     /* 1.8.15 float*/
 148 }ZDepthSelect;
 149
 150
 151 /**********************************
 152     BCI Register Addressing Index
 153 ***********************************/
 154 typedef enum {
 155
 156     CRI_VTX0_X =    0x00,
 157     CRI_VTX0_Y =    0x01,
 158     CRI_VTX0_W =    0x02,
 159     CRI_VTX0_DIFFU= 0x03,
 160     CRI_VTX0_SPECU= 0x04,
 161     CRI_VTX0_U =    0x05,
 162     CRI_VTX0_V =    0x06,
 163     CRI_VTX0_U2 =   0x07,
 164     CRI_VTX0_V2 =   0x08,
 165     CRI_VTX1_X =    0x09,
 166     CRI_VTX1_Y =    0x0a,
 167     CRI_VTX1_W =    0x0b,
 168     CRI_VTX1_DIFFU= 0x0c,
 169     CRI_VTX1_SPECU= 0x0d,
 170     CRI_VTX1_U =    0x0e,
 171     CRI_VTX1_V =    0x0f,
 172     CRI_VTX1_U2 =   0x10,
 173     CRI_VTX1_V2 =   0x11,
 174     CRI_VTX2_X =    0x12,
 175     CRI_VTX2_Y =    0x13,
 176     CRI_VTX2_W =    0x14,
 177     CRI_VTX2_DIFFU= 0x15,
 178     CRI_VTX2_SPECU= 0x16,
 179     CRI_VTX2_U =    0x17,
 180     CRI_VTX2_V =    0x18,
 181     CRI_VTX2_U2 =   0x19,
 182     CRI_VTX2_V2 =   0x1a,
 183
 184     CRI_ZPixelOffset  = 0x1d,
 185     CRI_DrawCtrlLocal = 0x1e,
 186     CRI_TexPalAddr    = 0x1f,
 187     CRI_TexCtrl0      = 0x20,
 188     CRI_TexCtrl1      = 0x21,
 189     CRI_TexAddr0      = 0x22,
 190     CRI_TexAddr1      = 0x23,
 191     CRI_TexBlendCtrl0 = 0x24,
 192     CRI_TexBlendCtrl1 = 0x25,
 193     CRI_TexXprClr     = 0x26,
 194     CRI_TexDescr      = 0x27,
 195
 196     CRI_FogTable00= 0x28,
 197     CRI_FogTable04= 0x29,
 198     CRI_FogTable08= 0x2a,
 199     CRI_FogTable12= 0x2b,
 200     CRI_FogTable16= 0x2c,
 201     CRI_FogTable20= 0x2d,
 202     CRI_FogTable24= 0x2e,
 203     CRI_FogTable28= 0x2f,
 204     CRI_FogCtrl=    0x30,
 205     CRI_StencilCtrl= 0x31,
 206     CRI_ZBufCtrl=   0x32,
 207     CRI_ZBufOffset= 0x33,
 208     CRI_DstCtrl=    0x34,
 209     CRI_DrawCtrlGlobal0=   0x35,
 210     CRI_DrawCtrlGlobal1=   0x36,
 211     CRI_ZRW_WTMK =  0x37,
 212     CRI_DST_WTMK =  0x38,
 213     CRI_TexBlendColor= 0x39,
 214
 215     CRI_VertBufAddr= 0x3e,
 216     /* new in ms1*/
 217     CRI_MauFrameAddr0 = 0x40,
 218     CRI_MauFrameAddr1 = 0x41,
 219     CRI_MauFrameAddr2 = 0x42,
 220     CRI_MauFrameAddr3 = 0x43,
 221     CRI_FrameDesc     = 0x44,
 222     CRI_IDCT9bitEn    = 0x45,
 223     CRI_MV0           = 0x46,
 224     CRI_MV1           = 0x47,
 225     CRI_MV2           = 0x48,
 226     CRI_MV3           = 0x49,
 227     CRI_MacroDescr    = 0x4a,  /*kickoff?*/
 228
 229     CRI_MeuCtrl = 0x50,
 230     CRI_SrcYAddr = 0x51,
 231     CRI_DestAddr = 0x52,
 232     CRI_FmtrSrcDimen = 0x53,
 233     CRI_FmtrDestDimen = 0x54,
 234     CRI_SrcCbAddr = 0x55,
 235     CRI_SrcCrAddr = 0x56,
 236     CRI_SrcCrCbStride = 0x57,
 237
 238     CRI_BCI_Power= 0x5f,
 239
 240     CRI_PSCtrl=0xA0,
 241     CRI_SSClrKeyCtrl=0xA1,
 242     CRI_SSCtrl=0xA4,
 243     CRI_SSChromUpBound=0xA5,
 244     CRI_SSHoriScaleCtrl=0xA6,
 245     CRI_SSClrAdj=0xA7,
 246     CRI_SSBlendCtrl=0xA8,
 247     CRI_PSFBAddr0=0xB0,
 248     CRI_PSFBAddr1=0xB1,
 249     CRI_PSStride=0xB2,
 250     CRI_DB_LPB_Support=0xB3,
 251     CRI_SSFBAddr0=0xB4,
 252     CRI_SSFBAddr1=0xB5,
 253     CRI_SSStride=0xB6,
 254     CRI_SSOpaqueCtrl=0xB7,
 255     CRI_SSVertScaleCtrl=0xB8,
 256     CRI_SSVertInitValue=0xB9,
 257     CRI_SSSrcLineCnt=0xBA,
 258     CRI_FIFO_RAS_Ctrl=0xBB,
 259     CRI_PSWinStartCoord=0xBC,
 260     CRI_PSWinSize=0xBD,
 261     CRI_SSWinStartCoord=0xBE,
 262     CRI_SSWinSize=0xBF,
 263     CRI_PSFIFOMon0=0xC0,
 264     CRI_SSFIFOMon0=0xC1,
 265     CRI_PSFIFOMon1=0xC2,
 266     CRI_SSFIFOMon1=0xC3,
 267     CRI_PSFBSize=0xC4,
 268     CRI_SSFBSize=0xC5,
 269     CRI_SSFBAddr2=0xC6,
 270     /* 2D register starts at D0*/
 271     CRI_CurrXY=0xD0,
 272     CRI_DstXYorStep=0xD1 ,
 273     CRI_LineErr=0xD2 ,
 274     CRI_DrawCmd=0xD3,   /*kick off for image xfer*/
 275     CRI_ShortStrkVecXfer=0xD4,
 276     CRI_BackClr=0xD5,
 277     CRI_ForeClr=0xD6,
 278     CRI_BitPlaneWtMask=0xD7,
 279     CRI_BitPlaneRdMask=0xD8,
 280     CRI_ClrCmp=0xD9 ,
 281     CRI_BackAndForeMix=0xDA ,
 282     CRI_TopLeftSciss=0xDB ,
 283     CRI_BotRightSciss=0xDC ,
 284     CRI_PixOrMultiCtrl=0xDD ,
 285     CRI_MultiCtrlOrRdSelct=0xDE ,
 286     CRI_MinorOrMajorAxisCnt=0xDF ,
 287     CRI_GlobalBmpDesc1=0xE0 ,
 288     CRI_GlobalBmpDesc2=0xE1 ,
 289     CRI_BurstPriBmpDesc1=0xE2 ,
 290     CRI_BurstPriBmpDesc2=0xE3 ,
 291     CRI_BurstSecBmpDesc1=0xE4 ,
 292     CRI_BurstSecBmpDesc2=0xE5,
 293     CRI_ImageDataPort=0xF8
 294
 295 }CtrlRegIdx;
 296
 297 /***********************
 298         Fog Mode
 299 ************************/
 300 typedef enum
 301 {
 302   FGM_Z_FOG,  /*Table*/
 303   FGM_V_FOG   /*Vertex*/
 304 } FogMode;
 305
 306 /***********************
 307   Texture
 308 ************************/
 309 typedef enum
 310 {
 311     TAM_Wrap,
 312     TAM_Clamp,
 313     TAM_Mirror
 314 } TexAddressModel;
 315
 316 typedef enum
 317 {
 318     TFT_S3TC4Bit,
 319     TFT_Pal8Bit565,
 320     TFT_Pal8Bit1555,
 321     TFT_ARGB8888,
 322     TFT_ARGB1555,
 323     TFT_ARGB4444,
 324     TFT_RGB565,
 325     TFT_Pal8Bit4444,
 326     TFT_S3TC4A4Bit,  /*like S3TC4Bit but with 4 bit alpha*/
 327     TFT_S3TC4CA4Bit, /*like S3TC4Bit, but with 4 bit compressed alpha*/
 328     TFT_S3TCL4,
 329     TFT_S3TCA4L4,
 330     TFT_L8,
 331     TFT_A4L4,
 332     TFT_I8,
 333     TFT_A8
 334 } TexFmt;
 335
 336 typedef enum
 337 {
 338     TPS_64,
 339     TPS_128,
 340     TPS_192,
 341     TPS_256
 342 } TexPaletteSize;
 343
 344     #define MAX_MIPMAP_LOD_BIAS             255
 345     #define MIN_MIPMAP_LOD_BIAS             -255
 346
 347 typedef enum
 348 {
 349   TFM_Point,              /*1 TPP*/
 350   TFM_Bilin,              /*2 TPP*/
 351   TFM_Reserved,
 352   TFM_Trilin             /*16 TPP*/
 353 } TexFilterMode;
 354
 355
 356 #define TBC_Decal       0x00850410
 357 #define TBC_Modul       0x00850011
 358 #define TBC_DecalAlpha  0x00852A04
 359 #define TBC_ModulAlpha  0x00110011
 360 #define TBC_Copy        0x00840410
 361 #define TBC_CopyAlpha   0x00900405
 362 #define TBC_NoTexMap    0x00850405
 363 #define TBC_Blend0      0x00810004
 364 #define TBC_Blend1      0x00870e02
 365 #define TBC_BlendAlpha0 0x00040004
 366 #define TBC_BlendAlpha1 TBC_Blend1
 367 #define TBC_BlendInt0   0x00040004
 368 #define TBC_BlendInt1   0x01c20e02
 369 #define TBC_AddAlpha    0x19910c11
 370
 371 #define TBC_Decal1      0x00870410
 372 #define TBC_Modul1      0x00870013
 373 #define TBC_DecalAlpha1 0x00832A00
 374 #define TBC_ModulAlpha1 0x00130013
 375 #define TBC_NoTexMap1   0x00870407
 376 #define TBC_Copy1       0x00870400
 377 #define TBC_CopyAlpha1  0x00900400
 378 #define TBC_AddAlpha1   0x19930c13
 379
 380 /*
 381  * derived from TexBlendCtrl
 382  */
 383
 384 typedef enum
 385 {
 386     TBC_UseSrc,
 387     TBC_UseTex,
 388     TBC_TexTimesSrc,
 389     TBC_BlendTexWithSrc
 390 } TexBlendCtrlMode;
 391
 392 /***********************
 393         Draw Control
 394 ************************/
 395 typedef enum
 396 {
 397     BCM_Reserved,
 398     BCM_None,
 399     BCM_CW,
 400     BCM_CCW
 401 } BackfaceCullingMode;
 402
 403 typedef enum
 404 {
 405     SAM_Zero,
 406     SAM_One,
 407     SAM_DstClr,
 408     SAM_1DstClr,
 409     SAM_SrcAlpha,
 410     SAM_1SrcAlpha,
 411     SAM_DstAlpha,
 412     SAM_1DstAlpha
 413 } SrcAlphaBlendMode;
 414
 415 /* -1 from state*/
 416 typedef enum
 417 {
 418     DAM_Zero,
 419     DAM_One,
 420     DAM_SrcClr,
 421     DAM_1SrcClr,
 422     DAM_SrcAlpha,
 423     DAM_1SrcAlpha,
 424     DAM_DstAlpha,
 425     DAM_1DstAlpha
 426 } DstAlphaBlendMode;
 427
 428 /*
 429  * stencil control
 430  */
 431
 432 typedef ZCmpFunc SCmpFunc;
 433
 434 typedef enum
 435 {
 436     STC_FAIL_Keep,
 437     STC_FAIL_Zero,
 438     STC_FAIL_Equal,
 439     STC_FAIL_IncClamp,
 440     STC_FAIL_DecClamp,
 441     STC_FAIL_Invert,
 442     STC_FAIL_Inc,
 443     STC_FAIL_Dec
 444 } StencilFailOp;
 445
 446 typedef enum
 447 {
 448     STC_ZPASS_Keep,
 449     STC_ZPASS_Zero,
 450     STC_ZPASS_Equal,
 451     STC_ZPASS_IncClamp,
 452     STC_ZPASS_DecClamp,
 453     STC_ZPASS_Invert,
 454     STC_ZPASS_Inc,
 455     STC_ZPASS_Dec
 456 } StencilZPassOp;
 457
 458 typedef enum
 459 {
 460     STC_ZFAIL_Keep,
 461     STC_ZFAIL_Zero,
 462     STC_ZFAIL_Equal,
 463     STC_ZFAIL_IncClamp,
 464     STC_ZFAIL_DecClamp,
 465     STC_ZFAIL_Invert,
 466     STC_ZFAIL_Inc,
 467     STC_ZFAIL_Dec
 468 } StencilZFailOp;
 469
 470 /***************************************************************
 471 *** Bitfield Structures for Programming Interface **************
 472 ***************************************************************/
 473
 474 /**************************
 475  Command Header Entry
 476 **************************/
 477
 478 typedef struct {  /*for DrawIndexPrimitive command, vert0Idx is meaningful.*/
 479     unsigned int vert0Idx:16;
 480     unsigned int vertCnt:8;
 481     unsigned int cont:1;
 482     unsigned int type:2;   /*00=list, 01=strip, 10=fan, 11=reserved*/
 483     unsigned int cmd:5;
 484 }Reg_DrawIndexPrimitive;
 485
 486 typedef struct {  /*for DrawIndexPrimitive command, vert0Idx is meaningful.*/
 487     unsigned int noW:1;
 488     unsigned int noCd:1;
 489     unsigned int noCs:1;
 490     unsigned int noU:1;
 491     unsigned int noV:1;
 492     unsigned int noU2:1;
 493     unsigned int noV2:1;
 494
 495     unsigned int reserved:9;
 496     unsigned int vertCnt:8;
 497     unsigned int cont:1;
 498     unsigned int type:2;   /* 00=list, 01=strip, 10=fan, 11=reserved*/
 499     unsigned int cmd:5;
 500 }Reg_DrawPrimitive;
 501
 502
 503 typedef struct {
 504     unsigned int startRegIdx:8;
 505     unsigned int reserved:8;
 506     unsigned int regCnt:8;
 507     unsigned int resvered1:1;
 508     unsigned int lowEn:1;
 509     unsigned int highEn:1;
 510     unsigned int cmd:5;
 511 }Reg_SetRegister;
 512
 513 typedef struct {
 514     unsigned int reserved1:22;
 515     unsigned int isPrimary:1;
 516     unsigned int MIU_SYNC:1;
 517     unsigned int reserved2:3;
 518     unsigned int cmd:5;
 519 }Reg_QueuedPageFlip;
 520
 521 typedef struct {
 522     unsigned int reserved1:22;
 523     unsigned int DIR:1;
 524     unsigned int CTG:1; /*set to 0*/
 525     unsigned int BPP:1;
 526     unsigned int reserved2:1;
 527     unsigned int cmd:5;
 528 }Reg_MasterImgXfer;
 529
 530 typedef struct {
 531     unsigned int PD:4;   /*PM=mono, PS=descriptor specified*/
 532     unsigned int PT:1;
 533     unsigned int SD:4;
 534     unsigned int ST:1;
 535     unsigned int DD:3;
 536     unsigned int DC:2; /*DC=destination clip*/
 537   unsigned int CS:1;  /*cs=color specified*/
 538     unsigned int MIX3:8;
 539     unsigned int XP:1;
 540     unsigned int YP:1;
 541     unsigned int LP:1;
 542     unsigned int cmd:5;
 543 }Reg_2D;
 544
 545 typedef struct {
 546     unsigned int CodedBlkPattern:6;
 547     unsigned int DCT_Type:1;
 548     unsigned int MB_Type:2;
 549     unsigned int MotionType:2;
 550     unsigned int MB_Row:6;
 551     unsigned int MB_Column:6;
 552     unsigned int mv3:1;
 553     unsigned int mv2:1;
 554     unsigned int mv1:1;
 555     unsigned int mv0:1;
 556     unsigned int cmd:5;
 557 }Reg_MacroBlock;
 558
 559 typedef struct {
 560     unsigned int scanLnCnt:11;
 561     unsigned int clkCnt:5;
 562     unsigned int e3d:1;
 563     unsigned int e2d:1;
 564     unsigned int mau:1;
 565     unsigned int veu:1;
 566     unsigned int meuMit:1;
 567     unsigned int meuSit:1;
 568     unsigned int meuVx:1;
 569     unsigned int meuMau:1;
 570     unsigned int pageFlip:1;
 571     unsigned int scanLn:1;
 572     unsigned int clk:1;
 573     unsigned int cmd:5;
 574 }Reg_Wait;
 575
 576 typedef struct{
 577     unsigned int reserved:27;
 578     unsigned int cmd:5;
 579 }Reg_ScaledImgXfer  ;
 580
 581 typedef struct{
 582     unsigned int eventTag:16;
 583     unsigned int reserved2:6;
 584     unsigned int ET:1;
 585     unsigned int INT:1;
 586     unsigned int reserved1:3;
 587     unsigned int cmd:5;
 588 }Reg_UpdtShadowStat;
 589
 590 typedef union {
 591     Reg_DrawPrimitive  vert;
 592     Reg_DrawIndexPrimitive  vertIdx;
 593     Reg_SetRegister    set;
 594     Reg_QueuedPageFlip pageFlip;
 595     Reg_MasterImgXfer  masterImgXfer;
 596     Reg_ScaledImgXfer  scaledImgXfer;
 597     Reg_UpdtShadowStat updtShadow;
 598     Reg_MacroBlock     macroBlk;
 599     Reg_2D             cmd2D;
 600     Reg_Wait           wait;
 601 }CmdHeaderUnion;
 602
 603
 604 /*frank 2001/11/14 add BCI write macros*/
 605 /* Registers not used in the X server
 606  */
 607
 608 #define SAVAGE_NOP_ID           0x2094
 609 #define SAVAGE_NOP_ID_MASK        ((1<<22)-1)
 610
 611
 612 /* 3D instructions
 613  */
 614
 615 /*          Draw Primitive Control */
 616
 617
 618 #define SAVAGE_HW_NO_Z          (1<<0)
 619 #define SAVAGE_HW_NO_W          (1<<1)
 620 #define SAVAGE_HW_NO_CD         (1<<2)
 621 #define SAVAGE_HW_NO_CS         (1<<3)
 622 #define SAVAGE_HW_NO_U0         (1<<4)
 623 #define SAVAGE_HW_NO_V0         (1<<5)
 624 #define SAVAGE_HW_NO_UV0        ((1<<4) | (1<<5))
 625 #define SAVAGE_HW_NO_U1         (1<<6)
 626 #define SAVAGE_HW_NO_V1         (1<<7)
 627 #define SAVAGE_HW_NO_UV1        ((1<<6) | (1<<7))
 628 #define SAVAGE_HW_SKIPFLAGS     0x000000ff
 629
 630 #define SAVAGE_HW_TRIANGLE_TYPE     (3UL<<25)
 631 #define SAVAGE_HW_TRIANGLE_CONT     (1UL<<24)
 632 #define SAVAGE_HW_TRIANGLE_LIST     (0<<25)
 633 #define SAVAGE_HW_TRIANGLE_STRIP    (1<<25)
 634 #define SAVAGE_HW_TRIANGLE_FAN      (2<<25)
 635 #define SAVAGE_HW_QUAD              (3<<25)
 636
 637 #define __HW_TEXTURE_CHANGED       0x00002FE
 638 #define __HW_HAS_SCISSORS_CHANGED  0x00001800
 639 #define __HW_ALL_CHANGED           0x1FFFFFF
 640 /*Frank 2001/11/14 Wait commands*/
 641 #define WAIT_3D_IDLE    0xC0010000
 642 #define WAIT_3D_2D_IDLE 0xC0030000
 643
 644 #define SET_REGISTER(index, count) \
 645     ((CMD_SetRegister << 27) | (0x6000000) | ((count) << 16) | (index))
 646
 647 /*frank 2001/11/20 */
 648 #define MAXLOOP 0xFFFFFF
 649 /*#define MAXFIFO 0x7F00*/
 650 #define MAXFIFO 0x1FF00
 651
 652 /* get eventtag from shadow status */
 653 /* here we use eventTag1 because eventTag0 is used by HWXvMC*/
 654 #define GET_EVENTTAG \
 655     (((*(volatile GLuint *)(imesa->MMIO_BASE+0x48c04)) & 0xffff0000L)>>16)
 656
 657 #define SHADOW_WAIT(imesa ) do \
 658 { \
 659     int loop=0; \
 660     imesa->shadowCounter = (imesa->shadowCounter + 1) & 0xffff;\
 661     if(imesa->shadowCounter == 0)\
 662       imesa->shadowCounter = MAX_SHADOWCOUNTER;\
 663     *(volatile GLuint *)imesa->BCIBase = imesa->shadowCounter | 0x98400000L;\
 664     while(\
 665           (GET_EVENTTAG) != imesa->shadowCounter  &&\
 666           (loop++ < MAXLOOP));\
 667 }while(0);
 668
 669 #define SHADOW_WAIT_IDLE(imesa ) do \
 670 { \
 671     int loop=0; \
 672     imesa->shadowCounter = (imesa->shadowCounter + 1) & 0xffff;\
 673     if(imesa->shadowCounter == 0)\
 674       imesa->shadowCounter = MAX_SHADOWCOUNTER;\
 675 /*    *(volatile GLuint *)imesa->BCIBase = WAIT_3D_IDLE;\*/\
 676     *(volatile GLuint *)imesa->BCIBase = imesa->shadowCounter | 0x98400000L;\
 677     while ( \
 678     (GET_EVENTTAG) != imesa->shadowCounter && \
 679     (loop++ < MAXLOOP)); \
 680 }while(0);
 681
 682 #if 0
 683 #define ALT_STATUS_WORD0 (* (volatile GLuint *)(imesa->MMIO_BASE+0x48c60))
 684
 685 #define PAGE_PENDING(result) do{\
 686 result=((ALT_STATUS_WORD0 & 0x08000000)?GL_TRUE:GL_FALSE);\
 687 }while(0)
 688
 689 #define WAIT_FOR_FIFO(count) do{\
 690 int loop = 0; \
 691 int slots = MAXFIFO-count; \
 692 while(((ALT_STATUS_WORD0 &0x001fffff)>slots)&&(loop++<MAXLOOP)); \
 693 }while(0)
 694
 695
 696 #define WAIT_IDLE_EMPTY do{\
 697 int loop = 0; \
 698  if (/*imesa->shadowStatus*/0)\
 699    {\
 700      SHADOW_WAIT_IDLE(imesa);\
 701    }\
 702  else\
 703    { \
 704      while(((ALT_STATUS_WORD0 &0x00ffffff)!=0x00E00000L)&&(loop++<MAXLOOP));\
 705    }\
 706 }while(0)
 707
 708 #define WAIT_IDLE do{\
 709 int loop = 0; \
 710 if (imesa->shadowStatus)\
 711  while((((*imesa->shadowPointer) & 0x0E000000L)!=0x0E000000L)&&(loop++<MAXLOOP));\
 712 else\
 713 while(((ALT_STATUS_WORD0 &0x00E00000)!=0x00E00000L)&&(loop++<MAXLOOP)); \
 714 }while(0)
 715 #endif /* 0 */
 716
 717 #define SAVAGE_DRAW_PRIMITIVE(count, typeandvertexSkip, isCont)  \
 718         ( ((count)<<16) | (typeandvertexSkip) | (isCont | (1<<31)));
 719
 720 static __inline volatile GLuint * SAVAGE_GET_BCI_POINTER(savageContextPtr imesa, GLuint count)
 721 {
 722   WAIT_FOR_FIFO(count);
 723   return (volatile GLuint *)(imesa->BCIBase);
 724 }
 725
 726 /*use this set bci cmd now!*/
 727 #define WRITE_CMD(buf,cmd,type) do {\
 728     *((type*)buf)=cmd;\
 729     buf++;\
 730   }while(0)
 731 #endif
 732
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 737