src/mesa/drivers/dri/unichrome/server/via_dri.c

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via_dri.c,v 1.4 2003/09/24 02:43:30 dawes Exp $ */
   2 /*
   3  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   4  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25 #if 0
  26 #include "xf86.h"
  27 #include "xf86_OSproc.h"
  28 #include "xf86_ansic.h"
  29 #include "xf86Priv.h"
  30
  31 #include "xf86PciInfo.h"
  32 #include "xf86Pci.h"
  33
  34 #define _XF86DRI_SERVER_
  35 #include "GL/glxtokens.h"
  36
  37 #else
  38
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <errno.h>
  43 #include <unistd.h>
  44
  45 #include "driver.h"
  46 #include "drm.h"
  47 #include "imports.h"
  48 #endif
  49
  50 #include "dri_util.h"
  51
  52 #include "via_context.h"
  53 #include "via_dri.h"
  54 #include "via_driver.h"
  55 #include "via_common.h"
  56 #include "xf86drm.h"
  57
  58 static void VIAEnableMMIO(DRIDriverContext * ctx);
  59 static void VIADisableMMIO(DRIDriverContext * ctx);
  60 static void VIADisableExtendedFIFO(DRIDriverContext *ctx);
  61 static void VIAEnableExtendedFIFO(DRIDriverContext *ctx);
  62 static void VIAInitialize2DEngine(DRIDriverContext *ctx);
  63 static void VIAInitialize3DEngine(DRIDriverContext *ctx);
  64
  65 static int VIADRIScreenInit(DRIDriverContext * ctx);
  66 static void VIADRICloseScreen(DRIDriverContext * ctx);
  67 static int VIADRIFinishScreenInit(DRIDriverContext * ctx);
  68
  69 /* _SOLO : missing macros normally defined by X code */
  70 #define xf86DrvMsg(a, b, ...) fprintf(stderr, __VA_ARGS__)
  71 #define MMIO_IN8(base, addr) ((*(((volatile uint8_t*)base)+(addr)))+0)
  72 #define MMIO_OUT8(base, addr, val) ((*(((volatile uint8_t*)base)+(addr)))=((uint8_t)val))
  73 #define MMIO_OUT16(base, addr, val) ((*(volatile uint16_t*)(((uint8_t*)base)+(addr)))=((uint16_t)val))
  74
  75 #define VIDEO   0
  76 #define AGP             1
  77 #define AGP_PAGE_SIZE 4096
  78 #define AGP_PAGES 8192
  79 #define AGP_SIZE (AGP_PAGE_SIZE * AGP_PAGES)
  80 #define AGP_CMDBUF_PAGES 256
  81 #define AGP_CMDBUF_SIZE (AGP_PAGE_SIZE * AGP_CMDBUF_PAGES)
  82
  83 static char VIAKernelDriverName[] = "via";
  84 static char VIAClientDriverName[] = "via";
  85
  86 static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia);
  87 static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia);
  88 static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia);
  89 static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia);
  90 static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia);
  91
  92 static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia)
  93 {
  94     unsigned long  agp_phys;
  95     unsigned int agpaddr;
  96     VIADRIPtr pVIADRI;
  97     pVIADRI = pVia->devPrivate;
  98     pVia->agpSize = 0;
  99
 100     if (drmAgpAcquire(pVia->drmFD) < 0) {
 101         xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpAcquire failed %d\n", errno);
 102         return GL_FALSE;
 103     }
 104
 105     if (drmAgpEnable(pVia->drmFD, drmAgpGetMode(pVia->drmFD)&~0x0) < 0) {
 106          xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpEnable failed\n");
 107         return GL_FALSE;
 108     }
 109
 110     xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] drmAgpEnabled succeeded\n");
 111
 112     if (drmAgpAlloc(pVia->drmFD, AGP_SIZE, 0, &agp_phys, &pVia->agpHandle) < 0) {
 113         xf86DrvMsg(pScreen->myNum, X_ERROR,
 114                  "[drm] drmAgpAlloc failed\n");
 115         drmAgpRelease(pVia->drmFD);
 116         return GL_FALSE;
 117     }
 118
 119     if (drmAgpBind(pVia->drmFD, pVia->agpHandle, 0) < 0) {
 120         xf86DrvMsg(pScreen->myNum, X_ERROR,
 121                  "[drm] drmAgpBind failed\n");
 122         drmAgpFree(pVia->drmFD, pVia->agpHandle);
 123         drmAgpRelease(pVia->drmFD);
 124
 125         return GL_FALSE;
 126     }
 127
 128     pVia->agpSize = AGP_SIZE;
 129     pVia->agpAddr = drmAgpBase(pVia->drmFD);
 130     xf86DrvMsg(pScreen->myNum, X_INFO,
 131                  "[drm] agpAddr = 0x%08lx\n",pVia->agpAddr);
 132
 133     pVIADRI->agp.size = pVia->agpSize;
 134     if (drmAddMap(pVia->drmFD, (drm_handle_t)0,
 135                  pVIADRI->agp.size, DRM_AGP, 0,
 136                  &pVIADRI->agp.handle) < 0) {
 137         xf86DrvMsg(pScreen->myNum, X_ERROR,
 138             "[drm] Failed to map public agp area\n");
 139         pVIADRI->agp.size = 0;
 140         return GL_FALSE;
 141     }
 142     /* Map AGP from kernel to Xserver - Not really needed */
 143     drmMap(pVia->drmFD, pVIADRI->agp.handle,pVIADRI->agp.size,
 144         (drmAddressPtr)&agpaddr);
 145
 146 #if 0
 147     xf86DrvMsg(pScreen->myNum, X_INFO,
 148                 "[drm] agpBase = 0x%08lx\n", pVia->agpBase);
 149     xf86DrvMsg(pScreen->myNum, X_INFO,
 150                 "[drm] agpAddr = 0x%08lx\n", pVia->agpAddr);
 151 #endif
 152     xf86DrvMsg(pScreen->myNum, X_INFO,
 153                 "[drm] agpSize = 0x%08lx\n", pVia->agpSize);
 154     xf86DrvMsg(pScreen->myNum, X_INFO,
 155                 "[drm] agp physical addr = 0x%08lx\n", agp_phys);
 156
 157     drmVIAAgpInit(pVia->drmFD, 0, AGP_SIZE);
 158     return GL_TRUE;
 159
 160 }
 161
 162 static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia)
 163 {
 164     int FBSize = pVia->FBFreeEnd-pVia->FBFreeStart;
 165     int FBOffset = pVia->FBFreeStart;
 166     VIADRIPtr pVIADRI = pVia->devPrivate;
 167     pVIADRI->fbOffset = FBOffset;
 168     pVIADRI->fbSize = pVia->videoRambytes;
 169
 170     if (drmVIAFBInit(pVia->drmFD, FBOffset, FBSize) < 0) {
 171         xf86DrvMsg(pScreen->myNum, X_ERROR,"[drm] failed to init frame buffer area\n");
 172         return GL_FALSE;
 173     }
 174     else {
 175         xf86DrvMsg(pScreen->myNum, X_INFO,"[drm] FBFreeStart= 0x%08lx FBFreeEnd= 0x%08lx FBSize= 0x%08lx\n", pVia->FBFreeStart, pVia->FBFreeEnd, FBSize);
 176         return GL_TRUE;
 177     }
 178 }
 179
 180 static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia)
 181 {
 182     return GL_TRUE;
 183 }
 184
 185 static int VIADRIScreenInit(DRIDriverContext * ctx)
 186 {
 187     VIAPtr pVia = VIAPTR(ctx);
 188     VIADRIPtr pVIADRI;
 189     int err;
 190
 191 #if 0
 192     ctx->shared.SAREASize = ((sizeof(drm_sarea_t) + 0xfff) & 0x1000);
 193 #else
 194     if (sizeof(drm_sarea_t)+sizeof(VIASAREAPriv) > SAREA_MAX) {
 195         xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 196                         "Data does not fit in SAREA\n");
 197         return GL_FALSE;
 198     }
 199     ctx->shared.SAREASize = SAREA_MAX;
 200 #endif
 201
 202     ctx->drmFD = drmOpen(VIAKernelDriverName, NULL);
 203     if (ctx->drmFD < 0) {
 204         fprintf(stderr, "[drm] drmOpen failed\n");
 205         return 0;
 206     }
 207     pVia->drmFD = ctx->drmFD;
 208
 209     err = drmSetBusid(ctx->drmFD, ctx->pciBusID);
 210     if (err < 0) {
 211         fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
 212                 ctx->drmFD, ctx->pciBusID, strerror(-err));
 213         return 0;
 214     }
 215
 216     err = drmAddMap(ctx->drmFD, 0, ctx->shared.SAREASize, DRM_SHM,
 217                   DRM_CONTAINS_LOCK, &ctx->shared.hSAREA);
 218     if (err < 0) {
 219         fprintf(stderr, "[drm] drmAddMap failed\n");
 220         return 0;
 221     }
 222     fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
 223             ctx->shared.SAREASize, ctx->shared.hSAREA);
 224
 225     if (drmMap(ctx->drmFD,
 226                ctx->shared.hSAREA,
 227                ctx->shared.SAREASize,
 228                (drmAddressPtr)(&ctx->pSAREA)) < 0)
 229     {
 230         fprintf(stderr, "[drm] drmMap failed\n");
 231         return 0;
 232     }
 233     memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
 234     fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
 235             ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
 236
 237     /* Need to AddMap the framebuffer and mmio regions here:
 238      */
 239     if (drmAddMap(ctx->drmFD,
 240                   (drm_handle_t)ctx->FBStart,
 241                   ctx->FBSize,
 242                   DRM_FRAME_BUFFER,
 243 #ifndef _EMBEDDED
 244                    0,
 245 #else
 246                    DRM_READ_ONLY,
 247 #endif
 248                    &ctx->shared.hFrameBuffer) < 0)
 249     {
 250         fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
 251         return 0;
 252     }
 253
 254     fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
 255             ctx->shared.hFrameBuffer);
 256
 257     pVIADRI = (VIADRIPtr) CALLOC(sizeof(VIADRIRec));
 258     if (!pVIADRI) {
 259         drmClose(ctx->drmFD);
 260         return GL_FALSE;
 261     }
 262     pVia->devPrivate = pVIADRI;
 263     ctx->driverClientMsg = pVIADRI;
 264     ctx->driverClientMsgSize = sizeof(*pVIADRI);
 265
 266     pVia->IsPCI = !VIADRIAgpInit(ctx, pVia);
 267
 268     if (pVia->IsPCI) {
 269         VIADRIPciInit(ctx, pVia);
 270         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use pci.\n" );
 271     }
 272     else
 273         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use agp.\n" );
 274
 275     if (!(VIADRIFBInit(ctx, pVia))) {
 276         VIADRICloseScreen(ctx);
 277         xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] frame buffer initialize fial .\n" );
 278         return GL_FALSE;
 279     }
 280
 281     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] frame buffer initialized.\n" );
 282
 283     /* DRIScreenInit doesn't add all the common mappings.  Add additional mappings here. */
 284     if (!VIADRIMapInit(ctx, pVia)) {
 285         VIADRICloseScreen(ctx);
 286         return GL_FALSE;
 287     }
 288     pVIADRI->regs.size = VIA_MMIO_REGSIZE;
 289     pVIADRI->regs.map = 0;
 290     pVIADRI->regs.handle = pVia->registerHandle;
 291     xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] mmio Registers = 0x%08lx\n",
 292         pVIADRI->regs.handle);
 293
 294     /*pVIADRI->drixinerama = pVia->drixinerama;*/
 295     /*=* John Sheng [2003.12.9] Tuxracer & VQ *=*/
 296     pVIADRI->VQEnable = pVia->VQEnable;
 297
 298     if (drmMap(pVia->drmFD,
 299                pVIADRI->regs.handle,
 300                pVIADRI->regs.size,
 301                (drmAddress *)&pVia->MapBase) != 0)
 302     {
 303         VIADRICloseScreen(ctx);
 304         return GL_FALSE;
 305     }
 306
 307     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] mmio mapped.\n" );
 308
 309     return VIADRIFinishScreenInit(ctx);
 310 }
 311
 312 static void
 313 VIADRICloseScreen(DRIDriverContext * ctx)
 314 {
 315     VIAPtr pVia = VIAPTR(ctx);
 316     VIADRIPtr pVIADRI=(VIADRIPtr)pVia->devPrivate;
 317
 318     if (pVia->MapBase) {
 319         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Unmapping MMIO registers\n");
 320         drmUnmap(pVia->MapBase, pVIADRI->regs.size);
 321     }
 322
 323     if (pVia->agpSize) {
 324         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Freeing agp memory\n");
 325         drmAgpFree(pVia->drmFD, pVia->agpHandle);
 326         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Releasing agp module\n");
 327         drmAgpRelease(pVia->drmFD);
 328     }
 329 }
 330
 331 static int
 332 VIADRIFinishScreenInit(DRIDriverContext * ctx)
 333 {
 334     VIAPtr pVia = VIAPTR(ctx);
 335     VIADRIPtr pVIADRI;
 336     int err;
 337
 338     err = drmCreateContext(ctx->drmFD, &ctx->serverContext);
 339     if (err != 0) {
 340         fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
 341         return GL_FALSE;
 342     }
 343
 344     DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);
 345
 346
 347     if (!VIADRIKernelInit(ctx, pVia)) {
 348         VIADRICloseScreen(ctx);
 349         return GL_FALSE;
 350     }
 351     xf86DrvMsg(pScreen->myNum, X_INFO, "[dri] kernel data initialized.\n");
 352
 353     /* set SAREA value */
 354     {
 355         VIASAREAPriv *saPriv;
 356
 357         saPriv=(VIASAREAPriv*)(((char*)ctx->pSAREA) +
 358                                sizeof(drm_sarea_t));
 359         assert(saPriv);
 360         memset(saPriv, 0, sizeof(*saPriv));
 361         saPriv->CtxOwner = -1;
 362     }
 363     pVIADRI=(VIADRIPtr)pVia->devPrivate;
 364     pVIADRI->deviceID=pVia->Chipset;
 365     pVIADRI->width=ctx->shared.virtualWidth;
 366     pVIADRI->height=ctx->shared.virtualHeight;
 367     pVIADRI->mem=ctx->shared.fbSize;
 368     pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8;
 369     pVIADRI->sarea_priv_offset = sizeof(drm_sarea_t);
 370     /* TODO */
 371     pVIADRI->scrnX=pVIADRI->width;
 372     pVIADRI->scrnY=pVIADRI->height;
 373
 374     return GL_TRUE;
 375 }
 376
 377 /* Initialize the kernel data structures. */
 378 static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia)
 379 {
 380     drmVIAInit drmInfo;
 381     memset(&drmInfo, 0, sizeof(drmVIAInit));
 382     drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
 383     drmInfo.fb_offset           = pVia->FrameBufferBase;
 384     drmInfo.mmio_offset         = pVia->registerHandle;
 385     if (pVia->IsPCI)
 386         drmInfo.agpAddr = (uint32_t)NULL;
 387     else
 388         drmInfo.agpAddr = (uint32_t)pVia->agpAddr;
 389
 390     if (drmVIAInitMAP(pVia->drmFD, &drmInfo) < 0) return GL_FALSE;
 391
 392     return GL_TRUE;
 393 }
 394 /* Add a map for the MMIO registers */
 395 static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia)
 396 {
 397     int flags = 0;
 398
 399     if (drmAddMap(pVia->drmFD, pVia->MmioBase, VIA_MMIO_REGSIZE,
 400                   DRM_REGISTERS, flags, &pVia->registerHandle) < 0) {
 401         return GL_FALSE;
 402     }
 403
 404     xf86DrvMsg(pScreen->myNum, X_INFO,
 405         "[drm] register handle = 0x%08lx\n", pVia->registerHandle);
 406
 407     return GL_TRUE;
 408 }
 409
 410 const __GLcontextModes __glModes[] =
 411 {
 412     /* 32 bit, RGBA Depth=16 Stencil=8 */
 413     {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
 414      .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_TRUE,
 415      .redBits = 8, .greenBits = 8, .blueBits = 8, .alphaBits = 8,
 416      .redMask = 0xff0000, .greenMask = 0xff00, .blueMask = 0xff, .alphaMask = 0xff000000,
 417      .rgbBits = 32, .indexBits = 0,
 418      .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
 419      .depthBits = 16, .stencilBits = 8,
 420      .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_TRUE, },
 421
 422 #if 0
 423     /* 16 bit, RGB Depth=16 */
 424     {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
 425      .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_FALSE,
 426      .redBits = 5, .greenBits = 6, .blueBits = 5, .alphaBits = 0,
 427      .redMask = 0xf800, .greenMask = 0x07e0, .blueMask = 0x001f, .alphaMask = 0x0,
 428      .rgbBits = 16, .indexBits = 0,
 429      .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
 430      .depthBits = 16, .stencilBits = 0,
 431      .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_TRUE, },
 432 #endif
 433 };
 434
 435 static int viaInitContextModes(const DRIDriverContext *ctx,
 436                                   int *numModes, const __GLcontextModes **modes)
 437 {
 438     *numModes = sizeof(__glModes)/sizeof(__glModes[0]);
 439     *modes = &__glModes[0];
 440     return 1;
 441 }
 442
 443 static int viaValidateMode(const DRIDriverContext *ctx)
 444 {
 445     VIAPtr pVia = VIAPTR(ctx);
 446
 447     return 1;
 448 }
 449
 450 static int viaPostValidateMode(const DRIDriverContext *ctx)
 451 {
 452     VIAPtr pVia = VIAPTR(ctx);
 453
 454     return 1;
 455 }
 456
 457 static void VIAEnableMMIO(DRIDriverContext * ctx)
 458 {
 459     /*vgaHWPtr hwp = VGAHWPTR(ctx);*/
 460     VIAPtr pVia = VIAPTR(ctx);
 461     unsigned char val;
 462
 463 #if 0
 464     if (xf86IsPrimaryPci(pVia->PciInfo)) {
 465         /* If we are primary card, we still use std vga port. If we use
 466          * MMIO, system will hang in vgaHWSave when our card used in
 467          * PLE and KLE (integrated Trident MVP4)
 468          */
 469         vgaHWSetStdFuncs(hwp);
 470     }
 471     else {
 472         vgaHWSetMmioFuncs(hwp, pVia->MapBase, 0x8000);
 473     }
 474 #endif
 475
 476     val = VGAIN8(0x3c3);
 477     VGAOUT8(0x3c3, val | 0x01);
 478     val = VGAIN8(0x3cc);
 479     VGAOUT8(0x3c2, val | 0x01);
 480
 481     /* Unlock Extended IO Space */
 482     VGAOUT8(0x3c4, 0x10);
 483     VGAOUT8(0x3c5, 0x01);
 484
 485     /* Enable MMIO */
 486     if(!pVia->IsSecondary) {
 487         VGAOUT8(0x3c4, 0x1a);
 488         val = VGAIN8(0x3c5);
 489 #ifdef DEBUG
 490         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "primary val = %x\n", val);
 491 #endif
 492         VGAOUT8(0x3c5, val | 0x68);
 493     }
 494     else {
 495         VGAOUT8(0x3c4, 0x1a);
 496         val = VGAIN8(0x3c5);
 497 #ifdef DEBUG
 498         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "secondary val = %x\n", val);
 499 #endif
 500         VGAOUT8(0x3c5, val | 0x38);
 501     }
 502
 503     /* Unlock CRTC registers */
 504     VGAOUT8(0x3d4, 0x47);
 505     VGAOUT8(0x3d5, 0x00);
 506
 507     return;
 508 }
 509
 510 static void VIADisableMMIO(DRIDriverContext * ctx)
 511 {
 512     VIAPtr pVia = VIAPTR(ctx);
 513     unsigned char val;
 514
 515     VGAOUT8(0x3c4, 0x1a);
 516     val = VGAIN8(0x3c5);
 517     VGAOUT8(0x3c5, val & 0x97);
 518
 519     return;
 520 }
 521
 522 static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
 523 {
 524     VIAPtr  pVia = VIAPTR(ctx);
 525     uint32_t  dwGE230, dwGE298;
 526
 527     /* Cause of exit XWindow will dump back register value, others chipset no
 528      * need to set extended fifo value */
 529     if (pVia->Chipset == VIA_CLE266 && pVia->ChipRev < 15 &&
 530         (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary)) {
 531         /* Turn off Extend FIFO */
 532         /* 0x298[29] */
 533         dwGE298 = VIAGETREG(0x298);
 534         VIASETREG(0x298, dwGE298 | 0x20000000);
 535         /* 0x230[21] */
 536         dwGE230 = VIAGETREG(0x230);
 537         VIASETREG(0x230, dwGE230 & ~0x00200000);
 538         /* 0x298[29] */
 539         dwGE298 = VIAGETREG(0x298);
 540         VIASETREG(0x298, dwGE298 & ~0x20000000);
 541     }
 542 }
 543
 544 static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
 545 {
 546     VIAPtr  pVia = VIAPTR(ctx);
 547     uint8_t   bRegTemp;
 548     uint32_t  dwGE230, dwGE298;
 549
 550     switch (pVia->Chipset) {
 551     case VIA_CLE266:
 552         if (pVia->ChipRev > 14) {  /* For 3123Cx */
 553             if (pVia->HasSecondary) {  /* SAMM or DuoView case */
 554                 if (ctx->shared.virtualWidth >= 1024)
 555                 {
 556                     /* 3c5.16[0:5] */
 557                         VGAOUT8(0x3C4, 0x16);
 558                     bRegTemp = VGAIN8(0x3C5);
 559                     bRegTemp &= ~0x3F;
 560                         bRegTemp |= 0x1C;
 561                     VGAOUT8(0x3C5, bRegTemp);
 562                         /* 3c5.17[0:6] */
 563                     VGAOUT8(0x3C4, 0x17);
 564                         bRegTemp = VGAIN8(0x3C5);
 565                     bRegTemp &= ~0x7F;
 566                         bRegTemp |= 0x3F;
 567                     VGAOUT8(0x3C5, bRegTemp);
 568                     pVia->EnableExtendedFIFO = GL_TRUE;
 569                 }
 570             }
 571             else   /* Single view or Simultaneoue case */
 572             {
 573                 if (ctx->shared.virtualWidth > 1024)
 574                 {
 575                     /* 3c5.16[0:5] */
 576                         VGAOUT8(0x3C4, 0x16);
 577                     bRegTemp = VGAIN8(0x3C5);
 578                     bRegTemp &= ~0x3F;
 579                         bRegTemp |= 0x17;
 580                     VGAOUT8(0x3C5, bRegTemp);
 581                         /* 3c5.17[0:6] */
 582                     VGAOUT8(0x3C4, 0x17);
 583                         bRegTemp = VGAIN8(0x3C5);
 584                     bRegTemp &= ~0x7F;
 585                         bRegTemp |= 0x2F;
 586                     VGAOUT8(0x3C5, bRegTemp);
 587                     pVia->EnableExtendedFIFO = GL_TRUE;
 588                 }
 589             }
 590             /* 3c5.18[0:5] */
 591             VGAOUT8(0x3C4, 0x18);
 592             bRegTemp = VGAIN8(0x3C5);
 593             bRegTemp &= ~0x3F;
 594             bRegTemp |= 0x17;
 595             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 596             VGAOUT8(0x3C5, bRegTemp);
 597         }
 598         else {      /* for 3123Ax */
 599             if (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary) {
 600                 /* Turn on Extend FIFO */
 601                 /* 0x298[29] */
 602                 dwGE298 = VIAGETREG(0x298);
 603                 VIASETREG(0x298, dwGE298 | 0x20000000);
 604                 /* 0x230[21] */
 605                 dwGE230 = VIAGETREG(0x230);
 606                 VIASETREG(0x230, dwGE230 | 0x00200000);
 607                 /* 0x298[29] */
 608                 dwGE298 = VIAGETREG(0x298);
 609                 VIASETREG(0x298, dwGE298 & ~0x20000000);
 610
 611                 /* 3c5.16[0:5] */
 612                 VGAOUT8(0x3C4, 0x16);
 613                 bRegTemp = VGAIN8(0x3C5);
 614                 bRegTemp &= ~0x3F;
 615                 bRegTemp |= 0x17;
 616                 /* bRegTemp |= 0x10; */
 617                 VGAOUT8(0x3C5, bRegTemp);
 618                 /* 3c5.17[0:6] */
 619                 VGAOUT8(0x3C4, 0x17);
 620                 bRegTemp = VGAIN8(0x3C5);
 621                 bRegTemp &= ~0x7F;
 622                 bRegTemp |= 0x2F;
 623                 /*bRegTemp |= 0x1F;*/
 624                 VGAOUT8(0x3C5, bRegTemp);
 625                 /* 3c5.18[0:5] */
 626                 VGAOUT8(0x3C4, 0x18);
 627                 bRegTemp = VGAIN8(0x3C5);
 628                 bRegTemp &= ~0x3F;
 629                 bRegTemp |= 0x17;
 630                 bRegTemp |= 0x40;  /* force the preq always higher than treq */
 631                 VGAOUT8(0x3C5, bRegTemp);
 632                     pVia->EnableExtendedFIFO = GL_TRUE;
 633             }
 634         }
 635         break;
 636     case VIA_KM400:
 637         if (pVia->HasSecondary) {  /* SAMM or DuoView case */
 638             if ((ctx->shared.virtualWidth >= 1600) &&
 639                 (pVia->MemClk <= VIA_MEM_DDR200)) {
 640                     /* enable CRT extendded FIFO */
 641                 VGAOUT8(0x3C4, 0x17);
 642                 VGAOUT8(0x3C5, 0x1C);
 643                 /* revise second display queue depth and read threshold */
 644                     VGAOUT8(0x3C4, 0x16);
 645                 bRegTemp = VGAIN8(0x3C5);
 646                 bRegTemp &= ~0x3F;
 647                 bRegTemp = (bRegTemp) | (0x09);
 648                 VGAOUT8(0x3C5, bRegTemp);
 649             }
 650             else {
 651                 /* enable CRT extendded FIFO */
 652                 VGAOUT8(0x3C4, 0x17);
 653                 VGAOUT8(0x3C5,0x3F);
 654                 /* revise second display queue depth and read threshold */
 655                 VGAOUT8(0x3C4, 0x16);
 656                 bRegTemp = VGAIN8(0x3C5);
 657                 bRegTemp &= ~0x3F;
 658                 bRegTemp = (bRegTemp) | (0x1C);
 659                 VGAOUT8(0x3C5, bRegTemp);
 660             }
 661             /* 3c5.18[0:5] */
 662             VGAOUT8(0x3C4, 0x18);
 663             bRegTemp = VGAIN8(0x3C5);
 664             bRegTemp &= ~0x3F;
 665             bRegTemp |= 0x17;
 666             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 667             VGAOUT8(0x3C5, bRegTemp);
 668             pVia->EnableExtendedFIFO = GL_TRUE;
 669         }
 670         else {
 671             if ( (ctx->shared.virtualWidth > 1024) && (ctx->shared.virtualWidth <= 1280) )
 672             {
 673                 /* enable CRT extendded FIFO */
 674                 VGAOUT8(0x3C4, 0x17);
 675                 VGAOUT8(0x3C5, 0x3F);
 676                 /* revise second display queue depth and read threshold */
 677                 VGAOUT8(0x3C4, 0x16);
 678                 bRegTemp = VGAIN8(0x3C5);
 679                 bRegTemp &= ~0x3F;
 680                 bRegTemp = (bRegTemp) | (0x17);
 681                 VGAOUT8(0x3C5, bRegTemp);
 682                     pVia->EnableExtendedFIFO = GL_TRUE;
 683             }
 684             else if ((ctx->shared.virtualWidth > 1280))
 685             {
 686                 /* enable CRT extendded FIFO */
 687                 VGAOUT8(0x3C4, 0x17);
 688                 VGAOUT8(0x3C5, 0x3F);
 689                 /* revise second display queue depth and read threshold */
 690                 VGAOUT8(0x3C4, 0x16);
 691                 bRegTemp = VGAIN8(0x3C5);
 692                 bRegTemp &= ~0x3F;
 693                 bRegTemp = (bRegTemp) | (0x1C);
 694                 VGAOUT8(0x3C5, bRegTemp);
 695                     pVia->EnableExtendedFIFO = GL_TRUE;
 696             }
 697             else
 698             {
 699                 /* enable CRT extendded FIFO */
 700                 VGAOUT8(0x3C4, 0x17);
 701                 VGAOUT8(0x3C5, 0x3F);
 702                 /* revise second display queue depth and read threshold */
 703                 VGAOUT8(0x3C4, 0x16);
 704                 bRegTemp = VGAIN8(0x3C5);
 705                 bRegTemp &= ~0x3F;
 706                 bRegTemp = (bRegTemp) | (0x10);
 707                 VGAOUT8(0x3C5, bRegTemp);
 708             }
 709             /* 3c5.18[0:5] */
 710             VGAOUT8(0x3C4, 0x18);
 711             bRegTemp = VGAIN8(0x3C5);
 712             bRegTemp &= ~0x3F;
 713             bRegTemp |= 0x17;
 714             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 715             VGAOUT8(0x3C5, bRegTemp);
 716         }
 717         break;
 718     case VIA_K8M800:
 719         /*=* R1 Display FIFO depth (384 /8 -1 -> 0xbf) SR17[7:0] (8bits) *=*/
 720         VGAOUT8(0x3c4, 0x17);
 721         VGAOUT8(0x3c5, 0xbf);
 722
 723         /*=* R2 Display fetch datum threshold value (328/4 -> 0x52)
 724              SR16[5:0], SR16[7] (7bits) *=*/
 725         VGAOUT8(0x3c4, 0x16);
 726         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 727         bRegTemp |= (0x52 & 0x3F);
 728         bRegTemp |= ((0x52 & 0x40) << 1);
 729         VGAOUT8(0x3c5, bRegTemp);
 730
 731         /*=* R3 Switch to the highest agent threshold value (74 -> 0x4a)
 732              SR18[5:0], SR18[7] (7bits) *=*/
 733         VGAOUT8(0x3c4, 0x18);
 734         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 735         bRegTemp |= (0x4a & 0x3F);
 736         bRegTemp |= ((0x4a & 0x40) << 1);
 737         VGAOUT8(0x3c5, bRegTemp);
 738 #if 0
 739         /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
 740              SR1C[7:0], SR1D[1:0] (10bits) *=*/
 741         wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
 742         VGAOUT8(0x3c4, 0x1c);
 743         VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
 744         VGAOUT8(0x3c4, 0x1d);
 745         bRegTemp = VGAIN8(0x3c5) & ~0x03;
 746         VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
 747 #endif
 748         if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
 749         {
 750             /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
 751             VGAOUT8(0x3c4, 0x22);
 752             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 753             VGAOUT8(0x3c5, bRegTemp | 0x10);
 754         }
 755         else
 756         {
 757             /*=* Max. length for a request SR22[4:0]
 758                  (128/4 -> over flow 0x0) *=*/
 759             VGAOUT8(0x3c4, 0x22);
 760             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 761             VGAOUT8(0x3c5, bRegTemp);
 762         }
 763         break;
 764     case VIA_PM800:
 765         /*=* R1 Display FIFO depth (96-1 -> 0x5f) SR17[7:0] (8bits) *=*/
 766         VGAOUT8(0x3c4, 0x17);
 767         VGAOUT8(0x3c5, 0x5f);
 768
 769         /*=* R2 Display fetch datum threshold value (32 -> 0x20)
 770              SR16[5:0], SR16[7] (7bits) *=*/
 771         VGAOUT8(0x3c4, 0x16);
 772         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 773         bRegTemp |= (0x20 & 0x3F);
 774         bRegTemp |= ((0x20 & 0x40) << 1);
 775         VGAOUT8(0x3c5, bRegTemp);
 776
 777         /*=* R3 Switch to the highest agent threshold value (16 -> 0x10)
 778              SR18[5:0], SR18[7] (7bits) *=*/
 779         VGAOUT8(0x3c4, 0x18);
 780         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 781         bRegTemp |= (0x10 & 0x3F);
 782         bRegTemp |= ((0x10 & 0x40) << 1);
 783         VGAOUT8(0x3c5, bRegTemp);
 784 #if 0
 785         /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
 786              SR1C[7:0], SR1D[1:0] (10bits) *=*/
 787         wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
 788         VGAOUT8(0x3c4, 0x1c);
 789         VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
 790         VGAOUT8(0x3c4, 0x1d);
 791         bRegTemp = VGAIN8(0x3c5) & ~0x03;
 792         VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
 793 #endif
 794         if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
 795         {
 796             /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
 797             VGAOUT8(0x3c4, 0x22);
 798             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 799             VGAOUT8(0x3c5, bRegTemp | 0x10);
 800         }
 801         else
 802         {
 803             /*=* Max. length for a request SR22[4:0] (0x1F) *=*/
 804             VGAOUT8(0x3c4, 0x22);
 805             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 806             VGAOUT8(0x3c5, bRegTemp | 0x1F);
 807         }
 808         break;
 809     default:
 810         break;
 811     }
 812 }
 813
 814 static void VIAInitialize2DEngine(DRIDriverContext *ctx)
 815 {
 816     VIAPtr  pVia = VIAPTR(ctx);
 817     uint32_t  dwVQStartAddr, dwVQEndAddr;
 818     uint32_t  dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
 819     uint32_t  dwGEMode;
 820
 821     /* init 2D engine regs to reset 2D engine */
 822     VIASETREG(0x04, 0x0);
 823     VIASETREG(0x08, 0x0);
 824     VIASETREG(0x0c, 0x0);
 825     VIASETREG(0x10, 0x0);
 826     VIASETREG(0x14, 0x0);
 827     VIASETREG(0x18, 0x0);
 828     VIASETREG(0x1c, 0x0);
 829     VIASETREG(0x20, 0x0);
 830     VIASETREG(0x24, 0x0);
 831     VIASETREG(0x28, 0x0);
 832     VIASETREG(0x2c, 0x0);
 833     VIASETREG(0x30, 0x0);
 834     VIASETREG(0x34, 0x0);
 835     VIASETREG(0x38, 0x0);
 836     VIASETREG(0x3c, 0x0);
 837     VIASETREG(0x40, 0x0);
 838
 839     VIADisableMMIO(ctx);
 840
 841     /* Init AGP and VQ regs */
 842     VIASETREG(0x43c, 0x00100000);
 843     VIASETREG(0x440, 0x00000000);
 844     VIASETREG(0x440, 0x00333004);
 845     VIASETREG(0x440, 0x60000000);
 846     VIASETREG(0x440, 0x61000000);
 847     VIASETREG(0x440, 0x62000000);
 848     VIASETREG(0x440, 0x63000000);
 849     VIASETREG(0x440, 0x64000000);
 850     VIASETREG(0x440, 0x7D000000);
 851
 852     VIASETREG(0x43c, 0xfe020000);
 853     VIASETREG(0x440, 0x00000000);
 854
 855     if (pVia->VQStart != 0) {
 856         /* Enable VQ */
 857         dwVQStartAddr = pVia->VQStart;
 858         dwVQEndAddr = pVia->VQEnd;
 859         dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
 860         dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
 861         dwVQStartEndH = 0x52000000 | ((dwVQStartAddr & 0xFF000000) >> 24) |
 862                         ((dwVQEndAddr & 0xFF000000) >> 16);
 863         dwVQLen = 0x53000000 | (VIA_VQ_SIZE >> 3);
 864
 865         VIASETREG(0x43c, 0x00fe0000);
 866         VIASETREG(0x440, 0x080003fe);
 867         VIASETREG(0x440, 0x0a00027c);
 868         VIASETREG(0x440, 0x0b000260);
 869         VIASETREG(0x440, 0x0c000274);
 870         VIASETREG(0x440, 0x0d000264);
 871         VIASETREG(0x440, 0x0e000000);
 872         VIASETREG(0x440, 0x0f000020);
 873         VIASETREG(0x440, 0x1000027e);
 874         VIASETREG(0x440, 0x110002fe);
 875         VIASETREG(0x440, 0x200f0060);
 876
 877         VIASETREG(0x440, 0x00000006);
 878         VIASETREG(0x440, 0x40008c0f);
 879         VIASETREG(0x440, 0x44000000);
 880         VIASETREG(0x440, 0x45080c04);
 881         VIASETREG(0x440, 0x46800408);
 882
 883         VIASETREG(0x440, dwVQStartEndH);
 884         VIASETREG(0x440, dwVQStartL);
 885         VIASETREG(0x440, dwVQEndL);
 886         VIASETREG(0x440, dwVQLen);
 887     }
 888     else {
 889         /* Diable VQ */
 890         VIASETREG(0x43c, 0x00fe0000);
 891         VIASETREG(0x440, 0x00000004);
 892         VIASETREG(0x440, 0x40008c0f);
 893         VIASETREG(0x440, 0x44000000);
 894         VIASETREG(0x440, 0x45080c04);
 895         VIASETREG(0x440, 0x46800408);
 896     }
 897
 898     dwGEMode = 0;
 899
 900     switch (ctx->bpp) {
 901     case 16:
 902         dwGEMode |= VIA_GEM_16bpp;
 903         break;
 904     case 32:
 905         dwGEMode |= VIA_GEM_32bpp;
 906     default:
 907         dwGEMode |= VIA_GEM_8bpp;
 908         break;
 909     }
 910
 911 #if 0
 912     switch (ctx->shared.virtualWidth) {
 913     case 800:
 914         dwGEMode |= VIA_GEM_800;
 915         break;
 916     case 1024:
 917         dwGEMode |= VIA_GEM_1024;
 918         break;
 919     case 1280:
 920         dwGEMode |= VIA_GEM_1280;
 921         break;
 922     case 1600:
 923         dwGEMode |= VIA_GEM_1600;
 924         break;
 925     case 2048:
 926         dwGEMode |= VIA_GEM_2048;
 927         break;
 928     default:
 929         dwGEMode |= VIA_GEM_640;
 930         break;
 931     }
 932 #endif
 933
 934     VIAEnableMMIO(ctx);
 935
 936     /* Set BPP and Pitch */
 937     VIASETREG(VIA_REG_GEMODE, dwGEMode);
 938
 939     /* Set Src and Dst base address and pitch, pitch is qword */
 940     VIASETREG(VIA_REG_SRCBASE, 0x0);
 941     VIASETREG(VIA_REG_DSTBASE, 0x0);
 942     VIASETREG(VIA_REG_PITCH, VIA_PITCH_ENABLE |
 943               ((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) |
 944               (((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) << 16));
 945 }
 946
 947 static int b3DRegsInitialized = 0;
 948
 949 static void VIAInitialize3DEngine(DRIDriverContext *ctx)
 950 {
 951     VIAPtr  pVia = VIAPTR(ctx);
 952     int i;
 953
 954     if (!b3DRegsInitialized)
 955     {
 956
 957         VIASETREG(0x43C, 0x00010000);
 958
 959         for (i = 0; i <= 0x7D; i++)
 960         {
 961             VIASETREG(0x440, (uint32_t) i << 24);
 962         }
 963
 964         VIASETREG(0x43C, 0x00020000);
 965
 966         for (i = 0; i <= 0x94; i++)
 967         {
 968             VIASETREG(0x440, (uint32_t) i << 24);
 969         }
 970
 971         VIASETREG(0x440, 0x82400000);
 972
 973         VIASETREG(0x43C, 0x01020000);
 974
 975
 976         for (i = 0; i <= 0x94; i++)
 977         {
 978             VIASETREG(0x440, (uint32_t) i << 24);
 979         }
 980
 981         VIASETREG(0x440, 0x82400000);
 982         VIASETREG(0x43C, 0xfe020000);
 983
 984         for (i = 0; i <= 0x03; i++)
 985         {
 986             VIASETREG(0x440, (uint32_t) i << 24);
 987         }
 988
 989         VIASETREG(0x43C, 0x00030000);
 990
 991         for (i = 0; i <= 0xff; i++)
 992         {
 993             VIASETREG(0x440, 0);
 994         }
 995         VIASETREG(0x43C, 0x00100000);
 996         VIASETREG(0x440, 0x00333004);
 997         VIASETREG(0x440, 0x10000002);
 998         VIASETREG(0x440, 0x60000000);
 999         VIASETREG(0x440, 0x61000000);
1000         VIASETREG(0x440, 0x62000000);
1001         VIASETREG(0x440, 0x63000000);
1002         VIASETREG(0x440, 0x64000000);
1003
1004         VIASETREG(0x43C, 0x00fe0000);
1005
1006         if (pVia->ChipRev >= 3 )
1007             VIASETREG(0x440,0x40008c0f);
1008         else
1009             VIASETREG(0x440,0x4000800f);
1010
1011         VIASETREG(0x440,0x44000000);
1012         VIASETREG(0x440,0x45080C04);
1013         VIASETREG(0x440,0x46800408);
1014         VIASETREG(0x440,0x50000000);
1015         VIASETREG(0x440,0x51000000);
1016         VIASETREG(0x440,0x52000000);
1017         VIASETREG(0x440,0x53000000);
1018
1019         b3DRegsInitialized = 1;
1020         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1021                    "3D Engine has been initialized.\n");
1022     }
1023
1024     VIASETREG(0x43C,0x00fe0000);
1025     VIASETREG(0x440,0x08000001);
1026     VIASETREG(0x440,0x0A000183);
1027     VIASETREG(0x440,0x0B00019F);
1028     VIASETREG(0x440,0x0C00018B);
1029     VIASETREG(0x440,0x0D00019B);
1030     VIASETREG(0x440,0x0E000000);
1031     VIASETREG(0x440,0x0F000000);
1032     VIASETREG(0x440,0x10000000);
1033     VIASETREG(0x440,0x11000000);
1034     VIASETREG(0x440,0x20000000);
1035 }
1036
1037 static int
1038 WaitIdleCLE266(VIAPtr pVia)
1039 {
1040     int loop = 0;
1041
1042     /*mem_barrier();*/
1043
1044     while (!(VIAGETREG(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
1045         ;
1046
1047     while ((VIAGETREG(VIA_REG_STATUS) &
1048           (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
1049           (loop++ < MAXLOOP))
1050         ;
1051
1052     return loop >= MAXLOOP;
1053 }
1054
1055 static int viaInitFBDev(DRIDriverContext *ctx)
1056 {
1057     VIAPtr pVia = CALLOC(sizeof(*pVia));
1058
1059     ctx->driverPrivate = (void *)pVia;
1060
1061     switch (ctx->chipset) {
1062     case PCI_CHIP_CLE3122:
1063     case PCI_CHIP_CLE3022:
1064         pVia->Chipset = VIA_CLE266;
1065         break;
1066     case PCI_CHIP_VT7205:
1067     case PCI_CHIP_VT3205:
1068         pVia->Chipset = VIA_KM400;
1069         break;
1070     case PCI_CHIP_VT3204:
1071         pVia->Chipset = VIA_K8M800;
1072         break;
1073     case PCI_CHIP_VT3259:
1074         pVia->Chipset = VIA_PM800;
1075         break;
1076     default:
1077         xf86DrvMsg(0, X_ERROR, "VIA: Unknown device ID (0x%x)\n", ctx->chipset);
1078     }
1079
1080     /* _SOLO TODO XXX need to read ChipRev too */
1081     pVia->ChipRev = 0;
1082
1083     pVia->videoRambytes = ctx->shared.fbSize;
1084     pVia->MmioBase = ctx->MMIOStart;
1085     pVia->FrameBufferBase = ctx->FBStart & 0xfc000000;
1086
1087     pVia->FBFreeStart = ctx->shared.virtualWidth * ctx->cpp *
1088         ctx->shared.virtualHeight;
1089     pVia->FBFreeEnd = pVia->videoRambytes;
1090
1091     if (!VIADRIScreenInit(ctx))
1092         return 0;
1093
1094     VIAEnableMMIO(ctx);
1095
1096     /* Get video memory clock. */
1097     VGAOUT8(0x3D4, 0x3D);
1098     pVia->MemClk = (VGAIN8(0x3D5) & 0xF0) >> 4;
1099     xf86DrvMsg(0, X_INFO, "[dri] MemClk (0x%x)\n", pVia->MemClk);
1100
1101     /* 3D rendering has noise if not enabled. */
1102     VIAEnableExtendedFIFO(ctx);
1103
1104     VIAInitialize2DEngine(ctx);
1105
1106     /* Must disable MMIO or 3D won't work. */
1107     VIADisableMMIO(ctx);
1108
1109     VIAInitialize3DEngine(ctx);
1110
1111     return 1;
1112 }
1113
1114 static void viaHaltFBDev(DRIDriverContext *ctx)
1115 {
1116     drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
1117     drmClose(ctx->drmFD);
1118
1119     if (ctx->driverPrivate) {
1120         free(ctx->driverPrivate);
1121         ctx->driverPrivate = 0;
1122     }
1123 }
1124
1125 static int viaEngineShutdown(const DRIDriverContext *ctx)
1126 {
1127     return 1;
1128 }
1129
1130 static int viaEngineRestore(const DRIDriverContext *ctx)
1131 {
1132     return 1;
1133 }
1134
1135 const struct DRIDriverRec __driDriver =
1136 {
1137     viaInitContextModes,
1138     viaValidateMode,
1139     viaPostValidateMode,
1140     viaInitFBDev,
1141     viaHaltFBDev,
1142     viaEngineShutdown,
1143     viaEngineRestore,
1144     0,
1145 };
1146