src/mesa/drivers/dri/unichrome/server/via_dri.c

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via_dri.c,v 1.4 2003/09/24 02:43:30 dawes Exp $ */
   2 /*
   3  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   4  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25 #if 0
  26 #include "xf86.h"
  27 #include "xf86_OSproc.h"
  28 #include "xf86_ansic.h"
  29 #include "xf86Priv.h"
  30
  31 #include "xf86PciInfo.h"
  32 #include "xf86Pci.h"
  33
  34 #define _XF86DRI_SERVER_
  35 #include "GL/glxtokens.h"
  36
  37 #else
  38
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <errno.h>
  43 #include <unistd.h>
  44
  45 #include "driver.h"
  46 #include "drm.h"
  47 #include "imports.h"
  48 #endif
  49
  50 #include "dri_util.h"
  51 #include "sarea.h"
  52
  53 #include "via_context.h"
  54 #include "via_dri.h"
  55 #include "via_driver.h"
  56 #include "via_common.h"
  57 #include "xf86drm.h"
  58
  59 static void VIAEnableMMIO(DRIDriverContext * ctx);
  60 static void VIADisableMMIO(DRIDriverContext * ctx);
  61 static void VIADisableExtendedFIFO(DRIDriverContext *ctx);
  62 static void VIAEnableExtendedFIFO(DRIDriverContext *ctx);
  63 static void VIAInitialize2DEngine(DRIDriverContext *ctx);
  64 static void VIAInitialize3DEngine(DRIDriverContext *ctx);
  65
  66 static int VIADRIScreenInit(DRIDriverContext * ctx);
  67 static void VIADRICloseScreen(DRIDriverContext * ctx);
  68 static int VIADRIFinishScreenInit(DRIDriverContext * ctx);
  69
  70 /* _SOLO : missing macros normally defined by X code */
  71 #define xf86DrvMsg(a, b, ...) fprintf(stderr, __VA_ARGS__)
  72 #define MMIO_IN8(base, addr) ((*(((volatile CARD8*)base)+(addr)))+0)
  73 #define MMIO_OUT8(base, addr, val) ((*(((volatile CARD8*)base)+(addr)))=((CARD8)val))
  74 #define MMIO_OUT16(base, addr, val) ((*(volatile CARD16*)(((CARD8*)base)+(addr)))=((CARD16)val))
  75
  76 #define VIDEO   0
  77 #define AGP             1
  78 #define AGP_PAGE_SIZE 4096
  79 #define AGP_PAGES 8192
  80 #define AGP_SIZE (AGP_PAGE_SIZE * AGP_PAGES)
  81 #define AGP_CMDBUF_PAGES 256
  82 #define AGP_CMDBUF_SIZE (AGP_PAGE_SIZE * AGP_CMDBUF_PAGES)
  83
  84 static char VIAKernelDriverName[] = "via";
  85 static char VIAClientDriverName[] = "via";
  86
  87 static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia);
  88 static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia);
  89 static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia);
  90 static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia);
  91 static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia);
  92
  93 static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia)
  94 {
  95     unsigned long  agp_phys;
  96     unsigned int agpaddr;
  97     VIADRIPtr pVIADRI;
  98     pVIADRI = pVia->devPrivate;
  99     pVia->agpSize = 0;
 100
 101     if (drmAgpAcquire(pVia->drmFD) < 0) {
 102         xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpAcquire failed %d\n", errno);
 103         return FALSE;
 104     }
 105
 106     if (drmAgpEnable(pVia->drmFD, drmAgpGetMode(pVia->drmFD)&~0x0) < 0) {
 107          xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpEnable failed\n");
 108         return FALSE;
 109     }
 110
 111     xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] drmAgpEnabled succeeded\n");
 112
 113     if (drmAgpAlloc(pVia->drmFD, AGP_SIZE, 0, &agp_phys, &pVia->agpHandle) < 0) {
 114         xf86DrvMsg(pScreen->myNum, X_ERROR,
 115                  "[drm] drmAgpAlloc failed\n");
 116         drmAgpRelease(pVia->drmFD);
 117         return FALSE;
 118     }
 119
 120     if (drmAgpBind(pVia->drmFD, pVia->agpHandle, 0) < 0) {
 121         xf86DrvMsg(pScreen->myNum, X_ERROR,
 122                  "[drm] drmAgpBind failed\n");
 123         drmAgpFree(pVia->drmFD, pVia->agpHandle);
 124         drmAgpRelease(pVia->drmFD);
 125
 126         return FALSE;
 127     }
 128
 129     pVia->agpSize = AGP_SIZE;
 130     pVia->agpAddr = drmAgpBase(pVia->drmFD);
 131     xf86DrvMsg(pScreen->myNum, X_INFO,
 132                  "[drm] agpAddr = 0x%08lx\n",pVia->agpAddr);
 133
 134     pVIADRI->agp.size = pVia->agpSize;
 135     if (drmAddMap(pVia->drmFD, (drmHandle)0,
 136                  pVIADRI->agp.size, DRM_AGP, 0,
 137                  &pVIADRI->agp.handle) < 0) {
 138         xf86DrvMsg(pScreen->myNum, X_ERROR,
 139             "[drm] Failed to map public agp area\n");
 140         pVIADRI->agp.size = 0;
 141         return FALSE;
 142     }
 143     /* Map AGP from kernel to Xserver - Not really needed */
 144     drmMap(pVia->drmFD, pVIADRI->agp.handle,pVIADRI->agp.size,
 145         (drmAddressPtr)&agpaddr);
 146
 147 #if 0
 148     xf86DrvMsg(pScreen->myNum, X_INFO,
 149                 "[drm] agpBase = 0x%08lx\n", pVia->agpBase);
 150     xf86DrvMsg(pScreen->myNum, X_INFO,
 151                 "[drm] agpAddr = 0x%08lx\n", pVia->agpAddr);
 152 #endif
 153     xf86DrvMsg(pScreen->myNum, X_INFO,
 154                 "[drm] agpSize = 0x%08lx\n", pVia->agpSize);
 155     xf86DrvMsg(pScreen->myNum, X_INFO,
 156                 "[drm] agp physical addr = 0x%08lx\n", agp_phys);
 157
 158     drmVIAAgpInit(pVia->drmFD, 0, AGP_SIZE);
 159     return TRUE;
 160
 161 }
 162
 163 static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia)
 164 {
 165     int FBSize = pVia->FBFreeEnd-pVia->FBFreeStart;
 166     int FBOffset = pVia->FBFreeStart;
 167     VIADRIPtr pVIADRI = pVia->devPrivate;
 168     pVIADRI->fbOffset = FBOffset;
 169     pVIADRI->fbSize = pVia->videoRambytes;
 170
 171     if (drmVIAFBInit(pVia->drmFD, FBOffset, FBSize) < 0) {
 172         xf86DrvMsg(pScreen->myNum, X_ERROR,"[drm] failed to init frame buffer area\n");
 173         return FALSE;
 174     }
 175     else {
 176         xf86DrvMsg(pScreen->myNum, X_INFO,"[drm] FBFreeStart= 0x%08lx FBFreeEnd= 0x%08lx FBSize= 0x%08lx\n", pVia->FBFreeStart, pVia->FBFreeEnd, FBSize);
 177         return TRUE;
 178     }
 179 }
 180
 181 static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia)
 182 {
 183     return TRUE;
 184 }
 185
 186 static int VIADRIScreenInit(DRIDriverContext * ctx)
 187 {
 188     VIAPtr pVia = VIAPTR(ctx);
 189     VIADRIPtr pVIADRI;
 190     int err;
 191
 192 #if 0
 193     ctx->shared.SAREASize = ((sizeof(XF86DRISAREARec) + 0xfff) & 0x1000);
 194 #else
 195     if (sizeof(XF86DRISAREARec)+sizeof(VIASAREAPriv) > SAREA_MAX) {
 196         xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 197                         "Data does not fit in SAREA\n");
 198         return FALSE;
 199     }
 200     ctx->shared.SAREASize = SAREA_MAX;
 201 #endif
 202
 203     ctx->drmFD = drmOpen(VIAKernelDriverName, NULL);
 204     if (ctx->drmFD < 0) {
 205         fprintf(stderr, "[drm] drmOpen failed\n");
 206         return 0;
 207     }
 208     pVia->drmFD = ctx->drmFD;
 209
 210     err = drmSetBusid(ctx->drmFD, ctx->pciBusID);
 211     if (err < 0) {
 212         fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
 213                 ctx->drmFD, ctx->pciBusID, strerror(-err));
 214         return 0;
 215     }
 216
 217     err = drmAddMap(ctx->drmFD, 0, ctx->shared.SAREASize, DRM_SHM,
 218                   DRM_CONTAINS_LOCK, &ctx->shared.hSAREA);
 219     if (err < 0) {
 220         fprintf(stderr, "[drm] drmAddMap failed\n");
 221         return 0;
 222     }
 223     fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
 224             ctx->shared.SAREASize, ctx->shared.hSAREA);
 225
 226     if (drmMap(ctx->drmFD,
 227                ctx->shared.hSAREA,
 228                ctx->shared.SAREASize,
 229                (drmAddressPtr)(&ctx->pSAREA)) < 0)
 230     {
 231         fprintf(stderr, "[drm] drmMap failed\n");
 232         return 0;
 233     }
 234     memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
 235     fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
 236             ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
 237
 238     /* Need to AddMap the framebuffer and mmio regions here:
 239      */
 240     if (drmAddMap(ctx->drmFD,
 241                   (drmHandle)ctx->FBStart,
 242                   ctx->FBSize,
 243                   DRM_FRAME_BUFFER,
 244 #ifndef _EMBEDDED
 245                    0,
 246 #else
 247                    DRM_READ_ONLY,
 248 #endif
 249                    &ctx->shared.hFrameBuffer) < 0)
 250     {
 251         fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
 252         return 0;
 253     }
 254
 255     fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
 256             ctx->shared.hFrameBuffer);
 257
 258     pVIADRI = (VIADRIPtr) CALLOC(sizeof(VIADRIRec));
 259     if (!pVIADRI) {
 260         drmClose(ctx->drmFD);
 261         return FALSE;
 262     }
 263     pVia->devPrivate = pVIADRI;
 264     ctx->driverClientMsg = pVIADRI;
 265     ctx->driverClientMsgSize = sizeof(*pVIADRI);
 266
 267     pVia->IsPCI = !VIADRIAgpInit(ctx, pVia);
 268
 269     if (pVia->IsPCI) {
 270         VIADRIPciInit(ctx, pVia);
 271         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use pci.\n" );
 272     }
 273     else
 274         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use agp.\n" );
 275
 276     if (!(VIADRIFBInit(ctx, pVia))) {
 277         VIADRICloseScreen(ctx);
 278         xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] frame buffer initialize fial .\n" );
 279         return FALSE;
 280     }
 281
 282     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] frame buffer initialized.\n" );
 283
 284     /* DRIScreenInit doesn't add all the common mappings.  Add additional mappings here. */
 285     if (!VIADRIMapInit(ctx, pVia)) {
 286         VIADRICloseScreen(ctx);
 287         return FALSE;
 288     }
 289     pVIADRI->regs.size = VIA_MMIO_REGSIZE;
 290     pVIADRI->regs.map = 0;
 291     pVIADRI->regs.handle = pVia->registerHandle;
 292     xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] mmio Registers = 0x%08lx\n",
 293         pVIADRI->regs.handle);
 294
 295     /*pVIADRI->drixinerama = pVia->drixinerama;*/
 296     /*=* John Sheng [2003.12.9] Tuxracer & VQ *=*/
 297     pVIADRI->VQEnable = pVia->VQEnable;
 298
 299     if (drmMap(pVia->drmFD,
 300                pVIADRI->regs.handle,
 301                pVIADRI->regs.size,
 302                (drmAddress *)&pVia->MapBase) != 0)
 303     {
 304         VIADRICloseScreen(ctx);
 305         return FALSE;
 306     }
 307
 308     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] mmio mapped.\n" );
 309
 310     return VIADRIFinishScreenInit(ctx);
 311 }
 312
 313 static void
 314 VIADRICloseScreen(DRIDriverContext * ctx)
 315 {
 316     VIAPtr pVia = VIAPTR(ctx);
 317     VIADRIPtr pVIADRI=(VIADRIPtr)pVia->devPrivate;
 318
 319     if (pVia->MapBase) {
 320         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Unmapping MMIO registers\n");
 321         drmUnmap(pVia->MapBase, pVIADRI->regs.size);
 322     }
 323
 324     if (pVia->agpSize) {
 325         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Freeing agp memory\n");
 326         drmAgpFree(pVia->drmFD, pVia->agpHandle);
 327         xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Releasing agp module\n");
 328         drmAgpRelease(pVia->drmFD);
 329     }
 330 }
 331
 332 static int
 333 VIADRIFinishScreenInit(DRIDriverContext * ctx)
 334 {
 335     VIAPtr pVia = VIAPTR(ctx);
 336     VIADRIPtr pVIADRI;
 337     int err;
 338
 339     err = drmCreateContext(ctx->drmFD, &ctx->serverContext);
 340     if (err != 0) {
 341         fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
 342         return FALSE;
 343     }
 344
 345     DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);
 346
 347
 348     if (!VIADRIKernelInit(ctx, pVia)) {
 349         VIADRICloseScreen(ctx);
 350         return FALSE;
 351     }
 352     xf86DrvMsg(pScreen->myNum, X_INFO, "[dri] kernel data initialized.\n");
 353
 354     /* set SAREA value */
 355     {
 356         VIASAREAPriv *saPriv;
 357
 358         saPriv=(VIASAREAPriv*)(((char*)ctx->pSAREA) +
 359                                sizeof(XF86DRISAREARec));
 360         assert(saPriv);
 361         memset(saPriv, 0, sizeof(*saPriv));
 362         saPriv->CtxOwner = -1;
 363     }
 364     pVIADRI=(VIADRIPtr)pVia->devPrivate;
 365     pVIADRI->deviceID=pVia->Chipset;
 366     pVIADRI->width=ctx->shared.virtualWidth;
 367     pVIADRI->height=ctx->shared.virtualHeight;
 368     pVIADRI->mem=ctx->shared.fbSize;
 369     pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8;
 370     pVIADRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
 371     /* TODO */
 372     pVIADRI->scrnX=pVIADRI->width;
 373     pVIADRI->scrnY=pVIADRI->height;
 374
 375     return TRUE;
 376 }
 377
 378 /* Initialize the kernel data structures. */
 379 static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia)
 380 {
 381     drmVIAInit drmInfo;
 382     memset(&drmInfo, 0, sizeof(drmVIAInit));
 383     drmInfo.sarea_priv_offset   = sizeof(XF86DRISAREARec);
 384     drmInfo.fb_offset           = pVia->FrameBufferBase;
 385     drmInfo.mmio_offset         = pVia->registerHandle;
 386     if (pVia->IsPCI)
 387         drmInfo.agpAddr = (CARD32)NULL;
 388     else
 389         drmInfo.agpAddr = (CARD32)pVia->agpAddr;
 390
 391     if (drmVIAInitMAP(pVia->drmFD, &drmInfo) < 0) return FALSE;
 392
 393     return TRUE;
 394 }
 395 /* Add a map for the MMIO registers */
 396 static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia)
 397 {
 398     int flags = 0;
 399
 400     if (drmAddMap(pVia->drmFD, pVia->MmioBase, VIA_MMIO_REGSIZE,
 401                   DRM_REGISTERS, flags, &pVia->registerHandle) < 0) {
 402         return FALSE;
 403     }
 404
 405     xf86DrvMsg(pScreen->myNum, X_INFO,
 406         "[drm] register handle = 0x%08lx\n", pVia->registerHandle);
 407
 408     return TRUE;
 409 }
 410
 411 const __GLcontextModes __glModes[] =
 412 {
 413     /* 32 bit, RGBA Depth=16 Stencil=8 */
 414     {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
 415      .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_TRUE,
 416      .redBits = 8, .greenBits = 8, .blueBits = 8, .alphaBits = 8,
 417      .redMask = 0xff0000, .greenMask = 0xff00, .blueMask = 0xff, .alphaMask = 0xff000000,
 418      .rgbBits = 32, .indexBits = 0,
 419      .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
 420      .depthBits = 16, .stencilBits = 8,
 421      .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_TRUE, },
 422
 423 #if 0
 424     /* 16 bit, RGB Depth=16 */
 425     {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
 426      .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_FALSE,
 427      .redBits = 5, .greenBits = 6, .blueBits = 5, .alphaBits = 0,
 428      .redMask = 0xf800, .greenMask = 0x07e0, .blueMask = 0x001f, .alphaMask = 0x0,
 429      .rgbBits = 16, .indexBits = 0,
 430      .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
 431      .depthBits = 16, .stencilBits = 0,
 432      .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_TRUE, },
 433 #endif
 434 };
 435
 436 static int viaInitContextModes(const DRIDriverContext *ctx,
 437                                   int *numModes, const __GLcontextModes **modes)
 438 {
 439     *numModes = sizeof(__glModes)/sizeof(__GLcontextModes *);
 440     *modes = &__glModes[0];
 441     return 1;
 442 }
 443
 444 static int viaValidateMode(const DRIDriverContext *ctx)
 445 {
 446     VIAPtr pVia = VIAPTR(ctx);
 447
 448     return 1;
 449 }
 450
 451 static int viaPostValidateMode(const DRIDriverContext *ctx)
 452 {
 453     VIAPtr pVia = VIAPTR(ctx);
 454
 455     return 1;
 456 }
 457
 458 static void VIAEnableMMIO(DRIDriverContext * ctx)
 459 {
 460     /*vgaHWPtr hwp = VGAHWPTR(ctx);*/
 461     VIAPtr pVia = VIAPTR(ctx);
 462     unsigned char val;
 463
 464 #if 0
 465     if (xf86IsPrimaryPci(pVia->PciInfo)) {
 466         /* If we are primary card, we still use std vga port. If we use
 467          * MMIO, system will hang in vgaHWSave when our card used in
 468          * PLE and KLE (integrated Trident MVP4)
 469          */
 470         vgaHWSetStdFuncs(hwp);
 471     }
 472     else {
 473         vgaHWSetMmioFuncs(hwp, pVia->MapBase, 0x8000);
 474     }
 475 #endif
 476
 477     val = VGAIN8(0x3c3);
 478     VGAOUT8(0x3c3, val | 0x01);
 479     val = VGAIN8(0x3cc);
 480     VGAOUT8(0x3c2, val | 0x01);
 481
 482     /* Unlock Extended IO Space */
 483     VGAOUT8(0x3c4, 0x10);
 484     VGAOUT8(0x3c5, 0x01);
 485
 486     /* Enable MMIO */
 487     if(!pVia->IsSecondary) {
 488         VGAOUT8(0x3c4, 0x1a);
 489         val = VGAIN8(0x3c5);
 490 #ifdef DEBUG
 491         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "primary val = %x\n", val);
 492 #endif
 493         VGAOUT8(0x3c5, val | 0x68);
 494     }
 495     else {
 496         VGAOUT8(0x3c4, 0x1a);
 497         val = VGAIN8(0x3c5);
 498 #ifdef DEBUG
 499         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "secondary val = %x\n", val);
 500 #endif
 501         VGAOUT8(0x3c5, val | 0x38);
 502     }
 503
 504     /* Unlock CRTC registers */
 505     VGAOUT8(0x3d4, 0x47);
 506     VGAOUT8(0x3d5, 0x00);
 507
 508     return;
 509 }
 510
 511 static void VIADisableMMIO(DRIDriverContext * ctx)
 512 {
 513     VIAPtr pVia = VIAPTR(ctx);
 514     unsigned char val;
 515
 516     VGAOUT8(0x3c4, 0x1a);
 517     val = VGAIN8(0x3c5);
 518     VGAOUT8(0x3c5, val & 0x97);
 519
 520     return;
 521 }
 522
 523 static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
 524 {
 525     VIAPtr  pVia = VIAPTR(ctx);
 526     CARD32  dwGE230, dwGE298;
 527
 528     /* Cause of exit XWindow will dump back register value, others chipset no
 529      * need to set extended fifo value */
 530     if (pVia->Chipset == VIA_CLE266 && pVia->ChipRev < 15 &&
 531         (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary)) {
 532         /* Turn off Extend FIFO */
 533         /* 0x298[29] */
 534         dwGE298 = VIAGETREG(0x298);
 535         VIASETREG(0x298, dwGE298 | 0x20000000);
 536         /* 0x230[21] */
 537         dwGE230 = VIAGETREG(0x230);
 538         VIASETREG(0x230, dwGE230 & ~0x00200000);
 539         /* 0x298[29] */
 540         dwGE298 = VIAGETREG(0x298);
 541         VIASETREG(0x298, dwGE298 & ~0x20000000);
 542     }
 543 }
 544
 545 static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
 546 {
 547     VIAPtr  pVia = VIAPTR(ctx);
 548     CARD8   bRegTemp;
 549     CARD32  dwGE230, dwGE298;
 550
 551     switch (pVia->Chipset) {
 552     case VIA_CLE266:
 553         if (pVia->ChipRev > 14) {  /* For 3123Cx */
 554             if (pVia->HasSecondary) {  /* SAMM or DuoView case */
 555                 if (ctx->shared.virtualWidth >= 1024)
 556                 {
 557                     /* 3c5.16[0:5] */
 558                         VGAOUT8(0x3C4, 0x16);
 559                     bRegTemp = VGAIN8(0x3C5);
 560                     bRegTemp &= ~0x3F;
 561                         bRegTemp |= 0x1C;
 562                     VGAOUT8(0x3C5, bRegTemp);
 563                         /* 3c5.17[0:6] */
 564                     VGAOUT8(0x3C4, 0x17);
 565                         bRegTemp = VGAIN8(0x3C5);
 566                     bRegTemp &= ~0x7F;
 567                         bRegTemp |= 0x3F;
 568                     VGAOUT8(0x3C5, bRegTemp);
 569                     pVia->EnableExtendedFIFO = TRUE;
 570                 }
 571             }
 572             else   /* Single view or Simultaneoue case */
 573             {
 574                 if (ctx->shared.virtualWidth > 1024)
 575                 {
 576                     /* 3c5.16[0:5] */
 577                         VGAOUT8(0x3C4, 0x16);
 578                     bRegTemp = VGAIN8(0x3C5);
 579                     bRegTemp &= ~0x3F;
 580                         bRegTemp |= 0x17;
 581                     VGAOUT8(0x3C5, bRegTemp);
 582                         /* 3c5.17[0:6] */
 583                     VGAOUT8(0x3C4, 0x17);
 584                         bRegTemp = VGAIN8(0x3C5);
 585                     bRegTemp &= ~0x7F;
 586                         bRegTemp |= 0x2F;
 587                     VGAOUT8(0x3C5, bRegTemp);
 588                     pVia->EnableExtendedFIFO = TRUE;
 589                 }
 590             }
 591             /* 3c5.18[0:5] */
 592             VGAOUT8(0x3C4, 0x18);
 593             bRegTemp = VGAIN8(0x3C5);
 594             bRegTemp &= ~0x3F;
 595             bRegTemp |= 0x17;
 596             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 597             VGAOUT8(0x3C5, bRegTemp);
 598         }
 599         else {      /* for 3123Ax */
 600             if (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary) {
 601                 /* Turn on Extend FIFO */
 602                 /* 0x298[29] */
 603                 dwGE298 = VIAGETREG(0x298);
 604                 VIASETREG(0x298, dwGE298 | 0x20000000);
 605                 /* 0x230[21] */
 606                 dwGE230 = VIAGETREG(0x230);
 607                 VIASETREG(0x230, dwGE230 | 0x00200000);
 608                 /* 0x298[29] */
 609                 dwGE298 = VIAGETREG(0x298);
 610                 VIASETREG(0x298, dwGE298 & ~0x20000000);
 611
 612                 /* 3c5.16[0:5] */
 613                 VGAOUT8(0x3C4, 0x16);
 614                 bRegTemp = VGAIN8(0x3C5);
 615                 bRegTemp &= ~0x3F;
 616                 bRegTemp |= 0x17;
 617                 /* bRegTemp |= 0x10; */
 618                 VGAOUT8(0x3C5, bRegTemp);
 619                 /* 3c5.17[0:6] */
 620                 VGAOUT8(0x3C4, 0x17);
 621                 bRegTemp = VGAIN8(0x3C5);
 622                 bRegTemp &= ~0x7F;
 623                 bRegTemp |= 0x2F;
 624                 /*bRegTemp |= 0x1F;*/
 625                 VGAOUT8(0x3C5, bRegTemp);
 626                 /* 3c5.18[0:5] */
 627                 VGAOUT8(0x3C4, 0x18);
 628                 bRegTemp = VGAIN8(0x3C5);
 629                 bRegTemp &= ~0x3F;
 630                 bRegTemp |= 0x17;
 631                 bRegTemp |= 0x40;  /* force the preq always higher than treq */
 632                 VGAOUT8(0x3C5, bRegTemp);
 633                     pVia->EnableExtendedFIFO = TRUE;
 634             }
 635         }
 636         break;
 637     case VIA_KM400:
 638         if (pVia->HasSecondary) {  /* SAMM or DuoView case */
 639             if ((ctx->shared.virtualWidth >= 1600) &&
 640                 (pVia->MemClk <= VIA_MEM_DDR200)) {
 641                     /* enable CRT extendded FIFO */
 642                 VGAOUT8(0x3C4, 0x17);
 643                 VGAOUT8(0x3C5, 0x1C);
 644                 /* revise second display queue depth and read threshold */
 645                     VGAOUT8(0x3C4, 0x16);
 646                 bRegTemp = VGAIN8(0x3C5);
 647                 bRegTemp &= ~0x3F;
 648                 bRegTemp = (bRegTemp) | (0x09);
 649                 VGAOUT8(0x3C5, bRegTemp);
 650             }
 651             else {
 652                 /* enable CRT extendded FIFO */
 653                 VGAOUT8(0x3C4, 0x17);
 654                 VGAOUT8(0x3C5,0x3F);
 655                 /* revise second display queue depth and read threshold */
 656                 VGAOUT8(0x3C4, 0x16);
 657                 bRegTemp = VGAIN8(0x3C5);
 658                 bRegTemp &= ~0x3F;
 659                 bRegTemp = (bRegTemp) | (0x1C);
 660                 VGAOUT8(0x3C5, bRegTemp);
 661             }
 662             /* 3c5.18[0:5] */
 663             VGAOUT8(0x3C4, 0x18);
 664             bRegTemp = VGAIN8(0x3C5);
 665             bRegTemp &= ~0x3F;
 666             bRegTemp |= 0x17;
 667             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 668             VGAOUT8(0x3C5, bRegTemp);
 669             pVia->EnableExtendedFIFO = TRUE;
 670         }
 671         else {
 672             if ( (ctx->shared.virtualWidth > 1024) && (ctx->shared.virtualWidth <= 1280) )
 673             {
 674                 /* enable CRT extendded FIFO */
 675                 VGAOUT8(0x3C4, 0x17);
 676                 VGAOUT8(0x3C5, 0x3F);
 677                 /* revise second display queue depth and read threshold */
 678                 VGAOUT8(0x3C4, 0x16);
 679                 bRegTemp = VGAIN8(0x3C5);
 680                 bRegTemp &= ~0x3F;
 681                 bRegTemp = (bRegTemp) | (0x17);
 682                 VGAOUT8(0x3C5, bRegTemp);
 683                     pVia->EnableExtendedFIFO = TRUE;
 684             }
 685             else if ((ctx->shared.virtualWidth > 1280))
 686             {
 687                 /* enable CRT extendded FIFO */
 688                 VGAOUT8(0x3C4, 0x17);
 689                 VGAOUT8(0x3C5, 0x3F);
 690                 /* revise second display queue depth and read threshold */
 691                 VGAOUT8(0x3C4, 0x16);
 692                 bRegTemp = VGAIN8(0x3C5);
 693                 bRegTemp &= ~0x3F;
 694                 bRegTemp = (bRegTemp) | (0x1C);
 695                 VGAOUT8(0x3C5, bRegTemp);
 696                     pVia->EnableExtendedFIFO = TRUE;
 697             }
 698             else
 699             {
 700                 /* enable CRT extendded FIFO */
 701                 VGAOUT8(0x3C4, 0x17);
 702                 VGAOUT8(0x3C5, 0x3F);
 703                 /* revise second display queue depth and read threshold */
 704                 VGAOUT8(0x3C4, 0x16);
 705                 bRegTemp = VGAIN8(0x3C5);
 706                 bRegTemp &= ~0x3F;
 707                 bRegTemp = (bRegTemp) | (0x10);
 708                 VGAOUT8(0x3C5, bRegTemp);
 709             }
 710             /* 3c5.18[0:5] */
 711             VGAOUT8(0x3C4, 0x18);
 712             bRegTemp = VGAIN8(0x3C5);
 713             bRegTemp &= ~0x3F;
 714             bRegTemp |= 0x17;
 715             bRegTemp |= 0x40;  /* force the preq always higher than treq */
 716             VGAOUT8(0x3C5, bRegTemp);
 717         }
 718         break;
 719     case VIA_K8M800:
 720         /*=* R1 Display FIFO depth (384 /8 -1 -> 0xbf) SR17[7:0] (8bits) *=*/
 721         VGAOUT8(0x3c4, 0x17);
 722         VGAOUT8(0x3c5, 0xbf);
 723
 724         /*=* R2 Display fetch datum threshold value (328/4 -> 0x52)
 725              SR16[5:0], SR16[7] (7bits) *=*/
 726         VGAOUT8(0x3c4, 0x16);
 727         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 728         bRegTemp |= (0x52 & 0x3F);
 729         bRegTemp |= ((0x52 & 0x40) << 1);
 730         VGAOUT8(0x3c5, bRegTemp);
 731
 732         /*=* R3 Switch to the highest agent threshold value (74 -> 0x4a)
 733              SR18[5:0], SR18[7] (7bits) *=*/
 734         VGAOUT8(0x3c4, 0x18);
 735         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 736         bRegTemp |= (0x4a & 0x3F);
 737         bRegTemp |= ((0x4a & 0x40) << 1);
 738         VGAOUT8(0x3c5, bRegTemp);
 739 #if 0
 740         /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
 741              SR1C[7:0], SR1D[1:0] (10bits) *=*/
 742         wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
 743         VGAOUT8(0x3c4, 0x1c);
 744         VGAOUT8(0x3c5, (CARD8)(wRegTemp & 0xFF));
 745         VGAOUT8(0x3c4, 0x1d);
 746         bRegTemp = VGAIN8(0x3c5) & ~0x03;
 747         VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
 748 #endif
 749         if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
 750         {
 751             /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
 752             VGAOUT8(0x3c4, 0x22);
 753             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 754             VGAOUT8(0x3c5, bRegTemp | 0x10);
 755         }
 756         else
 757         {
 758             /*=* Max. length for a request SR22[4:0]
 759                  (128/4 -> over flow 0x0) *=*/
 760             VGAOUT8(0x3c4, 0x22);
 761             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 762             VGAOUT8(0x3c5, bRegTemp);
 763         }
 764         break;
 765     case VIA_PM800:
 766         /*=* R1 Display FIFO depth (96-1 -> 0x5f) SR17[7:0] (8bits) *=*/
 767         VGAOUT8(0x3c4, 0x17);
 768         VGAOUT8(0x3c5, 0x5f);
 769
 770         /*=* R2 Display fetch datum threshold value (32 -> 0x20)
 771              SR16[5:0], SR16[7] (7bits) *=*/
 772         VGAOUT8(0x3c4, 0x16);
 773         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 774         bRegTemp |= (0x20 & 0x3F);
 775         bRegTemp |= ((0x20 & 0x40) << 1);
 776         VGAOUT8(0x3c5, bRegTemp);
 777
 778         /*=* R3 Switch to the highest agent threshold value (16 -> 0x10)
 779              SR18[5:0], SR18[7] (7bits) *=*/
 780         VGAOUT8(0x3c4, 0x18);
 781         bRegTemp = VGAIN8(0x3c5) & ~0xBF;
 782         bRegTemp |= (0x10 & 0x3F);
 783         bRegTemp |= ((0x10 & 0x40) << 1);
 784         VGAOUT8(0x3c5, bRegTemp);
 785 #if 0
 786         /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
 787              SR1C[7:0], SR1D[1:0] (10bits) *=*/
 788         wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
 789         VGAOUT8(0x3c4, 0x1c);
 790         VGAOUT8(0x3c5, (CARD8)(wRegTemp & 0xFF));
 791         VGAOUT8(0x3c4, 0x1d);
 792         bRegTemp = VGAIN8(0x3c5) & ~0x03;
 793         VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
 794 #endif
 795         if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
 796         {
 797             /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
 798             VGAOUT8(0x3c4, 0x22);
 799             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 800             VGAOUT8(0x3c5, bRegTemp | 0x10);
 801         }
 802         else
 803         {
 804             /*=* Max. length for a request SR22[4:0] (0x1F) *=*/
 805             VGAOUT8(0x3c4, 0x22);
 806             bRegTemp = VGAIN8(0x3c5) & ~0x1F;
 807             VGAOUT8(0x3c5, bRegTemp | 0x1F);
 808         }
 809         break;
 810     default:
 811         break;
 812     }
 813 }
 814
 815 static void VIAInitialize2DEngine(DRIDriverContext *ctx)
 816 {
 817     VIAPtr  pVia = VIAPTR(ctx);
 818     CARD32  dwVQStartAddr, dwVQEndAddr;
 819     CARD32  dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
 820     CARD32  dwGEMode;
 821
 822     /* init 2D engine regs to reset 2D engine */
 823     VIASETREG(0x04, 0x0);
 824     VIASETREG(0x08, 0x0);
 825     VIASETREG(0x0c, 0x0);
 826     VIASETREG(0x10, 0x0);
 827     VIASETREG(0x14, 0x0);
 828     VIASETREG(0x18, 0x0);
 829     VIASETREG(0x1c, 0x0);
 830     VIASETREG(0x20, 0x0);
 831     VIASETREG(0x24, 0x0);
 832     VIASETREG(0x28, 0x0);
 833     VIASETREG(0x2c, 0x0);
 834     VIASETREG(0x30, 0x0);
 835     VIASETREG(0x34, 0x0);
 836     VIASETREG(0x38, 0x0);
 837     VIASETREG(0x3c, 0x0);
 838     VIASETREG(0x40, 0x0);
 839
 840     VIADisableMMIO(ctx);
 841
 842     /* Init AGP and VQ regs */
 843     VIASETREG(0x43c, 0x00100000);
 844     VIASETREG(0x440, 0x00000000);
 845     VIASETREG(0x440, 0x00333004);
 846     VIASETREG(0x440, 0x60000000);
 847     VIASETREG(0x440, 0x61000000);
 848     VIASETREG(0x440, 0x62000000);
 849     VIASETREG(0x440, 0x63000000);
 850     VIASETREG(0x440, 0x64000000);
 851     VIASETREG(0x440, 0x7D000000);
 852
 853     VIASETREG(0x43c, 0xfe020000);
 854     VIASETREG(0x440, 0x00000000);
 855
 856     if (pVia->VQStart != 0) {
 857         /* Enable VQ */
 858         dwVQStartAddr = pVia->VQStart;
 859         dwVQEndAddr = pVia->VQEnd;
 860         dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
 861         dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
 862         dwVQStartEndH = 0x52000000 | ((dwVQStartAddr & 0xFF000000) >> 24) |
 863                         ((dwVQEndAddr & 0xFF000000) >> 16);
 864         dwVQLen = 0x53000000 | (VIA_VQ_SIZE >> 3);
 865
 866         VIASETREG(0x43c, 0x00fe0000);
 867         VIASETREG(0x440, 0x080003fe);
 868         VIASETREG(0x440, 0x0a00027c);
 869         VIASETREG(0x440, 0x0b000260);
 870         VIASETREG(0x440, 0x0c000274);
 871         VIASETREG(0x440, 0x0d000264);
 872         VIASETREG(0x440, 0x0e000000);
 873         VIASETREG(0x440, 0x0f000020);
 874         VIASETREG(0x440, 0x1000027e);
 875         VIASETREG(0x440, 0x110002fe);
 876         VIASETREG(0x440, 0x200f0060);
 877
 878         VIASETREG(0x440, 0x00000006);
 879         VIASETREG(0x440, 0x40008c0f);
 880         VIASETREG(0x440, 0x44000000);
 881         VIASETREG(0x440, 0x45080c04);
 882         VIASETREG(0x440, 0x46800408);
 883
 884         VIASETREG(0x440, dwVQStartEndH);
 885         VIASETREG(0x440, dwVQStartL);
 886         VIASETREG(0x440, dwVQEndL);
 887         VIASETREG(0x440, dwVQLen);
 888     }
 889     else {
 890         /* Diable VQ */
 891         VIASETREG(0x43c, 0x00fe0000);
 892         VIASETREG(0x440, 0x00000004);
 893         VIASETREG(0x440, 0x40008c0f);
 894         VIASETREG(0x440, 0x44000000);
 895         VIASETREG(0x440, 0x45080c04);
 896         VIASETREG(0x440, 0x46800408);
 897     }
 898
 899     dwGEMode = 0;
 900
 901     switch (ctx->bpp) {
 902     case 16:
 903         dwGEMode |= VIA_GEM_16bpp;
 904         break;
 905     case 32:
 906         dwGEMode |= VIA_GEM_32bpp;
 907     default:
 908         dwGEMode |= VIA_GEM_8bpp;
 909         break;
 910     }
 911
 912 #if 0
 913     switch (ctx->shared.virtualWidth) {
 914     case 800:
 915         dwGEMode |= VIA_GEM_800;
 916         break;
 917     case 1024:
 918         dwGEMode |= VIA_GEM_1024;
 919         break;
 920     case 1280:
 921         dwGEMode |= VIA_GEM_1280;
 922         break;
 923     case 1600:
 924         dwGEMode |= VIA_GEM_1600;
 925         break;
 926     case 2048:
 927         dwGEMode |= VIA_GEM_2048;
 928         break;
 929     default:
 930         dwGEMode |= VIA_GEM_640;
 931         break;
 932     }
 933 #endif
 934
 935     VIAEnableMMIO(ctx);
 936
 937     /* Set BPP and Pitch */
 938     VIASETREG(VIA_REG_GEMODE, dwGEMode);
 939
 940     /* Set Src and Dst base address and pitch, pitch is qword */
 941     VIASETREG(VIA_REG_SRCBASE, 0x0);
 942     VIASETREG(VIA_REG_DSTBASE, 0x0);
 943     VIASETREG(VIA_REG_PITCH, VIA_PITCH_ENABLE |
 944               ((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) |
 945               (((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) << 16));
 946 }
 947
 948 static int b3DRegsInitialized = 0;
 949
 950 static void VIAInitialize3DEngine(DRIDriverContext *ctx)
 951 {
 952     VIAPtr  pVia = VIAPTR(ctx);
 953     int i;
 954
 955     if (!b3DRegsInitialized)
 956     {
 957
 958         VIASETREG(0x43C, 0x00010000);
 959
 960         for (i = 0; i <= 0x7D; i++)
 961         {
 962             VIASETREG(0x440, (CARD32) i << 24);
 963         }
 964
 965         VIASETREG(0x43C, 0x00020000);
 966
 967         for (i = 0; i <= 0x94; i++)
 968         {
 969             VIASETREG(0x440, (CARD32) i << 24);
 970         }
 971
 972         VIASETREG(0x440, 0x82400000);
 973
 974         VIASETREG(0x43C, 0x01020000);
 975
 976
 977         for (i = 0; i <= 0x94; i++)
 978         {
 979             VIASETREG(0x440, (CARD32) i << 24);
 980         }
 981
 982         VIASETREG(0x440, 0x82400000);
 983         VIASETREG(0x43C, 0xfe020000);
 984
 985         for (i = 0; i <= 0x03; i++)
 986         {
 987             VIASETREG(0x440, (CARD32) i << 24);
 988         }
 989
 990         VIASETREG(0x43C, 0x00030000);
 991
 992         for (i = 0; i <= 0xff; i++)
 993         {
 994             VIASETREG(0x440, 0);
 995         }
 996         VIASETREG(0x43C, 0x00100000);
 997         VIASETREG(0x440, 0x00333004);
 998         VIASETREG(0x440, 0x10000002);
 999         VIASETREG(0x440, 0x60000000);
1000         VIASETREG(0x440, 0x61000000);
1001         VIASETREG(0x440, 0x62000000);
1002         VIASETREG(0x440, 0x63000000);
1003         VIASETREG(0x440, 0x64000000);
1004
1005         VIASETREG(0x43C, 0x00fe0000);
1006
1007         if (pVia->ChipRev >= 3 )
1008             VIASETREG(0x440,0x40008c0f);
1009         else
1010             VIASETREG(0x440,0x4000800f);
1011
1012         VIASETREG(0x440,0x44000000);
1013         VIASETREG(0x440,0x45080C04);
1014         VIASETREG(0x440,0x46800408);
1015         VIASETREG(0x440,0x50000000);
1016         VIASETREG(0x440,0x51000000);
1017         VIASETREG(0x440,0x52000000);
1018         VIASETREG(0x440,0x53000000);
1019
1020         b3DRegsInitialized = 1;
1021         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1022                    "3D Engine has been initialized.\n");
1023     }
1024
1025     VIASETREG(0x43C,0x00fe0000);
1026     VIASETREG(0x440,0x08000001);
1027     VIASETREG(0x440,0x0A000183);
1028     VIASETREG(0x440,0x0B00019F);
1029     VIASETREG(0x440,0x0C00018B);
1030     VIASETREG(0x440,0x0D00019B);
1031     VIASETREG(0x440,0x0E000000);
1032     VIASETREG(0x440,0x0F000000);
1033     VIASETREG(0x440,0x10000000);
1034     VIASETREG(0x440,0x11000000);
1035     VIASETREG(0x440,0x20000000);
1036 }
1037
1038 static int
1039 WaitIdleCLE266(VIAPtr pVia)
1040 {
1041     int loop = 0;
1042
1043     /*mem_barrier();*/
1044
1045     while (!(VIAGETREG(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
1046         ;
1047
1048     while ((VIAGETREG(VIA_REG_STATUS) &
1049           (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
1050           (loop++ < MAXLOOP))
1051         ;
1052
1053     return loop >= MAXLOOP;
1054 }
1055
1056 static int viaInitFBDev(DRIDriverContext *ctx)
1057 {
1058     VIAPtr pVia = CALLOC(sizeof(*pVia));
1059
1060     ctx->driverPrivate = (void *)pVia;
1061
1062     switch (ctx->chipset) {
1063     case PCI_CHIP_CLE3122:
1064     case PCI_CHIP_CLE3022:
1065         pVia->Chipset = VIA_CLE266;
1066         break;
1067     case PCI_CHIP_VT7205:
1068     case PCI_CHIP_VT3205:
1069         pVia->Chipset = VIA_KM400;
1070         break;
1071     case PCI_CHIP_VT3204:
1072         pVia->Chipset = VIA_K8M800;
1073         break;
1074     case PCI_CHIP_VT3259:
1075         pVia->Chipset = VIA_PM800;
1076         break;
1077     default:
1078         xf86DrvMsg(0, X_ERROR, "VIA: Unknown device ID (0x%x)\n", ctx->chipset);
1079     }
1080
1081     /* _SOLO TODO XXX need to read ChipRev too */
1082     pVia->ChipRev = 0;
1083
1084     pVia->videoRambytes = ctx->shared.fbSize;
1085     pVia->MmioBase = ctx->MMIOStart;
1086     pVia->FrameBufferBase = ctx->FBStart & 0xfc000000;
1087
1088     pVia->FBFreeStart = ctx->shared.virtualWidth * ctx->cpp *
1089         ctx->shared.virtualHeight;
1090     pVia->FBFreeEnd = pVia->videoRambytes;
1091
1092     if (!VIADRIScreenInit(ctx))
1093         return 0;
1094
1095     VIAEnableMMIO(ctx);
1096
1097     /* Get video memory clock. */
1098     VGAOUT8(0x3D4, 0x3D);
1099     pVia->MemClk = (VGAIN8(0x3D5) & 0xF0) >> 4;
1100     xf86DrvMsg(0, X_INFO, "[dri] MemClk (0x%x)\n", pVia->MemClk);
1101
1102     /* 3D rendering has noise if not enabled. */
1103     VIAEnableExtendedFIFO(ctx);
1104
1105     VIAInitialize2DEngine(ctx);
1106
1107     /* Must disable MMIO or 3D won't work. */
1108     VIADisableMMIO(ctx);
1109
1110     VIAInitialize3DEngine(ctx);
1111
1112     return 1;
1113 }
1114
1115 static void viaHaltFBDev(DRIDriverContext *ctx)
1116 {
1117     drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
1118     drmClose(ctx->drmFD);
1119
1120     if (ctx->driverPrivate) {
1121         free(ctx->driverPrivate);
1122         ctx->driverPrivate = 0;
1123     }
1124 }
1125
1126 static int viaEngineShutdown(const DRIDriverContext *ctx)
1127 {
1128     return 1;
1129 }
1130
1131 static int viaEngineRestore(const DRIDriverContext *ctx)
1132 {
1133     return 1;
1134 }
1135
1136 const struct DRIDriverRec __driDriver =
1137 {
1138     viaInitContextModes,
1139     viaValidateMode,
1140     viaPostValidateMode,
1141     viaInitFBDev,
1142     viaHaltFBDev,
1143     viaEngineShutdown,
1144     viaEngineRestore,
1145     0,
1146 };
1147