src/mesa/drivers/dri/unichrome/via_common.h

   1 /*
   2  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef _VIA_DRM_H_
  25 #define _VIA_DRM_H_
  26
  27 /* WARNING: These defines must be the same as what the Xserver uses.
  28  * if you change them, you must change the defines in the Xserver.
  29  */
  30
  31 #ifndef _VIA_DEFINES_
  32 #define _VIA_DEFINES_
  33
  34 #define VIA_DMA_BUF_ORDER               12
  35 #define VIA_DMA_BUF_SZ                  (1 << VIA_DMA_BUF_ORDER)
  36 #define VIA_DMA_BUF_NR                  256
  37 #define VIA_NR_SAREA_CLIPRECTS          8
  38 #define VIA_NR_XVMC_PORTS               10
  39 #define VIA_NR_XVMC_LOCKS               5
  40 #define VIA_MAX_CACHELINE_SIZE          64
  41 #define XVMCLOCKPTR(saPriv,lockNo)                                      \
  42         ((volatile int *)(((((unsigned long) (saPriv)->XvMCLockArea) +  \
  43                             (VIA_MAX_CACHELINE_SIZE - 1)) &             \
  44                            ~(VIA_MAX_CACHELINE_SIZE - 1)) +             \
  45                           VIA_MAX_CACHELINE_SIZE*(lockNo)))
  46
  47 /* Each region is a minimum of 64k, and there are at most 64 of them.
  48  */
  49 #define VIA_NR_TEX_REGIONS 64
  50 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
  51 #endif
  52
  53 #define VIA_UPLOAD_TEX0IMAGE  0x1       /* handled clientside */
  54 #define VIA_UPLOAD_TEX1IMAGE  0x2       /* handled clientside */
  55 #define VIA_UPLOAD_CTX        0x4
  56 #define VIA_UPLOAD_BUFFERS    0x8
  57 #define VIA_UPLOAD_TEX0       0x10
  58 #define VIA_UPLOAD_TEX1       0x20
  59 #define VIA_UPLOAD_CLIPRECTS  0x40
  60 #define VIA_UPLOAD_ALL        0xff
  61
  62 /* VIA specific ioctls */
  63 #define DRM_VIA_ALLOCMEM        0x00
  64 #define DRM_VIA_FREEMEM         0x01
  65 #define DRM_VIA_AGP_INIT        0x02
  66 #define DRM_VIA_FB_INIT         0x03
  67 #define DRM_VIA_MAP_INIT        0x04
  68 #define DRM_VIA_DEC_FUTEX       0x05
  69 #define NOT_USED
  70 #define DRM_VIA_DMA_INIT        0x07
  71 #define DRM_VIA_CMDBUFFER       0x08
  72 #define DRM_VIA_FLUSH           0x09
  73 #define DRM_VIA_PCICMD          0x0a
  74 #define DRM_VIA_CMDBUF_SIZE     0x0b
  75
  76 #define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
  77 #define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
  78 #define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
  79 #define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
  80 #define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
  81 #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
  82 #define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
  83 #define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
  84 #define DRM_IOCTL_VIA_FLUSH       DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
  85 #define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
  86 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
  87                                             drm_via_cmdbuf_size_t)
  88
  89 /* Indices into buf.Setup where various bits of state are mirrored per
  90  * context and per buffer.  These can be fired at the card as a unit,
  91  * or in a piecewise fashion as required.
  92  */
  93
  94 #define VIA_TEX_SETUP_SIZE 8
  95
  96 /* Flags for clear ioctl
  97  */
  98 #define VIA_FRONT   0x1
  99 #define VIA_BACK    0x2
 100 #define VIA_DEPTH   0x4
 101 #define VIA_STENCIL 0x8
 102 #define VIDEO 0
 103 #define AGP 1
 104 typedef struct {
 105         u_int32_t offset;
 106         u_int32_t size;
 107 } drm_via_agp_t;
 108
 109 typedef struct {
 110         u_int32_t offset;
 111         u_int32_t size;
 112 } drm_via_fb_t;
 113
 114 typedef struct {
 115         u_int32_t context;
 116         u_int32_t type;
 117         u_int32_t size;
 118         unsigned long index;
 119         unsigned long offset;
 120 } drm_via_mem_t;
 121
 122 typedef struct _drm_via_init {
 123         enum {
 124                 VIA_INIT_MAP = 0x01,
 125                 VIA_CLEANUP_MAP = 0x02
 126         } func;
 127
 128         unsigned long sarea_priv_offset;
 129         unsigned long fb_offset;
 130         unsigned long mmio_offset;
 131         unsigned long agpAddr;
 132 } drm_via_init_t;
 133
 134 typedef struct _drm_via_futex {
 135         enum {
 136                 VIA_FUTEX_WAIT = 0x00,
 137                 VIA_FUTEX_WAKE = 0X01
 138         } func;
 139         u_int32_t ms;
 140         u_int32_t lock;
 141         u_int32_t val;
 142 } drm_via_futex_t;
 143
 144 typedef struct _drm_via_dma_init {
 145         enum {
 146                 VIA_INIT_DMA = 0x01,
 147                 VIA_CLEANUP_DMA = 0x02,
 148                 VIA_DMA_INITIALIZED = 0x03
 149         } func;
 150
 151         unsigned long offset;
 152         unsigned long size;
 153         unsigned long reg_pause_addr;
 154 } drm_via_dma_init_t;
 155
 156 typedef struct _drm_via_cmdbuffer {
 157         char *buf;
 158         unsigned long size;
 159 } drm_via_cmdbuffer_t;
 160
 161 /* Warning: If you change the SAREA structure you must change the Xserver
 162  * structure as well */
 163
 164 typedef struct _drm_via_tex_region {
 165         unsigned char next, prev;       /* indices to form a circular LRU  */
 166         unsigned char inUse;    /* owned by a client, or free? */
 167         int age;                /* tracked by clients to update local LRU's */
 168 } drm_via_tex_region_t;
 169
 170 typedef struct _drm_via_sarea {
 171         unsigned int dirty;
 172         unsigned int nbox;
 173         drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
 174         drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 175         int texAge;             /* last time texture was uploaded */
 176         int ctxOwner;           /* last context to upload state */
 177         int vertexPrim;
 178
 179         /*
 180          * Below is for XvMC.
 181          * We want the lock integers alone on, and aligned to, a cache line.
 182          * Therefore this somewhat strange construct.
 183          */
 184
 185         char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 186
 187         unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
 188         unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
 189         unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
 190
 191 } drm_via_sarea_t;
 192
 193 typedef struct _drm_via_cmdbuf_size {
 194         enum {
 195                 VIA_CMDBUF_SPACE = 0x01,
 196                 VIA_CMDBUF_LAG = 0x02
 197         } func;
 198         int wait;
 199         u_int32_t size;
 200 } drm_via_cmdbuf_size_t;
 201
 202
 203 #ifdef __KERNEL__
 204
 205 int via_fb_init(DRM_IOCTL_ARGS);
 206 int via_mem_alloc(DRM_IOCTL_ARGS);
 207 int via_mem_free(DRM_IOCTL_ARGS);
 208 int via_agp_init(DRM_IOCTL_ARGS);
 209 int via_map_init(DRM_IOCTL_ARGS);
 210 int via_decoder_futex(DRM_IOCTL_ARGS);
 211 int via_dma_init(DRM_IOCTL_ARGS);
 212 int via_cmdbuffer(DRM_IOCTL_ARGS);
 213 int via_flush_ioctl(DRM_IOCTL_ARGS);
 214 int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
 215 int via_cmdbuf_size(DRM_IOCTL_ARGS);
 216
 217 #endif
 218 #endif                          /* _VIA_DRM_H_ */