new X86 CPU detection code (Petr Sebor)
[mesa.git] / src / mesa / main / nvfragprog.h
1 /* $Id: nvfragprog.h,v 1.1 2003/01/14 04:55:46 brianp Exp $ */
2
3 /*
4 * Mesa 3-D graphics library
5 * Version: 5.1
6 *
7 * Copyright (C) 1999-2003 Brian Paul All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included
17 * in all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
23 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27
28 /* Private vertex program types and constants only used by files
29 * related to vertex programs.
30 */
31
32
33 #ifndef NVFRAGPROG_H
34 #define NVFRAGPROG_H
35
36 #include "config.h"
37
38
39 /* Location of register sets within the whole register file */
40 #define FP_INPUT_REG_START 0
41 #define FP_INPUT_REG_END (FP_INPUT_REG_START + MAX_NV_FRAGMENT_PROGRAM_INPUTS - 1)
42 #define FP_OUTPUT_REG_START (FP_INPUT_REG_END + 1)
43 #define FP_OUTPUT_REG_END (FP_OUTPUT_REG_START + MAX_NV_FRAGMENT_PROGRAM_OUTPUTS - 1)
44 #define FP_TEMP_REG_START (FP_OUTPUT_REG_END + 1)
45 #define FP_TEMP_REG_END (FP_TEMP_REG_START + MAX_NV_FRAGMENT_PROGRAM_TEMPS - 1)
46 #define FP_PROG_REG_START (FP_TEMP_REG_END + 1)
47 #define FP_PROG_REG_END (FP_PROG_REG_START + MAX_NV_FRAGMENT_PROGRAM_PARAMS - 1)
48 #define FP_DUMMY_REG_START (FP_PROG_REG_END + 1)
49 #define FP_DUMMY_REG_END (FP_DUMMY_REG_START + MAX_NV_FRAGMENT_PROGRAM_WRITE_ONLYS - 1)
50
51
52
53 #define COND_GT 1 /* greater than zero */
54 #define COND_EQ 2 /* equal to zero */
55 #define COND_LT 3 /* less than zero */
56 #define COND_UN 4 /* unordered (NaN) */
57 #define COND_GE 5 /* greater then or equal to zero */
58 #define COND_LE 6 /* less then or equal to zero */
59 #define COND_NE 7 /* not equal to zero */
60 #define COND_TR 8 /* always true */
61 #define COND_FL 9 /* always false */
62
63
64 enum fp_opcode {
65 FP_OPCODE_ADD = 1000,
66 FP_OPCODE_COS,
67 FP_OPCODE_DDX,
68 FP_OPCODE_DDY,
69 FP_OPCODE_DP3,
70 FP_OPCODE_DP4,
71 FP_OPCODE_DST,
72 FP_OPCODE_EX2,
73 FP_OPCODE_FLR,
74 FP_OPCODE_FRC,
75 FP_OPCODE_KIL,
76 FP_OPCODE_LG2,
77 FP_OPCODE_LIT,
78 FP_OPCODE_LRP,
79 FP_OPCODE_MAD,
80 FP_OPCODE_MAX,
81 FP_OPCODE_MIN,
82 FP_OPCODE_MOV,
83 FP_OPCODE_MUL,
84 FP_OPCODE_PK2H,
85 FP_OPCODE_PK2US,
86 FP_OPCODE_PK4B,
87 FP_OPCODE_PK4UB,
88 FP_OPCODE_POW,
89 FP_OPCODE_RCP,
90 FP_OPCODE_RFL,
91 FP_OPCODE_RSQ,
92 FP_OPCODE_SEQ,
93 FP_OPCODE_SFL,
94 FP_OPCODE_SGE,
95 FP_OPCODE_SGT,
96 FP_OPCODE_SIN,
97 FP_OPCODE_SLE,
98 FP_OPCODE_SLT,
99 FP_OPCODE_SNE,
100 FP_OPCODE_STR,
101 FP_OPCODE_SUB,
102 FP_OPCODE_TEX,
103 FP_OPCODE_TXC,
104 FP_OPCODE_TXP,
105 FP_OPCODE_UP2H,
106 FP_OPCODE_UP2US,
107 FP_OPCODE_UP4B,
108 FP_OPCODE_UP4UB,
109 FP_OPCODE_X2D,
110 FP_OPCODE_END /* private opcode */
111 };
112
113
114 struct fp_src_register
115 {
116 GLint RegType; /* constant, param, temp or attribute register */
117 GLint Register; /* or the offset from the address register */
118 GLuint Swizzle[4];
119 GLboolean NegateBase; /* negate before absolute value? */
120 GLboolean Abs; /* take absolute value? */
121 GLboolean NegateAbs; /* negate after absolute value? */
122 };
123
124
125 /* Instruction destination register */
126 struct fp_dst_register
127 {
128 GLint Register;
129 GLboolean WriteMask[4];
130 GLuint CondMask;
131 GLuint CondSwizzle[4];
132 };
133
134
135 struct fp_instruction
136 {
137 enum fp_opcode Opcode;
138 struct fp_src_register SrcReg[3];
139 struct fp_dst_register DstReg;
140 GLboolean Saturate;
141 GLboolean UpdateCondRegister;
142 GLuint Precision; /* SINGLE, HALF or FIXED */
143 GLuint TexSrcUnit; /* texture unit for TEX, TXD, TXP instructions */
144 GLenum TexSrcTarget; /* texture target for TEX, TXD, TXP instructions */
145 };
146
147
148
149 #endif