src/mesa/pipe/i915simple/i915_state_emit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "i915_reg.h"
  30 #include "i915_context.h"
  31 #include "i915_winsys.h"
  32 #include "i915_batch.h"
  33 #include "i915_reg.h"
  34
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_defines.h"
  37
  38 static unsigned translate_format( unsigned format )
  39 {
  40    switch (format) {
  41    case PIPE_FORMAT_U_A8_R8_G8_B8:
  42       return COLOR_BUF_ARGB8888;
  43    case PIPE_FORMAT_U_R5_G6_B5:
  44       return COLOR_BUF_RGB565;
  45    default:
  46       assert(0);
  47       return 0;
  48    }
  49 }
  50
  51 static unsigned translate_depth_format( unsigned zformat )
  52 {
  53    assert(zformat == PIPE_FORMAT_S8_Z24);
  54    return DEPTH_FRMT_24_FIXED_8_OTHER;
  55 }
  56
  57
  58 /* Push the state into the sarea and/or texture memory.
  59  */
  60 void
  61 i915_emit_hardware_state(struct i915_context *i915 )
  62 {
  63    BEGIN_BATCH(100, 10);
  64
  65    if (i915->hardware_dirty & I915_HW_INVARIENT)
  66    {
  67       OUT_BATCH(_3DSTATE_AA_CMD |
  68                 AA_LINE_ECAAR_WIDTH_ENABLE |
  69                 AA_LINE_ECAAR_WIDTH_1_0 |
  70                 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
  71
  72       OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
  73       OUT_BATCH(0);
  74
  75       OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
  76       OUT_BATCH(0);
  77
  78       OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
  79       OUT_BATCH(0);
  80
  81       OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
  82                 CSB_TCB(0, 0) |
  83                 CSB_TCB(1, 1) |
  84                 CSB_TCB(2, 2) |
  85                 CSB_TCB(3, 3) |
  86                 CSB_TCB(4, 4) |
  87                 CSB_TCB(5, 5) |
  88                 CSB_TCB(6, 6) |
  89                 CSB_TCB(7, 7));
  90
  91       OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
  92                 ENABLE_POINT_RASTER_RULE |
  93                 OGL_POINT_RASTER_RULE |
  94                 ENABLE_LINE_STRIP_PROVOKE_VRTX |
  95                 ENABLE_TRI_FAN_PROVOKE_VRTX |
  96                 LINE_STRIP_PROVOKE_VRTX(1) |
  97                 TRI_FAN_PROVOKE_VRTX(2) |
  98                 ENABLE_TEXKILL_3D_4D |
  99                 TEXKILL_4D);
 100
 101       /* Need to initialize this to zero.
 102        */
 103       OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 104       OUT_BATCH(0);
 105
 106       OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 107
 108       /* disable indirect state for now
 109        */
 110       OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);
 111       OUT_BATCH(0);
 112    }
 113
 114
 115    if (i915->hardware_dirty & I915_HW_IMMEDIATE)
 116    {
 117       OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
 118                 I1_LOAD_S(2) |
 119                 I1_LOAD_S(4) |
 120                 I1_LOAD_S(5) |
 121                 I1_LOAD_S(6) |
 122                 (3));
 123
 124       OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S2]);
 125       OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S4]);
 126       OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S5]);
 127       OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S6]);
 128    }
 129
 130
 131    if (i915->hardware_dirty & I915_HW_DYNAMIC)
 132    {
 133       int i;
 134       for (i = 0; i < I915_MAX_DYNAMIC; i++) {
 135          OUT_BATCH(i915->current.dynamic[i]);
 136       }
 137    }
 138
 139    if (i915->hardware_dirty & I915_HW_STATIC)
 140    {
 141       if (i915->framebuffer.cbufs[0]) {
 142          struct pipe_region *cbuf_region = i915->framebuffer.cbufs[0]->region;
 143          unsigned pitch = (cbuf_region->pitch *
 144                            cbuf_region->cpp);
 145
 146          OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
 147
 148          OUT_BATCH(BUF_3D_ID_COLOR_BACK |
 149                    BUF_3D_PITCH(pitch) |  /* pitch in bytes */
 150                    BUF_3D_USE_FENCE);
 151
 152          OUT_RELOC(cbuf_region->buffer,
 153                    I915_BUFFER_ACCESS_WRITE,
 154                    0);
 155       }
 156
 157       /* What happens if no zbuf??
 158        */
 159       if (i915->framebuffer.zbuf) {
 160          struct pipe_region *depth_region = i915->framebuffer.zbuf->region;
 161          unsigned zpitch = (depth_region->pitch *
 162                             depth_region->cpp);
 163
 164          OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
 165
 166          OUT_BATCH(BUF_3D_ID_DEPTH |
 167                    BUF_3D_PITCH(zpitch) |  /* pitch in bytes */
 168                    BUF_3D_USE_FENCE);
 169
 170          OUT_RELOC(depth_region->buffer,
 171                    I915_BUFFER_ACCESS_WRITE,
 172                    0);
 173       }
 174
 175       {
 176          unsigned cformat = translate_format( i915->framebuffer.cbufs[0]->format );
 177          unsigned zformat = 0;
 178
 179          if (i915->framebuffer.zbuf)
 180             zformat = translate_depth_format( i915->framebuffer.zbuf->format );
 181
 182          OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
 183          OUT_BATCH(DSTORG_HORT_BIAS(0x8) | /* .5 */
 184                    DSTORG_VERT_BIAS(0x8) | /* .5 */
 185                    LOD_PRECLAMP_OGL |
 186                    TEX_DEFAULT_COLOR_OGL |
 187                    cformat |
 188                    zformat );
 189       }
 190    }
 191
 192
 193 #if 01
 194       /* texture images */
 195       if (i915->hardware_dirty & (I915_HW_MAP | I915_HW_SAMPLER))
 196       {
 197          /* XXX: we were refering to sampler state
 198           * (current.sampler_enable_nr) below, but only checking
 199           * I915_HW_MAP above.  Should probably calculate the enabled
 200           * flags separately - but there will be further rework of
 201           * state so perhaps not necessary yet.
 202           */
 203          const uint nr = i915->current.sampler_enable_nr;
 204          if (nr) {
 205             const uint enabled = i915->current.sampler_enable_flags;
 206             uint unit;
 207             uint count = 0;
 208             OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 209             OUT_BATCH(enabled);
 210             for (unit = 0; unit < I915_TEX_UNITS; unit++) {
 211                if (enabled & (1 << unit)) {
 212                   struct pipe_buffer_handle *buf =
 213                      i915->texture[unit]->region->buffer;
 214                   uint offset = 0;
 215                   assert(buf);
 216
 217                   count++;
 218
 219                   OUT_RELOC(buf,
 220                             I915_BUFFER_ACCESS_READ,
 221                             offset);
 222                   OUT_BATCH(i915->current.texbuffer[unit][0]); /* MS3 */
 223                   OUT_BATCH(i915->current.texbuffer[unit][1]); /* MS4 */
 224                }
 225             }
 226             assert(count == nr);
 227          }
 228       }
 229 #endif
 230
 231 #if 01
 232    /* samplers */
 233    if (i915->hardware_dirty & I915_HW_SAMPLER)
 234    {
 235       if (i915->current.sampler_enable_nr) {
 236          int i;
 237
 238          OUT_BATCH( _3DSTATE_SAMPLER_STATE |
 239                     (3 * i915->current.sampler_enable_nr) );
 240
 241          OUT_BATCH( i915->current.sampler_enable_flags );
 242
 243          for (i = 0; i < I915_TEX_UNITS; i++) {
 244             if (i915->current.sampler_enable_flags & (1<<i)) {
 245                OUT_BATCH( i915->current.sampler[i][0] );
 246                OUT_BATCH( i915->current.sampler[i][1] );
 247                OUT_BATCH( i915->current.sampler[i][2] );
 248             }
 249          }
 250       }
 251    }
 252 #endif
 253
 254    /* constants */
 255    if (i915->hardware_dirty & I915_HW_PROGRAM)
 256    {
 257       const uint nr = i915->current.num_constants[PIPE_SHADER_FRAGMENT];
 258       assert(nr <= I915_MAX_CONSTANT);
 259       if (nr > 0) {
 260          const uint *c
 261             = (const uint *) i915->current.constants[PIPE_SHADER_FRAGMENT];
 262          uint i;
 263          OUT_BATCH( _3DSTATE_PIXEL_SHADER_CONSTANTS | (nr * 4) );
 264          OUT_BATCH( (1 << (nr - 1)) | ((1 << (nr - 1)) - 1) );
 265          for (i = 0; i < nr; i++) {
 266             OUT_BATCH(*c++);
 267             OUT_BATCH(*c++);
 268             OUT_BATCH(*c++);
 269             OUT_BATCH(*c++);
 270          }
 271       }
 272    }
 273
 274    /* Fragment program */
 275    if (i915->hardware_dirty & I915_HW_PROGRAM)
 276    {
 277       uint i;
 278       /* we should always have, at least, a pass-through program */
 279       assert(i915->current.program_len > 0);
 280       for (i = 0; i < i915->current.program_len; i++) {
 281          OUT_BATCH(i915->current.program[i]);
 282       }
 283    }
 284
 285    /* drawing surface size */
 286    {
 287       int w = i915->framebuffer.cbufs[0]->width;
 288       int h = i915->framebuffer.cbufs[0]->height;
 289
 290       OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
 291       OUT_BATCH(0);
 292       OUT_BATCH(0);
 293       OUT_BATCH(((w - 1) & 0xffff) | ((h - 1) << 16));
 294       OUT_BATCH(0);
 295       OUT_BATCH(0);
 296    }
 297
 298
 299    i915->hardware_dirty = 0;
 300 }
 301