src/mesa/pipe/i965simple/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35
  36 static unsigned translate_tex_target( int target )
  37 {
  38    switch (target) {
  39    case PIPE_TEXTURE_1D:
  40       return BRW_SURFACE_1D;
  41
  42    case PIPE_TEXTURE_2D:
  43       return BRW_SURFACE_2D;
  44
  45    case PIPE_TEXTURE_3D:
  46       return BRW_SURFACE_3D;
  47
  48    case PIPE_TEXTURE_CUBE:
  49       return BRW_SURFACE_CUBE;
  50
  51    default:
  52       assert(0);
  53       return 0;
  54    }
  55 }
  56
  57 static unsigned translate_tex_format( unsigned mesa_format )
  58 {
  59    switch( mesa_format ) {
  60    case PIPE_FORMAT_U_L8:
  61       return BRW_SURFACEFORMAT_L8_UNORM;
  62
  63    case PIPE_FORMAT_U_I8:
  64       return BRW_SURFACEFORMAT_I8_UNORM;
  65
  66    case PIPE_FORMAT_U_A8:
  67       return BRW_SURFACEFORMAT_A8_UNORM;
  68
  69    case PIPE_FORMAT_U_A8_L8:
  70       return BRW_SURFACEFORMAT_L8A8_UNORM;
  71
  72    case PIPE_FORMAT_R8G8B8_UNORM:
  73       assert(0);                /* not supported for sampling */
  74       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  75
  76    case PIPE_FORMAT_B8G8R8A8_UNORM:
  77       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  78
  79    case PIPE_FORMAT_R8G8B8A8_UNORM:
  80       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
  81
  82    case PIPE_FORMAT_R5G6B5_UNORM:
  83       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
  84
  85    case PIPE_FORMAT_A1R5G5B5_UNORM:
  86       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
  87
  88    case PIPE_FORMAT_A4R4G4B4_UNORM:
  89       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
  90
  91    case PIPE_FORMAT_YCBCR_REV:
  92       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
  93
  94    case PIPE_FORMAT_YCBCR:
  95       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
  96 #if 0
  97    case PIPE_FORMAT_RGB_FXT1:
  98    case PIPE_FORMAT_RGBA_FXT1:
  99       return BRW_SURFACEFORMAT_FXT1;
 100 #endif
 101
 102    case PIPE_FORMAT_Z16_UNORM:
 103       return BRW_SURFACEFORMAT_I16_UNORM;
 104 #if 0
 105    case PIPE_FORMAT_RGB_DXT1:
 106        return BRW_SURFACEFORMAT_DXT1_RGB;
 107
 108    case PIPE_FORMAT_RGBA_DXT1:
 109        return BRW_SURFACEFORMAT_BC1_UNORM;
 110
 111    case PIPE_FORMAT_RGBA_DXT3:
 112        return BRW_SURFACEFORMAT_BC2_UNORM;
 113
 114    case PIPE_FORMAT_RGBA_DXT5:
 115        return BRW_SURFACEFORMAT_BC3_UNORM;
 116
 117    case PIPE_FORMAT_SRGBA8:
 118       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
 119    case PIPE_FORMAT_SRGB_DXT1:
 120       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 121 #endif
 122
 123    default:
 124       assert(0);
 125       return 0;
 126    }
 127 }
 128
 129 static unsigned brw_buffer_offset(struct brw_context *brw,
 130                                   struct pipe_buffer_handle *buffer)
 131 {
 132    return brw->winsys->get_buffer_offset(brw->winsys,
 133                                          buffer,
 134                                          0);
 135 }
 136
 137 static
 138 void brw_update_texture_surface( struct brw_context *brw,
 139                                  unsigned unit )
 140 {
 141    const struct brw_texture *tObj = brw->attribs.Texture[unit];
 142    struct brw_surface_state surf;
 143
 144    memset(&surf, 0, sizeof(surf));
 145
 146    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 147    surf.ss0.surface_type = translate_tex_target(tObj->base.target);
 148    surf.ss0.surface_format = translate_tex_format(tObj->base.format);
 149
 150    /* This is ok for all textures with channel width 8bit or less:
 151     */
 152 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 153
 154    /* Updated in emit_reloc */
 155    surf.ss1.base_addr = brw_buffer_offset( brw, tObj->buffer );
 156
 157    surf.ss2.mip_count = tObj->base.last_level - tObj->base.first_level;
 158    surf.ss2.width = tObj->base.width[0];
 159    surf.ss2.height = tObj->base.height[0];
 160
 161    surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 162    surf.ss3.tiled_surface = 0; /* always zero */
 163    surf.ss3.pitch = tObj->pitch;
 164    surf.ss3.depth = tObj->base.depth[0];
 165
 166    surf.ss4.min_lod = 0;
 167
 168    if (tObj->base.target == PIPE_TEXTURE_CUBE) {
 169       surf.ss0.cube_pos_x = 1;
 170       surf.ss0.cube_pos_y = 1;
 171       surf.ss0.cube_pos_z = 1;
 172       surf.ss0.cube_neg_x = 1;
 173       surf.ss0.cube_neg_y = 1;
 174       surf.ss0.cube_neg_z = 1;
 175    }
 176
 177    brw->wm.bind.surf_ss_offset[unit + 1] =
 178       brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
 179 }
 180
 181
 182
 183 #define OFFSET(TYPE, FIELD) ( (unsigned)&(((TYPE *)0)->FIELD) )
 184
 185
 186 static void upload_wm_surfaces(struct brw_context *brw )
 187 {
 188    unsigned i;
 189
 190    {
 191       struct brw_surface_state surf;
 192
 193       /* BRW_NEW_FRAMEBUFFER
 194        */
 195       struct pipe_surface *region = brw->attribs.FrameBuffer.cbufs[0];/*fixme*/
 196
 197       memset(&surf, 0, sizeof(surf));
 198
 199       if (region != NULL) {
 200          if (region->cpp == 4)
 201             surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 202          else
 203             surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 204
 205          surf.ss0.surface_type = BRW_SURFACE_2D;
 206
 207          surf.ss1.base_addr = brw_buffer_offset( brw, region->buffer );
 208
 209          surf.ss2.width = region->width;
 210          surf.ss2.height = region->height;
 211          surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 212          surf.ss3.tiled_surface = 0;
 213          surf.ss3.pitch = region->pitch;
 214       } else {
 215          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 216          surf.ss0.surface_type = BRW_SURFACE_NULL;
 217       }
 218
 219       /* BRW_NEW_BLEND */
 220       surf.ss0.color_blend = (!brw->attribs.Blend->logicop_enable &&
 221                               brw->attribs.Blend->blend_enable);
 222
 223
 224       surf.ss0.writedisable_red =   !brw->attribs.BlendColor.color[0];
 225       surf.ss0.writedisable_green = !brw->attribs.BlendColor.color[1];
 226       surf.ss0.writedisable_blue =  !brw->attribs.BlendColor.color[2];
 227       surf.ss0.writedisable_alpha = !brw->attribs.BlendColor.color[3];
 228
 229
 230
 231
 232       brw->wm.bind.surf_ss_offset[0] = brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
 233
 234       brw->wm.nr_surfaces = 1;
 235    }
 236
 237
 238    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 239       const struct brw_texture *texUnit = brw->attribs.Texture[i];
 240       if (texUnit == NULL)
 241          continue;
 242
 243
 244       /* BRW_NEW_TEXTURE
 245        */
 246       if (texUnit->base.refcount/*(texUnit->refcount > 0) == really used */) {
 247
 248          brw_update_texture_surface(brw, i);
 249
 250          brw->wm.nr_surfaces = i+2;
 251       }
 252 #if 0
 253       else if( texUnit->refcount &&
 254                texUnit->_Current == intel->frame_buffer_texobj )
 255       {
 256          brw->wm.bind.surf_ss_offset[i+1] = brw->wm.bind.surf_ss_offset[0];
 257          brw->wm.nr_surfaces = i+2;
 258       }
 259 #endif
 260       else {
 261          brw->wm.bind.surf_ss_offset[i+1] = 0;
 262       }
 263    }
 264
 265    brw->wm.bind_ss_offset = brw_cache_data( &brw->cache[BRW_SS_SURF_BIND],
 266                                             &brw->wm.bind );
 267 }
 268
 269
 270 /* KW: Will find a different way to acheive this, see for example the
 271  * state caches with relocs in the i915 swz driver.
 272  */
 273 #if 0
 274 static void emit_reloc_wm_surfaces(struct brw_context *brw)
 275 {
 276    int unit;
 277
 278    if (brw->state.draw_region != NULL) {
 279       /* Emit framebuffer relocation */
 280       dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
 281                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
 282                      0,
 283                      brw->wm.bind.surf_ss_offset[0] +
 284                      offsetof(struct brw_surface_state, ss1),
 285                      brw->state.draw_region->buffer);
 286    }
 287
 288    /* Emit relocations for texture buffers */
 289    for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
 290       struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[unit];
 291       struct gl_texture_object *tObj = texUnit->_Current;
 292       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 293
 294       if (texUnit->_ReallyEnabled && intelObj->mt != NULL) {
 295          dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
 296                         DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 297                         0,
 298                         brw->wm.bind.surf_ss_offset[unit + 1] +
 299                         offsetof(struct brw_surface_state, ss1),
 300                         intelObj->mt->region->buffer);
 301       }
 302    }
 303 }
 304 #endif
 305
 306 const struct brw_tracked_state brw_wm_surfaces = {
 307    .dirty = {
 308       .brw = (BRW_NEW_FRAMEBUFFER |
 309               BRW_NEW_BLEND |
 310               BRW_NEW_TEXTURE),
 311       .cache = 0
 312    },
 313    .update = upload_wm_surfaces,
 314 };