src/mesa/pipe/i965simple/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35
  36
  37 #if 0
  38 static unsigned translate_tex_target( int target )
  39 {
  40    switch (target) {
  41    case PIPE_TEXTURE_1D:
  42       return BRW_SURFACE_1D;
  43
  44    case PIPE_TEXTURE_2D:
  45       return BRW_SURFACE_2D;
  46
  47    case PIPE_TEXTURE_3D:
  48       return BRW_SURFACE_3D;
  49
  50    case PIPE_TEXTURE_CUBE:
  51       return BRW_SURFACE_CUBE;
  52
  53    default:
  54       assert(0);
  55       return 0;
  56    }
  57 }
  58
  59 static unsigned translate_tex_format( unsigned mesa_format )
  60 {
  61    switch( mesa_format ) {
  62    case PIPE_FORMAT_U_L8:
  63       return BRW_SURFACEFORMAT_L8_UNORM;
  64
  65    case PIPE_FORMAT_U_I8:
  66       return BRW_SURFACEFORMAT_I8_UNORM;
  67
  68    case PIPE_FORMAT_U_A8:
  69       return BRW_SURFACEFORMAT_A8_UNORM;
  70
  71    case PIPE_FORMAT_U_A8_L8:
  72       return BRW_SURFACEFORMAT_L8A8_UNORM;
  73
  74    case PIPE_FORMAT_R8G8B8_UNORM:
  75       assert(0);                /* not supported for sampling */
  76       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  77
  78    case PIPE_FORMAT_U_A8_R8_G8_B8:
  79       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  80
  81    case PIPE_FORMAT_RGBA8888_REV:
  82       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
  83
  84    case PIPE_FORMAT_U_R5_G6_B5:
  85       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
  86
  87    case PIPE_FORMAT_A1R5G5B5_UNORM:
  88       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
  89
  90    case PIPE_FORMAT_A4R4G4B4_UNORM:
  91       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
  92
  93    case PIPE_FORMAT_YCBCR_REV:
  94       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
  95
  96    case PIPE_FORMAT_YCBCR:
  97       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
  98
  99    case PIPE_FORMAT_RGB_FXT1:
 100    case PIPE_FORMAT_RGBA_FXT1:
 101       return BRW_SURFACEFORMAT_FXT1;
 102
 103    case PIPE_FORMAT_Z16_UNORM:
 104       return BRW_SURFACEFORMAT_I16_UNORM;
 105
 106    case PIPE_FORMAT_RGB_DXT1:
 107        return BRW_SURFACEFORMAT_DXT1_RGB;
 108
 109    case PIPE_FORMAT_RGBA_DXT1:
 110        return BRW_SURFACEFORMAT_BC1_UNORM;
 111
 112    case PIPE_FORMAT_RGBA_DXT3:
 113        return BRW_SURFACEFORMAT_BC2_UNORM;
 114
 115    case PIPE_FORMAT_RGBA_DXT5:
 116        return BRW_SURFACEFORMAT_BC3_UNORM;
 117
 118    case PIPE_FORMAT_SRGBA8:
 119       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
 120    case PIPE_FORMAT_SRGB_DXT1:
 121       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 122
 123    default:
 124       assert(0);
 125       return 0;
 126    }
 127 }
 128
 129 static
 130 void brw_update_texture_surface( GLcontext *ctx,
 131                                  unsigned unit )
 132 {
 133    struct brw_context *brw = brw_context(ctx);
 134    struct gl_texture_object *tObj = brw->attribs.Texture->Unit[unit]._Current;
 135    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 136    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 137    struct brw_surface_state surf;
 138
 139    memset(&surf, 0, sizeof(surf));
 140
 141    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 142    surf.ss0.surface_type = translate_tex_target(tObj->Target);
 143    surf.ss0.surface_format = translate_tex_format(firstImage->TexFormat->MesaFormat);
 144
 145    /* This is ok for all textures with channel width 8bit or less:
 146     */
 147 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 148
 149    /* Updated in emit_reloc */
 150    surf.ss1.base_addr = intelObj->mt->region->buffer->offset;
 151
 152    surf.ss2.mip_count = intelObj->lastLevel - intelObj->firstLevel;
 153    surf.ss2.width = firstImage->Width - 1;
 154    surf.ss2.height = firstImage->Height - 1;
 155
 156    surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 157    surf.ss3.tiled_surface = intelObj->mt->region->tiled; /* always zero */
 158    surf.ss3.pitch = (intelObj->mt->pitch * intelObj->mt->cpp) - 1;
 159    surf.ss3.depth = firstImage->Depth - 1;
 160
 161    surf.ss4.min_lod = 0;
 162
 163    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
 164       surf.ss0.cube_pos_x = 1;
 165       surf.ss0.cube_pos_y = 1;
 166       surf.ss0.cube_pos_z = 1;
 167       surf.ss0.cube_neg_x = 1;
 168       surf.ss0.cube_neg_y = 1;
 169       surf.ss0.cube_neg_z = 1;
 170    }
 171
 172    brw->wm.bind.surf_ss_offset[unit + 1] =
 173       brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
 174 }
 175
 176
 177
 178 #define OFFSET(TYPE, FIELD) ( (unsigned)&(((TYPE *)0)->FIELD) )
 179
 180
 181 static void upload_wm_surfaces(struct brw_context *brw )
 182 {
 183    GLcontext *ctx = &brw->intel.ctx;
 184    struct intel_context *intel = &brw->intel;
 185    unsigned i;
 186
 187    {
 188       struct brw_surface_state surf;
 189       struct intel_region *region = brw->state.draw_region;
 190
 191       memset(&surf, 0, sizeof(surf));
 192
 193       if (region != NULL) {
 194          if (region->cpp == 4)
 195             surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 196          else
 197             surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 198
 199          surf.ss0.surface_type = BRW_SURFACE_2D;
 200
 201          surf.ss2.width = region->pitch - 1; /* XXX: not really! */
 202          surf.ss2.height = region->height - 1;
 203          surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 204          surf.ss3.tiled_surface = region->tiled;
 205          surf.ss3.pitch = (region->pitch * region->cpp) - 1;
 206       } else {
 207          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 208          surf.ss0.surface_type = BRW_SURFACE_NULL;
 209       }
 210
 211       /* _NEW_COLOR */
 212       surf.ss0.color_blend = (!brw->attribs.Color->_LogicOpEnabled &&
 213                               brw->attribs.Color->BlendEnabled);
 214
 215
 216       surf.ss0.writedisable_red =   !brw->attribs.Color->ColorMask[0];
 217       surf.ss0.writedisable_green = !brw->attribs.Color->ColorMask[1];
 218       surf.ss0.writedisable_blue =  !brw->attribs.Color->ColorMask[2];
 219       surf.ss0.writedisable_alpha = !brw->attribs.Color->ColorMask[3];
 220
 221       brw->wm.bind.surf_ss_offset[0] = brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
 222
 223       brw->wm.nr_surfaces = 1;
 224    }
 225
 226
 227    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 228       struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[i];
 229
 230       /* _NEW_TEXTURE, BRW_NEW_TEXDATA
 231        */
 232       if (texUnit->_ReallyEnabled &&
 233           intel_finalize_mipmap_tree(intel, i)) {
 234
 235          brw_update_texture_surface(ctx, i);
 236
 237          brw->wm.nr_surfaces = i+2;
 238       }
 239       else if( texUnit->_ReallyEnabled &&
 240                texUnit->_Current == intel->frame_buffer_texobj )
 241       {
 242          brw->wm.bind.surf_ss_offset[i+1] = brw->wm.bind.surf_ss_offset[0];
 243          brw->wm.nr_surfaces = i+2;
 244       }
 245       else {
 246          brw->wm.bind.surf_ss_offset[i+1] = 0;
 247       }
 248    }
 249
 250    brw->wm.bind_ss_offset = brw_cache_data( &brw->cache[BRW_SS_SURF_BIND],
 251                                             &brw->wm.bind );
 252 }
 253
 254 static void emit_reloc_wm_surfaces(struct brw_context *brw)
 255 {
 256    int unit;
 257
 258    if (brw->state.draw_region != NULL) {
 259       /* Emit framebuffer relocation */
 260       dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
 261                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
 262                      0,
 263                      brw->wm.bind.surf_ss_offset[0] +
 264                      offsetof(struct brw_surface_state, ss1),
 265                      brw->state.draw_region->buffer);
 266    }
 267
 268    /* Emit relocations for texture buffers */
 269    for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
 270       struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[unit];
 271       struct gl_texture_object *tObj = texUnit->_Current;
 272       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 273
 274       if (texUnit->_ReallyEnabled && intelObj->mt != NULL) {
 275          dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
 276                         DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 277                         0,
 278                         brw->wm.bind.surf_ss_offset[unit + 1] +
 279                         offsetof(struct brw_surface_state, ss1),
 280                         intelObj->mt->region->buffer);
 281       }
 282    }
 283 }
 284
 285 const struct brw_tracked_state brw_wm_surfaces = {
 286    .dirty = {
 287       .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
 288       .brw = BRW_NEW_CONTEXT,
 289       .cache = 0
 290    },
 291    .update = upload_wm_surfaces,
 292    .emit_reloc = emit_reloc_wm_surfaces,
 293 };
 294 #endif