1 #include "pipe/draw/draw_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_winsys.h"
4 #include "pipe/p_util.h"
6 #include "nv40_context.h"
10 nv40_is_format_supported(struct pipe_context
*pipe
, uint format
)
13 case PIPE_FORMAT_U_A8_R8_G8_B8
:
14 case PIPE_FORMAT_U_R5_G6_B5
:
15 case PIPE_FORMAT_Z24_S8
:
25 nv40_get_name(struct pipe_context
*pipe
)
27 struct nv40_context
*nv40
= (struct nv40_context
*)pipe
;
28 static char buffer
[128];
30 snprintf(buffer
, sizeof(buffer
), "NV%02X", nv40
->chipset
);
35 nv40_get_vendor(struct pipe_context
*pipe
)
41 nv40_get_param(struct pipe_context
*pipe
, int param
)
44 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
46 case PIPE_CAP_NPOT_TEXTURES
:
48 case PIPE_CAP_TWO_SIDED_STENCIL
:
54 case PIPE_CAP_ANISOTROPIC_FILTER
:
56 case PIPE_CAP_POINT_SPRITE
:
58 case PIPE_CAP_MAX_RENDER_TARGETS
:
60 case PIPE_CAP_OCCLUSION_QUERY
:
62 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
64 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
66 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
68 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
71 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
77 nv40_get_paramf(struct pipe_context
*pipe
, int param
)
80 case PIPE_CAP_MAX_LINE_WIDTH
:
81 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
83 case PIPE_CAP_MAX_POINT_WIDTH
:
84 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
86 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
88 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
91 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
97 nv40_flush(struct pipe_context
*pipe
, unsigned flags
)
99 struct nv40_context
*nv40
= (struct nv40_context
*)pipe
;
100 struct nouveau_winsys
*nvws
= nv40
->nvws
;
102 if (flags
& PIPE_FLUSH_TEXTURE_CACHE
) {
103 BEGIN_RING(curie
, 0x1fd8, 1);
105 BEGIN_RING(curie
, 0x1fd8, 1);
109 if (flags
& PIPE_FLUSH_WAIT
) {
110 nvws
->notifier_reset(nv40
->sync
, 0);
111 BEGIN_RING(curie
, 0x104, 1);
113 BEGIN_RING(curie
, 0x100, 1);
119 if (flags
& PIPE_FLUSH_WAIT
)
120 nvws
->notifier_wait(nv40
->sync
, 0, 0, 2000);
124 nv40_destroy(struct pipe_context
*pipe
)
126 struct nv40_context
*nv40
= (struct nv40_context
*)pipe
;
128 draw_destroy(nv40
->draw
);
133 nv40_init_hwctx(struct nv40_context
*nv40
, int curie_class
)
135 struct nouveau_winsys
*nvws
= nv40
->nvws
;
138 if ((ret
= nvws
->notifier_alloc(nvws
, nv40
->num_query_objects
,
140 NOUVEAU_ERR("Error creating query notifier objects: %d\n", ret
);
144 if ((ret
= nvws
->grobj_alloc(nvws
, curie_class
,
146 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
150 BEGIN_RING(curie
, NV40TCL_DMA_NOTIFY
, 1);
151 OUT_RING (nv40
->sync
->handle
);
152 BEGIN_RING(curie
, NV40TCL_DMA_TEXTURE0
, 2);
153 OUT_RING (nvws
->channel
->vram
->handle
);
154 OUT_RING (nvws
->channel
->gart
->handle
);
155 BEGIN_RING(curie
, NV40TCL_DMA_COLOR1
, 1);
156 OUT_RING (nvws
->channel
->vram
->handle
);
157 BEGIN_RING(curie
, NV40TCL_DMA_COLOR0
, 2);
158 OUT_RING (nvws
->channel
->vram
->handle
);
159 OUT_RING (nvws
->channel
->vram
->handle
);
160 BEGIN_RING(curie
, NV40TCL_DMA_VTXBUF0
, 2);
161 OUT_RING (nvws
->channel
->vram
->handle
);
162 OUT_RING (nvws
->channel
->gart
->handle
);
163 BEGIN_RING(curie
, NV40TCL_DMA_FENCE
, 2);
165 OUT_RING (nv40
->query
->handle
);
166 BEGIN_RING(curie
, NV40TCL_DMA_UNK01AC
, 2);
167 OUT_RING (nvws
->channel
->vram
->handle
);
168 OUT_RING (nvws
->channel
->vram
->handle
);
169 BEGIN_RING(curie
, NV40TCL_DMA_COLOR2
, 2);
170 OUT_RING (nvws
->channel
->vram
->handle
);
171 OUT_RING (nvws
->channel
->vram
->handle
);
173 BEGIN_RING(curie
, 0x1ea4, 3);
174 OUT_RING (0x00000010);
175 OUT_RING (0x01000100);
176 OUT_RING (0xff800006);
178 /* vtxprog output routing */
179 BEGIN_RING(curie
, 0x1fc4, 1);
180 OUT_RING (0x06144321);
181 BEGIN_RING(curie
, 0x1fc8, 2);
182 OUT_RING (0xedcba987);
183 OUT_RING (0x00000021);
184 BEGIN_RING(curie
, 0x1fd0, 1);
185 OUT_RING (0x00171615);
186 BEGIN_RING(curie
, 0x1fd4, 1);
187 OUT_RING (0x001b1a19);
189 BEGIN_RING(curie
, 0x1ef8, 1);
190 OUT_RING (0x0020ffff);
191 BEGIN_RING(curie
, 0x1d64, 1);
192 OUT_RING (0x00d30000);
193 BEGIN_RING(curie
, 0x1e94, 1);
194 OUT_RING (0x00000001);
200 #define GRCLASS4097_CHIPSETS 0x00000baf
201 #define GRCLASS4497_CHIPSETS 0x00005450
202 struct pipe_context
*
203 nv40_create(struct pipe_winsys
*pipe_winsys
, struct nouveau_winsys
*nvws
,
206 struct nv40_context
*nv40
;
207 int curie_class
, ret
;
209 if ((chipset
& 0xf0) != 0x40) {
210 NOUVEAU_ERR("Not a NV4X chipset\n");
214 if (GRCLASS4097_CHIPSETS
& (1 << (chipset
& 0x0f))) {
215 curie_class
= 0x4097;
217 if (GRCLASS4497_CHIPSETS
& (1 << (chipset
& 0x0f))) {
218 curie_class
= 0x4497;
220 NOUVEAU_ERR("Unknown NV4X chipset: NV%02x\n", chipset
);
224 nv40
= CALLOC_STRUCT(nv40_context
);
227 nv40
->chipset
= chipset
;
230 if ((ret
= nvws
->notifier_alloc(nvws
, 1, &nv40
->sync
))) {
231 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
236 nv40
->num_query_objects
= 32;
237 nv40
->query_objects
= calloc(nv40
->num_query_objects
,
238 sizeof(struct pipe_query_object
*));
239 if (!nv40
->query_objects
) {
244 if (!nv40_init_hwctx(nv40
, curie_class
)) {
249 nv40
->pipe
.winsys
= pipe_winsys
;
251 nv40
->pipe
.destroy
= nv40_destroy
;
252 nv40
->pipe
.is_format_supported
= nv40_is_format_supported
;
253 nv40
->pipe
.get_name
= nv40_get_name
;
254 nv40
->pipe
.get_vendor
= nv40_get_vendor
;
255 nv40
->pipe
.get_param
= nv40_get_param
;
256 nv40
->pipe
.get_paramf
= nv40_get_paramf
;
258 nv40
->pipe
.draw_arrays
= nv40_draw_arrays
;
259 nv40
->pipe
.draw_elements
= nv40_draw_elements
;
260 nv40
->pipe
.clear
= nv40_clear
;
262 nv40
->pipe
.begin_query
= nv40_query_begin
;
263 nv40
->pipe
.end_query
= nv40_query_end
;
264 nv40
->pipe
.wait_query
= nv40_query_wait
;
266 nv40
->pipe
.mipmap_tree_layout
= nv40_miptree_layout
;
268 nv40
->pipe
.flush
= nv40_flush
;
270 nv40_init_region_functions(nv40
);
271 nv40_init_surface_functions(nv40
);
272 nv40_init_state_functions(nv40
);
274 nv40
->draw
= draw_create();
276 draw_set_rasterize_stage(nv40
->draw
, nv40_draw_render_stage(nv40
));