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1d4cbb454d458dc44aca842262bb008a652329f8
[mesa.git] / src / mesa / pipe / nv40 / nv40_state.c
1 #include "pipe/p_state.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_util.h"
4
5 #include "nv40_context.h"
6 #include "nv40_dma.h"
7 #include "nv40_state.h"
8
9 static void *
10 nv40_alpha_test_state_create(struct pipe_context *pipe,
11 const struct pipe_alpha_test_state *cso)
12 {
13 struct nv40_alpha_test_state *at;
14
15 at = malloc(sizeof(struct nv40_alpha_test_state));
16
17 at->enabled = cso->enabled ? 1 : 0;
18 if (at->enabled) {
19 at->func = nvgl_comparison_op(cso->func);
20 at->ref = float_to_ubyte(cso->ref);
21 }
22
23 return (void *)at;
24 }
25
26 static void
27 nv40_alpha_test_state_bind(struct pipe_context *pipe, void *hwcso)
28 {
29 struct nv40_context *nv40 = (struct nv40_context *)pipe;
30 struct nv40_alpha_test_state *at = hwcso;
31
32 if (at->enabled) {
33 BEGIN_RING(curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
34 OUT_RING (at->enabled);
35 OUT_RING (at->func);
36 OUT_RING (at->ref);
37 } else {
38 BEGIN_RING(curie, NV40TCL_ALPHA_TEST_ENABLE, 1);
39 OUT_RING (0);
40 }
41 }
42
43 static void
44 nv40_alpha_test_state_delete(struct pipe_context *pipe, void *hwcso)
45 {
46 free(hwcso);
47 }
48
49 static void *
50 nv40_blend_state_create(struct pipe_context *pipe,
51 const struct pipe_blend_state *cso)
52 {
53 struct nv40_blend_state *cb;
54
55 cb = malloc(sizeof(struct nv40_blend_state));
56
57 cb->b_enable = cso->blend_enable ? 1 : 0;
58 if (cb->b_enable) {
59 cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) |
60 (nvgl_blend_func(cso->rgb_src_factor)));
61 cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) |
62 (nvgl_blend_func(cso->rgb_dst_factor)));
63 cb->b_eqn = ((nvgl_blend_eqn(cso->alpha_func) << 16) |
64 (nvgl_blend_eqn(cso->rgb_func)));
65 }
66
67 cb->l_enable = cso->logicop_enable ? 1 : 0;
68 if (cb->l_enable) {
69 cb->l_op = nvgl_logicop_func(cso->logicop_func);
70 }
71
72 cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) |
73 ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) |
74 ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) |
75 ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0));
76
77 cb->d_enable = cso->dither ? 1 : 0;
78
79 return (void *)cb;
80 }
81
82 static void
83 nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
84 {
85 struct nv40_context *nv40 = (struct nv40_context *)pipe;
86 struct nv40_blend_state *cb = hwcso;
87
88 BEGIN_RING(curie, NV40TCL_DITHER_ENABLE, 1);
89 OUT_RING (cb->d_enable);
90
91 if (cb->b_enable) {
92 BEGIN_RING(curie, NV40TCL_BLEND_ENABLE, 3);
93 OUT_RING (cb->b_enable);
94 OUT_RING (cb->b_srcfunc);
95 OUT_RING (cb->b_dstfunc);
96 BEGIN_RING(curie, NV40TCL_BLEND_EQUATION, 2);
97 OUT_RING (cb->b_eqn);
98 OUT_RING (cb->c_mask);
99 } else {
100 BEGIN_RING(curie, NV40TCL_BLEND_ENABLE, 1);
101 OUT_RING (0);
102 }
103
104 if (cb->l_enable) {
105 BEGIN_RING(curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
106 OUT_RING (cb->l_enable);
107 OUT_RING (cb->l_op);
108 } else {
109 BEGIN_RING(curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
110 OUT_RING (0);
111 }
112 }
113
114 static void
115 nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
116 {
117 free(hwcso);
118 }
119
120
121 static INLINE unsigned
122 wrap_mode(unsigned wrap) {
123 unsigned ret;
124
125 switch (wrap) {
126 case PIPE_TEX_WRAP_REPEAT:
127 ret = NV40TCL_TEX_WRAP_S_REPEAT;
128 break;
129 case PIPE_TEX_WRAP_MIRROR_REPEAT:
130 ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
131 break;
132 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
133 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
134 break;
135 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
136 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
137 break;
138 case PIPE_TEX_WRAP_CLAMP:
139 ret = NV40TCL_TEX_WRAP_S_CLAMP;
140 break;
141 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
142 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
143 break;
144 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
145 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
146 break;
147 case PIPE_TEX_WRAP_MIRROR_CLAMP:
148 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
149 break;
150 default:
151 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
152 ret = NV40TCL_TEX_WRAP_S_REPEAT;
153 break;
154 }
155
156 return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
157 }
158
159 static void *
160 nv40_sampler_state_create(struct pipe_context *pipe,
161 const struct pipe_sampler_state *cso)
162 {
163 struct nv40_sampler_state *ps;
164 uint32_t filter = 0;
165
166 ps = malloc(sizeof(struct nv40_sampler_state));
167
168 ps->fmt = 0;
169 if (!cso->normalized_coords)
170 ps->fmt |= NV40TCL_TEX_FORMAT_RECT;
171
172 ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) |
173 (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
174 (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT));
175
176 ps->en = 0;
177 if (cso->max_anisotropy >= 2.0) {
178 /* no idea, binary driver sets it, works without it.. meh.. */
179 ps->wrap |= (1 << 5);
180
181 if (cso->max_anisotropy >= 16.0) {
182 ps->en |= (7 << 4);
183 } else
184 if (cso->max_anisotropy >= 12.0) {
185 ps->en |= (6 << 4);
186 } else
187 if (cso->max_anisotropy >= 10.0) {
188 ps->en |= (5 << 4);
189 } else
190 if (cso->max_anisotropy >= 8.0) {
191 ps->en |= (4 << 4);
192 } else
193 if (cso->max_anisotropy >= 6.0) {
194 ps->en |= (3 << 4);
195 } else
196 if (cso->max_anisotropy >= 4.0) {
197 ps->en |= (2 << 4);
198 } else {
199 ps->en |= (1 << 4); /* 2.0 */
200 }
201 }
202
203 switch (cso->mag_img_filter) {
204 case PIPE_TEX_FILTER_LINEAR:
205 filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
206 break;
207 case PIPE_TEX_FILTER_NEAREST:
208 default:
209 filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
210 break;
211 }
212
213 switch (cso->min_img_filter) {
214 case PIPE_TEX_FILTER_LINEAR:
215 switch (cso->min_mip_filter) {
216 case PIPE_TEX_MIPFILTER_NEAREST:
217 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
218 break;
219 case PIPE_TEX_MIPFILTER_LINEAR:
220 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
221 break;
222 case PIPE_TEX_MIPFILTER_NONE:
223 default:
224 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
225 break;
226 }
227 break;
228 case PIPE_TEX_FILTER_NEAREST:
229 default:
230 switch (cso->min_mip_filter) {
231 case PIPE_TEX_MIPFILTER_NEAREST:
232 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
233 break;
234 case PIPE_TEX_MIPFILTER_LINEAR:
235 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
236 break;
237 case PIPE_TEX_MIPFILTER_NONE:
238 default:
239 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
240 break;
241 }
242 break;
243 }
244
245 ps->filt = filter;
246
247 if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
248 switch (cso->compare_func) {
249 case PIPE_FUNC_NEVER:
250 ps->wrap |= (0x0 << 28);
251 break;
252 case PIPE_FUNC_GREATER:
253 ps->wrap |= (0x1 << 28);
254 break;
255 case PIPE_FUNC_EQUAL:
256 ps->wrap |= (0x2 << 28);
257 break;
258 case PIPE_FUNC_GEQUAL:
259 ps->wrap |= (0x3 << 28);
260 break;
261 case PIPE_FUNC_LESS:
262 ps->wrap |= (0x4 << 28);
263 break;
264 case PIPE_FUNC_NOTEQUAL:
265 ps->wrap |= (0x5 << 28);
266 break;
267 case PIPE_FUNC_LEQUAL:
268 ps->wrap |= (0x6 << 28);
269 break;
270 case PIPE_FUNC_ALWAYS:
271 ps->wrap |= (0x7 << 28);
272 break;
273 default:
274 break;
275 }
276 }
277
278 ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
279 (float_to_ubyte(cso->border_color[0]) << 16) |
280 (float_to_ubyte(cso->border_color[1]) << 8) |
281 (float_to_ubyte(cso->border_color[2]) << 0));
282
283 return (void *)ps;
284 }
285
286 static void
287 nv40_sampler_state_bind(struct pipe_context *pipe, unsigned unit,
288 void *hwcso)
289 {
290 struct nv40_context *nv40 = (struct nv40_context *)pipe;
291 struct nv40_sampler_state *ps = hwcso;
292
293 nv40->tex_sampler[unit] = ps;
294 nv40->tex_dirty |= (1 << unit);
295
296 nv40->dirty |= NV40_NEW_TEXTURE;
297 }
298
299 static void
300 nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
301 {
302 free(hwcso);
303 }
304
305 static void *
306 nv40_rasterizer_state_create(struct pipe_context *pipe,
307 const struct pipe_rasterizer_state *cso)
308 {
309 struct nv40_rasterizer_state *rs;
310 int i;
311
312 /*XXX: ignored:
313 * light_twoside
314 * offset_cw/ccw -nohw
315 * scissor
316 * point_smooth -nohw
317 * multisample
318 * offset_units / offset_scale
319 */
320 rs = malloc(sizeof(struct nv40_rasterizer_state));
321
322 rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01;
323
324 rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff;
325 rs->line_smooth_en = cso->line_smooth ? 1 : 0;
326 rs->line_stipple_en = cso->line_stipple_enable ? 1 : 0;
327 rs->line_stipple = (cso->line_stipple_pattern << 16) |
328 cso->line_stipple_factor;
329
330 rs->point_size = *(uint32_t*)&cso->point_size;
331
332 rs->poly_smooth_en = cso->poly_smooth ? 1 : 0;
333 rs->poly_stipple_en = cso->poly_stipple_enable ? 1 : 0;
334
335 if (cso->front_winding == PIPE_WINDING_CCW) {
336 rs->front_face = 0x0901;
337 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw);
338 rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw);
339 } else {
340 rs->front_face = 0x0900;
341 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw);
342 rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw);
343 }
344
345 rs->cull_face_en = 0;
346 rs->cull_face = 0x0900;
347 switch (cso->cull_mode) {
348 case PIPE_WINDING_CCW:
349 rs->cull_face = 0x0901;
350 /* fall-through */
351 case PIPE_WINDING_CW:
352 rs->cull_face_en = 1;
353 break;
354 case PIPE_WINDING_NONE:
355 default:
356 break;
357 }
358
359 if (cso->point_sprite) {
360 rs->point_sprite = (1 << 0);
361 for (i = 0; i < 8; i++) {
362 if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
363 rs->point_sprite |= (1 << (8 + i));
364 }
365 } else {
366 rs->point_sprite = 0;
367 }
368
369 return (void *)rs;
370 }
371
372 static void
373 nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
374 {
375 struct nv40_context *nv40 = (struct nv40_context *)pipe;
376 struct nv40_rasterizer_state *rs = hwcso;
377
378 BEGIN_RING(curie, NV40TCL_SHADE_MODEL, 1);
379 OUT_RING (rs->shade_model);
380
381 BEGIN_RING(curie, NV40TCL_LINE_WIDTH, 2);
382 OUT_RING (rs->line_width);
383 OUT_RING (rs->line_smooth_en);
384 BEGIN_RING(curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
385 OUT_RING (rs->line_stipple_en);
386 OUT_RING (rs->line_stipple);
387
388 BEGIN_RING(curie, NV40TCL_POINT_SIZE, 1);
389 OUT_RING (rs->point_size);
390
391 BEGIN_RING(curie, NV40TCL_POLYGON_MODE_FRONT, 6);
392 OUT_RING (rs->poly_mode_front);
393 OUT_RING (rs->poly_mode_back);
394 OUT_RING (rs->cull_face);
395 OUT_RING (rs->front_face);
396 OUT_RING (rs->poly_smooth_en);
397 OUT_RING (rs->cull_face_en);
398
399 BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
400 OUT_RING (rs->poly_stipple_en);
401
402 BEGIN_RING(curie, NV40TCL_POINT_SPRITE, 1);
403 OUT_RING (rs->point_sprite);
404 }
405
406 static void
407 nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
408 {
409 free(hwcso);
410 }
411
412 static void *
413 nv40_depth_stencil_state_create(struct pipe_context *pipe,
414 const struct pipe_depth_stencil_state *cso)
415 {
416 struct nv40_depth_stencil_state *zs;
417
418 /*XXX: ignored:
419 * depth.occlusion_count
420 * depth.clear
421 * stencil.clear_value
422 */
423 zs = malloc(sizeof(struct nv40_depth_stencil_state));
424
425 zs->depth.func = nvgl_comparison_op(cso->depth.func);
426 zs->depth.write_enable = cso->depth.writemask ? 1 : 0;
427 zs->depth.test_enable = cso->depth.enabled ? 1 : 0;
428
429 zs->stencil.back.enable = cso->stencil.back_enabled ? 1 : 0;
430 zs->stencil.back.wmask = cso->stencil.write_mask[1];
431 zs->stencil.back.func =
432 nvgl_comparison_op(cso->stencil.back_func);
433 zs->stencil.back.ref = cso->stencil.ref_value[1];
434 zs->stencil.back.vmask = cso->stencil.value_mask[1];
435 zs->stencil.back.fail = nvgl_stencil_op(cso->stencil.back_fail_op);
436 zs->stencil.back.zfail = nvgl_stencil_op(cso->stencil.back_zfail_op);
437 zs->stencil.back.zpass = nvgl_stencil_op(cso->stencil.back_zpass_op);
438
439 zs->stencil.front.enable= cso->stencil.front_enabled ? 1 : 0;
440 zs->stencil.front.wmask = cso->stencil.write_mask[0];
441 zs->stencil.front.func =
442 nvgl_comparison_op(cso->stencil.front_func);
443 zs->stencil.front.ref = cso->stencil.ref_value[0];
444 zs->stencil.front.vmask = cso->stencil.value_mask[0];
445 zs->stencil.front.fail = nvgl_stencil_op(cso->stencil.front_fail_op);
446 zs->stencil.front.zfail = nvgl_stencil_op(cso->stencil.front_zfail_op);
447 zs->stencil.front.zpass = nvgl_stencil_op(cso->stencil.front_zpass_op);
448
449 return (void *)zs;
450 }
451
452 static void
453 nv40_depth_stencil_state_bind(struct pipe_context *pipe, void *hwcso)
454 {
455 struct nv40_context *nv40 = (struct nv40_context *)pipe;
456 struct nv40_depth_stencil_state *zs = hwcso;
457
458 BEGIN_RING(curie, NV40TCL_DEPTH_FUNC, 3);
459 OUT_RINGp ((uint32_t *)&zs->depth, 3);
460 BEGIN_RING(curie, NV40TCL_STENCIL_BACK_ENABLE, 16);
461 OUT_RINGp ((uint32_t *)&zs->stencil.back, 8);
462 OUT_RINGp ((uint32_t *)&zs->stencil.front, 8);
463 }
464
465 static void
466 nv40_depth_stencil_state_delete(struct pipe_context *pipe, void *hwcso)
467 {
468 free(hwcso);
469 }
470
471 static void *
472 nv40_vp_state_create(struct pipe_context *pipe,
473 const struct pipe_shader_state *cso)
474 {
475 struct nv40_vertex_program *vp;
476
477 vp = calloc(1, sizeof(struct nv40_vertex_program));
478 vp->pipe = cso;
479
480 return (void *)vp;
481 }
482
483 static void
484 nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
485 {
486 struct nv40_context *nv40 = (struct nv40_context *)pipe;
487 struct nv40_vertex_program *vp = hwcso;
488
489 nv40->vertprog.current = vp;
490 nv40->dirty |= NV40_NEW_VERTPROG;
491 }
492
493 static void
494 nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
495 {
496 free(hwcso);
497 }
498
499 static void *
500 nv40_fp_state_create(struct pipe_context *pipe,
501 const struct pipe_shader_state *cso)
502 {
503 struct nv40_fragment_program *fp;
504
505 fp = calloc(1, sizeof(struct nv40_fragment_program));
506 fp->pipe = cso;
507
508 return (void *)fp;
509 }
510
511 static void
512 nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
513 {
514 struct nv40_context *nv40 = (struct nv40_context *)pipe;
515 struct nv40_fragment_program *fp = hwcso;
516
517 nv40->fragprog.current = fp;
518 nv40->dirty |= NV40_NEW_FRAGPROG;
519 }
520
521 static void
522 nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
523 {
524 free(hwcso);
525 }
526
527 static void
528 nv40_set_blend_color(struct pipe_context *pipe,
529 const struct pipe_blend_color *bcol)
530 {
531 struct nv40_context *nv40 = (struct nv40_context *)pipe;
532
533 BEGIN_RING(curie, NV40TCL_BLEND_COLOR, 1);
534 OUT_RING ((float_to_ubyte(bcol->color[3]) << 24) |
535 (float_to_ubyte(bcol->color[0]) << 16) |
536 (float_to_ubyte(bcol->color[1]) << 8) |
537 (float_to_ubyte(bcol->color[2]) << 0));
538 }
539
540 static void
541 nv40_set_clip_state(struct pipe_context *pipe,
542 const struct pipe_clip_state *clip)
543 {
544 struct nv40_context *nv40 = (struct nv40_context *)pipe;
545
546 nv40->dirty |= NV40_NEW_VERTPROG;
547 }
548
549 static void
550 nv40_set_clear_color_state(struct pipe_context *pipe,
551 const struct pipe_clear_color_state *ccol)
552 {
553 struct nv40_context *nv40 = (struct nv40_context *)pipe;
554
555 BEGIN_RING(curie, NV40TCL_CLEAR_VALUE_COLOR, 1);
556 OUT_RING ((float_to_ubyte(ccol->color[3]) << 24) |
557 (float_to_ubyte(ccol->color[0]) << 16) |
558 (float_to_ubyte(ccol->color[1]) << 8) |
559 (float_to_ubyte(ccol->color[2]) << 0));
560 }
561
562 static void
563 nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
564 const struct pipe_constant_buffer *buf )
565 {
566 struct nv40_context *nv40 = (struct nv40_context *)pipe;
567
568 if (shader == PIPE_SHADER_VERTEX) {
569 nv40->vertprog.constant_buf = buf->buffer;
570 nv40->dirty |= NV40_NEW_VERTPROG;
571 } else
572 if (shader == PIPE_SHADER_FRAGMENT) {
573 nv40->fragprog.constant_buf = buf->buffer;
574 nv40->dirty |= NV40_NEW_FRAGPROG;
575 }
576 }
577
578 static void
579 nv40_set_framebuffer_state(struct pipe_context *pipe,
580 const struct pipe_framebuffer_state *fb)
581 {
582 struct nv40_context *nv40 = (struct nv40_context *)pipe;
583 struct pipe_surface *rt[4], *zeta;
584 uint32_t rt_enable, rt_format, w, h;
585 int i, colour_format = 0, zeta_format = 0;
586
587 rt_enable = 0;
588 for (i = 0; i < 4; i++) {
589 if (!fb->cbufs[i])
590 continue;
591
592 if (colour_format) {
593 assert(w == fb->cbufs[i]->width);
594 assert(h == fb->cbufs[i]->height);
595 assert(colour_format == fb->cbufs[i]->format);
596 } else {
597 w = fb->cbufs[i]->width;
598 h = fb->cbufs[i]->height;
599 colour_format = fb->cbufs[i]->format;
600 rt_enable |= (NV40TCL_RT_ENABLE_COLOR0 << i);
601 rt[i] = fb->cbufs[i];
602 }
603 }
604
605 if (rt_enable & (NV40TCL_RT_ENABLE_COLOR1 | NV40TCL_RT_ENABLE_COLOR2 |
606 NV40TCL_RT_ENABLE_COLOR3))
607 rt_enable |= NV40TCL_RT_ENABLE_MRT;
608
609 if (fb->zbuf) {
610 if (colour_format) {
611 assert(w == fb->zbuf->width);
612 assert(h == fb->zbuf->height);
613 } else {
614 w = fb->zbuf->width;
615 h = fb->zbuf->height;
616 }
617
618 zeta_format = fb->zbuf->format;
619 zeta = fb->zbuf;
620 }
621
622 if (fb->sbuf) {
623 if (colour_format) {
624 assert(w == fb->sbuf->width);
625 assert(h == fb->sbuf->height);
626 } else {
627 w = fb->zbuf->width;
628 h = fb->zbuf->height;
629 }
630
631 if (zeta_format) {
632 assert(fb->sbuf->format == zeta_format);
633 assert(fb->sbuf == zeta);
634 } else {
635 zeta_format = fb->sbuf->format;
636 zeta = fb->sbuf;
637 }
638 }
639
640 rt_format = NV40TCL_RT_FORMAT_TYPE_LINEAR;
641
642 switch (colour_format) {
643 case PIPE_FORMAT_A8R8G8B8_UNORM:
644 case 0:
645 rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8;
646 break;
647 case PIPE_FORMAT_R5G6B5_UNORM:
648 rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5;
649 break;
650 default:
651 assert(0);
652 }
653
654 switch (zeta_format) {
655 case PIPE_FORMAT_Z16_UNORM:
656 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16;
657 break;
658 case PIPE_FORMAT_Z24S8_UNORM:
659 case 0:
660 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8;
661 break;
662 default:
663 assert(0);
664 }
665
666 if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
667 BEGIN_RING(curie, NV40TCL_DMA_COLOR0, 1);
668 OUT_RELOCo(rt[0]->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
669 BEGIN_RING(curie, NV40TCL_COLOR0_PITCH, 2);
670 OUT_RING (rt[0]->pitch * rt[0]->cpp);
671 OUT_RELOCl(rt[0]->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
672 }
673
674 if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
675 BEGIN_RING(curie, NV40TCL_DMA_COLOR1, 1);
676 OUT_RELOCo(rt[1]->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
677 BEGIN_RING(curie, NV40TCL_COLOR1_OFFSET, 2);
678 OUT_RELOCl(rt[1]->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
679 OUT_RING (rt[1]->pitch * rt[1]->cpp);
680 }
681
682 if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
683 BEGIN_RING(curie, NV40TCL_DMA_COLOR2, 1);
684 OUT_RELOCo(rt[2]->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
685 BEGIN_RING(curie, NV40TCL_COLOR2_OFFSET, 1);
686 OUT_RELOCl(rt[2]->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
687 BEGIN_RING(curie, NV40TCL_COLOR2_PITCH, 1);
688 OUT_RING (rt[2]->pitch * rt[2]->cpp);
689 }
690
691 if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
692 BEGIN_RING(curie, NV40TCL_DMA_COLOR3, 1);
693 OUT_RELOCo(rt[3]->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
694 BEGIN_RING(curie, NV40TCL_COLOR3_OFFSET, 1);
695 OUT_RELOCl(rt[3]->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
696 BEGIN_RING(curie, NV40TCL_COLOR3_PITCH, 1);
697 OUT_RING (rt[3]->pitch * rt[3]->cpp);
698 }
699
700 if (zeta_format) {
701 BEGIN_RING(curie, NV40TCL_DMA_ZETA, 1);
702 OUT_RELOCo(zeta->buffer,
703 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR | NOUVEAU_BO_RD);
704 BEGIN_RING(curie, NV40TCL_ZETA_OFFSET, 1);
705 OUT_RELOCl(zeta->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR |
706 NOUVEAU_BO_RD);
707 BEGIN_RING(curie, NV40TCL_ZETA_PITCH, 1);
708 OUT_RING (zeta->pitch * zeta->cpp);
709 }
710
711 BEGIN_RING(curie, NV40TCL_RT_ENABLE, 1);
712 OUT_RING (rt_enable);
713 BEGIN_RING(curie, NV40TCL_RT_HORIZ, 3);
714 OUT_RING ((w << 16) | 0);
715 OUT_RING ((h << 16) | 0);
716 OUT_RING (rt_format);
717 BEGIN_RING(curie, NV40TCL_VIEWPORT_HORIZ, 2);
718 OUT_RING ((w << 16) | 0);
719 OUT_RING ((h << 16) | 0);
720 BEGIN_RING(curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
721 OUT_RING (((w - 1) << 16) | 0);
722 OUT_RING (((h - 1) << 16) | 0);
723 }
724
725 static void
726 nv40_set_polygon_stipple(struct pipe_context *pipe,
727 const struct pipe_poly_stipple *stipple)
728 {
729 struct nv40_context *nv40 = (struct nv40_context *)pipe;
730
731 BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 32);
732 OUT_RINGp ((uint32_t *)stipple->stipple, 32);
733 }
734
735 static void
736 nv40_set_sampler_units(struct pipe_context *pipe,
737 uint num_samplers, const uint *units)
738 {
739 }
740
741 static void
742 nv40_set_scissor_state(struct pipe_context *pipe,
743 const struct pipe_scissor_state *s)
744 {
745 struct nv40_context *nv40 = (struct nv40_context *)pipe;
746
747 BEGIN_RING(curie, NV40TCL_SCISSOR_HORIZ, 2);
748 OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
749 OUT_RING (((s->maxy - s->miny) << 16) | s->miny);
750 }
751
752 static void
753 nv40_set_texture_state(struct pipe_context *pipe, unsigned unit,
754 struct pipe_texture *miptree)
755 {
756 struct nv40_context *nv40 = (struct nv40_context *)pipe;
757
758 nv40->tex_miptree[unit] = miptree;
759 nv40->tex_dirty |= unit;
760
761 nv40->dirty |= NV40_NEW_TEXTURE;
762 }
763
764 static void
765 nv40_set_viewport_state(struct pipe_context *pipe,
766 const struct pipe_viewport_state *vpt)
767 {
768 struct nv40_context *nv40 = (struct nv40_context *)pipe;
769
770 BEGIN_RING(curie, NV40TCL_VIEWPORT_TRANSLATE_X, 8);
771 OUT_RINGf (vpt->translate[0]);
772 OUT_RINGf (vpt->translate[1]);
773 OUT_RINGf (vpt->translate[2]);
774 OUT_RINGf (vpt->translate[3]);
775 OUT_RINGf (vpt->scale[0]);
776 OUT_RINGf (vpt->scale[1]);
777 OUT_RINGf (vpt->scale[2]);
778 OUT_RINGf (vpt->scale[3]);
779 }
780
781 static void
782 nv40_set_vertex_buffer(struct pipe_context *pipe, unsigned index,
783 const struct pipe_vertex_buffer *vb)
784 {
785 struct nv40_context *nv40 = (struct nv40_context *)pipe;
786
787 nv40->vtxbuf[index] = *vb;
788
789 nv40->dirty |= NV40_NEW_ARRAYS;
790 }
791
792 static void
793 nv40_set_vertex_element(struct pipe_context *pipe, unsigned index,
794 const struct pipe_vertex_element *ve)
795 {
796 struct nv40_context *nv40 = (struct nv40_context *)pipe;
797
798 nv40->vtxelt[index] = *ve;
799
800 nv40->dirty |= NV40_NEW_ARRAYS;
801 }
802
803 void
804 nv40_init_state_functions(struct nv40_context *nv40)
805 {
806 nv40->pipe.create_alpha_test_state = nv40_alpha_test_state_create;
807 nv40->pipe.bind_alpha_test_state = nv40_alpha_test_state_bind;
808 nv40->pipe.delete_alpha_test_state = nv40_alpha_test_state_delete;
809
810 nv40->pipe.create_blend_state = nv40_blend_state_create;
811 nv40->pipe.bind_blend_state = nv40_blend_state_bind;
812 nv40->pipe.delete_blend_state = nv40_blend_state_delete;
813
814 nv40->pipe.create_sampler_state = nv40_sampler_state_create;
815 nv40->pipe.bind_sampler_state = nv40_sampler_state_bind;
816 nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
817
818 nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
819 nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
820 nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
821
822 nv40->pipe.create_depth_stencil_state = nv40_depth_stencil_state_create;
823 nv40->pipe.bind_depth_stencil_state = nv40_depth_stencil_state_bind;
824 nv40->pipe.delete_depth_stencil_state = nv40_depth_stencil_state_delete;
825
826 nv40->pipe.create_vs_state = nv40_vp_state_create;
827 nv40->pipe.bind_vs_state = nv40_vp_state_bind;
828 nv40->pipe.delete_vs_state = nv40_vp_state_delete;
829
830 nv40->pipe.create_fs_state = nv40_fp_state_create;
831 nv40->pipe.bind_fs_state = nv40_fp_state_bind;
832 nv40->pipe.delete_fs_state = nv40_fp_state_delete;
833
834 nv40->pipe.set_blend_color = nv40_set_blend_color;
835 nv40->pipe.set_clip_state = nv40_set_clip_state;
836 nv40->pipe.set_clear_color_state = nv40_set_clear_color_state;
837 nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
838 nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
839 nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
840 nv40->pipe.set_sampler_units = nv40_set_sampler_units;
841 nv40->pipe.set_scissor_state = nv40_set_scissor_state;
842 nv40->pipe.set_texture_state = nv40_set_texture_state;
843 nv40->pipe.set_viewport_state = nv40_set_viewport_state;
844
845 nv40->pipe.set_vertex_buffer = nv40_set_vertex_buffer;
846 nv40->pipe.set_vertex_element = nv40_set_vertex_element;
847
848 // nv40->pipe.set_feedback_state = nv40_set_feedback_state;
849 // nv40->pipe.set_feedback_buffer = nv40_set_feedback_buffer;
850 }
851