nv40: cleanup state handling a bit
[mesa.git] / src / mesa / pipe / nv40 / nv40_vbo.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_state.h"
3 #include "pipe/p_util.h"
4
5 #include "nv40_context.h"
6 #include "nv40_state.h"
7
8 #include "pipe/nouveau/nouveau_channel.h"
9 #include "pipe/nouveau/nouveau_pushbuf.h"
10
11 static INLINE int
12 nv40_vbo_ncomp(uint format)
13 {
14 int ncomp = 0;
15
16 if (pf_size_x(format)) ncomp++;
17 if (pf_size_y(format)) ncomp++;
18 if (pf_size_z(format)) ncomp++;
19 if (pf_size_w(format)) ncomp++;
20
21 return ncomp;
22 }
23
24 static INLINE int
25 nv40_vbo_type(uint format)
26 {
27 switch (pf_type(format)) {
28 case PIPE_FORMAT_TYPE_FLOAT:
29 return NV40TCL_VTXFMT_TYPE_FLOAT;
30 case PIPE_FORMAT_TYPE_UNORM:
31 return NV40TCL_VTXFMT_TYPE_UBYTE;
32 default:
33 assert(0);
34 }
35 }
36
37 static boolean
38 nv40_vbo_static_attrib(struct nv40_context *nv40, int attrib,
39 struct pipe_vertex_element *ve,
40 struct pipe_vertex_buffer *vb)
41 {
42 struct pipe_winsys *ws = nv40->pipe.winsys;
43 int type, ncomp;
44 void *map;
45
46 type = nv40_vbo_type(ve->src_format);
47 ncomp = nv40_vbo_ncomp(ve->src_format);
48
49 map = ws->buffer_map(ws, vb->buffer, PIPE_BUFFER_USAGE_CPU_READ);
50 map += vb->buffer_offset + ve->src_offset;
51
52 switch (type) {
53 case NV40TCL_VTXFMT_TYPE_FLOAT:
54 {
55 float *v = map;
56
57 BEGIN_RING(curie, NV40TCL_VTX_ATTR_4F_X(attrib), 4);
58 switch (ncomp) {
59 case 4:
60 OUT_RINGf(v[0]);
61 OUT_RINGf(v[1]);
62 OUT_RINGf(v[2]);
63 OUT_RINGf(v[3]);
64 break;
65 case 3:
66 OUT_RINGf(v[0]);
67 OUT_RINGf(v[1]);
68 OUT_RINGf(v[2]);
69 OUT_RINGf(1.0);
70 break;
71 case 2:
72 OUT_RINGf(v[0]);
73 OUT_RINGf(v[1]);
74 OUT_RINGf(0.0);
75 OUT_RINGf(1.0);
76 break;
77 case 1:
78 OUT_RINGf(v[0]);
79 OUT_RINGf(0.0);
80 OUT_RINGf(0.0);
81 OUT_RINGf(1.0);
82 break;
83 default:
84 ws->buffer_unmap(ws, vb->buffer);
85 return FALSE;
86 }
87 }
88 break;
89 default:
90 ws->buffer_unmap(ws, vb->buffer);
91 return FALSE;
92 }
93
94 ws->buffer_unmap(ws, vb->buffer);
95
96 return TRUE;
97 }
98
99 static void
100 nv40_vbo_arrays_update(struct nv40_context *nv40, struct pipe_buffer *ib,
101 unsigned ib_format)
102 {
103 struct nv40_vertex_program *vp = nv40->vertprog.active;
104 struct nouveau_stateobj *vtxbuf, *vtxfmt;
105 unsigned inputs, hw, num_hw;
106 unsigned vb_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
107
108 inputs = vp->ir;
109 for (hw = 0; hw < 16 && inputs; hw++) {
110 if (inputs & (1 << hw)) {
111 num_hw = hw;
112 inputs &= ~(1 << hw);
113 }
114 }
115 num_hw++;
116
117 vtxbuf = so_new(20, 18);
118 so_method(vtxbuf, nv40->curie, NV40TCL_VTXBUF_ADDRESS(0), num_hw);
119 vtxfmt = so_new(17, 0);
120 so_method(vtxfmt, nv40->curie, NV40TCL_VTXFMT(0), num_hw);
121
122 inputs = vp->ir;
123 for (hw = 0; hw < num_hw; hw++) {
124 struct pipe_vertex_element *ve;
125 struct pipe_vertex_buffer *vb;
126
127 if (!(inputs & (1 << hw))) {
128 so_data(vtxbuf, 0);
129 so_data(vtxfmt, NV40TCL_VTXFMT_TYPE_FLOAT);
130 continue;
131 }
132
133 ve = &nv40->vtxelt[hw];
134 vb = &nv40->vtxbuf[ve->vertex_buffer_index];
135
136 if (!vb->pitch && nv40_vbo_static_attrib(nv40, hw, ve, vb)) {
137 so_data(vtxbuf, 0);
138 so_data(vtxfmt, NV40TCL_VTXFMT_TYPE_FLOAT);
139 continue;
140 }
141
142 so_reloc(vtxbuf, vb->buffer, vb->buffer_offset + ve->src_offset,
143 vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
144 0, NV40TCL_VTXBUF_ADDRESS_DMA1);
145 so_data (vtxfmt, ((vb->pitch << NV40TCL_VTXFMT_STRIDE_SHIFT) |
146 (nv40_vbo_ncomp(ve->src_format) <<
147 NV40TCL_VTXFMT_SIZE_SHIFT) |
148 nv40_vbo_type(ve->src_format)));
149 }
150
151 if (ib) {
152 so_method(vtxbuf, nv40->curie, NV40TCL_IDXBUF_ADDRESS, 2);
153 so_reloc (vtxbuf, ib, 0, vb_flags | NOUVEAU_BO_LOW, 0, 0);
154 so_reloc (vtxbuf, ib, ib_format, vb_flags | NOUVEAU_BO_OR,
155 0, NV40TCL_IDXBUF_FORMAT_DMA1);
156 }
157
158 so_emit(nv40->nvws, vtxfmt);
159 so_emit(nv40->nvws, vtxbuf);
160 so_ref (vtxbuf, &nv40->so_vtxbuf);
161 so_ref (NULL, &vtxfmt);
162 }
163
164 static boolean
165 nv40_vbo_validate_state(struct nv40_context *nv40,
166 struct pipe_buffer *ib, unsigned ib_format)
167 {
168 nv40_emit_hw_state(nv40);
169 if (nv40->dirty & NV40_NEW_ARRAYS || ib) {
170 nv40_vbo_arrays_update(nv40, ib, ib_format);
171 nv40->dirty &= ~NV40_NEW_ARRAYS;
172 }
173
174 so_emit_reloc_markers(nv40->nvws, nv40->so_vtxbuf);
175
176 BEGIN_RING(curie, 0x1710, 1);
177 OUT_RING (0); /* vtx cache flush */
178
179 return TRUE;
180 }
181
182 boolean
183 nv40_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
184 unsigned count)
185 {
186 struct nv40_context *nv40 = nv40_context(pipe);
187 unsigned nr;
188
189 assert(nv40_vbo_validate_state(nv40, NULL, 0));
190
191 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
192 OUT_RING (nvgl_primitive(mode));
193
194 nr = (count & 0xff);
195 if (nr) {
196 BEGIN_RING(curie, NV40TCL_VB_VERTEX_BATCH, 1);
197 OUT_RING (((nr - 1) << 24) | start);
198 start += nr;
199 }
200
201 nr = count >> 8;
202 while (nr) {
203 unsigned push = nr > 2047 ? 2047 : nr;
204
205 nr -= push;
206
207 BEGIN_RING_NI(curie, NV40TCL_VB_VERTEX_BATCH, push);
208 while (push--) {
209 OUT_RING(((0x100 - 1) << 24) | start);
210 start += 0x100;
211 }
212 }
213
214 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
215 OUT_RING (0);
216
217 pipe->flush(pipe, 0);
218 return TRUE;
219 }
220
221 static INLINE void
222 nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
223 unsigned start, unsigned count)
224 {
225 uint8_t *elts = (uint8_t *)ib + start;
226 int push, i;
227
228 if (count & 1) {
229 BEGIN_RING(curie, NV40TCL_VB_ELEMENT_U32, 1);
230 OUT_RING (elts[0]);
231 elts++; count--;
232 }
233
234 while (count) {
235 push = MIN2(count, 2046);
236
237 BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U16, push);
238 for (i = 0; i < push; i+=2)
239 OUT_RING((elts[i+1] << 16) | elts[i]);
240
241 count -= push;
242 elts += push;
243 }
244 }
245
246 static INLINE void
247 nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
248 unsigned start, unsigned count)
249 {
250 uint16_t *elts = (uint16_t *)ib + start;
251 int push, i;
252
253 if (count & 1) {
254 BEGIN_RING(curie, NV40TCL_VB_ELEMENT_U32, 1);
255 OUT_RING (elts[0]);
256 elts++; count--;
257 }
258
259 while (count) {
260 push = MIN2(count, 2046);
261
262 BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U16, push);
263 for (i = 0; i < push; i+=2)
264 OUT_RING((elts[i+1] << 16) | elts[i]);
265
266 count -= push;
267 elts += push;
268 }
269 }
270
271 static INLINE void
272 nv40_draw_elements_u32(struct nv40_context *nv40, void *ib,
273 unsigned start, unsigned count)
274 {
275 uint32_t *elts = (uint32_t *)ib + start;
276 int push;
277
278 while (count) {
279 push = MIN2(count, 2047);
280
281 BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U32, push);
282 OUT_RINGp (elts, push);
283
284 count -= push;
285 elts += push;
286 }
287 }
288
289 static boolean
290 nv40_draw_elements_inline(struct pipe_context *pipe,
291 struct pipe_buffer *ib, unsigned ib_size,
292 unsigned mode, unsigned start, unsigned count)
293 {
294 struct nv40_context *nv40 = nv40_context(pipe);
295 struct pipe_winsys *ws = pipe->winsys;
296 void *map;
297
298 assert(nv40_vbo_validate_state(nv40, NULL, 0));
299
300 map = ws->buffer_map(ws, ib, PIPE_BUFFER_USAGE_CPU_READ);
301 if (!ib)
302 assert(0);
303
304 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
305 OUT_RING (nvgl_primitive(mode));
306
307 switch (ib_size) {
308 case 1:
309 nv40_draw_elements_u08(nv40, map, start, count);
310 break;
311 case 2:
312 nv40_draw_elements_u16(nv40, map, start, count);
313 break;
314 case 4:
315 nv40_draw_elements_u32(nv40, map, start, count);
316 break;
317 default:
318 assert(0);
319 break;
320 }
321
322 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
323 OUT_RING (0);
324
325 ws->buffer_unmap(ws, ib);
326
327 return TRUE;
328 }
329
330 static boolean
331 nv40_draw_elements_vbo(struct pipe_context *pipe,
332 struct pipe_buffer *ib, unsigned ib_size,
333 unsigned mode, unsigned start, unsigned count)
334 {
335 struct nv40_context *nv40 = nv40_context(pipe);
336 unsigned nr, type;
337
338 switch (ib_size) {
339 case 2:
340 type = NV40TCL_IDXBUF_FORMAT_TYPE_U16;
341 break;
342 case 4:
343 type = NV40TCL_IDXBUF_FORMAT_TYPE_U32;
344 break;
345 default:
346 assert(0);
347 }
348
349 assert(nv40_vbo_validate_state(nv40, ib, type));
350
351 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
352 OUT_RING (nvgl_primitive(mode));
353
354 nr = (count & 0xff);
355 if (nr) {
356 BEGIN_RING(curie, NV40TCL_VB_INDEX_BATCH, 1);
357 OUT_RING (((nr - 1) << 24) | start);
358 start += nr;
359 }
360
361 nr = count >> 8;
362 while (nr) {
363 unsigned push = nr > 2047 ? 2047 : nr;
364
365 nr -= push;
366
367 BEGIN_RING_NI(curie, NV40TCL_VB_INDEX_BATCH, push);
368 while (push--) {
369 OUT_RING(((0x100 - 1) << 24) | start);
370 start += 0x100;
371 }
372 }
373
374 BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
375 OUT_RING (0);
376
377 return TRUE;
378 }
379
380 boolean
381 nv40_draw_elements(struct pipe_context *pipe,
382 struct pipe_buffer *indexBuffer, unsigned indexSize,
383 unsigned mode, unsigned start, unsigned count)
384 {
385 struct nv40_context *nv40 = nv40_context(pipe);
386
387 /* 0x4497 doesn't support real index buffers, and there doesn't appear
388 * to be support on any chipset for 8-bit indices.
389 */
390 if (nv40->curie->grclass == NV44TCL || indexSize == 1) {
391 nv40_draw_elements_inline(pipe, indexBuffer, indexSize,
392 mode, start, count);
393 } else {
394 nv40_draw_elements_vbo(pipe, indexBuffer, indexSize,
395 mode, start, count);
396 }
397
398 pipe->flush(pipe, 0);
399 return TRUE;
400 }
401
402