Real-time assembler for Cell SPE.
[mesa.git] / src / mesa / ppc / rtasm / spe_asm.c
1 /*
2 * (C) Copyright IBM Corporation 2008
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /**
26 * \file spe_asm.c
27 * Real-time assembly generation interface for Cell B.E. SPEs.
28 *
29 * \author Ian Romanick <idr@us.ibm.com>
30 */
31 #ifdef GALLIUM_CELL
32 #include <inttypes.h>
33 #include <imports.h>
34 #include "spe_asm.h"
35
36 /**
37 * SPE instruction types
38 *
39 * There are 6 primary instruction encodings used on the Cell's SPEs. Each of
40 * the following unions encodes one type.
41 *
42 * \bug
43 * If, at some point, we start generating SPE code from a little-endian host
44 * these unions will not work.
45 */
46 /*@{*/
47 /**
48 * Encode one output register with two input registers
49 */
50 union spe_inst_RR {
51 uint32_t bits;
52 struct {
53 unsigned op:11;
54 unsigned rB:7;
55 unsigned rA:7;
56 unsigned rT:7;
57 } inst;
58 };
59
60
61 /**
62 * Encode one output register with three input registers
63 */
64 union spe_inst_RRR {
65 uint32_t bits;
66 struct {
67 unsigned op:4;
68 unsigned rT:7;
69 unsigned rB:7;
70 unsigned rA:7;
71 unsigned rC:7;
72 } inst;
73 };
74
75
76 /**
77 * Encode one output register with one input reg. and a 7-bit signed immed
78 */
79 union spe_inst_RI7 {
80 uint32_t bits;
81 struct {
82 unsigned op:11;
83 unsigned i7:7;
84 unsigned rA:7;
85 unsigned rT:7;
86 } inst;
87 };
88
89
90 /**
91 * Encode one output register with one input reg. and a 10-bit signed immed
92 */
93 union spe_inst_RI10 {
94 uint32_t bits;
95 struct {
96 unsigned op:8;
97 unsigned i10:10;
98 unsigned rA:7;
99 unsigned rT:7;
100 } inst;
101 };
102
103
104 /**
105 * Encode one output register with a 16-bit signed immediate
106 */
107 union spe_inst_RI16 {
108 uint32_t bits;
109 struct {
110 unsigned op:9;
111 unsigned i16:16;
112 unsigned rT:7;
113 } inst;
114 };
115
116
117 /**
118 * Encode one output register with a 18-bit signed immediate
119 */
120 union spe_inst_RI18 {
121 uint32_t bits;
122 struct {
123 unsigned op:7;
124 unsigned i18:18;
125 unsigned rT:7;
126 } inst;
127 };
128 /*@}*/
129
130
131 static void emit_RR(struct spe_function *p, unsigned op, unsigned rT,
132 unsigned rA, unsigned rB)
133 {
134 union spe_inst_RR inst;
135 inst.inst.op = op;
136 inst.inst.rB = rB;
137 inst.inst.rA = rA;
138 inst.inst.rT = rT;
139 *p->csr = inst.bits;
140 p->csr++;
141 }
142
143
144 static void emit_RRR(struct spe_function *p, unsigned op, unsigned rT,
145 unsigned rA, unsigned rB, unsigned rC)
146 {
147 union spe_inst_RRR inst;
148 inst.inst.op = op;
149 inst.inst.rT = rT;
150 inst.inst.rB = rB;
151 inst.inst.rA = rA;
152 inst.inst.rC = rC;
153 *p->csr = inst.bits;
154 p->csr++;
155 }
156
157
158 static void emit_RI7(struct spe_function *p, unsigned op, unsigned rT,
159 unsigned rA, int imm)
160 {
161 union spe_inst_RI7 inst;
162 inst.inst.op = op;
163 inst.inst.i7 = imm;
164 inst.inst.rA = rA;
165 inst.inst.rT = rT;
166 *p->csr = inst.bits;
167 p->csr++;
168 }
169
170
171
172 static void emit_RI10(struct spe_function *p, unsigned op, unsigned rT,
173 unsigned rA, int imm)
174 {
175 union spe_inst_RI10 inst;
176 inst.inst.op = op;
177 inst.inst.i10 = imm;
178 inst.inst.rA = rA;
179 inst.inst.rT = rT;
180 *p->csr = inst.bits;
181 p->csr++;
182 }
183
184
185 static void emit_RI16(struct spe_function *p, unsigned op, unsigned rT,
186 int imm)
187 {
188 union spe_inst_RI16 inst;
189 inst.inst.op = op;
190 inst.inst.i16 = imm;
191 inst.inst.rT = rT;
192 *p->csr = inst.bits;
193 p->csr++;
194 }
195
196
197 static void emit_RI18(struct spe_function *p, unsigned op, unsigned rT,
198 int imm)
199 {
200 union spe_inst_RI18 inst;
201 inst.inst.op = op;
202 inst.inst.i18 = imm;
203 inst.inst.rT = rT;
204 *p->csr = inst.bits;
205 p->csr++;
206 }
207
208
209
210
211 #define EMIT_(_name, _op) \
212 void _name (struct spe_function *p, unsigned rT) \
213 { \
214 emit_RR(p, _op, rT, 0, 0); \
215 }
216
217 #define EMIT_R(_name, _op) \
218 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
219 { \
220 emit_RR(p, _op, rT, rA, 0); \
221 }
222
223 #define EMIT_RR(_name, _op) \
224 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
225 { \
226 emit_RR(p, _op, rT, rA, rB); \
227 }
228
229 #define EMIT_RRR(_name, _op) \
230 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
231 { \
232 emit_RRR(p, _op, rT, rA, rB, rC); \
233 }
234
235 #define EMIT_RI7(_name, _op) \
236 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
237 { \
238 emit_RI7(p, _op, rT, rA, imm); \
239 }
240
241 #define EMIT_RI10(_name, _op) \
242 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
243 { \
244 emit_RI10(p, _op, rT, rA, imm); \
245 }
246
247 #define EMIT_RI16(_name, _op) \
248 void _name (struct spe_function *p, unsigned rT, int imm) \
249 { \
250 emit_RI16(p, _op, rT, imm); \
251 }
252
253 #define EMIT_RI18(_name, _op) \
254 void _name (struct spe_function *p, unsigned rT, int imm) \
255 { \
256 emit_RI18(p, _op, rT, imm); \
257 }
258
259 #define EMIT_I16(_name, _op) \
260 void _name (struct spe_function *p, int imm) \
261 { \
262 emit_RI16(p, _op, 0, imm); \
263 }
264
265 #include "spe_asm.h"
266
267
268 /*
269 */
270 void spe_init_func(struct spe_function *p, unsigned code_size)
271 {
272 p->store = _mesa_align_malloc(code_size, 16);
273 p->csr = p->store;
274 }
275
276
277 void spe_release_func(struct spe_function *p)
278 {
279 _mesa_align_free(p->store);
280 p->store = NULL;
281 p->csr = NULL;
282 }
283
284
285 void spu_bi(struct spe_function *p, unsigned rA, int d, int e)
286 {
287 emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4));
288 }
289
290 void spu_iret(struct spe_function *p, unsigned rA, int d, int e)
291 {
292 emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4));
293 }
294
295 void spu_bisled(struct spe_function *p, unsigned rT, unsigned rA, int d,
296 int e)
297 {
298 emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4));
299 }
300
301 void spu_bisl(struct spe_function *p, unsigned rT, unsigned rA, int d,
302 int e)
303 {
304 emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4));
305 }
306
307 void spu_biz(struct spe_function *p, unsigned rT, unsigned rA, int d,
308 int e)
309 {
310 emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4));
311 }
312
313 void spu_binz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
314 {
315 emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4));
316 }
317
318 void spu_bihz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
319 {
320 emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4));
321 }
322
323 void spu_bihnz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
324 {
325 emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4));
326 }
327
328
329 /* Hint-for-branch instructions
330 */
331 #if 0
332 hbr;
333 hbra;
334 hbrr;
335 #endif
336
337
338 /* Control instructions
339 */
340 #if 0
341 stop;
342 EMIT_RR (spu_stopd, 0x140);
343 EMIT_ (spu_lnop, 0x001);
344 EMIT_ (spu_nop, 0x201);
345 sync;
346 EMIT_ (spu_dsync, 0x003);
347 EMIT_R (spu_mfspr, 0x00c);
348 EMIT_R (spu_mtspr, 0x10c);
349 #endif
350
351 #endif /* GALLIUM_CELL */