2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderapi.h"
47 #include "main/shaderobj.h"
48 #include "main/uniforms.h"
50 #include "program/hash_table.h"
51 #include "program/prog_instruction.h"
52 #include "program/prog_optimize.h"
53 #include "program/prog_print.h"
54 #include "program/program.h"
55 #include "program/prog_parameter.h"
56 #include "program/sampler.h"
59 static int swizzle_for_size(int size
);
67 * This struct is a corresponding struct to Mesa prog_src_register, with
72 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
86 this->file
= PROGRAM_UNDEFINED
;
93 explicit src_reg(dst_reg reg
);
95 gl_register_file file
; /**< PROGRAM_* from Mesa */
96 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
97 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
98 int negate
; /**< NEGATE_XYZW mask from mesa */
99 /** Register index should be offset by the integer in this reg. */
105 dst_reg(gl_register_file file
, int writemask
)
109 this->writemask
= writemask
;
110 this->cond_mask
= COND_TR
;
111 this->reladdr
= NULL
;
116 this->file
= PROGRAM_UNDEFINED
;
119 this->cond_mask
= COND_TR
;
120 this->reladdr
= NULL
;
123 explicit dst_reg(src_reg reg
);
125 gl_register_file file
; /**< PROGRAM_* from Mesa */
126 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
127 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
129 /** Register index should be offset by the integer in this reg. */
133 } /* anonymous namespace */
135 src_reg::src_reg(dst_reg reg
)
137 this->file
= reg
.file
;
138 this->index
= reg
.index
;
139 this->swizzle
= SWIZZLE_XYZW
;
141 this->reladdr
= reg
.reladdr
;
144 dst_reg::dst_reg(src_reg reg
)
146 this->file
= reg
.file
;
147 this->index
= reg
.index
;
148 this->writemask
= WRITEMASK_XYZW
;
149 this->cond_mask
= COND_TR
;
150 this->reladdr
= reg
.reladdr
;
155 class ir_to_mesa_instruction
: public exec_node
{
157 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
162 /** Pointer to the ir source this tree came from for debugging */
164 GLboolean cond_update
;
166 int sampler
; /**< sampler index */
167 int tex_target
; /**< One of TEXTURE_*_INDEX */
168 GLboolean tex_shadow
;
171 class variable_storage
: public exec_node
{
173 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
174 : file(file
), index(index
), var(var
)
179 gl_register_file file
;
181 ir_variable
*var
; /* variable that maps to this, if any */
184 class function_entry
: public exec_node
{
186 ir_function_signature
*sig
;
189 * identifier of this function signature used by the program.
191 * At the point that Mesa instructions for function calls are
192 * generated, we don't know the address of the first instruction of
193 * the function body. So we make the BranchTarget that is called a
194 * small integer and rewrite them during set_branchtargets().
199 * Pointer to first instruction of the function body.
201 * Set during function body emits after main() is processed.
203 ir_to_mesa_instruction
*bgn_inst
;
206 * Index of the first instruction of the function body in actual
209 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
213 /** Storage for the return value. */
217 class ir_to_mesa_visitor
: public ir_visitor
{
219 ir_to_mesa_visitor();
220 ~ir_to_mesa_visitor();
222 function_entry
*current_function
;
224 struct gl_context
*ctx
;
225 struct gl_program
*prog
;
226 struct gl_shader_program
*shader_program
;
227 struct gl_shader_compiler_options
*options
;
231 variable_storage
*find_variable_storage(const ir_variable
*var
);
233 src_reg
get_temp(const glsl_type
*type
);
234 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
236 src_reg
src_reg_for_float(float val
);
239 * \name Visit methods
241 * As typical for the visitor pattern, there must be one \c visit method for
242 * each concrete subclass of \c ir_instruction. Virtual base classes within
243 * the hierarchy should not have \c visit methods.
246 virtual void visit(ir_variable
*);
247 virtual void visit(ir_loop
*);
248 virtual void visit(ir_loop_jump
*);
249 virtual void visit(ir_function_signature
*);
250 virtual void visit(ir_function
*);
251 virtual void visit(ir_expression
*);
252 virtual void visit(ir_swizzle
*);
253 virtual void visit(ir_dereference_variable
*);
254 virtual void visit(ir_dereference_array
*);
255 virtual void visit(ir_dereference_record
*);
256 virtual void visit(ir_assignment
*);
257 virtual void visit(ir_constant
*);
258 virtual void visit(ir_call
*);
259 virtual void visit(ir_return
*);
260 virtual void visit(ir_discard
*);
261 virtual void visit(ir_texture
*);
262 virtual void visit(ir_if
*);
263 virtual void visit(ir_emit_vertex
*);
264 virtual void visit(ir_end_primitive
*);
269 /** List of variable_storage */
272 /** List of function_entry */
273 exec_list function_signatures
;
274 int next_signature_id
;
276 /** List of ir_to_mesa_instruction */
277 exec_list instructions
;
279 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
281 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
282 dst_reg dst
, src_reg src0
);
284 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
285 dst_reg dst
, src_reg src0
, src_reg src1
);
287 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
289 src_reg src0
, src_reg src1
, src_reg src2
);
292 * Emit the correct dot-product instruction for the type of arguments
294 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
300 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
301 dst_reg dst
, src_reg src0
);
303 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
304 dst_reg dst
, src_reg src0
, src_reg src1
);
306 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
307 dst_reg dst
, const src_reg
&src
);
309 bool try_emit_mad(ir_expression
*ir
,
311 bool try_emit_mad_for_and_not(ir_expression
*ir
,
314 void emit_swz(ir_expression
*ir
);
316 bool process_move_condition(ir_rvalue
*ir
);
318 void copy_propagate(void);
323 } /* anonymous namespace */
325 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
327 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
329 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
332 swizzle_for_size(int size
)
334 static const int size_swizzles
[4] = {
335 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
336 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
337 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
338 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
341 assert((size
>= 1) && (size
<= 4));
342 return size_swizzles
[size
- 1];
345 ir_to_mesa_instruction
*
346 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
348 src_reg src0
, src_reg src1
, src_reg src2
)
350 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
353 /* If we have to do relative addressing, we want to load the ARL
354 * reg directly for one of the regs, and preload the other reladdr
355 * sources into temps.
357 num_reladdr
+= dst
.reladdr
!= NULL
;
358 num_reladdr
+= src0
.reladdr
!= NULL
;
359 num_reladdr
+= src1
.reladdr
!= NULL
;
360 num_reladdr
+= src2
.reladdr
!= NULL
;
362 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
363 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
364 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
367 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
370 assert(num_reladdr
== 0);
379 this->instructions
.push_tail(inst
);
385 ir_to_mesa_instruction
*
386 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
387 dst_reg dst
, src_reg src0
, src_reg src1
)
389 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
392 ir_to_mesa_instruction
*
393 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
394 dst_reg dst
, src_reg src0
)
396 assert(dst
.writemask
!= 0);
397 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
400 ir_to_mesa_instruction
*
401 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
403 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
406 ir_to_mesa_instruction
*
407 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
408 dst_reg dst
, src_reg src0
, src_reg src1
,
411 static const gl_inst_opcode dot_opcodes
[] = {
412 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
415 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
419 * Emits Mesa scalar opcodes to produce unique answers across channels.
421 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
422 * channel determines the result across all channels. So to do a vec4
423 * of this operation, we want to emit a scalar per source channel used
424 * to produce dest channels.
427 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
429 src_reg orig_src0
, src_reg orig_src1
)
432 int done_mask
= ~dst
.writemask
;
434 /* Mesa RCP is a scalar operation splatting results to all channels,
435 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
438 for (i
= 0; i
< 4; i
++) {
439 GLuint this_mask
= (1 << i
);
440 ir_to_mesa_instruction
*inst
;
441 src_reg src0
= orig_src0
;
442 src_reg src1
= orig_src1
;
444 if (done_mask
& this_mask
)
447 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
448 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
449 for (j
= i
+ 1; j
< 4; j
++) {
450 /* If there is another enabled component in the destination that is
451 * derived from the same inputs, generate its value on this pass as
454 if (!(done_mask
& (1 << j
)) &&
455 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
456 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
457 this_mask
|= (1 << j
);
460 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
461 src0_swiz
, src0_swiz
);
462 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
463 src1_swiz
, src1_swiz
);
465 inst
= emit(ir
, op
, dst
, src0
, src1
);
466 inst
->dst
.writemask
= this_mask
;
467 done_mask
|= this_mask
;
472 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
473 dst_reg dst
, src_reg src0
)
475 src_reg undef
= undef_src
;
477 undef
.swizzle
= SWIZZLE_XXXX
;
479 emit_scalar(ir
, op
, dst
, src0
, undef
);
483 * Emit an OPCODE_SCS instruction
485 * The \c SCS opcode functions a bit differently than the other Mesa (or
486 * ARB_fragment_program) opcodes. Instead of splatting its result across all
487 * four components of the destination, it writes one value to the \c x
488 * component and another value to the \c y component.
490 * \param ir IR instruction being processed
491 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
493 * \param dst Destination register
494 * \param src Source register
497 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
501 /* Vertex programs cannot use the SCS opcode.
503 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
504 emit_scalar(ir
, op
, dst
, src
);
508 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
509 const unsigned scs_mask
= (1U << component
);
510 int done_mask
= ~dst
.writemask
;
513 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
515 /* If there are compnents in the destination that differ from the component
516 * that will be written by the SCS instrution, we'll need a temporary.
518 if (scs_mask
!= unsigned(dst
.writemask
)) {
519 tmp
= get_temp(glsl_type::vec4_type
);
522 for (unsigned i
= 0; i
< 4; i
++) {
523 unsigned this_mask
= (1U << i
);
526 if ((done_mask
& this_mask
) != 0)
529 /* The source swizzle specified which component of the source generates
530 * sine / cosine for the current component in the destination. The SCS
531 * instruction requires that this value be swizzle to the X component.
532 * Replace the current swizzle with a swizzle that puts the source in
535 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
537 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
538 src0_swiz
, src0_swiz
);
539 for (unsigned j
= i
+ 1; j
< 4; j
++) {
540 /* If there is another enabled component in the destination that is
541 * derived from the same inputs, generate its value on this pass as
544 if (!(done_mask
& (1 << j
)) &&
545 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
546 this_mask
|= (1 << j
);
550 if (this_mask
!= scs_mask
) {
551 ir_to_mesa_instruction
*inst
;
552 dst_reg tmp_dst
= dst_reg(tmp
);
554 /* Emit the SCS instruction.
556 inst
= emit(ir
, OPCODE_SCS
, tmp_dst
, src0
);
557 inst
->dst
.writemask
= scs_mask
;
559 /* Move the result of the SCS instruction to the desired location in
562 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
563 component
, component
);
564 inst
= emit(ir
, OPCODE_SCS
, dst
, tmp
);
565 inst
->dst
.writemask
= this_mask
;
567 /* Emit the SCS instruction to write directly to the destination.
569 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_SCS
, dst
, src0
);
570 inst
->dst
.writemask
= scs_mask
;
573 done_mask
|= this_mask
;
578 ir_to_mesa_visitor::src_reg_for_float(float val
)
580 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
582 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
583 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
589 type_size(const struct glsl_type
*type
)
594 switch (type
->base_type
) {
597 case GLSL_TYPE_FLOAT
:
599 if (type
->is_matrix()) {
600 return type
->matrix_columns
;
602 /* Regardless of size of vector, it gets a vec4. This is bad
603 * packing for things like floats, but otherwise arrays become a
604 * mess. Hopefully a later pass over the code can pack scalars
605 * down if appropriate.
610 case GLSL_TYPE_DOUBLE
:
611 if (type
->is_matrix()) {
612 if (type
->vector_elements
> 2)
613 return type
->matrix_columns
* 2;
615 return type
->matrix_columns
;
617 if (type
->vector_elements
> 2)
623 case GLSL_TYPE_ARRAY
:
624 assert(type
->length
> 0);
625 return type_size(type
->fields
.array
) * type
->length
;
626 case GLSL_TYPE_STRUCT
:
628 for (i
= 0; i
< type
->length
; i
++) {
629 size
+= type_size(type
->fields
.structure
[i
].type
);
632 case GLSL_TYPE_SAMPLER
:
633 case GLSL_TYPE_IMAGE
:
634 /* Samplers take up one slot in UNIFORMS[], but they're baked in
638 case GLSL_TYPE_ATOMIC_UINT
:
640 case GLSL_TYPE_ERROR
:
641 case GLSL_TYPE_INTERFACE
:
642 assert(!"Invalid type in type_size");
650 * In the initial pass of codegen, we assign temporary numbers to
651 * intermediate results. (not SSA -- variable assignments will reuse
652 * storage). Actual register allocation for the Mesa VM occurs in a
653 * pass over the Mesa IR later.
656 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
660 src
.file
= PROGRAM_TEMPORARY
;
661 src
.index
= next_temp
;
663 next_temp
+= type_size(type
);
665 if (type
->is_array() || type
->is_record()) {
666 src
.swizzle
= SWIZZLE_NOOP
;
668 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
676 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
678 foreach_in_list(variable_storage
, entry
, &this->variables
) {
679 if (entry
->var
== var
)
687 ir_to_mesa_visitor::visit(ir_variable
*ir
)
689 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
690 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
692 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
693 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
696 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
698 const ir_state_slot
*const slots
= ir
->get_state_slots();
699 assert(slots
!= NULL
);
701 /* Check if this statevar's setup in the STATE file exactly
702 * matches how we'll want to reference it as a
703 * struct/array/whatever. If not, then we need to move it into
704 * temporary storage and hope that it'll get copy-propagated
707 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
708 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
713 variable_storage
*storage
;
715 if (i
== ir
->get_num_state_slots()) {
716 /* We'll set the index later. */
717 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
718 this->variables
.push_tail(storage
);
722 /* The variable_storage constructor allocates slots based on the size
723 * of the type. However, this had better match the number of state
724 * elements that we're going to copy into the new temporary.
726 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
728 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
730 this->variables
.push_tail(storage
);
731 this->next_temp
+= type_size(ir
->type
);
733 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
737 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
738 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
739 (gl_state_index
*)slots
[i
].tokens
);
741 if (storage
->file
== PROGRAM_STATE_VAR
) {
742 if (storage
->index
== -1) {
743 storage
->index
= index
;
745 assert(index
== storage
->index
+ (int)i
);
748 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
749 src
.swizzle
= slots
[i
].swizzle
;
750 emit(ir
, OPCODE_MOV
, dst
, src
);
751 /* even a float takes up a whole vec4 reg in a struct/array. */
756 if (storage
->file
== PROGRAM_TEMPORARY
&&
757 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
758 linker_error(this->shader_program
,
759 "failed to load builtin uniform `%s' "
760 "(%d/%d regs loaded)\n",
761 ir
->name
, dst
.index
- storage
->index
,
762 type_size(ir
->type
));
768 ir_to_mesa_visitor::visit(ir_loop
*ir
)
770 emit(NULL
, OPCODE_BGNLOOP
);
772 visit_exec_list(&ir
->body_instructions
, this);
774 emit(NULL
, OPCODE_ENDLOOP
);
778 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
781 case ir_loop_jump::jump_break
:
782 emit(NULL
, OPCODE_BRK
);
784 case ir_loop_jump::jump_continue
:
785 emit(NULL
, OPCODE_CONT
);
792 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
799 ir_to_mesa_visitor::visit(ir_function
*ir
)
801 /* Ignore function bodies other than main() -- we shouldn't see calls to
802 * them since they should all be inlined before we get to ir_to_mesa.
804 if (strcmp(ir
->name
, "main") == 0) {
805 const ir_function_signature
*sig
;
808 sig
= ir
->matching_signature(NULL
, &empty
, false);
812 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
819 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
821 int nonmul_operand
= 1 - mul_operand
;
824 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
825 if (!expr
|| expr
->operation
!= ir_binop_mul
)
828 expr
->operands
[0]->accept(this);
830 expr
->operands
[1]->accept(this);
832 ir
->operands
[nonmul_operand
]->accept(this);
835 this->result
= get_temp(ir
->type
);
836 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
842 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
844 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
845 * implemented using multiplication, and logical-or is implemented using
846 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
847 * As result, the logical expression (a & !b) can be rewritten as:
851 * - (a * 1) - (a * b)
855 * This final expression can be implemented as a single MAD(a, -b, a)
859 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
861 const int other_operand
= 1 - try_operand
;
864 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
865 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
868 ir
->operands
[other_operand
]->accept(this);
870 expr
->operands
[0]->accept(this);
873 b
.negate
= ~b
.negate
;
875 this->result
= get_temp(ir
->type
);
876 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
882 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
883 src_reg
*reg
, int *num_reladdr
)
888 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
890 if (*num_reladdr
!= 1) {
891 src_reg temp
= get_temp(glsl_type::vec4_type
);
893 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
901 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
903 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
904 * This means that each of the operands is either an immediate value of -1,
905 * 0, or 1, or is a component from one source register (possibly with
908 uint8_t components
[4] = { 0 };
909 bool negate
[4] = { false };
910 ir_variable
*var
= NULL
;
912 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
913 ir_rvalue
*op
= ir
->operands
[i
];
915 assert(op
->type
->is_scalar());
918 switch (op
->ir_type
) {
919 case ir_type_constant
: {
921 assert(op
->type
->is_scalar());
923 const ir_constant
*const c
= op
->as_constant();
925 components
[i
] = SWIZZLE_ONE
;
926 } else if (c
->is_zero()) {
927 components
[i
] = SWIZZLE_ZERO
;
928 } else if (c
->is_negative_one()) {
929 components
[i
] = SWIZZLE_ONE
;
932 assert(!"SWZ constant must be 0.0 or 1.0.");
939 case ir_type_dereference_variable
: {
940 ir_dereference_variable
*const deref
=
941 (ir_dereference_variable
*) op
;
943 assert((var
== NULL
) || (deref
->var
== var
));
944 components
[i
] = SWIZZLE_X
;
950 case ir_type_expression
: {
951 ir_expression
*const expr
= (ir_expression
*) op
;
953 assert(expr
->operation
== ir_unop_neg
);
956 op
= expr
->operands
[0];
960 case ir_type_swizzle
: {
961 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
963 components
[i
] = swiz
->mask
.x
;
969 assert(!"Should not get here.");
977 ir_dereference_variable
*const deref
=
978 new(mem_ctx
) ir_dereference_variable(var
);
980 this->result
.file
= PROGRAM_UNDEFINED
;
982 if (this->result
.file
== PROGRAM_UNDEFINED
) {
983 printf("Failed to get tree for expression operand:\n");
992 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
996 src
.negate
= ((unsigned(negate
[0]) << 0)
997 | (unsigned(negate
[1]) << 1)
998 | (unsigned(negate
[2]) << 2)
999 | (unsigned(negate
[3]) << 3));
1001 /* Storage for our result. Ideally for an assignment we'd be using the
1002 * actual storage for the result here, instead.
1004 const src_reg result_src
= get_temp(ir
->type
);
1005 dst_reg result_dst
= dst_reg(result_src
);
1007 /* Limit writes to the channels that will be used by result_src later.
1008 * This does limit this temp's use as a temporary for multi-instruction
1011 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1013 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
1014 this->result
= result_src
;
1018 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1020 unsigned int operand
;
1021 src_reg op
[ARRAY_SIZE(ir
->operands
)];
1025 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1027 if (ir
->operation
== ir_binop_add
) {
1028 if (try_emit_mad(ir
, 1))
1030 if (try_emit_mad(ir
, 0))
1034 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1036 if (ir
->operation
== ir_binop_logic_and
) {
1037 if (try_emit_mad_for_and_not(ir
, 1))
1039 if (try_emit_mad_for_and_not(ir
, 0))
1043 if (ir
->operation
== ir_quadop_vector
) {
1048 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1049 this->result
.file
= PROGRAM_UNDEFINED
;
1050 ir
->operands
[operand
]->accept(this);
1051 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1052 printf("Failed to get tree for expression operand:\n");
1053 ir
->operands
[operand
]->print();
1057 op
[operand
] = this->result
;
1059 /* Matrix expression operands should have been broken down to vector
1060 * operations already.
1062 assert(!ir
->operands
[operand
]->type
->is_matrix());
1065 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1066 if (ir
->operands
[1]) {
1067 vector_elements
= MAX2(vector_elements
,
1068 ir
->operands
[1]->type
->vector_elements
);
1071 this->result
.file
= PROGRAM_UNDEFINED
;
1073 /* Storage for our result. Ideally for an assignment we'd be using
1074 * the actual storage for the result here, instead.
1076 result_src
= get_temp(ir
->type
);
1077 /* convenience for the emit functions below. */
1078 result_dst
= dst_reg(result_src
);
1079 /* Limit writes to the channels that will be used by result_src later.
1080 * This does limit this temp's use as a temporary for multi-instruction
1083 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1085 switch (ir
->operation
) {
1086 case ir_unop_logic_not
:
1087 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1088 * older GPUs implement SEQ using multiple instructions (i915 uses two
1089 * SGE instructions and a MUL instruction). Since our logic values are
1090 * 0.0 and 1.0, 1-x also implements !x.
1092 op
[0].negate
= ~op
[0].negate
;
1093 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1096 op
[0].negate
= ~op
[0].negate
;
1100 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1103 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1106 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1110 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1114 assert(!"not reached: should be handled by ir_explog_to_explog2");
1117 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1120 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1123 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1125 case ir_unop_sin_reduced
:
1126 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1128 case ir_unop_cos_reduced
:
1129 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1133 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1136 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1139 case ir_unop_saturate
: {
1140 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_MOV
,
1142 inst
->saturate
= true;
1145 case ir_unop_noise
: {
1146 const enum prog_opcode opcode
=
1147 prog_opcode(OPCODE_NOISE1
1148 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1149 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1151 emit(ir
, opcode
, result_dst
, op
[0]);
1156 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1159 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1163 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1166 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1169 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1170 assert(ir
->type
->is_integer());
1171 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1175 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1177 case ir_binop_greater
:
1178 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1180 case ir_binop_lequal
:
1181 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1183 case ir_binop_gequal
:
1184 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1186 case ir_binop_equal
:
1187 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1189 case ir_binop_nequal
:
1190 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1192 case ir_binop_all_equal
:
1193 /* "==" operator producing a scalar boolean. */
1194 if (ir
->operands
[0]->type
->is_vector() ||
1195 ir
->operands
[1]->type
->is_vector()) {
1196 src_reg temp
= get_temp(glsl_type::vec4_type
);
1197 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1199 /* After the dot-product, the value will be an integer on the
1200 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1202 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1204 /* Negating the result of the dot-product gives values on the range
1205 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1206 * achieved using SGE.
1208 src_reg sge_src
= result_src
;
1209 sge_src
.negate
= ~sge_src
.negate
;
1210 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1212 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1215 case ir_binop_any_nequal
:
1216 /* "!=" operator producing a scalar boolean. */
1217 if (ir
->operands
[0]->type
->is_vector() ||
1218 ir
->operands
[1]->type
->is_vector()) {
1219 src_reg temp
= get_temp(glsl_type::vec4_type
);
1220 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1222 /* After the dot-product, the value will be an integer on the
1223 * range [0,4]. Zero stays zero, and positive values become 1.0.
1225 ir_to_mesa_instruction
*const dp
=
1226 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1227 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1228 /* The clamping to [0,1] can be done for free in the fragment
1229 * shader with a saturate.
1231 dp
->saturate
= true;
1233 /* Negating the result of the dot-product gives values on the range
1234 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1235 * achieved using SLT.
1237 src_reg slt_src
= result_src
;
1238 slt_src
.negate
= ~slt_src
.negate
;
1239 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1242 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1247 assert(ir
->operands
[0]->type
->is_vector());
1249 /* After the dot-product, the value will be an integer on the
1250 * range [0,4]. Zero stays zero, and positive values become 1.0.
1252 ir_to_mesa_instruction
*const dp
=
1253 emit_dp(ir
, result_dst
, op
[0], op
[0],
1254 ir
->operands
[0]->type
->vector_elements
);
1255 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1256 /* The clamping to [0,1] can be done for free in the fragment
1257 * shader with a saturate.
1259 dp
->saturate
= true;
1261 /* Negating the result of the dot-product gives values on the range
1262 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1263 * is achieved using SLT.
1265 src_reg slt_src
= result_src
;
1266 slt_src
.negate
= ~slt_src
.negate
;
1267 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1272 case ir_binop_logic_xor
:
1273 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1276 case ir_binop_logic_or
: {
1277 /* After the addition, the value will be an integer on the
1278 * range [0,2]. Zero stays zero, and positive values become 1.0.
1280 ir_to_mesa_instruction
*add
=
1281 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1282 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1283 /* The clamping to [0,1] can be done for free in the fragment
1284 * shader with a saturate.
1286 add
->saturate
= true;
1288 /* Negating the result of the addition gives values on the range
1289 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1290 * is achieved using SLT.
1292 src_reg slt_src
= result_src
;
1293 slt_src
.negate
= ~slt_src
.negate
;
1294 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1299 case ir_binop_logic_and
:
1300 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1301 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1305 assert(ir
->operands
[0]->type
->is_vector());
1306 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1307 emit_dp(ir
, result_dst
, op
[0], op
[1],
1308 ir
->operands
[0]->type
->vector_elements
);
1312 /* sqrt(x) = x * rsq(x). */
1313 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1314 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1315 /* For incoming channels <= 0, set the result to 0. */
1316 op
[0].negate
= ~op
[0].negate
;
1317 emit(ir
, OPCODE_CMP
, result_dst
,
1318 op
[0], result_src
, src_reg_for_float(0.0));
1321 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1329 /* Mesa IR lacks types, ints are stored as truncated floats. */
1334 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1338 emit(ir
, OPCODE_SNE
, result_dst
,
1339 op
[0], src_reg_for_float(0.0));
1341 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1342 case ir_unop_bitcast_f2u
:
1343 case ir_unop_bitcast_i2f
:
1344 case ir_unop_bitcast_u2f
:
1347 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1350 op
[0].negate
= ~op
[0].negate
;
1351 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1352 result_src
.negate
= ~result_src
.negate
;
1355 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1358 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1360 case ir_unop_pack_snorm_2x16
:
1361 case ir_unop_pack_snorm_4x8
:
1362 case ir_unop_pack_unorm_2x16
:
1363 case ir_unop_pack_unorm_4x8
:
1364 case ir_unop_pack_half_2x16
:
1365 case ir_unop_pack_double_2x32
:
1366 case ir_unop_unpack_snorm_2x16
:
1367 case ir_unop_unpack_snorm_4x8
:
1368 case ir_unop_unpack_unorm_2x16
:
1369 case ir_unop_unpack_unorm_4x8
:
1370 case ir_unop_unpack_half_2x16
:
1371 case ir_unop_unpack_half_2x16_split_x
:
1372 case ir_unop_unpack_half_2x16_split_y
:
1373 case ir_unop_unpack_double_2x32
:
1374 case ir_binop_pack_half_2x16_split
:
1375 case ir_unop_bitfield_reverse
:
1376 case ir_unop_bit_count
:
1377 case ir_unop_find_msb
:
1378 case ir_unop_find_lsb
:
1386 case ir_unop_frexp_sig
:
1387 case ir_unop_frexp_exp
:
1388 assert(!"not supported");
1391 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1394 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1397 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1400 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1401 * hardware backends have no way to avoid Mesa IR generation
1402 * even if they don't use it, we need to emit "something" and
1405 case ir_binop_lshift
:
1406 case ir_binop_rshift
:
1407 case ir_binop_bit_and
:
1408 case ir_binop_bit_xor
:
1409 case ir_binop_bit_or
:
1410 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1413 case ir_unop_bit_not
:
1414 case ir_unop_round_even
:
1415 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1418 case ir_binop_ubo_load
:
1419 assert(!"not supported");
1423 /* ir_triop_lrp operands are (x, y, a) while
1424 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1426 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1429 case ir_binop_vector_extract
:
1433 case ir_triop_bitfield_extract
:
1434 case ir_triop_vector_insert
:
1435 case ir_quadop_bitfield_insert
:
1436 case ir_binop_ldexp
:
1438 case ir_binop_carry
:
1439 case ir_binop_borrow
:
1440 case ir_binop_imul_high
:
1441 case ir_unop_interpolate_at_centroid
:
1442 case ir_binop_interpolate_at_offset
:
1443 case ir_binop_interpolate_at_sample
:
1444 case ir_unop_dFdx_coarse
:
1445 case ir_unop_dFdx_fine
:
1446 case ir_unop_dFdy_coarse
:
1447 case ir_unop_dFdy_fine
:
1448 assert(!"not supported");
1451 case ir_quadop_vector
:
1452 /* This operation should have already been handled.
1454 assert(!"Should not get here.");
1458 this->result
= result_src
;
1463 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1469 /* Note that this is only swizzles in expressions, not those on the left
1470 * hand side of an assignment, which do write masking. See ir_assignment
1474 ir
->val
->accept(this);
1476 assert(src
.file
!= PROGRAM_UNDEFINED
);
1477 assert(ir
->type
->vector_elements
> 0);
1479 for (i
= 0; i
< 4; i
++) {
1480 if (i
< ir
->type
->vector_elements
) {
1483 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1486 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1489 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1492 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1496 /* If the type is smaller than a vec4, replicate the last
1499 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1503 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1509 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1511 variable_storage
*entry
= find_variable_storage(ir
->var
);
1512 ir_variable
*var
= ir
->var
;
1515 switch (var
->data
.mode
) {
1516 case ir_var_uniform
:
1517 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1518 var
->data
.location
);
1519 this->variables
.push_tail(entry
);
1521 case ir_var_shader_in
:
1522 /* The linker assigns locations for varyings and attributes,
1523 * including deprecated builtins (like gl_Color),
1524 * user-assigned generic attributes (glBindVertexLocation),
1525 * and user-defined varyings.
1527 assert(var
->data
.location
!= -1);
1528 entry
= new(mem_ctx
) variable_storage(var
,
1530 var
->data
.location
);
1532 case ir_var_shader_out
:
1533 assert(var
->data
.location
!= -1);
1534 entry
= new(mem_ctx
) variable_storage(var
,
1536 var
->data
.location
);
1538 case ir_var_system_value
:
1539 entry
= new(mem_ctx
) variable_storage(var
,
1540 PROGRAM_SYSTEM_VALUE
,
1541 var
->data
.location
);
1544 case ir_var_temporary
:
1545 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1547 this->variables
.push_tail(entry
);
1549 next_temp
+= type_size(var
->type
);
1554 printf("Failed to make storage for %s\n", var
->name
);
1559 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1563 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1567 int element_size
= type_size(ir
->type
);
1569 index
= ir
->array_index
->constant_expression_value();
1571 ir
->array
->accept(this);
1575 src
.index
+= index
->value
.i
[0] * element_size
;
1577 /* Variable index array dereference. It eats the "vec4" of the
1578 * base of the array and an index that offsets the Mesa register
1581 ir
->array_index
->accept(this);
1585 if (element_size
== 1) {
1586 index_reg
= this->result
;
1588 index_reg
= get_temp(glsl_type::float_type
);
1590 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1591 this->result
, src_reg_for_float(element_size
));
1594 /* If there was already a relative address register involved, add the
1595 * new and the old together to get the new offset.
1597 if (src
.reladdr
!= NULL
) {
1598 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1600 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1601 index_reg
, *src
.reladdr
);
1603 index_reg
= accum_reg
;
1606 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1607 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1610 /* If the type is smaller than a vec4, replicate the last channel out. */
1611 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1612 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1614 src
.swizzle
= SWIZZLE_NOOP
;
1620 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1623 const glsl_type
*struct_type
= ir
->record
->type
;
1626 ir
->record
->accept(this);
1628 for (i
= 0; i
< struct_type
->length
; i
++) {
1629 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1631 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1634 /* If the type is smaller than a vec4, replicate the last channel out. */
1635 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1636 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1638 this->result
.swizzle
= SWIZZLE_NOOP
;
1640 this->result
.index
+= offset
;
1644 * We want to be careful in assignment setup to hit the actual storage
1645 * instead of potentially using a temporary like we might with the
1646 * ir_dereference handler.
1649 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1651 /* The LHS must be a dereference. If the LHS is a variable indexed array
1652 * access of a vector, it must be separated into a series conditional moves
1653 * before reaching this point (see ir_vec_index_to_cond_assign).
1655 assert(ir
->as_dereference());
1656 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1658 assert(!deref_array
->array
->type
->is_vector());
1661 /* Use the rvalue deref handler for the most part. We'll ignore
1662 * swizzles in it and write swizzles using writemask, though.
1665 return dst_reg(v
->result
);
1669 * Process the condition of a conditional assignment
1671 * Examines the condition of a conditional assignment to generate the optimal
1672 * first operand of a \c CMP instruction. If the condition is a relational
1673 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1674 * used as the source for the \c CMP instruction. Otherwise the comparison
1675 * is processed to a boolean result, and the boolean result is used as the
1676 * operand to the CMP instruction.
1679 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1681 ir_rvalue
*src_ir
= ir
;
1683 bool switch_order
= false;
1685 ir_expression
*const expr
= ir
->as_expression();
1686 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1687 bool zero_on_left
= false;
1689 if (expr
->operands
[0]->is_zero()) {
1690 src_ir
= expr
->operands
[1];
1691 zero_on_left
= true;
1692 } else if (expr
->operands
[1]->is_zero()) {
1693 src_ir
= expr
->operands
[0];
1694 zero_on_left
= false;
1698 * (a < 0) T F F ( a < 0) T F F
1699 * (0 < a) F F T (-a < 0) F F T
1700 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1701 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1702 * (a > 0) F F T (-a < 0) F F T
1703 * (0 > a) T F F ( a < 0) T F F
1704 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1705 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1707 * Note that exchanging the order of 0 and 'a' in the comparison simply
1708 * means that the value of 'a' should be negated.
1711 switch (expr
->operation
) {
1713 switch_order
= false;
1714 negate
= zero_on_left
;
1717 case ir_binop_greater
:
1718 switch_order
= false;
1719 negate
= !zero_on_left
;
1722 case ir_binop_lequal
:
1723 switch_order
= true;
1724 negate
= !zero_on_left
;
1727 case ir_binop_gequal
:
1728 switch_order
= true;
1729 negate
= zero_on_left
;
1733 /* This isn't the right kind of comparison afterall, so make sure
1734 * the whole condition is visited.
1742 src_ir
->accept(this);
1744 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1745 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1746 * choose which value OPCODE_CMP produces without an extra instruction
1747 * computing the condition.
1750 this->result
.negate
= ~this->result
.negate
;
1752 return switch_order
;
1756 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1762 ir
->rhs
->accept(this);
1765 l
= get_assignment_lhs(ir
->lhs
, this);
1767 /* FINISHME: This should really set to the correct maximal writemask for each
1768 * FINISHME: component written (in the loops below). This case can only
1769 * FINISHME: occur for matrices, arrays, and structures.
1771 if (ir
->write_mask
== 0) {
1772 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1773 l
.writemask
= WRITEMASK_XYZW
;
1774 } else if (ir
->lhs
->type
->is_scalar()) {
1775 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1776 * FINISHME: W component of fragment shader output zero, work correctly.
1778 l
.writemask
= WRITEMASK_XYZW
;
1781 int first_enabled_chan
= 0;
1784 assert(ir
->lhs
->type
->is_vector());
1785 l
.writemask
= ir
->write_mask
;
1787 for (int i
= 0; i
< 4; i
++) {
1788 if (l
.writemask
& (1 << i
)) {
1789 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1794 /* Swizzle a small RHS vector into the channels being written.
1796 * glsl ir treats write_mask as dictating how many channels are
1797 * present on the RHS while Mesa IR treats write_mask as just
1798 * showing which channels of the vec4 RHS get written.
1800 for (int i
= 0; i
< 4; i
++) {
1801 if (l
.writemask
& (1 << i
))
1802 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1804 swizzles
[i
] = first_enabled_chan
;
1806 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1807 swizzles
[2], swizzles
[3]);
1810 assert(l
.file
!= PROGRAM_UNDEFINED
);
1811 assert(r
.file
!= PROGRAM_UNDEFINED
);
1813 if (ir
->condition
) {
1814 const bool switch_order
= this->process_move_condition(ir
->condition
);
1815 src_reg condition
= this->result
;
1817 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1819 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1821 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1828 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1829 emit(ir
, OPCODE_MOV
, l
, r
);
1838 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1841 GLfloat stack_vals
[4] = { 0 };
1842 GLfloat
*values
= stack_vals
;
1845 /* Unfortunately, 4 floats is all we can get into
1846 * _mesa_add_unnamed_constant. So, make a temp to store an
1847 * aggregate constant and move each constant value into it. If we
1848 * get lucky, copy propagation will eliminate the extra moves.
1851 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1852 src_reg temp_base
= get_temp(ir
->type
);
1853 dst_reg temp
= dst_reg(temp_base
);
1855 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1856 int size
= type_size(field_value
->type
);
1860 field_value
->accept(this);
1863 for (i
= 0; i
< (unsigned int)size
; i
++) {
1864 emit(ir
, OPCODE_MOV
, temp
, src
);
1870 this->result
= temp_base
;
1874 if (ir
->type
->is_array()) {
1875 src_reg temp_base
= get_temp(ir
->type
);
1876 dst_reg temp
= dst_reg(temp_base
);
1877 int size
= type_size(ir
->type
->fields
.array
);
1881 for (i
= 0; i
< ir
->type
->length
; i
++) {
1882 ir
->array_elements
[i
]->accept(this);
1884 for (int j
= 0; j
< size
; j
++) {
1885 emit(ir
, OPCODE_MOV
, temp
, src
);
1891 this->result
= temp_base
;
1895 if (ir
->type
->is_matrix()) {
1896 src_reg mat
= get_temp(ir
->type
);
1897 dst_reg mat_column
= dst_reg(mat
);
1899 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1900 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1901 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1903 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1904 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1905 (gl_constant_value
*) values
,
1906 ir
->type
->vector_elements
,
1908 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1917 src
.file
= PROGRAM_CONSTANT
;
1918 switch (ir
->type
->base_type
) {
1919 case GLSL_TYPE_FLOAT
:
1920 values
= &ir
->value
.f
[0];
1922 case GLSL_TYPE_UINT
:
1923 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1924 values
[i
] = ir
->value
.u
[i
];
1928 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1929 values
[i
] = ir
->value
.i
[i
];
1932 case GLSL_TYPE_BOOL
:
1933 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1934 values
[i
] = ir
->value
.b
[i
];
1938 assert(!"Non-float/uint/int/bool constant");
1941 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1942 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1943 (gl_constant_value
*) values
,
1944 ir
->type
->vector_elements
,
1945 &this->result
.swizzle
);
1949 ir_to_mesa_visitor::visit(ir_call
*)
1951 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1955 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1957 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1958 dst_reg result_dst
, coord_dst
;
1959 ir_to_mesa_instruction
*inst
= NULL
;
1960 prog_opcode opcode
= OPCODE_NOP
;
1962 if (ir
->op
== ir_txs
)
1963 this->result
= src_reg_for_float(0.0);
1965 ir
->coordinate
->accept(this);
1967 /* Put our coords in a temp. We'll need to modify them for shadow,
1968 * projection, or LOD, so the only case we'd use it as is is if
1969 * we're doing plain old texturing. Mesa IR optimization should
1970 * handle cleaning up our mess in that case.
1972 coord
= get_temp(glsl_type::vec4_type
);
1973 coord_dst
= dst_reg(coord
);
1974 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1976 if (ir
->projector
) {
1977 ir
->projector
->accept(this);
1978 projector
= this->result
;
1981 /* Storage for our result. Ideally for an assignment we'd be using
1982 * the actual storage for the result here, instead.
1984 result_src
= get_temp(glsl_type::vec4_type
);
1985 result_dst
= dst_reg(result_src
);
1990 opcode
= OPCODE_TEX
;
1993 opcode
= OPCODE_TXB
;
1994 ir
->lod_info
.bias
->accept(this);
1995 lod_info
= this->result
;
1998 /* Pretend to be TXL so the sampler, coordinate, lod are available */
2000 opcode
= OPCODE_TXL
;
2001 ir
->lod_info
.lod
->accept(this);
2002 lod_info
= this->result
;
2005 opcode
= OPCODE_TXD
;
2006 ir
->lod_info
.grad
.dPdx
->accept(this);
2008 ir
->lod_info
.grad
.dPdy
->accept(this);
2012 assert(!"Unexpected ir_txf_ms opcode");
2015 assert(!"Unexpected ir_lod opcode");
2018 assert(!"Unexpected ir_tg4 opcode");
2020 case ir_query_levels
:
2021 assert(!"Unexpected ir_query_levels opcode");
2025 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2027 if (ir
->projector
) {
2028 if (opcode
== OPCODE_TEX
) {
2029 /* Slot the projector in as the last component of the coord. */
2030 coord_dst
.writemask
= WRITEMASK_W
;
2031 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
2032 coord_dst
.writemask
= WRITEMASK_XYZW
;
2033 opcode
= OPCODE_TXP
;
2035 src_reg coord_w
= coord
;
2036 coord_w
.swizzle
= SWIZZLE_WWWW
;
2038 /* For the other TEX opcodes there's no projective version
2039 * since the last slot is taken up by lod info. Do the
2040 * projective divide now.
2042 coord_dst
.writemask
= WRITEMASK_W
;
2043 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
2045 /* In the case where we have to project the coordinates "by hand,"
2046 * the shadow comparitor value must also be projected.
2048 src_reg tmp_src
= coord
;
2049 if (ir
->shadow_comparitor
) {
2050 /* Slot the shadow value in as the second to last component of the
2053 ir
->shadow_comparitor
->accept(this);
2055 tmp_src
= get_temp(glsl_type::vec4_type
);
2056 dst_reg tmp_dst
= dst_reg(tmp_src
);
2058 /* Projective division not allowed for array samplers. */
2059 assert(!sampler_type
->sampler_array
);
2061 tmp_dst
.writemask
= WRITEMASK_Z
;
2062 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
2064 tmp_dst
.writemask
= WRITEMASK_XY
;
2065 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
2068 coord_dst
.writemask
= WRITEMASK_XYZ
;
2069 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
2071 coord_dst
.writemask
= WRITEMASK_XYZW
;
2072 coord
.swizzle
= SWIZZLE_XYZW
;
2076 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2077 * comparitor was put in the correct place (and projected) by the code,
2078 * above, that handles by-hand projection.
2080 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
2081 /* Slot the shadow value in as the second to last component of the
2084 ir
->shadow_comparitor
->accept(this);
2086 /* XXX This will need to be updated for cubemap array samplers. */
2087 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
2088 sampler_type
->sampler_array
) {
2089 coord_dst
.writemask
= WRITEMASK_W
;
2091 coord_dst
.writemask
= WRITEMASK_Z
;
2094 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2095 coord_dst
.writemask
= WRITEMASK_XYZW
;
2098 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2099 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2100 coord_dst
.writemask
= WRITEMASK_W
;
2101 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2102 coord_dst
.writemask
= WRITEMASK_XYZW
;
2105 if (opcode
== OPCODE_TXD
)
2106 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2108 inst
= emit(ir
, opcode
, result_dst
, coord
);
2110 if (ir
->shadow_comparitor
)
2111 inst
->tex_shadow
= GL_TRUE
;
2113 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2114 this->shader_program
,
2117 switch (sampler_type
->sampler_dimensionality
) {
2118 case GLSL_SAMPLER_DIM_1D
:
2119 inst
->tex_target
= (sampler_type
->sampler_array
)
2120 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2122 case GLSL_SAMPLER_DIM_2D
:
2123 inst
->tex_target
= (sampler_type
->sampler_array
)
2124 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2126 case GLSL_SAMPLER_DIM_3D
:
2127 inst
->tex_target
= TEXTURE_3D_INDEX
;
2129 case GLSL_SAMPLER_DIM_CUBE
:
2130 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2132 case GLSL_SAMPLER_DIM_RECT
:
2133 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2135 case GLSL_SAMPLER_DIM_BUF
:
2136 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2138 case GLSL_SAMPLER_DIM_EXTERNAL
:
2139 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2142 assert(!"Should not get here.");
2145 this->result
= result_src
;
2149 ir_to_mesa_visitor::visit(ir_return
*ir
)
2151 /* Non-void functions should have been inlined. We may still emit RETs
2152 * from main() unless the EmitNoMainReturn option is set.
2154 assert(!ir
->get_value());
2155 emit(ir
, OPCODE_RET
);
2159 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2161 if (ir
->condition
) {
2162 ir
->condition
->accept(this);
2163 this->result
.negate
= ~this->result
.negate
;
2164 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2166 emit(ir
, OPCODE_KIL_NV
);
2171 ir_to_mesa_visitor::visit(ir_if
*ir
)
2173 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2174 ir_to_mesa_instruction
*prev_inst
;
2176 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2178 ir
->condition
->accept(this);
2179 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2181 if (this->options
->EmitCondCodes
) {
2182 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2184 /* See if we actually generated any instruction for generating
2185 * the condition. If not, then cook up a move to a temp so we
2186 * have something to set cond_update on.
2188 if (cond_inst
== prev_inst
) {
2189 src_reg temp
= get_temp(glsl_type::bool_type
);
2190 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2192 cond_inst
->cond_update
= GL_TRUE
;
2194 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2195 if_inst
->dst
.cond_mask
= COND_NE
;
2197 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2200 this->instructions
.push_tail(if_inst
);
2202 visit_exec_list(&ir
->then_instructions
, this);
2204 if (!ir
->else_instructions
.is_empty()) {
2205 emit(ir
->condition
, OPCODE_ELSE
);
2206 visit_exec_list(&ir
->else_instructions
, this);
2209 emit(ir
->condition
, OPCODE_ENDIF
);
2213 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2215 assert(!"Geometry shaders not supported.");
2219 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2221 assert(!"Geometry shaders not supported.");
2224 ir_to_mesa_visitor::ir_to_mesa_visitor()
2226 result
.file
= PROGRAM_UNDEFINED
;
2228 next_signature_id
= 1;
2229 current_function
= NULL
;
2230 mem_ctx
= ralloc_context(NULL
);
2233 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2235 ralloc_free(mem_ctx
);
2238 static struct prog_src_register
2239 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2241 struct prog_src_register mesa_reg
;
2243 mesa_reg
.File
= reg
.file
;
2244 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2245 mesa_reg
.Index
= reg
.index
;
2246 mesa_reg
.Swizzle
= reg
.swizzle
;
2247 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2248 mesa_reg
.Negate
= reg
.negate
;
2250 mesa_reg
.HasIndex2
= GL_FALSE
;
2251 mesa_reg
.RelAddr2
= 0;
2252 mesa_reg
.Index2
= 0;
2258 set_branchtargets(ir_to_mesa_visitor
*v
,
2259 struct prog_instruction
*mesa_instructions
,
2260 int num_instructions
)
2262 int if_count
= 0, loop_count
= 0;
2263 int *if_stack
, *loop_stack
;
2264 int if_stack_pos
= 0, loop_stack_pos
= 0;
2267 for (i
= 0; i
< num_instructions
; i
++) {
2268 switch (mesa_instructions
[i
].Opcode
) {
2272 case OPCODE_BGNLOOP
:
2277 mesa_instructions
[i
].BranchTarget
= -1;
2284 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2285 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2287 for (i
= 0; i
< num_instructions
; i
++) {
2288 switch (mesa_instructions
[i
].Opcode
) {
2290 if_stack
[if_stack_pos
] = i
;
2294 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2295 if_stack
[if_stack_pos
- 1] = i
;
2298 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2301 case OPCODE_BGNLOOP
:
2302 loop_stack
[loop_stack_pos
] = i
;
2305 case OPCODE_ENDLOOP
:
2307 /* Rewrite any breaks/conts at this nesting level (haven't
2308 * already had a BranchTarget assigned) to point to the end
2311 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2312 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2313 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2314 if (mesa_instructions
[j
].BranchTarget
== -1) {
2315 mesa_instructions
[j
].BranchTarget
= i
;
2319 /* The loop ends point at each other. */
2320 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2321 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2324 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2325 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2326 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2338 print_program(struct prog_instruction
*mesa_instructions
,
2339 ir_instruction
**mesa_instruction_annotation
,
2340 int num_instructions
)
2342 ir_instruction
*last_ir
= NULL
;
2346 for (i
= 0; i
< num_instructions
; i
++) {
2347 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2348 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2350 fprintf(stdout
, "%3d: ", i
);
2352 if (last_ir
!= ir
&& ir
) {
2355 for (j
= 0; j
< indent
; j
++) {
2356 fprintf(stdout
, " ");
2362 fprintf(stdout
, " "); /* line number spacing. */
2365 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2366 PROG_PRINT_DEBUG
, NULL
);
2372 class add_uniform_to_shader
: public program_resource_visitor
{
2374 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2375 struct gl_program_parameter_list
*params
,
2376 gl_shader_stage shader_type
)
2377 : shader_program(shader_program
), params(params
), idx(-1),
2378 shader_type(shader_type
)
2383 void process(ir_variable
*var
)
2386 this->program_resource_visitor::process(var
);
2388 var
->data
.location
= this->idx
;
2392 virtual void visit_field(const glsl_type
*type
, const char *name
,
2395 struct gl_shader_program
*shader_program
;
2396 struct gl_program_parameter_list
*params
;
2398 gl_shader_stage shader_type
;
2401 } /* anonymous namespace */
2404 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2411 if (type
->is_vector() || type
->is_scalar()) {
2412 size
= type
->vector_elements
;
2413 if (type
->is_double())
2416 size
= type_size(type
) * 4;
2419 gl_register_file file
;
2420 if (type
->without_array()->is_sampler()) {
2421 file
= PROGRAM_SAMPLER
;
2423 file
= PROGRAM_UNIFORM
;
2426 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2428 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2431 /* Sampler uniform values are stored in prog->SamplerUnits,
2432 * and the entry in that array is selected by this index we
2433 * store in ParameterValues[].
2435 if (file
== PROGRAM_SAMPLER
) {
2438 this->shader_program
->UniformHash
->get(location
,
2439 params
->Parameters
[index
].Name
);
2445 struct gl_uniform_storage
*storage
=
2446 &this->shader_program
->UniformStorage
[location
];
2448 assert(storage
->sampler
[shader_type
].active
);
2450 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2451 params
->ParameterValues
[index
+ j
][0].f
=
2452 storage
->sampler
[shader_type
].index
+ j
;
2456 /* The first part of the uniform that's processed determines the base
2457 * location of the whole uniform (for structures).
2464 * Generate the program parameters list for the user uniforms in a shader
2466 * \param shader_program Linked shader program. This is only used to
2467 * emit possible link errors to the info log.
2468 * \param sh Shader whose uniforms are to be processed.
2469 * \param params Parameter list to be filled in.
2472 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2474 struct gl_shader
*sh
,
2475 struct gl_program_parameter_list
2478 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2480 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2481 ir_variable
*var
= node
->as_variable();
2483 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2484 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2492 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2493 struct gl_shader_program
*shader_program
,
2494 struct gl_program_parameter_list
*params
)
2496 /* After adding each uniform to the parameter list, connect the storage for
2497 * the parameter with the tracking structure used by the API for the
2500 unsigned last_location
= unsigned(~0);
2501 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2502 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2507 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2513 if (location
!= last_location
) {
2514 struct gl_uniform_storage
*storage
=
2515 &shader_program
->UniformStorage
[location
];
2516 enum gl_uniform_driver_format format
= uniform_native
;
2518 unsigned columns
= 0;
2519 int dmul
= 4 * sizeof(float);
2520 switch (storage
->type
->base_type
) {
2521 case GLSL_TYPE_UINT
:
2522 assert(ctx
->Const
.NativeIntegers
);
2523 format
= uniform_native
;
2528 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2532 case GLSL_TYPE_DOUBLE
:
2533 if (storage
->type
->vector_elements
> 2)
2536 case GLSL_TYPE_FLOAT
:
2537 format
= uniform_native
;
2538 columns
= storage
->type
->matrix_columns
;
2540 case GLSL_TYPE_BOOL
:
2541 format
= uniform_native
;
2544 case GLSL_TYPE_SAMPLER
:
2545 case GLSL_TYPE_IMAGE
:
2546 format
= uniform_native
;
2549 case GLSL_TYPE_ATOMIC_UINT
:
2550 case GLSL_TYPE_ARRAY
:
2551 case GLSL_TYPE_VOID
:
2552 case GLSL_TYPE_STRUCT
:
2553 case GLSL_TYPE_ERROR
:
2554 case GLSL_TYPE_INTERFACE
:
2555 assert(!"Should not get here.");
2559 _mesa_uniform_attach_driver_storage(storage
,
2563 ¶ms
->ParameterValues
[i
]);
2565 /* After attaching the driver's storage to the uniform, propagate any
2566 * data from the linker's backing store. This will cause values from
2567 * initializers in the source code to be copied over.
2569 _mesa_propagate_uniforms_to_driver_storage(storage
,
2571 MAX2(1, storage
->array_elements
));
2573 last_location
= location
;
2579 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2580 * channels for copy propagation and updates following instructions to
2581 * use the original versions.
2583 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2584 * will occur. As an example, a TXP production before this pass:
2586 * 0: MOV TEMP[1], INPUT[4].xyyy;
2587 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2588 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2592 * 0: MOV TEMP[1], INPUT[4].xyyy;
2593 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2594 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2596 * which allows for dead code elimination on TEMP[1]'s writes.
2599 ir_to_mesa_visitor::copy_propagate(void)
2601 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2602 ir_to_mesa_instruction
*,
2603 this->next_temp
* 4);
2604 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2607 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2608 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2609 || inst
->dst
.index
< this->next_temp
);
2611 /* First, do any copy propagation possible into the src regs. */
2612 for (int r
= 0; r
< 3; r
++) {
2613 ir_to_mesa_instruction
*first
= NULL
;
2615 int acp_base
= inst
->src
[r
].index
* 4;
2617 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2618 inst
->src
[r
].reladdr
)
2621 /* See if we can find entries in the ACP consisting of MOVs
2622 * from the same src register for all the swizzled channels
2623 * of this src register reference.
2625 for (int i
= 0; i
< 4; i
++) {
2626 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2627 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2634 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2639 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2640 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2648 /* We've now validated that we can copy-propagate to
2649 * replace this src register reference. Do it.
2651 inst
->src
[r
].file
= first
->src
[0].file
;
2652 inst
->src
[r
].index
= first
->src
[0].index
;
2655 for (int i
= 0; i
< 4; i
++) {
2656 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2657 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2658 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2661 inst
->src
[r
].swizzle
= swizzle
;
2666 case OPCODE_BGNLOOP
:
2667 case OPCODE_ENDLOOP
:
2668 /* End of a basic block, clear the ACP entirely. */
2669 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2678 /* Clear all channels written inside the block from the ACP, but
2679 * leaving those that were not touched.
2681 for (int r
= 0; r
< this->next_temp
; r
++) {
2682 for (int c
= 0; c
< 4; c
++) {
2683 if (!acp
[4 * r
+ c
])
2686 if (acp_level
[4 * r
+ c
] >= level
)
2687 acp
[4 * r
+ c
] = NULL
;
2690 if (inst
->op
== OPCODE_ENDIF
)
2695 /* Continuing the block, clear any written channels from
2698 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2699 /* Any temporary might be written, so no copy propagation
2700 * across this instruction.
2702 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2703 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2704 inst
->dst
.reladdr
) {
2705 /* Any output might be written, so no copy propagation
2706 * from outputs across this instruction.
2708 for (int r
= 0; r
< this->next_temp
; r
++) {
2709 for (int c
= 0; c
< 4; c
++) {
2710 if (!acp
[4 * r
+ c
])
2713 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2714 acp
[4 * r
+ c
] = NULL
;
2717 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2718 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2719 /* Clear where it's used as dst. */
2720 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2721 for (int c
= 0; c
< 4; c
++) {
2722 if (inst
->dst
.writemask
& (1 << c
)) {
2723 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2728 /* Clear where it's used as src. */
2729 for (int r
= 0; r
< this->next_temp
; r
++) {
2730 for (int c
= 0; c
< 4; c
++) {
2731 if (!acp
[4 * r
+ c
])
2734 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2736 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2737 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2738 inst
->dst
.writemask
& (1 << src_chan
))
2740 acp
[4 * r
+ c
] = NULL
;
2748 /* If this is a copy, add it to the ACP. */
2749 if (inst
->op
== OPCODE_MOV
&&
2750 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2751 !(inst
->dst
.file
== inst
->src
[0].file
&&
2752 inst
->dst
.index
== inst
->src
[0].index
) &&
2753 !inst
->dst
.reladdr
&&
2755 !inst
->src
[0].reladdr
&&
2756 !inst
->src
[0].negate
) {
2757 for (int i
= 0; i
< 4; i
++) {
2758 if (inst
->dst
.writemask
& (1 << i
)) {
2759 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2760 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2766 ralloc_free(acp_level
);
2772 * Convert a shader's GLSL IR into a Mesa gl_program.
2774 static struct gl_program
*
2775 get_mesa_program(struct gl_context
*ctx
,
2776 struct gl_shader_program
*shader_program
,
2777 struct gl_shader
*shader
)
2779 ir_to_mesa_visitor v
;
2780 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2781 ir_instruction
**mesa_instruction_annotation
;
2783 struct gl_program
*prog
;
2784 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2785 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2786 struct gl_shader_compiler_options
*options
=
2787 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2789 validate_ir_tree(shader
->ir
);
2791 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2794 prog
->Parameters
= _mesa_new_parameter_list();
2797 v
.shader_program
= shader_program
;
2798 v
.options
= options
;
2800 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2803 /* Emit Mesa IR for main(). */
2804 visit_exec_list(shader
->ir
, &v
);
2805 v
.emit(NULL
, OPCODE_END
);
2807 prog
->NumTemporaries
= v
.next_temp
;
2809 unsigned num_instructions
= v
.instructions
.length();
2812 (struct prog_instruction
*)calloc(num_instructions
,
2813 sizeof(*mesa_instructions
));
2814 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2819 /* Convert ir_mesa_instructions into prog_instructions.
2821 mesa_inst
= mesa_instructions
;
2823 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2824 mesa_inst
->Opcode
= inst
->op
;
2825 mesa_inst
->CondUpdate
= inst
->cond_update
;
2827 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2828 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2829 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2830 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2831 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2832 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2833 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2834 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2835 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2836 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2837 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2838 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2839 mesa_instruction_annotation
[i
] = inst
->ir
;
2841 /* Set IndirectRegisterFiles. */
2842 if (mesa_inst
->DstReg
.RelAddr
)
2843 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2845 /* Update program's bitmask of indirectly accessed register files */
2846 for (unsigned src
= 0; src
< 3; src
++)
2847 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2848 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2850 switch (mesa_inst
->Opcode
) {
2852 if (options
->MaxIfDepth
== 0) {
2853 linker_warning(shader_program
,
2854 "Couldn't flatten if-statement. "
2855 "This will likely result in software "
2856 "rasterization.\n");
2859 case OPCODE_BGNLOOP
:
2860 if (options
->EmitNoLoops
) {
2861 linker_warning(shader_program
,
2862 "Couldn't unroll loop. "
2863 "This will likely result in software "
2864 "rasterization.\n");
2868 if (options
->EmitNoCont
) {
2869 linker_warning(shader_program
,
2870 "Couldn't lower continue-statement. "
2871 "This will likely result in software "
2872 "rasterization.\n");
2876 prog
->NumAddressRegs
= 1;
2885 if (!shader_program
->LinkStatus
)
2889 if (!shader_program
->LinkStatus
) {
2893 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2895 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2896 fprintf(stderr
, "\n");
2897 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2898 shader_program
->Name
);
2899 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2900 fprintf(stderr
, "\n");
2901 fprintf(stderr
, "\n");
2902 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2903 shader_program
->Name
);
2904 print_program(mesa_instructions
, mesa_instruction_annotation
,
2909 prog
->Instructions
= mesa_instructions
;
2910 prog
->NumInstructions
= num_instructions
;
2912 /* Setting this to NULL prevents a possible double free in the fail_exit
2915 mesa_instructions
= NULL
;
2917 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2919 prog
->SamplersUsed
= shader
->active_samplers
;
2920 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2921 _mesa_update_shader_textures_used(shader_program
, prog
);
2923 /* Set the gl_FragDepth layout. */
2924 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2925 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2926 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2929 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2931 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2932 _mesa_optimize_program(ctx
, prog
);
2935 /* This has to be done last. Any operation that can cause
2936 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2937 * program constant) has to happen before creating this linkage.
2939 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2940 if (!shader_program
->LinkStatus
) {
2947 free(mesa_instructions
);
2948 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2956 * Called via ctx->Driver.LinkShader()
2957 * This actually involves converting GLSL IR into Mesa gl_programs with
2958 * code lowering and other optimizations.
2961 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2963 assert(prog
->LinkStatus
);
2965 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2966 if (prog
->_LinkedShaders
[i
] == NULL
)
2970 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2971 const struct gl_shader_compiler_options
*options
=
2972 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2978 do_mat_op_to_vec(ir
);
2979 lower_instructions(ir
, (MOD_TO_FLOOR
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2980 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2981 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2983 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2985 progress
= do_common_optimization(ir
, true, true,
2986 options
, ctx
->Const
.NativeIntegers
)
2989 progress
= lower_quadop_vector(ir
, true) || progress
;
2991 if (options
->MaxIfDepth
== 0)
2992 progress
= lower_discard(ir
) || progress
;
2994 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
2996 if (options
->EmitNoNoise
)
2997 progress
= lower_noise(ir
) || progress
;
2999 /* If there are forms of indirect addressing that the driver
3000 * cannot handle, perform the lowering pass.
3002 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
3003 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
3005 lower_variable_index_to_cond_assign(ir
,
3006 options
->EmitNoIndirectInput
,
3007 options
->EmitNoIndirectOutput
,
3008 options
->EmitNoIndirectTemp
,
3009 options
->EmitNoIndirectUniform
)
3012 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
3013 progress
= lower_vector_insert(ir
, true) || progress
;
3016 validate_ir_tree(ir
);
3019 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3020 struct gl_program
*linked_prog
;
3022 if (prog
->_LinkedShaders
[i
] == NULL
)
3025 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
3028 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
3030 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
3032 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
3033 _mesa_shader_stage_to_program(i
),
3039 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3042 return prog
->LinkStatus
;
3046 * Link a GLSL shader program. Called via glLinkProgram().
3049 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3053 _mesa_clear_shader_program_data(prog
);
3055 prog
->LinkStatus
= GL_TRUE
;
3057 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3058 if (!prog
->Shaders
[i
]->CompileStatus
) {
3059 linker_error(prog
, "linking with uncompiled shader");
3063 if (prog
->LinkStatus
) {
3064 link_shaders(ctx
, prog
);
3067 if (prog
->LinkStatus
) {
3068 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3069 prog
->LinkStatus
= GL_FALSE
;
3073 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
3074 if (!prog
->LinkStatus
) {
3075 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
3078 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3079 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
3080 fprintf(stderr
, "%s\n", prog
->InfoLog
);