2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderobj.h"
47 #include "program/hash_table.h"
50 #include "main/shaderapi.h"
51 #include "main/uniforms.h"
52 #include "program/prog_instruction.h"
53 #include "program/prog_optimize.h"
54 #include "program/prog_print.h"
55 #include "program/program.h"
56 #include "program/prog_parameter.h"
57 #include "program/sampler.h"
60 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to Mesa prog_src_register, with
73 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
87 this->file
= PROGRAM_UNDEFINED
;
94 explicit src_reg(dst_reg reg
);
96 gl_register_file file
; /**< PROGRAM_* from Mesa */
97 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
98 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
99 int negate
; /**< NEGATE_XYZW mask from mesa */
100 /** Register index should be offset by the integer in this reg. */
106 dst_reg(gl_register_file file
, int writemask
)
110 this->writemask
= writemask
;
111 this->cond_mask
= COND_TR
;
112 this->reladdr
= NULL
;
117 this->file
= PROGRAM_UNDEFINED
;
120 this->cond_mask
= COND_TR
;
121 this->reladdr
= NULL
;
124 explicit dst_reg(src_reg reg
);
126 gl_register_file file
; /**< PROGRAM_* from Mesa */
127 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
128 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
130 /** Register index should be offset by the integer in this reg. */
134 } /* anonymous namespace */
136 src_reg::src_reg(dst_reg reg
)
138 this->file
= reg
.file
;
139 this->index
= reg
.index
;
140 this->swizzle
= SWIZZLE_XYZW
;
142 this->reladdr
= reg
.reladdr
;
145 dst_reg::dst_reg(src_reg reg
)
147 this->file
= reg
.file
;
148 this->index
= reg
.index
;
149 this->writemask
= WRITEMASK_XYZW
;
150 this->cond_mask
= COND_TR
;
151 this->reladdr
= reg
.reladdr
;
156 class ir_to_mesa_instruction
: public exec_node
{
158 DECLARE_RZALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
163 /** Pointer to the ir source this tree came from for debugging */
165 GLboolean cond_update
;
167 int sampler
; /**< sampler index */
168 int tex_target
; /**< One of TEXTURE_*_INDEX */
169 GLboolean tex_shadow
;
172 class variable_storage
: public exec_node
{
174 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
175 : file(file
), index(index
), var(var
)
180 gl_register_file file
;
182 ir_variable
*var
; /* variable that maps to this, if any */
185 class function_entry
: public exec_node
{
187 ir_function_signature
*sig
;
190 * identifier of this function signature used by the program.
192 * At the point that Mesa instructions for function calls are
193 * generated, we don't know the address of the first instruction of
194 * the function body. So we make the BranchTarget that is called a
195 * small integer and rewrite them during set_branchtargets().
200 * Pointer to first instruction of the function body.
202 * Set during function body emits after main() is processed.
204 ir_to_mesa_instruction
*bgn_inst
;
207 * Index of the first instruction of the function body in actual
210 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
214 /** Storage for the return value. */
218 class ir_to_mesa_visitor
: public ir_visitor
{
220 ir_to_mesa_visitor();
221 ~ir_to_mesa_visitor();
223 function_entry
*current_function
;
225 struct gl_context
*ctx
;
226 struct gl_program
*prog
;
227 struct gl_shader_program
*shader_program
;
228 struct gl_shader_compiler_options
*options
;
232 variable_storage
*find_variable_storage(ir_variable
*var
);
234 src_reg
get_temp(const glsl_type
*type
);
235 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
237 src_reg
src_reg_for_float(float val
);
240 * \name Visit methods
242 * As typical for the visitor pattern, there must be one \c visit method for
243 * each concrete subclass of \c ir_instruction. Virtual base classes within
244 * the hierarchy should not have \c visit methods.
247 virtual void visit(ir_variable
*);
248 virtual void visit(ir_loop
*);
249 virtual void visit(ir_loop_jump
*);
250 virtual void visit(ir_function_signature
*);
251 virtual void visit(ir_function
*);
252 virtual void visit(ir_expression
*);
253 virtual void visit(ir_swizzle
*);
254 virtual void visit(ir_dereference_variable
*);
255 virtual void visit(ir_dereference_array
*);
256 virtual void visit(ir_dereference_record
*);
257 virtual void visit(ir_assignment
*);
258 virtual void visit(ir_constant
*);
259 virtual void visit(ir_call
*);
260 virtual void visit(ir_return
*);
261 virtual void visit(ir_discard
*);
262 virtual void visit(ir_texture
*);
263 virtual void visit(ir_if
*);
264 virtual void visit(ir_emit_vertex
*);
265 virtual void visit(ir_end_primitive
*);
270 /** List of variable_storage */
273 /** List of function_entry */
274 exec_list function_signatures
;
275 int next_signature_id
;
277 /** List of ir_to_mesa_instruction */
278 exec_list instructions
;
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
282 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
283 dst_reg dst
, src_reg src0
);
285 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
286 dst_reg dst
, src_reg src0
, src_reg src1
);
288 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
290 src_reg src0
, src_reg src1
, src_reg src2
);
293 * Emit the correct dot-product instruction for the type of arguments
295 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
301 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
302 dst_reg dst
, src_reg src0
);
304 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
305 dst_reg dst
, src_reg src0
, src_reg src1
);
307 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
308 dst_reg dst
, const src_reg
&src
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
314 bool try_emit_sat(ir_expression
*ir
);
316 void emit_swz(ir_expression
*ir
);
318 bool process_move_condition(ir_rvalue
*ir
);
320 void copy_propagate(void);
325 } /* anonymous namespace */
327 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
329 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
331 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
334 swizzle_for_size(int size
)
336 static const int size_swizzles
[4] = {
337 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
338 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
339 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
340 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
343 assert((size
>= 1) && (size
<= 4));
344 return size_swizzles
[size
- 1];
347 ir_to_mesa_instruction
*
348 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
350 src_reg src0
, src_reg src1
, src_reg src2
)
352 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
355 /* If we have to do relative addressing, we want to load the ARL
356 * reg directly for one of the regs, and preload the other reladdr
357 * sources into temps.
359 num_reladdr
+= dst
.reladdr
!= NULL
;
360 num_reladdr
+= src0
.reladdr
!= NULL
;
361 num_reladdr
+= src1
.reladdr
!= NULL
;
362 num_reladdr
+= src2
.reladdr
!= NULL
;
364 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
365 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
366 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
369 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
372 assert(num_reladdr
== 0);
381 this->instructions
.push_tail(inst
);
387 ir_to_mesa_instruction
*
388 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
389 dst_reg dst
, src_reg src0
, src_reg src1
)
391 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
394 ir_to_mesa_instruction
*
395 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
396 dst_reg dst
, src_reg src0
)
398 assert(dst
.writemask
!= 0);
399 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
402 ir_to_mesa_instruction
*
403 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
405 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
408 ir_to_mesa_instruction
*
409 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
410 dst_reg dst
, src_reg src0
, src_reg src1
,
413 static const gl_inst_opcode dot_opcodes
[] = {
414 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
417 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
421 * Emits Mesa scalar opcodes to produce unique answers across channels.
423 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
424 * channel determines the result across all channels. So to do a vec4
425 * of this operation, we want to emit a scalar per source channel used
426 * to produce dest channels.
429 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
431 src_reg orig_src0
, src_reg orig_src1
)
434 int done_mask
= ~dst
.writemask
;
436 /* Mesa RCP is a scalar operation splatting results to all channels,
437 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
440 for (i
= 0; i
< 4; i
++) {
441 GLuint this_mask
= (1 << i
);
442 ir_to_mesa_instruction
*inst
;
443 src_reg src0
= orig_src0
;
444 src_reg src1
= orig_src1
;
446 if (done_mask
& this_mask
)
449 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
450 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
451 for (j
= i
+ 1; j
< 4; j
++) {
452 /* If there is another enabled component in the destination that is
453 * derived from the same inputs, generate its value on this pass as
456 if (!(done_mask
& (1 << j
)) &&
457 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
458 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
459 this_mask
|= (1 << j
);
462 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
463 src0_swiz
, src0_swiz
);
464 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
465 src1_swiz
, src1_swiz
);
467 inst
= emit(ir
, op
, dst
, src0
, src1
);
468 inst
->dst
.writemask
= this_mask
;
469 done_mask
|= this_mask
;
474 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
475 dst_reg dst
, src_reg src0
)
477 src_reg undef
= undef_src
;
479 undef
.swizzle
= SWIZZLE_XXXX
;
481 emit_scalar(ir
, op
, dst
, src0
, undef
);
485 * Emit an OPCODE_SCS instruction
487 * The \c SCS opcode functions a bit differently than the other Mesa (or
488 * ARB_fragment_program) opcodes. Instead of splatting its result across all
489 * four components of the destination, it writes one value to the \c x
490 * component and another value to the \c y component.
492 * \param ir IR instruction being processed
493 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
495 * \param dst Destination register
496 * \param src Source register
499 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
503 /* Vertex programs cannot use the SCS opcode.
505 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
506 emit_scalar(ir
, op
, dst
, src
);
510 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
511 const unsigned scs_mask
= (1U << component
);
512 int done_mask
= ~dst
.writemask
;
515 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
517 /* If there are compnents in the destination that differ from the component
518 * that will be written by the SCS instrution, we'll need a temporary.
520 if (scs_mask
!= unsigned(dst
.writemask
)) {
521 tmp
= get_temp(glsl_type::vec4_type
);
524 for (unsigned i
= 0; i
< 4; i
++) {
525 unsigned this_mask
= (1U << i
);
528 if ((done_mask
& this_mask
) != 0)
531 /* The source swizzle specified which component of the source generates
532 * sine / cosine for the current component in the destination. The SCS
533 * instruction requires that this value be swizzle to the X component.
534 * Replace the current swizzle with a swizzle that puts the source in
537 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
539 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
540 src0_swiz
, src0_swiz
);
541 for (unsigned j
= i
+ 1; j
< 4; j
++) {
542 /* If there is another enabled component in the destination that is
543 * derived from the same inputs, generate its value on this pass as
546 if (!(done_mask
& (1 << j
)) &&
547 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
548 this_mask
|= (1 << j
);
552 if (this_mask
!= scs_mask
) {
553 ir_to_mesa_instruction
*inst
;
554 dst_reg tmp_dst
= dst_reg(tmp
);
556 /* Emit the SCS instruction.
558 inst
= emit(ir
, OPCODE_SCS
, tmp_dst
, src0
);
559 inst
->dst
.writemask
= scs_mask
;
561 /* Move the result of the SCS instruction to the desired location in
564 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
565 component
, component
);
566 inst
= emit(ir
, OPCODE_SCS
, dst
, tmp
);
567 inst
->dst
.writemask
= this_mask
;
569 /* Emit the SCS instruction to write directly to the destination.
571 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_SCS
, dst
, src0
);
572 inst
->dst
.writemask
= scs_mask
;
575 done_mask
|= this_mask
;
580 ir_to_mesa_visitor::src_reg_for_float(float val
)
582 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
584 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
585 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
591 type_size(const struct glsl_type
*type
)
596 switch (type
->base_type
) {
599 case GLSL_TYPE_FLOAT
:
601 if (type
->is_matrix()) {
602 return type
->matrix_columns
;
604 /* Regardless of size of vector, it gets a vec4. This is bad
605 * packing for things like floats, but otherwise arrays become a
606 * mess. Hopefully a later pass over the code can pack scalars
607 * down if appropriate.
611 case GLSL_TYPE_ARRAY
:
612 assert(type
->length
> 0);
613 return type_size(type
->fields
.array
) * type
->length
;
614 case GLSL_TYPE_STRUCT
:
616 for (i
= 0; i
< type
->length
; i
++) {
617 size
+= type_size(type
->fields
.structure
[i
].type
);
620 case GLSL_TYPE_SAMPLER
:
621 /* Samplers take up one slot in UNIFORMS[], but they're baked in
626 case GLSL_TYPE_ERROR
:
627 case GLSL_TYPE_INTERFACE
:
628 assert(!"Invalid type in type_size");
636 * In the initial pass of codegen, we assign temporary numbers to
637 * intermediate results. (not SSA -- variable assignments will reuse
638 * storage). Actual register allocation for the Mesa VM occurs in a
639 * pass over the Mesa IR later.
642 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
646 src
.file
= PROGRAM_TEMPORARY
;
647 src
.index
= next_temp
;
649 next_temp
+= type_size(type
);
651 if (type
->is_array() || type
->is_record()) {
652 src
.swizzle
= SWIZZLE_NOOP
;
654 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
662 ir_to_mesa_visitor::find_variable_storage(ir_variable
*var
)
665 variable_storage
*entry
;
667 foreach_iter(exec_list_iterator
, iter
, this->variables
) {
668 entry
= (variable_storage
*)iter
.get();
670 if (entry
->var
== var
)
678 ir_to_mesa_visitor::visit(ir_variable
*ir
)
680 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
681 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
683 fp
->OriginUpperLeft
= ir
->origin_upper_left
;
684 fp
->PixelCenterInteger
= ir
->pixel_center_integer
;
687 if (ir
->mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
689 const ir_state_slot
*const slots
= ir
->state_slots
;
690 assert(ir
->state_slots
!= NULL
);
692 /* Check if this statevar's setup in the STATE file exactly
693 * matches how we'll want to reference it as a
694 * struct/array/whatever. If not, then we need to move it into
695 * temporary storage and hope that it'll get copy-propagated
698 for (i
= 0; i
< ir
->num_state_slots
; i
++) {
699 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
704 variable_storage
*storage
;
706 if (i
== ir
->num_state_slots
) {
707 /* We'll set the index later. */
708 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
709 this->variables
.push_tail(storage
);
713 /* The variable_storage constructor allocates slots based on the size
714 * of the type. However, this had better match the number of state
715 * elements that we're going to copy into the new temporary.
717 assert((int) ir
->num_state_slots
== type_size(ir
->type
));
719 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
721 this->variables
.push_tail(storage
);
722 this->next_temp
+= type_size(ir
->type
);
724 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
728 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
729 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
730 (gl_state_index
*)slots
[i
].tokens
);
732 if (storage
->file
== PROGRAM_STATE_VAR
) {
733 if (storage
->index
== -1) {
734 storage
->index
= index
;
736 assert(index
== storage
->index
+ (int)i
);
739 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
740 src
.swizzle
= slots
[i
].swizzle
;
741 emit(ir
, OPCODE_MOV
, dst
, src
);
742 /* even a float takes up a whole vec4 reg in a struct/array. */
747 if (storage
->file
== PROGRAM_TEMPORARY
&&
748 dst
.index
!= storage
->index
+ (int) ir
->num_state_slots
) {
749 linker_error(this->shader_program
,
750 "failed to load builtin uniform `%s' "
751 "(%d/%d regs loaded)\n",
752 ir
->name
, dst
.index
- storage
->index
,
753 type_size(ir
->type
));
759 ir_to_mesa_visitor::visit(ir_loop
*ir
)
761 ir_dereference_variable
*counter
= NULL
;
763 if (ir
->counter
!= NULL
)
764 counter
= new(mem_ctx
) ir_dereference_variable(ir
->counter
);
766 if (ir
->from
!= NULL
) {
767 assert(ir
->counter
!= NULL
);
770 new(mem_ctx
) ir_assignment(counter
, ir
->from
, NULL
);
775 emit(NULL
, OPCODE_BGNLOOP
);
779 new(mem_ctx
) ir_expression(ir
->cmp
, glsl_type::bool_type
,
781 ir_if
*if_stmt
= new(mem_ctx
) ir_if(e
);
784 new(mem_ctx
) ir_loop_jump(ir_loop_jump::jump_break
);
786 if_stmt
->then_instructions
.push_tail(brk
);
788 if_stmt
->accept(this);
791 visit_exec_list(&ir
->body_instructions
, this);
795 new(mem_ctx
) ir_expression(ir_binop_add
, counter
->type
,
796 counter
, ir
->increment
);
799 new(mem_ctx
) ir_assignment(counter
, e
, NULL
);
804 emit(NULL
, OPCODE_ENDLOOP
);
808 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
811 case ir_loop_jump::jump_break
:
812 emit(NULL
, OPCODE_BRK
);
814 case ir_loop_jump::jump_continue
:
815 emit(NULL
, OPCODE_CONT
);
822 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
829 ir_to_mesa_visitor::visit(ir_function
*ir
)
831 /* Ignore function bodies other than main() -- we shouldn't see calls to
832 * them since they should all be inlined before we get to ir_to_mesa.
834 if (strcmp(ir
->name
, "main") == 0) {
835 const ir_function_signature
*sig
;
838 sig
= ir
->matching_signature(NULL
, &empty
);
842 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
843 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
851 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
853 int nonmul_operand
= 1 - mul_operand
;
856 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
857 if (!expr
|| expr
->operation
!= ir_binop_mul
)
860 expr
->operands
[0]->accept(this);
862 expr
->operands
[1]->accept(this);
864 ir
->operands
[nonmul_operand
]->accept(this);
867 this->result
= get_temp(ir
->type
);
868 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
874 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
876 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
877 * implemented using multiplication, and logical-or is implemented using
878 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
879 * As result, the logical expression (a & !b) can be rewritten as:
883 * - (a * 1) - (a * b)
887 * This final expression can be implemented as a single MAD(a, -b, a)
891 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
893 const int other_operand
= 1 - try_operand
;
896 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
897 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
900 ir
->operands
[other_operand
]->accept(this);
902 expr
->operands
[0]->accept(this);
905 b
.negate
= ~b
.negate
;
907 this->result
= get_temp(ir
->type
);
908 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
914 ir_to_mesa_visitor::try_emit_sat(ir_expression
*ir
)
916 /* Saturates were only introduced to vertex programs in
917 * NV_vertex_program3, so don't give them to drivers in the VP.
919 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
)
922 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
926 sat_src
->accept(this);
927 src_reg src
= this->result
;
929 /* If we generated an expression instruction into a temporary in
930 * processing the saturate's operand, apply the saturate to that
931 * instruction. Otherwise, generate a MOV to do the saturate.
933 * Note that we have to be careful to only do this optimization if
934 * the instruction in question was what generated src->result. For
935 * example, ir_dereference_array might generate a MUL instruction
936 * to create the reladdr, and return us a src reg using that
937 * reladdr. That MUL result is not the value we're trying to
940 ir_expression
*sat_src_expr
= sat_src
->as_expression();
941 ir_to_mesa_instruction
*new_inst
;
942 new_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
943 if (sat_src_expr
&& (sat_src_expr
->operation
== ir_binop_mul
||
944 sat_src_expr
->operation
== ir_binop_add
||
945 sat_src_expr
->operation
== ir_binop_dot
)) {
946 new_inst
->saturate
= true;
948 this->result
= get_temp(ir
->type
);
949 ir_to_mesa_instruction
*inst
;
950 inst
= emit(ir
, OPCODE_MOV
, dst_reg(this->result
), src
);
951 inst
->saturate
= true;
958 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
959 src_reg
*reg
, int *num_reladdr
)
964 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
966 if (*num_reladdr
!= 1) {
967 src_reg temp
= get_temp(glsl_type::vec4_type
);
969 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
977 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
979 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
980 * This means that each of the operands is either an immediate value of -1,
981 * 0, or 1, or is a component from one source register (possibly with
984 uint8_t components
[4] = { 0 };
985 bool negate
[4] = { false };
986 ir_variable
*var
= NULL
;
988 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
989 ir_rvalue
*op
= ir
->operands
[i
];
991 assert(op
->type
->is_scalar());
994 switch (op
->ir_type
) {
995 case ir_type_constant
: {
997 assert(op
->type
->is_scalar());
999 const ir_constant
*const c
= op
->as_constant();
1001 components
[i
] = SWIZZLE_ONE
;
1002 } else if (c
->is_zero()) {
1003 components
[i
] = SWIZZLE_ZERO
;
1004 } else if (c
->is_negative_one()) {
1005 components
[i
] = SWIZZLE_ONE
;
1008 assert(!"SWZ constant must be 0.0 or 1.0.");
1015 case ir_type_dereference_variable
: {
1016 ir_dereference_variable
*const deref
=
1017 (ir_dereference_variable
*) op
;
1019 assert((var
== NULL
) || (deref
->var
== var
));
1020 components
[i
] = SWIZZLE_X
;
1026 case ir_type_expression
: {
1027 ir_expression
*const expr
= (ir_expression
*) op
;
1029 assert(expr
->operation
== ir_unop_neg
);
1032 op
= expr
->operands
[0];
1036 case ir_type_swizzle
: {
1037 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
1039 components
[i
] = swiz
->mask
.x
;
1045 assert(!"Should not get here.");
1051 assert(var
!= NULL
);
1053 ir_dereference_variable
*const deref
=
1054 new(mem_ctx
) ir_dereference_variable(var
);
1056 this->result
.file
= PROGRAM_UNDEFINED
;
1057 deref
->accept(this);
1058 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1059 printf("Failed to get tree for expression operand:\n");
1068 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
1072 src
.negate
= ((unsigned(negate
[0]) << 0)
1073 | (unsigned(negate
[1]) << 1)
1074 | (unsigned(negate
[2]) << 2)
1075 | (unsigned(negate
[3]) << 3));
1077 /* Storage for our result. Ideally for an assignment we'd be using the
1078 * actual storage for the result here, instead.
1080 const src_reg result_src
= get_temp(ir
->type
);
1081 dst_reg result_dst
= dst_reg(result_src
);
1083 /* Limit writes to the channels that will be used by result_src later.
1084 * This does limit this temp's use as a temporary for multi-instruction
1087 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1089 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
1090 this->result
= result_src
;
1094 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1096 unsigned int operand
;
1097 src_reg op
[Elements(ir
->operands
)];
1101 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1103 if (ir
->operation
== ir_binop_add
) {
1104 if (try_emit_mad(ir
, 1))
1106 if (try_emit_mad(ir
, 0))
1110 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1112 if (ir
->operation
== ir_binop_logic_and
) {
1113 if (try_emit_mad_for_and_not(ir
, 1))
1115 if (try_emit_mad_for_and_not(ir
, 0))
1119 if (try_emit_sat(ir
))
1122 if (ir
->operation
== ir_quadop_vector
) {
1127 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1128 this->result
.file
= PROGRAM_UNDEFINED
;
1129 ir
->operands
[operand
]->accept(this);
1130 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1131 printf("Failed to get tree for expression operand:\n");
1132 ir
->operands
[operand
]->print();
1136 op
[operand
] = this->result
;
1138 /* Matrix expression operands should have been broken down to vector
1139 * operations already.
1141 assert(!ir
->operands
[operand
]->type
->is_matrix());
1144 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1145 if (ir
->operands
[1]) {
1146 vector_elements
= MAX2(vector_elements
,
1147 ir
->operands
[1]->type
->vector_elements
);
1150 this->result
.file
= PROGRAM_UNDEFINED
;
1152 /* Storage for our result. Ideally for an assignment we'd be using
1153 * the actual storage for the result here, instead.
1155 result_src
= get_temp(ir
->type
);
1156 /* convenience for the emit functions below. */
1157 result_dst
= dst_reg(result_src
);
1158 /* Limit writes to the channels that will be used by result_src later.
1159 * This does limit this temp's use as a temporary for multi-instruction
1162 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1164 switch (ir
->operation
) {
1165 case ir_unop_logic_not
:
1166 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1167 * older GPUs implement SEQ using multiple instructions (i915 uses two
1168 * SGE instructions and a MUL instruction). Since our logic values are
1169 * 0.0 and 1.0, 1-x also implements !x.
1171 op
[0].negate
= ~op
[0].negate
;
1172 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1175 op
[0].negate
= ~op
[0].negate
;
1179 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1182 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1185 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1189 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1193 assert(!"not reached: should be handled by ir_explog_to_explog2");
1196 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1199 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1202 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1204 case ir_unop_sin_reduced
:
1205 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1207 case ir_unop_cos_reduced
:
1208 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1212 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1215 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1218 case ir_unop_noise
: {
1219 const enum prog_opcode opcode
=
1220 prog_opcode(OPCODE_NOISE1
1221 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1222 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1224 emit(ir
, opcode
, result_dst
, op
[0]);
1229 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1232 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1236 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1239 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1242 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1243 assert(ir
->type
->is_integer());
1244 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1248 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1250 case ir_binop_greater
:
1251 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1253 case ir_binop_lequal
:
1254 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1256 case ir_binop_gequal
:
1257 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1259 case ir_binop_equal
:
1260 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1262 case ir_binop_nequal
:
1263 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1265 case ir_binop_all_equal
:
1266 /* "==" operator producing a scalar boolean. */
1267 if (ir
->operands
[0]->type
->is_vector() ||
1268 ir
->operands
[1]->type
->is_vector()) {
1269 src_reg temp
= get_temp(glsl_type::vec4_type
);
1270 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1272 /* After the dot-product, the value will be an integer on the
1273 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1275 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1277 /* Negating the result of the dot-product gives values on the range
1278 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1279 * achieved using SGE.
1281 src_reg sge_src
= result_src
;
1282 sge_src
.negate
= ~sge_src
.negate
;
1283 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1285 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1288 case ir_binop_any_nequal
:
1289 /* "!=" operator producing a scalar boolean. */
1290 if (ir
->operands
[0]->type
->is_vector() ||
1291 ir
->operands
[1]->type
->is_vector()) {
1292 src_reg temp
= get_temp(glsl_type::vec4_type
);
1293 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1295 /* After the dot-product, the value will be an integer on the
1296 * range [0,4]. Zero stays zero, and positive values become 1.0.
1298 ir_to_mesa_instruction
*const dp
=
1299 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1300 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1301 /* The clamping to [0,1] can be done for free in the fragment
1302 * shader with a saturate.
1304 dp
->saturate
= true;
1306 /* Negating the result of the dot-product gives values on the range
1307 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1308 * achieved using SLT.
1310 src_reg slt_src
= result_src
;
1311 slt_src
.negate
= ~slt_src
.negate
;
1312 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1315 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1320 assert(ir
->operands
[0]->type
->is_vector());
1322 /* After the dot-product, the value will be an integer on the
1323 * range [0,4]. Zero stays zero, and positive values become 1.0.
1325 ir_to_mesa_instruction
*const dp
=
1326 emit_dp(ir
, result_dst
, op
[0], op
[0],
1327 ir
->operands
[0]->type
->vector_elements
);
1328 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1329 /* The clamping to [0,1] can be done for free in the fragment
1330 * shader with a saturate.
1332 dp
->saturate
= true;
1334 /* Negating the result of the dot-product gives values on the range
1335 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1336 * is achieved using SLT.
1338 src_reg slt_src
= result_src
;
1339 slt_src
.negate
= ~slt_src
.negate
;
1340 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1345 case ir_binop_logic_xor
:
1346 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1349 case ir_binop_logic_or
: {
1350 /* After the addition, the value will be an integer on the
1351 * range [0,2]. Zero stays zero, and positive values become 1.0.
1353 ir_to_mesa_instruction
*add
=
1354 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1355 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1356 /* The clamping to [0,1] can be done for free in the fragment
1357 * shader with a saturate.
1359 add
->saturate
= true;
1361 /* Negating the result of the addition gives values on the range
1362 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1363 * is achieved using SLT.
1365 src_reg slt_src
= result_src
;
1366 slt_src
.negate
= ~slt_src
.negate
;
1367 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1372 case ir_binop_logic_and
:
1373 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1374 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1378 assert(ir
->operands
[0]->type
->is_vector());
1379 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1380 emit_dp(ir
, result_dst
, op
[0], op
[1],
1381 ir
->operands
[0]->type
->vector_elements
);
1385 /* sqrt(x) = x * rsq(x). */
1386 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1387 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1388 /* For incoming channels <= 0, set the result to 0. */
1389 op
[0].negate
= ~op
[0].negate
;
1390 emit(ir
, OPCODE_CMP
, result_dst
,
1391 op
[0], result_src
, src_reg_for_float(0.0));
1394 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1402 /* Mesa IR lacks types, ints are stored as truncated floats. */
1407 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1411 emit(ir
, OPCODE_SNE
, result_dst
,
1412 op
[0], src_reg_for_float(0.0));
1414 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1415 case ir_unop_bitcast_f2u
:
1416 case ir_unop_bitcast_i2f
:
1417 case ir_unop_bitcast_u2f
:
1420 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1423 op
[0].negate
= ~op
[0].negate
;
1424 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1425 result_src
.negate
= ~result_src
.negate
;
1428 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1431 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1433 case ir_unop_pack_snorm_2x16
:
1434 case ir_unop_pack_snorm_4x8
:
1435 case ir_unop_pack_unorm_2x16
:
1436 case ir_unop_pack_unorm_4x8
:
1437 case ir_unop_pack_half_2x16
:
1438 case ir_unop_unpack_snorm_2x16
:
1439 case ir_unop_unpack_snorm_4x8
:
1440 case ir_unop_unpack_unorm_2x16
:
1441 case ir_unop_unpack_unorm_4x8
:
1442 case ir_unop_unpack_half_2x16
:
1443 case ir_unop_unpack_half_2x16_split_x
:
1444 case ir_unop_unpack_half_2x16_split_y
:
1445 case ir_binop_pack_half_2x16_split
:
1446 case ir_unop_bitfield_reverse
:
1447 case ir_unop_bit_count
:
1448 case ir_unop_find_msb
:
1449 case ir_unop_find_lsb
:
1450 assert(!"not supported");
1453 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1456 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1459 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1462 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1463 * hardware backends have no way to avoid Mesa IR generation
1464 * even if they don't use it, we need to emit "something" and
1467 case ir_binop_lshift
:
1468 case ir_binop_rshift
:
1469 case ir_binop_bit_and
:
1470 case ir_binop_bit_xor
:
1471 case ir_binop_bit_or
:
1472 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1475 case ir_unop_bit_not
:
1476 case ir_unop_round_even
:
1477 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1480 case ir_binop_ubo_load
:
1481 assert(!"not supported");
1485 /* ir_triop_lrp operands are (x, y, a) while
1486 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1488 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1491 case ir_binop_vector_extract
:
1495 case ir_triop_bitfield_extract
:
1496 case ir_triop_vector_insert
:
1497 case ir_quadop_bitfield_insert
:
1498 case ir_binop_ldexp
:
1500 assert(!"not supported");
1503 case ir_quadop_vector
:
1504 /* This operation should have already been handled.
1506 assert(!"Should not get here.");
1510 this->result
= result_src
;
1515 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1521 /* Note that this is only swizzles in expressions, not those on the left
1522 * hand side of an assignment, which do write masking. See ir_assignment
1526 ir
->val
->accept(this);
1528 assert(src
.file
!= PROGRAM_UNDEFINED
);
1530 for (i
= 0; i
< 4; i
++) {
1531 if (i
< ir
->type
->vector_elements
) {
1534 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1537 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1540 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1543 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1547 /* If the type is smaller than a vec4, replicate the last
1550 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1554 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1560 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1562 variable_storage
*entry
= find_variable_storage(ir
->var
);
1563 ir_variable
*var
= ir
->var
;
1566 switch (var
->mode
) {
1567 case ir_var_uniform
:
1568 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1570 this->variables
.push_tail(entry
);
1572 case ir_var_shader_in
:
1573 /* The linker assigns locations for varyings and attributes,
1574 * including deprecated builtins (like gl_Color),
1575 * user-assigned generic attributes (glBindVertexLocation),
1576 * and user-defined varyings.
1578 assert(var
->location
!= -1);
1579 entry
= new(mem_ctx
) variable_storage(var
,
1583 case ir_var_shader_out
:
1584 assert(var
->location
!= -1);
1585 entry
= new(mem_ctx
) variable_storage(var
,
1589 case ir_var_system_value
:
1590 entry
= new(mem_ctx
) variable_storage(var
,
1591 PROGRAM_SYSTEM_VALUE
,
1595 case ir_var_temporary
:
1596 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1598 this->variables
.push_tail(entry
);
1600 next_temp
+= type_size(var
->type
);
1605 printf("Failed to make storage for %s\n", var
->name
);
1610 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1614 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1618 int element_size
= type_size(ir
->type
);
1620 index
= ir
->array_index
->constant_expression_value();
1622 ir
->array
->accept(this);
1626 src
.index
+= index
->value
.i
[0] * element_size
;
1628 /* Variable index array dereference. It eats the "vec4" of the
1629 * base of the array and an index that offsets the Mesa register
1632 ir
->array_index
->accept(this);
1636 if (element_size
== 1) {
1637 index_reg
= this->result
;
1639 index_reg
= get_temp(glsl_type::float_type
);
1641 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1642 this->result
, src_reg_for_float(element_size
));
1645 /* If there was already a relative address register involved, add the
1646 * new and the old together to get the new offset.
1648 if (src
.reladdr
!= NULL
) {
1649 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1651 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1652 index_reg
, *src
.reladdr
);
1654 index_reg
= accum_reg
;
1657 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1658 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1661 /* If the type is smaller than a vec4, replicate the last channel out. */
1662 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1663 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1665 src
.swizzle
= SWIZZLE_NOOP
;
1671 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1674 const glsl_type
*struct_type
= ir
->record
->type
;
1677 ir
->record
->accept(this);
1679 for (i
= 0; i
< struct_type
->length
; i
++) {
1680 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1682 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1685 /* If the type is smaller than a vec4, replicate the last channel out. */
1686 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1687 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1689 this->result
.swizzle
= SWIZZLE_NOOP
;
1691 this->result
.index
+= offset
;
1695 * We want to be careful in assignment setup to hit the actual storage
1696 * instead of potentially using a temporary like we might with the
1697 * ir_dereference handler.
1700 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1702 /* The LHS must be a dereference. If the LHS is a variable indexed array
1703 * access of a vector, it must be separated into a series conditional moves
1704 * before reaching this point (see ir_vec_index_to_cond_assign).
1706 assert(ir
->as_dereference());
1707 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1709 assert(!deref_array
->array
->type
->is_vector());
1712 /* Use the rvalue deref handler for the most part. We'll ignore
1713 * swizzles in it and write swizzles using writemask, though.
1716 return dst_reg(v
->result
);
1720 * Process the condition of a conditional assignment
1722 * Examines the condition of a conditional assignment to generate the optimal
1723 * first operand of a \c CMP instruction. If the condition is a relational
1724 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1725 * used as the source for the \c CMP instruction. Otherwise the comparison
1726 * is processed to a boolean result, and the boolean result is used as the
1727 * operand to the CMP instruction.
1730 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1732 ir_rvalue
*src_ir
= ir
;
1734 bool switch_order
= false;
1736 ir_expression
*const expr
= ir
->as_expression();
1737 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1738 bool zero_on_left
= false;
1740 if (expr
->operands
[0]->is_zero()) {
1741 src_ir
= expr
->operands
[1];
1742 zero_on_left
= true;
1743 } else if (expr
->operands
[1]->is_zero()) {
1744 src_ir
= expr
->operands
[0];
1745 zero_on_left
= false;
1749 * (a < 0) T F F ( a < 0) T F F
1750 * (0 < a) F F T (-a < 0) F F T
1751 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1752 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1753 * (a > 0) F F T (-a < 0) F F T
1754 * (0 > a) T F F ( a < 0) T F F
1755 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1756 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1758 * Note that exchanging the order of 0 and 'a' in the comparison simply
1759 * means that the value of 'a' should be negated.
1762 switch (expr
->operation
) {
1764 switch_order
= false;
1765 negate
= zero_on_left
;
1768 case ir_binop_greater
:
1769 switch_order
= false;
1770 negate
= !zero_on_left
;
1773 case ir_binop_lequal
:
1774 switch_order
= true;
1775 negate
= !zero_on_left
;
1778 case ir_binop_gequal
:
1779 switch_order
= true;
1780 negate
= zero_on_left
;
1784 /* This isn't the right kind of comparison afterall, so make sure
1785 * the whole condition is visited.
1793 src_ir
->accept(this);
1795 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1796 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1797 * choose which value OPCODE_CMP produces without an extra instruction
1798 * computing the condition.
1801 this->result
.negate
= ~this->result
.negate
;
1803 return switch_order
;
1807 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1813 ir
->rhs
->accept(this);
1816 l
= get_assignment_lhs(ir
->lhs
, this);
1818 /* FINISHME: This should really set to the correct maximal writemask for each
1819 * FINISHME: component written (in the loops below). This case can only
1820 * FINISHME: occur for matrices, arrays, and structures.
1822 if (ir
->write_mask
== 0) {
1823 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1824 l
.writemask
= WRITEMASK_XYZW
;
1825 } else if (ir
->lhs
->type
->is_scalar()) {
1826 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1827 * FINISHME: W component of fragment shader output zero, work correctly.
1829 l
.writemask
= WRITEMASK_XYZW
;
1832 int first_enabled_chan
= 0;
1835 assert(ir
->lhs
->type
->is_vector());
1836 l
.writemask
= ir
->write_mask
;
1838 for (int i
= 0; i
< 4; i
++) {
1839 if (l
.writemask
& (1 << i
)) {
1840 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1845 /* Swizzle a small RHS vector into the channels being written.
1847 * glsl ir treats write_mask as dictating how many channels are
1848 * present on the RHS while Mesa IR treats write_mask as just
1849 * showing which channels of the vec4 RHS get written.
1851 for (int i
= 0; i
< 4; i
++) {
1852 if (l
.writemask
& (1 << i
))
1853 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1855 swizzles
[i
] = first_enabled_chan
;
1857 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1858 swizzles
[2], swizzles
[3]);
1861 assert(l
.file
!= PROGRAM_UNDEFINED
);
1862 assert(r
.file
!= PROGRAM_UNDEFINED
);
1864 if (ir
->condition
) {
1865 const bool switch_order
= this->process_move_condition(ir
->condition
);
1866 src_reg condition
= this->result
;
1868 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1870 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1872 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1879 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1880 emit(ir
, OPCODE_MOV
, l
, r
);
1889 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1892 GLfloat stack_vals
[4] = { 0 };
1893 GLfloat
*values
= stack_vals
;
1896 /* Unfortunately, 4 floats is all we can get into
1897 * _mesa_add_unnamed_constant. So, make a temp to store an
1898 * aggregate constant and move each constant value into it. If we
1899 * get lucky, copy propagation will eliminate the extra moves.
1902 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1903 src_reg temp_base
= get_temp(ir
->type
);
1904 dst_reg temp
= dst_reg(temp_base
);
1906 foreach_iter(exec_list_iterator
, iter
, ir
->components
) {
1907 ir_constant
*field_value
= (ir_constant
*)iter
.get();
1908 int size
= type_size(field_value
->type
);
1912 field_value
->accept(this);
1915 for (i
= 0; i
< (unsigned int)size
; i
++) {
1916 emit(ir
, OPCODE_MOV
, temp
, src
);
1922 this->result
= temp_base
;
1926 if (ir
->type
->is_array()) {
1927 src_reg temp_base
= get_temp(ir
->type
);
1928 dst_reg temp
= dst_reg(temp_base
);
1929 int size
= type_size(ir
->type
->fields
.array
);
1933 for (i
= 0; i
< ir
->type
->length
; i
++) {
1934 ir
->array_elements
[i
]->accept(this);
1936 for (int j
= 0; j
< size
; j
++) {
1937 emit(ir
, OPCODE_MOV
, temp
, src
);
1943 this->result
= temp_base
;
1947 if (ir
->type
->is_matrix()) {
1948 src_reg mat
= get_temp(ir
->type
);
1949 dst_reg mat_column
= dst_reg(mat
);
1951 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1952 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1953 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1955 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1956 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1957 (gl_constant_value
*) values
,
1958 ir
->type
->vector_elements
,
1960 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1969 src
.file
= PROGRAM_CONSTANT
;
1970 switch (ir
->type
->base_type
) {
1971 case GLSL_TYPE_FLOAT
:
1972 values
= &ir
->value
.f
[0];
1974 case GLSL_TYPE_UINT
:
1975 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1976 values
[i
] = ir
->value
.u
[i
];
1980 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1981 values
[i
] = ir
->value
.i
[i
];
1984 case GLSL_TYPE_BOOL
:
1985 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1986 values
[i
] = ir
->value
.b
[i
];
1990 assert(!"Non-float/uint/int/bool constant");
1993 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1994 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1995 (gl_constant_value
*) values
,
1996 ir
->type
->vector_elements
,
1997 &this->result
.swizzle
);
2001 ir_to_mesa_visitor::visit(ir_call
*ir
)
2003 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
2007 ir_to_mesa_visitor::visit(ir_texture
*ir
)
2009 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
2010 dst_reg result_dst
, coord_dst
;
2011 ir_to_mesa_instruction
*inst
= NULL
;
2012 prog_opcode opcode
= OPCODE_NOP
;
2014 if (ir
->op
== ir_txs
)
2015 this->result
= src_reg_for_float(0.0);
2017 ir
->coordinate
->accept(this);
2019 /* Put our coords in a temp. We'll need to modify them for shadow,
2020 * projection, or LOD, so the only case we'd use it as is is if
2021 * we're doing plain old texturing. Mesa IR optimization should
2022 * handle cleaning up our mess in that case.
2024 coord
= get_temp(glsl_type::vec4_type
);
2025 coord_dst
= dst_reg(coord
);
2026 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2028 if (ir
->projector
) {
2029 ir
->projector
->accept(this);
2030 projector
= this->result
;
2033 /* Storage for our result. Ideally for an assignment we'd be using
2034 * the actual storage for the result here, instead.
2036 result_src
= get_temp(glsl_type::vec4_type
);
2037 result_dst
= dst_reg(result_src
);
2042 opcode
= OPCODE_TEX
;
2045 opcode
= OPCODE_TXB
;
2046 ir
->lod_info
.bias
->accept(this);
2047 lod_info
= this->result
;
2050 /* Pretend to be TXL so the sampler, coordinate, lod are available */
2052 opcode
= OPCODE_TXL
;
2053 ir
->lod_info
.lod
->accept(this);
2054 lod_info
= this->result
;
2057 opcode
= OPCODE_TXD
;
2058 ir
->lod_info
.grad
.dPdx
->accept(this);
2060 ir
->lod_info
.grad
.dPdy
->accept(this);
2064 assert(!"Unexpected ir_txf_ms opcode");
2067 assert(!"Unexpected ir_lod opcode");
2071 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2073 if (ir
->projector
) {
2074 if (opcode
== OPCODE_TEX
) {
2075 /* Slot the projector in as the last component of the coord. */
2076 coord_dst
.writemask
= WRITEMASK_W
;
2077 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
2078 coord_dst
.writemask
= WRITEMASK_XYZW
;
2079 opcode
= OPCODE_TXP
;
2081 src_reg coord_w
= coord
;
2082 coord_w
.swizzle
= SWIZZLE_WWWW
;
2084 /* For the other TEX opcodes there's no projective version
2085 * since the last slot is taken up by lod info. Do the
2086 * projective divide now.
2088 coord_dst
.writemask
= WRITEMASK_W
;
2089 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
2091 /* In the case where we have to project the coordinates "by hand,"
2092 * the shadow comparitor value must also be projected.
2094 src_reg tmp_src
= coord
;
2095 if (ir
->shadow_comparitor
) {
2096 /* Slot the shadow value in as the second to last component of the
2099 ir
->shadow_comparitor
->accept(this);
2101 tmp_src
= get_temp(glsl_type::vec4_type
);
2102 dst_reg tmp_dst
= dst_reg(tmp_src
);
2104 /* Projective division not allowed for array samplers. */
2105 assert(!sampler_type
->sampler_array
);
2107 tmp_dst
.writemask
= WRITEMASK_Z
;
2108 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
2110 tmp_dst
.writemask
= WRITEMASK_XY
;
2111 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
2114 coord_dst
.writemask
= WRITEMASK_XYZ
;
2115 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
2117 coord_dst
.writemask
= WRITEMASK_XYZW
;
2118 coord
.swizzle
= SWIZZLE_XYZW
;
2122 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2123 * comparitor was put in the correct place (and projected) by the code,
2124 * above, that handles by-hand projection.
2126 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
2127 /* Slot the shadow value in as the second to last component of the
2130 ir
->shadow_comparitor
->accept(this);
2132 /* XXX This will need to be updated for cubemap array samplers. */
2133 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
2134 sampler_type
->sampler_array
) {
2135 coord_dst
.writemask
= WRITEMASK_W
;
2137 coord_dst
.writemask
= WRITEMASK_Z
;
2140 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2141 coord_dst
.writemask
= WRITEMASK_XYZW
;
2144 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2145 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2146 coord_dst
.writemask
= WRITEMASK_W
;
2147 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2148 coord_dst
.writemask
= WRITEMASK_XYZW
;
2151 if (opcode
== OPCODE_TXD
)
2152 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2154 inst
= emit(ir
, opcode
, result_dst
, coord
);
2156 if (ir
->shadow_comparitor
)
2157 inst
->tex_shadow
= GL_TRUE
;
2159 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2160 this->shader_program
,
2163 switch (sampler_type
->sampler_dimensionality
) {
2164 case GLSL_SAMPLER_DIM_1D
:
2165 inst
->tex_target
= (sampler_type
->sampler_array
)
2166 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2168 case GLSL_SAMPLER_DIM_2D
:
2169 inst
->tex_target
= (sampler_type
->sampler_array
)
2170 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2172 case GLSL_SAMPLER_DIM_3D
:
2173 inst
->tex_target
= TEXTURE_3D_INDEX
;
2175 case GLSL_SAMPLER_DIM_CUBE
:
2176 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2178 case GLSL_SAMPLER_DIM_RECT
:
2179 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2181 case GLSL_SAMPLER_DIM_BUF
:
2182 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2184 case GLSL_SAMPLER_DIM_EXTERNAL
:
2185 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2188 assert(!"Should not get here.");
2191 this->result
= result_src
;
2195 ir_to_mesa_visitor::visit(ir_return
*ir
)
2197 /* Non-void functions should have been inlined. We may still emit RETs
2198 * from main() unless the EmitNoMainReturn option is set.
2200 assert(!ir
->get_value());
2201 emit(ir
, OPCODE_RET
);
2205 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2207 if (ir
->condition
) {
2208 ir
->condition
->accept(this);
2209 this->result
.negate
= ~this->result
.negate
;
2210 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2212 emit(ir
, OPCODE_KIL_NV
);
2217 ir_to_mesa_visitor::visit(ir_if
*ir
)
2219 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2220 ir_to_mesa_instruction
*prev_inst
;
2222 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2224 ir
->condition
->accept(this);
2225 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2227 if (this->options
->EmitCondCodes
) {
2228 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2230 /* See if we actually generated any instruction for generating
2231 * the condition. If not, then cook up a move to a temp so we
2232 * have something to set cond_update on.
2234 if (cond_inst
== prev_inst
) {
2235 src_reg temp
= get_temp(glsl_type::bool_type
);
2236 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2238 cond_inst
->cond_update
= GL_TRUE
;
2240 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2241 if_inst
->dst
.cond_mask
= COND_NE
;
2243 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2246 this->instructions
.push_tail(if_inst
);
2248 visit_exec_list(&ir
->then_instructions
, this);
2250 if (!ir
->else_instructions
.is_empty()) {
2251 emit(ir
->condition
, OPCODE_ELSE
);
2252 visit_exec_list(&ir
->else_instructions
, this);
2255 emit(ir
->condition
, OPCODE_ENDIF
);
2259 ir_to_mesa_visitor::visit(ir_emit_vertex
*ir
)
2261 assert(!"Geometry shaders not supported.");
2265 ir_to_mesa_visitor::visit(ir_end_primitive
*ir
)
2267 assert(!"Geometry shaders not supported.");
2270 ir_to_mesa_visitor::ir_to_mesa_visitor()
2272 result
.file
= PROGRAM_UNDEFINED
;
2274 next_signature_id
= 1;
2275 current_function
= NULL
;
2276 mem_ctx
= ralloc_context(NULL
);
2279 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2281 ralloc_free(mem_ctx
);
2284 static struct prog_src_register
2285 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2287 struct prog_src_register mesa_reg
;
2289 mesa_reg
.File
= reg
.file
;
2290 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2291 mesa_reg
.Index
= reg
.index
;
2292 mesa_reg
.Swizzle
= reg
.swizzle
;
2293 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2294 mesa_reg
.Negate
= reg
.negate
;
2296 mesa_reg
.HasIndex2
= GL_FALSE
;
2297 mesa_reg
.RelAddr2
= 0;
2298 mesa_reg
.Index2
= 0;
2304 set_branchtargets(ir_to_mesa_visitor
*v
,
2305 struct prog_instruction
*mesa_instructions
,
2306 int num_instructions
)
2308 int if_count
= 0, loop_count
= 0;
2309 int *if_stack
, *loop_stack
;
2310 int if_stack_pos
= 0, loop_stack_pos
= 0;
2313 for (i
= 0; i
< num_instructions
; i
++) {
2314 switch (mesa_instructions
[i
].Opcode
) {
2318 case OPCODE_BGNLOOP
:
2323 mesa_instructions
[i
].BranchTarget
= -1;
2330 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2331 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2333 for (i
= 0; i
< num_instructions
; i
++) {
2334 switch (mesa_instructions
[i
].Opcode
) {
2336 if_stack
[if_stack_pos
] = i
;
2340 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2341 if_stack
[if_stack_pos
- 1] = i
;
2344 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2347 case OPCODE_BGNLOOP
:
2348 loop_stack
[loop_stack_pos
] = i
;
2351 case OPCODE_ENDLOOP
:
2353 /* Rewrite any breaks/conts at this nesting level (haven't
2354 * already had a BranchTarget assigned) to point to the end
2357 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2358 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2359 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2360 if (mesa_instructions
[j
].BranchTarget
== -1) {
2361 mesa_instructions
[j
].BranchTarget
= i
;
2365 /* The loop ends point at each other. */
2366 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2367 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2370 foreach_iter(exec_list_iterator
, iter
, v
->function_signatures
) {
2371 function_entry
*entry
= (function_entry
*)iter
.get();
2373 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2374 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2386 print_program(struct prog_instruction
*mesa_instructions
,
2387 ir_instruction
**mesa_instruction_annotation
,
2388 int num_instructions
)
2390 ir_instruction
*last_ir
= NULL
;
2394 for (i
= 0; i
< num_instructions
; i
++) {
2395 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2396 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2398 fprintf(stdout
, "%3d: ", i
);
2400 if (last_ir
!= ir
&& ir
) {
2403 for (j
= 0; j
< indent
; j
++) {
2404 fprintf(stdout
, " ");
2410 fprintf(stdout
, " "); /* line number spacing. */
2413 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2414 PROG_PRINT_DEBUG
, NULL
);
2420 class add_uniform_to_shader
: public program_resource_visitor
{
2422 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2423 struct gl_program_parameter_list
*params
,
2424 gl_shader_type shader_type
)
2425 : shader_program(shader_program
), params(params
), idx(-1),
2426 shader_type(shader_type
)
2431 void process(ir_variable
*var
)
2434 this->program_resource_visitor::process(var
);
2436 var
->location
= this->idx
;
2440 virtual void visit_field(const glsl_type
*type
, const char *name
,
2443 struct gl_shader_program
*shader_program
;
2444 struct gl_program_parameter_list
*params
;
2446 gl_shader_type shader_type
;
2449 } /* anonymous namespace */
2452 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2459 if (type
->is_vector() || type
->is_scalar()) {
2460 size
= type
->vector_elements
;
2462 size
= type_size(type
) * 4;
2465 gl_register_file file
;
2466 if (type
->is_sampler() ||
2467 (type
->is_array() && type
->fields
.array
->is_sampler())) {
2468 file
= PROGRAM_SAMPLER
;
2470 file
= PROGRAM_UNIFORM
;
2473 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2475 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2478 /* Sampler uniform values are stored in prog->SamplerUnits,
2479 * and the entry in that array is selected by this index we
2480 * store in ParameterValues[].
2482 if (file
== PROGRAM_SAMPLER
) {
2485 this->shader_program
->UniformHash
->get(location
,
2486 params
->Parameters
[index
].Name
);
2492 struct gl_uniform_storage
*storage
=
2493 &this->shader_program
->UniformStorage
[location
];
2495 assert(storage
->sampler
[shader_type
].active
);
2497 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2498 params
->ParameterValues
[index
+ j
][0].f
=
2499 storage
->sampler
[shader_type
].index
+ j
;
2503 /* The first part of the uniform that's processed determines the base
2504 * location of the whole uniform (for structures).
2511 * Generate the program parameters list for the user uniforms in a shader
2513 * \param shader_program Linked shader program. This is only used to
2514 * emit possible link errors to the info log.
2515 * \param sh Shader whose uniforms are to be processed.
2516 * \param params Parameter list to be filled in.
2519 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2521 struct gl_shader
*sh
,
2522 struct gl_program_parameter_list
2525 add_uniform_to_shader
add(shader_program
, params
,
2526 _mesa_shader_type_to_index(sh
->Type
));
2528 foreach_list(node
, sh
->ir
) {
2529 ir_variable
*var
= ((ir_instruction
*) node
)->as_variable();
2531 if ((var
== NULL
) || (var
->mode
!= ir_var_uniform
)
2532 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2540 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2541 struct gl_shader_program
*shader_program
,
2542 struct gl_program_parameter_list
*params
)
2544 /* After adding each uniform to the parameter list, connect the storage for
2545 * the parameter with the tracking structure used by the API for the
2548 unsigned last_location
= unsigned(~0);
2549 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2550 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2555 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2561 if (location
!= last_location
) {
2562 struct gl_uniform_storage
*storage
=
2563 &shader_program
->UniformStorage
[location
];
2564 enum gl_uniform_driver_format format
= uniform_native
;
2566 unsigned columns
= 0;
2567 switch (storage
->type
->base_type
) {
2568 case GLSL_TYPE_UINT
:
2569 assert(ctx
->Const
.NativeIntegers
);
2570 format
= uniform_native
;
2575 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2578 case GLSL_TYPE_FLOAT
:
2579 format
= uniform_native
;
2580 columns
= storage
->type
->matrix_columns
;
2582 case GLSL_TYPE_BOOL
:
2583 if (ctx
->Const
.NativeIntegers
) {
2584 format
= (ctx
->Const
.UniformBooleanTrue
== 1)
2585 ? uniform_bool_int_0_1
: uniform_bool_int_0_not0
;
2587 format
= uniform_bool_float
;
2591 case GLSL_TYPE_SAMPLER
:
2592 format
= uniform_native
;
2595 case GLSL_TYPE_ARRAY
:
2596 case GLSL_TYPE_VOID
:
2597 case GLSL_TYPE_STRUCT
:
2598 case GLSL_TYPE_ERROR
:
2599 case GLSL_TYPE_INTERFACE
:
2600 assert(!"Should not get here.");
2604 _mesa_uniform_attach_driver_storage(storage
,
2605 4 * sizeof(float) * columns
,
2608 ¶ms
->ParameterValues
[i
]);
2610 /* After attaching the driver's storage to the uniform, propagate any
2611 * data from the linker's backing store. This will cause values from
2612 * initializers in the source code to be copied over.
2614 _mesa_propagate_uniforms_to_driver_storage(storage
,
2616 MAX2(1, storage
->array_elements
));
2618 last_location
= location
;
2624 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2625 * channels for copy propagation and updates following instructions to
2626 * use the original versions.
2628 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2629 * will occur. As an example, a TXP production before this pass:
2631 * 0: MOV TEMP[1], INPUT[4].xyyy;
2632 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2633 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2637 * 0: MOV TEMP[1], INPUT[4].xyyy;
2638 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2639 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2641 * which allows for dead code elimination on TEMP[1]'s writes.
2644 ir_to_mesa_visitor::copy_propagate(void)
2646 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2647 ir_to_mesa_instruction
*,
2648 this->next_temp
* 4);
2649 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2652 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2653 ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2655 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2656 || inst
->dst
.index
< this->next_temp
);
2658 /* First, do any copy propagation possible into the src regs. */
2659 for (int r
= 0; r
< 3; r
++) {
2660 ir_to_mesa_instruction
*first
= NULL
;
2662 int acp_base
= inst
->src
[r
].index
* 4;
2664 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2665 inst
->src
[r
].reladdr
)
2668 /* See if we can find entries in the ACP consisting of MOVs
2669 * from the same src register for all the swizzled channels
2670 * of this src register reference.
2672 for (int i
= 0; i
< 4; i
++) {
2673 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2674 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2681 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2686 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2687 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2695 /* We've now validated that we can copy-propagate to
2696 * replace this src register reference. Do it.
2698 inst
->src
[r
].file
= first
->src
[0].file
;
2699 inst
->src
[r
].index
= first
->src
[0].index
;
2702 for (int i
= 0; i
< 4; i
++) {
2703 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2704 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2705 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2708 inst
->src
[r
].swizzle
= swizzle
;
2713 case OPCODE_BGNLOOP
:
2714 case OPCODE_ENDLOOP
:
2715 /* End of a basic block, clear the ACP entirely. */
2716 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2725 /* Clear all channels written inside the block from the ACP, but
2726 * leaving those that were not touched.
2728 for (int r
= 0; r
< this->next_temp
; r
++) {
2729 for (int c
= 0; c
< 4; c
++) {
2730 if (!acp
[4 * r
+ c
])
2733 if (acp_level
[4 * r
+ c
] >= level
)
2734 acp
[4 * r
+ c
] = NULL
;
2737 if (inst
->op
== OPCODE_ENDIF
)
2742 /* Continuing the block, clear any written channels from
2745 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2746 /* Any temporary might be written, so no copy propagation
2747 * across this instruction.
2749 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2750 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2751 inst
->dst
.reladdr
) {
2752 /* Any output might be written, so no copy propagation
2753 * from outputs across this instruction.
2755 for (int r
= 0; r
< this->next_temp
; r
++) {
2756 for (int c
= 0; c
< 4; c
++) {
2757 if (!acp
[4 * r
+ c
])
2760 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2761 acp
[4 * r
+ c
] = NULL
;
2764 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2765 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2766 /* Clear where it's used as dst. */
2767 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2768 for (int c
= 0; c
< 4; c
++) {
2769 if (inst
->dst
.writemask
& (1 << c
)) {
2770 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2775 /* Clear where it's used as src. */
2776 for (int r
= 0; r
< this->next_temp
; r
++) {
2777 for (int c
= 0; c
< 4; c
++) {
2778 if (!acp
[4 * r
+ c
])
2781 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2783 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2784 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2785 inst
->dst
.writemask
& (1 << src_chan
))
2787 acp
[4 * r
+ c
] = NULL
;
2795 /* If this is a copy, add it to the ACP. */
2796 if (inst
->op
== OPCODE_MOV
&&
2797 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2798 !(inst
->dst
.file
== inst
->src
[0].file
&&
2799 inst
->dst
.index
== inst
->src
[0].index
) &&
2800 !inst
->dst
.reladdr
&&
2802 !inst
->src
[0].reladdr
&&
2803 !inst
->src
[0].negate
) {
2804 for (int i
= 0; i
< 4; i
++) {
2805 if (inst
->dst
.writemask
& (1 << i
)) {
2806 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2807 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2813 ralloc_free(acp_level
);
2819 * Convert a shader's GLSL IR into a Mesa gl_program.
2821 static struct gl_program
*
2822 get_mesa_program(struct gl_context
*ctx
,
2823 struct gl_shader_program
*shader_program
,
2824 struct gl_shader
*shader
)
2826 ir_to_mesa_visitor v
;
2827 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2828 ir_instruction
**mesa_instruction_annotation
;
2830 struct gl_program
*prog
;
2832 const char *target_string
= _mesa_glsl_shader_target_name(shader
->Type
);
2833 struct gl_shader_compiler_options
*options
=
2834 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(shader
->Type
)];
2836 switch (shader
->Type
) {
2837 case GL_VERTEX_SHADER
:
2838 target
= GL_VERTEX_PROGRAM_ARB
;
2840 case GL_FRAGMENT_SHADER
:
2841 target
= GL_FRAGMENT_PROGRAM_ARB
;
2843 case GL_GEOMETRY_SHADER
:
2844 target
= GL_GEOMETRY_PROGRAM_NV
;
2847 assert(!"should not be reached");
2851 validate_ir_tree(shader
->ir
);
2853 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2856 prog
->Parameters
= _mesa_new_parameter_list();
2859 v
.shader_program
= shader_program
;
2860 v
.options
= options
;
2862 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2865 /* Emit Mesa IR for main(). */
2866 visit_exec_list(shader
->ir
, &v
);
2867 v
.emit(NULL
, OPCODE_END
);
2869 prog
->NumTemporaries
= v
.next_temp
;
2871 int num_instructions
= 0;
2872 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2877 (struct prog_instruction
*)calloc(num_instructions
,
2878 sizeof(*mesa_instructions
));
2879 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2884 /* Convert ir_mesa_instructions into prog_instructions.
2886 mesa_inst
= mesa_instructions
;
2888 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2889 const ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2891 mesa_inst
->Opcode
= inst
->op
;
2892 mesa_inst
->CondUpdate
= inst
->cond_update
;
2894 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2895 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2896 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2897 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2898 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2899 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2900 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2901 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2902 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2903 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2904 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2905 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2906 mesa_instruction_annotation
[i
] = inst
->ir
;
2908 /* Set IndirectRegisterFiles. */
2909 if (mesa_inst
->DstReg
.RelAddr
)
2910 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2912 /* Update program's bitmask of indirectly accessed register files */
2913 for (unsigned src
= 0; src
< 3; src
++)
2914 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2915 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2917 switch (mesa_inst
->Opcode
) {
2919 if (options
->MaxIfDepth
== 0) {
2920 linker_warning(shader_program
,
2921 "Couldn't flatten if-statement. "
2922 "This will likely result in software "
2923 "rasterization.\n");
2926 case OPCODE_BGNLOOP
:
2927 if (options
->EmitNoLoops
) {
2928 linker_warning(shader_program
,
2929 "Couldn't unroll loop. "
2930 "This will likely result in software "
2931 "rasterization.\n");
2935 if (options
->EmitNoCont
) {
2936 linker_warning(shader_program
,
2937 "Couldn't lower continue-statement. "
2938 "This will likely result in software "
2939 "rasterization.\n");
2943 prog
->NumAddressRegs
= 1;
2952 if (!shader_program
->LinkStatus
)
2956 if (!shader_program
->LinkStatus
) {
2960 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2962 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
2964 printf("GLSL IR for linked %s program %d:\n", target_string
,
2965 shader_program
->Name
);
2966 _mesa_print_ir(shader
->ir
, NULL
);
2969 printf("Mesa IR for linked %s program %d:\n", target_string
,
2970 shader_program
->Name
);
2971 print_program(mesa_instructions
, mesa_instruction_annotation
,
2975 prog
->Instructions
= mesa_instructions
;
2976 prog
->NumInstructions
= num_instructions
;
2978 /* Setting this to NULL prevents a possible double free in the fail_exit
2981 mesa_instructions
= NULL
;
2983 do_set_program_inouts(shader
->ir
, prog
, shader
->Type
);
2985 prog
->SamplersUsed
= shader
->active_samplers
;
2986 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2987 _mesa_update_shader_textures_used(shader_program
, prog
);
2989 /* Set the gl_FragDepth layout. */
2990 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2991 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2992 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2995 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2997 if ((ctx
->Shader
.Flags
& GLSL_NO_OPT
) == 0) {
2998 _mesa_optimize_program(ctx
, prog
);
3001 /* This has to be done last. Any operation that can cause
3002 * prog->ParameterValues to get reallocated (e.g., anything that adds a
3003 * program constant) has to happen before creating this linkage.
3005 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
3006 if (!shader_program
->LinkStatus
) {
3013 free(mesa_instructions
);
3014 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
3022 * Called via ctx->Driver.LinkShader()
3023 * This actually involves converting GLSL IR into Mesa gl_programs with
3024 * code lowering and other optimizations.
3027 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3029 assert(prog
->LinkStatus
);
3031 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
3032 if (prog
->_LinkedShaders
[i
] == NULL
)
3036 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
3037 const struct gl_shader_compiler_options
*options
=
3038 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(prog
->_LinkedShaders
[i
]->Type
)];
3044 do_mat_op_to_vec(ir
);
3045 lower_instructions(ir
, (MOD_TO_FRACT
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
3046 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
3047 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
3049 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
3051 progress
= do_common_optimization(ir
, true, true,
3052 options
->MaxUnrollIterations
,
3056 progress
= lower_quadop_vector(ir
, true) || progress
;
3058 if (options
->MaxIfDepth
== 0)
3059 progress
= lower_discard(ir
) || progress
;
3061 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
3063 if (options
->EmitNoNoise
)
3064 progress
= lower_noise(ir
) || progress
;
3066 /* If there are forms of indirect addressing that the driver
3067 * cannot handle, perform the lowering pass.
3069 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
3070 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
3072 lower_variable_index_to_cond_assign(ir
,
3073 options
->EmitNoIndirectInput
,
3074 options
->EmitNoIndirectOutput
,
3075 options
->EmitNoIndirectTemp
,
3076 options
->EmitNoIndirectUniform
)
3079 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
3080 progress
= lower_vector_insert(ir
, true) || progress
;
3083 validate_ir_tree(ir
);
3086 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
3087 struct gl_program
*linked_prog
;
3089 if (prog
->_LinkedShaders
[i
] == NULL
)
3092 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
3095 _mesa_copy_linked_program_data((gl_shader_type
) i
, prog
, linked_prog
);
3097 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
3099 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
3100 _mesa_program_index_to_target(i
),
3106 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3109 return prog
->LinkStatus
;
3113 * Link a GLSL shader program. Called via glLinkProgram().
3116 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3120 _mesa_clear_shader_program_data(ctx
, prog
);
3122 prog
->LinkStatus
= GL_TRUE
;
3124 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3125 if (!prog
->Shaders
[i
]->CompileStatus
) {
3126 linker_error(prog
, "linking with uncompiled shader");
3130 if (prog
->LinkStatus
) {
3131 link_shaders(ctx
, prog
);
3134 if (prog
->LinkStatus
) {
3135 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3136 prog
->LinkStatus
= GL_FALSE
;
3140 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
3141 if (!prog
->LinkStatus
) {
3142 printf("GLSL shader program %d failed to link\n", prog
->Name
);
3145 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3146 printf("GLSL shader program %d info log:\n", prog
->Name
);
3147 printf("%s\n", prog
->InfoLog
);