2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderobj.h"
47 #include "main/uniforms.h"
48 #include "program/hash_table.h"
51 #include "main/shaderapi.h"
52 #include "program/prog_instruction.h"
53 #include "program/prog_optimize.h"
54 #include "program/prog_print.h"
55 #include "program/program.h"
56 #include "program/prog_parameter.h"
57 #include "program/sampler.h"
60 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to Mesa prog_src_register, with
73 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
87 this->file
= PROGRAM_UNDEFINED
;
94 explicit src_reg(dst_reg reg
);
96 gl_register_file file
; /**< PROGRAM_* from Mesa */
97 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
98 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
99 int negate
; /**< NEGATE_XYZW mask from mesa */
100 /** Register index should be offset by the integer in this reg. */
106 dst_reg(gl_register_file file
, int writemask
)
110 this->writemask
= writemask
;
111 this->cond_mask
= COND_TR
;
112 this->reladdr
= NULL
;
117 this->file
= PROGRAM_UNDEFINED
;
120 this->cond_mask
= COND_TR
;
121 this->reladdr
= NULL
;
124 explicit dst_reg(src_reg reg
);
126 gl_register_file file
; /**< PROGRAM_* from Mesa */
127 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
128 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
130 /** Register index should be offset by the integer in this reg. */
134 } /* anonymous namespace */
136 src_reg::src_reg(dst_reg reg
)
138 this->file
= reg
.file
;
139 this->index
= reg
.index
;
140 this->swizzle
= SWIZZLE_XYZW
;
142 this->reladdr
= reg
.reladdr
;
145 dst_reg::dst_reg(src_reg reg
)
147 this->file
= reg
.file
;
148 this->index
= reg
.index
;
149 this->writemask
= WRITEMASK_XYZW
;
150 this->cond_mask
= COND_TR
;
151 this->reladdr
= reg
.reladdr
;
156 class ir_to_mesa_instruction
: public exec_node
{
158 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
163 /** Pointer to the ir source this tree came from for debugging */
165 GLboolean cond_update
;
167 int sampler
; /**< sampler index */
168 int tex_target
; /**< One of TEXTURE_*_INDEX */
169 GLboolean tex_shadow
;
172 class variable_storage
: public exec_node
{
174 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
175 : file(file
), index(index
), var(var
)
180 gl_register_file file
;
182 ir_variable
*var
; /* variable that maps to this, if any */
185 class function_entry
: public exec_node
{
187 ir_function_signature
*sig
;
190 * identifier of this function signature used by the program.
192 * At the point that Mesa instructions for function calls are
193 * generated, we don't know the address of the first instruction of
194 * the function body. So we make the BranchTarget that is called a
195 * small integer and rewrite them during set_branchtargets().
200 * Pointer to first instruction of the function body.
202 * Set during function body emits after main() is processed.
204 ir_to_mesa_instruction
*bgn_inst
;
207 * Index of the first instruction of the function body in actual
210 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
214 /** Storage for the return value. */
218 class ir_to_mesa_visitor
: public ir_visitor
{
220 ir_to_mesa_visitor();
221 ~ir_to_mesa_visitor();
223 function_entry
*current_function
;
225 struct gl_context
*ctx
;
226 struct gl_program
*prog
;
227 struct gl_shader_program
*shader_program
;
228 struct gl_shader_compiler_options
*options
;
232 variable_storage
*find_variable_storage(const ir_variable
*var
);
234 src_reg
get_temp(const glsl_type
*type
);
235 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
237 src_reg
src_reg_for_float(float val
);
240 * \name Visit methods
242 * As typical for the visitor pattern, there must be one \c visit method for
243 * each concrete subclass of \c ir_instruction. Virtual base classes within
244 * the hierarchy should not have \c visit methods.
247 virtual void visit(ir_variable
*);
248 virtual void visit(ir_loop
*);
249 virtual void visit(ir_loop_jump
*);
250 virtual void visit(ir_function_signature
*);
251 virtual void visit(ir_function
*);
252 virtual void visit(ir_expression
*);
253 virtual void visit(ir_swizzle
*);
254 virtual void visit(ir_dereference_variable
*);
255 virtual void visit(ir_dereference_array
*);
256 virtual void visit(ir_dereference_record
*);
257 virtual void visit(ir_assignment
*);
258 virtual void visit(ir_constant
*);
259 virtual void visit(ir_call
*);
260 virtual void visit(ir_return
*);
261 virtual void visit(ir_discard
*);
262 virtual void visit(ir_texture
*);
263 virtual void visit(ir_if
*);
264 virtual void visit(ir_emit_vertex
*);
265 virtual void visit(ir_end_primitive
*);
270 /** List of variable_storage */
273 /** List of function_entry */
274 exec_list function_signatures
;
275 int next_signature_id
;
277 /** List of ir_to_mesa_instruction */
278 exec_list instructions
;
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
282 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
283 dst_reg dst
, src_reg src0
);
285 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
286 dst_reg dst
, src_reg src0
, src_reg src1
);
288 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
290 src_reg src0
, src_reg src1
, src_reg src2
);
293 * Emit the correct dot-product instruction for the type of arguments
295 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
301 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
302 dst_reg dst
, src_reg src0
);
304 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
305 dst_reg dst
, src_reg src0
, src_reg src1
);
307 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
308 dst_reg dst
, const src_reg
&src
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
314 bool try_emit_sat(ir_expression
*ir
);
316 void emit_swz(ir_expression
*ir
);
318 bool process_move_condition(ir_rvalue
*ir
);
320 void copy_propagate(void);
325 } /* anonymous namespace */
327 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
329 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
331 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
334 swizzle_for_size(int size
)
336 static const int size_swizzles
[4] = {
337 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
338 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
339 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
340 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
343 assert((size
>= 1) && (size
<= 4));
344 return size_swizzles
[size
- 1];
347 ir_to_mesa_instruction
*
348 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
350 src_reg src0
, src_reg src1
, src_reg src2
)
352 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
355 /* If we have to do relative addressing, we want to load the ARL
356 * reg directly for one of the regs, and preload the other reladdr
357 * sources into temps.
359 num_reladdr
+= dst
.reladdr
!= NULL
;
360 num_reladdr
+= src0
.reladdr
!= NULL
;
361 num_reladdr
+= src1
.reladdr
!= NULL
;
362 num_reladdr
+= src2
.reladdr
!= NULL
;
364 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
365 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
366 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
369 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
372 assert(num_reladdr
== 0);
381 this->instructions
.push_tail(inst
);
387 ir_to_mesa_instruction
*
388 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
389 dst_reg dst
, src_reg src0
, src_reg src1
)
391 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
394 ir_to_mesa_instruction
*
395 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
396 dst_reg dst
, src_reg src0
)
398 assert(dst
.writemask
!= 0);
399 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
402 ir_to_mesa_instruction
*
403 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
405 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
408 ir_to_mesa_instruction
*
409 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
410 dst_reg dst
, src_reg src0
, src_reg src1
,
413 static const gl_inst_opcode dot_opcodes
[] = {
414 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
417 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
421 * Emits Mesa scalar opcodes to produce unique answers across channels.
423 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
424 * channel determines the result across all channels. So to do a vec4
425 * of this operation, we want to emit a scalar per source channel used
426 * to produce dest channels.
429 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
431 src_reg orig_src0
, src_reg orig_src1
)
434 int done_mask
= ~dst
.writemask
;
436 /* Mesa RCP is a scalar operation splatting results to all channels,
437 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
440 for (i
= 0; i
< 4; i
++) {
441 GLuint this_mask
= (1 << i
);
442 ir_to_mesa_instruction
*inst
;
443 src_reg src0
= orig_src0
;
444 src_reg src1
= orig_src1
;
446 if (done_mask
& this_mask
)
449 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
450 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
451 for (j
= i
+ 1; j
< 4; j
++) {
452 /* If there is another enabled component in the destination that is
453 * derived from the same inputs, generate its value on this pass as
456 if (!(done_mask
& (1 << j
)) &&
457 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
458 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
459 this_mask
|= (1 << j
);
462 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
463 src0_swiz
, src0_swiz
);
464 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
465 src1_swiz
, src1_swiz
);
467 inst
= emit(ir
, op
, dst
, src0
, src1
);
468 inst
->dst
.writemask
= this_mask
;
469 done_mask
|= this_mask
;
474 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
475 dst_reg dst
, src_reg src0
)
477 src_reg undef
= undef_src
;
479 undef
.swizzle
= SWIZZLE_XXXX
;
481 emit_scalar(ir
, op
, dst
, src0
, undef
);
485 * Emit an OPCODE_SCS instruction
487 * The \c SCS opcode functions a bit differently than the other Mesa (or
488 * ARB_fragment_program) opcodes. Instead of splatting its result across all
489 * four components of the destination, it writes one value to the \c x
490 * component and another value to the \c y component.
492 * \param ir IR instruction being processed
493 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
495 * \param dst Destination register
496 * \param src Source register
499 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
503 /* Vertex programs cannot use the SCS opcode.
505 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
506 emit_scalar(ir
, op
, dst
, src
);
510 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
511 const unsigned scs_mask
= (1U << component
);
512 int done_mask
= ~dst
.writemask
;
515 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
517 /* If there are compnents in the destination that differ from the component
518 * that will be written by the SCS instrution, we'll need a temporary.
520 if (scs_mask
!= unsigned(dst
.writemask
)) {
521 tmp
= get_temp(glsl_type::vec4_type
);
524 for (unsigned i
= 0; i
< 4; i
++) {
525 unsigned this_mask
= (1U << i
);
528 if ((done_mask
& this_mask
) != 0)
531 /* The source swizzle specified which component of the source generates
532 * sine / cosine for the current component in the destination. The SCS
533 * instruction requires that this value be swizzle to the X component.
534 * Replace the current swizzle with a swizzle that puts the source in
537 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
539 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
540 src0_swiz
, src0_swiz
);
541 for (unsigned j
= i
+ 1; j
< 4; j
++) {
542 /* If there is another enabled component in the destination that is
543 * derived from the same inputs, generate its value on this pass as
546 if (!(done_mask
& (1 << j
)) &&
547 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
548 this_mask
|= (1 << j
);
552 if (this_mask
!= scs_mask
) {
553 ir_to_mesa_instruction
*inst
;
554 dst_reg tmp_dst
= dst_reg(tmp
);
556 /* Emit the SCS instruction.
558 inst
= emit(ir
, OPCODE_SCS
, tmp_dst
, src0
);
559 inst
->dst
.writemask
= scs_mask
;
561 /* Move the result of the SCS instruction to the desired location in
564 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
565 component
, component
);
566 inst
= emit(ir
, OPCODE_SCS
, dst
, tmp
);
567 inst
->dst
.writemask
= this_mask
;
569 /* Emit the SCS instruction to write directly to the destination.
571 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_SCS
, dst
, src0
);
572 inst
->dst
.writemask
= scs_mask
;
575 done_mask
|= this_mask
;
580 ir_to_mesa_visitor::src_reg_for_float(float val
)
582 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
584 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
585 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
591 type_size(const struct glsl_type
*type
)
596 switch (type
->base_type
) {
599 case GLSL_TYPE_FLOAT
:
601 if (type
->is_matrix()) {
602 return type
->matrix_columns
;
604 /* Regardless of size of vector, it gets a vec4. This is bad
605 * packing for things like floats, but otherwise arrays become a
606 * mess. Hopefully a later pass over the code can pack scalars
607 * down if appropriate.
611 case GLSL_TYPE_ARRAY
:
612 assert(type
->length
> 0);
613 return type_size(type
->fields
.array
) * type
->length
;
614 case GLSL_TYPE_STRUCT
:
616 for (i
= 0; i
< type
->length
; i
++) {
617 size
+= type_size(type
->fields
.structure
[i
].type
);
620 case GLSL_TYPE_SAMPLER
:
621 case GLSL_TYPE_IMAGE
:
622 /* Samplers take up one slot in UNIFORMS[], but they're baked in
626 case GLSL_TYPE_ATOMIC_UINT
:
628 case GLSL_TYPE_ERROR
:
629 case GLSL_TYPE_INTERFACE
:
630 assert(!"Invalid type in type_size");
638 * In the initial pass of codegen, we assign temporary numbers to
639 * intermediate results. (not SSA -- variable assignments will reuse
640 * storage). Actual register allocation for the Mesa VM occurs in a
641 * pass over the Mesa IR later.
644 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
648 src
.file
= PROGRAM_TEMPORARY
;
649 src
.index
= next_temp
;
651 next_temp
+= type_size(type
);
653 if (type
->is_array() || type
->is_record()) {
654 src
.swizzle
= SWIZZLE_NOOP
;
656 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
664 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
666 foreach_in_list(variable_storage
, entry
, &this->variables
) {
667 if (entry
->var
== var
)
675 ir_to_mesa_visitor::visit(ir_variable
*ir
)
677 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
678 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
680 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
681 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
684 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
686 const ir_state_slot
*const slots
= ir
->state_slots
;
687 assert(ir
->state_slots
!= NULL
);
689 /* Check if this statevar's setup in the STATE file exactly
690 * matches how we'll want to reference it as a
691 * struct/array/whatever. If not, then we need to move it into
692 * temporary storage and hope that it'll get copy-propagated
695 for (i
= 0; i
< ir
->num_state_slots
; i
++) {
696 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
701 variable_storage
*storage
;
703 if (i
== ir
->num_state_slots
) {
704 /* We'll set the index later. */
705 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
706 this->variables
.push_tail(storage
);
710 /* The variable_storage constructor allocates slots based on the size
711 * of the type. However, this had better match the number of state
712 * elements that we're going to copy into the new temporary.
714 assert((int) ir
->num_state_slots
== type_size(ir
->type
));
716 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
718 this->variables
.push_tail(storage
);
719 this->next_temp
+= type_size(ir
->type
);
721 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
725 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
726 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
727 (gl_state_index
*)slots
[i
].tokens
);
729 if (storage
->file
== PROGRAM_STATE_VAR
) {
730 if (storage
->index
== -1) {
731 storage
->index
= index
;
733 assert(index
== storage
->index
+ (int)i
);
736 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
737 src
.swizzle
= slots
[i
].swizzle
;
738 emit(ir
, OPCODE_MOV
, dst
, src
);
739 /* even a float takes up a whole vec4 reg in a struct/array. */
744 if (storage
->file
== PROGRAM_TEMPORARY
&&
745 dst
.index
!= storage
->index
+ (int) ir
->num_state_slots
) {
746 linker_error(this->shader_program
,
747 "failed to load builtin uniform `%s' "
748 "(%d/%d regs loaded)\n",
749 ir
->name
, dst
.index
- storage
->index
,
750 type_size(ir
->type
));
756 ir_to_mesa_visitor::visit(ir_loop
*ir
)
758 emit(NULL
, OPCODE_BGNLOOP
);
760 visit_exec_list(&ir
->body_instructions
, this);
762 emit(NULL
, OPCODE_ENDLOOP
);
766 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
769 case ir_loop_jump::jump_break
:
770 emit(NULL
, OPCODE_BRK
);
772 case ir_loop_jump::jump_continue
:
773 emit(NULL
, OPCODE_CONT
);
780 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
787 ir_to_mesa_visitor::visit(ir_function
*ir
)
789 /* Ignore function bodies other than main() -- we shouldn't see calls to
790 * them since they should all be inlined before we get to ir_to_mesa.
792 if (strcmp(ir
->name
, "main") == 0) {
793 const ir_function_signature
*sig
;
796 sig
= ir
->matching_signature(NULL
, &empty
, false);
800 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
807 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
809 int nonmul_operand
= 1 - mul_operand
;
812 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
813 if (!expr
|| expr
->operation
!= ir_binop_mul
)
816 expr
->operands
[0]->accept(this);
818 expr
->operands
[1]->accept(this);
820 ir
->operands
[nonmul_operand
]->accept(this);
823 this->result
= get_temp(ir
->type
);
824 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
830 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
832 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
833 * implemented using multiplication, and logical-or is implemented using
834 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
835 * As result, the logical expression (a & !b) can be rewritten as:
839 * - (a * 1) - (a * b)
843 * This final expression can be implemented as a single MAD(a, -b, a)
847 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
849 const int other_operand
= 1 - try_operand
;
852 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
853 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
856 ir
->operands
[other_operand
]->accept(this);
858 expr
->operands
[0]->accept(this);
861 b
.negate
= ~b
.negate
;
863 this->result
= get_temp(ir
->type
);
864 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
870 ir_to_mesa_visitor::try_emit_sat(ir_expression
*ir
)
872 /* Saturates were only introduced to vertex programs in
873 * NV_vertex_program3, so don't give them to drivers in the VP.
875 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
)
878 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
882 sat_src
->accept(this);
883 src_reg src
= this->result
;
885 /* If we generated an expression instruction into a temporary in
886 * processing the saturate's operand, apply the saturate to that
887 * instruction. Otherwise, generate a MOV to do the saturate.
889 * Note that we have to be careful to only do this optimization if
890 * the instruction in question was what generated src->result. For
891 * example, ir_dereference_array might generate a MUL instruction
892 * to create the reladdr, and return us a src reg using that
893 * reladdr. That MUL result is not the value we're trying to
896 ir_expression
*sat_src_expr
= sat_src
->as_expression();
897 ir_to_mesa_instruction
*new_inst
;
898 new_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
899 if (sat_src_expr
&& (sat_src_expr
->operation
== ir_binop_mul
||
900 sat_src_expr
->operation
== ir_binop_add
||
901 sat_src_expr
->operation
== ir_binop_dot
)) {
902 new_inst
->saturate
= true;
904 this->result
= get_temp(ir
->type
);
905 ir_to_mesa_instruction
*inst
;
906 inst
= emit(ir
, OPCODE_MOV
, dst_reg(this->result
), src
);
907 inst
->saturate
= true;
914 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
915 src_reg
*reg
, int *num_reladdr
)
920 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
922 if (*num_reladdr
!= 1) {
923 src_reg temp
= get_temp(glsl_type::vec4_type
);
925 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
933 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
935 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
936 * This means that each of the operands is either an immediate value of -1,
937 * 0, or 1, or is a component from one source register (possibly with
940 uint8_t components
[4] = { 0 };
941 bool negate
[4] = { false };
942 ir_variable
*var
= NULL
;
944 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
945 ir_rvalue
*op
= ir
->operands
[i
];
947 assert(op
->type
->is_scalar());
950 switch (op
->ir_type
) {
951 case ir_type_constant
: {
953 assert(op
->type
->is_scalar());
955 const ir_constant
*const c
= op
->as_constant();
957 components
[i
] = SWIZZLE_ONE
;
958 } else if (c
->is_zero()) {
959 components
[i
] = SWIZZLE_ZERO
;
960 } else if (c
->is_negative_one()) {
961 components
[i
] = SWIZZLE_ONE
;
964 assert(!"SWZ constant must be 0.0 or 1.0.");
971 case ir_type_dereference_variable
: {
972 ir_dereference_variable
*const deref
=
973 (ir_dereference_variable
*) op
;
975 assert((var
== NULL
) || (deref
->var
== var
));
976 components
[i
] = SWIZZLE_X
;
982 case ir_type_expression
: {
983 ir_expression
*const expr
= (ir_expression
*) op
;
985 assert(expr
->operation
== ir_unop_neg
);
988 op
= expr
->operands
[0];
992 case ir_type_swizzle
: {
993 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
995 components
[i
] = swiz
->mask
.x
;
1001 assert(!"Should not get here.");
1007 assert(var
!= NULL
);
1009 ir_dereference_variable
*const deref
=
1010 new(mem_ctx
) ir_dereference_variable(var
);
1012 this->result
.file
= PROGRAM_UNDEFINED
;
1013 deref
->accept(this);
1014 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1015 printf("Failed to get tree for expression operand:\n");
1024 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
1028 src
.negate
= ((unsigned(negate
[0]) << 0)
1029 | (unsigned(negate
[1]) << 1)
1030 | (unsigned(negate
[2]) << 2)
1031 | (unsigned(negate
[3]) << 3));
1033 /* Storage for our result. Ideally for an assignment we'd be using the
1034 * actual storage for the result here, instead.
1036 const src_reg result_src
= get_temp(ir
->type
);
1037 dst_reg result_dst
= dst_reg(result_src
);
1039 /* Limit writes to the channels that will be used by result_src later.
1040 * This does limit this temp's use as a temporary for multi-instruction
1043 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1045 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
1046 this->result
= result_src
;
1050 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1052 unsigned int operand
;
1053 src_reg op
[Elements(ir
->operands
)];
1057 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1059 if (ir
->operation
== ir_binop_add
) {
1060 if (try_emit_mad(ir
, 1))
1062 if (try_emit_mad(ir
, 0))
1066 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1068 if (ir
->operation
== ir_binop_logic_and
) {
1069 if (try_emit_mad_for_and_not(ir
, 1))
1071 if (try_emit_mad_for_and_not(ir
, 0))
1075 if (try_emit_sat(ir
))
1078 if (ir
->operation
== ir_quadop_vector
) {
1083 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1084 this->result
.file
= PROGRAM_UNDEFINED
;
1085 ir
->operands
[operand
]->accept(this);
1086 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1087 printf("Failed to get tree for expression operand:\n");
1088 ir
->operands
[operand
]->print();
1092 op
[operand
] = this->result
;
1094 /* Matrix expression operands should have been broken down to vector
1095 * operations already.
1097 assert(!ir
->operands
[operand
]->type
->is_matrix());
1100 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1101 if (ir
->operands
[1]) {
1102 vector_elements
= MAX2(vector_elements
,
1103 ir
->operands
[1]->type
->vector_elements
);
1106 this->result
.file
= PROGRAM_UNDEFINED
;
1108 /* Storage for our result. Ideally for an assignment we'd be using
1109 * the actual storage for the result here, instead.
1111 result_src
= get_temp(ir
->type
);
1112 /* convenience for the emit functions below. */
1113 result_dst
= dst_reg(result_src
);
1114 /* Limit writes to the channels that will be used by result_src later.
1115 * This does limit this temp's use as a temporary for multi-instruction
1118 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1120 switch (ir
->operation
) {
1121 case ir_unop_logic_not
:
1122 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1123 * older GPUs implement SEQ using multiple instructions (i915 uses two
1124 * SGE instructions and a MUL instruction). Since our logic values are
1125 * 0.0 and 1.0, 1-x also implements !x.
1127 op
[0].negate
= ~op
[0].negate
;
1128 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1131 op
[0].negate
= ~op
[0].negate
;
1135 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1138 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1141 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1145 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1149 assert(!"not reached: should be handled by ir_explog_to_explog2");
1152 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1155 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1158 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1160 case ir_unop_sin_reduced
:
1161 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1163 case ir_unop_cos_reduced
:
1164 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1168 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1171 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1174 case ir_unop_noise
: {
1175 const enum prog_opcode opcode
=
1176 prog_opcode(OPCODE_NOISE1
1177 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1178 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1180 emit(ir
, opcode
, result_dst
, op
[0]);
1185 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1188 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1192 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1195 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1198 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1199 assert(ir
->type
->is_integer());
1200 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1204 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1206 case ir_binop_greater
:
1207 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1209 case ir_binop_lequal
:
1210 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1212 case ir_binop_gequal
:
1213 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1215 case ir_binop_equal
:
1216 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1218 case ir_binop_nequal
:
1219 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1221 case ir_binop_all_equal
:
1222 /* "==" operator producing a scalar boolean. */
1223 if (ir
->operands
[0]->type
->is_vector() ||
1224 ir
->operands
[1]->type
->is_vector()) {
1225 src_reg temp
= get_temp(glsl_type::vec4_type
);
1226 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1228 /* After the dot-product, the value will be an integer on the
1229 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1231 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1233 /* Negating the result of the dot-product gives values on the range
1234 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1235 * achieved using SGE.
1237 src_reg sge_src
= result_src
;
1238 sge_src
.negate
= ~sge_src
.negate
;
1239 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1241 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1244 case ir_binop_any_nequal
:
1245 /* "!=" operator producing a scalar boolean. */
1246 if (ir
->operands
[0]->type
->is_vector() ||
1247 ir
->operands
[1]->type
->is_vector()) {
1248 src_reg temp
= get_temp(glsl_type::vec4_type
);
1249 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1251 /* After the dot-product, the value will be an integer on the
1252 * range [0,4]. Zero stays zero, and positive values become 1.0.
1254 ir_to_mesa_instruction
*const dp
=
1255 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1256 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1257 /* The clamping to [0,1] can be done for free in the fragment
1258 * shader with a saturate.
1260 dp
->saturate
= true;
1262 /* Negating the result of the dot-product gives values on the range
1263 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1264 * achieved using SLT.
1266 src_reg slt_src
= result_src
;
1267 slt_src
.negate
= ~slt_src
.negate
;
1268 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1271 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1276 assert(ir
->operands
[0]->type
->is_vector());
1278 /* After the dot-product, the value will be an integer on the
1279 * range [0,4]. Zero stays zero, and positive values become 1.0.
1281 ir_to_mesa_instruction
*const dp
=
1282 emit_dp(ir
, result_dst
, op
[0], op
[0],
1283 ir
->operands
[0]->type
->vector_elements
);
1284 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1285 /* The clamping to [0,1] can be done for free in the fragment
1286 * shader with a saturate.
1288 dp
->saturate
= true;
1290 /* Negating the result of the dot-product gives values on the range
1291 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1292 * is achieved using SLT.
1294 src_reg slt_src
= result_src
;
1295 slt_src
.negate
= ~slt_src
.negate
;
1296 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1301 case ir_binop_logic_xor
:
1302 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1305 case ir_binop_logic_or
: {
1306 /* After the addition, the value will be an integer on the
1307 * range [0,2]. Zero stays zero, and positive values become 1.0.
1309 ir_to_mesa_instruction
*add
=
1310 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1311 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1312 /* The clamping to [0,1] can be done for free in the fragment
1313 * shader with a saturate.
1315 add
->saturate
= true;
1317 /* Negating the result of the addition gives values on the range
1318 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1319 * is achieved using SLT.
1321 src_reg slt_src
= result_src
;
1322 slt_src
.negate
= ~slt_src
.negate
;
1323 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1328 case ir_binop_logic_and
:
1329 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1330 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1334 assert(ir
->operands
[0]->type
->is_vector());
1335 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1336 emit_dp(ir
, result_dst
, op
[0], op
[1],
1337 ir
->operands
[0]->type
->vector_elements
);
1341 /* sqrt(x) = x * rsq(x). */
1342 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1343 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1344 /* For incoming channels <= 0, set the result to 0. */
1345 op
[0].negate
= ~op
[0].negate
;
1346 emit(ir
, OPCODE_CMP
, result_dst
,
1347 op
[0], result_src
, src_reg_for_float(0.0));
1350 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1358 /* Mesa IR lacks types, ints are stored as truncated floats. */
1363 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1367 emit(ir
, OPCODE_SNE
, result_dst
,
1368 op
[0], src_reg_for_float(0.0));
1370 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1371 case ir_unop_bitcast_f2u
:
1372 case ir_unop_bitcast_i2f
:
1373 case ir_unop_bitcast_u2f
:
1376 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1379 op
[0].negate
= ~op
[0].negate
;
1380 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1381 result_src
.negate
= ~result_src
.negate
;
1384 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1387 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1389 case ir_unop_pack_snorm_2x16
:
1390 case ir_unop_pack_snorm_4x8
:
1391 case ir_unop_pack_unorm_2x16
:
1392 case ir_unop_pack_unorm_4x8
:
1393 case ir_unop_pack_half_2x16
:
1394 case ir_unop_unpack_snorm_2x16
:
1395 case ir_unop_unpack_snorm_4x8
:
1396 case ir_unop_unpack_unorm_2x16
:
1397 case ir_unop_unpack_unorm_4x8
:
1398 case ir_unop_unpack_half_2x16
:
1399 case ir_unop_unpack_half_2x16_split_x
:
1400 case ir_unop_unpack_half_2x16_split_y
:
1401 case ir_binop_pack_half_2x16_split
:
1402 case ir_unop_bitfield_reverse
:
1403 case ir_unop_bit_count
:
1404 case ir_unop_find_msb
:
1405 case ir_unop_find_lsb
:
1406 assert(!"not supported");
1409 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1412 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1415 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1418 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1419 * hardware backends have no way to avoid Mesa IR generation
1420 * even if they don't use it, we need to emit "something" and
1423 case ir_binop_lshift
:
1424 case ir_binop_rshift
:
1425 case ir_binop_bit_and
:
1426 case ir_binop_bit_xor
:
1427 case ir_binop_bit_or
:
1428 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1431 case ir_unop_bit_not
:
1432 case ir_unop_round_even
:
1433 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1436 case ir_binop_ubo_load
:
1437 assert(!"not supported");
1441 /* ir_triop_lrp operands are (x, y, a) while
1442 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1444 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1447 case ir_binop_vector_extract
:
1451 case ir_triop_bitfield_extract
:
1452 case ir_triop_vector_insert
:
1453 case ir_quadop_bitfield_insert
:
1454 case ir_binop_ldexp
:
1456 case ir_binop_carry
:
1457 case ir_binop_borrow
:
1458 case ir_binop_imul_high
:
1459 case ir_unop_interpolate_at_centroid
:
1460 case ir_binop_interpolate_at_offset
:
1461 case ir_binop_interpolate_at_sample
:
1462 assert(!"not supported");
1465 case ir_quadop_vector
:
1466 /* This operation should have already been handled.
1468 assert(!"Should not get here.");
1472 this->result
= result_src
;
1477 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1483 /* Note that this is only swizzles in expressions, not those on the left
1484 * hand side of an assignment, which do write masking. See ir_assignment
1488 ir
->val
->accept(this);
1490 assert(src
.file
!= PROGRAM_UNDEFINED
);
1492 for (i
= 0; i
< 4; i
++) {
1493 if (i
< ir
->type
->vector_elements
) {
1496 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1499 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1502 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1505 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1509 /* If the type is smaller than a vec4, replicate the last
1512 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1516 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1522 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1524 variable_storage
*entry
= find_variable_storage(ir
->var
);
1525 ir_variable
*var
= ir
->var
;
1528 switch (var
->data
.mode
) {
1529 case ir_var_uniform
:
1530 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1531 var
->data
.location
);
1532 this->variables
.push_tail(entry
);
1534 case ir_var_shader_in
:
1535 /* The linker assigns locations for varyings and attributes,
1536 * including deprecated builtins (like gl_Color),
1537 * user-assigned generic attributes (glBindVertexLocation),
1538 * and user-defined varyings.
1540 assert(var
->data
.location
!= -1);
1541 entry
= new(mem_ctx
) variable_storage(var
,
1543 var
->data
.location
);
1545 case ir_var_shader_out
:
1546 assert(var
->data
.location
!= -1);
1547 entry
= new(mem_ctx
) variable_storage(var
,
1549 var
->data
.location
);
1551 case ir_var_system_value
:
1552 entry
= new(mem_ctx
) variable_storage(var
,
1553 PROGRAM_SYSTEM_VALUE
,
1554 var
->data
.location
);
1557 case ir_var_temporary
:
1558 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1560 this->variables
.push_tail(entry
);
1562 next_temp
+= type_size(var
->type
);
1567 printf("Failed to make storage for %s\n", var
->name
);
1572 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1576 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1580 int element_size
= type_size(ir
->type
);
1582 index
= ir
->array_index
->constant_expression_value();
1584 ir
->array
->accept(this);
1588 src
.index
+= index
->value
.i
[0] * element_size
;
1590 /* Variable index array dereference. It eats the "vec4" of the
1591 * base of the array and an index that offsets the Mesa register
1594 ir
->array_index
->accept(this);
1598 if (element_size
== 1) {
1599 index_reg
= this->result
;
1601 index_reg
= get_temp(glsl_type::float_type
);
1603 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1604 this->result
, src_reg_for_float(element_size
));
1607 /* If there was already a relative address register involved, add the
1608 * new and the old together to get the new offset.
1610 if (src
.reladdr
!= NULL
) {
1611 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1613 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1614 index_reg
, *src
.reladdr
);
1616 index_reg
= accum_reg
;
1619 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1620 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1623 /* If the type is smaller than a vec4, replicate the last channel out. */
1624 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1625 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1627 src
.swizzle
= SWIZZLE_NOOP
;
1633 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1636 const glsl_type
*struct_type
= ir
->record
->type
;
1639 ir
->record
->accept(this);
1641 for (i
= 0; i
< struct_type
->length
; i
++) {
1642 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1644 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1647 /* If the type is smaller than a vec4, replicate the last channel out. */
1648 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1649 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1651 this->result
.swizzle
= SWIZZLE_NOOP
;
1653 this->result
.index
+= offset
;
1657 * We want to be careful in assignment setup to hit the actual storage
1658 * instead of potentially using a temporary like we might with the
1659 * ir_dereference handler.
1662 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1664 /* The LHS must be a dereference. If the LHS is a variable indexed array
1665 * access of a vector, it must be separated into a series conditional moves
1666 * before reaching this point (see ir_vec_index_to_cond_assign).
1668 assert(ir
->as_dereference());
1669 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1671 assert(!deref_array
->array
->type
->is_vector());
1674 /* Use the rvalue deref handler for the most part. We'll ignore
1675 * swizzles in it and write swizzles using writemask, though.
1678 return dst_reg(v
->result
);
1682 * Process the condition of a conditional assignment
1684 * Examines the condition of a conditional assignment to generate the optimal
1685 * first operand of a \c CMP instruction. If the condition is a relational
1686 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1687 * used as the source for the \c CMP instruction. Otherwise the comparison
1688 * is processed to a boolean result, and the boolean result is used as the
1689 * operand to the CMP instruction.
1692 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1694 ir_rvalue
*src_ir
= ir
;
1696 bool switch_order
= false;
1698 ir_expression
*const expr
= ir
->as_expression();
1699 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1700 bool zero_on_left
= false;
1702 if (expr
->operands
[0]->is_zero()) {
1703 src_ir
= expr
->operands
[1];
1704 zero_on_left
= true;
1705 } else if (expr
->operands
[1]->is_zero()) {
1706 src_ir
= expr
->operands
[0];
1707 zero_on_left
= false;
1711 * (a < 0) T F F ( a < 0) T F F
1712 * (0 < a) F F T (-a < 0) F F T
1713 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1714 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1715 * (a > 0) F F T (-a < 0) F F T
1716 * (0 > a) T F F ( a < 0) T F F
1717 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1718 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1720 * Note that exchanging the order of 0 and 'a' in the comparison simply
1721 * means that the value of 'a' should be negated.
1724 switch (expr
->operation
) {
1726 switch_order
= false;
1727 negate
= zero_on_left
;
1730 case ir_binop_greater
:
1731 switch_order
= false;
1732 negate
= !zero_on_left
;
1735 case ir_binop_lequal
:
1736 switch_order
= true;
1737 negate
= !zero_on_left
;
1740 case ir_binop_gequal
:
1741 switch_order
= true;
1742 negate
= zero_on_left
;
1746 /* This isn't the right kind of comparison afterall, so make sure
1747 * the whole condition is visited.
1755 src_ir
->accept(this);
1757 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1758 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1759 * choose which value OPCODE_CMP produces without an extra instruction
1760 * computing the condition.
1763 this->result
.negate
= ~this->result
.negate
;
1765 return switch_order
;
1769 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1775 ir
->rhs
->accept(this);
1778 l
= get_assignment_lhs(ir
->lhs
, this);
1780 /* FINISHME: This should really set to the correct maximal writemask for each
1781 * FINISHME: component written (in the loops below). This case can only
1782 * FINISHME: occur for matrices, arrays, and structures.
1784 if (ir
->write_mask
== 0) {
1785 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1786 l
.writemask
= WRITEMASK_XYZW
;
1787 } else if (ir
->lhs
->type
->is_scalar()) {
1788 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1789 * FINISHME: W component of fragment shader output zero, work correctly.
1791 l
.writemask
= WRITEMASK_XYZW
;
1794 int first_enabled_chan
= 0;
1797 assert(ir
->lhs
->type
->is_vector());
1798 l
.writemask
= ir
->write_mask
;
1800 for (int i
= 0; i
< 4; i
++) {
1801 if (l
.writemask
& (1 << i
)) {
1802 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1807 /* Swizzle a small RHS vector into the channels being written.
1809 * glsl ir treats write_mask as dictating how many channels are
1810 * present on the RHS while Mesa IR treats write_mask as just
1811 * showing which channels of the vec4 RHS get written.
1813 for (int i
= 0; i
< 4; i
++) {
1814 if (l
.writemask
& (1 << i
))
1815 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1817 swizzles
[i
] = first_enabled_chan
;
1819 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1820 swizzles
[2], swizzles
[3]);
1823 assert(l
.file
!= PROGRAM_UNDEFINED
);
1824 assert(r
.file
!= PROGRAM_UNDEFINED
);
1826 if (ir
->condition
) {
1827 const bool switch_order
= this->process_move_condition(ir
->condition
);
1828 src_reg condition
= this->result
;
1830 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1832 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1834 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1841 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1842 emit(ir
, OPCODE_MOV
, l
, r
);
1851 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1854 GLfloat stack_vals
[4] = { 0 };
1855 GLfloat
*values
= stack_vals
;
1858 /* Unfortunately, 4 floats is all we can get into
1859 * _mesa_add_unnamed_constant. So, make a temp to store an
1860 * aggregate constant and move each constant value into it. If we
1861 * get lucky, copy propagation will eliminate the extra moves.
1864 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1865 src_reg temp_base
= get_temp(ir
->type
);
1866 dst_reg temp
= dst_reg(temp_base
);
1868 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1869 int size
= type_size(field_value
->type
);
1873 field_value
->accept(this);
1876 for (i
= 0; i
< (unsigned int)size
; i
++) {
1877 emit(ir
, OPCODE_MOV
, temp
, src
);
1883 this->result
= temp_base
;
1887 if (ir
->type
->is_array()) {
1888 src_reg temp_base
= get_temp(ir
->type
);
1889 dst_reg temp
= dst_reg(temp_base
);
1890 int size
= type_size(ir
->type
->fields
.array
);
1894 for (i
= 0; i
< ir
->type
->length
; i
++) {
1895 ir
->array_elements
[i
]->accept(this);
1897 for (int j
= 0; j
< size
; j
++) {
1898 emit(ir
, OPCODE_MOV
, temp
, src
);
1904 this->result
= temp_base
;
1908 if (ir
->type
->is_matrix()) {
1909 src_reg mat
= get_temp(ir
->type
);
1910 dst_reg mat_column
= dst_reg(mat
);
1912 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1913 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1914 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1916 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1917 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1918 (gl_constant_value
*) values
,
1919 ir
->type
->vector_elements
,
1921 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1930 src
.file
= PROGRAM_CONSTANT
;
1931 switch (ir
->type
->base_type
) {
1932 case GLSL_TYPE_FLOAT
:
1933 values
= &ir
->value
.f
[0];
1935 case GLSL_TYPE_UINT
:
1936 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1937 values
[i
] = ir
->value
.u
[i
];
1941 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1942 values
[i
] = ir
->value
.i
[i
];
1945 case GLSL_TYPE_BOOL
:
1946 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1947 values
[i
] = ir
->value
.b
[i
];
1951 assert(!"Non-float/uint/int/bool constant");
1954 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1955 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1956 (gl_constant_value
*) values
,
1957 ir
->type
->vector_elements
,
1958 &this->result
.swizzle
);
1962 ir_to_mesa_visitor::visit(ir_call
*)
1964 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1968 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1970 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1971 dst_reg result_dst
, coord_dst
;
1972 ir_to_mesa_instruction
*inst
= NULL
;
1973 prog_opcode opcode
= OPCODE_NOP
;
1975 if (ir
->op
== ir_txs
)
1976 this->result
= src_reg_for_float(0.0);
1978 ir
->coordinate
->accept(this);
1980 /* Put our coords in a temp. We'll need to modify them for shadow,
1981 * projection, or LOD, so the only case we'd use it as is is if
1982 * we're doing plain old texturing. Mesa IR optimization should
1983 * handle cleaning up our mess in that case.
1985 coord
= get_temp(glsl_type::vec4_type
);
1986 coord_dst
= dst_reg(coord
);
1987 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1989 if (ir
->projector
) {
1990 ir
->projector
->accept(this);
1991 projector
= this->result
;
1994 /* Storage for our result. Ideally for an assignment we'd be using
1995 * the actual storage for the result here, instead.
1997 result_src
= get_temp(glsl_type::vec4_type
);
1998 result_dst
= dst_reg(result_src
);
2003 opcode
= OPCODE_TEX
;
2006 opcode
= OPCODE_TXB
;
2007 ir
->lod_info
.bias
->accept(this);
2008 lod_info
= this->result
;
2011 /* Pretend to be TXL so the sampler, coordinate, lod are available */
2013 opcode
= OPCODE_TXL
;
2014 ir
->lod_info
.lod
->accept(this);
2015 lod_info
= this->result
;
2018 opcode
= OPCODE_TXD
;
2019 ir
->lod_info
.grad
.dPdx
->accept(this);
2021 ir
->lod_info
.grad
.dPdy
->accept(this);
2025 assert(!"Unexpected ir_txf_ms opcode");
2028 assert(!"Unexpected ir_lod opcode");
2031 assert(!"Unexpected ir_tg4 opcode");
2033 case ir_query_levels
:
2034 assert(!"Unexpected ir_query_levels opcode");
2038 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2040 if (ir
->projector
) {
2041 if (opcode
== OPCODE_TEX
) {
2042 /* Slot the projector in as the last component of the coord. */
2043 coord_dst
.writemask
= WRITEMASK_W
;
2044 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
2045 coord_dst
.writemask
= WRITEMASK_XYZW
;
2046 opcode
= OPCODE_TXP
;
2048 src_reg coord_w
= coord
;
2049 coord_w
.swizzle
= SWIZZLE_WWWW
;
2051 /* For the other TEX opcodes there's no projective version
2052 * since the last slot is taken up by lod info. Do the
2053 * projective divide now.
2055 coord_dst
.writemask
= WRITEMASK_W
;
2056 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
2058 /* In the case where we have to project the coordinates "by hand,"
2059 * the shadow comparitor value must also be projected.
2061 src_reg tmp_src
= coord
;
2062 if (ir
->shadow_comparitor
) {
2063 /* Slot the shadow value in as the second to last component of the
2066 ir
->shadow_comparitor
->accept(this);
2068 tmp_src
= get_temp(glsl_type::vec4_type
);
2069 dst_reg tmp_dst
= dst_reg(tmp_src
);
2071 /* Projective division not allowed for array samplers. */
2072 assert(!sampler_type
->sampler_array
);
2074 tmp_dst
.writemask
= WRITEMASK_Z
;
2075 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
2077 tmp_dst
.writemask
= WRITEMASK_XY
;
2078 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
2081 coord_dst
.writemask
= WRITEMASK_XYZ
;
2082 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
2084 coord_dst
.writemask
= WRITEMASK_XYZW
;
2085 coord
.swizzle
= SWIZZLE_XYZW
;
2089 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2090 * comparitor was put in the correct place (and projected) by the code,
2091 * above, that handles by-hand projection.
2093 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
2094 /* Slot the shadow value in as the second to last component of the
2097 ir
->shadow_comparitor
->accept(this);
2099 /* XXX This will need to be updated for cubemap array samplers. */
2100 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
2101 sampler_type
->sampler_array
) {
2102 coord_dst
.writemask
= WRITEMASK_W
;
2104 coord_dst
.writemask
= WRITEMASK_Z
;
2107 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2108 coord_dst
.writemask
= WRITEMASK_XYZW
;
2111 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2112 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2113 coord_dst
.writemask
= WRITEMASK_W
;
2114 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2115 coord_dst
.writemask
= WRITEMASK_XYZW
;
2118 if (opcode
== OPCODE_TXD
)
2119 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2121 inst
= emit(ir
, opcode
, result_dst
, coord
);
2123 if (ir
->shadow_comparitor
)
2124 inst
->tex_shadow
= GL_TRUE
;
2126 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2127 this->shader_program
,
2130 switch (sampler_type
->sampler_dimensionality
) {
2131 case GLSL_SAMPLER_DIM_1D
:
2132 inst
->tex_target
= (sampler_type
->sampler_array
)
2133 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2135 case GLSL_SAMPLER_DIM_2D
:
2136 inst
->tex_target
= (sampler_type
->sampler_array
)
2137 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2139 case GLSL_SAMPLER_DIM_3D
:
2140 inst
->tex_target
= TEXTURE_3D_INDEX
;
2142 case GLSL_SAMPLER_DIM_CUBE
:
2143 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2145 case GLSL_SAMPLER_DIM_RECT
:
2146 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2148 case GLSL_SAMPLER_DIM_BUF
:
2149 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2151 case GLSL_SAMPLER_DIM_EXTERNAL
:
2152 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2155 assert(!"Should not get here.");
2158 this->result
= result_src
;
2162 ir_to_mesa_visitor::visit(ir_return
*ir
)
2164 /* Non-void functions should have been inlined. We may still emit RETs
2165 * from main() unless the EmitNoMainReturn option is set.
2167 assert(!ir
->get_value());
2168 emit(ir
, OPCODE_RET
);
2172 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2174 if (ir
->condition
) {
2175 ir
->condition
->accept(this);
2176 this->result
.negate
= ~this->result
.negate
;
2177 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2179 emit(ir
, OPCODE_KIL_NV
);
2184 ir_to_mesa_visitor::visit(ir_if
*ir
)
2186 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2187 ir_to_mesa_instruction
*prev_inst
;
2189 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2191 ir
->condition
->accept(this);
2192 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2194 if (this->options
->EmitCondCodes
) {
2195 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2197 /* See if we actually generated any instruction for generating
2198 * the condition. If not, then cook up a move to a temp so we
2199 * have something to set cond_update on.
2201 if (cond_inst
== prev_inst
) {
2202 src_reg temp
= get_temp(glsl_type::bool_type
);
2203 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2205 cond_inst
->cond_update
= GL_TRUE
;
2207 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2208 if_inst
->dst
.cond_mask
= COND_NE
;
2210 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2213 this->instructions
.push_tail(if_inst
);
2215 visit_exec_list(&ir
->then_instructions
, this);
2217 if (!ir
->else_instructions
.is_empty()) {
2218 emit(ir
->condition
, OPCODE_ELSE
);
2219 visit_exec_list(&ir
->else_instructions
, this);
2222 emit(ir
->condition
, OPCODE_ENDIF
);
2226 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2228 assert(!"Geometry shaders not supported.");
2232 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2234 assert(!"Geometry shaders not supported.");
2237 ir_to_mesa_visitor::ir_to_mesa_visitor()
2239 result
.file
= PROGRAM_UNDEFINED
;
2241 next_signature_id
= 1;
2242 current_function
= NULL
;
2243 mem_ctx
= ralloc_context(NULL
);
2246 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2248 ralloc_free(mem_ctx
);
2251 static struct prog_src_register
2252 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2254 struct prog_src_register mesa_reg
;
2256 mesa_reg
.File
= reg
.file
;
2257 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2258 mesa_reg
.Index
= reg
.index
;
2259 mesa_reg
.Swizzle
= reg
.swizzle
;
2260 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2261 mesa_reg
.Negate
= reg
.negate
;
2263 mesa_reg
.HasIndex2
= GL_FALSE
;
2264 mesa_reg
.RelAddr2
= 0;
2265 mesa_reg
.Index2
= 0;
2271 set_branchtargets(ir_to_mesa_visitor
*v
,
2272 struct prog_instruction
*mesa_instructions
,
2273 int num_instructions
)
2275 int if_count
= 0, loop_count
= 0;
2276 int *if_stack
, *loop_stack
;
2277 int if_stack_pos
= 0, loop_stack_pos
= 0;
2280 for (i
= 0; i
< num_instructions
; i
++) {
2281 switch (mesa_instructions
[i
].Opcode
) {
2285 case OPCODE_BGNLOOP
:
2290 mesa_instructions
[i
].BranchTarget
= -1;
2297 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2298 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2300 for (i
= 0; i
< num_instructions
; i
++) {
2301 switch (mesa_instructions
[i
].Opcode
) {
2303 if_stack
[if_stack_pos
] = i
;
2307 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2308 if_stack
[if_stack_pos
- 1] = i
;
2311 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2314 case OPCODE_BGNLOOP
:
2315 loop_stack
[loop_stack_pos
] = i
;
2318 case OPCODE_ENDLOOP
:
2320 /* Rewrite any breaks/conts at this nesting level (haven't
2321 * already had a BranchTarget assigned) to point to the end
2324 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2325 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2326 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2327 if (mesa_instructions
[j
].BranchTarget
== -1) {
2328 mesa_instructions
[j
].BranchTarget
= i
;
2332 /* The loop ends point at each other. */
2333 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2334 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2337 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2338 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2339 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2351 print_program(struct prog_instruction
*mesa_instructions
,
2352 ir_instruction
**mesa_instruction_annotation
,
2353 int num_instructions
)
2355 ir_instruction
*last_ir
= NULL
;
2359 for (i
= 0; i
< num_instructions
; i
++) {
2360 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2361 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2363 fprintf(stdout
, "%3d: ", i
);
2365 if (last_ir
!= ir
&& ir
) {
2368 for (j
= 0; j
< indent
; j
++) {
2369 fprintf(stdout
, " ");
2375 fprintf(stdout
, " "); /* line number spacing. */
2378 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2379 PROG_PRINT_DEBUG
, NULL
);
2385 class add_uniform_to_shader
: public program_resource_visitor
{
2387 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2388 struct gl_program_parameter_list
*params
,
2389 gl_shader_stage shader_type
)
2390 : shader_program(shader_program
), params(params
), idx(-1),
2391 shader_type(shader_type
)
2396 void process(ir_variable
*var
)
2399 this->program_resource_visitor::process(var
);
2401 var
->data
.location
= this->idx
;
2405 virtual void visit_field(const glsl_type
*type
, const char *name
,
2408 struct gl_shader_program
*shader_program
;
2409 struct gl_program_parameter_list
*params
;
2411 gl_shader_stage shader_type
;
2414 } /* anonymous namespace */
2417 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2424 if (type
->is_vector() || type
->is_scalar()) {
2425 size
= type
->vector_elements
;
2427 size
= type_size(type
) * 4;
2430 gl_register_file file
;
2431 if (type
->is_sampler() ||
2432 (type
->is_array() && type
->fields
.array
->is_sampler())) {
2433 file
= PROGRAM_SAMPLER
;
2435 file
= PROGRAM_UNIFORM
;
2438 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2440 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2443 /* Sampler uniform values are stored in prog->SamplerUnits,
2444 * and the entry in that array is selected by this index we
2445 * store in ParameterValues[].
2447 if (file
== PROGRAM_SAMPLER
) {
2450 this->shader_program
->UniformHash
->get(location
,
2451 params
->Parameters
[index
].Name
);
2457 struct gl_uniform_storage
*storage
=
2458 &this->shader_program
->UniformStorage
[location
];
2460 assert(storage
->sampler
[shader_type
].active
);
2462 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2463 params
->ParameterValues
[index
+ j
][0].f
=
2464 storage
->sampler
[shader_type
].index
+ j
;
2468 /* The first part of the uniform that's processed determines the base
2469 * location of the whole uniform (for structures).
2476 * Generate the program parameters list for the user uniforms in a shader
2478 * \param shader_program Linked shader program. This is only used to
2479 * emit possible link errors to the info log.
2480 * \param sh Shader whose uniforms are to be processed.
2481 * \param params Parameter list to be filled in.
2484 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2486 struct gl_shader
*sh
,
2487 struct gl_program_parameter_list
2490 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2492 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2493 ir_variable
*var
= node
->as_variable();
2495 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2496 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2504 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2505 struct gl_shader_program
*shader_program
,
2506 struct gl_program_parameter_list
*params
)
2508 /* After adding each uniform to the parameter list, connect the storage for
2509 * the parameter with the tracking structure used by the API for the
2512 unsigned last_location
= unsigned(~0);
2513 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2514 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2519 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2525 if (location
!= last_location
) {
2526 struct gl_uniform_storage
*storage
=
2527 &shader_program
->UniformStorage
[location
];
2528 enum gl_uniform_driver_format format
= uniform_native
;
2530 unsigned columns
= 0;
2531 switch (storage
->type
->base_type
) {
2532 case GLSL_TYPE_UINT
:
2533 assert(ctx
->Const
.NativeIntegers
);
2534 format
= uniform_native
;
2539 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2542 case GLSL_TYPE_FLOAT
:
2543 format
= uniform_native
;
2544 columns
= storage
->type
->matrix_columns
;
2546 case GLSL_TYPE_BOOL
:
2547 if (ctx
->Const
.NativeIntegers
) {
2548 format
= (ctx
->Const
.UniformBooleanTrue
== 1)
2549 ? uniform_bool_int_0_1
: uniform_bool_int_0_not0
;
2551 format
= uniform_bool_float
;
2555 case GLSL_TYPE_SAMPLER
:
2556 case GLSL_TYPE_IMAGE
:
2557 format
= uniform_native
;
2560 case GLSL_TYPE_ATOMIC_UINT
:
2561 case GLSL_TYPE_ARRAY
:
2562 case GLSL_TYPE_VOID
:
2563 case GLSL_TYPE_STRUCT
:
2564 case GLSL_TYPE_ERROR
:
2565 case GLSL_TYPE_INTERFACE
:
2566 assert(!"Should not get here.");
2570 _mesa_uniform_attach_driver_storage(storage
,
2571 4 * sizeof(float) * columns
,
2574 ¶ms
->ParameterValues
[i
]);
2576 /* After attaching the driver's storage to the uniform, propagate any
2577 * data from the linker's backing store. This will cause values from
2578 * initializers in the source code to be copied over.
2580 _mesa_propagate_uniforms_to_driver_storage(storage
,
2582 MAX2(1, storage
->array_elements
));
2584 last_location
= location
;
2590 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2591 * channels for copy propagation and updates following instructions to
2592 * use the original versions.
2594 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2595 * will occur. As an example, a TXP production before this pass:
2597 * 0: MOV TEMP[1], INPUT[4].xyyy;
2598 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2599 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2603 * 0: MOV TEMP[1], INPUT[4].xyyy;
2604 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2605 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2607 * which allows for dead code elimination on TEMP[1]'s writes.
2610 ir_to_mesa_visitor::copy_propagate(void)
2612 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2613 ir_to_mesa_instruction
*,
2614 this->next_temp
* 4);
2615 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2618 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2619 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2620 || inst
->dst
.index
< this->next_temp
);
2622 /* First, do any copy propagation possible into the src regs. */
2623 for (int r
= 0; r
< 3; r
++) {
2624 ir_to_mesa_instruction
*first
= NULL
;
2626 int acp_base
= inst
->src
[r
].index
* 4;
2628 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2629 inst
->src
[r
].reladdr
)
2632 /* See if we can find entries in the ACP consisting of MOVs
2633 * from the same src register for all the swizzled channels
2634 * of this src register reference.
2636 for (int i
= 0; i
< 4; i
++) {
2637 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2638 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2645 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2650 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2651 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2659 /* We've now validated that we can copy-propagate to
2660 * replace this src register reference. Do it.
2662 inst
->src
[r
].file
= first
->src
[0].file
;
2663 inst
->src
[r
].index
= first
->src
[0].index
;
2666 for (int i
= 0; i
< 4; i
++) {
2667 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2668 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2669 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2672 inst
->src
[r
].swizzle
= swizzle
;
2677 case OPCODE_BGNLOOP
:
2678 case OPCODE_ENDLOOP
:
2679 /* End of a basic block, clear the ACP entirely. */
2680 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2689 /* Clear all channels written inside the block from the ACP, but
2690 * leaving those that were not touched.
2692 for (int r
= 0; r
< this->next_temp
; r
++) {
2693 for (int c
= 0; c
< 4; c
++) {
2694 if (!acp
[4 * r
+ c
])
2697 if (acp_level
[4 * r
+ c
] >= level
)
2698 acp
[4 * r
+ c
] = NULL
;
2701 if (inst
->op
== OPCODE_ENDIF
)
2706 /* Continuing the block, clear any written channels from
2709 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2710 /* Any temporary might be written, so no copy propagation
2711 * across this instruction.
2713 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2714 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2715 inst
->dst
.reladdr
) {
2716 /* Any output might be written, so no copy propagation
2717 * from outputs across this instruction.
2719 for (int r
= 0; r
< this->next_temp
; r
++) {
2720 for (int c
= 0; c
< 4; c
++) {
2721 if (!acp
[4 * r
+ c
])
2724 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2725 acp
[4 * r
+ c
] = NULL
;
2728 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2729 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2730 /* Clear where it's used as dst. */
2731 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2732 for (int c
= 0; c
< 4; c
++) {
2733 if (inst
->dst
.writemask
& (1 << c
)) {
2734 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2739 /* Clear where it's used as src. */
2740 for (int r
= 0; r
< this->next_temp
; r
++) {
2741 for (int c
= 0; c
< 4; c
++) {
2742 if (!acp
[4 * r
+ c
])
2745 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2747 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2748 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2749 inst
->dst
.writemask
& (1 << src_chan
))
2751 acp
[4 * r
+ c
] = NULL
;
2759 /* If this is a copy, add it to the ACP. */
2760 if (inst
->op
== OPCODE_MOV
&&
2761 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2762 !(inst
->dst
.file
== inst
->src
[0].file
&&
2763 inst
->dst
.index
== inst
->src
[0].index
) &&
2764 !inst
->dst
.reladdr
&&
2766 !inst
->src
[0].reladdr
&&
2767 !inst
->src
[0].negate
) {
2768 for (int i
= 0; i
< 4; i
++) {
2769 if (inst
->dst
.writemask
& (1 << i
)) {
2770 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2771 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2777 ralloc_free(acp_level
);
2783 * Convert a shader's GLSL IR into a Mesa gl_program.
2785 static struct gl_program
*
2786 get_mesa_program(struct gl_context
*ctx
,
2787 struct gl_shader_program
*shader_program
,
2788 struct gl_shader
*shader
)
2790 ir_to_mesa_visitor v
;
2791 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2792 ir_instruction
**mesa_instruction_annotation
;
2794 struct gl_program
*prog
;
2795 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2796 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2797 struct gl_shader_compiler_options
*options
=
2798 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2800 validate_ir_tree(shader
->ir
);
2802 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2805 prog
->Parameters
= _mesa_new_parameter_list();
2808 v
.shader_program
= shader_program
;
2809 v
.options
= options
;
2811 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2814 /* Emit Mesa IR for main(). */
2815 visit_exec_list(shader
->ir
, &v
);
2816 v
.emit(NULL
, OPCODE_END
);
2818 prog
->NumTemporaries
= v
.next_temp
;
2820 unsigned num_instructions
= v
.instructions
.length();
2823 (struct prog_instruction
*)calloc(num_instructions
,
2824 sizeof(*mesa_instructions
));
2825 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2830 /* Convert ir_mesa_instructions into prog_instructions.
2832 mesa_inst
= mesa_instructions
;
2834 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2835 mesa_inst
->Opcode
= inst
->op
;
2836 mesa_inst
->CondUpdate
= inst
->cond_update
;
2838 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2839 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2840 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2841 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2842 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2843 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2844 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2845 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2846 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2847 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2848 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2849 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2850 mesa_instruction_annotation
[i
] = inst
->ir
;
2852 /* Set IndirectRegisterFiles. */
2853 if (mesa_inst
->DstReg
.RelAddr
)
2854 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2856 /* Update program's bitmask of indirectly accessed register files */
2857 for (unsigned src
= 0; src
< 3; src
++)
2858 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2859 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2861 switch (mesa_inst
->Opcode
) {
2863 if (options
->MaxIfDepth
== 0) {
2864 linker_warning(shader_program
,
2865 "Couldn't flatten if-statement. "
2866 "This will likely result in software "
2867 "rasterization.\n");
2870 case OPCODE_BGNLOOP
:
2871 if (options
->EmitNoLoops
) {
2872 linker_warning(shader_program
,
2873 "Couldn't unroll loop. "
2874 "This will likely result in software "
2875 "rasterization.\n");
2879 if (options
->EmitNoCont
) {
2880 linker_warning(shader_program
,
2881 "Couldn't lower continue-statement. "
2882 "This will likely result in software "
2883 "rasterization.\n");
2887 prog
->NumAddressRegs
= 1;
2896 if (!shader_program
->LinkStatus
)
2900 if (!shader_program
->LinkStatus
) {
2904 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2906 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2907 fprintf(stderr
, "\n");
2908 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2909 shader_program
->Name
);
2910 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2911 fprintf(stderr
, "\n");
2912 fprintf(stderr
, "\n");
2913 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2914 shader_program
->Name
);
2915 print_program(mesa_instructions
, mesa_instruction_annotation
,
2920 prog
->Instructions
= mesa_instructions
;
2921 prog
->NumInstructions
= num_instructions
;
2923 /* Setting this to NULL prevents a possible double free in the fail_exit
2926 mesa_instructions
= NULL
;
2928 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2930 prog
->SamplersUsed
= shader
->active_samplers
;
2931 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2932 _mesa_update_shader_textures_used(shader_program
, prog
);
2934 /* Set the gl_FragDepth layout. */
2935 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2936 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2937 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2940 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2942 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2943 _mesa_optimize_program(ctx
, prog
);
2946 /* This has to be done last. Any operation that can cause
2947 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2948 * program constant) has to happen before creating this linkage.
2950 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2951 if (!shader_program
->LinkStatus
) {
2958 free(mesa_instructions
);
2959 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2967 * Called via ctx->Driver.LinkShader()
2968 * This actually involves converting GLSL IR into Mesa gl_programs with
2969 * code lowering and other optimizations.
2972 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2974 assert(prog
->LinkStatus
);
2976 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2977 if (prog
->_LinkedShaders
[i
] == NULL
)
2981 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2982 const struct gl_shader_compiler_options
*options
=
2983 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2989 do_mat_op_to_vec(ir
);
2990 lower_instructions(ir
, (MOD_TO_FRACT
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2991 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2992 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2994 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2996 progress
= do_common_optimization(ir
, true, true,
2997 options
, ctx
->Const
.NativeIntegers
)
3000 progress
= lower_quadop_vector(ir
, true) || progress
;
3002 if (options
->MaxIfDepth
== 0)
3003 progress
= lower_discard(ir
) || progress
;
3005 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
3007 if (options
->EmitNoNoise
)
3008 progress
= lower_noise(ir
) || progress
;
3010 /* If there are forms of indirect addressing that the driver
3011 * cannot handle, perform the lowering pass.
3013 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
3014 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
3016 lower_variable_index_to_cond_assign(ir
,
3017 options
->EmitNoIndirectInput
,
3018 options
->EmitNoIndirectOutput
,
3019 options
->EmitNoIndirectTemp
,
3020 options
->EmitNoIndirectUniform
)
3023 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
3024 progress
= lower_vector_insert(ir
, true) || progress
;
3027 validate_ir_tree(ir
);
3030 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3031 struct gl_program
*linked_prog
;
3033 if (prog
->_LinkedShaders
[i
] == NULL
)
3036 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
3039 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
3041 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
3043 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
3044 _mesa_shader_stage_to_program(i
),
3050 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3053 return prog
->LinkStatus
;
3057 * Link a GLSL shader program. Called via glLinkProgram().
3060 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3064 _mesa_clear_shader_program_data(ctx
, prog
);
3066 prog
->LinkStatus
= GL_TRUE
;
3068 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3069 if (!prog
->Shaders
[i
]->CompileStatus
) {
3070 linker_error(prog
, "linking with uncompiled shader");
3074 if (prog
->LinkStatus
) {
3075 link_shaders(ctx
, prog
);
3078 if (prog
->LinkStatus
) {
3079 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3080 prog
->LinkStatus
= GL_FALSE
;
3084 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
3085 if (!prog
->LinkStatus
) {
3086 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
3089 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3090 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
3091 fprintf(stderr
, "%s\n", prog
->InfoLog
);