2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_print_visitor.h"
37 #include "ir_expression_flattening.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderapi.h"
47 #include "main/shaderobj.h"
48 #include "main/uniforms.h"
49 #include "program/hash_table.h"
50 #include "program/prog_instruction.h"
51 #include "program/prog_optimize.h"
52 #include "program/prog_print.h"
53 #include "program/program.h"
54 #include "program/prog_uniform.h"
55 #include "program/prog_parameter.h"
56 #include "program/sampler.h"
59 static int swizzle_for_size(int size
);
62 * This struct is a corresponding struct to Mesa prog_src_register, with
65 typedef struct ir_to_mesa_src_reg
{
66 ir_to_mesa_src_reg(int file
, int index
, const glsl_type
*type
)
68 this->file
= (gl_register_file
) file
;
70 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
71 this->swizzle
= swizzle_for_size(type
->vector_elements
);
73 this->swizzle
= SWIZZLE_XYZW
;
80 this->file
= PROGRAM_UNDEFINED
;
87 gl_register_file file
; /**< PROGRAM_* from Mesa */
88 int index
; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
89 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
90 int negate
; /**< NEGATE_XYZW mask from mesa */
91 /** Register index should be offset by the integer in this reg. */
92 ir_to_mesa_src_reg
*reladdr
;
95 typedef struct ir_to_mesa_dst_reg
{
96 int file
; /**< PROGRAM_* from Mesa */
97 int index
; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
98 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
100 /** Register index should be offset by the integer in this reg. */
101 ir_to_mesa_src_reg
*reladdr
;
102 } ir_to_mesa_dst_reg
;
104 extern ir_to_mesa_src_reg ir_to_mesa_undef
;
106 class ir_to_mesa_instruction
: public exec_node
{
108 /* Callers of this talloc-based new need not call delete. It's
109 * easier to just talloc_free 'ctx' (or any of its ancestors). */
110 static void* operator new(size_t size
, void *ctx
)
114 node
= talloc_zero_size(ctx
, size
);
115 assert(node
!= NULL
);
121 ir_to_mesa_dst_reg dst_reg
;
122 ir_to_mesa_src_reg src_reg
[3];
123 /** Pointer to the ir source this tree came from for debugging */
125 GLboolean cond_update
;
127 int sampler
; /**< sampler index */
128 int tex_target
; /**< One of TEXTURE_*_INDEX */
129 GLboolean tex_shadow
;
131 class function_entry
*function
; /* Set on OPCODE_CAL or OPCODE_BGNSUB */
134 class variable_storage
: public exec_node
{
136 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
137 : file(file
), index(index
), var(var
)
142 gl_register_file file
;
144 ir_variable
*var
; /* variable that maps to this, if any */
147 class function_entry
: public exec_node
{
149 ir_function_signature
*sig
;
152 * identifier of this function signature used by the program.
154 * At the point that Mesa instructions for function calls are
155 * generated, we don't know the address of the first instruction of
156 * the function body. So we make the BranchTarget that is called a
157 * small integer and rewrite them during set_branchtargets().
162 * Pointer to first instruction of the function body.
164 * Set during function body emits after main() is processed.
166 ir_to_mesa_instruction
*bgn_inst
;
169 * Index of the first instruction of the function body in actual
172 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
176 /** Storage for the return value. */
177 ir_to_mesa_src_reg return_reg
;
180 class ir_to_mesa_visitor
: public ir_visitor
{
182 ir_to_mesa_visitor();
183 ~ir_to_mesa_visitor();
185 function_entry
*current_function
;
187 struct gl_context
*ctx
;
188 struct gl_program
*prog
;
189 struct gl_shader_program
*shader_program
;
190 struct gl_shader_compiler_options
*options
;
194 variable_storage
*find_variable_storage(ir_variable
*var
);
196 function_entry
*get_function_signature(ir_function_signature
*sig
);
198 ir_to_mesa_src_reg
get_temp(const glsl_type
*type
);
199 void reladdr_to_temp(ir_instruction
*ir
,
200 ir_to_mesa_src_reg
*reg
, int *num_reladdr
);
202 struct ir_to_mesa_src_reg
src_reg_for_float(float val
);
205 * \name Visit methods
207 * As typical for the visitor pattern, there must be one \c visit method for
208 * each concrete subclass of \c ir_instruction. Virtual base classes within
209 * the hierarchy should not have \c visit methods.
212 virtual void visit(ir_variable
*);
213 virtual void visit(ir_loop
*);
214 virtual void visit(ir_loop_jump
*);
215 virtual void visit(ir_function_signature
*);
216 virtual void visit(ir_function
*);
217 virtual void visit(ir_expression
*);
218 virtual void visit(ir_swizzle
*);
219 virtual void visit(ir_dereference_variable
*);
220 virtual void visit(ir_dereference_array
*);
221 virtual void visit(ir_dereference_record
*);
222 virtual void visit(ir_assignment
*);
223 virtual void visit(ir_constant
*);
224 virtual void visit(ir_call
*);
225 virtual void visit(ir_return
*);
226 virtual void visit(ir_discard
*);
227 virtual void visit(ir_texture
*);
228 virtual void visit(ir_if
*);
231 struct ir_to_mesa_src_reg result
;
233 /** List of variable_storage */
236 /** List of function_entry */
237 exec_list function_signatures
;
238 int next_signature_id
;
240 /** List of ir_to_mesa_instruction */
241 exec_list instructions
;
243 ir_to_mesa_instruction
*ir_to_mesa_emit_op0(ir_instruction
*ir
,
244 enum prog_opcode op
);
246 ir_to_mesa_instruction
*ir_to_mesa_emit_op1(ir_instruction
*ir
,
248 ir_to_mesa_dst_reg dst
,
249 ir_to_mesa_src_reg src0
);
251 ir_to_mesa_instruction
*ir_to_mesa_emit_op2(ir_instruction
*ir
,
253 ir_to_mesa_dst_reg dst
,
254 ir_to_mesa_src_reg src0
,
255 ir_to_mesa_src_reg src1
);
257 ir_to_mesa_instruction
*ir_to_mesa_emit_op3(ir_instruction
*ir
,
259 ir_to_mesa_dst_reg dst
,
260 ir_to_mesa_src_reg src0
,
261 ir_to_mesa_src_reg src1
,
262 ir_to_mesa_src_reg src2
);
265 * Emit the correct dot-product instruction for the type of arguments
267 * \sa ir_to_mesa_emit_op2
269 void ir_to_mesa_emit_dp(ir_instruction
*ir
,
270 ir_to_mesa_dst_reg dst
,
271 ir_to_mesa_src_reg src0
,
272 ir_to_mesa_src_reg src1
,
275 void ir_to_mesa_emit_scalar_op1(ir_instruction
*ir
,
277 ir_to_mesa_dst_reg dst
,
278 ir_to_mesa_src_reg src0
);
280 void ir_to_mesa_emit_scalar_op2(ir_instruction
*ir
,
282 ir_to_mesa_dst_reg dst
,
283 ir_to_mesa_src_reg src0
,
284 ir_to_mesa_src_reg src1
);
286 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
287 ir_to_mesa_dst_reg dst
,
288 const ir_to_mesa_src_reg
&src
);
290 GLboolean
try_emit_mad(ir_expression
*ir
,
292 GLboolean
try_emit_sat(ir_expression
*ir
);
294 void emit_swz(ir_expression
*ir
);
296 bool process_move_condition(ir_rvalue
*ir
);
298 void copy_propagate(void);
303 ir_to_mesa_src_reg ir_to_mesa_undef
= ir_to_mesa_src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
305 ir_to_mesa_dst_reg ir_to_mesa_undef_dst
= {
306 PROGRAM_UNDEFINED
, 0, SWIZZLE_NOOP
, COND_TR
, NULL
,
309 ir_to_mesa_dst_reg ir_to_mesa_address_reg
= {
310 PROGRAM_ADDRESS
, 0, WRITEMASK_X
, COND_TR
, NULL
314 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
317 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
321 prog
->InfoLog
= talloc_vasprintf_append(prog
->InfoLog
, fmt
, args
);
324 prog
->LinkStatus
= GL_FALSE
;
328 swizzle_for_size(int size
)
330 int size_swizzles
[4] = {
331 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
332 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
333 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
334 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
337 assert((size
>= 1) && (size
<= 4));
338 return size_swizzles
[size
- 1];
341 ir_to_mesa_instruction
*
342 ir_to_mesa_visitor::ir_to_mesa_emit_op3(ir_instruction
*ir
,
344 ir_to_mesa_dst_reg dst
,
345 ir_to_mesa_src_reg src0
,
346 ir_to_mesa_src_reg src1
,
347 ir_to_mesa_src_reg src2
)
349 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
352 /* If we have to do relative addressing, we want to load the ARL
353 * reg directly for one of the regs, and preload the other reladdr
354 * sources into temps.
356 num_reladdr
+= dst
.reladdr
!= NULL
;
357 num_reladdr
+= src0
.reladdr
!= NULL
;
358 num_reladdr
+= src1
.reladdr
!= NULL
;
359 num_reladdr
+= src2
.reladdr
!= NULL
;
361 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
362 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
363 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
366 ir_to_mesa_emit_op1(ir
, OPCODE_ARL
, ir_to_mesa_address_reg
,
371 assert(num_reladdr
== 0);
375 inst
->src_reg
[0] = src0
;
376 inst
->src_reg
[1] = src1
;
377 inst
->src_reg
[2] = src2
;
380 inst
->function
= NULL
;
382 this->instructions
.push_tail(inst
);
388 ir_to_mesa_instruction
*
389 ir_to_mesa_visitor::ir_to_mesa_emit_op2(ir_instruction
*ir
,
391 ir_to_mesa_dst_reg dst
,
392 ir_to_mesa_src_reg src0
,
393 ir_to_mesa_src_reg src1
)
395 return ir_to_mesa_emit_op3(ir
, op
, dst
, src0
, src1
, ir_to_mesa_undef
);
398 ir_to_mesa_instruction
*
399 ir_to_mesa_visitor::ir_to_mesa_emit_op1(ir_instruction
*ir
,
401 ir_to_mesa_dst_reg dst
,
402 ir_to_mesa_src_reg src0
)
404 assert(dst
.writemask
!= 0);
405 return ir_to_mesa_emit_op3(ir
, op
, dst
,
406 src0
, ir_to_mesa_undef
, ir_to_mesa_undef
);
409 ir_to_mesa_instruction
*
410 ir_to_mesa_visitor::ir_to_mesa_emit_op0(ir_instruction
*ir
,
413 return ir_to_mesa_emit_op3(ir
, op
, ir_to_mesa_undef_dst
,
420 ir_to_mesa_visitor::ir_to_mesa_emit_dp(ir_instruction
*ir
,
421 ir_to_mesa_dst_reg dst
,
422 ir_to_mesa_src_reg src0
,
423 ir_to_mesa_src_reg src1
,
426 static const gl_inst_opcode dot_opcodes
[] = {
427 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
430 ir_to_mesa_emit_op3(ir
, dot_opcodes
[elements
- 2],
431 dst
, src0
, src1
, ir_to_mesa_undef
);
434 inline ir_to_mesa_dst_reg
435 ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg reg
)
437 ir_to_mesa_dst_reg dst_reg
;
439 dst_reg
.file
= reg
.file
;
440 dst_reg
.index
= reg
.index
;
441 dst_reg
.writemask
= WRITEMASK_XYZW
;
442 dst_reg
.cond_mask
= COND_TR
;
443 dst_reg
.reladdr
= reg
.reladdr
;
448 inline ir_to_mesa_src_reg
449 ir_to_mesa_src_reg_from_dst(ir_to_mesa_dst_reg reg
)
451 return ir_to_mesa_src_reg(reg
.file
, reg
.index
, NULL
);
455 * Emits Mesa scalar opcodes to produce unique answers across channels.
457 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
458 * channel determines the result across all channels. So to do a vec4
459 * of this operation, we want to emit a scalar per source channel used
460 * to produce dest channels.
463 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op2(ir_instruction
*ir
,
465 ir_to_mesa_dst_reg dst
,
466 ir_to_mesa_src_reg orig_src0
,
467 ir_to_mesa_src_reg orig_src1
)
470 int done_mask
= ~dst
.writemask
;
472 /* Mesa RCP is a scalar operation splatting results to all channels,
473 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
476 for (i
= 0; i
< 4; i
++) {
477 GLuint this_mask
= (1 << i
);
478 ir_to_mesa_instruction
*inst
;
479 ir_to_mesa_src_reg src0
= orig_src0
;
480 ir_to_mesa_src_reg src1
= orig_src1
;
482 if (done_mask
& this_mask
)
485 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
486 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
487 for (j
= i
+ 1; j
< 4; j
++) {
488 /* If there is another enabled component in the destination that is
489 * derived from the same inputs, generate its value on this pass as
492 if (!(done_mask
& (1 << j
)) &&
493 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
494 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
495 this_mask
|= (1 << j
);
498 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
499 src0_swiz
, src0_swiz
);
500 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
501 src1_swiz
, src1_swiz
);
503 inst
= ir_to_mesa_emit_op2(ir
, op
,
507 inst
->dst_reg
.writemask
= this_mask
;
508 done_mask
|= this_mask
;
513 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op1(ir_instruction
*ir
,
515 ir_to_mesa_dst_reg dst
,
516 ir_to_mesa_src_reg src0
)
518 ir_to_mesa_src_reg undef
= ir_to_mesa_undef
;
520 undef
.swizzle
= SWIZZLE_XXXX
;
522 ir_to_mesa_emit_scalar_op2(ir
, op
, dst
, src0
, undef
);
526 * Emit an OPCODE_SCS instruction
528 * The \c SCS opcode functions a bit differently than the other Mesa (or
529 * ARB_fragment_program) opcodes. Instead of splatting its result across all
530 * four components of the destination, it writes one value to the \c x
531 * component and another value to the \c y component.
533 * \param ir IR instruction being processed
534 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
536 * \param dst Destination register
537 * \param src Source register
540 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
541 ir_to_mesa_dst_reg dst
,
542 const ir_to_mesa_src_reg
&src
)
544 /* Vertex programs cannot use the SCS opcode.
546 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
547 ir_to_mesa_emit_scalar_op1(ir
, op
, dst
, src
);
551 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
552 const unsigned scs_mask
= (1U << component
);
553 int done_mask
= ~dst
.writemask
;
554 ir_to_mesa_src_reg tmp
;
556 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
558 /* If there are compnents in the destination that differ from the component
559 * that will be written by the SCS instrution, we'll need a temporary.
561 if (scs_mask
!= unsigned(dst
.writemask
)) {
562 tmp
= get_temp(glsl_type::vec4_type
);
565 for (unsigned i
= 0; i
< 4; i
++) {
566 unsigned this_mask
= (1U << i
);
567 ir_to_mesa_src_reg src0
= src
;
569 if ((done_mask
& this_mask
) != 0)
572 /* The source swizzle specified which component of the source generates
573 * sine / cosine for the current component in the destination. The SCS
574 * instruction requires that this value be swizzle to the X component.
575 * Replace the current swizzle with a swizzle that puts the source in
578 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
580 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
581 src0_swiz
, src0_swiz
);
582 for (unsigned j
= i
+ 1; j
< 4; j
++) {
583 /* If there is another enabled component in the destination that is
584 * derived from the same inputs, generate its value on this pass as
587 if (!(done_mask
& (1 << j
)) &&
588 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
589 this_mask
|= (1 << j
);
593 if (this_mask
!= scs_mask
) {
594 ir_to_mesa_instruction
*inst
;
595 ir_to_mesa_dst_reg tmp_dst
= ir_to_mesa_dst_reg_from_src(tmp
);
597 /* Emit the SCS instruction.
599 inst
= ir_to_mesa_emit_op1(ir
, OPCODE_SCS
, tmp_dst
, src0
);
600 inst
->dst_reg
.writemask
= scs_mask
;
602 /* Move the result of the SCS instruction to the desired location in
605 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
606 component
, component
);
607 inst
= ir_to_mesa_emit_op1(ir
, OPCODE_SCS
, dst
, tmp
);
608 inst
->dst_reg
.writemask
= this_mask
;
610 /* Emit the SCS instruction to write directly to the destination.
612 ir_to_mesa_instruction
*inst
=
613 ir_to_mesa_emit_op1(ir
, OPCODE_SCS
, dst
, src0
);
614 inst
->dst_reg
.writemask
= scs_mask
;
617 done_mask
|= this_mask
;
621 struct ir_to_mesa_src_reg
622 ir_to_mesa_visitor::src_reg_for_float(float val
)
624 ir_to_mesa_src_reg
src_reg(PROGRAM_CONSTANT
, -1, NULL
);
626 src_reg
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
627 &val
, 1, &src_reg
.swizzle
);
633 type_size(const struct glsl_type
*type
)
638 switch (type
->base_type
) {
641 case GLSL_TYPE_FLOAT
:
643 if (type
->is_matrix()) {
644 return type
->matrix_columns
;
646 /* Regardless of size of vector, it gets a vec4. This is bad
647 * packing for things like floats, but otherwise arrays become a
648 * mess. Hopefully a later pass over the code can pack scalars
649 * down if appropriate.
653 case GLSL_TYPE_ARRAY
:
654 return type_size(type
->fields
.array
) * type
->length
;
655 case GLSL_TYPE_STRUCT
:
657 for (i
= 0; i
< type
->length
; i
++) {
658 size
+= type_size(type
->fields
.structure
[i
].type
);
661 case GLSL_TYPE_SAMPLER
:
662 /* Samplers take up one slot in UNIFORMS[], but they're baked in
673 * In the initial pass of codegen, we assign temporary numbers to
674 * intermediate results. (not SSA -- variable assignments will reuse
675 * storage). Actual register allocation for the Mesa VM occurs in a
676 * pass over the Mesa IR later.
679 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
681 ir_to_mesa_src_reg src_reg
;
685 src_reg
.file
= PROGRAM_TEMPORARY
;
686 src_reg
.index
= next_temp
;
687 src_reg
.reladdr
= NULL
;
688 next_temp
+= type_size(type
);
690 if (type
->is_array() || type
->is_record()) {
691 src_reg
.swizzle
= SWIZZLE_NOOP
;
693 for (i
= 0; i
< type
->vector_elements
; i
++)
696 swizzle
[i
] = type
->vector_elements
- 1;
697 src_reg
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1],
698 swizzle
[2], swizzle
[3]);
706 ir_to_mesa_visitor::find_variable_storage(ir_variable
*var
)
709 variable_storage
*entry
;
711 foreach_iter(exec_list_iterator
, iter
, this->variables
) {
712 entry
= (variable_storage
*)iter
.get();
714 if (entry
->var
== var
)
722 ir_to_mesa_visitor::visit(ir_variable
*ir
)
724 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
725 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
727 fp
->OriginUpperLeft
= ir
->origin_upper_left
;
728 fp
->PixelCenterInteger
= ir
->pixel_center_integer
;
731 if (ir
->mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
733 const struct gl_builtin_uniform_desc
*statevar
;
735 for (i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
736 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
740 if (!_mesa_builtin_uniform_desc
[i
].name
) {
741 fail_link(this->shader_program
,
742 "Failed to find builtin uniform `%s'\n", ir
->name
);
746 statevar
= &_mesa_builtin_uniform_desc
[i
];
749 if (ir
->type
->is_array()) {
750 array_count
= ir
->type
->length
;
755 /* Check if this statevar's setup in the STATE file exactly
756 * matches how we'll want to reference it as a
757 * struct/array/whatever. If not, then we need to move it into
758 * temporary storage and hope that it'll get copy-propagated
761 for (i
= 0; i
< statevar
->num_elements
; i
++) {
762 if (statevar
->elements
[i
].swizzle
!= SWIZZLE_XYZW
) {
767 struct variable_storage
*storage
;
768 ir_to_mesa_dst_reg dst
;
769 if (i
== statevar
->num_elements
) {
770 /* We'll set the index later. */
771 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
772 this->variables
.push_tail(storage
);
774 dst
= ir_to_mesa_undef_dst
;
776 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
778 this->variables
.push_tail(storage
);
779 this->next_temp
+= type_size(ir
->type
);
781 dst
= ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg(PROGRAM_TEMPORARY
,
787 for (int a
= 0; a
< array_count
; a
++) {
788 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
789 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
790 int tokens
[STATE_LENGTH
];
792 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
793 if (ir
->type
->is_array()) {
797 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
798 (gl_state_index
*)tokens
);
800 if (storage
->file
== PROGRAM_STATE_VAR
) {
801 if (storage
->index
== -1) {
802 storage
->index
= index
;
805 (int)(storage
->index
+ a
* statevar
->num_elements
+ i
));
808 ir_to_mesa_src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
809 src
.swizzle
= element
->swizzle
;
810 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, dst
, src
);
811 /* even a float takes up a whole vec4 reg in a struct/array. */
816 if (storage
->file
== PROGRAM_TEMPORARY
&&
817 dst
.index
!= storage
->index
+ type_size(ir
->type
)) {
818 fail_link(this->shader_program
,
819 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
820 ir
->name
, dst
.index
- storage
->index
,
821 type_size(ir
->type
));
827 ir_to_mesa_visitor::visit(ir_loop
*ir
)
829 ir_dereference_variable
*counter
= NULL
;
831 if (ir
->counter
!= NULL
)
832 counter
= new(ir
) ir_dereference_variable(ir
->counter
);
834 if (ir
->from
!= NULL
) {
835 assert(ir
->counter
!= NULL
);
837 ir_assignment
*a
= new(ir
) ir_assignment(counter
, ir
->from
, NULL
);
843 ir_to_mesa_emit_op0(NULL
, OPCODE_BGNLOOP
);
847 new(ir
) ir_expression(ir
->cmp
, glsl_type::bool_type
,
849 ir_if
*if_stmt
= new(ir
) ir_if(e
);
851 ir_loop_jump
*brk
= new(ir
) ir_loop_jump(ir_loop_jump::jump_break
);
853 if_stmt
->then_instructions
.push_tail(brk
);
855 if_stmt
->accept(this);
862 visit_exec_list(&ir
->body_instructions
, this);
866 new(ir
) ir_expression(ir_binop_add
, counter
->type
,
867 counter
, ir
->increment
);
869 ir_assignment
*a
= new(ir
) ir_assignment(counter
, e
, NULL
);
876 ir_to_mesa_emit_op0(NULL
, OPCODE_ENDLOOP
);
880 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
883 case ir_loop_jump::jump_break
:
884 ir_to_mesa_emit_op0(NULL
, OPCODE_BRK
);
886 case ir_loop_jump::jump_continue
:
887 ir_to_mesa_emit_op0(NULL
, OPCODE_CONT
);
894 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
901 ir_to_mesa_visitor::visit(ir_function
*ir
)
903 /* Ignore function bodies other than main() -- we shouldn't see calls to
904 * them since they should all be inlined before we get to ir_to_mesa.
906 if (strcmp(ir
->name
, "main") == 0) {
907 const ir_function_signature
*sig
;
910 sig
= ir
->matching_signature(&empty
);
914 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
915 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
923 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
925 int nonmul_operand
= 1 - mul_operand
;
926 ir_to_mesa_src_reg a
, b
, c
;
928 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
929 if (!expr
|| expr
->operation
!= ir_binop_mul
)
932 expr
->operands
[0]->accept(this);
934 expr
->operands
[1]->accept(this);
936 ir
->operands
[nonmul_operand
]->accept(this);
939 this->result
= get_temp(ir
->type
);
940 ir_to_mesa_emit_op3(ir
, OPCODE_MAD
,
941 ir_to_mesa_dst_reg_from_src(this->result
), a
, b
, c
);
947 ir_to_mesa_visitor::try_emit_sat(ir_expression
*ir
)
949 /* Saturates were only introduced to vertex programs in
950 * NV_vertex_program3, so don't give them to drivers in the VP.
952 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
)
955 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
959 sat_src
->accept(this);
960 ir_to_mesa_src_reg src
= this->result
;
962 this->result
= get_temp(ir
->type
);
963 ir_to_mesa_instruction
*inst
;
964 inst
= ir_to_mesa_emit_op1(ir
, OPCODE_MOV
,
965 ir_to_mesa_dst_reg_from_src(this->result
),
967 inst
->saturate
= true;
973 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
974 ir_to_mesa_src_reg
*reg
, int *num_reladdr
)
979 ir_to_mesa_emit_op1(ir
, OPCODE_ARL
, ir_to_mesa_address_reg
, *reg
->reladdr
);
981 if (*num_reladdr
!= 1) {
982 ir_to_mesa_src_reg temp
= get_temp(glsl_type::vec4_type
);
984 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
,
985 ir_to_mesa_dst_reg_from_src(temp
), *reg
);
993 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
995 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
996 * This means that each of the operands is either an immediate value of -1,
997 * 0, or 1, or is a component from one source register (possibly with
1000 uint8_t components
[4] = { 0 };
1001 bool negate
[4] = { false };
1002 ir_variable
*var
= NULL
;
1004 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1005 ir_rvalue
*op
= ir
->operands
[i
];
1007 assert(op
->type
->is_scalar());
1009 while (op
!= NULL
) {
1010 switch (op
->ir_type
) {
1011 case ir_type_constant
: {
1013 assert(op
->type
->is_scalar());
1015 const ir_constant
*const c
= op
->as_constant();
1017 components
[i
] = SWIZZLE_ONE
;
1018 } else if (c
->is_zero()) {
1019 components
[i
] = SWIZZLE_ZERO
;
1020 } else if (c
->is_negative_one()) {
1021 components
[i
] = SWIZZLE_ONE
;
1024 assert(!"SWZ constant must be 0.0 or 1.0.");
1031 case ir_type_dereference_variable
: {
1032 ir_dereference_variable
*const deref
=
1033 (ir_dereference_variable
*) op
;
1035 assert((var
== NULL
) || (deref
->var
== var
));
1036 components
[i
] = SWIZZLE_X
;
1042 case ir_type_expression
: {
1043 ir_expression
*const expr
= (ir_expression
*) op
;
1045 assert(expr
->operation
== ir_unop_neg
);
1048 op
= expr
->operands
[0];
1052 case ir_type_swizzle
: {
1053 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
1055 components
[i
] = swiz
->mask
.x
;
1061 assert(!"Should not get here.");
1067 assert(var
!= NULL
);
1069 ir_dereference_variable
*const deref
=
1070 new(mem_ctx
) ir_dereference_variable(var
);
1072 this->result
.file
= PROGRAM_UNDEFINED
;
1073 deref
->accept(this);
1074 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1076 printf("Failed to get tree for expression operand:\n");
1081 ir_to_mesa_src_reg src
;
1084 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
1088 src
.negate
= ((unsigned(negate
[0]) << 0)
1089 | (unsigned(negate
[1]) << 1)
1090 | (unsigned(negate
[2]) << 2)
1091 | (unsigned(negate
[3]) << 3));
1093 /* Storage for our result. Ideally for an assignment we'd be using the
1094 * actual storage for the result here, instead.
1096 const ir_to_mesa_src_reg result_src
= get_temp(ir
->type
);
1097 ir_to_mesa_dst_reg result_dst
= ir_to_mesa_dst_reg_from_src(result_src
);
1099 /* Limit writes to the channels that will be used by result_src later.
1100 * This does limit this temp's use as a temporary for multi-instruction
1103 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1105 ir_to_mesa_emit_op1(ir
, OPCODE_SWZ
, result_dst
, src
);
1106 this->result
= result_src
;
1110 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1112 unsigned int operand
;
1113 struct ir_to_mesa_src_reg op
[Elements(ir
->operands
)];
1114 struct ir_to_mesa_src_reg result_src
;
1115 struct ir_to_mesa_dst_reg result_dst
;
1117 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1119 if (ir
->operation
== ir_binop_add
) {
1120 if (try_emit_mad(ir
, 1))
1122 if (try_emit_mad(ir
, 0))
1125 if (try_emit_sat(ir
))
1128 if (ir
->operation
== ir_quadop_vector
) {
1133 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1134 this->result
.file
= PROGRAM_UNDEFINED
;
1135 ir
->operands
[operand
]->accept(this);
1136 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1138 printf("Failed to get tree for expression operand:\n");
1139 ir
->operands
[operand
]->accept(&v
);
1142 op
[operand
] = this->result
;
1144 /* Matrix expression operands should have been broken down to vector
1145 * operations already.
1147 assert(!ir
->operands
[operand
]->type
->is_matrix());
1150 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1151 if (ir
->operands
[1]) {
1152 vector_elements
= MAX2(vector_elements
,
1153 ir
->operands
[1]->type
->vector_elements
);
1156 this->result
.file
= PROGRAM_UNDEFINED
;
1158 /* Storage for our result. Ideally for an assignment we'd be using
1159 * the actual storage for the result here, instead.
1161 result_src
= get_temp(ir
->type
);
1162 /* convenience for the emit functions below. */
1163 result_dst
= ir_to_mesa_dst_reg_from_src(result_src
);
1164 /* Limit writes to the channels that will be used by result_src later.
1165 * This does limit this temp's use as a temporary for multi-instruction
1168 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1170 switch (ir
->operation
) {
1171 case ir_unop_logic_not
:
1172 ir_to_mesa_emit_op2(ir
, OPCODE_SEQ
, result_dst
,
1173 op
[0], src_reg_for_float(0.0));
1176 op
[0].negate
= ~op
[0].negate
;
1180 ir_to_mesa_emit_op1(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1183 ir_to_mesa_emit_op1(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1186 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1190 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1194 assert(!"not reached: should be handled by ir_explog_to_explog2");
1197 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1200 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1203 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_COS
, result_dst
, op
[0]);
1205 case ir_unop_sin_reduced
:
1206 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1208 case ir_unop_cos_reduced
:
1209 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1213 ir_to_mesa_emit_op1(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1216 ir_to_mesa_emit_op1(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1219 case ir_unop_noise
: {
1220 const enum prog_opcode opcode
=
1221 prog_opcode(OPCODE_NOISE1
1222 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1223 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1225 ir_to_mesa_emit_op1(ir
, opcode
, result_dst
, op
[0]);
1230 ir_to_mesa_emit_op2(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1233 ir_to_mesa_emit_op2(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1237 ir_to_mesa_emit_op2(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1240 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1242 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1246 ir_to_mesa_emit_op2(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1248 case ir_binop_greater
:
1249 ir_to_mesa_emit_op2(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1251 case ir_binop_lequal
:
1252 ir_to_mesa_emit_op2(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1254 case ir_binop_gequal
:
1255 ir_to_mesa_emit_op2(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1257 case ir_binop_equal
:
1258 ir_to_mesa_emit_op2(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1260 case ir_binop_nequal
:
1261 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1263 case ir_binop_all_equal
:
1264 /* "==" operator producing a scalar boolean. */
1265 if (ir
->operands
[0]->type
->is_vector() ||
1266 ir
->operands
[1]->type
->is_vector()) {
1267 ir_to_mesa_src_reg temp
= get_temp(glsl_type::vec4_type
);
1268 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
,
1269 ir_to_mesa_dst_reg_from_src(temp
), op
[0], op
[1]);
1270 ir_to_mesa_emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1271 ir_to_mesa_emit_op2(ir
, OPCODE_SEQ
,
1272 result_dst
, result_src
, src_reg_for_float(0.0));
1274 ir_to_mesa_emit_op2(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1277 case ir_binop_any_nequal
:
1278 /* "!=" operator producing a scalar boolean. */
1279 if (ir
->operands
[0]->type
->is_vector() ||
1280 ir
->operands
[1]->type
->is_vector()) {
1281 ir_to_mesa_src_reg temp
= get_temp(glsl_type::vec4_type
);
1282 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
,
1283 ir_to_mesa_dst_reg_from_src(temp
), op
[0], op
[1]);
1284 ir_to_mesa_emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1285 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
,
1286 result_dst
, result_src
, src_reg_for_float(0.0));
1288 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1293 assert(ir
->operands
[0]->type
->is_vector());
1294 ir_to_mesa_emit_dp(ir
, result_dst
, op
[0], op
[0],
1295 ir
->operands
[0]->type
->vector_elements
);
1296 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
,
1297 result_dst
, result_src
, src_reg_for_float(0.0));
1300 case ir_binop_logic_xor
:
1301 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1304 case ir_binop_logic_or
:
1305 /* This could be a saturated add and skip the SNE. */
1306 ir_to_mesa_emit_op2(ir
, OPCODE_ADD
,
1310 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
,
1312 result_src
, src_reg_for_float(0.0));
1315 case ir_binop_logic_and
:
1316 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1317 ir_to_mesa_emit_op2(ir
, OPCODE_MUL
,
1323 assert(ir
->operands
[0]->type
->is_vector());
1324 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1325 ir_to_mesa_emit_dp(ir
, result_dst
, op
[0], op
[1],
1326 ir
->operands
[0]->type
->vector_elements
);
1330 /* sqrt(x) = x * rsq(x). */
1331 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1332 ir_to_mesa_emit_op2(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1333 /* For incoming channels <= 0, set the result to 0. */
1334 op
[0].negate
= ~op
[0].negate
;
1335 ir_to_mesa_emit_op3(ir
, OPCODE_CMP
, result_dst
,
1336 op
[0], result_src
, src_reg_for_float(0.0));
1339 ir_to_mesa_emit_scalar_op1(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1344 /* Mesa IR lacks types, ints are stored as truncated floats. */
1348 ir_to_mesa_emit_op1(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1352 ir_to_mesa_emit_op2(ir
, OPCODE_SNE
, result_dst
,
1353 op
[0], src_reg_for_float(0.0));
1356 ir_to_mesa_emit_op1(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1359 op
[0].negate
= ~op
[0].negate
;
1360 ir_to_mesa_emit_op1(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1361 result_src
.negate
= ~result_src
.negate
;
1364 ir_to_mesa_emit_op1(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1367 ir_to_mesa_emit_op1(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1371 ir_to_mesa_emit_op2(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1374 ir_to_mesa_emit_op2(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1377 ir_to_mesa_emit_scalar_op2(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1380 case ir_unop_bit_not
:
1382 case ir_binop_lshift
:
1383 case ir_binop_rshift
:
1384 case ir_binop_bit_and
:
1385 case ir_binop_bit_xor
:
1386 case ir_binop_bit_or
:
1387 case ir_unop_round_even
:
1388 assert(!"GLSL 1.30 features unsupported");
1391 case ir_quadop_vector
:
1392 /* This operation should have already been handled.
1394 assert(!"Should not get here.");
1398 this->result
= result_src
;
1403 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1405 ir_to_mesa_src_reg src_reg
;
1409 /* Note that this is only swizzles in expressions, not those on the left
1410 * hand side of an assignment, which do write masking. See ir_assignment
1414 ir
->val
->accept(this);
1415 src_reg
= this->result
;
1416 assert(src_reg
.file
!= PROGRAM_UNDEFINED
);
1418 for (i
= 0; i
< 4; i
++) {
1419 if (i
< ir
->type
->vector_elements
) {
1422 swizzle
[i
] = GET_SWZ(src_reg
.swizzle
, ir
->mask
.x
);
1425 swizzle
[i
] = GET_SWZ(src_reg
.swizzle
, ir
->mask
.y
);
1428 swizzle
[i
] = GET_SWZ(src_reg
.swizzle
, ir
->mask
.z
);
1431 swizzle
[i
] = GET_SWZ(src_reg
.swizzle
, ir
->mask
.w
);
1435 /* If the type is smaller than a vec4, replicate the last
1438 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1442 src_reg
.swizzle
= MAKE_SWIZZLE4(swizzle
[0],
1447 this->result
= src_reg
;
1451 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1453 variable_storage
*entry
= find_variable_storage(ir
->var
);
1456 switch (ir
->var
->mode
) {
1457 case ir_var_uniform
:
1458 entry
= new(mem_ctx
) variable_storage(ir
->var
, PROGRAM_UNIFORM
,
1460 this->variables
.push_tail(entry
);
1465 /* The linker assigns locations for varyings and attributes,
1466 * including deprecated builtins (like gl_Color), user-assign
1467 * generic attributes (glBindVertexLocation), and
1468 * user-defined varyings.
1470 * FINISHME: We would hit this path for function arguments. Fix!
1472 assert(ir
->var
->location
!= -1);
1473 if (ir
->var
->mode
== ir_var_in
||
1474 ir
->var
->mode
== ir_var_inout
) {
1475 entry
= new(mem_ctx
) variable_storage(ir
->var
,
1479 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
1480 ir
->var
->location
>= VERT_ATTRIB_GENERIC0
) {
1481 _mesa_add_attribute(prog
->Attributes
,
1483 _mesa_sizeof_glsl_type(ir
->var
->type
->gl_type
),
1484 ir
->var
->type
->gl_type
,
1485 ir
->var
->location
- VERT_ATTRIB_GENERIC0
);
1488 entry
= new(mem_ctx
) variable_storage(ir
->var
,
1495 case ir_var_temporary
:
1496 entry
= new(mem_ctx
) variable_storage(ir
->var
, PROGRAM_TEMPORARY
,
1498 this->variables
.push_tail(entry
);
1500 next_temp
+= type_size(ir
->var
->type
);
1505 printf("Failed to make storage for %s\n", ir
->var
->name
);
1510 this->result
= ir_to_mesa_src_reg(entry
->file
, entry
->index
, ir
->var
->type
);
1514 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1517 ir_to_mesa_src_reg src_reg
;
1518 int element_size
= type_size(ir
->type
);
1520 index
= ir
->array_index
->constant_expression_value();
1522 ir
->array
->accept(this);
1523 src_reg
= this->result
;
1526 src_reg
.index
+= index
->value
.i
[0] * element_size
;
1528 ir_to_mesa_src_reg array_base
= this->result
;
1529 /* Variable index array dereference. It eats the "vec4" of the
1530 * base of the array and an index that offsets the Mesa register
1533 ir
->array_index
->accept(this);
1535 ir_to_mesa_src_reg index_reg
;
1537 if (element_size
== 1) {
1538 index_reg
= this->result
;
1540 index_reg
= get_temp(glsl_type::float_type
);
1542 ir_to_mesa_emit_op2(ir
, OPCODE_MUL
,
1543 ir_to_mesa_dst_reg_from_src(index_reg
),
1544 this->result
, src_reg_for_float(element_size
));
1547 src_reg
.reladdr
= talloc(mem_ctx
, ir_to_mesa_src_reg
);
1548 memcpy(src_reg
.reladdr
, &index_reg
, sizeof(index_reg
));
1551 /* If the type is smaller than a vec4, replicate the last channel out. */
1552 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1553 src_reg
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1555 src_reg
.swizzle
= SWIZZLE_NOOP
;
1557 this->result
= src_reg
;
1561 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1564 const glsl_type
*struct_type
= ir
->record
->type
;
1567 ir
->record
->accept(this);
1569 for (i
= 0; i
< struct_type
->length
; i
++) {
1570 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1572 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1575 /* If the type is smaller than a vec4, replicate the last channel out. */
1576 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1577 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1579 this->result
.swizzle
= SWIZZLE_NOOP
;
1581 this->result
.index
+= offset
;
1585 * We want to be careful in assignment setup to hit the actual storage
1586 * instead of potentially using a temporary like we might with the
1587 * ir_dereference handler.
1589 static struct ir_to_mesa_dst_reg
1590 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1592 /* The LHS must be a dereference. If the LHS is a variable indexed array
1593 * access of a vector, it must be separated into a series conditional moves
1594 * before reaching this point (see ir_vec_index_to_cond_assign).
1596 assert(ir
->as_dereference());
1597 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1599 assert(!deref_array
->array
->type
->is_vector());
1602 /* Use the rvalue deref handler for the most part. We'll ignore
1603 * swizzles in it and write swizzles using writemask, though.
1606 return ir_to_mesa_dst_reg_from_src(v
->result
);
1610 * Process the condition of a conditional assignment
1612 * Examines the condition of a conditional assignment to generate the optimal
1613 * first operand of a \c CMP instruction. If the condition is a relational
1614 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1615 * used as the source for the \c CMP instruction. Otherwise the comparison
1616 * is processed to a boolean result, and the boolean result is used as the
1617 * operand to the CMP instruction.
1620 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1622 ir_rvalue
*src_ir
= ir
;
1624 bool switch_order
= false;
1626 ir_expression
*const expr
= ir
->as_expression();
1627 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1628 bool zero_on_left
= false;
1630 if (expr
->operands
[0]->is_zero()) {
1631 src_ir
= expr
->operands
[1];
1632 zero_on_left
= true;
1633 } else if (expr
->operands
[1]->is_zero()) {
1634 src_ir
= expr
->operands
[0];
1635 zero_on_left
= false;
1639 * (a < 0) T F F ( a < 0) T F F
1640 * (0 < a) F F T (-a < 0) F F T
1641 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1642 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1643 * (a > 0) F F T (-a < 0) F F T
1644 * (0 > a) T F F ( a < 0) T F F
1645 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1646 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1648 * Note that exchanging the order of 0 and 'a' in the comparison simply
1649 * means that the value of 'a' should be negated.
1652 switch (expr
->operation
) {
1654 switch_order
= false;
1655 negate
= zero_on_left
;
1658 case ir_binop_greater
:
1659 switch_order
= false;
1660 negate
= !zero_on_left
;
1663 case ir_binop_lequal
:
1664 switch_order
= true;
1665 negate
= !zero_on_left
;
1668 case ir_binop_gequal
:
1669 switch_order
= true;
1670 negate
= zero_on_left
;
1674 /* This isn't the right kind of comparison afterall, so make sure
1675 * the whole condition is visited.
1683 src_ir
->accept(this);
1685 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1686 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1687 * choose which value OPCODE_CMP produces without an extra instruction
1688 * computing the condition.
1691 this->result
.negate
= ~this->result
.negate
;
1693 return switch_order
;
1697 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1699 struct ir_to_mesa_dst_reg l
;
1700 struct ir_to_mesa_src_reg r
;
1703 ir
->rhs
->accept(this);
1706 l
= get_assignment_lhs(ir
->lhs
, this);
1708 /* FINISHME: This should really set to the correct maximal writemask for each
1709 * FINISHME: component written (in the loops below). This case can only
1710 * FINISHME: occur for matrices, arrays, and structures.
1712 if (ir
->write_mask
== 0) {
1713 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1714 l
.writemask
= WRITEMASK_XYZW
;
1715 } else if (ir
->lhs
->type
->is_scalar()) {
1716 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1717 * FINISHME: W component of fragment shader output zero, work correctly.
1719 l
.writemask
= WRITEMASK_XYZW
;
1722 int first_enabled_chan
= 0;
1725 assert(ir
->lhs
->type
->is_vector());
1726 l
.writemask
= ir
->write_mask
;
1728 for (int i
= 0; i
< 4; i
++) {
1729 if (l
.writemask
& (1 << i
)) {
1730 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1735 /* Swizzle a small RHS vector into the channels being written.
1737 * glsl ir treats write_mask as dictating how many channels are
1738 * present on the RHS while Mesa IR treats write_mask as just
1739 * showing which channels of the vec4 RHS get written.
1741 for (int i
= 0; i
< 4; i
++) {
1742 if (l
.writemask
& (1 << i
))
1743 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1745 swizzles
[i
] = first_enabled_chan
;
1747 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1748 swizzles
[2], swizzles
[3]);
1751 assert(l
.file
!= PROGRAM_UNDEFINED
);
1752 assert(r
.file
!= PROGRAM_UNDEFINED
);
1754 if (ir
->condition
) {
1755 const bool switch_order
= this->process_move_condition(ir
->condition
);
1756 ir_to_mesa_src_reg condition
= this->result
;
1758 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1760 ir_to_mesa_emit_op3(ir
, OPCODE_CMP
, l
,
1761 condition
, ir_to_mesa_src_reg_from_dst(l
), r
);
1763 ir_to_mesa_emit_op3(ir
, OPCODE_CMP
, l
,
1764 condition
, r
, ir_to_mesa_src_reg_from_dst(l
));
1771 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1772 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, l
, r
);
1781 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1783 ir_to_mesa_src_reg src_reg
;
1784 GLfloat stack_vals
[4] = { 0 };
1785 GLfloat
*values
= stack_vals
;
1788 /* Unfortunately, 4 floats is all we can get into
1789 * _mesa_add_unnamed_constant. So, make a temp to store an
1790 * aggregate constant and move each constant value into it. If we
1791 * get lucky, copy propagation will eliminate the extra moves.
1794 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1795 ir_to_mesa_src_reg temp_base
= get_temp(ir
->type
);
1796 ir_to_mesa_dst_reg temp
= ir_to_mesa_dst_reg_from_src(temp_base
);
1798 foreach_iter(exec_list_iterator
, iter
, ir
->components
) {
1799 ir_constant
*field_value
= (ir_constant
*)iter
.get();
1800 int size
= type_size(field_value
->type
);
1804 field_value
->accept(this);
1805 src_reg
= this->result
;
1807 for (i
= 0; i
< (unsigned int)size
; i
++) {
1808 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, temp
, src_reg
);
1814 this->result
= temp_base
;
1818 if (ir
->type
->is_array()) {
1819 ir_to_mesa_src_reg temp_base
= get_temp(ir
->type
);
1820 ir_to_mesa_dst_reg temp
= ir_to_mesa_dst_reg_from_src(temp_base
);
1821 int size
= type_size(ir
->type
->fields
.array
);
1825 for (i
= 0; i
< ir
->type
->length
; i
++) {
1826 ir
->array_elements
[i
]->accept(this);
1827 src_reg
= this->result
;
1828 for (int j
= 0; j
< size
; j
++) {
1829 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, temp
, src_reg
);
1835 this->result
= temp_base
;
1839 if (ir
->type
->is_matrix()) {
1840 ir_to_mesa_src_reg mat
= get_temp(ir
->type
);
1841 ir_to_mesa_dst_reg mat_column
= ir_to_mesa_dst_reg_from_src(mat
);
1843 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1844 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1845 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1847 src_reg
= ir_to_mesa_src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1848 src_reg
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1850 ir
->type
->vector_elements
,
1852 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, mat_column
, src_reg
);
1861 src_reg
.file
= PROGRAM_CONSTANT
;
1862 switch (ir
->type
->base_type
) {
1863 case GLSL_TYPE_FLOAT
:
1864 values
= &ir
->value
.f
[0];
1866 case GLSL_TYPE_UINT
:
1867 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1868 values
[i
] = ir
->value
.u
[i
];
1872 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1873 values
[i
] = ir
->value
.i
[i
];
1876 case GLSL_TYPE_BOOL
:
1877 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1878 values
[i
] = ir
->value
.b
[i
];
1882 assert(!"Non-float/uint/int/bool constant");
1885 this->result
= ir_to_mesa_src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1886 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1888 ir
->type
->vector_elements
,
1889 &this->result
.swizzle
);
1893 ir_to_mesa_visitor::get_function_signature(ir_function_signature
*sig
)
1895 function_entry
*entry
;
1897 foreach_iter(exec_list_iterator
, iter
, this->function_signatures
) {
1898 entry
= (function_entry
*)iter
.get();
1900 if (entry
->sig
== sig
)
1904 entry
= talloc(mem_ctx
, function_entry
);
1906 entry
->sig_id
= this->next_signature_id
++;
1907 entry
->bgn_inst
= NULL
;
1909 /* Allocate storage for all the parameters. */
1910 foreach_iter(exec_list_iterator
, iter
, sig
->parameters
) {
1911 ir_variable
*param
= (ir_variable
*)iter
.get();
1912 variable_storage
*storage
;
1914 storage
= find_variable_storage(param
);
1917 storage
= new(mem_ctx
) variable_storage(param
, PROGRAM_TEMPORARY
,
1919 this->variables
.push_tail(storage
);
1921 this->next_temp
+= type_size(param
->type
);
1924 if (!sig
->return_type
->is_void()) {
1925 entry
->return_reg
= get_temp(sig
->return_type
);
1927 entry
->return_reg
= ir_to_mesa_undef
;
1930 this->function_signatures
.push_tail(entry
);
1935 ir_to_mesa_visitor::visit(ir_call
*ir
)
1937 ir_to_mesa_instruction
*call_inst
;
1938 ir_function_signature
*sig
= ir
->get_callee();
1939 function_entry
*entry
= get_function_signature(sig
);
1942 /* Process in parameters. */
1943 exec_list_iterator sig_iter
= sig
->parameters
.iterator();
1944 foreach_iter(exec_list_iterator
, iter
, *ir
) {
1945 ir_rvalue
*param_rval
= (ir_rvalue
*)iter
.get();
1946 ir_variable
*param
= (ir_variable
*)sig_iter
.get();
1948 if (param
->mode
== ir_var_in
||
1949 param
->mode
== ir_var_inout
) {
1950 variable_storage
*storage
= find_variable_storage(param
);
1953 param_rval
->accept(this);
1954 ir_to_mesa_src_reg r
= this->result
;
1956 ir_to_mesa_dst_reg l
;
1957 l
.file
= storage
->file
;
1958 l
.index
= storage
->index
;
1960 l
.writemask
= WRITEMASK_XYZW
;
1961 l
.cond_mask
= COND_TR
;
1963 for (i
= 0; i
< type_size(param
->type
); i
++) {
1964 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, l
, r
);
1972 assert(!sig_iter
.has_next());
1974 /* Emit call instruction */
1975 call_inst
= ir_to_mesa_emit_op1(ir
, OPCODE_CAL
,
1976 ir_to_mesa_undef_dst
, ir_to_mesa_undef
);
1977 call_inst
->function
= entry
;
1979 /* Process out parameters. */
1980 sig_iter
= sig
->parameters
.iterator();
1981 foreach_iter(exec_list_iterator
, iter
, *ir
) {
1982 ir_rvalue
*param_rval
= (ir_rvalue
*)iter
.get();
1983 ir_variable
*param
= (ir_variable
*)sig_iter
.get();
1985 if (param
->mode
== ir_var_out
||
1986 param
->mode
== ir_var_inout
) {
1987 variable_storage
*storage
= find_variable_storage(param
);
1990 ir_to_mesa_src_reg r
;
1991 r
.file
= storage
->file
;
1992 r
.index
= storage
->index
;
1994 r
.swizzle
= SWIZZLE_NOOP
;
1997 param_rval
->accept(this);
1998 ir_to_mesa_dst_reg l
= ir_to_mesa_dst_reg_from_src(this->result
);
2000 for (i
= 0; i
< type_size(param
->type
); i
++) {
2001 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, l
, r
);
2009 assert(!sig_iter
.has_next());
2011 /* Process return value. */
2012 this->result
= entry
->return_reg
;
2016 ir_to_mesa_visitor::visit(ir_texture
*ir
)
2018 ir_to_mesa_src_reg result_src
, coord
, lod_info
, projector
;
2019 ir_to_mesa_dst_reg result_dst
, coord_dst
;
2020 ir_to_mesa_instruction
*inst
= NULL
;
2021 prog_opcode opcode
= OPCODE_NOP
;
2023 ir
->coordinate
->accept(this);
2025 /* Put our coords in a temp. We'll need to modify them for shadow,
2026 * projection, or LOD, so the only case we'd use it as is is if
2027 * we're doing plain old texturing. Mesa IR optimization should
2028 * handle cleaning up our mess in that case.
2030 coord
= get_temp(glsl_type::vec4_type
);
2031 coord_dst
= ir_to_mesa_dst_reg_from_src(coord
);
2032 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, coord_dst
,
2035 if (ir
->projector
) {
2036 ir
->projector
->accept(this);
2037 projector
= this->result
;
2040 /* Storage for our result. Ideally for an assignment we'd be using
2041 * the actual storage for the result here, instead.
2043 result_src
= get_temp(glsl_type::vec4_type
);
2044 result_dst
= ir_to_mesa_dst_reg_from_src(result_src
);
2048 opcode
= OPCODE_TEX
;
2051 opcode
= OPCODE_TXB
;
2052 ir
->lod_info
.bias
->accept(this);
2053 lod_info
= this->result
;
2056 opcode
= OPCODE_TXL
;
2057 ir
->lod_info
.lod
->accept(this);
2058 lod_info
= this->result
;
2062 assert(!"GLSL 1.30 features unsupported");
2066 if (ir
->projector
) {
2067 if (opcode
== OPCODE_TEX
) {
2068 /* Slot the projector in as the last component of the coord. */
2069 coord_dst
.writemask
= WRITEMASK_W
;
2070 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, coord_dst
, projector
);
2071 coord_dst
.writemask
= WRITEMASK_XYZW
;
2072 opcode
= OPCODE_TXP
;
2074 ir_to_mesa_src_reg coord_w
= coord
;
2075 coord_w
.swizzle
= SWIZZLE_WWWW
;
2077 /* For the other TEX opcodes there's no projective version
2078 * since the last slot is taken up by lod info. Do the
2079 * projective divide now.
2081 coord_dst
.writemask
= WRITEMASK_W
;
2082 ir_to_mesa_emit_op1(ir
, OPCODE_RCP
, coord_dst
, projector
);
2084 coord_dst
.writemask
= WRITEMASK_XYZ
;
2085 ir_to_mesa_emit_op2(ir
, OPCODE_MUL
, coord_dst
, coord
, coord_w
);
2087 coord_dst
.writemask
= WRITEMASK_XYZW
;
2088 coord
.swizzle
= SWIZZLE_XYZW
;
2092 if (ir
->shadow_comparitor
) {
2093 /* Slot the shadow value in as the second to last component of the
2096 ir
->shadow_comparitor
->accept(this);
2097 coord_dst
.writemask
= WRITEMASK_Z
;
2098 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2099 coord_dst
.writemask
= WRITEMASK_XYZW
;
2102 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2103 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2104 coord_dst
.writemask
= WRITEMASK_W
;
2105 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2106 coord_dst
.writemask
= WRITEMASK_XYZW
;
2109 inst
= ir_to_mesa_emit_op1(ir
, opcode
, result_dst
, coord
);
2111 if (ir
->shadow_comparitor
)
2112 inst
->tex_shadow
= GL_TRUE
;
2114 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2115 this->shader_program
,
2118 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2120 switch (sampler_type
->sampler_dimensionality
) {
2121 case GLSL_SAMPLER_DIM_1D
:
2122 inst
->tex_target
= (sampler_type
->sampler_array
)
2123 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2125 case GLSL_SAMPLER_DIM_2D
:
2126 inst
->tex_target
= (sampler_type
->sampler_array
)
2127 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2129 case GLSL_SAMPLER_DIM_3D
:
2130 inst
->tex_target
= TEXTURE_3D_INDEX
;
2132 case GLSL_SAMPLER_DIM_CUBE
:
2133 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2135 case GLSL_SAMPLER_DIM_RECT
:
2136 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2138 case GLSL_SAMPLER_DIM_BUF
:
2139 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2142 assert(!"Should not get here.");
2145 this->result
= result_src
;
2149 ir_to_mesa_visitor::visit(ir_return
*ir
)
2151 if (ir
->get_value()) {
2152 ir_to_mesa_dst_reg l
;
2155 assert(current_function
);
2157 ir
->get_value()->accept(this);
2158 ir_to_mesa_src_reg r
= this->result
;
2160 l
= ir_to_mesa_dst_reg_from_src(current_function
->return_reg
);
2162 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
2163 ir_to_mesa_emit_op1(ir
, OPCODE_MOV
, l
, r
);
2169 ir_to_mesa_emit_op0(ir
, OPCODE_RET
);
2173 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2175 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
2177 if (ir
->condition
) {
2178 ir
->condition
->accept(this);
2179 this->result
.negate
= ~this->result
.negate
;
2180 ir_to_mesa_emit_op1(ir
, OPCODE_KIL
, ir_to_mesa_undef_dst
, this->result
);
2182 ir_to_mesa_emit_op0(ir
, OPCODE_KIL_NV
);
2185 fp
->UsesKill
= GL_TRUE
;
2189 ir_to_mesa_visitor::visit(ir_if
*ir
)
2191 ir_to_mesa_instruction
*cond_inst
, *if_inst
, *else_inst
= NULL
;
2192 ir_to_mesa_instruction
*prev_inst
;
2194 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2196 ir
->condition
->accept(this);
2197 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2199 if (this->options
->EmitCondCodes
) {
2200 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2202 /* See if we actually generated any instruction for generating
2203 * the condition. If not, then cook up a move to a temp so we
2204 * have something to set cond_update on.
2206 if (cond_inst
== prev_inst
) {
2207 ir_to_mesa_src_reg temp
= get_temp(glsl_type::bool_type
);
2208 cond_inst
= ir_to_mesa_emit_op1(ir
->condition
, OPCODE_MOV
,
2209 ir_to_mesa_dst_reg_from_src(temp
),
2212 cond_inst
->cond_update
= GL_TRUE
;
2214 if_inst
= ir_to_mesa_emit_op0(ir
->condition
, OPCODE_IF
);
2215 if_inst
->dst_reg
.cond_mask
= COND_NE
;
2217 if_inst
= ir_to_mesa_emit_op1(ir
->condition
,
2218 OPCODE_IF
, ir_to_mesa_undef_dst
,
2222 this->instructions
.push_tail(if_inst
);
2224 visit_exec_list(&ir
->then_instructions
, this);
2226 if (!ir
->else_instructions
.is_empty()) {
2227 else_inst
= ir_to_mesa_emit_op0(ir
->condition
, OPCODE_ELSE
);
2228 visit_exec_list(&ir
->else_instructions
, this);
2231 if_inst
= ir_to_mesa_emit_op1(ir
->condition
, OPCODE_ENDIF
,
2232 ir_to_mesa_undef_dst
, ir_to_mesa_undef
);
2235 ir_to_mesa_visitor::ir_to_mesa_visitor()
2237 result
.file
= PROGRAM_UNDEFINED
;
2239 next_signature_id
= 1;
2240 current_function
= NULL
;
2241 mem_ctx
= talloc_new(NULL
);
2244 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2246 talloc_free(mem_ctx
);
2249 static struct prog_src_register
2250 mesa_src_reg_from_ir_src_reg(ir_to_mesa_src_reg reg
)
2252 struct prog_src_register mesa_reg
;
2254 mesa_reg
.File
= reg
.file
;
2255 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2256 mesa_reg
.Index
= reg
.index
;
2257 mesa_reg
.Swizzle
= reg
.swizzle
;
2258 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2259 mesa_reg
.Negate
= reg
.negate
;
2261 mesa_reg
.HasIndex2
= GL_FALSE
;
2262 mesa_reg
.RelAddr2
= 0;
2263 mesa_reg
.Index2
= 0;
2269 set_branchtargets(ir_to_mesa_visitor
*v
,
2270 struct prog_instruction
*mesa_instructions
,
2271 int num_instructions
)
2273 int if_count
= 0, loop_count
= 0;
2274 int *if_stack
, *loop_stack
;
2275 int if_stack_pos
= 0, loop_stack_pos
= 0;
2278 for (i
= 0; i
< num_instructions
; i
++) {
2279 switch (mesa_instructions
[i
].Opcode
) {
2283 case OPCODE_BGNLOOP
:
2288 mesa_instructions
[i
].BranchTarget
= -1;
2295 if_stack
= talloc_zero_array(v
->mem_ctx
, int, if_count
);
2296 loop_stack
= talloc_zero_array(v
->mem_ctx
, int, loop_count
);
2298 for (i
= 0; i
< num_instructions
; i
++) {
2299 switch (mesa_instructions
[i
].Opcode
) {
2301 if_stack
[if_stack_pos
] = i
;
2305 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2306 if_stack
[if_stack_pos
- 1] = i
;
2309 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2312 case OPCODE_BGNLOOP
:
2313 loop_stack
[loop_stack_pos
] = i
;
2316 case OPCODE_ENDLOOP
:
2318 /* Rewrite any breaks/conts at this nesting level (haven't
2319 * already had a BranchTarget assigned) to point to the end
2322 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2323 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2324 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2325 if (mesa_instructions
[j
].BranchTarget
== -1) {
2326 mesa_instructions
[j
].BranchTarget
= i
;
2330 /* The loop ends point at each other. */
2331 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2332 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2335 foreach_iter(exec_list_iterator
, iter
, v
->function_signatures
) {
2336 function_entry
*entry
= (function_entry
*)iter
.get();
2338 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2339 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2351 print_program(struct prog_instruction
*mesa_instructions
,
2352 ir_instruction
**mesa_instruction_annotation
,
2353 int num_instructions
)
2355 ir_instruction
*last_ir
= NULL
;
2359 for (i
= 0; i
< num_instructions
; i
++) {
2360 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2361 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2363 fprintf(stdout
, "%3d: ", i
);
2365 if (last_ir
!= ir
&& ir
) {
2368 for (j
= 0; j
< indent
; j
++) {
2369 fprintf(stdout
, " ");
2375 fprintf(stdout
, " "); /* line number spacing. */
2378 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2379 PROG_PRINT_DEBUG
, NULL
);
2384 count_resources(struct gl_program
*prog
)
2388 prog
->SamplersUsed
= 0;
2390 for (i
= 0; i
< prog
->NumInstructions
; i
++) {
2391 struct prog_instruction
*inst
= &prog
->Instructions
[i
];
2393 if (_mesa_is_tex_instruction(inst
->Opcode
)) {
2394 prog
->SamplerTargets
[inst
->TexSrcUnit
] =
2395 (gl_texture_index
)inst
->TexSrcTarget
;
2396 prog
->SamplersUsed
|= 1 << inst
->TexSrcUnit
;
2397 if (inst
->TexShadow
) {
2398 prog
->ShadowSamplers
|= 1 << inst
->TexSrcUnit
;
2403 _mesa_update_shader_textures_used(prog
);
2406 struct uniform_sort
{
2407 struct gl_uniform
*u
;
2411 /* The shader_program->Uniforms list is almost sorted in increasing
2412 * uniform->{Frag,Vert}Pos locations, but not quite when there are
2413 * uniforms shared between targets. We need to add parameters in
2414 * increasing order for the targets.
2417 sort_uniforms(const void *a
, const void *b
)
2419 struct uniform_sort
*u1
= (struct uniform_sort
*)a
;
2420 struct uniform_sort
*u2
= (struct uniform_sort
*)b
;
2422 return u1
->pos
- u2
->pos
;
2425 /* Add the uniforms to the parameters. The linker chose locations
2426 * in our parameters lists (which weren't created yet), which the
2427 * uniforms code will use to poke values into our parameters list
2428 * when uniforms are updated.
2431 add_uniforms_to_parameters_list(struct gl_shader_program
*shader_program
,
2432 struct gl_shader
*shader
,
2433 struct gl_program
*prog
)
2436 unsigned int next_sampler
= 0, num_uniforms
= 0;
2437 struct uniform_sort
*sorted_uniforms
;
2439 sorted_uniforms
= talloc_array(NULL
, struct uniform_sort
,
2440 shader_program
->Uniforms
->NumUniforms
);
2442 for (i
= 0; i
< shader_program
->Uniforms
->NumUniforms
; i
++) {
2443 struct gl_uniform
*uniform
= shader_program
->Uniforms
->Uniforms
+ i
;
2444 int parameter_index
= -1;
2446 switch (shader
->Type
) {
2447 case GL_VERTEX_SHADER
:
2448 parameter_index
= uniform
->VertPos
;
2450 case GL_FRAGMENT_SHADER
:
2451 parameter_index
= uniform
->FragPos
;
2453 case GL_GEOMETRY_SHADER
:
2454 parameter_index
= uniform
->GeomPos
;
2458 /* Only add uniforms used in our target. */
2459 if (parameter_index
!= -1) {
2460 sorted_uniforms
[num_uniforms
].pos
= parameter_index
;
2461 sorted_uniforms
[num_uniforms
].u
= uniform
;
2466 qsort(sorted_uniforms
, num_uniforms
, sizeof(struct uniform_sort
),
2469 for (i
= 0; i
< num_uniforms
; i
++) {
2470 struct gl_uniform
*uniform
= sorted_uniforms
[i
].u
;
2471 int parameter_index
= sorted_uniforms
[i
].pos
;
2472 const glsl_type
*type
= uniform
->Type
;
2475 if (type
->is_vector() ||
2476 type
->is_scalar()) {
2477 size
= type
->vector_elements
;
2479 size
= type_size(type
) * 4;
2482 gl_register_file file
;
2483 if (type
->is_sampler() ||
2484 (type
->is_array() && type
->fields
.array
->is_sampler())) {
2485 file
= PROGRAM_SAMPLER
;
2487 file
= PROGRAM_UNIFORM
;
2490 GLint index
= _mesa_lookup_parameter_index(prog
->Parameters
, -1,
2494 index
= _mesa_add_parameter(prog
->Parameters
, file
,
2495 uniform
->Name
, size
, type
->gl_type
,
2498 /* Sampler uniform values are stored in prog->SamplerUnits,
2499 * and the entry in that array is selected by this index we
2500 * store in ParameterValues[].
2502 if (file
== PROGRAM_SAMPLER
) {
2503 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2504 prog
->Parameters
->ParameterValues
[index
+ j
][0] = next_sampler
++;
2507 /* The location chosen in the Parameters list here (returned
2508 * from _mesa_add_uniform) has to match what the linker chose.
2510 if (index
!= parameter_index
) {
2511 fail_link(shader_program
, "Allocation of uniform `%s' to target "
2512 "failed (%d vs %d)\n",
2513 uniform
->Name
, index
, parameter_index
);
2518 talloc_free(sorted_uniforms
);
2522 set_uniform_initializer(struct gl_context
*ctx
, void *mem_ctx
,
2523 struct gl_shader_program
*shader_program
,
2524 const char *name
, const glsl_type
*type
,
2527 if (type
->is_record()) {
2528 ir_constant
*field_constant
;
2530 field_constant
= (ir_constant
*)val
->components
.get_head();
2532 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2533 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
2534 const char *field_name
= talloc_asprintf(mem_ctx
, "%s.%s", name
,
2535 type
->fields
.structure
[i
].name
);
2536 set_uniform_initializer(ctx
, mem_ctx
, shader_program
, field_name
,
2537 field_type
, field_constant
);
2538 field_constant
= (ir_constant
*)field_constant
->next
;
2543 int loc
= _mesa_get_uniform_location(ctx
, shader_program
, name
);
2546 fail_link(shader_program
,
2547 "Couldn't find uniform for initializer %s\n", name
);
2551 for (unsigned int i
= 0; i
< (type
->is_array() ? type
->length
: 1); i
++) {
2552 ir_constant
*element
;
2553 const glsl_type
*element_type
;
2554 if (type
->is_array()) {
2555 element
= val
->array_elements
[i
];
2556 element_type
= type
->fields
.array
;
2559 element_type
= type
;
2564 if (element_type
->base_type
== GLSL_TYPE_BOOL
) {
2565 int *conv
= talloc_array(mem_ctx
, int, element_type
->components());
2566 for (unsigned int j
= 0; j
< element_type
->components(); j
++) {
2567 conv
[j
] = element
->value
.b
[j
];
2569 values
= (void *)conv
;
2570 element_type
= glsl_type::get_instance(GLSL_TYPE_INT
,
2571 element_type
->vector_elements
,
2574 values
= &element
->value
;
2577 if (element_type
->is_matrix()) {
2578 _mesa_uniform_matrix(ctx
, shader_program
,
2579 element_type
->matrix_columns
,
2580 element_type
->vector_elements
,
2581 loc
, 1, GL_FALSE
, (GLfloat
*)values
);
2582 loc
+= element_type
->matrix_columns
;
2584 _mesa_uniform(ctx
, shader_program
, loc
, element_type
->matrix_columns
,
2585 values
, element_type
->gl_type
);
2586 loc
+= type_size(element_type
);
2592 set_uniform_initializers(struct gl_context
*ctx
,
2593 struct gl_shader_program
*shader_program
)
2595 void *mem_ctx
= NULL
;
2597 for (unsigned int i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
2598 struct gl_shader
*shader
= shader_program
->_LinkedShaders
[i
];
2603 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2604 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2605 ir_variable
*var
= ir
->as_variable();
2607 if (!var
|| var
->mode
!= ir_var_uniform
|| !var
->constant_value
)
2611 mem_ctx
= talloc_new(NULL
);
2613 set_uniform_initializer(ctx
, mem_ctx
, shader_program
, var
->name
,
2614 var
->type
, var
->constant_value
);
2618 talloc_free(mem_ctx
);
2622 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2623 * channels for copy propagation and updates following instructions to
2624 * use the original versions.
2626 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2627 * will occur. As an example, a TXP production before this pass:
2629 * 0: MOV TEMP[1], INPUT[4].xyyy;
2630 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2631 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2635 * 0: MOV TEMP[1], INPUT[4].xyyy;
2636 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2637 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2639 * which allows for dead code elimination on TEMP[1]'s writes.
2642 ir_to_mesa_visitor::copy_propagate(void)
2644 ir_to_mesa_instruction
**acp
= talloc_zero_array(mem_ctx
,
2645 ir_to_mesa_instruction
*,
2646 this->next_temp
* 4);
2648 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2649 ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2651 /* First, do any copy propagation possible into the src regs. */
2652 for (int r
= 0; r
< 3; r
++) {
2653 ir_to_mesa_instruction
*first
= NULL
;
2655 int acp_base
= inst
->src_reg
[r
].index
* 4;
2657 if (inst
->src_reg
[r
].file
!= PROGRAM_TEMPORARY
||
2658 inst
->src_reg
[r
].reladdr
)
2661 /* See if we can find entries in the ACP consisting of MOVs
2662 * from the same src register for all the swizzled channels
2663 * of this src register reference.
2665 for (int i
= 0; i
< 4; i
++) {
2666 int src_chan
= GET_SWZ(inst
->src_reg
[r
].swizzle
, i
);
2667 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2677 if (first
->src_reg
[0].file
!= copy_chan
->src_reg
[0].file
||
2678 first
->src_reg
[0].index
!= copy_chan
->src_reg
[0].index
) {
2686 /* We've now validated that we can copy-propagate to
2687 * replace this src register reference. Do it.
2689 inst
->src_reg
[r
].file
= first
->src_reg
[0].file
;
2690 inst
->src_reg
[r
].index
= first
->src_reg
[0].index
;
2693 for (int i
= 0; i
< 4; i
++) {
2694 int src_chan
= GET_SWZ(inst
->src_reg
[r
].swizzle
, i
);
2695 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2696 swizzle
|= (GET_SWZ(copy_inst
->src_reg
[0].swizzle
, src_chan
) <<
2699 inst
->src_reg
[r
].swizzle
= swizzle
;
2704 case OPCODE_BGNLOOP
:
2705 case OPCODE_ENDLOOP
:
2708 /* End of a basic block, clear the ACP entirely. */
2709 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2713 /* Continuing the block, clear any written channels from
2716 if (inst
->dst_reg
.file
== PROGRAM_TEMPORARY
) {
2717 if (inst
->dst_reg
.reladdr
) {
2718 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2720 for (int i
= 0; i
< 4; i
++) {
2721 if (inst
->dst_reg
.writemask
& (1 << i
)) {
2722 acp
[4 * inst
->dst_reg
.index
+ i
] = NULL
;
2730 /* If this is a copy, add it to the ACP. */
2731 if (inst
->op
== OPCODE_MOV
&&
2732 inst
->dst_reg
.file
== PROGRAM_TEMPORARY
&&
2733 !inst
->dst_reg
.reladdr
&&
2735 !inst
->src_reg
[0].reladdr
&&
2736 !inst
->src_reg
[0].negate
) {
2737 for (int i
= 0; i
< 4; i
++) {
2738 if (inst
->dst_reg
.writemask
& (1 << i
)) {
2739 acp
[4 * inst
->dst_reg
.index
+ i
] = inst
;
2750 * Convert a shader's GLSL IR into a Mesa gl_program.
2752 static struct gl_program
*
2753 get_mesa_program(struct gl_context
*ctx
,
2754 struct gl_shader_program
*shader_program
,
2755 struct gl_shader
*shader
)
2757 ir_to_mesa_visitor v
;
2758 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2759 ir_instruction
**mesa_instruction_annotation
;
2761 struct gl_program
*prog
;
2763 const char *target_string
;
2765 struct gl_shader_compiler_options
*options
=
2766 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(shader
->Type
)];
2768 switch (shader
->Type
) {
2769 case GL_VERTEX_SHADER
:
2770 target
= GL_VERTEX_PROGRAM_ARB
;
2771 target_string
= "vertex";
2773 case GL_FRAGMENT_SHADER
:
2774 target
= GL_FRAGMENT_PROGRAM_ARB
;
2775 target_string
= "fragment";
2777 case GL_GEOMETRY_SHADER
:
2778 target
= GL_GEOMETRY_PROGRAM_NV
;
2779 target_string
= "geometry";
2782 assert(!"should not be reached");
2786 validate_ir_tree(shader
->ir
);
2788 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2791 prog
->Parameters
= _mesa_new_parameter_list();
2792 prog
->Varying
= _mesa_new_parameter_list();
2793 prog
->Attributes
= _mesa_new_parameter_list();
2796 v
.shader_program
= shader_program
;
2797 v
.options
= options
;
2799 add_uniforms_to_parameters_list(shader_program
, shader
, prog
);
2801 /* Emit Mesa IR for main(). */
2802 visit_exec_list(shader
->ir
, &v
);
2803 v
.ir_to_mesa_emit_op0(NULL
, OPCODE_END
);
2805 /* Now emit bodies for any functions that were used. */
2807 progress
= GL_FALSE
;
2809 foreach_iter(exec_list_iterator
, iter
, v
.function_signatures
) {
2810 function_entry
*entry
= (function_entry
*)iter
.get();
2812 if (!entry
->bgn_inst
) {
2813 v
.current_function
= entry
;
2815 entry
->bgn_inst
= v
.ir_to_mesa_emit_op0(NULL
, OPCODE_BGNSUB
);
2816 entry
->bgn_inst
->function
= entry
;
2818 visit_exec_list(&entry
->sig
->body
, &v
);
2820 ir_to_mesa_instruction
*last
;
2821 last
= (ir_to_mesa_instruction
*)v
.instructions
.get_tail();
2822 if (last
->op
!= OPCODE_RET
)
2823 v
.ir_to_mesa_emit_op0(NULL
, OPCODE_RET
);
2825 ir_to_mesa_instruction
*end
;
2826 end
= v
.ir_to_mesa_emit_op0(NULL
, OPCODE_ENDSUB
);
2827 end
->function
= entry
;
2834 prog
->NumTemporaries
= v
.next_temp
;
2836 int num_instructions
= 0;
2837 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2842 (struct prog_instruction
*)calloc(num_instructions
,
2843 sizeof(*mesa_instructions
));
2844 mesa_instruction_annotation
= talloc_array(v
.mem_ctx
, ir_instruction
*,
2849 /* Convert ir_mesa_instructions into prog_instructions.
2851 mesa_inst
= mesa_instructions
;
2853 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2854 const ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2856 mesa_inst
->Opcode
= inst
->op
;
2857 mesa_inst
->CondUpdate
= inst
->cond_update
;
2859 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2860 mesa_inst
->DstReg
.File
= inst
->dst_reg
.file
;
2861 mesa_inst
->DstReg
.Index
= inst
->dst_reg
.index
;
2862 mesa_inst
->DstReg
.CondMask
= inst
->dst_reg
.cond_mask
;
2863 mesa_inst
->DstReg
.WriteMask
= inst
->dst_reg
.writemask
;
2864 mesa_inst
->DstReg
.RelAddr
= inst
->dst_reg
.reladdr
!= NULL
;
2865 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src_reg
[0]);
2866 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src_reg
[1]);
2867 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src_reg
[2]);
2868 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2869 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2870 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2871 mesa_instruction_annotation
[i
] = inst
->ir
;
2873 /* Set IndirectRegisterFiles. */
2874 if (mesa_inst
->DstReg
.RelAddr
)
2875 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2877 /* Update program's bitmask of indirectly accessed register files */
2878 for (unsigned src
= 0; src
< 3; src
++)
2879 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2880 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2882 if (options
->EmitNoIfs
&& mesa_inst
->Opcode
== OPCODE_IF
) {
2883 fail_link(shader_program
, "Couldn't flatten if statement\n");
2886 switch (mesa_inst
->Opcode
) {
2888 inst
->function
->inst
= i
;
2889 mesa_inst
->Comment
= strdup(inst
->function
->sig
->function_name());
2892 mesa_inst
->Comment
= strdup(inst
->function
->sig
->function_name());
2895 mesa_inst
->BranchTarget
= inst
->function
->sig_id
; /* rewritten later */
2898 prog
->NumAddressRegs
= 1;
2907 if (!shader_program
->LinkStatus
)
2911 if (!shader_program
->LinkStatus
) {
2912 free(mesa_instructions
);
2913 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2917 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2919 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
2921 printf("GLSL IR for linked %s program %d:\n", target_string
,
2922 shader_program
->Name
);
2923 _mesa_print_ir(shader
->ir
, NULL
);
2926 printf("Mesa IR for linked %s program %d:\n", target_string
,
2927 shader_program
->Name
);
2928 print_program(mesa_instructions
, mesa_instruction_annotation
,
2932 prog
->Instructions
= mesa_instructions
;
2933 prog
->NumInstructions
= num_instructions
;
2935 do_set_program_inouts(shader
->ir
, prog
);
2936 count_resources(prog
);
2938 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2940 if ((ctx
->Shader
.Flags
& GLSL_NO_OPT
) == 0) {
2941 _mesa_optimize_program(ctx
, prog
);
2950 * Called via ctx->Driver.CompilerShader().
2952 * XXX can we remove the ctx->Driver.CompileShader() hook?
2955 _mesa_ir_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
2957 assert(shader
->CompileStatus
);
2966 * Called via ctx->Driver.LinkShader()
2967 * This actually involves converting GLSL IR into Mesa gl_programs with
2968 * code lowering and other optimizations.
2971 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2973 assert(prog
->LinkStatus
);
2975 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
2976 if (prog
->_LinkedShaders
[i
] == NULL
)
2980 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2981 const struct gl_shader_compiler_options
*options
=
2982 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(prog
->_LinkedShaders
[i
]->Type
)];
2988 do_mat_op_to_vec(ir
);
2989 lower_instructions(ir
, (MOD_TO_FRACT
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2991 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2993 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2995 progress
= do_common_optimization(ir
, true, options
->MaxUnrollIterations
) || progress
;
2997 progress
= lower_quadop_vector(ir
, true) || progress
;
2999 if (options
->EmitNoIfs
) {
3000 progress
= lower_discard(ir
) || progress
;
3001 progress
= lower_if_to_cond_assign(ir
) || progress
;
3004 if (options
->EmitNoNoise
)
3005 progress
= lower_noise(ir
) || progress
;
3007 /* If there are forms of indirect addressing that the driver
3008 * cannot handle, perform the lowering pass.
3010 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
3011 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
3013 lower_variable_index_to_cond_assign(ir
,
3014 options
->EmitNoIndirectInput
,
3015 options
->EmitNoIndirectOutput
,
3016 options
->EmitNoIndirectTemp
,
3017 options
->EmitNoIndirectUniform
)
3020 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
3023 validate_ir_tree(ir
);
3026 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
3027 struct gl_program
*linked_prog
;
3029 if (prog
->_LinkedShaders
[i
] == NULL
)
3032 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
3037 switch (prog
->_LinkedShaders
[i
]->Type
) {
3038 case GL_VERTEX_SHADER
:
3039 _mesa_reference_vertprog(ctx
, &prog
->VertexProgram
,
3040 (struct gl_vertex_program
*)linked_prog
);
3041 ok
= ctx
->Driver
.ProgramStringNotify(ctx
, GL_VERTEX_PROGRAM_ARB
,
3044 case GL_FRAGMENT_SHADER
:
3045 _mesa_reference_fragprog(ctx
, &prog
->FragmentProgram
,
3046 (struct gl_fragment_program
*)linked_prog
);
3047 ok
= ctx
->Driver
.ProgramStringNotify(ctx
, GL_FRAGMENT_PROGRAM_ARB
,
3050 case GL_GEOMETRY_SHADER
:
3051 _mesa_reference_geomprog(ctx
, &prog
->GeometryProgram
,
3052 (struct gl_geometry_program
*)linked_prog
);
3053 ok
= ctx
->Driver
.ProgramStringNotify(ctx
, GL_GEOMETRY_PROGRAM_NV
,
3062 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3070 * Compile a GLSL shader. Called via glCompileShader().
3073 _mesa_glsl_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
3075 struct _mesa_glsl_parse_state
*state
=
3076 new(shader
) _mesa_glsl_parse_state(ctx
, shader
->Type
, shader
);
3078 const char *source
= shader
->Source
;
3079 /* Check if the user called glCompileShader without first calling
3080 * glShaderSource. This should fail to compile, but not raise a GL_ERROR.
3082 if (source
== NULL
) {
3083 shader
->CompileStatus
= GL_FALSE
;
3087 state
->error
= preprocess(state
, &source
, &state
->info_log
,
3088 &ctx
->Extensions
, ctx
->API
);
3090 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
3091 printf("GLSL source for shader %d:\n", shader
->Name
);
3092 printf("%s\n", shader
->Source
);
3095 if (!state
->error
) {
3096 _mesa_glsl_lexer_ctor(state
, source
);
3097 _mesa_glsl_parse(state
);
3098 _mesa_glsl_lexer_dtor(state
);
3101 talloc_free(shader
->ir
);
3102 shader
->ir
= new(shader
) exec_list
;
3103 if (!state
->error
&& !state
->translation_unit
.is_empty())
3104 _mesa_ast_to_hir(shader
->ir
, state
);
3106 if (!state
->error
&& !shader
->ir
->is_empty()) {
3107 validate_ir_tree(shader
->ir
);
3109 /* Do some optimization at compile time to reduce shader IR size
3110 * and reduce later work if the same shader is linked multiple times
3112 while (do_common_optimization(shader
->ir
, false, 32))
3115 validate_ir_tree(shader
->ir
);
3118 shader
->symbols
= state
->symbols
;
3120 shader
->CompileStatus
= !state
->error
;
3121 shader
->InfoLog
= state
->info_log
;
3122 shader
->Version
= state
->language_version
;
3123 memcpy(shader
->builtins_to_link
, state
->builtins_to_link
,
3124 sizeof(shader
->builtins_to_link
[0]) * state
->num_builtins_to_link
);
3125 shader
->num_builtins_to_link
= state
->num_builtins_to_link
;
3127 if (ctx
->Shader
.Flags
& GLSL_LOG
) {
3128 _mesa_write_shader_to_file(shader
);
3131 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
3132 if (shader
->CompileStatus
) {
3133 printf("GLSL IR for shader %d:\n", shader
->Name
);
3134 _mesa_print_ir(shader
->ir
, NULL
);
3137 printf("GLSL shader %d failed to compile.\n", shader
->Name
);
3139 if (shader
->InfoLog
&& shader
->InfoLog
[0] != 0) {
3140 printf("GLSL shader %d info log:\n", shader
->Name
);
3141 printf("%s\n", shader
->InfoLog
);
3145 /* Retain any live IR, but trash the rest. */
3146 reparent_ir(shader
->ir
, shader
->ir
);
3150 if (shader
->CompileStatus
) {
3151 if (!ctx
->Driver
.CompileShader(ctx
, shader
))
3152 shader
->CompileStatus
= GL_FALSE
;
3158 * Link a GLSL shader program. Called via glLinkProgram().
3161 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3165 _mesa_clear_shader_program_data(ctx
, prog
);
3167 prog
->LinkStatus
= GL_TRUE
;
3169 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3170 if (!prog
->Shaders
[i
]->CompileStatus
) {
3171 fail_link(prog
, "linking with uncompiled shader");
3172 prog
->LinkStatus
= GL_FALSE
;
3176 prog
->Varying
= _mesa_new_parameter_list();
3177 _mesa_reference_vertprog(ctx
, &prog
->VertexProgram
, NULL
);
3178 _mesa_reference_fragprog(ctx
, &prog
->FragmentProgram
, NULL
);
3179 _mesa_reference_geomprog(ctx
, &prog
->GeometryProgram
, NULL
);
3181 if (prog
->LinkStatus
) {
3182 link_shaders(ctx
, prog
);
3185 if (prog
->LinkStatus
) {
3186 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3187 prog
->LinkStatus
= GL_FALSE
;
3191 set_uniform_initializers(ctx
, prog
);
3193 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
3194 if (!prog
->LinkStatus
) {
3195 printf("GLSL shader program %d failed to link\n", prog
->Name
);
3198 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3199 printf("GLSL shader program %d info log:\n", prog
->Name
);
3200 printf("%s\n", prog
->InfoLog
);