2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderobj.h"
47 #include "main/uniforms.h"
48 #include "program/hash_table.h"
51 #include "main/shaderapi.h"
52 #include "program/prog_instruction.h"
53 #include "program/prog_optimize.h"
54 #include "program/prog_print.h"
55 #include "program/program.h"
56 #include "program/prog_parameter.h"
57 #include "program/sampler.h"
60 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to Mesa prog_src_register, with
73 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
87 this->file
= PROGRAM_UNDEFINED
;
94 explicit src_reg(dst_reg reg
);
96 gl_register_file file
; /**< PROGRAM_* from Mesa */
97 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
98 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
99 int negate
; /**< NEGATE_XYZW mask from mesa */
100 /** Register index should be offset by the integer in this reg. */
106 dst_reg(gl_register_file file
, int writemask
)
110 this->writemask
= writemask
;
111 this->cond_mask
= COND_TR
;
112 this->reladdr
= NULL
;
117 this->file
= PROGRAM_UNDEFINED
;
120 this->cond_mask
= COND_TR
;
121 this->reladdr
= NULL
;
124 explicit dst_reg(src_reg reg
);
126 gl_register_file file
; /**< PROGRAM_* from Mesa */
127 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
128 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
130 /** Register index should be offset by the integer in this reg. */
134 } /* anonymous namespace */
136 src_reg::src_reg(dst_reg reg
)
138 this->file
= reg
.file
;
139 this->index
= reg
.index
;
140 this->swizzle
= SWIZZLE_XYZW
;
142 this->reladdr
= reg
.reladdr
;
145 dst_reg::dst_reg(src_reg reg
)
147 this->file
= reg
.file
;
148 this->index
= reg
.index
;
149 this->writemask
= WRITEMASK_XYZW
;
150 this->cond_mask
= COND_TR
;
151 this->reladdr
= reg
.reladdr
;
156 class ir_to_mesa_instruction
: public exec_node
{
158 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
163 /** Pointer to the ir source this tree came from for debugging */
165 GLboolean cond_update
;
167 int sampler
; /**< sampler index */
168 int tex_target
; /**< One of TEXTURE_*_INDEX */
169 GLboolean tex_shadow
;
172 class variable_storage
: public exec_node
{
174 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
175 : file(file
), index(index
), var(var
)
180 gl_register_file file
;
182 ir_variable
*var
; /* variable that maps to this, if any */
185 class function_entry
: public exec_node
{
187 ir_function_signature
*sig
;
190 * identifier of this function signature used by the program.
192 * At the point that Mesa instructions for function calls are
193 * generated, we don't know the address of the first instruction of
194 * the function body. So we make the BranchTarget that is called a
195 * small integer and rewrite them during set_branchtargets().
200 * Pointer to first instruction of the function body.
202 * Set during function body emits after main() is processed.
204 ir_to_mesa_instruction
*bgn_inst
;
207 * Index of the first instruction of the function body in actual
210 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
214 /** Storage for the return value. */
218 class ir_to_mesa_visitor
: public ir_visitor
{
220 ir_to_mesa_visitor();
221 ~ir_to_mesa_visitor();
223 function_entry
*current_function
;
225 struct gl_context
*ctx
;
226 struct gl_program
*prog
;
227 struct gl_shader_program
*shader_program
;
228 struct gl_shader_compiler_options
*options
;
232 variable_storage
*find_variable_storage(const ir_variable
*var
);
234 src_reg
get_temp(const glsl_type
*type
);
235 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
237 src_reg
src_reg_for_float(float val
);
240 * \name Visit methods
242 * As typical for the visitor pattern, there must be one \c visit method for
243 * each concrete subclass of \c ir_instruction. Virtual base classes within
244 * the hierarchy should not have \c visit methods.
247 virtual void visit(ir_variable
*);
248 virtual void visit(ir_loop
*);
249 virtual void visit(ir_loop_jump
*);
250 virtual void visit(ir_function_signature
*);
251 virtual void visit(ir_function
*);
252 virtual void visit(ir_expression
*);
253 virtual void visit(ir_swizzle
*);
254 virtual void visit(ir_dereference_variable
*);
255 virtual void visit(ir_dereference_array
*);
256 virtual void visit(ir_dereference_record
*);
257 virtual void visit(ir_assignment
*);
258 virtual void visit(ir_constant
*);
259 virtual void visit(ir_call
*);
260 virtual void visit(ir_return
*);
261 virtual void visit(ir_discard
*);
262 virtual void visit(ir_texture
*);
263 virtual void visit(ir_if
*);
264 virtual void visit(ir_emit_vertex
*);
265 virtual void visit(ir_end_primitive
*);
270 /** List of variable_storage */
273 /** List of function_entry */
274 exec_list function_signatures
;
275 int next_signature_id
;
277 /** List of ir_to_mesa_instruction */
278 exec_list instructions
;
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
282 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
283 dst_reg dst
, src_reg src0
);
285 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
286 dst_reg dst
, src_reg src0
, src_reg src1
);
288 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
290 src_reg src0
, src_reg src1
, src_reg src2
);
293 * Emit the correct dot-product instruction for the type of arguments
295 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
301 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
302 dst_reg dst
, src_reg src0
);
304 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
305 dst_reg dst
, src_reg src0
, src_reg src1
);
307 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
308 dst_reg dst
, const src_reg
&src
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
315 void emit_swz(ir_expression
*ir
);
317 bool process_move_condition(ir_rvalue
*ir
);
319 void copy_propagate(void);
324 } /* anonymous namespace */
326 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
328 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
330 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
333 swizzle_for_size(int size
)
335 static const int size_swizzles
[4] = {
336 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
337 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
338 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
339 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
342 assert((size
>= 1) && (size
<= 4));
343 return size_swizzles
[size
- 1];
346 ir_to_mesa_instruction
*
347 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
349 src_reg src0
, src_reg src1
, src_reg src2
)
351 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
354 /* If we have to do relative addressing, we want to load the ARL
355 * reg directly for one of the regs, and preload the other reladdr
356 * sources into temps.
358 num_reladdr
+= dst
.reladdr
!= NULL
;
359 num_reladdr
+= src0
.reladdr
!= NULL
;
360 num_reladdr
+= src1
.reladdr
!= NULL
;
361 num_reladdr
+= src2
.reladdr
!= NULL
;
363 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
364 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
365 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
368 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
371 assert(num_reladdr
== 0);
380 this->instructions
.push_tail(inst
);
386 ir_to_mesa_instruction
*
387 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
388 dst_reg dst
, src_reg src0
, src_reg src1
)
390 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
393 ir_to_mesa_instruction
*
394 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
395 dst_reg dst
, src_reg src0
)
397 assert(dst
.writemask
!= 0);
398 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
401 ir_to_mesa_instruction
*
402 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
404 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
407 ir_to_mesa_instruction
*
408 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
409 dst_reg dst
, src_reg src0
, src_reg src1
,
412 static const gl_inst_opcode dot_opcodes
[] = {
413 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
416 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
420 * Emits Mesa scalar opcodes to produce unique answers across channels.
422 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
423 * channel determines the result across all channels. So to do a vec4
424 * of this operation, we want to emit a scalar per source channel used
425 * to produce dest channels.
428 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
430 src_reg orig_src0
, src_reg orig_src1
)
433 int done_mask
= ~dst
.writemask
;
435 /* Mesa RCP is a scalar operation splatting results to all channels,
436 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
439 for (i
= 0; i
< 4; i
++) {
440 GLuint this_mask
= (1 << i
);
441 ir_to_mesa_instruction
*inst
;
442 src_reg src0
= orig_src0
;
443 src_reg src1
= orig_src1
;
445 if (done_mask
& this_mask
)
448 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
449 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
450 for (j
= i
+ 1; j
< 4; j
++) {
451 /* If there is another enabled component in the destination that is
452 * derived from the same inputs, generate its value on this pass as
455 if (!(done_mask
& (1 << j
)) &&
456 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
457 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
458 this_mask
|= (1 << j
);
461 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
462 src0_swiz
, src0_swiz
);
463 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
464 src1_swiz
, src1_swiz
);
466 inst
= emit(ir
, op
, dst
, src0
, src1
);
467 inst
->dst
.writemask
= this_mask
;
468 done_mask
|= this_mask
;
473 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
474 dst_reg dst
, src_reg src0
)
476 src_reg undef
= undef_src
;
478 undef
.swizzle
= SWIZZLE_XXXX
;
480 emit_scalar(ir
, op
, dst
, src0
, undef
);
484 * Emit an OPCODE_SCS instruction
486 * The \c SCS opcode functions a bit differently than the other Mesa (or
487 * ARB_fragment_program) opcodes. Instead of splatting its result across all
488 * four components of the destination, it writes one value to the \c x
489 * component and another value to the \c y component.
491 * \param ir IR instruction being processed
492 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
494 * \param dst Destination register
495 * \param src Source register
498 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
502 /* Vertex programs cannot use the SCS opcode.
504 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
505 emit_scalar(ir
, op
, dst
, src
);
509 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
510 const unsigned scs_mask
= (1U << component
);
511 int done_mask
= ~dst
.writemask
;
514 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
516 /* If there are compnents in the destination that differ from the component
517 * that will be written by the SCS instrution, we'll need a temporary.
519 if (scs_mask
!= unsigned(dst
.writemask
)) {
520 tmp
= get_temp(glsl_type::vec4_type
);
523 for (unsigned i
= 0; i
< 4; i
++) {
524 unsigned this_mask
= (1U << i
);
527 if ((done_mask
& this_mask
) != 0)
530 /* The source swizzle specified which component of the source generates
531 * sine / cosine for the current component in the destination. The SCS
532 * instruction requires that this value be swizzle to the X component.
533 * Replace the current swizzle with a swizzle that puts the source in
536 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
538 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
539 src0_swiz
, src0_swiz
);
540 for (unsigned j
= i
+ 1; j
< 4; j
++) {
541 /* If there is another enabled component in the destination that is
542 * derived from the same inputs, generate its value on this pass as
545 if (!(done_mask
& (1 << j
)) &&
546 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
547 this_mask
|= (1 << j
);
551 if (this_mask
!= scs_mask
) {
552 ir_to_mesa_instruction
*inst
;
553 dst_reg tmp_dst
= dst_reg(tmp
);
555 /* Emit the SCS instruction.
557 inst
= emit(ir
, OPCODE_SCS
, tmp_dst
, src0
);
558 inst
->dst
.writemask
= scs_mask
;
560 /* Move the result of the SCS instruction to the desired location in
563 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
564 component
, component
);
565 inst
= emit(ir
, OPCODE_SCS
, dst
, tmp
);
566 inst
->dst
.writemask
= this_mask
;
568 /* Emit the SCS instruction to write directly to the destination.
570 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_SCS
, dst
, src0
);
571 inst
->dst
.writemask
= scs_mask
;
574 done_mask
|= this_mask
;
579 ir_to_mesa_visitor::src_reg_for_float(float val
)
581 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
583 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
584 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
590 type_size(const struct glsl_type
*type
)
595 switch (type
->base_type
) {
598 case GLSL_TYPE_FLOAT
:
600 if (type
->is_matrix()) {
601 return type
->matrix_columns
;
603 /* Regardless of size of vector, it gets a vec4. This is bad
604 * packing for things like floats, but otherwise arrays become a
605 * mess. Hopefully a later pass over the code can pack scalars
606 * down if appropriate.
610 case GLSL_TYPE_ARRAY
:
611 assert(type
->length
> 0);
612 return type_size(type
->fields
.array
) * type
->length
;
613 case GLSL_TYPE_STRUCT
:
615 for (i
= 0; i
< type
->length
; i
++) {
616 size
+= type_size(type
->fields
.structure
[i
].type
);
619 case GLSL_TYPE_SAMPLER
:
620 case GLSL_TYPE_IMAGE
:
621 /* Samplers take up one slot in UNIFORMS[], but they're baked in
625 case GLSL_TYPE_ATOMIC_UINT
:
627 case GLSL_TYPE_ERROR
:
628 case GLSL_TYPE_INTERFACE
:
629 assert(!"Invalid type in type_size");
637 * In the initial pass of codegen, we assign temporary numbers to
638 * intermediate results. (not SSA -- variable assignments will reuse
639 * storage). Actual register allocation for the Mesa VM occurs in a
640 * pass over the Mesa IR later.
643 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
647 src
.file
= PROGRAM_TEMPORARY
;
648 src
.index
= next_temp
;
650 next_temp
+= type_size(type
);
652 if (type
->is_array() || type
->is_record()) {
653 src
.swizzle
= SWIZZLE_NOOP
;
655 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
663 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
665 foreach_in_list(variable_storage
, entry
, &this->variables
) {
666 if (entry
->var
== var
)
674 ir_to_mesa_visitor::visit(ir_variable
*ir
)
676 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
677 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
679 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
680 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
683 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
685 const ir_state_slot
*const slots
= ir
->get_state_slots();
686 assert(slots
!= NULL
);
688 /* Check if this statevar's setup in the STATE file exactly
689 * matches how we'll want to reference it as a
690 * struct/array/whatever. If not, then we need to move it into
691 * temporary storage and hope that it'll get copy-propagated
694 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
695 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
700 variable_storage
*storage
;
702 if (i
== ir
->get_num_state_slots()) {
703 /* We'll set the index later. */
704 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
705 this->variables
.push_tail(storage
);
709 /* The variable_storage constructor allocates slots based on the size
710 * of the type. However, this had better match the number of state
711 * elements that we're going to copy into the new temporary.
713 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
715 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
717 this->variables
.push_tail(storage
);
718 this->next_temp
+= type_size(ir
->type
);
720 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
724 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
725 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
726 (gl_state_index
*)slots
[i
].tokens
);
728 if (storage
->file
== PROGRAM_STATE_VAR
) {
729 if (storage
->index
== -1) {
730 storage
->index
= index
;
732 assert(index
== storage
->index
+ (int)i
);
735 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
736 src
.swizzle
= slots
[i
].swizzle
;
737 emit(ir
, OPCODE_MOV
, dst
, src
);
738 /* even a float takes up a whole vec4 reg in a struct/array. */
743 if (storage
->file
== PROGRAM_TEMPORARY
&&
744 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
745 linker_error(this->shader_program
,
746 "failed to load builtin uniform `%s' "
747 "(%d/%d regs loaded)\n",
748 ir
->name
, dst
.index
- storage
->index
,
749 type_size(ir
->type
));
755 ir_to_mesa_visitor::visit(ir_loop
*ir
)
757 emit(NULL
, OPCODE_BGNLOOP
);
759 visit_exec_list(&ir
->body_instructions
, this);
761 emit(NULL
, OPCODE_ENDLOOP
);
765 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
768 case ir_loop_jump::jump_break
:
769 emit(NULL
, OPCODE_BRK
);
771 case ir_loop_jump::jump_continue
:
772 emit(NULL
, OPCODE_CONT
);
779 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
786 ir_to_mesa_visitor::visit(ir_function
*ir
)
788 /* Ignore function bodies other than main() -- we shouldn't see calls to
789 * them since they should all be inlined before we get to ir_to_mesa.
791 if (strcmp(ir
->name
, "main") == 0) {
792 const ir_function_signature
*sig
;
795 sig
= ir
->matching_signature(NULL
, &empty
, false);
799 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
806 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
808 int nonmul_operand
= 1 - mul_operand
;
811 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
812 if (!expr
|| expr
->operation
!= ir_binop_mul
)
815 expr
->operands
[0]->accept(this);
817 expr
->operands
[1]->accept(this);
819 ir
->operands
[nonmul_operand
]->accept(this);
822 this->result
= get_temp(ir
->type
);
823 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
829 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
831 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
832 * implemented using multiplication, and logical-or is implemented using
833 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
834 * As result, the logical expression (a & !b) can be rewritten as:
838 * - (a * 1) - (a * b)
842 * This final expression can be implemented as a single MAD(a, -b, a)
846 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
848 const int other_operand
= 1 - try_operand
;
851 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
852 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
855 ir
->operands
[other_operand
]->accept(this);
857 expr
->operands
[0]->accept(this);
860 b
.negate
= ~b
.negate
;
862 this->result
= get_temp(ir
->type
);
863 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
869 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
870 src_reg
*reg
, int *num_reladdr
)
875 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
877 if (*num_reladdr
!= 1) {
878 src_reg temp
= get_temp(glsl_type::vec4_type
);
880 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
888 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
890 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
891 * This means that each of the operands is either an immediate value of -1,
892 * 0, or 1, or is a component from one source register (possibly with
895 uint8_t components
[4] = { 0 };
896 bool negate
[4] = { false };
897 ir_variable
*var
= NULL
;
899 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
900 ir_rvalue
*op
= ir
->operands
[i
];
902 assert(op
->type
->is_scalar());
905 switch (op
->ir_type
) {
906 case ir_type_constant
: {
908 assert(op
->type
->is_scalar());
910 const ir_constant
*const c
= op
->as_constant();
912 components
[i
] = SWIZZLE_ONE
;
913 } else if (c
->is_zero()) {
914 components
[i
] = SWIZZLE_ZERO
;
915 } else if (c
->is_negative_one()) {
916 components
[i
] = SWIZZLE_ONE
;
919 assert(!"SWZ constant must be 0.0 or 1.0.");
926 case ir_type_dereference_variable
: {
927 ir_dereference_variable
*const deref
=
928 (ir_dereference_variable
*) op
;
930 assert((var
== NULL
) || (deref
->var
== var
));
931 components
[i
] = SWIZZLE_X
;
937 case ir_type_expression
: {
938 ir_expression
*const expr
= (ir_expression
*) op
;
940 assert(expr
->operation
== ir_unop_neg
);
943 op
= expr
->operands
[0];
947 case ir_type_swizzle
: {
948 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
950 components
[i
] = swiz
->mask
.x
;
956 assert(!"Should not get here.");
964 ir_dereference_variable
*const deref
=
965 new(mem_ctx
) ir_dereference_variable(var
);
967 this->result
.file
= PROGRAM_UNDEFINED
;
969 if (this->result
.file
== PROGRAM_UNDEFINED
) {
970 printf("Failed to get tree for expression operand:\n");
979 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
983 src
.negate
= ((unsigned(negate
[0]) << 0)
984 | (unsigned(negate
[1]) << 1)
985 | (unsigned(negate
[2]) << 2)
986 | (unsigned(negate
[3]) << 3));
988 /* Storage for our result. Ideally for an assignment we'd be using the
989 * actual storage for the result here, instead.
991 const src_reg result_src
= get_temp(ir
->type
);
992 dst_reg result_dst
= dst_reg(result_src
);
994 /* Limit writes to the channels that will be used by result_src later.
995 * This does limit this temp's use as a temporary for multi-instruction
998 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1000 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
1001 this->result
= result_src
;
1005 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1007 unsigned int operand
;
1008 src_reg op
[Elements(ir
->operands
)];
1012 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1014 if (ir
->operation
== ir_binop_add
) {
1015 if (try_emit_mad(ir
, 1))
1017 if (try_emit_mad(ir
, 0))
1021 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1023 if (ir
->operation
== ir_binop_logic_and
) {
1024 if (try_emit_mad_for_and_not(ir
, 1))
1026 if (try_emit_mad_for_and_not(ir
, 0))
1030 if (ir
->operation
== ir_quadop_vector
) {
1035 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1036 this->result
.file
= PROGRAM_UNDEFINED
;
1037 ir
->operands
[operand
]->accept(this);
1038 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1039 printf("Failed to get tree for expression operand:\n");
1040 ir
->operands
[operand
]->print();
1044 op
[operand
] = this->result
;
1046 /* Matrix expression operands should have been broken down to vector
1047 * operations already.
1049 assert(!ir
->operands
[operand
]->type
->is_matrix());
1052 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1053 if (ir
->operands
[1]) {
1054 vector_elements
= MAX2(vector_elements
,
1055 ir
->operands
[1]->type
->vector_elements
);
1058 this->result
.file
= PROGRAM_UNDEFINED
;
1060 /* Storage for our result. Ideally for an assignment we'd be using
1061 * the actual storage for the result here, instead.
1063 result_src
= get_temp(ir
->type
);
1064 /* convenience for the emit functions below. */
1065 result_dst
= dst_reg(result_src
);
1066 /* Limit writes to the channels that will be used by result_src later.
1067 * This does limit this temp's use as a temporary for multi-instruction
1070 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1072 switch (ir
->operation
) {
1073 case ir_unop_logic_not
:
1074 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1075 * older GPUs implement SEQ using multiple instructions (i915 uses two
1076 * SGE instructions and a MUL instruction). Since our logic values are
1077 * 0.0 and 1.0, 1-x also implements !x.
1079 op
[0].negate
= ~op
[0].negate
;
1080 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1083 op
[0].negate
= ~op
[0].negate
;
1087 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1090 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1093 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1097 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1101 assert(!"not reached: should be handled by ir_explog_to_explog2");
1104 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1107 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1110 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1112 case ir_unop_sin_reduced
:
1113 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1115 case ir_unop_cos_reduced
:
1116 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1120 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1123 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1126 case ir_unop_saturate
: {
1127 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_MOV
,
1129 inst
->saturate
= true;
1132 case ir_unop_noise
: {
1133 const enum prog_opcode opcode
=
1134 prog_opcode(OPCODE_NOISE1
1135 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1136 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1138 emit(ir
, opcode
, result_dst
, op
[0]);
1143 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1146 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1150 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1153 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1156 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1157 assert(ir
->type
->is_integer());
1158 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1162 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1164 case ir_binop_greater
:
1165 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1167 case ir_binop_lequal
:
1168 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1170 case ir_binop_gequal
:
1171 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1173 case ir_binop_equal
:
1174 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1176 case ir_binop_nequal
:
1177 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1179 case ir_binop_all_equal
:
1180 /* "==" operator producing a scalar boolean. */
1181 if (ir
->operands
[0]->type
->is_vector() ||
1182 ir
->operands
[1]->type
->is_vector()) {
1183 src_reg temp
= get_temp(glsl_type::vec4_type
);
1184 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1186 /* After the dot-product, the value will be an integer on the
1187 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1189 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1191 /* Negating the result of the dot-product gives values on the range
1192 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1193 * achieved using SGE.
1195 src_reg sge_src
= result_src
;
1196 sge_src
.negate
= ~sge_src
.negate
;
1197 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1199 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1202 case ir_binop_any_nequal
:
1203 /* "!=" operator producing a scalar boolean. */
1204 if (ir
->operands
[0]->type
->is_vector() ||
1205 ir
->operands
[1]->type
->is_vector()) {
1206 src_reg temp
= get_temp(glsl_type::vec4_type
);
1207 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1209 /* After the dot-product, the value will be an integer on the
1210 * range [0,4]. Zero stays zero, and positive values become 1.0.
1212 ir_to_mesa_instruction
*const dp
=
1213 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1214 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1215 /* The clamping to [0,1] can be done for free in the fragment
1216 * shader with a saturate.
1218 dp
->saturate
= true;
1220 /* Negating the result of the dot-product gives values on the range
1221 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1222 * achieved using SLT.
1224 src_reg slt_src
= result_src
;
1225 slt_src
.negate
= ~slt_src
.negate
;
1226 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1229 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1234 assert(ir
->operands
[0]->type
->is_vector());
1236 /* After the dot-product, the value will be an integer on the
1237 * range [0,4]. Zero stays zero, and positive values become 1.0.
1239 ir_to_mesa_instruction
*const dp
=
1240 emit_dp(ir
, result_dst
, op
[0], op
[0],
1241 ir
->operands
[0]->type
->vector_elements
);
1242 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1243 /* The clamping to [0,1] can be done for free in the fragment
1244 * shader with a saturate.
1246 dp
->saturate
= true;
1248 /* Negating the result of the dot-product gives values on the range
1249 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1250 * is achieved using SLT.
1252 src_reg slt_src
= result_src
;
1253 slt_src
.negate
= ~slt_src
.negate
;
1254 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1259 case ir_binop_logic_xor
:
1260 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1263 case ir_binop_logic_or
: {
1264 /* After the addition, the value will be an integer on the
1265 * range [0,2]. Zero stays zero, and positive values become 1.0.
1267 ir_to_mesa_instruction
*add
=
1268 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1269 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1270 /* The clamping to [0,1] can be done for free in the fragment
1271 * shader with a saturate.
1273 add
->saturate
= true;
1275 /* Negating the result of the addition gives values on the range
1276 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1277 * is achieved using SLT.
1279 src_reg slt_src
= result_src
;
1280 slt_src
.negate
= ~slt_src
.negate
;
1281 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1286 case ir_binop_logic_and
:
1287 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1288 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1292 assert(ir
->operands
[0]->type
->is_vector());
1293 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1294 emit_dp(ir
, result_dst
, op
[0], op
[1],
1295 ir
->operands
[0]->type
->vector_elements
);
1299 /* sqrt(x) = x * rsq(x). */
1300 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1301 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1302 /* For incoming channels <= 0, set the result to 0. */
1303 op
[0].negate
= ~op
[0].negate
;
1304 emit(ir
, OPCODE_CMP
, result_dst
,
1305 op
[0], result_src
, src_reg_for_float(0.0));
1308 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1316 /* Mesa IR lacks types, ints are stored as truncated floats. */
1321 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1325 emit(ir
, OPCODE_SNE
, result_dst
,
1326 op
[0], src_reg_for_float(0.0));
1328 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1329 case ir_unop_bitcast_f2u
:
1330 case ir_unop_bitcast_i2f
:
1331 case ir_unop_bitcast_u2f
:
1334 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1337 op
[0].negate
= ~op
[0].negate
;
1338 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1339 result_src
.negate
= ~result_src
.negate
;
1342 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1345 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1347 case ir_unop_pack_snorm_2x16
:
1348 case ir_unop_pack_snorm_4x8
:
1349 case ir_unop_pack_unorm_2x16
:
1350 case ir_unop_pack_unorm_4x8
:
1351 case ir_unop_pack_half_2x16
:
1352 case ir_unop_unpack_snorm_2x16
:
1353 case ir_unop_unpack_snorm_4x8
:
1354 case ir_unop_unpack_unorm_2x16
:
1355 case ir_unop_unpack_unorm_4x8
:
1356 case ir_unop_unpack_half_2x16
:
1357 case ir_unop_unpack_half_2x16_split_x
:
1358 case ir_unop_unpack_half_2x16_split_y
:
1359 case ir_binop_pack_half_2x16_split
:
1360 case ir_unop_bitfield_reverse
:
1361 case ir_unop_bit_count
:
1362 case ir_unop_find_msb
:
1363 case ir_unop_find_lsb
:
1364 assert(!"not supported");
1367 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1370 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1373 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1376 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1377 * hardware backends have no way to avoid Mesa IR generation
1378 * even if they don't use it, we need to emit "something" and
1381 case ir_binop_lshift
:
1382 case ir_binop_rshift
:
1383 case ir_binop_bit_and
:
1384 case ir_binop_bit_xor
:
1385 case ir_binop_bit_or
:
1386 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1389 case ir_unop_bit_not
:
1390 case ir_unop_round_even
:
1391 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1394 case ir_binop_ubo_load
:
1395 assert(!"not supported");
1399 /* ir_triop_lrp operands are (x, y, a) while
1400 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1402 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1405 case ir_binop_vector_extract
:
1409 case ir_triop_bitfield_extract
:
1410 case ir_triop_vector_insert
:
1411 case ir_quadop_bitfield_insert
:
1412 case ir_binop_ldexp
:
1414 case ir_binop_carry
:
1415 case ir_binop_borrow
:
1416 case ir_binop_imul_high
:
1417 case ir_unop_interpolate_at_centroid
:
1418 case ir_binop_interpolate_at_offset
:
1419 case ir_binop_interpolate_at_sample
:
1420 case ir_unop_dFdx_coarse
:
1421 case ir_unop_dFdx_fine
:
1422 case ir_unop_dFdy_coarse
:
1423 case ir_unop_dFdy_fine
:
1424 assert(!"not supported");
1427 case ir_quadop_vector
:
1428 /* This operation should have already been handled.
1430 assert(!"Should not get here.");
1434 this->result
= result_src
;
1439 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1445 /* Note that this is only swizzles in expressions, not those on the left
1446 * hand side of an assignment, which do write masking. See ir_assignment
1450 ir
->val
->accept(this);
1452 assert(src
.file
!= PROGRAM_UNDEFINED
);
1454 for (i
= 0; i
< 4; i
++) {
1455 if (i
< ir
->type
->vector_elements
) {
1458 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1461 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1464 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1467 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1471 /* If the type is smaller than a vec4, replicate the last
1474 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1478 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1484 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1486 variable_storage
*entry
= find_variable_storage(ir
->var
);
1487 ir_variable
*var
= ir
->var
;
1490 switch (var
->data
.mode
) {
1491 case ir_var_uniform
:
1492 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1493 var
->data
.location
);
1494 this->variables
.push_tail(entry
);
1496 case ir_var_shader_in
:
1497 /* The linker assigns locations for varyings and attributes,
1498 * including deprecated builtins (like gl_Color),
1499 * user-assigned generic attributes (glBindVertexLocation),
1500 * and user-defined varyings.
1502 assert(var
->data
.location
!= -1);
1503 entry
= new(mem_ctx
) variable_storage(var
,
1505 var
->data
.location
);
1507 case ir_var_shader_out
:
1508 assert(var
->data
.location
!= -1);
1509 entry
= new(mem_ctx
) variable_storage(var
,
1511 var
->data
.location
);
1513 case ir_var_system_value
:
1514 entry
= new(mem_ctx
) variable_storage(var
,
1515 PROGRAM_SYSTEM_VALUE
,
1516 var
->data
.location
);
1519 case ir_var_temporary
:
1520 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1522 this->variables
.push_tail(entry
);
1524 next_temp
+= type_size(var
->type
);
1529 printf("Failed to make storage for %s\n", var
->name
);
1534 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1538 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1542 int element_size
= type_size(ir
->type
);
1544 index
= ir
->array_index
->constant_expression_value();
1546 ir
->array
->accept(this);
1550 src
.index
+= index
->value
.i
[0] * element_size
;
1552 /* Variable index array dereference. It eats the "vec4" of the
1553 * base of the array and an index that offsets the Mesa register
1556 ir
->array_index
->accept(this);
1560 if (element_size
== 1) {
1561 index_reg
= this->result
;
1563 index_reg
= get_temp(glsl_type::float_type
);
1565 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1566 this->result
, src_reg_for_float(element_size
));
1569 /* If there was already a relative address register involved, add the
1570 * new and the old together to get the new offset.
1572 if (src
.reladdr
!= NULL
) {
1573 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1575 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1576 index_reg
, *src
.reladdr
);
1578 index_reg
= accum_reg
;
1581 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1582 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1585 /* If the type is smaller than a vec4, replicate the last channel out. */
1586 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1587 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1589 src
.swizzle
= SWIZZLE_NOOP
;
1595 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1598 const glsl_type
*struct_type
= ir
->record
->type
;
1601 ir
->record
->accept(this);
1603 for (i
= 0; i
< struct_type
->length
; i
++) {
1604 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1606 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1609 /* If the type is smaller than a vec4, replicate the last channel out. */
1610 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1611 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1613 this->result
.swizzle
= SWIZZLE_NOOP
;
1615 this->result
.index
+= offset
;
1619 * We want to be careful in assignment setup to hit the actual storage
1620 * instead of potentially using a temporary like we might with the
1621 * ir_dereference handler.
1624 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1626 /* The LHS must be a dereference. If the LHS is a variable indexed array
1627 * access of a vector, it must be separated into a series conditional moves
1628 * before reaching this point (see ir_vec_index_to_cond_assign).
1630 assert(ir
->as_dereference());
1631 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1633 assert(!deref_array
->array
->type
->is_vector());
1636 /* Use the rvalue deref handler for the most part. We'll ignore
1637 * swizzles in it and write swizzles using writemask, though.
1640 return dst_reg(v
->result
);
1644 * Process the condition of a conditional assignment
1646 * Examines the condition of a conditional assignment to generate the optimal
1647 * first operand of a \c CMP instruction. If the condition is a relational
1648 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1649 * used as the source for the \c CMP instruction. Otherwise the comparison
1650 * is processed to a boolean result, and the boolean result is used as the
1651 * operand to the CMP instruction.
1654 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1656 ir_rvalue
*src_ir
= ir
;
1658 bool switch_order
= false;
1660 ir_expression
*const expr
= ir
->as_expression();
1661 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1662 bool zero_on_left
= false;
1664 if (expr
->operands
[0]->is_zero()) {
1665 src_ir
= expr
->operands
[1];
1666 zero_on_left
= true;
1667 } else if (expr
->operands
[1]->is_zero()) {
1668 src_ir
= expr
->operands
[0];
1669 zero_on_left
= false;
1673 * (a < 0) T F F ( a < 0) T F F
1674 * (0 < a) F F T (-a < 0) F F T
1675 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1676 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1677 * (a > 0) F F T (-a < 0) F F T
1678 * (0 > a) T F F ( a < 0) T F F
1679 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1680 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1682 * Note that exchanging the order of 0 and 'a' in the comparison simply
1683 * means that the value of 'a' should be negated.
1686 switch (expr
->operation
) {
1688 switch_order
= false;
1689 negate
= zero_on_left
;
1692 case ir_binop_greater
:
1693 switch_order
= false;
1694 negate
= !zero_on_left
;
1697 case ir_binop_lequal
:
1698 switch_order
= true;
1699 negate
= !zero_on_left
;
1702 case ir_binop_gequal
:
1703 switch_order
= true;
1704 negate
= zero_on_left
;
1708 /* This isn't the right kind of comparison afterall, so make sure
1709 * the whole condition is visited.
1717 src_ir
->accept(this);
1719 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1720 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1721 * choose which value OPCODE_CMP produces without an extra instruction
1722 * computing the condition.
1725 this->result
.negate
= ~this->result
.negate
;
1727 return switch_order
;
1731 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1737 ir
->rhs
->accept(this);
1740 l
= get_assignment_lhs(ir
->lhs
, this);
1742 /* FINISHME: This should really set to the correct maximal writemask for each
1743 * FINISHME: component written (in the loops below). This case can only
1744 * FINISHME: occur for matrices, arrays, and structures.
1746 if (ir
->write_mask
== 0) {
1747 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1748 l
.writemask
= WRITEMASK_XYZW
;
1749 } else if (ir
->lhs
->type
->is_scalar()) {
1750 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1751 * FINISHME: W component of fragment shader output zero, work correctly.
1753 l
.writemask
= WRITEMASK_XYZW
;
1756 int first_enabled_chan
= 0;
1759 assert(ir
->lhs
->type
->is_vector());
1760 l
.writemask
= ir
->write_mask
;
1762 for (int i
= 0; i
< 4; i
++) {
1763 if (l
.writemask
& (1 << i
)) {
1764 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1769 /* Swizzle a small RHS vector into the channels being written.
1771 * glsl ir treats write_mask as dictating how many channels are
1772 * present on the RHS while Mesa IR treats write_mask as just
1773 * showing which channels of the vec4 RHS get written.
1775 for (int i
= 0; i
< 4; i
++) {
1776 if (l
.writemask
& (1 << i
))
1777 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1779 swizzles
[i
] = first_enabled_chan
;
1781 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1782 swizzles
[2], swizzles
[3]);
1785 assert(l
.file
!= PROGRAM_UNDEFINED
);
1786 assert(r
.file
!= PROGRAM_UNDEFINED
);
1788 if (ir
->condition
) {
1789 const bool switch_order
= this->process_move_condition(ir
->condition
);
1790 src_reg condition
= this->result
;
1792 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1794 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1796 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1803 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1804 emit(ir
, OPCODE_MOV
, l
, r
);
1813 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1816 GLfloat stack_vals
[4] = { 0 };
1817 GLfloat
*values
= stack_vals
;
1820 /* Unfortunately, 4 floats is all we can get into
1821 * _mesa_add_unnamed_constant. So, make a temp to store an
1822 * aggregate constant and move each constant value into it. If we
1823 * get lucky, copy propagation will eliminate the extra moves.
1826 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1827 src_reg temp_base
= get_temp(ir
->type
);
1828 dst_reg temp
= dst_reg(temp_base
);
1830 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1831 int size
= type_size(field_value
->type
);
1835 field_value
->accept(this);
1838 for (i
= 0; i
< (unsigned int)size
; i
++) {
1839 emit(ir
, OPCODE_MOV
, temp
, src
);
1845 this->result
= temp_base
;
1849 if (ir
->type
->is_array()) {
1850 src_reg temp_base
= get_temp(ir
->type
);
1851 dst_reg temp
= dst_reg(temp_base
);
1852 int size
= type_size(ir
->type
->fields
.array
);
1856 for (i
= 0; i
< ir
->type
->length
; i
++) {
1857 ir
->array_elements
[i
]->accept(this);
1859 for (int j
= 0; j
< size
; j
++) {
1860 emit(ir
, OPCODE_MOV
, temp
, src
);
1866 this->result
= temp_base
;
1870 if (ir
->type
->is_matrix()) {
1871 src_reg mat
= get_temp(ir
->type
);
1872 dst_reg mat_column
= dst_reg(mat
);
1874 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1875 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1876 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1878 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1879 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1880 (gl_constant_value
*) values
,
1881 ir
->type
->vector_elements
,
1883 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1892 src
.file
= PROGRAM_CONSTANT
;
1893 switch (ir
->type
->base_type
) {
1894 case GLSL_TYPE_FLOAT
:
1895 values
= &ir
->value
.f
[0];
1897 case GLSL_TYPE_UINT
:
1898 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1899 values
[i
] = ir
->value
.u
[i
];
1903 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1904 values
[i
] = ir
->value
.i
[i
];
1907 case GLSL_TYPE_BOOL
:
1908 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1909 values
[i
] = ir
->value
.b
[i
];
1913 assert(!"Non-float/uint/int/bool constant");
1916 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1917 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1918 (gl_constant_value
*) values
,
1919 ir
->type
->vector_elements
,
1920 &this->result
.swizzle
);
1924 ir_to_mesa_visitor::visit(ir_call
*)
1926 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1930 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1932 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1933 dst_reg result_dst
, coord_dst
;
1934 ir_to_mesa_instruction
*inst
= NULL
;
1935 prog_opcode opcode
= OPCODE_NOP
;
1937 if (ir
->op
== ir_txs
)
1938 this->result
= src_reg_for_float(0.0);
1940 ir
->coordinate
->accept(this);
1942 /* Put our coords in a temp. We'll need to modify them for shadow,
1943 * projection, or LOD, so the only case we'd use it as is is if
1944 * we're doing plain old texturing. Mesa IR optimization should
1945 * handle cleaning up our mess in that case.
1947 coord
= get_temp(glsl_type::vec4_type
);
1948 coord_dst
= dst_reg(coord
);
1949 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1951 if (ir
->projector
) {
1952 ir
->projector
->accept(this);
1953 projector
= this->result
;
1956 /* Storage for our result. Ideally for an assignment we'd be using
1957 * the actual storage for the result here, instead.
1959 result_src
= get_temp(glsl_type::vec4_type
);
1960 result_dst
= dst_reg(result_src
);
1965 opcode
= OPCODE_TEX
;
1968 opcode
= OPCODE_TXB
;
1969 ir
->lod_info
.bias
->accept(this);
1970 lod_info
= this->result
;
1973 /* Pretend to be TXL so the sampler, coordinate, lod are available */
1975 opcode
= OPCODE_TXL
;
1976 ir
->lod_info
.lod
->accept(this);
1977 lod_info
= this->result
;
1980 opcode
= OPCODE_TXD
;
1981 ir
->lod_info
.grad
.dPdx
->accept(this);
1983 ir
->lod_info
.grad
.dPdy
->accept(this);
1987 assert(!"Unexpected ir_txf_ms opcode");
1990 assert(!"Unexpected ir_lod opcode");
1993 assert(!"Unexpected ir_tg4 opcode");
1995 case ir_query_levels
:
1996 assert(!"Unexpected ir_query_levels opcode");
2000 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2002 if (ir
->projector
) {
2003 if (opcode
== OPCODE_TEX
) {
2004 /* Slot the projector in as the last component of the coord. */
2005 coord_dst
.writemask
= WRITEMASK_W
;
2006 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
2007 coord_dst
.writemask
= WRITEMASK_XYZW
;
2008 opcode
= OPCODE_TXP
;
2010 src_reg coord_w
= coord
;
2011 coord_w
.swizzle
= SWIZZLE_WWWW
;
2013 /* For the other TEX opcodes there's no projective version
2014 * since the last slot is taken up by lod info. Do the
2015 * projective divide now.
2017 coord_dst
.writemask
= WRITEMASK_W
;
2018 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
2020 /* In the case where we have to project the coordinates "by hand,"
2021 * the shadow comparitor value must also be projected.
2023 src_reg tmp_src
= coord
;
2024 if (ir
->shadow_comparitor
) {
2025 /* Slot the shadow value in as the second to last component of the
2028 ir
->shadow_comparitor
->accept(this);
2030 tmp_src
= get_temp(glsl_type::vec4_type
);
2031 dst_reg tmp_dst
= dst_reg(tmp_src
);
2033 /* Projective division not allowed for array samplers. */
2034 assert(!sampler_type
->sampler_array
);
2036 tmp_dst
.writemask
= WRITEMASK_Z
;
2037 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
2039 tmp_dst
.writemask
= WRITEMASK_XY
;
2040 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
2043 coord_dst
.writemask
= WRITEMASK_XYZ
;
2044 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
2046 coord_dst
.writemask
= WRITEMASK_XYZW
;
2047 coord
.swizzle
= SWIZZLE_XYZW
;
2051 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2052 * comparitor was put in the correct place (and projected) by the code,
2053 * above, that handles by-hand projection.
2055 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
2056 /* Slot the shadow value in as the second to last component of the
2059 ir
->shadow_comparitor
->accept(this);
2061 /* XXX This will need to be updated for cubemap array samplers. */
2062 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
2063 sampler_type
->sampler_array
) {
2064 coord_dst
.writemask
= WRITEMASK_W
;
2066 coord_dst
.writemask
= WRITEMASK_Z
;
2069 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2070 coord_dst
.writemask
= WRITEMASK_XYZW
;
2073 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2074 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2075 coord_dst
.writemask
= WRITEMASK_W
;
2076 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2077 coord_dst
.writemask
= WRITEMASK_XYZW
;
2080 if (opcode
== OPCODE_TXD
)
2081 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2083 inst
= emit(ir
, opcode
, result_dst
, coord
);
2085 if (ir
->shadow_comparitor
)
2086 inst
->tex_shadow
= GL_TRUE
;
2088 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2089 this->shader_program
,
2092 switch (sampler_type
->sampler_dimensionality
) {
2093 case GLSL_SAMPLER_DIM_1D
:
2094 inst
->tex_target
= (sampler_type
->sampler_array
)
2095 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2097 case GLSL_SAMPLER_DIM_2D
:
2098 inst
->tex_target
= (sampler_type
->sampler_array
)
2099 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2101 case GLSL_SAMPLER_DIM_3D
:
2102 inst
->tex_target
= TEXTURE_3D_INDEX
;
2104 case GLSL_SAMPLER_DIM_CUBE
:
2105 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2107 case GLSL_SAMPLER_DIM_RECT
:
2108 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2110 case GLSL_SAMPLER_DIM_BUF
:
2111 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2113 case GLSL_SAMPLER_DIM_EXTERNAL
:
2114 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2117 assert(!"Should not get here.");
2120 this->result
= result_src
;
2124 ir_to_mesa_visitor::visit(ir_return
*ir
)
2126 /* Non-void functions should have been inlined. We may still emit RETs
2127 * from main() unless the EmitNoMainReturn option is set.
2129 assert(!ir
->get_value());
2130 emit(ir
, OPCODE_RET
);
2134 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2136 if (ir
->condition
) {
2137 ir
->condition
->accept(this);
2138 this->result
.negate
= ~this->result
.negate
;
2139 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2141 emit(ir
, OPCODE_KIL_NV
);
2146 ir_to_mesa_visitor::visit(ir_if
*ir
)
2148 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2149 ir_to_mesa_instruction
*prev_inst
;
2151 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2153 ir
->condition
->accept(this);
2154 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2156 if (this->options
->EmitCondCodes
) {
2157 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2159 /* See if we actually generated any instruction for generating
2160 * the condition. If not, then cook up a move to a temp so we
2161 * have something to set cond_update on.
2163 if (cond_inst
== prev_inst
) {
2164 src_reg temp
= get_temp(glsl_type::bool_type
);
2165 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2167 cond_inst
->cond_update
= GL_TRUE
;
2169 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2170 if_inst
->dst
.cond_mask
= COND_NE
;
2172 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2175 this->instructions
.push_tail(if_inst
);
2177 visit_exec_list(&ir
->then_instructions
, this);
2179 if (!ir
->else_instructions
.is_empty()) {
2180 emit(ir
->condition
, OPCODE_ELSE
);
2181 visit_exec_list(&ir
->else_instructions
, this);
2184 emit(ir
->condition
, OPCODE_ENDIF
);
2188 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2190 assert(!"Geometry shaders not supported.");
2194 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2196 assert(!"Geometry shaders not supported.");
2199 ir_to_mesa_visitor::ir_to_mesa_visitor()
2201 result
.file
= PROGRAM_UNDEFINED
;
2203 next_signature_id
= 1;
2204 current_function
= NULL
;
2205 mem_ctx
= ralloc_context(NULL
);
2208 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2210 ralloc_free(mem_ctx
);
2213 static struct prog_src_register
2214 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2216 struct prog_src_register mesa_reg
;
2218 mesa_reg
.File
= reg
.file
;
2219 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2220 mesa_reg
.Index
= reg
.index
;
2221 mesa_reg
.Swizzle
= reg
.swizzle
;
2222 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2223 mesa_reg
.Negate
= reg
.negate
;
2225 mesa_reg
.HasIndex2
= GL_FALSE
;
2226 mesa_reg
.RelAddr2
= 0;
2227 mesa_reg
.Index2
= 0;
2233 set_branchtargets(ir_to_mesa_visitor
*v
,
2234 struct prog_instruction
*mesa_instructions
,
2235 int num_instructions
)
2237 int if_count
= 0, loop_count
= 0;
2238 int *if_stack
, *loop_stack
;
2239 int if_stack_pos
= 0, loop_stack_pos
= 0;
2242 for (i
= 0; i
< num_instructions
; i
++) {
2243 switch (mesa_instructions
[i
].Opcode
) {
2247 case OPCODE_BGNLOOP
:
2252 mesa_instructions
[i
].BranchTarget
= -1;
2259 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2260 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2262 for (i
= 0; i
< num_instructions
; i
++) {
2263 switch (mesa_instructions
[i
].Opcode
) {
2265 if_stack
[if_stack_pos
] = i
;
2269 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2270 if_stack
[if_stack_pos
- 1] = i
;
2273 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2276 case OPCODE_BGNLOOP
:
2277 loop_stack
[loop_stack_pos
] = i
;
2280 case OPCODE_ENDLOOP
:
2282 /* Rewrite any breaks/conts at this nesting level (haven't
2283 * already had a BranchTarget assigned) to point to the end
2286 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2287 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2288 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2289 if (mesa_instructions
[j
].BranchTarget
== -1) {
2290 mesa_instructions
[j
].BranchTarget
= i
;
2294 /* The loop ends point at each other. */
2295 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2296 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2299 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2300 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2301 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2313 print_program(struct prog_instruction
*mesa_instructions
,
2314 ir_instruction
**mesa_instruction_annotation
,
2315 int num_instructions
)
2317 ir_instruction
*last_ir
= NULL
;
2321 for (i
= 0; i
< num_instructions
; i
++) {
2322 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2323 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2325 fprintf(stdout
, "%3d: ", i
);
2327 if (last_ir
!= ir
&& ir
) {
2330 for (j
= 0; j
< indent
; j
++) {
2331 fprintf(stdout
, " ");
2337 fprintf(stdout
, " "); /* line number spacing. */
2340 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2341 PROG_PRINT_DEBUG
, NULL
);
2347 class add_uniform_to_shader
: public program_resource_visitor
{
2349 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2350 struct gl_program_parameter_list
*params
,
2351 gl_shader_stage shader_type
)
2352 : shader_program(shader_program
), params(params
), idx(-1),
2353 shader_type(shader_type
)
2358 void process(ir_variable
*var
)
2361 this->program_resource_visitor::process(var
);
2363 var
->data
.location
= this->idx
;
2367 virtual void visit_field(const glsl_type
*type
, const char *name
,
2370 struct gl_shader_program
*shader_program
;
2371 struct gl_program_parameter_list
*params
;
2373 gl_shader_stage shader_type
;
2376 } /* anonymous namespace */
2379 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2386 if (type
->is_vector() || type
->is_scalar()) {
2387 size
= type
->vector_elements
;
2389 size
= type_size(type
) * 4;
2392 gl_register_file file
;
2393 if (type
->without_array()->is_sampler()) {
2394 file
= PROGRAM_SAMPLER
;
2396 file
= PROGRAM_UNIFORM
;
2399 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2401 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2404 /* Sampler uniform values are stored in prog->SamplerUnits,
2405 * and the entry in that array is selected by this index we
2406 * store in ParameterValues[].
2408 if (file
== PROGRAM_SAMPLER
) {
2411 this->shader_program
->UniformHash
->get(location
,
2412 params
->Parameters
[index
].Name
);
2418 struct gl_uniform_storage
*storage
=
2419 &this->shader_program
->UniformStorage
[location
];
2421 assert(storage
->sampler
[shader_type
].active
);
2423 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2424 params
->ParameterValues
[index
+ j
][0].f
=
2425 storage
->sampler
[shader_type
].index
+ j
;
2429 /* The first part of the uniform that's processed determines the base
2430 * location of the whole uniform (for structures).
2437 * Generate the program parameters list for the user uniforms in a shader
2439 * \param shader_program Linked shader program. This is only used to
2440 * emit possible link errors to the info log.
2441 * \param sh Shader whose uniforms are to be processed.
2442 * \param params Parameter list to be filled in.
2445 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2447 struct gl_shader
*sh
,
2448 struct gl_program_parameter_list
2451 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2453 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2454 ir_variable
*var
= node
->as_variable();
2456 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2457 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2465 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2466 struct gl_shader_program
*shader_program
,
2467 struct gl_program_parameter_list
*params
)
2469 /* After adding each uniform to the parameter list, connect the storage for
2470 * the parameter with the tracking structure used by the API for the
2473 unsigned last_location
= unsigned(~0);
2474 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2475 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2480 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2486 if (location
!= last_location
) {
2487 struct gl_uniform_storage
*storage
=
2488 &shader_program
->UniformStorage
[location
];
2489 enum gl_uniform_driver_format format
= uniform_native
;
2491 unsigned columns
= 0;
2492 switch (storage
->type
->base_type
) {
2493 case GLSL_TYPE_UINT
:
2494 assert(ctx
->Const
.NativeIntegers
);
2495 format
= uniform_native
;
2500 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2503 case GLSL_TYPE_FLOAT
:
2504 format
= uniform_native
;
2505 columns
= storage
->type
->matrix_columns
;
2507 case GLSL_TYPE_BOOL
:
2508 format
= uniform_native
;
2511 case GLSL_TYPE_SAMPLER
:
2512 case GLSL_TYPE_IMAGE
:
2513 format
= uniform_native
;
2516 case GLSL_TYPE_ATOMIC_UINT
:
2517 case GLSL_TYPE_ARRAY
:
2518 case GLSL_TYPE_VOID
:
2519 case GLSL_TYPE_STRUCT
:
2520 case GLSL_TYPE_ERROR
:
2521 case GLSL_TYPE_INTERFACE
:
2522 assert(!"Should not get here.");
2526 _mesa_uniform_attach_driver_storage(storage
,
2527 4 * sizeof(float) * columns
,
2530 ¶ms
->ParameterValues
[i
]);
2532 /* After attaching the driver's storage to the uniform, propagate any
2533 * data from the linker's backing store. This will cause values from
2534 * initializers in the source code to be copied over.
2536 _mesa_propagate_uniforms_to_driver_storage(storage
,
2538 MAX2(1, storage
->array_elements
));
2540 last_location
= location
;
2546 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2547 * channels for copy propagation and updates following instructions to
2548 * use the original versions.
2550 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2551 * will occur. As an example, a TXP production before this pass:
2553 * 0: MOV TEMP[1], INPUT[4].xyyy;
2554 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2555 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2559 * 0: MOV TEMP[1], INPUT[4].xyyy;
2560 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2561 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2563 * which allows for dead code elimination on TEMP[1]'s writes.
2566 ir_to_mesa_visitor::copy_propagate(void)
2568 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2569 ir_to_mesa_instruction
*,
2570 this->next_temp
* 4);
2571 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2574 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2575 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2576 || inst
->dst
.index
< this->next_temp
);
2578 /* First, do any copy propagation possible into the src regs. */
2579 for (int r
= 0; r
< 3; r
++) {
2580 ir_to_mesa_instruction
*first
= NULL
;
2582 int acp_base
= inst
->src
[r
].index
* 4;
2584 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2585 inst
->src
[r
].reladdr
)
2588 /* See if we can find entries in the ACP consisting of MOVs
2589 * from the same src register for all the swizzled channels
2590 * of this src register reference.
2592 for (int i
= 0; i
< 4; i
++) {
2593 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2594 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2601 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2606 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2607 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2615 /* We've now validated that we can copy-propagate to
2616 * replace this src register reference. Do it.
2618 inst
->src
[r
].file
= first
->src
[0].file
;
2619 inst
->src
[r
].index
= first
->src
[0].index
;
2622 for (int i
= 0; i
< 4; i
++) {
2623 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2624 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2625 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2628 inst
->src
[r
].swizzle
= swizzle
;
2633 case OPCODE_BGNLOOP
:
2634 case OPCODE_ENDLOOP
:
2635 /* End of a basic block, clear the ACP entirely. */
2636 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2645 /* Clear all channels written inside the block from the ACP, but
2646 * leaving those that were not touched.
2648 for (int r
= 0; r
< this->next_temp
; r
++) {
2649 for (int c
= 0; c
< 4; c
++) {
2650 if (!acp
[4 * r
+ c
])
2653 if (acp_level
[4 * r
+ c
] >= level
)
2654 acp
[4 * r
+ c
] = NULL
;
2657 if (inst
->op
== OPCODE_ENDIF
)
2662 /* Continuing the block, clear any written channels from
2665 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2666 /* Any temporary might be written, so no copy propagation
2667 * across this instruction.
2669 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2670 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2671 inst
->dst
.reladdr
) {
2672 /* Any output might be written, so no copy propagation
2673 * from outputs across this instruction.
2675 for (int r
= 0; r
< this->next_temp
; r
++) {
2676 for (int c
= 0; c
< 4; c
++) {
2677 if (!acp
[4 * r
+ c
])
2680 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2681 acp
[4 * r
+ c
] = NULL
;
2684 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2685 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2686 /* Clear where it's used as dst. */
2687 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2688 for (int c
= 0; c
< 4; c
++) {
2689 if (inst
->dst
.writemask
& (1 << c
)) {
2690 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2695 /* Clear where it's used as src. */
2696 for (int r
= 0; r
< this->next_temp
; r
++) {
2697 for (int c
= 0; c
< 4; c
++) {
2698 if (!acp
[4 * r
+ c
])
2701 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2703 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2704 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2705 inst
->dst
.writemask
& (1 << src_chan
))
2707 acp
[4 * r
+ c
] = NULL
;
2715 /* If this is a copy, add it to the ACP. */
2716 if (inst
->op
== OPCODE_MOV
&&
2717 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2718 !(inst
->dst
.file
== inst
->src
[0].file
&&
2719 inst
->dst
.index
== inst
->src
[0].index
) &&
2720 !inst
->dst
.reladdr
&&
2722 !inst
->src
[0].reladdr
&&
2723 !inst
->src
[0].negate
) {
2724 for (int i
= 0; i
< 4; i
++) {
2725 if (inst
->dst
.writemask
& (1 << i
)) {
2726 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2727 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2733 ralloc_free(acp_level
);
2739 * Convert a shader's GLSL IR into a Mesa gl_program.
2741 static struct gl_program
*
2742 get_mesa_program(struct gl_context
*ctx
,
2743 struct gl_shader_program
*shader_program
,
2744 struct gl_shader
*shader
)
2746 ir_to_mesa_visitor v
;
2747 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2748 ir_instruction
**mesa_instruction_annotation
;
2750 struct gl_program
*prog
;
2751 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2752 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2753 struct gl_shader_compiler_options
*options
=
2754 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2756 validate_ir_tree(shader
->ir
);
2758 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2761 prog
->Parameters
= _mesa_new_parameter_list();
2764 v
.shader_program
= shader_program
;
2765 v
.options
= options
;
2767 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2770 /* Emit Mesa IR for main(). */
2771 visit_exec_list(shader
->ir
, &v
);
2772 v
.emit(NULL
, OPCODE_END
);
2774 prog
->NumTemporaries
= v
.next_temp
;
2776 unsigned num_instructions
= v
.instructions
.length();
2779 (struct prog_instruction
*)calloc(num_instructions
,
2780 sizeof(*mesa_instructions
));
2781 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2786 /* Convert ir_mesa_instructions into prog_instructions.
2788 mesa_inst
= mesa_instructions
;
2790 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2791 mesa_inst
->Opcode
= inst
->op
;
2792 mesa_inst
->CondUpdate
= inst
->cond_update
;
2794 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2795 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2796 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2797 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2798 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2799 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2800 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2801 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2802 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2803 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2804 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2805 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2806 mesa_instruction_annotation
[i
] = inst
->ir
;
2808 /* Set IndirectRegisterFiles. */
2809 if (mesa_inst
->DstReg
.RelAddr
)
2810 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2812 /* Update program's bitmask of indirectly accessed register files */
2813 for (unsigned src
= 0; src
< 3; src
++)
2814 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2815 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2817 switch (mesa_inst
->Opcode
) {
2819 if (options
->MaxIfDepth
== 0) {
2820 linker_warning(shader_program
,
2821 "Couldn't flatten if-statement. "
2822 "This will likely result in software "
2823 "rasterization.\n");
2826 case OPCODE_BGNLOOP
:
2827 if (options
->EmitNoLoops
) {
2828 linker_warning(shader_program
,
2829 "Couldn't unroll loop. "
2830 "This will likely result in software "
2831 "rasterization.\n");
2835 if (options
->EmitNoCont
) {
2836 linker_warning(shader_program
,
2837 "Couldn't lower continue-statement. "
2838 "This will likely result in software "
2839 "rasterization.\n");
2843 prog
->NumAddressRegs
= 1;
2852 if (!shader_program
->LinkStatus
)
2856 if (!shader_program
->LinkStatus
) {
2860 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2862 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2863 fprintf(stderr
, "\n");
2864 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2865 shader_program
->Name
);
2866 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2867 fprintf(stderr
, "\n");
2868 fprintf(stderr
, "\n");
2869 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2870 shader_program
->Name
);
2871 print_program(mesa_instructions
, mesa_instruction_annotation
,
2876 prog
->Instructions
= mesa_instructions
;
2877 prog
->NumInstructions
= num_instructions
;
2879 /* Setting this to NULL prevents a possible double free in the fail_exit
2882 mesa_instructions
= NULL
;
2884 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2886 prog
->SamplersUsed
= shader
->active_samplers
;
2887 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2888 _mesa_update_shader_textures_used(shader_program
, prog
);
2890 /* Set the gl_FragDepth layout. */
2891 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2892 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2893 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2896 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2898 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2899 _mesa_optimize_program(ctx
, prog
);
2902 /* This has to be done last. Any operation that can cause
2903 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2904 * program constant) has to happen before creating this linkage.
2906 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2907 if (!shader_program
->LinkStatus
) {
2914 free(mesa_instructions
);
2915 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2923 * Called via ctx->Driver.LinkShader()
2924 * This actually involves converting GLSL IR into Mesa gl_programs with
2925 * code lowering and other optimizations.
2928 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2930 assert(prog
->LinkStatus
);
2932 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2933 if (prog
->_LinkedShaders
[i
] == NULL
)
2937 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2938 const struct gl_shader_compiler_options
*options
=
2939 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2945 do_mat_op_to_vec(ir
);
2946 GLenum target
= _mesa_shader_stage_to_program(prog
->_LinkedShaders
[i
]->Stage
);
2947 lower_instructions(ir
, (MOD_TO_FRACT
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2948 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2949 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2951 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2953 progress
= do_common_optimization(ir
, true, true,
2954 options
, ctx
->Const
.NativeIntegers
)
2957 progress
= lower_quadop_vector(ir
, true) || progress
;
2959 if (options
->MaxIfDepth
== 0)
2960 progress
= lower_discard(ir
) || progress
;
2962 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
2964 if (options
->EmitNoNoise
)
2965 progress
= lower_noise(ir
) || progress
;
2967 /* If there are forms of indirect addressing that the driver
2968 * cannot handle, perform the lowering pass.
2970 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
2971 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
2973 lower_variable_index_to_cond_assign(ir
,
2974 options
->EmitNoIndirectInput
,
2975 options
->EmitNoIndirectOutput
,
2976 options
->EmitNoIndirectTemp
,
2977 options
->EmitNoIndirectUniform
)
2980 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
2981 progress
= lower_vector_insert(ir
, true) || progress
;
2984 validate_ir_tree(ir
);
2987 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2988 struct gl_program
*linked_prog
;
2990 if (prog
->_LinkedShaders
[i
] == NULL
)
2993 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
2996 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
2998 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
3000 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
3001 _mesa_shader_stage_to_program(i
),
3007 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3010 return prog
->LinkStatus
;
3014 * Link a GLSL shader program. Called via glLinkProgram().
3017 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3021 _mesa_clear_shader_program_data(prog
);
3023 prog
->LinkStatus
= GL_TRUE
;
3025 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3026 if (!prog
->Shaders
[i
]->CompileStatus
) {
3027 linker_error(prog
, "linking with uncompiled shader");
3031 if (prog
->LinkStatus
) {
3032 link_shaders(ctx
, prog
);
3035 if (prog
->LinkStatus
) {
3036 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3037 prog
->LinkStatus
= GL_FALSE
;
3041 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
3042 if (!prog
->LinkStatus
) {
3043 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
3046 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3047 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
3048 fprintf(stderr
, "%s\n", prog
->InfoLog
);