2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
34 #include "main/mtypes.h"
35 #include "main/shaderapi.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
40 #include "glsl/ir_expression_flattening.h"
41 #include "glsl/ir_visitor.h"
42 #include "glsl/ir_optimization.h"
43 #include "glsl/ir_uniform.h"
44 #include "glsl/glsl_parser_extras.h"
45 #include "glsl/nir/glsl_types.h"
46 #include "glsl/linker.h"
47 #include "glsl/program.h"
48 #include "program/hash_table.h"
49 #include "program/prog_instruction.h"
50 #include "program/prog_optimize.h"
51 #include "program/prog_print.h"
52 #include "program/program.h"
53 #include "program/prog_parameter.h"
54 #include "program/sampler.h"
57 static int swizzle_for_size(int size
);
65 * This struct is a corresponding struct to Mesa prog_src_register, with
70 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
74 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
75 this->swizzle
= swizzle_for_size(type
->vector_elements
);
77 this->swizzle
= SWIZZLE_XYZW
;
84 this->file
= PROGRAM_UNDEFINED
;
91 explicit src_reg(dst_reg reg
);
93 gl_register_file file
; /**< PROGRAM_* from Mesa */
94 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
95 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
96 int negate
; /**< NEGATE_XYZW mask from mesa */
97 /** Register index should be offset by the integer in this reg. */
103 dst_reg(gl_register_file file
, int writemask
)
107 this->writemask
= writemask
;
108 this->cond_mask
= COND_TR
;
109 this->reladdr
= NULL
;
114 this->file
= PROGRAM_UNDEFINED
;
117 this->cond_mask
= COND_TR
;
118 this->reladdr
= NULL
;
121 explicit dst_reg(src_reg reg
);
123 gl_register_file file
; /**< PROGRAM_* from Mesa */
124 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
125 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
127 /** Register index should be offset by the integer in this reg. */
131 } /* anonymous namespace */
133 src_reg::src_reg(dst_reg reg
)
135 this->file
= reg
.file
;
136 this->index
= reg
.index
;
137 this->swizzle
= SWIZZLE_XYZW
;
139 this->reladdr
= reg
.reladdr
;
142 dst_reg::dst_reg(src_reg reg
)
144 this->file
= reg
.file
;
145 this->index
= reg
.index
;
146 this->writemask
= WRITEMASK_XYZW
;
147 this->cond_mask
= COND_TR
;
148 this->reladdr
= reg
.reladdr
;
153 class ir_to_mesa_instruction
: public exec_node
{
155 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
160 /** Pointer to the ir source this tree came from for debugging */
162 GLboolean cond_update
;
164 int sampler
; /**< sampler index */
165 int tex_target
; /**< One of TEXTURE_*_INDEX */
166 GLboolean tex_shadow
;
169 class variable_storage
: public exec_node
{
171 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
172 : file(file
), index(index
), var(var
)
177 gl_register_file file
;
179 ir_variable
*var
; /* variable that maps to this, if any */
182 class function_entry
: public exec_node
{
184 ir_function_signature
*sig
;
187 * identifier of this function signature used by the program.
189 * At the point that Mesa instructions for function calls are
190 * generated, we don't know the address of the first instruction of
191 * the function body. So we make the BranchTarget that is called a
192 * small integer and rewrite them during set_branchtargets().
197 * Pointer to first instruction of the function body.
199 * Set during function body emits after main() is processed.
201 ir_to_mesa_instruction
*bgn_inst
;
204 * Index of the first instruction of the function body in actual
207 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
211 /** Storage for the return value. */
215 class ir_to_mesa_visitor
: public ir_visitor
{
217 ir_to_mesa_visitor();
218 ~ir_to_mesa_visitor();
220 function_entry
*current_function
;
222 struct gl_context
*ctx
;
223 struct gl_program
*prog
;
224 struct gl_shader_program
*shader_program
;
225 struct gl_shader_compiler_options
*options
;
229 variable_storage
*find_variable_storage(const ir_variable
*var
);
231 src_reg
get_temp(const glsl_type
*type
);
232 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
234 src_reg
src_reg_for_float(float val
);
237 * \name Visit methods
239 * As typical for the visitor pattern, there must be one \c visit method for
240 * each concrete subclass of \c ir_instruction. Virtual base classes within
241 * the hierarchy should not have \c visit methods.
244 virtual void visit(ir_variable
*);
245 virtual void visit(ir_loop
*);
246 virtual void visit(ir_loop_jump
*);
247 virtual void visit(ir_function_signature
*);
248 virtual void visit(ir_function
*);
249 virtual void visit(ir_expression
*);
250 virtual void visit(ir_swizzle
*);
251 virtual void visit(ir_dereference_variable
*);
252 virtual void visit(ir_dereference_array
*);
253 virtual void visit(ir_dereference_record
*);
254 virtual void visit(ir_assignment
*);
255 virtual void visit(ir_constant
*);
256 virtual void visit(ir_call
*);
257 virtual void visit(ir_return
*);
258 virtual void visit(ir_discard
*);
259 virtual void visit(ir_texture
*);
260 virtual void visit(ir_if
*);
261 virtual void visit(ir_emit_vertex
*);
262 virtual void visit(ir_end_primitive
*);
263 virtual void visit(ir_barrier
*);
268 /** List of variable_storage */
271 /** List of function_entry */
272 exec_list function_signatures
;
273 int next_signature_id
;
275 /** List of ir_to_mesa_instruction */
276 exec_list instructions
;
278 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
281 dst_reg dst
, src_reg src0
);
283 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
284 dst_reg dst
, src_reg src0
, src_reg src1
);
286 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
288 src_reg src0
, src_reg src1
, src_reg src2
);
291 * Emit the correct dot-product instruction for the type of arguments
293 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
299 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
300 dst_reg dst
, src_reg src0
);
302 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
303 dst_reg dst
, src_reg src0
, src_reg src1
);
305 bool try_emit_mad(ir_expression
*ir
,
307 bool try_emit_mad_for_and_not(ir_expression
*ir
,
310 void emit_swz(ir_expression
*ir
);
312 bool process_move_condition(ir_rvalue
*ir
);
314 void copy_propagate(void);
319 } /* anonymous namespace */
321 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
323 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
325 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
328 swizzle_for_size(int size
)
330 static const int size_swizzles
[4] = {
331 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
332 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
333 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
334 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
337 assert((size
>= 1) && (size
<= 4));
338 return size_swizzles
[size
- 1];
341 ir_to_mesa_instruction
*
342 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
344 src_reg src0
, src_reg src1
, src_reg src2
)
346 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
349 /* If we have to do relative addressing, we want to load the ARL
350 * reg directly for one of the regs, and preload the other reladdr
351 * sources into temps.
353 num_reladdr
+= dst
.reladdr
!= NULL
;
354 num_reladdr
+= src0
.reladdr
!= NULL
;
355 num_reladdr
+= src1
.reladdr
!= NULL
;
356 num_reladdr
+= src2
.reladdr
!= NULL
;
358 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
359 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
360 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
363 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
366 assert(num_reladdr
== 0);
375 this->instructions
.push_tail(inst
);
381 ir_to_mesa_instruction
*
382 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
383 dst_reg dst
, src_reg src0
, src_reg src1
)
385 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
388 ir_to_mesa_instruction
*
389 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
390 dst_reg dst
, src_reg src0
)
392 assert(dst
.writemask
!= 0);
393 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
396 ir_to_mesa_instruction
*
397 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
399 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
402 ir_to_mesa_instruction
*
403 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
404 dst_reg dst
, src_reg src0
, src_reg src1
,
407 static const enum prog_opcode dot_opcodes
[] = {
408 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
411 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
415 * Emits Mesa scalar opcodes to produce unique answers across channels.
417 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
418 * channel determines the result across all channels. So to do a vec4
419 * of this operation, we want to emit a scalar per source channel used
420 * to produce dest channels.
423 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
425 src_reg orig_src0
, src_reg orig_src1
)
428 int done_mask
= ~dst
.writemask
;
430 /* Mesa RCP is a scalar operation splatting results to all channels,
431 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
434 for (i
= 0; i
< 4; i
++) {
435 GLuint this_mask
= (1 << i
);
436 ir_to_mesa_instruction
*inst
;
437 src_reg src0
= orig_src0
;
438 src_reg src1
= orig_src1
;
440 if (done_mask
& this_mask
)
443 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
444 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
445 for (j
= i
+ 1; j
< 4; j
++) {
446 /* If there is another enabled component in the destination that is
447 * derived from the same inputs, generate its value on this pass as
450 if (!(done_mask
& (1 << j
)) &&
451 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
452 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
453 this_mask
|= (1 << j
);
456 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
457 src0_swiz
, src0_swiz
);
458 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
459 src1_swiz
, src1_swiz
);
461 inst
= emit(ir
, op
, dst
, src0
, src1
);
462 inst
->dst
.writemask
= this_mask
;
463 done_mask
|= this_mask
;
468 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
469 dst_reg dst
, src_reg src0
)
471 src_reg undef
= undef_src
;
473 undef
.swizzle
= SWIZZLE_XXXX
;
475 emit_scalar(ir
, op
, dst
, src0
, undef
);
479 ir_to_mesa_visitor::src_reg_for_float(float val
)
481 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
483 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
484 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
490 type_size(const struct glsl_type
*type
)
495 switch (type
->base_type
) {
498 case GLSL_TYPE_FLOAT
:
500 if (type
->is_matrix()) {
501 return type
->matrix_columns
;
503 /* Regardless of size of vector, it gets a vec4. This is bad
504 * packing for things like floats, but otherwise arrays become a
505 * mess. Hopefully a later pass over the code can pack scalars
506 * down if appropriate.
511 case GLSL_TYPE_DOUBLE
:
512 if (type
->is_matrix()) {
513 if (type
->vector_elements
> 2)
514 return type
->matrix_columns
* 2;
516 return type
->matrix_columns
;
518 if (type
->vector_elements
> 2)
524 case GLSL_TYPE_ARRAY
:
525 assert(type
->length
> 0);
526 return type_size(type
->fields
.array
) * type
->length
;
527 case GLSL_TYPE_STRUCT
:
529 for (i
= 0; i
< type
->length
; i
++) {
530 size
+= type_size(type
->fields
.structure
[i
].type
);
533 case GLSL_TYPE_SAMPLER
:
534 case GLSL_TYPE_IMAGE
:
535 case GLSL_TYPE_SUBROUTINE
:
536 /* Samplers take up one slot in UNIFORMS[], but they're baked in
540 case GLSL_TYPE_ATOMIC_UINT
:
542 case GLSL_TYPE_ERROR
:
543 case GLSL_TYPE_INTERFACE
:
544 case GLSL_TYPE_FUNCTION
:
545 assert(!"Invalid type in type_size");
553 * In the initial pass of codegen, we assign temporary numbers to
554 * intermediate results. (not SSA -- variable assignments will reuse
555 * storage). Actual register allocation for the Mesa VM occurs in a
556 * pass over the Mesa IR later.
559 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
563 src
.file
= PROGRAM_TEMPORARY
;
564 src
.index
= next_temp
;
566 next_temp
+= type_size(type
);
568 if (type
->is_array() || type
->is_record()) {
569 src
.swizzle
= SWIZZLE_NOOP
;
571 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
579 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
581 foreach_in_list(variable_storage
, entry
, &this->variables
) {
582 if (entry
->var
== var
)
590 ir_to_mesa_visitor::visit(ir_variable
*ir
)
592 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
593 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
595 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
596 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
599 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
601 const ir_state_slot
*const slots
= ir
->get_state_slots();
602 assert(slots
!= NULL
);
604 /* Check if this statevar's setup in the STATE file exactly
605 * matches how we'll want to reference it as a
606 * struct/array/whatever. If not, then we need to move it into
607 * temporary storage and hope that it'll get copy-propagated
610 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
611 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
616 variable_storage
*storage
;
618 if (i
== ir
->get_num_state_slots()) {
619 /* We'll set the index later. */
620 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
621 this->variables
.push_tail(storage
);
625 /* The variable_storage constructor allocates slots based on the size
626 * of the type. However, this had better match the number of state
627 * elements that we're going to copy into the new temporary.
629 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
631 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
633 this->variables
.push_tail(storage
);
634 this->next_temp
+= type_size(ir
->type
);
636 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
640 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
641 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
642 (gl_state_index
*)slots
[i
].tokens
);
644 if (storage
->file
== PROGRAM_STATE_VAR
) {
645 if (storage
->index
== -1) {
646 storage
->index
= index
;
648 assert(index
== storage
->index
+ (int)i
);
651 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
652 src
.swizzle
= slots
[i
].swizzle
;
653 emit(ir
, OPCODE_MOV
, dst
, src
);
654 /* even a float takes up a whole vec4 reg in a struct/array. */
659 if (storage
->file
== PROGRAM_TEMPORARY
&&
660 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
661 linker_error(this->shader_program
,
662 "failed to load builtin uniform `%s' "
663 "(%d/%d regs loaded)\n",
664 ir
->name
, dst
.index
- storage
->index
,
665 type_size(ir
->type
));
671 ir_to_mesa_visitor::visit(ir_loop
*ir
)
673 emit(NULL
, OPCODE_BGNLOOP
);
675 visit_exec_list(&ir
->body_instructions
, this);
677 emit(NULL
, OPCODE_ENDLOOP
);
681 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
684 case ir_loop_jump::jump_break
:
685 emit(NULL
, OPCODE_BRK
);
687 case ir_loop_jump::jump_continue
:
688 emit(NULL
, OPCODE_CONT
);
695 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
702 ir_to_mesa_visitor::visit(ir_function
*ir
)
704 /* Ignore function bodies other than main() -- we shouldn't see calls to
705 * them since they should all be inlined before we get to ir_to_mesa.
707 if (strcmp(ir
->name
, "main") == 0) {
708 const ir_function_signature
*sig
;
711 sig
= ir
->matching_signature(NULL
, &empty
, false);
715 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
722 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
724 int nonmul_operand
= 1 - mul_operand
;
727 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
728 if (!expr
|| expr
->operation
!= ir_binop_mul
)
731 expr
->operands
[0]->accept(this);
733 expr
->operands
[1]->accept(this);
735 ir
->operands
[nonmul_operand
]->accept(this);
738 this->result
= get_temp(ir
->type
);
739 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
745 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
747 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
748 * implemented using multiplication, and logical-or is implemented using
749 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
750 * As result, the logical expression (a & !b) can be rewritten as:
754 * - (a * 1) - (a * b)
758 * This final expression can be implemented as a single MAD(a, -b, a)
762 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
764 const int other_operand
= 1 - try_operand
;
767 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
768 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
771 ir
->operands
[other_operand
]->accept(this);
773 expr
->operands
[0]->accept(this);
776 b
.negate
= ~b
.negate
;
778 this->result
= get_temp(ir
->type
);
779 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
785 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
786 src_reg
*reg
, int *num_reladdr
)
791 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
793 if (*num_reladdr
!= 1) {
794 src_reg temp
= get_temp(glsl_type::vec4_type
);
796 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
804 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
806 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
807 * This means that each of the operands is either an immediate value of -1,
808 * 0, or 1, or is a component from one source register (possibly with
811 uint8_t components
[4] = { 0 };
812 bool negate
[4] = { false };
813 ir_variable
*var
= NULL
;
815 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
816 ir_rvalue
*op
= ir
->operands
[i
];
818 assert(op
->type
->is_scalar());
821 switch (op
->ir_type
) {
822 case ir_type_constant
: {
824 assert(op
->type
->is_scalar());
826 const ir_constant
*const c
= op
->as_constant();
828 components
[i
] = SWIZZLE_ONE
;
829 } else if (c
->is_zero()) {
830 components
[i
] = SWIZZLE_ZERO
;
831 } else if (c
->is_negative_one()) {
832 components
[i
] = SWIZZLE_ONE
;
835 assert(!"SWZ constant must be 0.0 or 1.0.");
842 case ir_type_dereference_variable
: {
843 ir_dereference_variable
*const deref
=
844 (ir_dereference_variable
*) op
;
846 assert((var
== NULL
) || (deref
->var
== var
));
847 components
[i
] = SWIZZLE_X
;
853 case ir_type_expression
: {
854 ir_expression
*const expr
= (ir_expression
*) op
;
856 assert(expr
->operation
== ir_unop_neg
);
859 op
= expr
->operands
[0];
863 case ir_type_swizzle
: {
864 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
866 components
[i
] = swiz
->mask
.x
;
872 assert(!"Should not get here.");
880 ir_dereference_variable
*const deref
=
881 new(mem_ctx
) ir_dereference_variable(var
);
883 this->result
.file
= PROGRAM_UNDEFINED
;
885 if (this->result
.file
== PROGRAM_UNDEFINED
) {
886 printf("Failed to get tree for expression operand:\n");
895 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
899 src
.negate
= ((unsigned(negate
[0]) << 0)
900 | (unsigned(negate
[1]) << 1)
901 | (unsigned(negate
[2]) << 2)
902 | (unsigned(negate
[3]) << 3));
904 /* Storage for our result. Ideally for an assignment we'd be using the
905 * actual storage for the result here, instead.
907 const src_reg result_src
= get_temp(ir
->type
);
908 dst_reg result_dst
= dst_reg(result_src
);
910 /* Limit writes to the channels that will be used by result_src later.
911 * This does limit this temp's use as a temporary for multi-instruction
914 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
916 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
917 this->result
= result_src
;
921 ir_to_mesa_visitor::visit(ir_expression
*ir
)
923 unsigned int operand
;
924 src_reg op
[ARRAY_SIZE(ir
->operands
)];
928 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
930 if (ir
->operation
== ir_binop_add
) {
931 if (try_emit_mad(ir
, 1))
933 if (try_emit_mad(ir
, 0))
937 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
939 if (ir
->operation
== ir_binop_logic_and
) {
940 if (try_emit_mad_for_and_not(ir
, 1))
942 if (try_emit_mad_for_and_not(ir
, 0))
946 if (ir
->operation
== ir_quadop_vector
) {
951 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
952 this->result
.file
= PROGRAM_UNDEFINED
;
953 ir
->operands
[operand
]->accept(this);
954 if (this->result
.file
== PROGRAM_UNDEFINED
) {
955 printf("Failed to get tree for expression operand:\n");
956 ir
->operands
[operand
]->print();
960 op
[operand
] = this->result
;
962 /* Matrix expression operands should have been broken down to vector
963 * operations already.
965 assert(!ir
->operands
[operand
]->type
->is_matrix());
968 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
969 if (ir
->operands
[1]) {
970 vector_elements
= MAX2(vector_elements
,
971 ir
->operands
[1]->type
->vector_elements
);
974 this->result
.file
= PROGRAM_UNDEFINED
;
976 /* Storage for our result. Ideally for an assignment we'd be using
977 * the actual storage for the result here, instead.
979 result_src
= get_temp(ir
->type
);
980 /* convenience for the emit functions below. */
981 result_dst
= dst_reg(result_src
);
982 /* Limit writes to the channels that will be used by result_src later.
983 * This does limit this temp's use as a temporary for multi-instruction
986 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
988 switch (ir
->operation
) {
989 case ir_unop_logic_not
:
990 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
991 * older GPUs implement SEQ using multiple instructions (i915 uses two
992 * SGE instructions and a MUL instruction). Since our logic values are
993 * 0.0 and 1.0, 1-x also implements !x.
995 op
[0].negate
= ~op
[0].negate
;
996 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
999 op
[0].negate
= ~op
[0].negate
;
1003 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1006 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1009 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1013 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1017 assert(!"not reached: should be handled by ir_explog_to_explog2");
1020 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1023 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1026 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1030 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1033 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1036 case ir_unop_saturate
: {
1037 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_MOV
,
1039 inst
->saturate
= true;
1042 case ir_unop_noise
: {
1043 const enum prog_opcode opcode
=
1044 prog_opcode(OPCODE_NOISE1
1045 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1046 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1048 emit(ir
, opcode
, result_dst
, op
[0]);
1053 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1056 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1060 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1063 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1066 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1067 assert(ir
->type
->is_integer());
1068 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1072 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1074 case ir_binop_greater
:
1075 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1077 case ir_binop_lequal
:
1078 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1080 case ir_binop_gequal
:
1081 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1083 case ir_binop_equal
:
1084 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1086 case ir_binop_nequal
:
1087 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1089 case ir_binop_all_equal
:
1090 /* "==" operator producing a scalar boolean. */
1091 if (ir
->operands
[0]->type
->is_vector() ||
1092 ir
->operands
[1]->type
->is_vector()) {
1093 src_reg temp
= get_temp(glsl_type::vec4_type
);
1094 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1096 /* After the dot-product, the value will be an integer on the
1097 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1099 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1101 /* Negating the result of the dot-product gives values on the range
1102 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1103 * achieved using SGE.
1105 src_reg sge_src
= result_src
;
1106 sge_src
.negate
= ~sge_src
.negate
;
1107 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1109 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1112 case ir_binop_any_nequal
:
1113 /* "!=" operator producing a scalar boolean. */
1114 if (ir
->operands
[0]->type
->is_vector() ||
1115 ir
->operands
[1]->type
->is_vector()) {
1116 src_reg temp
= get_temp(glsl_type::vec4_type
);
1117 if (ir
->operands
[0]->type
->is_boolean() &&
1118 ir
->operands
[1]->as_constant() &&
1119 ir
->operands
[1]->as_constant()->is_zero()) {
1122 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1125 /* After the dot-product, the value will be an integer on the
1126 * range [0,4]. Zero stays zero, and positive values become 1.0.
1128 ir_to_mesa_instruction
*const dp
=
1129 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1130 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1131 /* The clamping to [0,1] can be done for free in the fragment
1132 * shader with a saturate.
1134 dp
->saturate
= true;
1136 /* Negating the result of the dot-product gives values on the range
1137 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1138 * achieved using SLT.
1140 src_reg slt_src
= result_src
;
1141 slt_src
.negate
= ~slt_src
.negate
;
1142 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1145 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1149 case ir_binop_logic_xor
:
1150 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1153 case ir_binop_logic_or
: {
1154 /* After the addition, the value will be an integer on the
1155 * range [0,2]. Zero stays zero, and positive values become 1.0.
1157 ir_to_mesa_instruction
*add
=
1158 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1159 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1160 /* The clamping to [0,1] can be done for free in the fragment
1161 * shader with a saturate.
1163 add
->saturate
= true;
1165 /* Negating the result of the addition gives values on the range
1166 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1167 * is achieved using SLT.
1169 src_reg slt_src
= result_src
;
1170 slt_src
.negate
= ~slt_src
.negate
;
1171 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1176 case ir_binop_logic_and
:
1177 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1178 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1182 assert(ir
->operands
[0]->type
->is_vector());
1183 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1184 emit_dp(ir
, result_dst
, op
[0], op
[1],
1185 ir
->operands
[0]->type
->vector_elements
);
1189 /* sqrt(x) = x * rsq(x). */
1190 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1191 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1192 /* For incoming channels <= 0, set the result to 0. */
1193 op
[0].negate
= ~op
[0].negate
;
1194 emit(ir
, OPCODE_CMP
, result_dst
,
1195 op
[0], result_src
, src_reg_for_float(0.0));
1198 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1206 /* Mesa IR lacks types, ints are stored as truncated floats. */
1211 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1215 emit(ir
, OPCODE_SNE
, result_dst
,
1216 op
[0], src_reg_for_float(0.0));
1218 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1219 case ir_unop_bitcast_f2u
:
1220 case ir_unop_bitcast_i2f
:
1221 case ir_unop_bitcast_u2f
:
1224 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1227 op
[0].negate
= ~op
[0].negate
;
1228 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1229 result_src
.negate
= ~result_src
.negate
;
1232 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1235 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1237 case ir_unop_pack_snorm_2x16
:
1238 case ir_unop_pack_snorm_4x8
:
1239 case ir_unop_pack_unorm_2x16
:
1240 case ir_unop_pack_unorm_4x8
:
1241 case ir_unop_pack_half_2x16
:
1242 case ir_unop_pack_double_2x32
:
1243 case ir_unop_unpack_snorm_2x16
:
1244 case ir_unop_unpack_snorm_4x8
:
1245 case ir_unop_unpack_unorm_2x16
:
1246 case ir_unop_unpack_unorm_4x8
:
1247 case ir_unop_unpack_half_2x16
:
1248 case ir_unop_unpack_half_2x16_split_x
:
1249 case ir_unop_unpack_half_2x16_split_y
:
1250 case ir_unop_unpack_double_2x32
:
1251 case ir_binop_pack_half_2x16_split
:
1252 case ir_unop_bitfield_reverse
:
1253 case ir_unop_bit_count
:
1254 case ir_unop_find_msb
:
1255 case ir_unop_find_lsb
:
1263 case ir_unop_frexp_sig
:
1264 case ir_unop_frexp_exp
:
1265 assert(!"not supported");
1268 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1271 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1274 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1277 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1278 * hardware backends have no way to avoid Mesa IR generation
1279 * even if they don't use it, we need to emit "something" and
1282 case ir_binop_lshift
:
1283 case ir_binop_rshift
:
1284 case ir_binop_bit_and
:
1285 case ir_binop_bit_xor
:
1286 case ir_binop_bit_or
:
1287 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1290 case ir_unop_bit_not
:
1291 case ir_unop_round_even
:
1292 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1295 case ir_binop_ubo_load
:
1296 assert(!"not supported");
1300 /* ir_triop_lrp operands are (x, y, a) while
1301 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1303 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1306 case ir_binop_vector_extract
:
1310 case ir_triop_bitfield_extract
:
1311 case ir_triop_vector_insert
:
1312 case ir_quadop_bitfield_insert
:
1313 case ir_binop_ldexp
:
1315 case ir_binop_carry
:
1316 case ir_binop_borrow
:
1317 case ir_binop_imul_high
:
1318 case ir_unop_interpolate_at_centroid
:
1319 case ir_binop_interpolate_at_offset
:
1320 case ir_binop_interpolate_at_sample
:
1321 case ir_unop_dFdx_coarse
:
1322 case ir_unop_dFdx_fine
:
1323 case ir_unop_dFdy_coarse
:
1324 case ir_unop_dFdy_fine
:
1325 case ir_unop_subroutine_to_int
:
1326 case ir_unop_get_buffer_size
:
1327 assert(!"not supported");
1330 case ir_unop_ssbo_unsized_array_length
:
1331 case ir_quadop_vector
:
1332 /* This operation should have already been handled.
1334 assert(!"Should not get here.");
1338 this->result
= result_src
;
1343 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1349 /* Note that this is only swizzles in expressions, not those on the left
1350 * hand side of an assignment, which do write masking. See ir_assignment
1354 ir
->val
->accept(this);
1356 assert(src
.file
!= PROGRAM_UNDEFINED
);
1357 assert(ir
->type
->vector_elements
> 0);
1359 for (i
= 0; i
< 4; i
++) {
1360 if (i
< ir
->type
->vector_elements
) {
1363 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1366 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1369 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1372 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1376 /* If the type is smaller than a vec4, replicate the last
1379 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1383 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1389 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1391 variable_storage
*entry
= find_variable_storage(ir
->var
);
1392 ir_variable
*var
= ir
->var
;
1395 switch (var
->data
.mode
) {
1396 case ir_var_uniform
:
1397 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1398 var
->data
.location
);
1399 this->variables
.push_tail(entry
);
1401 case ir_var_shader_in
:
1402 /* The linker assigns locations for varyings and attributes,
1403 * including deprecated builtins (like gl_Color),
1404 * user-assigned generic attributes (glBindVertexLocation),
1405 * and user-defined varyings.
1407 assert(var
->data
.location
!= -1);
1408 entry
= new(mem_ctx
) variable_storage(var
,
1410 var
->data
.location
);
1412 case ir_var_shader_out
:
1413 assert(var
->data
.location
!= -1);
1414 entry
= new(mem_ctx
) variable_storage(var
,
1416 var
->data
.location
);
1418 case ir_var_system_value
:
1419 entry
= new(mem_ctx
) variable_storage(var
,
1420 PROGRAM_SYSTEM_VALUE
,
1421 var
->data
.location
);
1424 case ir_var_temporary
:
1425 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1427 this->variables
.push_tail(entry
);
1429 next_temp
+= type_size(var
->type
);
1434 printf("Failed to make storage for %s\n", var
->name
);
1439 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1443 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1447 int element_size
= type_size(ir
->type
);
1449 index
= ir
->array_index
->constant_expression_value();
1451 ir
->array
->accept(this);
1455 src
.index
+= index
->value
.i
[0] * element_size
;
1457 /* Variable index array dereference. It eats the "vec4" of the
1458 * base of the array and an index that offsets the Mesa register
1461 ir
->array_index
->accept(this);
1465 if (element_size
== 1) {
1466 index_reg
= this->result
;
1468 index_reg
= get_temp(glsl_type::float_type
);
1470 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1471 this->result
, src_reg_for_float(element_size
));
1474 /* If there was already a relative address register involved, add the
1475 * new and the old together to get the new offset.
1477 if (src
.reladdr
!= NULL
) {
1478 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1480 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1481 index_reg
, *src
.reladdr
);
1483 index_reg
= accum_reg
;
1486 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1487 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1490 /* If the type is smaller than a vec4, replicate the last channel out. */
1491 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1492 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1494 src
.swizzle
= SWIZZLE_NOOP
;
1500 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1503 const glsl_type
*struct_type
= ir
->record
->type
;
1506 ir
->record
->accept(this);
1508 for (i
= 0; i
< struct_type
->length
; i
++) {
1509 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1511 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1514 /* If the type is smaller than a vec4, replicate the last channel out. */
1515 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1516 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1518 this->result
.swizzle
= SWIZZLE_NOOP
;
1520 this->result
.index
+= offset
;
1524 * We want to be careful in assignment setup to hit the actual storage
1525 * instead of potentially using a temporary like we might with the
1526 * ir_dereference handler.
1529 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1531 /* The LHS must be a dereference. If the LHS is a variable indexed array
1532 * access of a vector, it must be separated into a series conditional moves
1533 * before reaching this point (see ir_vec_index_to_cond_assign).
1535 assert(ir
->as_dereference());
1536 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1538 assert(!deref_array
->array
->type
->is_vector());
1541 /* Use the rvalue deref handler for the most part. We'll ignore
1542 * swizzles in it and write swizzles using writemask, though.
1545 return dst_reg(v
->result
);
1549 * Process the condition of a conditional assignment
1551 * Examines the condition of a conditional assignment to generate the optimal
1552 * first operand of a \c CMP instruction. If the condition is a relational
1553 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1554 * used as the source for the \c CMP instruction. Otherwise the comparison
1555 * is processed to a boolean result, and the boolean result is used as the
1556 * operand to the CMP instruction.
1559 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1561 ir_rvalue
*src_ir
= ir
;
1563 bool switch_order
= false;
1565 ir_expression
*const expr
= ir
->as_expression();
1566 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1567 bool zero_on_left
= false;
1569 if (expr
->operands
[0]->is_zero()) {
1570 src_ir
= expr
->operands
[1];
1571 zero_on_left
= true;
1572 } else if (expr
->operands
[1]->is_zero()) {
1573 src_ir
= expr
->operands
[0];
1574 zero_on_left
= false;
1578 * (a < 0) T F F ( a < 0) T F F
1579 * (0 < a) F F T (-a < 0) F F T
1580 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1581 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1582 * (a > 0) F F T (-a < 0) F F T
1583 * (0 > a) T F F ( a < 0) T F F
1584 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1585 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1587 * Note that exchanging the order of 0 and 'a' in the comparison simply
1588 * means that the value of 'a' should be negated.
1591 switch (expr
->operation
) {
1593 switch_order
= false;
1594 negate
= zero_on_left
;
1597 case ir_binop_greater
:
1598 switch_order
= false;
1599 negate
= !zero_on_left
;
1602 case ir_binop_lequal
:
1603 switch_order
= true;
1604 negate
= !zero_on_left
;
1607 case ir_binop_gequal
:
1608 switch_order
= true;
1609 negate
= zero_on_left
;
1613 /* This isn't the right kind of comparison afterall, so make sure
1614 * the whole condition is visited.
1622 src_ir
->accept(this);
1624 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1625 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1626 * choose which value OPCODE_CMP produces without an extra instruction
1627 * computing the condition.
1630 this->result
.negate
= ~this->result
.negate
;
1632 return switch_order
;
1636 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1642 ir
->rhs
->accept(this);
1645 l
= get_assignment_lhs(ir
->lhs
, this);
1647 /* FINISHME: This should really set to the correct maximal writemask for each
1648 * FINISHME: component written (in the loops below). This case can only
1649 * FINISHME: occur for matrices, arrays, and structures.
1651 if (ir
->write_mask
== 0) {
1652 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1653 l
.writemask
= WRITEMASK_XYZW
;
1654 } else if (ir
->lhs
->type
->is_scalar()) {
1655 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1656 * FINISHME: W component of fragment shader output zero, work correctly.
1658 l
.writemask
= WRITEMASK_XYZW
;
1661 int first_enabled_chan
= 0;
1664 assert(ir
->lhs
->type
->is_vector());
1665 l
.writemask
= ir
->write_mask
;
1667 for (int i
= 0; i
< 4; i
++) {
1668 if (l
.writemask
& (1 << i
)) {
1669 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1674 /* Swizzle a small RHS vector into the channels being written.
1676 * glsl ir treats write_mask as dictating how many channels are
1677 * present on the RHS while Mesa IR treats write_mask as just
1678 * showing which channels of the vec4 RHS get written.
1680 for (int i
= 0; i
< 4; i
++) {
1681 if (l
.writemask
& (1 << i
))
1682 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1684 swizzles
[i
] = first_enabled_chan
;
1686 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1687 swizzles
[2], swizzles
[3]);
1690 assert(l
.file
!= PROGRAM_UNDEFINED
);
1691 assert(r
.file
!= PROGRAM_UNDEFINED
);
1693 if (ir
->condition
) {
1694 const bool switch_order
= this->process_move_condition(ir
->condition
);
1695 src_reg condition
= this->result
;
1697 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1699 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1701 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1708 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1709 emit(ir
, OPCODE_MOV
, l
, r
);
1718 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1721 GLfloat stack_vals
[4] = { 0 };
1722 GLfloat
*values
= stack_vals
;
1725 /* Unfortunately, 4 floats is all we can get into
1726 * _mesa_add_unnamed_constant. So, make a temp to store an
1727 * aggregate constant and move each constant value into it. If we
1728 * get lucky, copy propagation will eliminate the extra moves.
1731 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1732 src_reg temp_base
= get_temp(ir
->type
);
1733 dst_reg temp
= dst_reg(temp_base
);
1735 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1736 int size
= type_size(field_value
->type
);
1740 field_value
->accept(this);
1743 for (i
= 0; i
< (unsigned int)size
; i
++) {
1744 emit(ir
, OPCODE_MOV
, temp
, src
);
1750 this->result
= temp_base
;
1754 if (ir
->type
->is_array()) {
1755 src_reg temp_base
= get_temp(ir
->type
);
1756 dst_reg temp
= dst_reg(temp_base
);
1757 int size
= type_size(ir
->type
->fields
.array
);
1761 for (i
= 0; i
< ir
->type
->length
; i
++) {
1762 ir
->array_elements
[i
]->accept(this);
1764 for (int j
= 0; j
< size
; j
++) {
1765 emit(ir
, OPCODE_MOV
, temp
, src
);
1771 this->result
= temp_base
;
1775 if (ir
->type
->is_matrix()) {
1776 src_reg mat
= get_temp(ir
->type
);
1777 dst_reg mat_column
= dst_reg(mat
);
1779 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1780 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1781 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1783 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1784 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1785 (gl_constant_value
*) values
,
1786 ir
->type
->vector_elements
,
1788 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1797 src
.file
= PROGRAM_CONSTANT
;
1798 switch (ir
->type
->base_type
) {
1799 case GLSL_TYPE_FLOAT
:
1800 values
= &ir
->value
.f
[0];
1802 case GLSL_TYPE_UINT
:
1803 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1804 values
[i
] = ir
->value
.u
[i
];
1808 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1809 values
[i
] = ir
->value
.i
[i
];
1812 case GLSL_TYPE_BOOL
:
1813 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1814 values
[i
] = ir
->value
.b
[i
];
1818 assert(!"Non-float/uint/int/bool constant");
1821 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1822 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1823 (gl_constant_value
*) values
,
1824 ir
->type
->vector_elements
,
1825 &this->result
.swizzle
);
1829 ir_to_mesa_visitor::visit(ir_call
*)
1831 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1835 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1837 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1838 dst_reg result_dst
, coord_dst
;
1839 ir_to_mesa_instruction
*inst
= NULL
;
1840 prog_opcode opcode
= OPCODE_NOP
;
1842 if (ir
->op
== ir_txs
)
1843 this->result
= src_reg_for_float(0.0);
1845 ir
->coordinate
->accept(this);
1847 /* Put our coords in a temp. We'll need to modify them for shadow,
1848 * projection, or LOD, so the only case we'd use it as is is if
1849 * we're doing plain old texturing. Mesa IR optimization should
1850 * handle cleaning up our mess in that case.
1852 coord
= get_temp(glsl_type::vec4_type
);
1853 coord_dst
= dst_reg(coord
);
1854 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1856 if (ir
->projector
) {
1857 ir
->projector
->accept(this);
1858 projector
= this->result
;
1861 /* Storage for our result. Ideally for an assignment we'd be using
1862 * the actual storage for the result here, instead.
1864 result_src
= get_temp(glsl_type::vec4_type
);
1865 result_dst
= dst_reg(result_src
);
1870 opcode
= OPCODE_TEX
;
1873 opcode
= OPCODE_TXB
;
1874 ir
->lod_info
.bias
->accept(this);
1875 lod_info
= this->result
;
1878 /* Pretend to be TXL so the sampler, coordinate, lod are available */
1880 opcode
= OPCODE_TXL
;
1881 ir
->lod_info
.lod
->accept(this);
1882 lod_info
= this->result
;
1885 opcode
= OPCODE_TXD
;
1886 ir
->lod_info
.grad
.dPdx
->accept(this);
1888 ir
->lod_info
.grad
.dPdy
->accept(this);
1892 assert(!"Unexpected ir_txf_ms opcode");
1895 assert(!"Unexpected ir_lod opcode");
1898 assert(!"Unexpected ir_tg4 opcode");
1900 case ir_query_levels
:
1901 assert(!"Unexpected ir_query_levels opcode");
1903 case ir_samples_identical
:
1904 unreachable("Unexpected ir_samples_identical opcode");
1905 case ir_texture_samples
:
1906 unreachable("Unexpected ir_texture_samples opcode");
1909 const glsl_type
*sampler_type
= ir
->sampler
->type
;
1911 if (ir
->projector
) {
1912 if (opcode
== OPCODE_TEX
) {
1913 /* Slot the projector in as the last component of the coord. */
1914 coord_dst
.writemask
= WRITEMASK_W
;
1915 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
1916 coord_dst
.writemask
= WRITEMASK_XYZW
;
1917 opcode
= OPCODE_TXP
;
1919 src_reg coord_w
= coord
;
1920 coord_w
.swizzle
= SWIZZLE_WWWW
;
1922 /* For the other TEX opcodes there's no projective version
1923 * since the last slot is taken up by lod info. Do the
1924 * projective divide now.
1926 coord_dst
.writemask
= WRITEMASK_W
;
1927 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
1929 /* In the case where we have to project the coordinates "by hand,"
1930 * the shadow comparitor value must also be projected.
1932 src_reg tmp_src
= coord
;
1933 if (ir
->shadow_comparitor
) {
1934 /* Slot the shadow value in as the second to last component of the
1937 ir
->shadow_comparitor
->accept(this);
1939 tmp_src
= get_temp(glsl_type::vec4_type
);
1940 dst_reg tmp_dst
= dst_reg(tmp_src
);
1942 /* Projective division not allowed for array samplers. */
1943 assert(!sampler_type
->sampler_array
);
1945 tmp_dst
.writemask
= WRITEMASK_Z
;
1946 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
1948 tmp_dst
.writemask
= WRITEMASK_XY
;
1949 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
1952 coord_dst
.writemask
= WRITEMASK_XYZ
;
1953 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
1955 coord_dst
.writemask
= WRITEMASK_XYZW
;
1956 coord
.swizzle
= SWIZZLE_XYZW
;
1960 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
1961 * comparitor was put in the correct place (and projected) by the code,
1962 * above, that handles by-hand projection.
1964 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
1965 /* Slot the shadow value in as the second to last component of the
1968 ir
->shadow_comparitor
->accept(this);
1970 /* XXX This will need to be updated for cubemap array samplers. */
1971 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
1972 sampler_type
->sampler_array
) {
1973 coord_dst
.writemask
= WRITEMASK_W
;
1975 coord_dst
.writemask
= WRITEMASK_Z
;
1978 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1979 coord_dst
.writemask
= WRITEMASK_XYZW
;
1982 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
1983 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
1984 coord_dst
.writemask
= WRITEMASK_W
;
1985 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
1986 coord_dst
.writemask
= WRITEMASK_XYZW
;
1989 if (opcode
== OPCODE_TXD
)
1990 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
1992 inst
= emit(ir
, opcode
, result_dst
, coord
);
1994 if (ir
->shadow_comparitor
)
1995 inst
->tex_shadow
= GL_TRUE
;
1997 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1998 this->shader_program
,
2001 switch (sampler_type
->sampler_dimensionality
) {
2002 case GLSL_SAMPLER_DIM_1D
:
2003 inst
->tex_target
= (sampler_type
->sampler_array
)
2004 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2006 case GLSL_SAMPLER_DIM_2D
:
2007 inst
->tex_target
= (sampler_type
->sampler_array
)
2008 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2010 case GLSL_SAMPLER_DIM_3D
:
2011 inst
->tex_target
= TEXTURE_3D_INDEX
;
2013 case GLSL_SAMPLER_DIM_CUBE
:
2014 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2016 case GLSL_SAMPLER_DIM_RECT
:
2017 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2019 case GLSL_SAMPLER_DIM_BUF
:
2020 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2022 case GLSL_SAMPLER_DIM_EXTERNAL
:
2023 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2026 assert(!"Should not get here.");
2029 this->result
= result_src
;
2033 ir_to_mesa_visitor::visit(ir_return
*ir
)
2035 /* Non-void functions should have been inlined. We may still emit RETs
2036 * from main() unless the EmitNoMainReturn option is set.
2038 assert(!ir
->get_value());
2039 emit(ir
, OPCODE_RET
);
2043 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2045 if (ir
->condition
) {
2046 ir
->condition
->accept(this);
2047 this->result
.negate
= ~this->result
.negate
;
2048 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2050 emit(ir
, OPCODE_KIL_NV
);
2055 ir_to_mesa_visitor::visit(ir_if
*ir
)
2057 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2058 ir_to_mesa_instruction
*prev_inst
;
2060 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2062 ir
->condition
->accept(this);
2063 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2065 if (this->options
->EmitCondCodes
) {
2066 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2068 /* See if we actually generated any instruction for generating
2069 * the condition. If not, then cook up a move to a temp so we
2070 * have something to set cond_update on.
2072 if (cond_inst
== prev_inst
) {
2073 src_reg temp
= get_temp(glsl_type::bool_type
);
2074 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2076 cond_inst
->cond_update
= GL_TRUE
;
2078 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2079 if_inst
->dst
.cond_mask
= COND_NE
;
2081 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2084 this->instructions
.push_tail(if_inst
);
2086 visit_exec_list(&ir
->then_instructions
, this);
2088 if (!ir
->else_instructions
.is_empty()) {
2089 emit(ir
->condition
, OPCODE_ELSE
);
2090 visit_exec_list(&ir
->else_instructions
, this);
2093 emit(ir
->condition
, OPCODE_ENDIF
);
2097 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2099 assert(!"Geometry shaders not supported.");
2103 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2105 assert(!"Geometry shaders not supported.");
2109 ir_to_mesa_visitor::visit(ir_barrier
*)
2111 unreachable("GLSL barrier() not supported.");
2114 ir_to_mesa_visitor::ir_to_mesa_visitor()
2116 result
.file
= PROGRAM_UNDEFINED
;
2118 next_signature_id
= 1;
2119 current_function
= NULL
;
2120 mem_ctx
= ralloc_context(NULL
);
2123 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2125 ralloc_free(mem_ctx
);
2128 static struct prog_src_register
2129 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2131 struct prog_src_register mesa_reg
;
2133 mesa_reg
.File
= reg
.file
;
2134 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2135 mesa_reg
.Index
= reg
.index
;
2136 mesa_reg
.Swizzle
= reg
.swizzle
;
2137 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2138 mesa_reg
.Negate
= reg
.negate
;
2140 mesa_reg
.HasIndex2
= GL_FALSE
;
2141 mesa_reg
.RelAddr2
= 0;
2142 mesa_reg
.Index2
= 0;
2148 set_branchtargets(ir_to_mesa_visitor
*v
,
2149 struct prog_instruction
*mesa_instructions
,
2150 int num_instructions
)
2152 int if_count
= 0, loop_count
= 0;
2153 int *if_stack
, *loop_stack
;
2154 int if_stack_pos
= 0, loop_stack_pos
= 0;
2157 for (i
= 0; i
< num_instructions
; i
++) {
2158 switch (mesa_instructions
[i
].Opcode
) {
2162 case OPCODE_BGNLOOP
:
2167 mesa_instructions
[i
].BranchTarget
= -1;
2174 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2175 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2177 for (i
= 0; i
< num_instructions
; i
++) {
2178 switch (mesa_instructions
[i
].Opcode
) {
2180 if_stack
[if_stack_pos
] = i
;
2184 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2185 if_stack
[if_stack_pos
- 1] = i
;
2188 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2191 case OPCODE_BGNLOOP
:
2192 loop_stack
[loop_stack_pos
] = i
;
2195 case OPCODE_ENDLOOP
:
2197 /* Rewrite any breaks/conts at this nesting level (haven't
2198 * already had a BranchTarget assigned) to point to the end
2201 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2202 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2203 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2204 if (mesa_instructions
[j
].BranchTarget
== -1) {
2205 mesa_instructions
[j
].BranchTarget
= i
;
2209 /* The loop ends point at each other. */
2210 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2211 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2214 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2215 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2216 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2228 print_program(struct prog_instruction
*mesa_instructions
,
2229 ir_instruction
**mesa_instruction_annotation
,
2230 int num_instructions
)
2232 ir_instruction
*last_ir
= NULL
;
2236 for (i
= 0; i
< num_instructions
; i
++) {
2237 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2238 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2240 fprintf(stdout
, "%3d: ", i
);
2242 if (last_ir
!= ir
&& ir
) {
2245 for (j
= 0; j
< indent
; j
++) {
2246 fprintf(stdout
, " ");
2252 fprintf(stdout
, " "); /* line number spacing. */
2255 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2256 PROG_PRINT_DEBUG
, NULL
);
2262 class add_uniform_to_shader
: public program_resource_visitor
{
2264 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2265 struct gl_program_parameter_list
*params
,
2266 gl_shader_stage shader_type
)
2267 : shader_program(shader_program
), params(params
), idx(-1),
2268 shader_type(shader_type
)
2273 void process(ir_variable
*var
)
2276 this->program_resource_visitor::process(var
);
2278 var
->data
.location
= this->idx
;
2282 virtual void visit_field(const glsl_type
*type
, const char *name
,
2285 struct gl_shader_program
*shader_program
;
2286 struct gl_program_parameter_list
*params
;
2288 gl_shader_stage shader_type
;
2291 } /* anonymous namespace */
2294 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2301 if (type
->is_vector() || type
->is_scalar()) {
2302 size
= type
->vector_elements
;
2303 if (type
->is_double())
2306 size
= type_size(type
) * 4;
2309 gl_register_file file
;
2310 if (type
->without_array()->is_sampler()) {
2311 file
= PROGRAM_SAMPLER
;
2313 file
= PROGRAM_UNIFORM
;
2316 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2318 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2321 /* Sampler uniform values are stored in prog->SamplerUnits,
2322 * and the entry in that array is selected by this index we
2323 * store in ParameterValues[].
2325 if (file
== PROGRAM_SAMPLER
) {
2328 this->shader_program
->UniformHash
->get(location
,
2329 params
->Parameters
[index
].Name
);
2335 struct gl_uniform_storage
*storage
=
2336 &this->shader_program
->UniformStorage
[location
];
2338 assert(storage
->type
->is_sampler() &&
2339 storage
->opaque
[shader_type
].active
);
2341 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2342 params
->ParameterValues
[index
+ j
][0].f
=
2343 storage
->opaque
[shader_type
].index
+ j
;
2347 /* The first part of the uniform that's processed determines the base
2348 * location of the whole uniform (for structures).
2355 * Generate the program parameters list for the user uniforms in a shader
2357 * \param shader_program Linked shader program. This is only used to
2358 * emit possible link errors to the info log.
2359 * \param sh Shader whose uniforms are to be processed.
2360 * \param params Parameter list to be filled in.
2363 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2365 struct gl_shader
*sh
,
2366 struct gl_program_parameter_list
2369 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2371 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2372 ir_variable
*var
= node
->as_variable();
2374 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2375 || var
->is_in_buffer_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2383 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2384 struct gl_shader_program
*shader_program
,
2385 struct gl_program_parameter_list
*params
)
2387 /* After adding each uniform to the parameter list, connect the storage for
2388 * the parameter with the tracking structure used by the API for the
2391 unsigned last_location
= unsigned(~0);
2392 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2393 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2398 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2404 struct gl_uniform_storage
*storage
=
2405 &shader_program
->UniformStorage
[location
];
2407 /* Do not associate any uniform storage to built-in uniforms */
2408 if (storage
->builtin
)
2411 if (location
!= last_location
) {
2412 enum gl_uniform_driver_format format
= uniform_native
;
2414 unsigned columns
= 0;
2415 int dmul
= 4 * sizeof(float);
2416 switch (storage
->type
->base_type
) {
2417 case GLSL_TYPE_UINT
:
2418 assert(ctx
->Const
.NativeIntegers
);
2419 format
= uniform_native
;
2424 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2428 case GLSL_TYPE_DOUBLE
:
2429 if (storage
->type
->vector_elements
> 2)
2432 case GLSL_TYPE_FLOAT
:
2433 format
= uniform_native
;
2434 columns
= storage
->type
->matrix_columns
;
2436 case GLSL_TYPE_BOOL
:
2437 format
= uniform_native
;
2440 case GLSL_TYPE_SAMPLER
:
2441 case GLSL_TYPE_IMAGE
:
2442 case GLSL_TYPE_SUBROUTINE
:
2443 format
= uniform_native
;
2446 case GLSL_TYPE_ATOMIC_UINT
:
2447 case GLSL_TYPE_ARRAY
:
2448 case GLSL_TYPE_VOID
:
2449 case GLSL_TYPE_STRUCT
:
2450 case GLSL_TYPE_ERROR
:
2451 case GLSL_TYPE_INTERFACE
:
2452 case GLSL_TYPE_FUNCTION
:
2453 assert(!"Should not get here.");
2457 _mesa_uniform_attach_driver_storage(storage
,
2461 ¶ms
->ParameterValues
[i
]);
2463 /* After attaching the driver's storage to the uniform, propagate any
2464 * data from the linker's backing store. This will cause values from
2465 * initializers in the source code to be copied over.
2467 _mesa_propagate_uniforms_to_driver_storage(storage
,
2469 MAX2(1, storage
->array_elements
));
2471 last_location
= location
;
2477 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2478 * channels for copy propagation and updates following instructions to
2479 * use the original versions.
2481 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2482 * will occur. As an example, a TXP production before this pass:
2484 * 0: MOV TEMP[1], INPUT[4].xyyy;
2485 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2486 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2490 * 0: MOV TEMP[1], INPUT[4].xyyy;
2491 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2492 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2494 * which allows for dead code elimination on TEMP[1]'s writes.
2497 ir_to_mesa_visitor::copy_propagate(void)
2499 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2500 ir_to_mesa_instruction
*,
2501 this->next_temp
* 4);
2502 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2505 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2506 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2507 || inst
->dst
.index
< this->next_temp
);
2509 /* First, do any copy propagation possible into the src regs. */
2510 for (int r
= 0; r
< 3; r
++) {
2511 ir_to_mesa_instruction
*first
= NULL
;
2513 int acp_base
= inst
->src
[r
].index
* 4;
2515 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2516 inst
->src
[r
].reladdr
)
2519 /* See if we can find entries in the ACP consisting of MOVs
2520 * from the same src register for all the swizzled channels
2521 * of this src register reference.
2523 for (int i
= 0; i
< 4; i
++) {
2524 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2525 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2532 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2537 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2538 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2546 /* We've now validated that we can copy-propagate to
2547 * replace this src register reference. Do it.
2549 inst
->src
[r
].file
= first
->src
[0].file
;
2550 inst
->src
[r
].index
= first
->src
[0].index
;
2553 for (int i
= 0; i
< 4; i
++) {
2554 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2555 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2556 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2559 inst
->src
[r
].swizzle
= swizzle
;
2564 case OPCODE_BGNLOOP
:
2565 case OPCODE_ENDLOOP
:
2566 /* End of a basic block, clear the ACP entirely. */
2567 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2576 /* Clear all channels written inside the block from the ACP, but
2577 * leaving those that were not touched.
2579 for (int r
= 0; r
< this->next_temp
; r
++) {
2580 for (int c
= 0; c
< 4; c
++) {
2581 if (!acp
[4 * r
+ c
])
2584 if (acp_level
[4 * r
+ c
] >= level
)
2585 acp
[4 * r
+ c
] = NULL
;
2588 if (inst
->op
== OPCODE_ENDIF
)
2593 /* Continuing the block, clear any written channels from
2596 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2597 /* Any temporary might be written, so no copy propagation
2598 * across this instruction.
2600 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2601 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2602 inst
->dst
.reladdr
) {
2603 /* Any output might be written, so no copy propagation
2604 * from outputs across this instruction.
2606 for (int r
= 0; r
< this->next_temp
; r
++) {
2607 for (int c
= 0; c
< 4; c
++) {
2608 if (!acp
[4 * r
+ c
])
2611 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2612 acp
[4 * r
+ c
] = NULL
;
2615 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2616 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2617 /* Clear where it's used as dst. */
2618 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2619 for (int c
= 0; c
< 4; c
++) {
2620 if (inst
->dst
.writemask
& (1 << c
)) {
2621 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2626 /* Clear where it's used as src. */
2627 for (int r
= 0; r
< this->next_temp
; r
++) {
2628 for (int c
= 0; c
< 4; c
++) {
2629 if (!acp
[4 * r
+ c
])
2632 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2634 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2635 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2636 inst
->dst
.writemask
& (1 << src_chan
))
2638 acp
[4 * r
+ c
] = NULL
;
2646 /* If this is a copy, add it to the ACP. */
2647 if (inst
->op
== OPCODE_MOV
&&
2648 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2649 !(inst
->dst
.file
== inst
->src
[0].file
&&
2650 inst
->dst
.index
== inst
->src
[0].index
) &&
2651 !inst
->dst
.reladdr
&&
2653 !inst
->src
[0].reladdr
&&
2654 !inst
->src
[0].negate
) {
2655 for (int i
= 0; i
< 4; i
++) {
2656 if (inst
->dst
.writemask
& (1 << i
)) {
2657 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2658 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2664 ralloc_free(acp_level
);
2670 * Convert a shader's GLSL IR into a Mesa gl_program.
2672 static struct gl_program
*
2673 get_mesa_program(struct gl_context
*ctx
,
2674 struct gl_shader_program
*shader_program
,
2675 struct gl_shader
*shader
)
2677 ir_to_mesa_visitor v
;
2678 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2679 ir_instruction
**mesa_instruction_annotation
;
2681 struct gl_program
*prog
;
2682 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2683 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2684 struct gl_shader_compiler_options
*options
=
2685 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2687 validate_ir_tree(shader
->ir
);
2689 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2692 prog
->Parameters
= _mesa_new_parameter_list();
2695 v
.shader_program
= shader_program
;
2696 v
.options
= options
;
2698 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2701 /* Emit Mesa IR for main(). */
2702 visit_exec_list(shader
->ir
, &v
);
2703 v
.emit(NULL
, OPCODE_END
);
2705 prog
->NumTemporaries
= v
.next_temp
;
2707 unsigned num_instructions
= v
.instructions
.length();
2710 (struct prog_instruction
*)calloc(num_instructions
,
2711 sizeof(*mesa_instructions
));
2712 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2717 /* Convert ir_mesa_instructions into prog_instructions.
2719 mesa_inst
= mesa_instructions
;
2721 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2722 mesa_inst
->Opcode
= inst
->op
;
2723 mesa_inst
->CondUpdate
= inst
->cond_update
;
2725 mesa_inst
->Saturate
= GL_TRUE
;
2726 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2727 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2728 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2729 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2730 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2731 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2732 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2733 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2734 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2735 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2736 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2737 mesa_instruction_annotation
[i
] = inst
->ir
;
2739 /* Set IndirectRegisterFiles. */
2740 if (mesa_inst
->DstReg
.RelAddr
)
2741 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2743 /* Update program's bitmask of indirectly accessed register files */
2744 for (unsigned src
= 0; src
< 3; src
++)
2745 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2746 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2748 switch (mesa_inst
->Opcode
) {
2750 if (options
->MaxIfDepth
== 0) {
2751 linker_warning(shader_program
,
2752 "Couldn't flatten if-statement. "
2753 "This will likely result in software "
2754 "rasterization.\n");
2757 case OPCODE_BGNLOOP
:
2758 if (options
->EmitNoLoops
) {
2759 linker_warning(shader_program
,
2760 "Couldn't unroll loop. "
2761 "This will likely result in software "
2762 "rasterization.\n");
2766 if (options
->EmitNoCont
) {
2767 linker_warning(shader_program
,
2768 "Couldn't lower continue-statement. "
2769 "This will likely result in software "
2770 "rasterization.\n");
2774 prog
->NumAddressRegs
= 1;
2783 if (!shader_program
->LinkStatus
)
2787 if (!shader_program
->LinkStatus
) {
2791 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2793 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2794 fprintf(stderr
, "\n");
2795 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2796 shader_program
->Name
);
2797 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2798 fprintf(stderr
, "\n");
2799 fprintf(stderr
, "\n");
2800 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2801 shader_program
->Name
);
2802 print_program(mesa_instructions
, mesa_instruction_annotation
,
2807 prog
->Instructions
= mesa_instructions
;
2808 prog
->NumInstructions
= num_instructions
;
2810 /* Setting this to NULL prevents a possible double free in the fail_exit
2813 mesa_instructions
= NULL
;
2815 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2817 prog
->SamplersUsed
= shader
->active_samplers
;
2818 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2819 _mesa_update_shader_textures_used(shader_program
, prog
);
2821 /* Set the gl_FragDepth layout. */
2822 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2823 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2824 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2827 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2829 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2830 _mesa_optimize_program(ctx
, prog
);
2833 /* This has to be done last. Any operation that can cause
2834 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2835 * program constant) has to happen before creating this linkage.
2837 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2838 if (!shader_program
->LinkStatus
) {
2845 free(mesa_instructions
);
2846 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2854 * Called via ctx->Driver.LinkShader()
2855 * This actually involves converting GLSL IR into Mesa gl_programs with
2856 * code lowering and other optimizations.
2859 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2861 assert(prog
->LinkStatus
);
2863 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2864 if (prog
->_LinkedShaders
[i
] == NULL
)
2868 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2869 const struct gl_shader_compiler_options
*options
=
2870 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2876 do_mat_op_to_vec(ir
);
2877 lower_instructions(ir
, (MOD_TO_FLOOR
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2878 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2879 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2881 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2883 progress
= do_common_optimization(ir
, true, true,
2884 options
, ctx
->Const
.NativeIntegers
)
2887 progress
= lower_quadop_vector(ir
, true) || progress
;
2889 if (options
->MaxIfDepth
== 0)
2890 progress
= lower_discard(ir
) || progress
;
2892 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
2894 if (options
->EmitNoNoise
)
2895 progress
= lower_noise(ir
) || progress
;
2897 /* If there are forms of indirect addressing that the driver
2898 * cannot handle, perform the lowering pass.
2900 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
2901 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
2903 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
2904 options
->EmitNoIndirectInput
,
2905 options
->EmitNoIndirectOutput
,
2906 options
->EmitNoIndirectTemp
,
2907 options
->EmitNoIndirectUniform
)
2910 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
2911 progress
= lower_vector_insert(ir
, true) || progress
;
2914 validate_ir_tree(ir
);
2917 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2918 struct gl_program
*linked_prog
;
2920 if (prog
->_LinkedShaders
[i
] == NULL
)
2923 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
2926 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
2928 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
2930 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
2931 _mesa_shader_stage_to_program(i
),
2937 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
2940 return prog
->LinkStatus
;
2944 * Link a GLSL shader program. Called via glLinkProgram().
2947 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2951 _mesa_clear_shader_program_data(prog
);
2953 prog
->LinkStatus
= GL_TRUE
;
2955 for (i
= 0; i
< prog
->NumShaders
; i
++) {
2956 if (!prog
->Shaders
[i
]->CompileStatus
) {
2957 linker_error(prog
, "linking with uncompiled shader");
2961 if (prog
->LinkStatus
) {
2962 link_shaders(ctx
, prog
);
2965 if (prog
->LinkStatus
) {
2966 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
2967 prog
->LinkStatus
= GL_FALSE
;
2969 build_program_resource_list(prog
);
2973 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2974 if (!prog
->LinkStatus
) {
2975 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
2978 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
2979 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
2980 fprintf(stderr
, "%s\n", prog
->InfoLog
);