2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderobj.h"
47 #include "program/hash_table.h"
50 #include "main/shaderapi.h"
51 #include "main/uniforms.h"
52 #include "program/prog_instruction.h"
53 #include "program/prog_optimize.h"
54 #include "program/prog_print.h"
55 #include "program/program.h"
56 #include "program/prog_parameter.h"
57 #include "program/sampler.h"
63 static int swizzle_for_size(int size
);
66 * This struct is a corresponding struct to Mesa prog_src_register, with
71 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
85 this->file
= PROGRAM_UNDEFINED
;
92 explicit src_reg(dst_reg reg
);
94 gl_register_file file
; /**< PROGRAM_* from Mesa */
95 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
96 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
97 int negate
; /**< NEGATE_XYZW mask from mesa */
98 /** Register index should be offset by the integer in this reg. */
104 dst_reg(gl_register_file file
, int writemask
)
108 this->writemask
= writemask
;
109 this->cond_mask
= COND_TR
;
110 this->reladdr
= NULL
;
115 this->file
= PROGRAM_UNDEFINED
;
118 this->cond_mask
= COND_TR
;
119 this->reladdr
= NULL
;
122 explicit dst_reg(src_reg reg
);
124 gl_register_file file
; /**< PROGRAM_* from Mesa */
125 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
126 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
128 /** Register index should be offset by the integer in this reg. */
132 src_reg::src_reg(dst_reg reg
)
134 this->file
= reg
.file
;
135 this->index
= reg
.index
;
136 this->swizzle
= SWIZZLE_XYZW
;
138 this->reladdr
= reg
.reladdr
;
141 dst_reg::dst_reg(src_reg reg
)
143 this->file
= reg
.file
;
144 this->index
= reg
.index
;
145 this->writemask
= WRITEMASK_XYZW
;
146 this->cond_mask
= COND_TR
;
147 this->reladdr
= reg
.reladdr
;
150 class ir_to_mesa_instruction
: public exec_node
{
152 /* Callers of this ralloc-based new need not call delete. It's
153 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
154 static void* operator new(size_t size
, void *ctx
)
158 node
= rzalloc_size(ctx
, size
);
159 assert(node
!= NULL
);
167 /** Pointer to the ir source this tree came from for debugging */
169 GLboolean cond_update
;
171 int sampler
; /**< sampler index */
172 int tex_target
; /**< One of TEXTURE_*_INDEX */
173 GLboolean tex_shadow
;
176 class variable_storage
: public exec_node
{
178 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
179 : file(file
), index(index
), var(var
)
184 gl_register_file file
;
186 ir_variable
*var
; /* variable that maps to this, if any */
189 class function_entry
: public exec_node
{
191 ir_function_signature
*sig
;
194 * identifier of this function signature used by the program.
196 * At the point that Mesa instructions for function calls are
197 * generated, we don't know the address of the first instruction of
198 * the function body. So we make the BranchTarget that is called a
199 * small integer and rewrite them during set_branchtargets().
204 * Pointer to first instruction of the function body.
206 * Set during function body emits after main() is processed.
208 ir_to_mesa_instruction
*bgn_inst
;
211 * Index of the first instruction of the function body in actual
214 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
218 /** Storage for the return value. */
222 class ir_to_mesa_visitor
: public ir_visitor
{
224 ir_to_mesa_visitor();
225 ~ir_to_mesa_visitor();
227 function_entry
*current_function
;
229 struct gl_context
*ctx
;
230 struct gl_program
*prog
;
231 struct gl_shader_program
*shader_program
;
232 struct gl_shader_compiler_options
*options
;
236 variable_storage
*find_variable_storage(ir_variable
*var
);
238 src_reg
get_temp(const glsl_type
*type
);
239 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
241 src_reg
src_reg_for_float(float val
);
244 * \name Visit methods
246 * As typical for the visitor pattern, there must be one \c visit method for
247 * each concrete subclass of \c ir_instruction. Virtual base classes within
248 * the hierarchy should not have \c visit methods.
251 virtual void visit(ir_variable
*);
252 virtual void visit(ir_loop
*);
253 virtual void visit(ir_loop_jump
*);
254 virtual void visit(ir_function_signature
*);
255 virtual void visit(ir_function
*);
256 virtual void visit(ir_expression
*);
257 virtual void visit(ir_swizzle
*);
258 virtual void visit(ir_dereference_variable
*);
259 virtual void visit(ir_dereference_array
*);
260 virtual void visit(ir_dereference_record
*);
261 virtual void visit(ir_assignment
*);
262 virtual void visit(ir_constant
*);
263 virtual void visit(ir_call
*);
264 virtual void visit(ir_return
*);
265 virtual void visit(ir_discard
*);
266 virtual void visit(ir_texture
*);
267 virtual void visit(ir_if
*);
268 virtual void visit(ir_emit_vertex
*);
269 virtual void visit(ir_end_primitive
*);
274 /** List of variable_storage */
277 /** List of function_entry */
278 exec_list function_signatures
;
279 int next_signature_id
;
281 /** List of ir_to_mesa_instruction */
282 exec_list instructions
;
284 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
286 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
287 dst_reg dst
, src_reg src0
);
289 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
290 dst_reg dst
, src_reg src0
, src_reg src1
);
292 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
294 src_reg src0
, src_reg src1
, src_reg src2
);
297 * Emit the correct dot-product instruction for the type of arguments
299 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
305 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
306 dst_reg dst
, src_reg src0
);
308 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
309 dst_reg dst
, src_reg src0
, src_reg src1
);
311 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
312 dst_reg dst
, const src_reg
&src
);
314 bool try_emit_mad(ir_expression
*ir
,
316 bool try_emit_mad_for_and_not(ir_expression
*ir
,
318 bool try_emit_sat(ir_expression
*ir
);
320 void emit_swz(ir_expression
*ir
);
322 bool process_move_condition(ir_rvalue
*ir
);
324 void copy_propagate(void);
329 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
331 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
333 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
336 swizzle_for_size(int size
)
338 static const int size_swizzles
[4] = {
339 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
340 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
341 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
342 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
345 assert((size
>= 1) && (size
<= 4));
346 return size_swizzles
[size
- 1];
349 ir_to_mesa_instruction
*
350 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
352 src_reg src0
, src_reg src1
, src_reg src2
)
354 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
357 /* If we have to do relative addressing, we want to load the ARL
358 * reg directly for one of the regs, and preload the other reladdr
359 * sources into temps.
361 num_reladdr
+= dst
.reladdr
!= NULL
;
362 num_reladdr
+= src0
.reladdr
!= NULL
;
363 num_reladdr
+= src1
.reladdr
!= NULL
;
364 num_reladdr
+= src2
.reladdr
!= NULL
;
366 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
367 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
368 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
371 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
374 assert(num_reladdr
== 0);
383 this->instructions
.push_tail(inst
);
389 ir_to_mesa_instruction
*
390 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
391 dst_reg dst
, src_reg src0
, src_reg src1
)
393 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
396 ir_to_mesa_instruction
*
397 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
398 dst_reg dst
, src_reg src0
)
400 assert(dst
.writemask
!= 0);
401 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
404 ir_to_mesa_instruction
*
405 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
407 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
410 ir_to_mesa_instruction
*
411 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
412 dst_reg dst
, src_reg src0
, src_reg src1
,
415 static const gl_inst_opcode dot_opcodes
[] = {
416 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
419 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
423 * Emits Mesa scalar opcodes to produce unique answers across channels.
425 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
426 * channel determines the result across all channels. So to do a vec4
427 * of this operation, we want to emit a scalar per source channel used
428 * to produce dest channels.
431 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
433 src_reg orig_src0
, src_reg orig_src1
)
436 int done_mask
= ~dst
.writemask
;
438 /* Mesa RCP is a scalar operation splatting results to all channels,
439 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
442 for (i
= 0; i
< 4; i
++) {
443 GLuint this_mask
= (1 << i
);
444 ir_to_mesa_instruction
*inst
;
445 src_reg src0
= orig_src0
;
446 src_reg src1
= orig_src1
;
448 if (done_mask
& this_mask
)
451 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
452 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
453 for (j
= i
+ 1; j
< 4; j
++) {
454 /* If there is another enabled component in the destination that is
455 * derived from the same inputs, generate its value on this pass as
458 if (!(done_mask
& (1 << j
)) &&
459 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
460 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
461 this_mask
|= (1 << j
);
464 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
465 src0_swiz
, src0_swiz
);
466 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
467 src1_swiz
, src1_swiz
);
469 inst
= emit(ir
, op
, dst
, src0
, src1
);
470 inst
->dst
.writemask
= this_mask
;
471 done_mask
|= this_mask
;
476 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
477 dst_reg dst
, src_reg src0
)
479 src_reg undef
= undef_src
;
481 undef
.swizzle
= SWIZZLE_XXXX
;
483 emit_scalar(ir
, op
, dst
, src0
, undef
);
487 * Emit an OPCODE_SCS instruction
489 * The \c SCS opcode functions a bit differently than the other Mesa (or
490 * ARB_fragment_program) opcodes. Instead of splatting its result across all
491 * four components of the destination, it writes one value to the \c x
492 * component and another value to the \c y component.
494 * \param ir IR instruction being processed
495 * \param op Either \c OPCODE_SIN or \c OPCODE_COS depending on which
497 * \param dst Destination register
498 * \param src Source register
501 ir_to_mesa_visitor::emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
505 /* Vertex programs cannot use the SCS opcode.
507 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
) {
508 emit_scalar(ir
, op
, dst
, src
);
512 const unsigned component
= (op
== OPCODE_SIN
) ? 0 : 1;
513 const unsigned scs_mask
= (1U << component
);
514 int done_mask
= ~dst
.writemask
;
517 assert(op
== OPCODE_SIN
|| op
== OPCODE_COS
);
519 /* If there are compnents in the destination that differ from the component
520 * that will be written by the SCS instrution, we'll need a temporary.
522 if (scs_mask
!= unsigned(dst
.writemask
)) {
523 tmp
= get_temp(glsl_type::vec4_type
);
526 for (unsigned i
= 0; i
< 4; i
++) {
527 unsigned this_mask
= (1U << i
);
530 if ((done_mask
& this_mask
) != 0)
533 /* The source swizzle specified which component of the source generates
534 * sine / cosine for the current component in the destination. The SCS
535 * instruction requires that this value be swizzle to the X component.
536 * Replace the current swizzle with a swizzle that puts the source in
539 unsigned src0_swiz
= GET_SWZ(src
.swizzle
, i
);
541 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
542 src0_swiz
, src0_swiz
);
543 for (unsigned j
= i
+ 1; j
< 4; j
++) {
544 /* If there is another enabled component in the destination that is
545 * derived from the same inputs, generate its value on this pass as
548 if (!(done_mask
& (1 << j
)) &&
549 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
) {
550 this_mask
|= (1 << j
);
554 if (this_mask
!= scs_mask
) {
555 ir_to_mesa_instruction
*inst
;
556 dst_reg tmp_dst
= dst_reg(tmp
);
558 /* Emit the SCS instruction.
560 inst
= emit(ir
, OPCODE_SCS
, tmp_dst
, src0
);
561 inst
->dst
.writemask
= scs_mask
;
563 /* Move the result of the SCS instruction to the desired location in
566 tmp
.swizzle
= MAKE_SWIZZLE4(component
, component
,
567 component
, component
);
568 inst
= emit(ir
, OPCODE_SCS
, dst
, tmp
);
569 inst
->dst
.writemask
= this_mask
;
571 /* Emit the SCS instruction to write directly to the destination.
573 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_SCS
, dst
, src0
);
574 inst
->dst
.writemask
= scs_mask
;
577 done_mask
|= this_mask
;
582 ir_to_mesa_visitor::src_reg_for_float(float val
)
584 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
586 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
587 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
593 type_size(const struct glsl_type
*type
)
598 switch (type
->base_type
) {
601 case GLSL_TYPE_FLOAT
:
603 if (type
->is_matrix()) {
604 return type
->matrix_columns
;
606 /* Regardless of size of vector, it gets a vec4. This is bad
607 * packing for things like floats, but otherwise arrays become a
608 * mess. Hopefully a later pass over the code can pack scalars
609 * down if appropriate.
613 case GLSL_TYPE_ARRAY
:
614 assert(type
->length
> 0);
615 return type_size(type
->fields
.array
) * type
->length
;
616 case GLSL_TYPE_STRUCT
:
618 for (i
= 0; i
< type
->length
; i
++) {
619 size
+= type_size(type
->fields
.structure
[i
].type
);
622 case GLSL_TYPE_SAMPLER
:
623 /* Samplers take up one slot in UNIFORMS[], but they're baked in
628 case GLSL_TYPE_ERROR
:
629 case GLSL_TYPE_INTERFACE
:
630 assert(!"Invalid type in type_size");
638 * In the initial pass of codegen, we assign temporary numbers to
639 * intermediate results. (not SSA -- variable assignments will reuse
640 * storage). Actual register allocation for the Mesa VM occurs in a
641 * pass over the Mesa IR later.
644 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
648 src
.file
= PROGRAM_TEMPORARY
;
649 src
.index
= next_temp
;
651 next_temp
+= type_size(type
);
653 if (type
->is_array() || type
->is_record()) {
654 src
.swizzle
= SWIZZLE_NOOP
;
656 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
664 ir_to_mesa_visitor::find_variable_storage(ir_variable
*var
)
667 variable_storage
*entry
;
669 foreach_iter(exec_list_iterator
, iter
, this->variables
) {
670 entry
= (variable_storage
*)iter
.get();
672 if (entry
->var
== var
)
680 ir_to_mesa_visitor::visit(ir_variable
*ir
)
682 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
683 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
685 fp
->OriginUpperLeft
= ir
->origin_upper_left
;
686 fp
->PixelCenterInteger
= ir
->pixel_center_integer
;
689 if (ir
->mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
691 const ir_state_slot
*const slots
= ir
->state_slots
;
692 assert(ir
->state_slots
!= NULL
);
694 /* Check if this statevar's setup in the STATE file exactly
695 * matches how we'll want to reference it as a
696 * struct/array/whatever. If not, then we need to move it into
697 * temporary storage and hope that it'll get copy-propagated
700 for (i
= 0; i
< ir
->num_state_slots
; i
++) {
701 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
706 variable_storage
*storage
;
708 if (i
== ir
->num_state_slots
) {
709 /* We'll set the index later. */
710 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
711 this->variables
.push_tail(storage
);
715 /* The variable_storage constructor allocates slots based on the size
716 * of the type. However, this had better match the number of state
717 * elements that we're going to copy into the new temporary.
719 assert((int) ir
->num_state_slots
== type_size(ir
->type
));
721 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
723 this->variables
.push_tail(storage
);
724 this->next_temp
+= type_size(ir
->type
);
726 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
730 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
731 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
732 (gl_state_index
*)slots
[i
].tokens
);
734 if (storage
->file
== PROGRAM_STATE_VAR
) {
735 if (storage
->index
== -1) {
736 storage
->index
= index
;
738 assert(index
== storage
->index
+ (int)i
);
741 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
742 src
.swizzle
= slots
[i
].swizzle
;
743 emit(ir
, OPCODE_MOV
, dst
, src
);
744 /* even a float takes up a whole vec4 reg in a struct/array. */
749 if (storage
->file
== PROGRAM_TEMPORARY
&&
750 dst
.index
!= storage
->index
+ (int) ir
->num_state_slots
) {
751 linker_error(this->shader_program
,
752 "failed to load builtin uniform `%s' "
753 "(%d/%d regs loaded)\n",
754 ir
->name
, dst
.index
- storage
->index
,
755 type_size(ir
->type
));
761 ir_to_mesa_visitor::visit(ir_loop
*ir
)
763 ir_dereference_variable
*counter
= NULL
;
765 if (ir
->counter
!= NULL
)
766 counter
= new(mem_ctx
) ir_dereference_variable(ir
->counter
);
768 if (ir
->from
!= NULL
) {
769 assert(ir
->counter
!= NULL
);
772 new(mem_ctx
) ir_assignment(counter
, ir
->from
, NULL
);
777 emit(NULL
, OPCODE_BGNLOOP
);
781 new(mem_ctx
) ir_expression(ir
->cmp
, glsl_type::bool_type
,
783 ir_if
*if_stmt
= new(mem_ctx
) ir_if(e
);
786 new(mem_ctx
) ir_loop_jump(ir_loop_jump::jump_break
);
788 if_stmt
->then_instructions
.push_tail(brk
);
790 if_stmt
->accept(this);
793 visit_exec_list(&ir
->body_instructions
, this);
797 new(mem_ctx
) ir_expression(ir_binop_add
, counter
->type
,
798 counter
, ir
->increment
);
801 new(mem_ctx
) ir_assignment(counter
, e
, NULL
);
806 emit(NULL
, OPCODE_ENDLOOP
);
810 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
813 case ir_loop_jump::jump_break
:
814 emit(NULL
, OPCODE_BRK
);
816 case ir_loop_jump::jump_continue
:
817 emit(NULL
, OPCODE_CONT
);
824 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
831 ir_to_mesa_visitor::visit(ir_function
*ir
)
833 /* Ignore function bodies other than main() -- we shouldn't see calls to
834 * them since they should all be inlined before we get to ir_to_mesa.
836 if (strcmp(ir
->name
, "main") == 0) {
837 const ir_function_signature
*sig
;
840 sig
= ir
->matching_signature(NULL
, &empty
);
844 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
845 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
853 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
855 int nonmul_operand
= 1 - mul_operand
;
858 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
859 if (!expr
|| expr
->operation
!= ir_binop_mul
)
862 expr
->operands
[0]->accept(this);
864 expr
->operands
[1]->accept(this);
866 ir
->operands
[nonmul_operand
]->accept(this);
869 this->result
= get_temp(ir
->type
);
870 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
876 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
878 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
879 * implemented using multiplication, and logical-or is implemented using
880 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
881 * As result, the logical expression (a & !b) can be rewritten as:
885 * - (a * 1) - (a * b)
889 * This final expression can be implemented as a single MAD(a, -b, a)
893 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
895 const int other_operand
= 1 - try_operand
;
898 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
899 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
902 ir
->operands
[other_operand
]->accept(this);
904 expr
->operands
[0]->accept(this);
907 b
.negate
= ~b
.negate
;
909 this->result
= get_temp(ir
->type
);
910 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
916 ir_to_mesa_visitor::try_emit_sat(ir_expression
*ir
)
918 /* Saturates were only introduced to vertex programs in
919 * NV_vertex_program3, so don't give them to drivers in the VP.
921 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
)
924 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
928 sat_src
->accept(this);
929 src_reg src
= this->result
;
931 /* If we generated an expression instruction into a temporary in
932 * processing the saturate's operand, apply the saturate to that
933 * instruction. Otherwise, generate a MOV to do the saturate.
935 * Note that we have to be careful to only do this optimization if
936 * the instruction in question was what generated src->result. For
937 * example, ir_dereference_array might generate a MUL instruction
938 * to create the reladdr, and return us a src reg using that
939 * reladdr. That MUL result is not the value we're trying to
942 ir_expression
*sat_src_expr
= sat_src
->as_expression();
943 ir_to_mesa_instruction
*new_inst
;
944 new_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
945 if (sat_src_expr
&& (sat_src_expr
->operation
== ir_binop_mul
||
946 sat_src_expr
->operation
== ir_binop_add
||
947 sat_src_expr
->operation
== ir_binop_dot
)) {
948 new_inst
->saturate
= true;
950 this->result
= get_temp(ir
->type
);
951 ir_to_mesa_instruction
*inst
;
952 inst
= emit(ir
, OPCODE_MOV
, dst_reg(this->result
), src
);
953 inst
->saturate
= true;
960 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
961 src_reg
*reg
, int *num_reladdr
)
966 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
968 if (*num_reladdr
!= 1) {
969 src_reg temp
= get_temp(glsl_type::vec4_type
);
971 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
979 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
981 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
982 * This means that each of the operands is either an immediate value of -1,
983 * 0, or 1, or is a component from one source register (possibly with
986 uint8_t components
[4] = { 0 };
987 bool negate
[4] = { false };
988 ir_variable
*var
= NULL
;
990 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
991 ir_rvalue
*op
= ir
->operands
[i
];
993 assert(op
->type
->is_scalar());
996 switch (op
->ir_type
) {
997 case ir_type_constant
: {
999 assert(op
->type
->is_scalar());
1001 const ir_constant
*const c
= op
->as_constant();
1003 components
[i
] = SWIZZLE_ONE
;
1004 } else if (c
->is_zero()) {
1005 components
[i
] = SWIZZLE_ZERO
;
1006 } else if (c
->is_negative_one()) {
1007 components
[i
] = SWIZZLE_ONE
;
1010 assert(!"SWZ constant must be 0.0 or 1.0.");
1017 case ir_type_dereference_variable
: {
1018 ir_dereference_variable
*const deref
=
1019 (ir_dereference_variable
*) op
;
1021 assert((var
== NULL
) || (deref
->var
== var
));
1022 components
[i
] = SWIZZLE_X
;
1028 case ir_type_expression
: {
1029 ir_expression
*const expr
= (ir_expression
*) op
;
1031 assert(expr
->operation
== ir_unop_neg
);
1034 op
= expr
->operands
[0];
1038 case ir_type_swizzle
: {
1039 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
1041 components
[i
] = swiz
->mask
.x
;
1047 assert(!"Should not get here.");
1053 assert(var
!= NULL
);
1055 ir_dereference_variable
*const deref
=
1056 new(mem_ctx
) ir_dereference_variable(var
);
1058 this->result
.file
= PROGRAM_UNDEFINED
;
1059 deref
->accept(this);
1060 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1061 printf("Failed to get tree for expression operand:\n");
1070 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
1074 src
.negate
= ((unsigned(negate
[0]) << 0)
1075 | (unsigned(negate
[1]) << 1)
1076 | (unsigned(negate
[2]) << 2)
1077 | (unsigned(negate
[3]) << 3));
1079 /* Storage for our result. Ideally for an assignment we'd be using the
1080 * actual storage for the result here, instead.
1082 const src_reg result_src
= get_temp(ir
->type
);
1083 dst_reg result_dst
= dst_reg(result_src
);
1085 /* Limit writes to the channels that will be used by result_src later.
1086 * This does limit this temp's use as a temporary for multi-instruction
1089 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1091 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
1092 this->result
= result_src
;
1096 ir_to_mesa_visitor::visit(ir_expression
*ir
)
1098 unsigned int operand
;
1099 src_reg op
[Elements(ir
->operands
)];
1103 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
1105 if (ir
->operation
== ir_binop_add
) {
1106 if (try_emit_mad(ir
, 1))
1108 if (try_emit_mad(ir
, 0))
1112 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1114 if (ir
->operation
== ir_binop_logic_and
) {
1115 if (try_emit_mad_for_and_not(ir
, 1))
1117 if (try_emit_mad_for_and_not(ir
, 0))
1121 if (try_emit_sat(ir
))
1124 if (ir
->operation
== ir_quadop_vector
) {
1129 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1130 this->result
.file
= PROGRAM_UNDEFINED
;
1131 ir
->operands
[operand
]->accept(this);
1132 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1133 printf("Failed to get tree for expression operand:\n");
1134 ir
->operands
[operand
]->print();
1138 op
[operand
] = this->result
;
1140 /* Matrix expression operands should have been broken down to vector
1141 * operations already.
1143 assert(!ir
->operands
[operand
]->type
->is_matrix());
1146 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1147 if (ir
->operands
[1]) {
1148 vector_elements
= MAX2(vector_elements
,
1149 ir
->operands
[1]->type
->vector_elements
);
1152 this->result
.file
= PROGRAM_UNDEFINED
;
1154 /* Storage for our result. Ideally for an assignment we'd be using
1155 * the actual storage for the result here, instead.
1157 result_src
= get_temp(ir
->type
);
1158 /* convenience for the emit functions below. */
1159 result_dst
= dst_reg(result_src
);
1160 /* Limit writes to the channels that will be used by result_src later.
1161 * This does limit this temp's use as a temporary for multi-instruction
1164 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1166 switch (ir
->operation
) {
1167 case ir_unop_logic_not
:
1168 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1169 * older GPUs implement SEQ using multiple instructions (i915 uses two
1170 * SGE instructions and a MUL instruction). Since our logic values are
1171 * 0.0 and 1.0, 1-x also implements !x.
1173 op
[0].negate
= ~op
[0].negate
;
1174 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1177 op
[0].negate
= ~op
[0].negate
;
1181 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1184 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1187 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1191 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1195 assert(!"not reached: should be handled by ir_explog_to_explog2");
1198 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1201 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1204 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1206 case ir_unop_sin_reduced
:
1207 emit_scs(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1209 case ir_unop_cos_reduced
:
1210 emit_scs(ir
, OPCODE_COS
, result_dst
, op
[0]);
1214 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1217 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1220 case ir_unop_noise
: {
1221 const enum prog_opcode opcode
=
1222 prog_opcode(OPCODE_NOISE1
1223 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1224 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1226 emit(ir
, opcode
, result_dst
, op
[0]);
1231 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1234 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1238 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1241 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1244 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1245 assert(ir
->type
->is_integer());
1246 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1250 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1252 case ir_binop_greater
:
1253 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1255 case ir_binop_lequal
:
1256 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1258 case ir_binop_gequal
:
1259 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1261 case ir_binop_equal
:
1262 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1264 case ir_binop_nequal
:
1265 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1267 case ir_binop_all_equal
:
1268 /* "==" operator producing a scalar boolean. */
1269 if (ir
->operands
[0]->type
->is_vector() ||
1270 ir
->operands
[1]->type
->is_vector()) {
1271 src_reg temp
= get_temp(glsl_type::vec4_type
);
1272 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1274 /* After the dot-product, the value will be an integer on the
1275 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1277 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1279 /* Negating the result of the dot-product gives values on the range
1280 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1281 * achieved using SGE.
1283 src_reg sge_src
= result_src
;
1284 sge_src
.negate
= ~sge_src
.negate
;
1285 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1287 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1290 case ir_binop_any_nequal
:
1291 /* "!=" operator producing a scalar boolean. */
1292 if (ir
->operands
[0]->type
->is_vector() ||
1293 ir
->operands
[1]->type
->is_vector()) {
1294 src_reg temp
= get_temp(glsl_type::vec4_type
);
1295 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1297 /* After the dot-product, the value will be an integer on the
1298 * range [0,4]. Zero stays zero, and positive values become 1.0.
1300 ir_to_mesa_instruction
*const dp
=
1301 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1302 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1303 /* The clamping to [0,1] can be done for free in the fragment
1304 * shader with a saturate.
1306 dp
->saturate
= true;
1308 /* Negating the result of the dot-product gives values on the range
1309 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1310 * achieved using SLT.
1312 src_reg slt_src
= result_src
;
1313 slt_src
.negate
= ~slt_src
.negate
;
1314 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1317 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1322 assert(ir
->operands
[0]->type
->is_vector());
1324 /* After the dot-product, the value will be an integer on the
1325 * range [0,4]. Zero stays zero, and positive values become 1.0.
1327 ir_to_mesa_instruction
*const dp
=
1328 emit_dp(ir
, result_dst
, op
[0], op
[0],
1329 ir
->operands
[0]->type
->vector_elements
);
1330 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1331 /* The clamping to [0,1] can be done for free in the fragment
1332 * shader with a saturate.
1334 dp
->saturate
= true;
1336 /* Negating the result of the dot-product gives values on the range
1337 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1338 * is achieved using SLT.
1340 src_reg slt_src
= result_src
;
1341 slt_src
.negate
= ~slt_src
.negate
;
1342 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1347 case ir_binop_logic_xor
:
1348 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1351 case ir_binop_logic_or
: {
1352 /* After the addition, the value will be an integer on the
1353 * range [0,2]. Zero stays zero, and positive values become 1.0.
1355 ir_to_mesa_instruction
*add
=
1356 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1357 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1358 /* The clamping to [0,1] can be done for free in the fragment
1359 * shader with a saturate.
1361 add
->saturate
= true;
1363 /* Negating the result of the addition gives values on the range
1364 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1365 * is achieved using SLT.
1367 src_reg slt_src
= result_src
;
1368 slt_src
.negate
= ~slt_src
.negate
;
1369 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1374 case ir_binop_logic_and
:
1375 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1376 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1380 assert(ir
->operands
[0]->type
->is_vector());
1381 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1382 emit_dp(ir
, result_dst
, op
[0], op
[1],
1383 ir
->operands
[0]->type
->vector_elements
);
1387 /* sqrt(x) = x * rsq(x). */
1388 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1389 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1390 /* For incoming channels <= 0, set the result to 0. */
1391 op
[0].negate
= ~op
[0].negate
;
1392 emit(ir
, OPCODE_CMP
, result_dst
,
1393 op
[0], result_src
, src_reg_for_float(0.0));
1396 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1404 /* Mesa IR lacks types, ints are stored as truncated floats. */
1409 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1413 emit(ir
, OPCODE_SNE
, result_dst
,
1414 op
[0], src_reg_for_float(0.0));
1416 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1417 case ir_unop_bitcast_f2u
:
1418 case ir_unop_bitcast_i2f
:
1419 case ir_unop_bitcast_u2f
:
1422 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1425 op
[0].negate
= ~op
[0].negate
;
1426 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1427 result_src
.negate
= ~result_src
.negate
;
1430 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1433 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1435 case ir_unop_pack_snorm_2x16
:
1436 case ir_unop_pack_snorm_4x8
:
1437 case ir_unop_pack_unorm_2x16
:
1438 case ir_unop_pack_unorm_4x8
:
1439 case ir_unop_pack_half_2x16
:
1440 case ir_unop_unpack_snorm_2x16
:
1441 case ir_unop_unpack_snorm_4x8
:
1442 case ir_unop_unpack_unorm_2x16
:
1443 case ir_unop_unpack_unorm_4x8
:
1444 case ir_unop_unpack_half_2x16
:
1445 case ir_unop_unpack_half_2x16_split_x
:
1446 case ir_unop_unpack_half_2x16_split_y
:
1447 case ir_binop_pack_half_2x16_split
:
1448 case ir_unop_bitfield_reverse
:
1449 case ir_unop_bit_count
:
1450 case ir_unop_find_msb
:
1451 case ir_unop_find_lsb
:
1452 assert(!"not supported");
1455 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1458 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1461 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1464 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1465 * hardware backends have no way to avoid Mesa IR generation
1466 * even if they don't use it, we need to emit "something" and
1469 case ir_binop_lshift
:
1470 case ir_binop_rshift
:
1471 case ir_binop_bit_and
:
1472 case ir_binop_bit_xor
:
1473 case ir_binop_bit_or
:
1474 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1477 case ir_unop_bit_not
:
1478 case ir_unop_round_even
:
1479 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1482 case ir_binop_ubo_load
:
1483 assert(!"not supported");
1487 /* ir_triop_lrp operands are (x, y, a) while
1488 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1490 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1493 case ir_binop_vector_extract
:
1497 case ir_triop_bitfield_extract
:
1498 case ir_triop_vector_insert
:
1499 case ir_quadop_bitfield_insert
:
1500 case ir_binop_ldexp
:
1502 assert(!"not supported");
1505 case ir_quadop_vector
:
1506 /* This operation should have already been handled.
1508 assert(!"Should not get here.");
1512 this->result
= result_src
;
1517 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1523 /* Note that this is only swizzles in expressions, not those on the left
1524 * hand side of an assignment, which do write masking. See ir_assignment
1528 ir
->val
->accept(this);
1530 assert(src
.file
!= PROGRAM_UNDEFINED
);
1532 for (i
= 0; i
< 4; i
++) {
1533 if (i
< ir
->type
->vector_elements
) {
1536 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1539 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1542 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1545 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1549 /* If the type is smaller than a vec4, replicate the last
1552 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1556 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1562 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1564 variable_storage
*entry
= find_variable_storage(ir
->var
);
1565 ir_variable
*var
= ir
->var
;
1568 switch (var
->mode
) {
1569 case ir_var_uniform
:
1570 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1572 this->variables
.push_tail(entry
);
1574 case ir_var_shader_in
:
1575 /* The linker assigns locations for varyings and attributes,
1576 * including deprecated builtins (like gl_Color),
1577 * user-assigned generic attributes (glBindVertexLocation),
1578 * and user-defined varyings.
1580 assert(var
->location
!= -1);
1581 entry
= new(mem_ctx
) variable_storage(var
,
1585 case ir_var_shader_out
:
1586 assert(var
->location
!= -1);
1587 entry
= new(mem_ctx
) variable_storage(var
,
1591 case ir_var_system_value
:
1592 entry
= new(mem_ctx
) variable_storage(var
,
1593 PROGRAM_SYSTEM_VALUE
,
1597 case ir_var_temporary
:
1598 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1600 this->variables
.push_tail(entry
);
1602 next_temp
+= type_size(var
->type
);
1607 printf("Failed to make storage for %s\n", var
->name
);
1612 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1616 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1620 int element_size
= type_size(ir
->type
);
1622 index
= ir
->array_index
->constant_expression_value();
1624 ir
->array
->accept(this);
1628 src
.index
+= index
->value
.i
[0] * element_size
;
1630 /* Variable index array dereference. It eats the "vec4" of the
1631 * base of the array and an index that offsets the Mesa register
1634 ir
->array_index
->accept(this);
1638 if (element_size
== 1) {
1639 index_reg
= this->result
;
1641 index_reg
= get_temp(glsl_type::float_type
);
1643 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1644 this->result
, src_reg_for_float(element_size
));
1647 /* If there was already a relative address register involved, add the
1648 * new and the old together to get the new offset.
1650 if (src
.reladdr
!= NULL
) {
1651 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1653 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1654 index_reg
, *src
.reladdr
);
1656 index_reg
= accum_reg
;
1659 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1660 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1663 /* If the type is smaller than a vec4, replicate the last channel out. */
1664 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1665 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1667 src
.swizzle
= SWIZZLE_NOOP
;
1673 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1676 const glsl_type
*struct_type
= ir
->record
->type
;
1679 ir
->record
->accept(this);
1681 for (i
= 0; i
< struct_type
->length
; i
++) {
1682 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1684 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1687 /* If the type is smaller than a vec4, replicate the last channel out. */
1688 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1689 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1691 this->result
.swizzle
= SWIZZLE_NOOP
;
1693 this->result
.index
+= offset
;
1697 * We want to be careful in assignment setup to hit the actual storage
1698 * instead of potentially using a temporary like we might with the
1699 * ir_dereference handler.
1702 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1704 /* The LHS must be a dereference. If the LHS is a variable indexed array
1705 * access of a vector, it must be separated into a series conditional moves
1706 * before reaching this point (see ir_vec_index_to_cond_assign).
1708 assert(ir
->as_dereference());
1709 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1711 assert(!deref_array
->array
->type
->is_vector());
1714 /* Use the rvalue deref handler for the most part. We'll ignore
1715 * swizzles in it and write swizzles using writemask, though.
1718 return dst_reg(v
->result
);
1722 * Process the condition of a conditional assignment
1724 * Examines the condition of a conditional assignment to generate the optimal
1725 * first operand of a \c CMP instruction. If the condition is a relational
1726 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1727 * used as the source for the \c CMP instruction. Otherwise the comparison
1728 * is processed to a boolean result, and the boolean result is used as the
1729 * operand to the CMP instruction.
1732 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1734 ir_rvalue
*src_ir
= ir
;
1736 bool switch_order
= false;
1738 ir_expression
*const expr
= ir
->as_expression();
1739 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1740 bool zero_on_left
= false;
1742 if (expr
->operands
[0]->is_zero()) {
1743 src_ir
= expr
->operands
[1];
1744 zero_on_left
= true;
1745 } else if (expr
->operands
[1]->is_zero()) {
1746 src_ir
= expr
->operands
[0];
1747 zero_on_left
= false;
1751 * (a < 0) T F F ( a < 0) T F F
1752 * (0 < a) F F T (-a < 0) F F T
1753 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1754 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1755 * (a > 0) F F T (-a < 0) F F T
1756 * (0 > a) T F F ( a < 0) T F F
1757 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1758 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1760 * Note that exchanging the order of 0 and 'a' in the comparison simply
1761 * means that the value of 'a' should be negated.
1764 switch (expr
->operation
) {
1766 switch_order
= false;
1767 negate
= zero_on_left
;
1770 case ir_binop_greater
:
1771 switch_order
= false;
1772 negate
= !zero_on_left
;
1775 case ir_binop_lequal
:
1776 switch_order
= true;
1777 negate
= !zero_on_left
;
1780 case ir_binop_gequal
:
1781 switch_order
= true;
1782 negate
= zero_on_left
;
1786 /* This isn't the right kind of comparison afterall, so make sure
1787 * the whole condition is visited.
1795 src_ir
->accept(this);
1797 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1798 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1799 * choose which value OPCODE_CMP produces without an extra instruction
1800 * computing the condition.
1803 this->result
.negate
= ~this->result
.negate
;
1805 return switch_order
;
1809 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1815 ir
->rhs
->accept(this);
1818 l
= get_assignment_lhs(ir
->lhs
, this);
1820 /* FINISHME: This should really set to the correct maximal writemask for each
1821 * FINISHME: component written (in the loops below). This case can only
1822 * FINISHME: occur for matrices, arrays, and structures.
1824 if (ir
->write_mask
== 0) {
1825 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1826 l
.writemask
= WRITEMASK_XYZW
;
1827 } else if (ir
->lhs
->type
->is_scalar()) {
1828 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1829 * FINISHME: W component of fragment shader output zero, work correctly.
1831 l
.writemask
= WRITEMASK_XYZW
;
1834 int first_enabled_chan
= 0;
1837 assert(ir
->lhs
->type
->is_vector());
1838 l
.writemask
= ir
->write_mask
;
1840 for (int i
= 0; i
< 4; i
++) {
1841 if (l
.writemask
& (1 << i
)) {
1842 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1847 /* Swizzle a small RHS vector into the channels being written.
1849 * glsl ir treats write_mask as dictating how many channels are
1850 * present on the RHS while Mesa IR treats write_mask as just
1851 * showing which channels of the vec4 RHS get written.
1853 for (int i
= 0; i
< 4; i
++) {
1854 if (l
.writemask
& (1 << i
))
1855 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1857 swizzles
[i
] = first_enabled_chan
;
1859 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1860 swizzles
[2], swizzles
[3]);
1863 assert(l
.file
!= PROGRAM_UNDEFINED
);
1864 assert(r
.file
!= PROGRAM_UNDEFINED
);
1866 if (ir
->condition
) {
1867 const bool switch_order
= this->process_move_condition(ir
->condition
);
1868 src_reg condition
= this->result
;
1870 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1872 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1874 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1881 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1882 emit(ir
, OPCODE_MOV
, l
, r
);
1891 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1894 GLfloat stack_vals
[4] = { 0 };
1895 GLfloat
*values
= stack_vals
;
1898 /* Unfortunately, 4 floats is all we can get into
1899 * _mesa_add_unnamed_constant. So, make a temp to store an
1900 * aggregate constant and move each constant value into it. If we
1901 * get lucky, copy propagation will eliminate the extra moves.
1904 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1905 src_reg temp_base
= get_temp(ir
->type
);
1906 dst_reg temp
= dst_reg(temp_base
);
1908 foreach_iter(exec_list_iterator
, iter
, ir
->components
) {
1909 ir_constant
*field_value
= (ir_constant
*)iter
.get();
1910 int size
= type_size(field_value
->type
);
1914 field_value
->accept(this);
1917 for (i
= 0; i
< (unsigned int)size
; i
++) {
1918 emit(ir
, OPCODE_MOV
, temp
, src
);
1924 this->result
= temp_base
;
1928 if (ir
->type
->is_array()) {
1929 src_reg temp_base
= get_temp(ir
->type
);
1930 dst_reg temp
= dst_reg(temp_base
);
1931 int size
= type_size(ir
->type
->fields
.array
);
1935 for (i
= 0; i
< ir
->type
->length
; i
++) {
1936 ir
->array_elements
[i
]->accept(this);
1938 for (int j
= 0; j
< size
; j
++) {
1939 emit(ir
, OPCODE_MOV
, temp
, src
);
1945 this->result
= temp_base
;
1949 if (ir
->type
->is_matrix()) {
1950 src_reg mat
= get_temp(ir
->type
);
1951 dst_reg mat_column
= dst_reg(mat
);
1953 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1954 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1955 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1957 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1958 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1959 (gl_constant_value
*) values
,
1960 ir
->type
->vector_elements
,
1962 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1971 src
.file
= PROGRAM_CONSTANT
;
1972 switch (ir
->type
->base_type
) {
1973 case GLSL_TYPE_FLOAT
:
1974 values
= &ir
->value
.f
[0];
1976 case GLSL_TYPE_UINT
:
1977 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1978 values
[i
] = ir
->value
.u
[i
];
1982 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1983 values
[i
] = ir
->value
.i
[i
];
1986 case GLSL_TYPE_BOOL
:
1987 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1988 values
[i
] = ir
->value
.b
[i
];
1992 assert(!"Non-float/uint/int/bool constant");
1995 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1996 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1997 (gl_constant_value
*) values
,
1998 ir
->type
->vector_elements
,
1999 &this->result
.swizzle
);
2003 ir_to_mesa_visitor::visit(ir_call
*ir
)
2005 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
2009 ir_to_mesa_visitor::visit(ir_texture
*ir
)
2011 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
2012 dst_reg result_dst
, coord_dst
;
2013 ir_to_mesa_instruction
*inst
= NULL
;
2014 prog_opcode opcode
= OPCODE_NOP
;
2016 if (ir
->op
== ir_txs
)
2017 this->result
= src_reg_for_float(0.0);
2019 ir
->coordinate
->accept(this);
2021 /* Put our coords in a temp. We'll need to modify them for shadow,
2022 * projection, or LOD, so the only case we'd use it as is is if
2023 * we're doing plain old texturing. Mesa IR optimization should
2024 * handle cleaning up our mess in that case.
2026 coord
= get_temp(glsl_type::vec4_type
);
2027 coord_dst
= dst_reg(coord
);
2028 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2030 if (ir
->projector
) {
2031 ir
->projector
->accept(this);
2032 projector
= this->result
;
2035 /* Storage for our result. Ideally for an assignment we'd be using
2036 * the actual storage for the result here, instead.
2038 result_src
= get_temp(glsl_type::vec4_type
);
2039 result_dst
= dst_reg(result_src
);
2044 opcode
= OPCODE_TEX
;
2047 opcode
= OPCODE_TXB
;
2048 ir
->lod_info
.bias
->accept(this);
2049 lod_info
= this->result
;
2052 /* Pretend to be TXL so the sampler, coordinate, lod are available */
2054 opcode
= OPCODE_TXL
;
2055 ir
->lod_info
.lod
->accept(this);
2056 lod_info
= this->result
;
2059 opcode
= OPCODE_TXD
;
2060 ir
->lod_info
.grad
.dPdx
->accept(this);
2062 ir
->lod_info
.grad
.dPdy
->accept(this);
2066 assert(!"Unexpected ir_txf_ms opcode");
2069 assert(!"Unexpected ir_lod opcode");
2073 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2075 if (ir
->projector
) {
2076 if (opcode
== OPCODE_TEX
) {
2077 /* Slot the projector in as the last component of the coord. */
2078 coord_dst
.writemask
= WRITEMASK_W
;
2079 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
2080 coord_dst
.writemask
= WRITEMASK_XYZW
;
2081 opcode
= OPCODE_TXP
;
2083 src_reg coord_w
= coord
;
2084 coord_w
.swizzle
= SWIZZLE_WWWW
;
2086 /* For the other TEX opcodes there's no projective version
2087 * since the last slot is taken up by lod info. Do the
2088 * projective divide now.
2090 coord_dst
.writemask
= WRITEMASK_W
;
2091 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
2093 /* In the case where we have to project the coordinates "by hand,"
2094 * the shadow comparitor value must also be projected.
2096 src_reg tmp_src
= coord
;
2097 if (ir
->shadow_comparitor
) {
2098 /* Slot the shadow value in as the second to last component of the
2101 ir
->shadow_comparitor
->accept(this);
2103 tmp_src
= get_temp(glsl_type::vec4_type
);
2104 dst_reg tmp_dst
= dst_reg(tmp_src
);
2106 /* Projective division not allowed for array samplers. */
2107 assert(!sampler_type
->sampler_array
);
2109 tmp_dst
.writemask
= WRITEMASK_Z
;
2110 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
2112 tmp_dst
.writemask
= WRITEMASK_XY
;
2113 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
2116 coord_dst
.writemask
= WRITEMASK_XYZ
;
2117 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
2119 coord_dst
.writemask
= WRITEMASK_XYZW
;
2120 coord
.swizzle
= SWIZZLE_XYZW
;
2124 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2125 * comparitor was put in the correct place (and projected) by the code,
2126 * above, that handles by-hand projection.
2128 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
2129 /* Slot the shadow value in as the second to last component of the
2132 ir
->shadow_comparitor
->accept(this);
2134 /* XXX This will need to be updated for cubemap array samplers. */
2135 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
2136 sampler_type
->sampler_array
) {
2137 coord_dst
.writemask
= WRITEMASK_W
;
2139 coord_dst
.writemask
= WRITEMASK_Z
;
2142 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
2143 coord_dst
.writemask
= WRITEMASK_XYZW
;
2146 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
2147 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2148 coord_dst
.writemask
= WRITEMASK_W
;
2149 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2150 coord_dst
.writemask
= WRITEMASK_XYZW
;
2153 if (opcode
== OPCODE_TXD
)
2154 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2156 inst
= emit(ir
, opcode
, result_dst
, coord
);
2158 if (ir
->shadow_comparitor
)
2159 inst
->tex_shadow
= GL_TRUE
;
2161 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2162 this->shader_program
,
2165 switch (sampler_type
->sampler_dimensionality
) {
2166 case GLSL_SAMPLER_DIM_1D
:
2167 inst
->tex_target
= (sampler_type
->sampler_array
)
2168 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2170 case GLSL_SAMPLER_DIM_2D
:
2171 inst
->tex_target
= (sampler_type
->sampler_array
)
2172 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2174 case GLSL_SAMPLER_DIM_3D
:
2175 inst
->tex_target
= TEXTURE_3D_INDEX
;
2177 case GLSL_SAMPLER_DIM_CUBE
:
2178 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2180 case GLSL_SAMPLER_DIM_RECT
:
2181 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2183 case GLSL_SAMPLER_DIM_BUF
:
2184 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2186 case GLSL_SAMPLER_DIM_EXTERNAL
:
2187 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2190 assert(!"Should not get here.");
2193 this->result
= result_src
;
2197 ir_to_mesa_visitor::visit(ir_return
*ir
)
2199 /* Non-void functions should have been inlined. We may still emit RETs
2200 * from main() unless the EmitNoMainReturn option is set.
2202 assert(!ir
->get_value());
2203 emit(ir
, OPCODE_RET
);
2207 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2209 if (ir
->condition
) {
2210 ir
->condition
->accept(this);
2211 this->result
.negate
= ~this->result
.negate
;
2212 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2214 emit(ir
, OPCODE_KIL_NV
);
2219 ir_to_mesa_visitor::visit(ir_if
*ir
)
2221 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2222 ir_to_mesa_instruction
*prev_inst
;
2224 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2226 ir
->condition
->accept(this);
2227 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2229 if (this->options
->EmitCondCodes
) {
2230 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2232 /* See if we actually generated any instruction for generating
2233 * the condition. If not, then cook up a move to a temp so we
2234 * have something to set cond_update on.
2236 if (cond_inst
== prev_inst
) {
2237 src_reg temp
= get_temp(glsl_type::bool_type
);
2238 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2240 cond_inst
->cond_update
= GL_TRUE
;
2242 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2243 if_inst
->dst
.cond_mask
= COND_NE
;
2245 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2248 this->instructions
.push_tail(if_inst
);
2250 visit_exec_list(&ir
->then_instructions
, this);
2252 if (!ir
->else_instructions
.is_empty()) {
2253 emit(ir
->condition
, OPCODE_ELSE
);
2254 visit_exec_list(&ir
->else_instructions
, this);
2257 if_inst
= emit(ir
->condition
, OPCODE_ENDIF
);
2261 ir_to_mesa_visitor::visit(ir_emit_vertex
*ir
)
2263 assert(!"Geometry shaders not supported.");
2267 ir_to_mesa_visitor::visit(ir_end_primitive
*ir
)
2269 assert(!"Geometry shaders not supported.");
2272 ir_to_mesa_visitor::ir_to_mesa_visitor()
2274 result
.file
= PROGRAM_UNDEFINED
;
2276 next_signature_id
= 1;
2277 current_function
= NULL
;
2278 mem_ctx
= ralloc_context(NULL
);
2281 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2283 ralloc_free(mem_ctx
);
2286 static struct prog_src_register
2287 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2289 struct prog_src_register mesa_reg
;
2291 mesa_reg
.File
= reg
.file
;
2292 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2293 mesa_reg
.Index
= reg
.index
;
2294 mesa_reg
.Swizzle
= reg
.swizzle
;
2295 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2296 mesa_reg
.Negate
= reg
.negate
;
2298 mesa_reg
.HasIndex2
= GL_FALSE
;
2299 mesa_reg
.RelAddr2
= 0;
2300 mesa_reg
.Index2
= 0;
2306 set_branchtargets(ir_to_mesa_visitor
*v
,
2307 struct prog_instruction
*mesa_instructions
,
2308 int num_instructions
)
2310 int if_count
= 0, loop_count
= 0;
2311 int *if_stack
, *loop_stack
;
2312 int if_stack_pos
= 0, loop_stack_pos
= 0;
2315 for (i
= 0; i
< num_instructions
; i
++) {
2316 switch (mesa_instructions
[i
].Opcode
) {
2320 case OPCODE_BGNLOOP
:
2325 mesa_instructions
[i
].BranchTarget
= -1;
2332 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2333 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2335 for (i
= 0; i
< num_instructions
; i
++) {
2336 switch (mesa_instructions
[i
].Opcode
) {
2338 if_stack
[if_stack_pos
] = i
;
2342 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2343 if_stack
[if_stack_pos
- 1] = i
;
2346 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2349 case OPCODE_BGNLOOP
:
2350 loop_stack
[loop_stack_pos
] = i
;
2353 case OPCODE_ENDLOOP
:
2355 /* Rewrite any breaks/conts at this nesting level (haven't
2356 * already had a BranchTarget assigned) to point to the end
2359 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2360 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2361 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2362 if (mesa_instructions
[j
].BranchTarget
== -1) {
2363 mesa_instructions
[j
].BranchTarget
= i
;
2367 /* The loop ends point at each other. */
2368 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2369 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2372 foreach_iter(exec_list_iterator
, iter
, v
->function_signatures
) {
2373 function_entry
*entry
= (function_entry
*)iter
.get();
2375 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2376 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2388 print_program(struct prog_instruction
*mesa_instructions
,
2389 ir_instruction
**mesa_instruction_annotation
,
2390 int num_instructions
)
2392 ir_instruction
*last_ir
= NULL
;
2396 for (i
= 0; i
< num_instructions
; i
++) {
2397 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2398 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2400 fprintf(stdout
, "%3d: ", i
);
2402 if (last_ir
!= ir
&& ir
) {
2405 for (j
= 0; j
< indent
; j
++) {
2406 fprintf(stdout
, " ");
2412 fprintf(stdout
, " "); /* line number spacing. */
2415 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2416 PROG_PRINT_DEBUG
, NULL
);
2420 class add_uniform_to_shader
: public program_resource_visitor
{
2422 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2423 struct gl_program_parameter_list
*params
,
2424 gl_shader_type shader_type
)
2425 : shader_program(shader_program
), params(params
), idx(-1),
2426 shader_type(shader_type
)
2431 void process(ir_variable
*var
)
2434 this->program_resource_visitor::process(var
);
2436 var
->location
= this->idx
;
2440 virtual void visit_field(const glsl_type
*type
, const char *name
,
2443 struct gl_shader_program
*shader_program
;
2444 struct gl_program_parameter_list
*params
;
2446 gl_shader_type shader_type
;
2450 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2457 if (type
->is_vector() || type
->is_scalar()) {
2458 size
= type
->vector_elements
;
2460 size
= type_size(type
) * 4;
2463 gl_register_file file
;
2464 if (type
->is_sampler() ||
2465 (type
->is_array() && type
->fields
.array
->is_sampler())) {
2466 file
= PROGRAM_SAMPLER
;
2468 file
= PROGRAM_UNIFORM
;
2471 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2473 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2476 /* Sampler uniform values are stored in prog->SamplerUnits,
2477 * and the entry in that array is selected by this index we
2478 * store in ParameterValues[].
2480 if (file
== PROGRAM_SAMPLER
) {
2483 this->shader_program
->UniformHash
->get(location
,
2484 params
->Parameters
[index
].Name
);
2490 struct gl_uniform_storage
*storage
=
2491 &this->shader_program
->UniformStorage
[location
];
2493 assert(storage
->sampler
[shader_type
].active
);
2495 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2496 params
->ParameterValues
[index
+ j
][0].f
=
2497 storage
->sampler
[shader_type
].index
+ j
;
2501 /* The first part of the uniform that's processed determines the base
2502 * location of the whole uniform (for structures).
2509 * Generate the program parameters list for the user uniforms in a shader
2511 * \param shader_program Linked shader program. This is only used to
2512 * emit possible link errors to the info log.
2513 * \param sh Shader whose uniforms are to be processed.
2514 * \param params Parameter list to be filled in.
2517 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2519 struct gl_shader
*sh
,
2520 struct gl_program_parameter_list
2523 add_uniform_to_shader
add(shader_program
, params
,
2524 _mesa_shader_type_to_index(sh
->Type
));
2526 foreach_list(node
, sh
->ir
) {
2527 ir_variable
*var
= ((ir_instruction
*) node
)->as_variable();
2529 if ((var
== NULL
) || (var
->mode
!= ir_var_uniform
)
2530 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2538 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2539 struct gl_shader_program
*shader_program
,
2540 struct gl_program_parameter_list
*params
)
2542 /* After adding each uniform to the parameter list, connect the storage for
2543 * the parameter with the tracking structure used by the API for the
2546 unsigned last_location
= unsigned(~0);
2547 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2548 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2553 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2559 if (location
!= last_location
) {
2560 struct gl_uniform_storage
*storage
=
2561 &shader_program
->UniformStorage
[location
];
2562 enum gl_uniform_driver_format format
= uniform_native
;
2564 unsigned columns
= 0;
2565 switch (storage
->type
->base_type
) {
2566 case GLSL_TYPE_UINT
:
2567 assert(ctx
->Const
.NativeIntegers
);
2568 format
= uniform_native
;
2573 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2576 case GLSL_TYPE_FLOAT
:
2577 format
= uniform_native
;
2578 columns
= storage
->type
->matrix_columns
;
2580 case GLSL_TYPE_BOOL
:
2581 if (ctx
->Const
.NativeIntegers
) {
2582 format
= (ctx
->Const
.UniformBooleanTrue
== 1)
2583 ? uniform_bool_int_0_1
: uniform_bool_int_0_not0
;
2585 format
= uniform_bool_float
;
2589 case GLSL_TYPE_SAMPLER
:
2590 format
= uniform_native
;
2593 case GLSL_TYPE_ARRAY
:
2594 case GLSL_TYPE_VOID
:
2595 case GLSL_TYPE_STRUCT
:
2596 case GLSL_TYPE_ERROR
:
2597 case GLSL_TYPE_INTERFACE
:
2598 assert(!"Should not get here.");
2602 _mesa_uniform_attach_driver_storage(storage
,
2603 4 * sizeof(float) * columns
,
2606 ¶ms
->ParameterValues
[i
]);
2608 /* After attaching the driver's storage to the uniform, propagate any
2609 * data from the linker's backing store. This will cause values from
2610 * initializers in the source code to be copied over.
2612 _mesa_propagate_uniforms_to_driver_storage(storage
,
2614 MAX2(1, storage
->array_elements
));
2616 last_location
= location
;
2622 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2623 * channels for copy propagation and updates following instructions to
2624 * use the original versions.
2626 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2627 * will occur. As an example, a TXP production before this pass:
2629 * 0: MOV TEMP[1], INPUT[4].xyyy;
2630 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2631 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2635 * 0: MOV TEMP[1], INPUT[4].xyyy;
2636 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2637 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2639 * which allows for dead code elimination on TEMP[1]'s writes.
2642 ir_to_mesa_visitor::copy_propagate(void)
2644 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2645 ir_to_mesa_instruction
*,
2646 this->next_temp
* 4);
2647 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2650 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2651 ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2653 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2654 || inst
->dst
.index
< this->next_temp
);
2656 /* First, do any copy propagation possible into the src regs. */
2657 for (int r
= 0; r
< 3; r
++) {
2658 ir_to_mesa_instruction
*first
= NULL
;
2660 int acp_base
= inst
->src
[r
].index
* 4;
2662 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2663 inst
->src
[r
].reladdr
)
2666 /* See if we can find entries in the ACP consisting of MOVs
2667 * from the same src register for all the swizzled channels
2668 * of this src register reference.
2670 for (int i
= 0; i
< 4; i
++) {
2671 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2672 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2679 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2684 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2685 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2693 /* We've now validated that we can copy-propagate to
2694 * replace this src register reference. Do it.
2696 inst
->src
[r
].file
= first
->src
[0].file
;
2697 inst
->src
[r
].index
= first
->src
[0].index
;
2700 for (int i
= 0; i
< 4; i
++) {
2701 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2702 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2703 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2706 inst
->src
[r
].swizzle
= swizzle
;
2711 case OPCODE_BGNLOOP
:
2712 case OPCODE_ENDLOOP
:
2713 /* End of a basic block, clear the ACP entirely. */
2714 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2723 /* Clear all channels written inside the block from the ACP, but
2724 * leaving those that were not touched.
2726 for (int r
= 0; r
< this->next_temp
; r
++) {
2727 for (int c
= 0; c
< 4; c
++) {
2728 if (!acp
[4 * r
+ c
])
2731 if (acp_level
[4 * r
+ c
] >= level
)
2732 acp
[4 * r
+ c
] = NULL
;
2735 if (inst
->op
== OPCODE_ENDIF
)
2740 /* Continuing the block, clear any written channels from
2743 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2744 /* Any temporary might be written, so no copy propagation
2745 * across this instruction.
2747 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2748 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2749 inst
->dst
.reladdr
) {
2750 /* Any output might be written, so no copy propagation
2751 * from outputs across this instruction.
2753 for (int r
= 0; r
< this->next_temp
; r
++) {
2754 for (int c
= 0; c
< 4; c
++) {
2755 if (!acp
[4 * r
+ c
])
2758 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2759 acp
[4 * r
+ c
] = NULL
;
2762 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2763 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2764 /* Clear where it's used as dst. */
2765 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2766 for (int c
= 0; c
< 4; c
++) {
2767 if (inst
->dst
.writemask
& (1 << c
)) {
2768 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2773 /* Clear where it's used as src. */
2774 for (int r
= 0; r
< this->next_temp
; r
++) {
2775 for (int c
= 0; c
< 4; c
++) {
2776 if (!acp
[4 * r
+ c
])
2779 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2781 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2782 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2783 inst
->dst
.writemask
& (1 << src_chan
))
2785 acp
[4 * r
+ c
] = NULL
;
2793 /* If this is a copy, add it to the ACP. */
2794 if (inst
->op
== OPCODE_MOV
&&
2795 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2796 !(inst
->dst
.file
== inst
->src
[0].file
&&
2797 inst
->dst
.index
== inst
->src
[0].index
) &&
2798 !inst
->dst
.reladdr
&&
2800 !inst
->src
[0].reladdr
&&
2801 !inst
->src
[0].negate
) {
2802 for (int i
= 0; i
< 4; i
++) {
2803 if (inst
->dst
.writemask
& (1 << i
)) {
2804 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2805 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2811 ralloc_free(acp_level
);
2817 * Convert a shader's GLSL IR into a Mesa gl_program.
2819 static struct gl_program
*
2820 get_mesa_program(struct gl_context
*ctx
,
2821 struct gl_shader_program
*shader_program
,
2822 struct gl_shader
*shader
)
2824 ir_to_mesa_visitor v
;
2825 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2826 ir_instruction
**mesa_instruction_annotation
;
2828 struct gl_program
*prog
;
2830 const char *target_string
= _mesa_glsl_shader_target_name(shader
->Type
);
2831 struct gl_shader_compiler_options
*options
=
2832 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(shader
->Type
)];
2834 switch (shader
->Type
) {
2835 case GL_VERTEX_SHADER
:
2836 target
= GL_VERTEX_PROGRAM_ARB
;
2838 case GL_FRAGMENT_SHADER
:
2839 target
= GL_FRAGMENT_PROGRAM_ARB
;
2841 case GL_GEOMETRY_SHADER
:
2842 target
= GL_GEOMETRY_PROGRAM_NV
;
2845 assert(!"should not be reached");
2849 validate_ir_tree(shader
->ir
);
2851 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2854 prog
->Parameters
= _mesa_new_parameter_list();
2857 v
.shader_program
= shader_program
;
2858 v
.options
= options
;
2860 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2863 /* Emit Mesa IR for main(). */
2864 visit_exec_list(shader
->ir
, &v
);
2865 v
.emit(NULL
, OPCODE_END
);
2867 prog
->NumTemporaries
= v
.next_temp
;
2869 int num_instructions
= 0;
2870 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2875 (struct prog_instruction
*)calloc(num_instructions
,
2876 sizeof(*mesa_instructions
));
2877 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2882 /* Convert ir_mesa_instructions into prog_instructions.
2884 mesa_inst
= mesa_instructions
;
2886 foreach_iter(exec_list_iterator
, iter
, v
.instructions
) {
2887 const ir_to_mesa_instruction
*inst
= (ir_to_mesa_instruction
*)iter
.get();
2889 mesa_inst
->Opcode
= inst
->op
;
2890 mesa_inst
->CondUpdate
= inst
->cond_update
;
2892 mesa_inst
->SaturateMode
= SATURATE_ZERO_ONE
;
2893 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2894 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2895 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2896 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2897 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2898 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2899 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2900 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2901 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2902 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2903 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2904 mesa_instruction_annotation
[i
] = inst
->ir
;
2906 /* Set IndirectRegisterFiles. */
2907 if (mesa_inst
->DstReg
.RelAddr
)
2908 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2910 /* Update program's bitmask of indirectly accessed register files */
2911 for (unsigned src
= 0; src
< 3; src
++)
2912 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2913 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2915 switch (mesa_inst
->Opcode
) {
2917 if (options
->MaxIfDepth
== 0) {
2918 linker_warning(shader_program
,
2919 "Couldn't flatten if-statement. "
2920 "This will likely result in software "
2921 "rasterization.\n");
2924 case OPCODE_BGNLOOP
:
2925 if (options
->EmitNoLoops
) {
2926 linker_warning(shader_program
,
2927 "Couldn't unroll loop. "
2928 "This will likely result in software "
2929 "rasterization.\n");
2933 if (options
->EmitNoCont
) {
2934 linker_warning(shader_program
,
2935 "Couldn't lower continue-statement. "
2936 "This will likely result in software "
2937 "rasterization.\n");
2941 prog
->NumAddressRegs
= 1;
2950 if (!shader_program
->LinkStatus
)
2954 if (!shader_program
->LinkStatus
) {
2958 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2960 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
2962 printf("GLSL IR for linked %s program %d:\n", target_string
,
2963 shader_program
->Name
);
2964 _mesa_print_ir(shader
->ir
, NULL
);
2967 printf("Mesa IR for linked %s program %d:\n", target_string
,
2968 shader_program
->Name
);
2969 print_program(mesa_instructions
, mesa_instruction_annotation
,
2973 prog
->Instructions
= mesa_instructions
;
2974 prog
->NumInstructions
= num_instructions
;
2976 /* Setting this to NULL prevents a possible double free in the fail_exit
2979 mesa_instructions
= NULL
;
2981 do_set_program_inouts(shader
->ir
, prog
, shader
->Type
);
2983 prog
->SamplersUsed
= shader
->active_samplers
;
2984 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2985 _mesa_update_shader_textures_used(shader_program
, prog
);
2987 /* Set the gl_FragDepth layout. */
2988 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2989 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2990 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2993 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2995 if ((ctx
->Shader
.Flags
& GLSL_NO_OPT
) == 0) {
2996 _mesa_optimize_program(ctx
, prog
);
2999 /* This has to be done last. Any operation that can cause
3000 * prog->ParameterValues to get reallocated (e.g., anything that adds a
3001 * program constant) has to happen before creating this linkage.
3003 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
3004 if (!shader_program
->LinkStatus
) {
3011 free(mesa_instructions
);
3012 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
3020 * Called via ctx->Driver.LinkShader()
3021 * This actually involves converting GLSL IR into Mesa gl_programs with
3022 * code lowering and other optimizations.
3025 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3027 assert(prog
->LinkStatus
);
3029 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
3030 if (prog
->_LinkedShaders
[i
] == NULL
)
3034 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
3035 const struct gl_shader_compiler_options
*options
=
3036 &ctx
->ShaderCompilerOptions
[_mesa_shader_type_to_index(prog
->_LinkedShaders
[i
]->Type
)];
3042 do_mat_op_to_vec(ir
);
3043 lower_instructions(ir
, (MOD_TO_FRACT
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
3044 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
3045 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
3047 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
3049 progress
= do_common_optimization(ir
, true, true,
3050 options
->MaxUnrollIterations
,
3054 progress
= lower_quadop_vector(ir
, true) || progress
;
3056 if (options
->MaxIfDepth
== 0)
3057 progress
= lower_discard(ir
) || progress
;
3059 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
3061 if (options
->EmitNoNoise
)
3062 progress
= lower_noise(ir
) || progress
;
3064 /* If there are forms of indirect addressing that the driver
3065 * cannot handle, perform the lowering pass.
3067 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
3068 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
3070 lower_variable_index_to_cond_assign(ir
,
3071 options
->EmitNoIndirectInput
,
3072 options
->EmitNoIndirectOutput
,
3073 options
->EmitNoIndirectTemp
,
3074 options
->EmitNoIndirectUniform
)
3077 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
3078 progress
= lower_vector_insert(ir
, true) || progress
;
3081 validate_ir_tree(ir
);
3084 for (unsigned i
= 0; i
< MESA_SHADER_TYPES
; i
++) {
3085 struct gl_program
*linked_prog
;
3087 if (prog
->_LinkedShaders
[i
] == NULL
)
3090 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
3093 _mesa_copy_linked_program_data((gl_shader_type
) i
, prog
, linked_prog
);
3095 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
3097 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
3098 _mesa_program_index_to_target(i
),
3104 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
3107 return prog
->LinkStatus
;
3111 * Link a GLSL shader program. Called via glLinkProgram().
3114 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3118 _mesa_clear_shader_program_data(ctx
, prog
);
3120 prog
->LinkStatus
= GL_TRUE
;
3122 for (i
= 0; i
< prog
->NumShaders
; i
++) {
3123 if (!prog
->Shaders
[i
]->CompileStatus
) {
3124 linker_error(prog
, "linking with uncompiled shader");
3128 if (prog
->LinkStatus
) {
3129 link_shaders(ctx
, prog
);
3132 if (prog
->LinkStatus
) {
3133 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
3134 prog
->LinkStatus
= GL_FALSE
;
3138 if (ctx
->Shader
.Flags
& GLSL_DUMP
) {
3139 if (!prog
->LinkStatus
) {
3140 printf("GLSL shader program %d failed to link\n", prog
->Name
);
3143 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
3144 printf("GLSL shader program %d info log:\n", prog
->Name
);
3145 printf("%s\n", prog
->InfoLog
);