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ir_to_mesa: Generate smarter code for some conditional moves
[mesa.git] / src / mesa / program / ir_to_mesa.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 /**
27 * \file ir_to_mesa.cpp
28 *
29 * Translate GLSL IR to Mesa's gl_program representation.
30 */
31
32 #include <stdio.h>
33 #include "main/compiler.h"
34 #include "ir.h"
35 #include "ir_visitor.h"
36 #include "ir_print_visitor.h"
37 #include "ir_expression_flattening.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
42 #include "ast.h"
43
44 extern "C" {
45 #include "main/mtypes.h"
46 #include "main/shaderapi.h"
47 #include "main/shaderobj.h"
48 #include "main/uniforms.h"
49 #include "program/hash_table.h"
50 #include "program/prog_instruction.h"
51 #include "program/prog_optimize.h"
52 #include "program/prog_print.h"
53 #include "program/program.h"
54 #include "program/prog_uniform.h"
55 #include "program/prog_parameter.h"
56 #include "program/sampler.h"
57 }
58
59 static int swizzle_for_size(int size);
60
61 /**
62 * This struct is a corresponding struct to Mesa prog_src_register, with
63 * wider fields.
64 */
65 typedef struct ir_to_mesa_src_reg {
66 ir_to_mesa_src_reg(int file, int index, const glsl_type *type)
67 {
68 this->file = file;
69 this->index = index;
70 if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
71 this->swizzle = swizzle_for_size(type->vector_elements);
72 else
73 this->swizzle = SWIZZLE_XYZW;
74 this->negate = 0;
75 this->reladdr = NULL;
76 }
77
78 ir_to_mesa_src_reg()
79 {
80 this->file = PROGRAM_UNDEFINED;
81 this->index = 0;
82 this->swizzle = 0;
83 this->negate = 0;
84 this->reladdr = NULL;
85 }
86
87 int file; /**< PROGRAM_* from Mesa */
88 int index; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
89 GLuint swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
90 int negate; /**< NEGATE_XYZW mask from mesa */
91 /** Register index should be offset by the integer in this reg. */
92 ir_to_mesa_src_reg *reladdr;
93 } ir_to_mesa_src_reg;
94
95 typedef struct ir_to_mesa_dst_reg {
96 int file; /**< PROGRAM_* from Mesa */
97 int index; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
98 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
99 GLuint cond_mask:4;
100 /** Register index should be offset by the integer in this reg. */
101 ir_to_mesa_src_reg *reladdr;
102 } ir_to_mesa_dst_reg;
103
104 extern ir_to_mesa_src_reg ir_to_mesa_undef;
105
106 class ir_to_mesa_instruction : public exec_node {
107 public:
108 /* Callers of this talloc-based new need not call delete. It's
109 * easier to just talloc_free 'ctx' (or any of its ancestors). */
110 static void* operator new(size_t size, void *ctx)
111 {
112 void *node;
113
114 node = talloc_zero_size(ctx, size);
115 assert(node != NULL);
116
117 return node;
118 }
119
120 enum prog_opcode op;
121 ir_to_mesa_dst_reg dst_reg;
122 ir_to_mesa_src_reg src_reg[3];
123 /** Pointer to the ir source this tree came from for debugging */
124 ir_instruction *ir;
125 GLboolean cond_update;
126 int sampler; /**< sampler index */
127 int tex_target; /**< One of TEXTURE_*_INDEX */
128 GLboolean tex_shadow;
129
130 class function_entry *function; /* Set on OPCODE_CAL or OPCODE_BGNSUB */
131 };
132
133 class variable_storage : public exec_node {
134 public:
135 variable_storage(ir_variable *var, int file, int index)
136 : file(file), index(index), var(var)
137 {
138 /* empty */
139 }
140
141 int file;
142 int index;
143 ir_variable *var; /* variable that maps to this, if any */
144 };
145
146 class function_entry : public exec_node {
147 public:
148 ir_function_signature *sig;
149
150 /**
151 * identifier of this function signature used by the program.
152 *
153 * At the point that Mesa instructions for function calls are
154 * generated, we don't know the address of the first instruction of
155 * the function body. So we make the BranchTarget that is called a
156 * small integer and rewrite them during set_branchtargets().
157 */
158 int sig_id;
159
160 /**
161 * Pointer to first instruction of the function body.
162 *
163 * Set during function body emits after main() is processed.
164 */
165 ir_to_mesa_instruction *bgn_inst;
166
167 /**
168 * Index of the first instruction of the function body in actual
169 * Mesa IR.
170 *
171 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
172 */
173 int inst;
174
175 /** Storage for the return value. */
176 ir_to_mesa_src_reg return_reg;
177 };
178
179 class ir_to_mesa_visitor : public ir_visitor {
180 public:
181 ir_to_mesa_visitor();
182 ~ir_to_mesa_visitor();
183
184 function_entry *current_function;
185
186 struct gl_context *ctx;
187 struct gl_program *prog;
188 struct gl_shader_program *shader_program;
189 struct gl_shader_compiler_options *options;
190
191 int next_temp;
192
193 variable_storage *find_variable_storage(ir_variable *var);
194
195 function_entry *get_function_signature(ir_function_signature *sig);
196
197 ir_to_mesa_src_reg get_temp(const glsl_type *type);
198 void reladdr_to_temp(ir_instruction *ir,
199 ir_to_mesa_src_reg *reg, int *num_reladdr);
200
201 struct ir_to_mesa_src_reg src_reg_for_float(float val);
202
203 /**
204 * \name Visit methods
205 *
206 * As typical for the visitor pattern, there must be one \c visit method for
207 * each concrete subclass of \c ir_instruction. Virtual base classes within
208 * the hierarchy should not have \c visit methods.
209 */
210 /*@{*/
211 virtual void visit(ir_variable *);
212 virtual void visit(ir_loop *);
213 virtual void visit(ir_loop_jump *);
214 virtual void visit(ir_function_signature *);
215 virtual void visit(ir_function *);
216 virtual void visit(ir_expression *);
217 virtual void visit(ir_swizzle *);
218 virtual void visit(ir_dereference_variable *);
219 virtual void visit(ir_dereference_array *);
220 virtual void visit(ir_dereference_record *);
221 virtual void visit(ir_assignment *);
222 virtual void visit(ir_constant *);
223 virtual void visit(ir_call *);
224 virtual void visit(ir_return *);
225 virtual void visit(ir_discard *);
226 virtual void visit(ir_texture *);
227 virtual void visit(ir_if *);
228 /*@}*/
229
230 struct ir_to_mesa_src_reg result;
231
232 /** List of variable_storage */
233 exec_list variables;
234
235 /** List of function_entry */
236 exec_list function_signatures;
237 int next_signature_id;
238
239 /** List of ir_to_mesa_instruction */
240 exec_list instructions;
241
242 ir_to_mesa_instruction *ir_to_mesa_emit_op0(ir_instruction *ir,
243 enum prog_opcode op);
244
245 ir_to_mesa_instruction *ir_to_mesa_emit_op1(ir_instruction *ir,
246 enum prog_opcode op,
247 ir_to_mesa_dst_reg dst,
248 ir_to_mesa_src_reg src0);
249
250 ir_to_mesa_instruction *ir_to_mesa_emit_op2(ir_instruction *ir,
251 enum prog_opcode op,
252 ir_to_mesa_dst_reg dst,
253 ir_to_mesa_src_reg src0,
254 ir_to_mesa_src_reg src1);
255
256 ir_to_mesa_instruction *ir_to_mesa_emit_op3(ir_instruction *ir,
257 enum prog_opcode op,
258 ir_to_mesa_dst_reg dst,
259 ir_to_mesa_src_reg src0,
260 ir_to_mesa_src_reg src1,
261 ir_to_mesa_src_reg src2);
262
263 /**
264 * Emit the correct dot-product instruction for the type of arguments
265 *
266 * \sa ir_to_mesa_emit_op2
267 */
268 void ir_to_mesa_emit_dp(ir_instruction *ir,
269 ir_to_mesa_dst_reg dst,
270 ir_to_mesa_src_reg src0,
271 ir_to_mesa_src_reg src1,
272 unsigned elements);
273
274 void ir_to_mesa_emit_scalar_op1(ir_instruction *ir,
275 enum prog_opcode op,
276 ir_to_mesa_dst_reg dst,
277 ir_to_mesa_src_reg src0);
278
279 void ir_to_mesa_emit_scalar_op2(ir_instruction *ir,
280 enum prog_opcode op,
281 ir_to_mesa_dst_reg dst,
282 ir_to_mesa_src_reg src0,
283 ir_to_mesa_src_reg src1);
284
285 GLboolean try_emit_mad(ir_expression *ir,
286 int mul_operand);
287
288 bool process_move_condition(ir_rvalue *ir);
289
290 void *mem_ctx;
291 };
292
293 ir_to_mesa_src_reg ir_to_mesa_undef = ir_to_mesa_src_reg(PROGRAM_UNDEFINED, 0, NULL);
294
295 ir_to_mesa_dst_reg ir_to_mesa_undef_dst = {
296 PROGRAM_UNDEFINED, 0, SWIZZLE_NOOP, COND_TR, NULL,
297 };
298
299 ir_to_mesa_dst_reg ir_to_mesa_address_reg = {
300 PROGRAM_ADDRESS, 0, WRITEMASK_X, COND_TR, NULL
301 };
302
303 static void
304 fail_link(struct gl_shader_program *prog, const char *fmt, ...) PRINTFLIKE(2, 3);
305
306 static void
307 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
308 {
309 va_list args;
310 va_start(args, fmt);
311 prog->InfoLog = talloc_vasprintf_append(prog->InfoLog, fmt, args);
312 va_end(args);
313
314 prog->LinkStatus = GL_FALSE;
315 }
316
317 static int
318 swizzle_for_size(int size)
319 {
320 int size_swizzles[4] = {
321 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
322 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
323 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
324 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
325 };
326
327 assert((size >= 1) && (size <= 4));
328 return size_swizzles[size - 1];
329 }
330
331 ir_to_mesa_instruction *
332 ir_to_mesa_visitor::ir_to_mesa_emit_op3(ir_instruction *ir,
333 enum prog_opcode op,
334 ir_to_mesa_dst_reg dst,
335 ir_to_mesa_src_reg src0,
336 ir_to_mesa_src_reg src1,
337 ir_to_mesa_src_reg src2)
338 {
339 ir_to_mesa_instruction *inst = new(mem_ctx) ir_to_mesa_instruction();
340 int num_reladdr = 0;
341
342 /* If we have to do relative addressing, we want to load the ARL
343 * reg directly for one of the regs, and preload the other reladdr
344 * sources into temps.
345 */
346 num_reladdr += dst.reladdr != NULL;
347 num_reladdr += src0.reladdr != NULL;
348 num_reladdr += src1.reladdr != NULL;
349 num_reladdr += src2.reladdr != NULL;
350
351 reladdr_to_temp(ir, &src2, &num_reladdr);
352 reladdr_to_temp(ir, &src1, &num_reladdr);
353 reladdr_to_temp(ir, &src0, &num_reladdr);
354
355 if (dst.reladdr) {
356 ir_to_mesa_emit_op1(ir, OPCODE_ARL, ir_to_mesa_address_reg,
357 *dst.reladdr);
358
359 num_reladdr--;
360 }
361 assert(num_reladdr == 0);
362
363 inst->op = op;
364 inst->dst_reg = dst;
365 inst->src_reg[0] = src0;
366 inst->src_reg[1] = src1;
367 inst->src_reg[2] = src2;
368 inst->ir = ir;
369
370 inst->function = NULL;
371
372 this->instructions.push_tail(inst);
373
374 return inst;
375 }
376
377
378 ir_to_mesa_instruction *
379 ir_to_mesa_visitor::ir_to_mesa_emit_op2(ir_instruction *ir,
380 enum prog_opcode op,
381 ir_to_mesa_dst_reg dst,
382 ir_to_mesa_src_reg src0,
383 ir_to_mesa_src_reg src1)
384 {
385 return ir_to_mesa_emit_op3(ir, op, dst, src0, src1, ir_to_mesa_undef);
386 }
387
388 ir_to_mesa_instruction *
389 ir_to_mesa_visitor::ir_to_mesa_emit_op1(ir_instruction *ir,
390 enum prog_opcode op,
391 ir_to_mesa_dst_reg dst,
392 ir_to_mesa_src_reg src0)
393 {
394 assert(dst.writemask != 0);
395 return ir_to_mesa_emit_op3(ir, op, dst,
396 src0, ir_to_mesa_undef, ir_to_mesa_undef);
397 }
398
399 ir_to_mesa_instruction *
400 ir_to_mesa_visitor::ir_to_mesa_emit_op0(ir_instruction *ir,
401 enum prog_opcode op)
402 {
403 return ir_to_mesa_emit_op3(ir, op, ir_to_mesa_undef_dst,
404 ir_to_mesa_undef,
405 ir_to_mesa_undef,
406 ir_to_mesa_undef);
407 }
408
409 void
410 ir_to_mesa_visitor::ir_to_mesa_emit_dp(ir_instruction *ir,
411 ir_to_mesa_dst_reg dst,
412 ir_to_mesa_src_reg src0,
413 ir_to_mesa_src_reg src1,
414 unsigned elements)
415 {
416 static const gl_inst_opcode dot_opcodes[] = {
417 OPCODE_DP2, OPCODE_DP3, OPCODE_DP4
418 };
419
420 ir_to_mesa_emit_op3(ir, dot_opcodes[elements - 2],
421 dst, src0, src1, ir_to_mesa_undef);
422 }
423
424 inline ir_to_mesa_dst_reg
425 ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg reg)
426 {
427 ir_to_mesa_dst_reg dst_reg;
428
429 dst_reg.file = reg.file;
430 dst_reg.index = reg.index;
431 dst_reg.writemask = WRITEMASK_XYZW;
432 dst_reg.cond_mask = COND_TR;
433 dst_reg.reladdr = reg.reladdr;
434
435 return dst_reg;
436 }
437
438 inline ir_to_mesa_src_reg
439 ir_to_mesa_src_reg_from_dst(ir_to_mesa_dst_reg reg)
440 {
441 return ir_to_mesa_src_reg(reg.file, reg.index, NULL);
442 }
443
444 /**
445 * Emits Mesa scalar opcodes to produce unique answers across channels.
446 *
447 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
448 * channel determines the result across all channels. So to do a vec4
449 * of this operation, we want to emit a scalar per source channel used
450 * to produce dest channels.
451 */
452 void
453 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op2(ir_instruction *ir,
454 enum prog_opcode op,
455 ir_to_mesa_dst_reg dst,
456 ir_to_mesa_src_reg orig_src0,
457 ir_to_mesa_src_reg orig_src1)
458 {
459 int i, j;
460 int done_mask = ~dst.writemask;
461
462 /* Mesa RCP is a scalar operation splatting results to all channels,
463 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
464 * dst channels.
465 */
466 for (i = 0; i < 4; i++) {
467 GLuint this_mask = (1 << i);
468 ir_to_mesa_instruction *inst;
469 ir_to_mesa_src_reg src0 = orig_src0;
470 ir_to_mesa_src_reg src1 = orig_src1;
471
472 if (done_mask & this_mask)
473 continue;
474
475 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
476 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
477 for (j = i + 1; j < 4; j++) {
478 if (!(done_mask & (1 << j)) &&
479 GET_SWZ(src0.swizzle, j) == src0_swiz &&
480 GET_SWZ(src1.swizzle, j) == src1_swiz) {
481 this_mask |= (1 << j);
482 }
483 }
484 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
485 src0_swiz, src0_swiz);
486 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
487 src1_swiz, src1_swiz);
488
489 inst = ir_to_mesa_emit_op2(ir, op,
490 dst,
491 src0,
492 src1);
493 inst->dst_reg.writemask = this_mask;
494 done_mask |= this_mask;
495 }
496 }
497
498 void
499 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op1(ir_instruction *ir,
500 enum prog_opcode op,
501 ir_to_mesa_dst_reg dst,
502 ir_to_mesa_src_reg src0)
503 {
504 ir_to_mesa_src_reg undef = ir_to_mesa_undef;
505
506 undef.swizzle = SWIZZLE_XXXX;
507
508 ir_to_mesa_emit_scalar_op2(ir, op, dst, src0, undef);
509 }
510
511 struct ir_to_mesa_src_reg
512 ir_to_mesa_visitor::src_reg_for_float(float val)
513 {
514 ir_to_mesa_src_reg src_reg(PROGRAM_CONSTANT, -1, NULL);
515
516 src_reg.index = _mesa_add_unnamed_constant(this->prog->Parameters,
517 &val, 1, &src_reg.swizzle);
518
519 return src_reg;
520 }
521
522 static int
523 type_size(const struct glsl_type *type)
524 {
525 unsigned int i;
526 int size;
527
528 switch (type->base_type) {
529 case GLSL_TYPE_UINT:
530 case GLSL_TYPE_INT:
531 case GLSL_TYPE_FLOAT:
532 case GLSL_TYPE_BOOL:
533 if (type->is_matrix()) {
534 return type->matrix_columns;
535 } else {
536 /* Regardless of size of vector, it gets a vec4. This is bad
537 * packing for things like floats, but otherwise arrays become a
538 * mess. Hopefully a later pass over the code can pack scalars
539 * down if appropriate.
540 */
541 return 1;
542 }
543 case GLSL_TYPE_ARRAY:
544 return type_size(type->fields.array) * type->length;
545 case GLSL_TYPE_STRUCT:
546 size = 0;
547 for (i = 0; i < type->length; i++) {
548 size += type_size(type->fields.structure[i].type);
549 }
550 return size;
551 case GLSL_TYPE_SAMPLER:
552 /* Samplers take up one slot in UNIFORMS[], but they're baked in
553 * at link time.
554 */
555 return 1;
556 default:
557 assert(0);
558 return 0;
559 }
560 }
561
562 /**
563 * In the initial pass of codegen, we assign temporary numbers to
564 * intermediate results. (not SSA -- variable assignments will reuse
565 * storage). Actual register allocation for the Mesa VM occurs in a
566 * pass over the Mesa IR later.
567 */
568 ir_to_mesa_src_reg
569 ir_to_mesa_visitor::get_temp(const glsl_type *type)
570 {
571 ir_to_mesa_src_reg src_reg;
572 int swizzle[4];
573 int i;
574
575 src_reg.file = PROGRAM_TEMPORARY;
576 src_reg.index = next_temp;
577 src_reg.reladdr = NULL;
578 next_temp += type_size(type);
579
580 if (type->is_array() || type->is_record()) {
581 src_reg.swizzle = SWIZZLE_NOOP;
582 } else {
583 for (i = 0; i < type->vector_elements; i++)
584 swizzle[i] = i;
585 for (; i < 4; i++)
586 swizzle[i] = type->vector_elements - 1;
587 src_reg.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1],
588 swizzle[2], swizzle[3]);
589 }
590 src_reg.negate = 0;
591
592 return src_reg;
593 }
594
595 variable_storage *
596 ir_to_mesa_visitor::find_variable_storage(ir_variable *var)
597 {
598
599 variable_storage *entry;
600
601 foreach_iter(exec_list_iterator, iter, this->variables) {
602 entry = (variable_storage *)iter.get();
603
604 if (entry->var == var)
605 return entry;
606 }
607
608 return NULL;
609 }
610
611 void
612 ir_to_mesa_visitor::visit(ir_variable *ir)
613 {
614 if (strcmp(ir->name, "gl_FragCoord") == 0) {
615 struct gl_fragment_program *fp = (struct gl_fragment_program *)this->prog;
616
617 fp->OriginUpperLeft = ir->origin_upper_left;
618 fp->PixelCenterInteger = ir->pixel_center_integer;
619 }
620
621 if (ir->mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
622 unsigned int i;
623 const struct gl_builtin_uniform_desc *statevar;
624
625 for (i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
626 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
627 break;
628 }
629
630 if (!_mesa_builtin_uniform_desc[i].name) {
631 fail_link(this->shader_program,
632 "Failed to find builtin uniform `%s'\n", ir->name);
633 return;
634 }
635
636 statevar = &_mesa_builtin_uniform_desc[i];
637
638 int array_count;
639 if (ir->type->is_array()) {
640 array_count = ir->type->length;
641 } else {
642 array_count = 1;
643 }
644
645 /* Check if this statevar's setup in the STATE file exactly
646 * matches how we'll want to reference it as a
647 * struct/array/whatever. If not, then we need to move it into
648 * temporary storage and hope that it'll get copy-propagated
649 * out.
650 */
651 for (i = 0; i < statevar->num_elements; i++) {
652 if (statevar->elements[i].swizzle != SWIZZLE_XYZW) {
653 break;
654 }
655 }
656
657 struct variable_storage *storage;
658 ir_to_mesa_dst_reg dst;
659 if (i == statevar->num_elements) {
660 /* We'll set the index later. */
661 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
662 this->variables.push_tail(storage);
663
664 dst = ir_to_mesa_undef_dst;
665 } else {
666 storage = new(mem_ctx) variable_storage(ir, PROGRAM_TEMPORARY,
667 this->next_temp);
668 this->variables.push_tail(storage);
669 this->next_temp += type_size(ir->type);
670
671 dst = ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg(PROGRAM_TEMPORARY,
672 storage->index,
673 NULL));
674 }
675
676
677 for (int a = 0; a < array_count; a++) {
678 for (unsigned int i = 0; i < statevar->num_elements; i++) {
679 struct gl_builtin_uniform_element *element = &statevar->elements[i];
680 int tokens[STATE_LENGTH];
681
682 memcpy(tokens, element->tokens, sizeof(element->tokens));
683 if (ir->type->is_array()) {
684 tokens[1] = a;
685 }
686
687 int index = _mesa_add_state_reference(this->prog->Parameters,
688 (gl_state_index *)tokens);
689
690 if (storage->file == PROGRAM_STATE_VAR) {
691 if (storage->index == -1) {
692 storage->index = index;
693 } else {
694 assert(index ==
695 (int)(storage->index + a * statevar->num_elements + i));
696 }
697 } else {
698 ir_to_mesa_src_reg src(PROGRAM_STATE_VAR, index, NULL);
699 src.swizzle = element->swizzle;
700 ir_to_mesa_emit_op1(ir, OPCODE_MOV, dst, src);
701 /* even a float takes up a whole vec4 reg in a struct/array. */
702 dst.index++;
703 }
704 }
705 }
706 if (storage->file == PROGRAM_TEMPORARY &&
707 dst.index != storage->index + type_size(ir->type)) {
708 fail_link(this->shader_program,
709 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
710 ir->name, dst.index - storage->index,
711 type_size(ir->type));
712 }
713 }
714 }
715
716 void
717 ir_to_mesa_visitor::visit(ir_loop *ir)
718 {
719 ir_dereference_variable *counter = NULL;
720
721 if (ir->counter != NULL)
722 counter = new(ir) ir_dereference_variable(ir->counter);
723
724 if (ir->from != NULL) {
725 assert(ir->counter != NULL);
726
727 ir_assignment *a = new(ir) ir_assignment(counter, ir->from, NULL);
728
729 a->accept(this);
730 delete a;
731 }
732
733 ir_to_mesa_emit_op0(NULL, OPCODE_BGNLOOP);
734
735 if (ir->to) {
736 ir_expression *e =
737 new(ir) ir_expression(ir->cmp, glsl_type::bool_type,
738 counter, ir->to);
739 ir_if *if_stmt = new(ir) ir_if(e);
740
741 ir_loop_jump *brk = new(ir) ir_loop_jump(ir_loop_jump::jump_break);
742
743 if_stmt->then_instructions.push_tail(brk);
744
745 if_stmt->accept(this);
746
747 delete if_stmt;
748 delete e;
749 delete brk;
750 }
751
752 visit_exec_list(&ir->body_instructions, this);
753
754 if (ir->increment) {
755 ir_expression *e =
756 new(ir) ir_expression(ir_binop_add, counter->type,
757 counter, ir->increment);
758
759 ir_assignment *a = new(ir) ir_assignment(counter, e, NULL);
760
761 a->accept(this);
762 delete a;
763 delete e;
764 }
765
766 ir_to_mesa_emit_op0(NULL, OPCODE_ENDLOOP);
767 }
768
769 void
770 ir_to_mesa_visitor::visit(ir_loop_jump *ir)
771 {
772 switch (ir->mode) {
773 case ir_loop_jump::jump_break:
774 ir_to_mesa_emit_op0(NULL, OPCODE_BRK);
775 break;
776 case ir_loop_jump::jump_continue:
777 ir_to_mesa_emit_op0(NULL, OPCODE_CONT);
778 break;
779 }
780 }
781
782
783 void
784 ir_to_mesa_visitor::visit(ir_function_signature *ir)
785 {
786 assert(0);
787 (void)ir;
788 }
789
790 void
791 ir_to_mesa_visitor::visit(ir_function *ir)
792 {
793 /* Ignore function bodies other than main() -- we shouldn't see calls to
794 * them since they should all be inlined before we get to ir_to_mesa.
795 */
796 if (strcmp(ir->name, "main") == 0) {
797 const ir_function_signature *sig;
798 exec_list empty;
799
800 sig = ir->matching_signature(&empty);
801
802 assert(sig);
803
804 foreach_iter(exec_list_iterator, iter, sig->body) {
805 ir_instruction *ir = (ir_instruction *)iter.get();
806
807 ir->accept(this);
808 }
809 }
810 }
811
812 GLboolean
813 ir_to_mesa_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
814 {
815 int nonmul_operand = 1 - mul_operand;
816 ir_to_mesa_src_reg a, b, c;
817
818 ir_expression *expr = ir->operands[mul_operand]->as_expression();
819 if (!expr || expr->operation != ir_binop_mul)
820 return false;
821
822 expr->operands[0]->accept(this);
823 a = this->result;
824 expr->operands[1]->accept(this);
825 b = this->result;
826 ir->operands[nonmul_operand]->accept(this);
827 c = this->result;
828
829 this->result = get_temp(ir->type);
830 ir_to_mesa_emit_op3(ir, OPCODE_MAD,
831 ir_to_mesa_dst_reg_from_src(this->result), a, b, c);
832
833 return true;
834 }
835
836 void
837 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction *ir,
838 ir_to_mesa_src_reg *reg, int *num_reladdr)
839 {
840 if (!reg->reladdr)
841 return;
842
843 ir_to_mesa_emit_op1(ir, OPCODE_ARL, ir_to_mesa_address_reg, *reg->reladdr);
844
845 if (*num_reladdr != 1) {
846 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
847
848 ir_to_mesa_emit_op1(ir, OPCODE_MOV,
849 ir_to_mesa_dst_reg_from_src(temp), *reg);
850 *reg = temp;
851 }
852
853 (*num_reladdr)--;
854 }
855
856 void
857 ir_to_mesa_visitor::visit(ir_expression *ir)
858 {
859 unsigned int operand;
860 struct ir_to_mesa_src_reg op[2];
861 struct ir_to_mesa_src_reg result_src;
862 struct ir_to_mesa_dst_reg result_dst;
863
864 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
865 */
866 if (ir->operation == ir_binop_add) {
867 if (try_emit_mad(ir, 1))
868 return;
869 if (try_emit_mad(ir, 0))
870 return;
871 }
872
873 for (operand = 0; operand < ir->get_num_operands(); operand++) {
874 this->result.file = PROGRAM_UNDEFINED;
875 ir->operands[operand]->accept(this);
876 if (this->result.file == PROGRAM_UNDEFINED) {
877 ir_print_visitor v;
878 printf("Failed to get tree for expression operand:\n");
879 ir->operands[operand]->accept(&v);
880 exit(1);
881 }
882 op[operand] = this->result;
883
884 /* Matrix expression operands should have been broken down to vector
885 * operations already.
886 */
887 assert(!ir->operands[operand]->type->is_matrix());
888 }
889
890 int vector_elements = ir->operands[0]->type->vector_elements;
891 if (ir->operands[1]) {
892 vector_elements = MAX2(vector_elements,
893 ir->operands[1]->type->vector_elements);
894 }
895
896 this->result.file = PROGRAM_UNDEFINED;
897
898 /* Storage for our result. Ideally for an assignment we'd be using
899 * the actual storage for the result here, instead.
900 */
901 result_src = get_temp(ir->type);
902 /* convenience for the emit functions below. */
903 result_dst = ir_to_mesa_dst_reg_from_src(result_src);
904 /* Limit writes to the channels that will be used by result_src later.
905 * This does limit this temp's use as a temporary for multi-instruction
906 * sequences.
907 */
908 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
909
910 switch (ir->operation) {
911 case ir_unop_logic_not:
912 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst,
913 op[0], src_reg_for_float(0.0));
914 break;
915 case ir_unop_neg:
916 op[0].negate = ~op[0].negate;
917 result_src = op[0];
918 break;
919 case ir_unop_abs:
920 ir_to_mesa_emit_op1(ir, OPCODE_ABS, result_dst, op[0]);
921 break;
922 case ir_unop_sign:
923 ir_to_mesa_emit_op1(ir, OPCODE_SSG, result_dst, op[0]);
924 break;
925 case ir_unop_rcp:
926 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RCP, result_dst, op[0]);
927 break;
928
929 case ir_unop_exp2:
930 ir_to_mesa_emit_scalar_op1(ir, OPCODE_EX2, result_dst, op[0]);
931 break;
932 case ir_unop_exp:
933 case ir_unop_log:
934 assert(!"not reached: should be handled by ir_explog_to_explog2");
935 break;
936 case ir_unop_log2:
937 ir_to_mesa_emit_scalar_op1(ir, OPCODE_LG2, result_dst, op[0]);
938 break;
939 case ir_unop_sin:
940 ir_to_mesa_emit_scalar_op1(ir, OPCODE_SIN, result_dst, op[0]);
941 break;
942 case ir_unop_cos:
943 ir_to_mesa_emit_scalar_op1(ir, OPCODE_COS, result_dst, op[0]);
944 break;
945
946 case ir_unop_dFdx:
947 ir_to_mesa_emit_op1(ir, OPCODE_DDX, result_dst, op[0]);
948 break;
949 case ir_unop_dFdy:
950 ir_to_mesa_emit_op1(ir, OPCODE_DDY, result_dst, op[0]);
951 break;
952
953 case ir_unop_noise: {
954 const enum prog_opcode opcode =
955 prog_opcode(OPCODE_NOISE1
956 + (ir->operands[0]->type->vector_elements) - 1);
957 assert((opcode >= OPCODE_NOISE1) && (opcode <= OPCODE_NOISE4));
958
959 ir_to_mesa_emit_op1(ir, opcode, result_dst, op[0]);
960 break;
961 }
962
963 case ir_binop_add:
964 ir_to_mesa_emit_op2(ir, OPCODE_ADD, result_dst, op[0], op[1]);
965 break;
966 case ir_binop_sub:
967 ir_to_mesa_emit_op2(ir, OPCODE_SUB, result_dst, op[0], op[1]);
968 break;
969
970 case ir_binop_mul:
971 ir_to_mesa_emit_op2(ir, OPCODE_MUL, result_dst, op[0], op[1]);
972 break;
973 case ir_binop_div:
974 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
975 case ir_binop_mod:
976 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
977 break;
978
979 case ir_binop_less:
980 ir_to_mesa_emit_op2(ir, OPCODE_SLT, result_dst, op[0], op[1]);
981 break;
982 case ir_binop_greater:
983 ir_to_mesa_emit_op2(ir, OPCODE_SGT, result_dst, op[0], op[1]);
984 break;
985 case ir_binop_lequal:
986 ir_to_mesa_emit_op2(ir, OPCODE_SLE, result_dst, op[0], op[1]);
987 break;
988 case ir_binop_gequal:
989 ir_to_mesa_emit_op2(ir, OPCODE_SGE, result_dst, op[0], op[1]);
990 break;
991 case ir_binop_equal:
992 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst, op[0], op[1]);
993 break;
994 case ir_binop_nequal:
995 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
996 break;
997 case ir_binop_all_equal:
998 /* "==" operator producing a scalar boolean. */
999 if (ir->operands[0]->type->is_vector() ||
1000 ir->operands[1]->type->is_vector()) {
1001 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
1002 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1003 ir_to_mesa_dst_reg_from_src(temp), op[0], op[1]);
1004 ir_to_mesa_emit_dp(ir, result_dst, temp, temp, vector_elements);
1005 ir_to_mesa_emit_op2(ir, OPCODE_SEQ,
1006 result_dst, result_src, src_reg_for_float(0.0));
1007 } else {
1008 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst, op[0], op[1]);
1009 }
1010 break;
1011 case ir_binop_any_nequal:
1012 /* "!=" operator producing a scalar boolean. */
1013 if (ir->operands[0]->type->is_vector() ||
1014 ir->operands[1]->type->is_vector()) {
1015 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
1016 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1017 ir_to_mesa_dst_reg_from_src(temp), op[0], op[1]);
1018 ir_to_mesa_emit_dp(ir, result_dst, temp, temp, vector_elements);
1019 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1020 result_dst, result_src, src_reg_for_float(0.0));
1021 } else {
1022 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
1023 }
1024 break;
1025
1026 case ir_unop_any:
1027 assert(ir->operands[0]->type->is_vector());
1028 ir_to_mesa_emit_dp(ir, result_dst, op[0], op[0],
1029 ir->operands[0]->type->vector_elements);
1030 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1031 result_dst, result_src, src_reg_for_float(0.0));
1032 break;
1033
1034 case ir_binop_logic_xor:
1035 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
1036 break;
1037
1038 case ir_binop_logic_or:
1039 /* This could be a saturated add and skip the SNE. */
1040 ir_to_mesa_emit_op2(ir, OPCODE_ADD,
1041 result_dst,
1042 op[0], op[1]);
1043
1044 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1045 result_dst,
1046 result_src, src_reg_for_float(0.0));
1047 break;
1048
1049 case ir_binop_logic_and:
1050 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1051 ir_to_mesa_emit_op2(ir, OPCODE_MUL,
1052 result_dst,
1053 op[0], op[1]);
1054 break;
1055
1056 case ir_binop_dot:
1057 assert(ir->operands[0]->type->is_vector());
1058 assert(ir->operands[0]->type == ir->operands[1]->type);
1059 ir_to_mesa_emit_dp(ir, result_dst, op[0], op[1],
1060 ir->operands[0]->type->vector_elements);
1061 break;
1062
1063 case ir_unop_sqrt:
1064 /* sqrt(x) = x * rsq(x). */
1065 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RSQ, result_dst, op[0]);
1066 ir_to_mesa_emit_op2(ir, OPCODE_MUL, result_dst, result_src, op[0]);
1067 /* For incoming channels <= 0, set the result to 0. */
1068 op[0].negate = ~op[0].negate;
1069 ir_to_mesa_emit_op3(ir, OPCODE_CMP, result_dst,
1070 op[0], result_src, src_reg_for_float(0.0));
1071 break;
1072 case ir_unop_rsq:
1073 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RSQ, result_dst, op[0]);
1074 break;
1075 case ir_unop_i2f:
1076 case ir_unop_b2f:
1077 case ir_unop_b2i:
1078 /* Mesa IR lacks types, ints are stored as truncated floats. */
1079 result_src = op[0];
1080 break;
1081 case ir_unop_f2i:
1082 ir_to_mesa_emit_op1(ir, OPCODE_TRUNC, result_dst, op[0]);
1083 break;
1084 case ir_unop_f2b:
1085 case ir_unop_i2b:
1086 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst,
1087 op[0], src_reg_for_float(0.0));
1088 break;
1089 case ir_unop_trunc:
1090 ir_to_mesa_emit_op1(ir, OPCODE_TRUNC, result_dst, op[0]);
1091 break;
1092 case ir_unop_ceil:
1093 op[0].negate = ~op[0].negate;
1094 ir_to_mesa_emit_op1(ir, OPCODE_FLR, result_dst, op[0]);
1095 result_src.negate = ~result_src.negate;
1096 break;
1097 case ir_unop_floor:
1098 ir_to_mesa_emit_op1(ir, OPCODE_FLR, result_dst, op[0]);
1099 break;
1100 case ir_unop_fract:
1101 ir_to_mesa_emit_op1(ir, OPCODE_FRC, result_dst, op[0]);
1102 break;
1103
1104 case ir_binop_min:
1105 ir_to_mesa_emit_op2(ir, OPCODE_MIN, result_dst, op[0], op[1]);
1106 break;
1107 case ir_binop_max:
1108 ir_to_mesa_emit_op2(ir, OPCODE_MAX, result_dst, op[0], op[1]);
1109 break;
1110 case ir_binop_pow:
1111 ir_to_mesa_emit_scalar_op2(ir, OPCODE_POW, result_dst, op[0], op[1]);
1112 break;
1113
1114 case ir_unop_bit_not:
1115 case ir_unop_u2f:
1116 case ir_binop_lshift:
1117 case ir_binop_rshift:
1118 case ir_binop_bit_and:
1119 case ir_binop_bit_xor:
1120 case ir_binop_bit_or:
1121 case ir_unop_round_even:
1122 assert(!"GLSL 1.30 features unsupported");
1123 break;
1124 }
1125
1126 this->result = result_src;
1127 }
1128
1129
1130 void
1131 ir_to_mesa_visitor::visit(ir_swizzle *ir)
1132 {
1133 ir_to_mesa_src_reg src_reg;
1134 int i;
1135 int swizzle[4];
1136
1137 /* Note that this is only swizzles in expressions, not those on the left
1138 * hand side of an assignment, which do write masking. See ir_assignment
1139 * for that.
1140 */
1141
1142 ir->val->accept(this);
1143 src_reg = this->result;
1144 assert(src_reg.file != PROGRAM_UNDEFINED);
1145
1146 for (i = 0; i < 4; i++) {
1147 if (i < ir->type->vector_elements) {
1148 switch (i) {
1149 case 0:
1150 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.x);
1151 break;
1152 case 1:
1153 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.y);
1154 break;
1155 case 2:
1156 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.z);
1157 break;
1158 case 3:
1159 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.w);
1160 break;
1161 }
1162 } else {
1163 /* If the type is smaller than a vec4, replicate the last
1164 * channel out.
1165 */
1166 swizzle[i] = swizzle[ir->type->vector_elements - 1];
1167 }
1168 }
1169
1170 src_reg.swizzle = MAKE_SWIZZLE4(swizzle[0],
1171 swizzle[1],
1172 swizzle[2],
1173 swizzle[3]);
1174
1175 this->result = src_reg;
1176 }
1177
1178 void
1179 ir_to_mesa_visitor::visit(ir_dereference_variable *ir)
1180 {
1181 variable_storage *entry = find_variable_storage(ir->var);
1182
1183 if (!entry) {
1184 switch (ir->var->mode) {
1185 case ir_var_uniform:
1186 entry = new(mem_ctx) variable_storage(ir->var, PROGRAM_UNIFORM,
1187 ir->var->location);
1188 this->variables.push_tail(entry);
1189 break;
1190 case ir_var_in:
1191 case ir_var_out:
1192 case ir_var_inout:
1193 /* The linker assigns locations for varyings and attributes,
1194 * including deprecated builtins (like gl_Color), user-assign
1195 * generic attributes (glBindVertexLocation), and
1196 * user-defined varyings.
1197 *
1198 * FINISHME: We would hit this path for function arguments. Fix!
1199 */
1200 assert(ir->var->location != -1);
1201 if (ir->var->mode == ir_var_in ||
1202 ir->var->mode == ir_var_inout) {
1203 entry = new(mem_ctx) variable_storage(ir->var,
1204 PROGRAM_INPUT,
1205 ir->var->location);
1206
1207 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
1208 ir->var->location >= VERT_ATTRIB_GENERIC0) {
1209 _mesa_add_attribute(prog->Attributes,
1210 ir->var->name,
1211 _mesa_sizeof_glsl_type(ir->var->type->gl_type),
1212 ir->var->type->gl_type,
1213 ir->var->location - VERT_ATTRIB_GENERIC0);
1214 }
1215 } else {
1216 entry = new(mem_ctx) variable_storage(ir->var,
1217 PROGRAM_OUTPUT,
1218 ir->var->location);
1219 }
1220
1221 break;
1222 case ir_var_auto:
1223 case ir_var_temporary:
1224 entry = new(mem_ctx) variable_storage(ir->var, PROGRAM_TEMPORARY,
1225 this->next_temp);
1226 this->variables.push_tail(entry);
1227
1228 next_temp += type_size(ir->var->type);
1229 break;
1230 }
1231
1232 if (!entry) {
1233 printf("Failed to make storage for %s\n", ir->var->name);
1234 exit(1);
1235 }
1236 }
1237
1238 this->result = ir_to_mesa_src_reg(entry->file, entry->index, ir->var->type);
1239 }
1240
1241 void
1242 ir_to_mesa_visitor::visit(ir_dereference_array *ir)
1243 {
1244 ir_constant *index;
1245 ir_to_mesa_src_reg src_reg;
1246 int element_size = type_size(ir->type);
1247
1248 index = ir->array_index->constant_expression_value();
1249
1250 ir->array->accept(this);
1251 src_reg = this->result;
1252
1253 if (index) {
1254 src_reg.index += index->value.i[0] * element_size;
1255 } else {
1256 ir_to_mesa_src_reg array_base = this->result;
1257 /* Variable index array dereference. It eats the "vec4" of the
1258 * base of the array and an index that offsets the Mesa register
1259 * index.
1260 */
1261 ir->array_index->accept(this);
1262
1263 ir_to_mesa_src_reg index_reg;
1264
1265 if (element_size == 1) {
1266 index_reg = this->result;
1267 } else {
1268 index_reg = get_temp(glsl_type::float_type);
1269
1270 ir_to_mesa_emit_op2(ir, OPCODE_MUL,
1271 ir_to_mesa_dst_reg_from_src(index_reg),
1272 this->result, src_reg_for_float(element_size));
1273 }
1274
1275 src_reg.reladdr = talloc(mem_ctx, ir_to_mesa_src_reg);
1276 memcpy(src_reg.reladdr, &index_reg, sizeof(index_reg));
1277 }
1278
1279 /* If the type is smaller than a vec4, replicate the last channel out. */
1280 if (ir->type->is_scalar() || ir->type->is_vector())
1281 src_reg.swizzle = swizzle_for_size(ir->type->vector_elements);
1282 else
1283 src_reg.swizzle = SWIZZLE_NOOP;
1284
1285 this->result = src_reg;
1286 }
1287
1288 void
1289 ir_to_mesa_visitor::visit(ir_dereference_record *ir)
1290 {
1291 unsigned int i;
1292 const glsl_type *struct_type = ir->record->type;
1293 int offset = 0;
1294
1295 ir->record->accept(this);
1296
1297 for (i = 0; i < struct_type->length; i++) {
1298 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
1299 break;
1300 offset += type_size(struct_type->fields.structure[i].type);
1301 }
1302 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
1303 this->result.index += offset;
1304 }
1305
1306 /**
1307 * We want to be careful in assignment setup to hit the actual storage
1308 * instead of potentially using a temporary like we might with the
1309 * ir_dereference handler.
1310 */
1311 static struct ir_to_mesa_dst_reg
1312 get_assignment_lhs(ir_dereference *ir, ir_to_mesa_visitor *v)
1313 {
1314 /* The LHS must be a dereference. If the LHS is a variable indexed array
1315 * access of a vector, it must be separated into a series conditional moves
1316 * before reaching this point (see ir_vec_index_to_cond_assign).
1317 */
1318 assert(ir->as_dereference());
1319 ir_dereference_array *deref_array = ir->as_dereference_array();
1320 if (deref_array) {
1321 assert(!deref_array->array->type->is_vector());
1322 }
1323
1324 /* Use the rvalue deref handler for the most part. We'll ignore
1325 * swizzles in it and write swizzles using writemask, though.
1326 */
1327 ir->accept(v);
1328 return ir_to_mesa_dst_reg_from_src(v->result);
1329 }
1330
1331 /**
1332 * Process the condition of a conditional assignment
1333 *
1334 * Examines the condition of a conditional assignment to generate the optimal
1335 * first operand of a \c CMP instruction. If the condition is a relational
1336 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1337 * used as the source for the \c CMP instruction. Otherwise the comparison
1338 * is processed to a boolean result, and the boolean result is used as the
1339 * operand to the CMP instruction.
1340 */
1341 bool
1342 ir_to_mesa_visitor::process_move_condition(ir_rvalue *ir)
1343 {
1344 ir_rvalue *src_ir = ir;
1345 bool negate = true;
1346 bool switch_order = false;
1347
1348 ir_expression *const expr = ir->as_expression();
1349 if ((expr != NULL) && (expr->get_num_operands() == 2)) {
1350 bool zero_on_left = false;
1351
1352 if (expr->operands[0]->is_zero()) {
1353 src_ir = expr->operands[1];
1354 zero_on_left = true;
1355 } else if (expr->operands[1]->is_zero()) {
1356 src_ir = expr->operands[0];
1357 zero_on_left = false;
1358 }
1359
1360 /* a is - 0 + - 0 +
1361 * (a < 0) T F F ( a < 0) T F F
1362 * (0 < a) F F T (-a < 0) F F T
1363 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1364 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1365 * (a > 0) F F T (-a < 0) F F T
1366 * (0 > a) T F F ( a < 0) T F F
1367 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1368 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1369 *
1370 * Note that exchanging the order of 0 and 'a' in the comparison simply
1371 * means that the value of 'a' should be negated.
1372 */
1373 if (src_ir != ir) {
1374 switch (expr->operation) {
1375 case ir_binop_less:
1376 switch_order = false;
1377 negate = zero_on_left;
1378 break;
1379
1380 case ir_binop_greater:
1381 switch_order = false;
1382 negate = !zero_on_left;
1383 break;
1384
1385 case ir_binop_lequal:
1386 switch_order = true;
1387 negate = !zero_on_left;
1388 break;
1389
1390 case ir_binop_gequal:
1391 switch_order = true;
1392 negate = zero_on_left;
1393 break;
1394
1395 default:
1396 /* This isn't the right kind of comparison afterall, so make sure
1397 * the whole condition is visited.
1398 */
1399 src_ir = ir;
1400 break;
1401 }
1402 }
1403 }
1404
1405 src_ir->accept(this);
1406
1407 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1408 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1409 * choose which value OPCODE_CMP produces without an extra instruction
1410 * computing the condition.
1411 */
1412 if (negate)
1413 this->result.negate = ~this->result.negate;
1414
1415 return switch_order;
1416 }
1417
1418 void
1419 ir_to_mesa_visitor::visit(ir_assignment *ir)
1420 {
1421 struct ir_to_mesa_dst_reg l;
1422 struct ir_to_mesa_src_reg r;
1423 int i;
1424
1425 ir->rhs->accept(this);
1426 r = this->result;
1427
1428 l = get_assignment_lhs(ir->lhs, this);
1429
1430 /* FINISHME: This should really set to the correct maximal writemask for each
1431 * FINISHME: component written (in the loops below). This case can only
1432 * FINISHME: occur for matrices, arrays, and structures.
1433 */
1434 if (ir->write_mask == 0) {
1435 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
1436 l.writemask = WRITEMASK_XYZW;
1437 } else if (ir->lhs->type->is_scalar()) {
1438 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1439 * FINISHME: W component of fragment shader output zero, work correctly.
1440 */
1441 l.writemask = WRITEMASK_XYZW;
1442 } else {
1443 int swizzles[4];
1444 int first_enabled_chan = 0;
1445 int rhs_chan = 0;
1446
1447 assert(ir->lhs->type->is_vector());
1448 l.writemask = ir->write_mask;
1449
1450 for (int i = 0; i < 4; i++) {
1451 if (l.writemask & (1 << i)) {
1452 first_enabled_chan = GET_SWZ(r.swizzle, i);
1453 break;
1454 }
1455 }
1456
1457 /* Swizzle a small RHS vector into the channels being written.
1458 *
1459 * glsl ir treats write_mask as dictating how many channels are
1460 * present on the RHS while Mesa IR treats write_mask as just
1461 * showing which channels of the vec4 RHS get written.
1462 */
1463 for (int i = 0; i < 4; i++) {
1464 if (l.writemask & (1 << i))
1465 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
1466 else
1467 swizzles[i] = first_enabled_chan;
1468 }
1469 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
1470 swizzles[2], swizzles[3]);
1471 }
1472
1473 assert(l.file != PROGRAM_UNDEFINED);
1474 assert(r.file != PROGRAM_UNDEFINED);
1475
1476 if (ir->condition) {
1477 const bool switch_order = this->process_move_condition(ir->condition);
1478 ir_to_mesa_src_reg condition = this->result;
1479
1480 for (i = 0; i < type_size(ir->lhs->type); i++) {
1481 if (switch_order) {
1482 ir_to_mesa_emit_op3(ir, OPCODE_CMP, l,
1483 condition, ir_to_mesa_src_reg_from_dst(l), r);
1484 } else {
1485 ir_to_mesa_emit_op3(ir, OPCODE_CMP, l,
1486 condition, r, ir_to_mesa_src_reg_from_dst(l));
1487 }
1488
1489 l.index++;
1490 r.index++;
1491 }
1492 } else {
1493 for (i = 0; i < type_size(ir->lhs->type); i++) {
1494 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1495 l.index++;
1496 r.index++;
1497 }
1498 }
1499 }
1500
1501
1502 void
1503 ir_to_mesa_visitor::visit(ir_constant *ir)
1504 {
1505 ir_to_mesa_src_reg src_reg;
1506 GLfloat stack_vals[4] = { 0 };
1507 GLfloat *values = stack_vals;
1508 unsigned int i;
1509
1510 /* Unfortunately, 4 floats is all we can get into
1511 * _mesa_add_unnamed_constant. So, make a temp to store an
1512 * aggregate constant and move each constant value into it. If we
1513 * get lucky, copy propagation will eliminate the extra moves.
1514 */
1515
1516 if (ir->type->base_type == GLSL_TYPE_STRUCT) {
1517 ir_to_mesa_src_reg temp_base = get_temp(ir->type);
1518 ir_to_mesa_dst_reg temp = ir_to_mesa_dst_reg_from_src(temp_base);
1519
1520 foreach_iter(exec_list_iterator, iter, ir->components) {
1521 ir_constant *field_value = (ir_constant *)iter.get();
1522 int size = type_size(field_value->type);
1523
1524 assert(size > 0);
1525
1526 field_value->accept(this);
1527 src_reg = this->result;
1528
1529 for (i = 0; i < (unsigned int)size; i++) {
1530 ir_to_mesa_emit_op1(ir, OPCODE_MOV, temp, src_reg);
1531
1532 src_reg.index++;
1533 temp.index++;
1534 }
1535 }
1536 this->result = temp_base;
1537 return;
1538 }
1539
1540 if (ir->type->is_array()) {
1541 ir_to_mesa_src_reg temp_base = get_temp(ir->type);
1542 ir_to_mesa_dst_reg temp = ir_to_mesa_dst_reg_from_src(temp_base);
1543 int size = type_size(ir->type->fields.array);
1544
1545 assert(size > 0);
1546
1547 for (i = 0; i < ir->type->length; i++) {
1548 ir->array_elements[i]->accept(this);
1549 src_reg = this->result;
1550 for (int j = 0; j < size; j++) {
1551 ir_to_mesa_emit_op1(ir, OPCODE_MOV, temp, src_reg);
1552
1553 src_reg.index++;
1554 temp.index++;
1555 }
1556 }
1557 this->result = temp_base;
1558 return;
1559 }
1560
1561 if (ir->type->is_matrix()) {
1562 ir_to_mesa_src_reg mat = get_temp(ir->type);
1563 ir_to_mesa_dst_reg mat_column = ir_to_mesa_dst_reg_from_src(mat);
1564
1565 for (i = 0; i < ir->type->matrix_columns; i++) {
1566 assert(ir->type->base_type == GLSL_TYPE_FLOAT);
1567 values = &ir->value.f[i * ir->type->vector_elements];
1568
1569 src_reg = ir_to_mesa_src_reg(PROGRAM_CONSTANT, -1, NULL);
1570 src_reg.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1571 values,
1572 ir->type->vector_elements,
1573 &src_reg.swizzle);
1574 ir_to_mesa_emit_op1(ir, OPCODE_MOV, mat_column, src_reg);
1575
1576 mat_column.index++;
1577 }
1578
1579 this->result = mat;
1580 return;
1581 }
1582
1583 src_reg.file = PROGRAM_CONSTANT;
1584 switch (ir->type->base_type) {
1585 case GLSL_TYPE_FLOAT:
1586 values = &ir->value.f[0];
1587 break;
1588 case GLSL_TYPE_UINT:
1589 for (i = 0; i < ir->type->vector_elements; i++) {
1590 values[i] = ir->value.u[i];
1591 }
1592 break;
1593 case GLSL_TYPE_INT:
1594 for (i = 0; i < ir->type->vector_elements; i++) {
1595 values[i] = ir->value.i[i];
1596 }
1597 break;
1598 case GLSL_TYPE_BOOL:
1599 for (i = 0; i < ir->type->vector_elements; i++) {
1600 values[i] = ir->value.b[i];
1601 }
1602 break;
1603 default:
1604 assert(!"Non-float/uint/int/bool constant");
1605 }
1606
1607 this->result = ir_to_mesa_src_reg(PROGRAM_CONSTANT, -1, ir->type);
1608 this->result.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1609 values,
1610 ir->type->vector_elements,
1611 &this->result.swizzle);
1612 }
1613
1614 function_entry *
1615 ir_to_mesa_visitor::get_function_signature(ir_function_signature *sig)
1616 {
1617 function_entry *entry;
1618
1619 foreach_iter(exec_list_iterator, iter, this->function_signatures) {
1620 entry = (function_entry *)iter.get();
1621
1622 if (entry->sig == sig)
1623 return entry;
1624 }
1625
1626 entry = talloc(mem_ctx, function_entry);
1627 entry->sig = sig;
1628 entry->sig_id = this->next_signature_id++;
1629 entry->bgn_inst = NULL;
1630
1631 /* Allocate storage for all the parameters. */
1632 foreach_iter(exec_list_iterator, iter, sig->parameters) {
1633 ir_variable *param = (ir_variable *)iter.get();
1634 variable_storage *storage;
1635
1636 storage = find_variable_storage(param);
1637 assert(!storage);
1638
1639 storage = new(mem_ctx) variable_storage(param, PROGRAM_TEMPORARY,
1640 this->next_temp);
1641 this->variables.push_tail(storage);
1642
1643 this->next_temp += type_size(param->type);
1644 }
1645
1646 if (!sig->return_type->is_void()) {
1647 entry->return_reg = get_temp(sig->return_type);
1648 } else {
1649 entry->return_reg = ir_to_mesa_undef;
1650 }
1651
1652 this->function_signatures.push_tail(entry);
1653 return entry;
1654 }
1655
1656 void
1657 ir_to_mesa_visitor::visit(ir_call *ir)
1658 {
1659 ir_to_mesa_instruction *call_inst;
1660 ir_function_signature *sig = ir->get_callee();
1661 function_entry *entry = get_function_signature(sig);
1662 int i;
1663
1664 /* Process in parameters. */
1665 exec_list_iterator sig_iter = sig->parameters.iterator();
1666 foreach_iter(exec_list_iterator, iter, *ir) {
1667 ir_rvalue *param_rval = (ir_rvalue *)iter.get();
1668 ir_variable *param = (ir_variable *)sig_iter.get();
1669
1670 if (param->mode == ir_var_in ||
1671 param->mode == ir_var_inout) {
1672 variable_storage *storage = find_variable_storage(param);
1673 assert(storage);
1674
1675 param_rval->accept(this);
1676 ir_to_mesa_src_reg r = this->result;
1677
1678 ir_to_mesa_dst_reg l;
1679 l.file = storage->file;
1680 l.index = storage->index;
1681 l.reladdr = NULL;
1682 l.writemask = WRITEMASK_XYZW;
1683 l.cond_mask = COND_TR;
1684
1685 for (i = 0; i < type_size(param->type); i++) {
1686 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1687 l.index++;
1688 r.index++;
1689 }
1690 }
1691
1692 sig_iter.next();
1693 }
1694 assert(!sig_iter.has_next());
1695
1696 /* Emit call instruction */
1697 call_inst = ir_to_mesa_emit_op1(ir, OPCODE_CAL,
1698 ir_to_mesa_undef_dst, ir_to_mesa_undef);
1699 call_inst->function = entry;
1700
1701 /* Process out parameters. */
1702 sig_iter = sig->parameters.iterator();
1703 foreach_iter(exec_list_iterator, iter, *ir) {
1704 ir_rvalue *param_rval = (ir_rvalue *)iter.get();
1705 ir_variable *param = (ir_variable *)sig_iter.get();
1706
1707 if (param->mode == ir_var_out ||
1708 param->mode == ir_var_inout) {
1709 variable_storage *storage = find_variable_storage(param);
1710 assert(storage);
1711
1712 ir_to_mesa_src_reg r;
1713 r.file = storage->file;
1714 r.index = storage->index;
1715 r.reladdr = NULL;
1716 r.swizzle = SWIZZLE_NOOP;
1717 r.negate = 0;
1718
1719 param_rval->accept(this);
1720 ir_to_mesa_dst_reg l = ir_to_mesa_dst_reg_from_src(this->result);
1721
1722 for (i = 0; i < type_size(param->type); i++) {
1723 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1724 l.index++;
1725 r.index++;
1726 }
1727 }
1728
1729 sig_iter.next();
1730 }
1731 assert(!sig_iter.has_next());
1732
1733 /* Process return value. */
1734 this->result = entry->return_reg;
1735 }
1736
1737 void
1738 ir_to_mesa_visitor::visit(ir_texture *ir)
1739 {
1740 ir_to_mesa_src_reg result_src, coord, lod_info, projector;
1741 ir_to_mesa_dst_reg result_dst, coord_dst;
1742 ir_to_mesa_instruction *inst = NULL;
1743 prog_opcode opcode = OPCODE_NOP;
1744
1745 ir->coordinate->accept(this);
1746
1747 /* Put our coords in a temp. We'll need to modify them for shadow,
1748 * projection, or LOD, so the only case we'd use it as is is if
1749 * we're doing plain old texturing. Mesa IR optimization should
1750 * handle cleaning up our mess in that case.
1751 */
1752 coord = get_temp(glsl_type::vec4_type);
1753 coord_dst = ir_to_mesa_dst_reg_from_src(coord);
1754 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst,
1755 this->result);
1756
1757 if (ir->projector) {
1758 ir->projector->accept(this);
1759 projector = this->result;
1760 }
1761
1762 /* Storage for our result. Ideally for an assignment we'd be using
1763 * the actual storage for the result here, instead.
1764 */
1765 result_src = get_temp(glsl_type::vec4_type);
1766 result_dst = ir_to_mesa_dst_reg_from_src(result_src);
1767
1768 switch (ir->op) {
1769 case ir_tex:
1770 opcode = OPCODE_TEX;
1771 break;
1772 case ir_txb:
1773 opcode = OPCODE_TXB;
1774 ir->lod_info.bias->accept(this);
1775 lod_info = this->result;
1776 break;
1777 case ir_txl:
1778 opcode = OPCODE_TXL;
1779 ir->lod_info.lod->accept(this);
1780 lod_info = this->result;
1781 break;
1782 case ir_txd:
1783 case ir_txf:
1784 assert(!"GLSL 1.30 features unsupported");
1785 break;
1786 }
1787
1788 if (ir->projector) {
1789 if (opcode == OPCODE_TEX) {
1790 /* Slot the projector in as the last component of the coord. */
1791 coord_dst.writemask = WRITEMASK_W;
1792 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, projector);
1793 coord_dst.writemask = WRITEMASK_XYZW;
1794 opcode = OPCODE_TXP;
1795 } else {
1796 ir_to_mesa_src_reg coord_w = coord;
1797 coord_w.swizzle = SWIZZLE_WWWW;
1798
1799 /* For the other TEX opcodes there's no projective version
1800 * since the last slot is taken up by lod info. Do the
1801 * projective divide now.
1802 */
1803 coord_dst.writemask = WRITEMASK_W;
1804 ir_to_mesa_emit_op1(ir, OPCODE_RCP, coord_dst, projector);
1805
1806 coord_dst.writemask = WRITEMASK_XYZ;
1807 ir_to_mesa_emit_op2(ir, OPCODE_MUL, coord_dst, coord, coord_w);
1808
1809 coord_dst.writemask = WRITEMASK_XYZW;
1810 coord.swizzle = SWIZZLE_XYZW;
1811 }
1812 }
1813
1814 if (ir->shadow_comparitor) {
1815 /* Slot the shadow value in as the second to last component of the
1816 * coord.
1817 */
1818 ir->shadow_comparitor->accept(this);
1819 coord_dst.writemask = WRITEMASK_Z;
1820 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, this->result);
1821 coord_dst.writemask = WRITEMASK_XYZW;
1822 }
1823
1824 if (opcode == OPCODE_TXL || opcode == OPCODE_TXB) {
1825 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
1826 coord_dst.writemask = WRITEMASK_W;
1827 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, lod_info);
1828 coord_dst.writemask = WRITEMASK_XYZW;
1829 }
1830
1831 inst = ir_to_mesa_emit_op1(ir, opcode, result_dst, coord);
1832
1833 if (ir->shadow_comparitor)
1834 inst->tex_shadow = GL_TRUE;
1835
1836 inst->sampler = _mesa_get_sampler_uniform_value(ir->sampler,
1837 this->shader_program,
1838 this->prog);
1839
1840 const glsl_type *sampler_type = ir->sampler->type;
1841
1842 switch (sampler_type->sampler_dimensionality) {
1843 case GLSL_SAMPLER_DIM_1D:
1844 inst->tex_target = (sampler_type->sampler_array)
1845 ? TEXTURE_1D_ARRAY_INDEX : TEXTURE_1D_INDEX;
1846 break;
1847 case GLSL_SAMPLER_DIM_2D:
1848 inst->tex_target = (sampler_type->sampler_array)
1849 ? TEXTURE_2D_ARRAY_INDEX : TEXTURE_2D_INDEX;
1850 break;
1851 case GLSL_SAMPLER_DIM_3D:
1852 inst->tex_target = TEXTURE_3D_INDEX;
1853 break;
1854 case GLSL_SAMPLER_DIM_CUBE:
1855 inst->tex_target = TEXTURE_CUBE_INDEX;
1856 break;
1857 case GLSL_SAMPLER_DIM_RECT:
1858 inst->tex_target = TEXTURE_RECT_INDEX;
1859 break;
1860 case GLSL_SAMPLER_DIM_BUF:
1861 assert(!"FINISHME: Implement ARB_texture_buffer_object");
1862 break;
1863 default:
1864 assert(!"Should not get here.");
1865 }
1866
1867 this->result = result_src;
1868 }
1869
1870 void
1871 ir_to_mesa_visitor::visit(ir_return *ir)
1872 {
1873 if (ir->get_value()) {
1874 ir_to_mesa_dst_reg l;
1875 int i;
1876
1877 assert(current_function);
1878
1879 ir->get_value()->accept(this);
1880 ir_to_mesa_src_reg r = this->result;
1881
1882 l = ir_to_mesa_dst_reg_from_src(current_function->return_reg);
1883
1884 for (i = 0; i < type_size(current_function->sig->return_type); i++) {
1885 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1886 l.index++;
1887 r.index++;
1888 }
1889 }
1890
1891 ir_to_mesa_emit_op0(ir, OPCODE_RET);
1892 }
1893
1894 void
1895 ir_to_mesa_visitor::visit(ir_discard *ir)
1896 {
1897 struct gl_fragment_program *fp = (struct gl_fragment_program *)this->prog;
1898
1899 assert(ir->condition == NULL); /* FINISHME */
1900
1901 ir_to_mesa_emit_op0(ir, OPCODE_KIL_NV);
1902 fp->UsesKill = GL_TRUE;
1903 }
1904
1905 void
1906 ir_to_mesa_visitor::visit(ir_if *ir)
1907 {
1908 ir_to_mesa_instruction *cond_inst, *if_inst, *else_inst = NULL;
1909 ir_to_mesa_instruction *prev_inst;
1910
1911 prev_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1912
1913 ir->condition->accept(this);
1914 assert(this->result.file != PROGRAM_UNDEFINED);
1915
1916 if (this->options->EmitCondCodes) {
1917 cond_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1918
1919 /* See if we actually generated any instruction for generating
1920 * the condition. If not, then cook up a move to a temp so we
1921 * have something to set cond_update on.
1922 */
1923 if (cond_inst == prev_inst) {
1924 ir_to_mesa_src_reg temp = get_temp(glsl_type::bool_type);
1925 cond_inst = ir_to_mesa_emit_op1(ir->condition, OPCODE_MOV,
1926 ir_to_mesa_dst_reg_from_src(temp),
1927 result);
1928 }
1929 cond_inst->cond_update = GL_TRUE;
1930
1931 if_inst = ir_to_mesa_emit_op0(ir->condition, OPCODE_IF);
1932 if_inst->dst_reg.cond_mask = COND_NE;
1933 } else {
1934 if_inst = ir_to_mesa_emit_op1(ir->condition,
1935 OPCODE_IF, ir_to_mesa_undef_dst,
1936 this->result);
1937 }
1938
1939 this->instructions.push_tail(if_inst);
1940
1941 visit_exec_list(&ir->then_instructions, this);
1942
1943 if (!ir->else_instructions.is_empty()) {
1944 else_inst = ir_to_mesa_emit_op0(ir->condition, OPCODE_ELSE);
1945 visit_exec_list(&ir->else_instructions, this);
1946 }
1947
1948 if_inst = ir_to_mesa_emit_op1(ir->condition, OPCODE_ENDIF,
1949 ir_to_mesa_undef_dst, ir_to_mesa_undef);
1950 }
1951
1952 ir_to_mesa_visitor::ir_to_mesa_visitor()
1953 {
1954 result.file = PROGRAM_UNDEFINED;
1955 next_temp = 1;
1956 next_signature_id = 1;
1957 current_function = NULL;
1958 mem_ctx = talloc_new(NULL);
1959 }
1960
1961 ir_to_mesa_visitor::~ir_to_mesa_visitor()
1962 {
1963 talloc_free(mem_ctx);
1964 }
1965
1966 static struct prog_src_register
1967 mesa_src_reg_from_ir_src_reg(ir_to_mesa_src_reg reg)
1968 {
1969 struct prog_src_register mesa_reg;
1970
1971 mesa_reg.File = reg.file;
1972 assert(reg.index < (1 << INST_INDEX_BITS) - 1);
1973 mesa_reg.Index = reg.index;
1974 mesa_reg.Swizzle = reg.swizzle;
1975 mesa_reg.RelAddr = reg.reladdr != NULL;
1976 mesa_reg.Negate = reg.negate;
1977 mesa_reg.Abs = 0;
1978 mesa_reg.HasIndex2 = GL_FALSE;
1979 mesa_reg.RelAddr2 = 0;
1980 mesa_reg.Index2 = 0;
1981
1982 return mesa_reg;
1983 }
1984
1985 static void
1986 set_branchtargets(ir_to_mesa_visitor *v,
1987 struct prog_instruction *mesa_instructions,
1988 int num_instructions)
1989 {
1990 int if_count = 0, loop_count = 0;
1991 int *if_stack, *loop_stack;
1992 int if_stack_pos = 0, loop_stack_pos = 0;
1993 int i, j;
1994
1995 for (i = 0; i < num_instructions; i++) {
1996 switch (mesa_instructions[i].Opcode) {
1997 case OPCODE_IF:
1998 if_count++;
1999 break;
2000 case OPCODE_BGNLOOP:
2001 loop_count++;
2002 break;
2003 case OPCODE_BRK:
2004 case OPCODE_CONT:
2005 mesa_instructions[i].BranchTarget = -1;
2006 break;
2007 default:
2008 break;
2009 }
2010 }
2011
2012 if_stack = talloc_zero_array(v->mem_ctx, int, if_count);
2013 loop_stack = talloc_zero_array(v->mem_ctx, int, loop_count);
2014
2015 for (i = 0; i < num_instructions; i++) {
2016 switch (mesa_instructions[i].Opcode) {
2017 case OPCODE_IF:
2018 if_stack[if_stack_pos] = i;
2019 if_stack_pos++;
2020 break;
2021 case OPCODE_ELSE:
2022 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
2023 if_stack[if_stack_pos - 1] = i;
2024 break;
2025 case OPCODE_ENDIF:
2026 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
2027 if_stack_pos--;
2028 break;
2029 case OPCODE_BGNLOOP:
2030 loop_stack[loop_stack_pos] = i;
2031 loop_stack_pos++;
2032 break;
2033 case OPCODE_ENDLOOP:
2034 loop_stack_pos--;
2035 /* Rewrite any breaks/conts at this nesting level (haven't
2036 * already had a BranchTarget assigned) to point to the end
2037 * of the loop.
2038 */
2039 for (j = loop_stack[loop_stack_pos]; j < i; j++) {
2040 if (mesa_instructions[j].Opcode == OPCODE_BRK ||
2041 mesa_instructions[j].Opcode == OPCODE_CONT) {
2042 if (mesa_instructions[j].BranchTarget == -1) {
2043 mesa_instructions[j].BranchTarget = i;
2044 }
2045 }
2046 }
2047 /* The loop ends point at each other. */
2048 mesa_instructions[i].BranchTarget = loop_stack[loop_stack_pos];
2049 mesa_instructions[loop_stack[loop_stack_pos]].BranchTarget = i;
2050 break;
2051 case OPCODE_CAL:
2052 foreach_iter(exec_list_iterator, iter, v->function_signatures) {
2053 function_entry *entry = (function_entry *)iter.get();
2054
2055 if (entry->sig_id == mesa_instructions[i].BranchTarget) {
2056 mesa_instructions[i].BranchTarget = entry->inst;
2057 break;
2058 }
2059 }
2060 break;
2061 default:
2062 break;
2063 }
2064 }
2065 }
2066
2067 static void
2068 print_program(struct prog_instruction *mesa_instructions,
2069 ir_instruction **mesa_instruction_annotation,
2070 int num_instructions)
2071 {
2072 ir_instruction *last_ir = NULL;
2073 int i;
2074 int indent = 0;
2075
2076 for (i = 0; i < num_instructions; i++) {
2077 struct prog_instruction *mesa_inst = mesa_instructions + i;
2078 ir_instruction *ir = mesa_instruction_annotation[i];
2079
2080 fprintf(stdout, "%3d: ", i);
2081
2082 if (last_ir != ir && ir) {
2083 int j;
2084
2085 for (j = 0; j < indent; j++) {
2086 fprintf(stdout, " ");
2087 }
2088 ir->print();
2089 printf("\n");
2090 last_ir = ir;
2091
2092 fprintf(stdout, " "); /* line number spacing. */
2093 }
2094
2095 indent = _mesa_fprint_instruction_opt(stdout, mesa_inst, indent,
2096 PROG_PRINT_DEBUG, NULL);
2097 }
2098 }
2099
2100 static void
2101 count_resources(struct gl_program *prog)
2102 {
2103 unsigned int i;
2104
2105 prog->SamplersUsed = 0;
2106
2107 for (i = 0; i < prog->NumInstructions; i++) {
2108 struct prog_instruction *inst = &prog->Instructions[i];
2109
2110 if (_mesa_is_tex_instruction(inst->Opcode)) {
2111 prog->SamplerTargets[inst->TexSrcUnit] =
2112 (gl_texture_index)inst->TexSrcTarget;
2113 prog->SamplersUsed |= 1 << inst->TexSrcUnit;
2114 if (inst->TexShadow) {
2115 prog->ShadowSamplers |= 1 << inst->TexSrcUnit;
2116 }
2117 }
2118 }
2119
2120 _mesa_update_shader_textures_used(prog);
2121 }
2122
2123 struct uniform_sort {
2124 struct gl_uniform *u;
2125 int pos;
2126 };
2127
2128 /* The shader_program->Uniforms list is almost sorted in increasing
2129 * uniform->{Frag,Vert}Pos locations, but not quite when there are
2130 * uniforms shared between targets. We need to add parameters in
2131 * increasing order for the targets.
2132 */
2133 static int
2134 sort_uniforms(const void *a, const void *b)
2135 {
2136 struct uniform_sort *u1 = (struct uniform_sort *)a;
2137 struct uniform_sort *u2 = (struct uniform_sort *)b;
2138
2139 return u1->pos - u2->pos;
2140 }
2141
2142 /* Add the uniforms to the parameters. The linker chose locations
2143 * in our parameters lists (which weren't created yet), which the
2144 * uniforms code will use to poke values into our parameters list
2145 * when uniforms are updated.
2146 */
2147 static void
2148 add_uniforms_to_parameters_list(struct gl_shader_program *shader_program,
2149 struct gl_shader *shader,
2150 struct gl_program *prog)
2151 {
2152 unsigned int i;
2153 unsigned int next_sampler = 0, num_uniforms = 0;
2154 struct uniform_sort *sorted_uniforms;
2155
2156 sorted_uniforms = talloc_array(NULL, struct uniform_sort,
2157 shader_program->Uniforms->NumUniforms);
2158
2159 for (i = 0; i < shader_program->Uniforms->NumUniforms; i++) {
2160 struct gl_uniform *uniform = shader_program->Uniforms->Uniforms + i;
2161 int parameter_index = -1;
2162
2163 switch (shader->Type) {
2164 case GL_VERTEX_SHADER:
2165 parameter_index = uniform->VertPos;
2166 break;
2167 case GL_FRAGMENT_SHADER:
2168 parameter_index = uniform->FragPos;
2169 break;
2170 case GL_GEOMETRY_SHADER:
2171 parameter_index = uniform->GeomPos;
2172 break;
2173 }
2174
2175 /* Only add uniforms used in our target. */
2176 if (parameter_index != -1) {
2177 sorted_uniforms[num_uniforms].pos = parameter_index;
2178 sorted_uniforms[num_uniforms].u = uniform;
2179 num_uniforms++;
2180 }
2181 }
2182
2183 qsort(sorted_uniforms, num_uniforms, sizeof(struct uniform_sort),
2184 sort_uniforms);
2185
2186 for (i = 0; i < num_uniforms; i++) {
2187 struct gl_uniform *uniform = sorted_uniforms[i].u;
2188 int parameter_index = sorted_uniforms[i].pos;
2189 const glsl_type *type = uniform->Type;
2190 unsigned int size;
2191
2192 if (type->is_vector() ||
2193 type->is_scalar()) {
2194 size = type->vector_elements;
2195 } else {
2196 size = type_size(type) * 4;
2197 }
2198
2199 gl_register_file file;
2200 if (type->is_sampler() ||
2201 (type->is_array() && type->fields.array->is_sampler())) {
2202 file = PROGRAM_SAMPLER;
2203 } else {
2204 file = PROGRAM_UNIFORM;
2205 }
2206
2207 GLint index = _mesa_lookup_parameter_index(prog->Parameters, -1,
2208 uniform->Name);
2209
2210 if (index < 0) {
2211 index = _mesa_add_parameter(prog->Parameters, file,
2212 uniform->Name, size, type->gl_type,
2213 NULL, NULL, 0x0);
2214
2215 /* Sampler uniform values are stored in prog->SamplerUnits,
2216 * and the entry in that array is selected by this index we
2217 * store in ParameterValues[].
2218 */
2219 if (file == PROGRAM_SAMPLER) {
2220 for (unsigned int j = 0; j < size / 4; j++)
2221 prog->Parameters->ParameterValues[index + j][0] = next_sampler++;
2222 }
2223
2224 /* The location chosen in the Parameters list here (returned
2225 * from _mesa_add_uniform) has to match what the linker chose.
2226 */
2227 if (index != parameter_index) {
2228 fail_link(shader_program, "Allocation of uniform `%s' to target "
2229 "failed (%d vs %d)\n",
2230 uniform->Name, index, parameter_index);
2231 }
2232 }
2233 }
2234
2235 talloc_free(sorted_uniforms);
2236 }
2237
2238 static void
2239 set_uniform_initializer(struct gl_context *ctx, void *mem_ctx,
2240 struct gl_shader_program *shader_program,
2241 const char *name, const glsl_type *type,
2242 ir_constant *val)
2243 {
2244 if (type->is_record()) {
2245 ir_constant *field_constant;
2246
2247 field_constant = (ir_constant *)val->components.get_head();
2248
2249 for (unsigned int i = 0; i < type->length; i++) {
2250 const glsl_type *field_type = type->fields.structure[i].type;
2251 const char *field_name = talloc_asprintf(mem_ctx, "%s.%s", name,
2252 type->fields.structure[i].name);
2253 set_uniform_initializer(ctx, mem_ctx, shader_program, field_name,
2254 field_type, field_constant);
2255 field_constant = (ir_constant *)field_constant->next;
2256 }
2257 return;
2258 }
2259
2260 int loc = _mesa_get_uniform_location(ctx, shader_program, name);
2261
2262 if (loc == -1) {
2263 fail_link(shader_program,
2264 "Couldn't find uniform for initializer %s\n", name);
2265 return;
2266 }
2267
2268 for (unsigned int i = 0; i < (type->is_array() ? type->length : 1); i++) {
2269 ir_constant *element;
2270 const glsl_type *element_type;
2271 if (type->is_array()) {
2272 element = val->array_elements[i];
2273 element_type = type->fields.array;
2274 } else {
2275 element = val;
2276 element_type = type;
2277 }
2278
2279 void *values;
2280
2281 if (element_type->base_type == GLSL_TYPE_BOOL) {
2282 int *conv = talloc_array(mem_ctx, int, element_type->components());
2283 for (unsigned int j = 0; j < element_type->components(); j++) {
2284 conv[j] = element->value.b[j];
2285 }
2286 values = (void *)conv;
2287 element_type = glsl_type::get_instance(GLSL_TYPE_INT,
2288 element_type->vector_elements,
2289 1);
2290 } else {
2291 values = &element->value;
2292 }
2293
2294 if (element_type->is_matrix()) {
2295 _mesa_uniform_matrix(ctx, shader_program,
2296 element_type->matrix_columns,
2297 element_type->vector_elements,
2298 loc, 1, GL_FALSE, (GLfloat *)values);
2299 loc += element_type->matrix_columns;
2300 } else {
2301 _mesa_uniform(ctx, shader_program, loc, element_type->matrix_columns,
2302 values, element_type->gl_type);
2303 loc += type_size(element_type);
2304 }
2305 }
2306 }
2307
2308 static void
2309 set_uniform_initializers(struct gl_context *ctx,
2310 struct gl_shader_program *shader_program)
2311 {
2312 void *mem_ctx = NULL;
2313
2314 for (unsigned int i = 0; i < MESA_SHADER_TYPES; i++) {
2315 struct gl_shader *shader = shader_program->_LinkedShaders[i];
2316
2317 if (shader == NULL)
2318 continue;
2319
2320 foreach_iter(exec_list_iterator, iter, *shader->ir) {
2321 ir_instruction *ir = (ir_instruction *)iter.get();
2322 ir_variable *var = ir->as_variable();
2323
2324 if (!var || var->mode != ir_var_uniform || !var->constant_value)
2325 continue;
2326
2327 if (!mem_ctx)
2328 mem_ctx = talloc_new(NULL);
2329
2330 set_uniform_initializer(ctx, mem_ctx, shader_program, var->name,
2331 var->type, var->constant_value);
2332 }
2333 }
2334
2335 talloc_free(mem_ctx);
2336 }
2337
2338
2339 /**
2340 * Convert a shader's GLSL IR into a Mesa gl_program.
2341 */
2342 struct gl_program *
2343 get_mesa_program(struct gl_context *ctx, struct gl_shader_program *shader_program,
2344 struct gl_shader *shader)
2345 {
2346 ir_to_mesa_visitor v;
2347 struct prog_instruction *mesa_instructions, *mesa_inst;
2348 ir_instruction **mesa_instruction_annotation;
2349 int i;
2350 struct gl_program *prog;
2351 GLenum target;
2352 const char *target_string;
2353 GLboolean progress;
2354 struct gl_shader_compiler_options *options =
2355 &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(shader->Type)];
2356
2357 switch (shader->Type) {
2358 case GL_VERTEX_SHADER:
2359 target = GL_VERTEX_PROGRAM_ARB;
2360 target_string = "vertex";
2361 break;
2362 case GL_FRAGMENT_SHADER:
2363 target = GL_FRAGMENT_PROGRAM_ARB;
2364 target_string = "fragment";
2365 break;
2366 default:
2367 assert(!"should not be reached");
2368 return NULL;
2369 }
2370
2371 validate_ir_tree(shader->ir);
2372
2373 prog = ctx->Driver.NewProgram(ctx, target, shader_program->Name);
2374 if (!prog)
2375 return NULL;
2376 prog->Parameters = _mesa_new_parameter_list();
2377 prog->Varying = _mesa_new_parameter_list();
2378 prog->Attributes = _mesa_new_parameter_list();
2379 v.ctx = ctx;
2380 v.prog = prog;
2381 v.shader_program = shader_program;
2382 v.options = options;
2383
2384 add_uniforms_to_parameters_list(shader_program, shader, prog);
2385
2386 /* Emit Mesa IR for main(). */
2387 visit_exec_list(shader->ir, &v);
2388 v.ir_to_mesa_emit_op0(NULL, OPCODE_END);
2389
2390 /* Now emit bodies for any functions that were used. */
2391 do {
2392 progress = GL_FALSE;
2393
2394 foreach_iter(exec_list_iterator, iter, v.function_signatures) {
2395 function_entry *entry = (function_entry *)iter.get();
2396
2397 if (!entry->bgn_inst) {
2398 v.current_function = entry;
2399
2400 entry->bgn_inst = v.ir_to_mesa_emit_op0(NULL, OPCODE_BGNSUB);
2401 entry->bgn_inst->function = entry;
2402
2403 visit_exec_list(&entry->sig->body, &v);
2404
2405 ir_to_mesa_instruction *last;
2406 last = (ir_to_mesa_instruction *)v.instructions.get_tail();
2407 if (last->op != OPCODE_RET)
2408 v.ir_to_mesa_emit_op0(NULL, OPCODE_RET);
2409
2410 ir_to_mesa_instruction *end;
2411 end = v.ir_to_mesa_emit_op0(NULL, OPCODE_ENDSUB);
2412 end->function = entry;
2413
2414 progress = GL_TRUE;
2415 }
2416 }
2417 } while (progress);
2418
2419 prog->NumTemporaries = v.next_temp;
2420
2421 int num_instructions = 0;
2422 foreach_iter(exec_list_iterator, iter, v.instructions) {
2423 num_instructions++;
2424 }
2425
2426 mesa_instructions =
2427 (struct prog_instruction *)calloc(num_instructions,
2428 sizeof(*mesa_instructions));
2429 mesa_instruction_annotation = talloc_array(v.mem_ctx, ir_instruction *,
2430 num_instructions);
2431
2432 /* Convert ir_mesa_instructions into prog_instructions.
2433 */
2434 mesa_inst = mesa_instructions;
2435 i = 0;
2436 foreach_iter(exec_list_iterator, iter, v.instructions) {
2437 const ir_to_mesa_instruction *inst = (ir_to_mesa_instruction *)iter.get();
2438
2439 mesa_inst->Opcode = inst->op;
2440 mesa_inst->CondUpdate = inst->cond_update;
2441 mesa_inst->DstReg.File = inst->dst_reg.file;
2442 mesa_inst->DstReg.Index = inst->dst_reg.index;
2443 mesa_inst->DstReg.CondMask = inst->dst_reg.cond_mask;
2444 mesa_inst->DstReg.WriteMask = inst->dst_reg.writemask;
2445 mesa_inst->DstReg.RelAddr = inst->dst_reg.reladdr != NULL;
2446 mesa_inst->SrcReg[0] = mesa_src_reg_from_ir_src_reg(inst->src_reg[0]);
2447 mesa_inst->SrcReg[1] = mesa_src_reg_from_ir_src_reg(inst->src_reg[1]);
2448 mesa_inst->SrcReg[2] = mesa_src_reg_from_ir_src_reg(inst->src_reg[2]);
2449 mesa_inst->TexSrcUnit = inst->sampler;
2450 mesa_inst->TexSrcTarget = inst->tex_target;
2451 mesa_inst->TexShadow = inst->tex_shadow;
2452 mesa_instruction_annotation[i] = inst->ir;
2453
2454 /* Set IndirectRegisterFiles. */
2455 if (mesa_inst->DstReg.RelAddr)
2456 prog->IndirectRegisterFiles |= 1 << mesa_inst->DstReg.File;
2457
2458 /* Update program's bitmask of indirectly accessed register files */
2459 for (unsigned src = 0; src < 3; src++)
2460 if (mesa_inst->SrcReg[src].RelAddr)
2461 prog->IndirectRegisterFiles |= 1 << mesa_inst->SrcReg[src].File;
2462
2463 if (options->EmitNoIfs && mesa_inst->Opcode == OPCODE_IF) {
2464 fail_link(shader_program, "Couldn't flatten if statement\n");
2465 }
2466
2467 switch (mesa_inst->Opcode) {
2468 case OPCODE_BGNSUB:
2469 inst->function->inst = i;
2470 mesa_inst->Comment = strdup(inst->function->sig->function_name());
2471 break;
2472 case OPCODE_ENDSUB:
2473 mesa_inst->Comment = strdup(inst->function->sig->function_name());
2474 break;
2475 case OPCODE_CAL:
2476 mesa_inst->BranchTarget = inst->function->sig_id; /* rewritten later */
2477 break;
2478 case OPCODE_ARL:
2479 prog->NumAddressRegs = 1;
2480 break;
2481 default:
2482 break;
2483 }
2484
2485 mesa_inst++;
2486 i++;
2487 }
2488
2489 set_branchtargets(&v, mesa_instructions, num_instructions);
2490
2491 if (ctx->Shader.Flags & GLSL_DUMP) {
2492 printf("\n");
2493 printf("GLSL IR for linked %s program %d:\n", target_string,
2494 shader_program->Name);
2495 _mesa_print_ir(shader->ir, NULL);
2496 printf("\n");
2497 printf("\n");
2498 printf("Mesa IR for linked %s program %d:\n", target_string,
2499 shader_program->Name);
2500 print_program(mesa_instructions, mesa_instruction_annotation,
2501 num_instructions);
2502 }
2503
2504 prog->Instructions = mesa_instructions;
2505 prog->NumInstructions = num_instructions;
2506
2507 do_set_program_inouts(shader->ir, prog);
2508 count_resources(prog);
2509
2510 _mesa_reference_program(ctx, &shader->Program, prog);
2511
2512 if ((ctx->Shader.Flags & GLSL_NO_OPT) == 0) {
2513 _mesa_optimize_program(ctx, prog);
2514 }
2515
2516 return prog;
2517 }
2518
2519 extern "C" {
2520
2521 /**
2522 * Called via ctx->Driver.CompilerShader().
2523 * This is a no-op.
2524 * XXX can we remove the ctx->Driver.CompileShader() hook?
2525 */
2526 GLboolean
2527 _mesa_ir_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
2528 {
2529 assert(shader->CompileStatus);
2530 (void) ctx;
2531
2532 return GL_TRUE;
2533 }
2534
2535
2536 /**
2537 * Link a shader.
2538 * Called via ctx->Driver.LinkShader()
2539 * This actually involves converting GLSL IR into Mesa gl_programs with
2540 * code lowering and other optimizations.
2541 */
2542 GLboolean
2543 _mesa_ir_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
2544 {
2545 assert(prog->LinkStatus);
2546
2547 for (unsigned i = 0; i < MESA_SHADER_TYPES; i++) {
2548 if (prog->_LinkedShaders[i] == NULL)
2549 continue;
2550
2551 bool progress;
2552 exec_list *ir = prog->_LinkedShaders[i]->ir;
2553 const struct gl_shader_compiler_options *options =
2554 &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(prog->_LinkedShaders[i]->Type)];
2555
2556 do {
2557 progress = false;
2558
2559 /* Lowering */
2560 do_mat_op_to_vec(ir);
2561 do_mod_to_fract(ir);
2562 do_div_to_mul_rcp(ir);
2563 do_explog_to_explog2(ir);
2564
2565 progress = do_lower_jumps(ir, true, true, options->EmitNoMainReturn, options->EmitNoCont, options->EmitNoLoops) || progress;
2566
2567 progress = do_common_optimization(ir, true, options->MaxUnrollIterations) || progress;
2568
2569 if (options->EmitNoIfs)
2570 progress = do_if_to_cond_assign(ir) || progress;
2571
2572 if (options->EmitNoNoise)
2573 progress = lower_noise(ir) || progress;
2574
2575 /* If there are forms of indirect addressing that the driver
2576 * cannot handle, perform the lowering pass.
2577 */
2578 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput
2579 || options->EmitNoIndirectTemp || options->EmitNoIndirectUniform)
2580 progress =
2581 lower_variable_index_to_cond_assign(ir,
2582 options->EmitNoIndirectInput,
2583 options->EmitNoIndirectOutput,
2584 options->EmitNoIndirectTemp,
2585 options->EmitNoIndirectUniform)
2586 || progress;
2587
2588 progress = do_vec_index_to_cond_assign(ir) || progress;
2589 } while (progress);
2590
2591 validate_ir_tree(ir);
2592 }
2593
2594 for (unsigned i = 0; i < MESA_SHADER_TYPES; i++) {
2595 struct gl_program *linked_prog;
2596 bool ok = true;
2597
2598 if (prog->_LinkedShaders[i] == NULL)
2599 continue;
2600
2601 linked_prog = get_mesa_program(ctx, prog, prog->_LinkedShaders[i]);
2602
2603 switch (prog->_LinkedShaders[i]->Type) {
2604 case GL_VERTEX_SHADER:
2605 _mesa_reference_vertprog(ctx, &prog->VertexProgram,
2606 (struct gl_vertex_program *)linked_prog);
2607 ok = ctx->Driver.ProgramStringNotify(ctx, GL_VERTEX_PROGRAM_ARB,
2608 linked_prog);
2609 break;
2610 case GL_FRAGMENT_SHADER:
2611 _mesa_reference_fragprog(ctx, &prog->FragmentProgram,
2612 (struct gl_fragment_program *)linked_prog);
2613 ok = ctx->Driver.ProgramStringNotify(ctx, GL_FRAGMENT_PROGRAM_ARB,
2614 linked_prog);
2615 break;
2616 }
2617 if (!ok) {
2618 return GL_FALSE;
2619 }
2620 _mesa_reference_program(ctx, &linked_prog, NULL);
2621 }
2622
2623 return GL_TRUE;
2624 }
2625
2626
2627 /**
2628 * Compile a GLSL shader. Called via glCompileShader().
2629 */
2630 void
2631 _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
2632 {
2633 struct _mesa_glsl_parse_state *state =
2634 new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shader);
2635
2636 const char *source = shader->Source;
2637 /* Check if the user called glCompileShader without first calling
2638 * glShaderSource. This should fail to compile, but not raise a GL_ERROR.
2639 */
2640 if (source == NULL) {
2641 shader->CompileStatus = GL_FALSE;
2642 return;
2643 }
2644
2645 state->error = preprocess(state, &source, &state->info_log,
2646 &ctx->Extensions, ctx->API);
2647
2648 if (ctx->Shader.Flags & GLSL_DUMP) {
2649 printf("GLSL source for shader %d:\n", shader->Name);
2650 printf("%s\n", shader->Source);
2651 }
2652
2653 if (!state->error) {
2654 _mesa_glsl_lexer_ctor(state, source);
2655 _mesa_glsl_parse(state);
2656 _mesa_glsl_lexer_dtor(state);
2657 }
2658
2659 talloc_free(shader->ir);
2660 shader->ir = new(shader) exec_list;
2661 if (!state->error && !state->translation_unit.is_empty())
2662 _mesa_ast_to_hir(shader->ir, state);
2663
2664 if (!state->error && !shader->ir->is_empty()) {
2665 validate_ir_tree(shader->ir);
2666
2667 /* Do some optimization at compile time to reduce shader IR size
2668 * and reduce later work if the same shader is linked multiple times
2669 */
2670 while (do_common_optimization(shader->ir, false, 32))
2671 ;
2672
2673 validate_ir_tree(shader->ir);
2674 }
2675
2676 shader->symbols = state->symbols;
2677
2678 shader->CompileStatus = !state->error;
2679 shader->InfoLog = state->info_log;
2680 shader->Version = state->language_version;
2681 memcpy(shader->builtins_to_link, state->builtins_to_link,
2682 sizeof(shader->builtins_to_link[0]) * state->num_builtins_to_link);
2683 shader->num_builtins_to_link = state->num_builtins_to_link;
2684
2685 if (ctx->Shader.Flags & GLSL_LOG) {
2686 _mesa_write_shader_to_file(shader);
2687 }
2688
2689 if (ctx->Shader.Flags & GLSL_DUMP) {
2690 if (shader->CompileStatus) {
2691 printf("GLSL IR for shader %d:\n", shader->Name);
2692 _mesa_print_ir(shader->ir, NULL);
2693 printf("\n\n");
2694 } else {
2695 printf("GLSL shader %d failed to compile.\n", shader->Name);
2696 }
2697 if (shader->InfoLog && shader->InfoLog[0] != 0) {
2698 printf("GLSL shader %d info log:\n", shader->Name);
2699 printf("%s\n", shader->InfoLog);
2700 }
2701 }
2702
2703 /* Retain any live IR, but trash the rest. */
2704 reparent_ir(shader->ir, shader->ir);
2705
2706 talloc_free(state);
2707
2708 if (shader->CompileStatus) {
2709 if (!ctx->Driver.CompileShader(ctx, shader))
2710 shader->CompileStatus = GL_FALSE;
2711 }
2712 }
2713
2714
2715 /**
2716 * Link a GLSL shader program. Called via glLinkProgram().
2717 */
2718 void
2719 _mesa_glsl_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
2720 {
2721 unsigned int i;
2722
2723 _mesa_clear_shader_program_data(ctx, prog);
2724
2725 prog->LinkStatus = GL_TRUE;
2726
2727 for (i = 0; i < prog->NumShaders; i++) {
2728 if (!prog->Shaders[i]->CompileStatus) {
2729 fail_link(prog, "linking with uncompiled shader");
2730 prog->LinkStatus = GL_FALSE;
2731 }
2732 }
2733
2734 prog->Varying = _mesa_new_parameter_list();
2735 _mesa_reference_vertprog(ctx, &prog->VertexProgram, NULL);
2736 _mesa_reference_fragprog(ctx, &prog->FragmentProgram, NULL);
2737
2738 if (prog->LinkStatus) {
2739 link_shaders(ctx, prog);
2740 }
2741
2742 if (prog->LinkStatus) {
2743 if (!ctx->Driver.LinkShader(ctx, prog)) {
2744 prog->LinkStatus = GL_FALSE;
2745 }
2746 }
2747
2748 set_uniform_initializers(ctx, prog);
2749
2750 if (ctx->Shader.Flags & GLSL_DUMP) {
2751 if (!prog->LinkStatus) {
2752 printf("GLSL shader program %d failed to link\n", prog->Name);
2753 }
2754
2755 if (prog->InfoLog && prog->InfoLog[0] != 0) {
2756 printf("GLSL shader program %d info log:\n", prog->Name);
2757 printf("%s\n", prog->InfoLog);
2758 }
2759 }
2760 }
2761
2762 } /* extern "C" */