Merge branch 'llvm-cliptest-viewport'
[mesa.git] / src / mesa / program / ir_to_mesa.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 /**
27 * \file ir_to_mesa.cpp
28 *
29 * Translate GLSL IR to Mesa's gl_program representation.
30 */
31
32 #include <stdio.h>
33 #include "main/compiler.h"
34 #include "ir.h"
35 #include "ir_visitor.h"
36 #include "ir_print_visitor.h"
37 #include "ir_expression_flattening.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
42 #include "ast.h"
43
44 extern "C" {
45 #include "main/mtypes.h"
46 #include "main/shaderapi.h"
47 #include "main/shaderobj.h"
48 #include "main/uniforms.h"
49 #include "program/hash_table.h"
50 #include "program/prog_instruction.h"
51 #include "program/prog_optimize.h"
52 #include "program/prog_print.h"
53 #include "program/program.h"
54 #include "program/prog_uniform.h"
55 #include "program/prog_parameter.h"
56 #include "program/sampler.h"
57 }
58
59 static int swizzle_for_size(int size);
60
61 /**
62 * This struct is a corresponding struct to Mesa prog_src_register, with
63 * wider fields.
64 */
65 typedef struct ir_to_mesa_src_reg {
66 ir_to_mesa_src_reg(int file, int index, const glsl_type *type)
67 {
68 this->file = file;
69 this->index = index;
70 if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
71 this->swizzle = swizzle_for_size(type->vector_elements);
72 else
73 this->swizzle = SWIZZLE_XYZW;
74 this->negate = 0;
75 this->reladdr = NULL;
76 }
77
78 ir_to_mesa_src_reg()
79 {
80 this->file = PROGRAM_UNDEFINED;
81 this->index = 0;
82 this->swizzle = 0;
83 this->negate = 0;
84 this->reladdr = NULL;
85 }
86
87 int file; /**< PROGRAM_* from Mesa */
88 int index; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
89 GLuint swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
90 int negate; /**< NEGATE_XYZW mask from mesa */
91 /** Register index should be offset by the integer in this reg. */
92 ir_to_mesa_src_reg *reladdr;
93 } ir_to_mesa_src_reg;
94
95 typedef struct ir_to_mesa_dst_reg {
96 int file; /**< PROGRAM_* from Mesa */
97 int index; /**< temporary index, VERT_ATTRIB_*, FRAG_ATTRIB_*, etc. */
98 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
99 GLuint cond_mask:4;
100 /** Register index should be offset by the integer in this reg. */
101 ir_to_mesa_src_reg *reladdr;
102 } ir_to_mesa_dst_reg;
103
104 extern ir_to_mesa_src_reg ir_to_mesa_undef;
105
106 class ir_to_mesa_instruction : public exec_node {
107 public:
108 /* Callers of this talloc-based new need not call delete. It's
109 * easier to just talloc_free 'ctx' (or any of its ancestors). */
110 static void* operator new(size_t size, void *ctx)
111 {
112 void *node;
113
114 node = talloc_zero_size(ctx, size);
115 assert(node != NULL);
116
117 return node;
118 }
119
120 enum prog_opcode op;
121 ir_to_mesa_dst_reg dst_reg;
122 ir_to_mesa_src_reg src_reg[3];
123 /** Pointer to the ir source this tree came from for debugging */
124 ir_instruction *ir;
125 GLboolean cond_update;
126 int sampler; /**< sampler index */
127 int tex_target; /**< One of TEXTURE_*_INDEX */
128 GLboolean tex_shadow;
129
130 class function_entry *function; /* Set on OPCODE_CAL or OPCODE_BGNSUB */
131 };
132
133 class variable_storage : public exec_node {
134 public:
135 variable_storage(ir_variable *var, int file, int index)
136 : file(file), index(index), var(var)
137 {
138 /* empty */
139 }
140
141 int file;
142 int index;
143 ir_variable *var; /* variable that maps to this, if any */
144 };
145
146 class function_entry : public exec_node {
147 public:
148 ir_function_signature *sig;
149
150 /**
151 * identifier of this function signature used by the program.
152 *
153 * At the point that Mesa instructions for function calls are
154 * generated, we don't know the address of the first instruction of
155 * the function body. So we make the BranchTarget that is called a
156 * small integer and rewrite them during set_branchtargets().
157 */
158 int sig_id;
159
160 /**
161 * Pointer to first instruction of the function body.
162 *
163 * Set during function body emits after main() is processed.
164 */
165 ir_to_mesa_instruction *bgn_inst;
166
167 /**
168 * Index of the first instruction of the function body in actual
169 * Mesa IR.
170 *
171 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
172 */
173 int inst;
174
175 /** Storage for the return value. */
176 ir_to_mesa_src_reg return_reg;
177 };
178
179 class ir_to_mesa_visitor : public ir_visitor {
180 public:
181 ir_to_mesa_visitor();
182 ~ir_to_mesa_visitor();
183
184 function_entry *current_function;
185
186 struct gl_context *ctx;
187 struct gl_program *prog;
188 struct gl_shader_program *shader_program;
189 struct gl_shader_compiler_options *options;
190
191 int next_temp;
192
193 variable_storage *find_variable_storage(ir_variable *var);
194
195 function_entry *get_function_signature(ir_function_signature *sig);
196
197 ir_to_mesa_src_reg get_temp(const glsl_type *type);
198 void reladdr_to_temp(ir_instruction *ir,
199 ir_to_mesa_src_reg *reg, int *num_reladdr);
200
201 struct ir_to_mesa_src_reg src_reg_for_float(float val);
202
203 /**
204 * \name Visit methods
205 *
206 * As typical for the visitor pattern, there must be one \c visit method for
207 * each concrete subclass of \c ir_instruction. Virtual base classes within
208 * the hierarchy should not have \c visit methods.
209 */
210 /*@{*/
211 virtual void visit(ir_variable *);
212 virtual void visit(ir_loop *);
213 virtual void visit(ir_loop_jump *);
214 virtual void visit(ir_function_signature *);
215 virtual void visit(ir_function *);
216 virtual void visit(ir_expression *);
217 virtual void visit(ir_swizzle *);
218 virtual void visit(ir_dereference_variable *);
219 virtual void visit(ir_dereference_array *);
220 virtual void visit(ir_dereference_record *);
221 virtual void visit(ir_assignment *);
222 virtual void visit(ir_constant *);
223 virtual void visit(ir_call *);
224 virtual void visit(ir_return *);
225 virtual void visit(ir_discard *);
226 virtual void visit(ir_texture *);
227 virtual void visit(ir_if *);
228 /*@}*/
229
230 struct ir_to_mesa_src_reg result;
231
232 /** List of variable_storage */
233 exec_list variables;
234
235 /** List of function_entry */
236 exec_list function_signatures;
237 int next_signature_id;
238
239 /** List of ir_to_mesa_instruction */
240 exec_list instructions;
241
242 ir_to_mesa_instruction *ir_to_mesa_emit_op0(ir_instruction *ir,
243 enum prog_opcode op);
244
245 ir_to_mesa_instruction *ir_to_mesa_emit_op1(ir_instruction *ir,
246 enum prog_opcode op,
247 ir_to_mesa_dst_reg dst,
248 ir_to_mesa_src_reg src0);
249
250 ir_to_mesa_instruction *ir_to_mesa_emit_op2(ir_instruction *ir,
251 enum prog_opcode op,
252 ir_to_mesa_dst_reg dst,
253 ir_to_mesa_src_reg src0,
254 ir_to_mesa_src_reg src1);
255
256 ir_to_mesa_instruction *ir_to_mesa_emit_op3(ir_instruction *ir,
257 enum prog_opcode op,
258 ir_to_mesa_dst_reg dst,
259 ir_to_mesa_src_reg src0,
260 ir_to_mesa_src_reg src1,
261 ir_to_mesa_src_reg src2);
262
263 void ir_to_mesa_emit_scalar_op1(ir_instruction *ir,
264 enum prog_opcode op,
265 ir_to_mesa_dst_reg dst,
266 ir_to_mesa_src_reg src0);
267
268 void ir_to_mesa_emit_scalar_op2(ir_instruction *ir,
269 enum prog_opcode op,
270 ir_to_mesa_dst_reg dst,
271 ir_to_mesa_src_reg src0,
272 ir_to_mesa_src_reg src1);
273
274 GLboolean try_emit_mad(ir_expression *ir,
275 int mul_operand);
276
277 void *mem_ctx;
278 };
279
280 ir_to_mesa_src_reg ir_to_mesa_undef = ir_to_mesa_src_reg(PROGRAM_UNDEFINED, 0, NULL);
281
282 ir_to_mesa_dst_reg ir_to_mesa_undef_dst = {
283 PROGRAM_UNDEFINED, 0, SWIZZLE_NOOP, COND_TR, NULL,
284 };
285
286 ir_to_mesa_dst_reg ir_to_mesa_address_reg = {
287 PROGRAM_ADDRESS, 0, WRITEMASK_X, COND_TR, NULL
288 };
289
290 static void
291 fail_link(struct gl_shader_program *prog, const char *fmt, ...) PRINTFLIKE(2, 3);
292
293 static void
294 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
295 {
296 va_list args;
297 va_start(args, fmt);
298 prog->InfoLog = talloc_vasprintf_append(prog->InfoLog, fmt, args);
299 va_end(args);
300
301 prog->LinkStatus = GL_FALSE;
302 }
303
304 static int
305 swizzle_for_size(int size)
306 {
307 int size_swizzles[4] = {
308 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
309 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
310 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
311 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
312 };
313
314 assert((size >= 1) && (size <= 4));
315 return size_swizzles[size - 1];
316 }
317
318 ir_to_mesa_instruction *
319 ir_to_mesa_visitor::ir_to_mesa_emit_op3(ir_instruction *ir,
320 enum prog_opcode op,
321 ir_to_mesa_dst_reg dst,
322 ir_to_mesa_src_reg src0,
323 ir_to_mesa_src_reg src1,
324 ir_to_mesa_src_reg src2)
325 {
326 ir_to_mesa_instruction *inst = new(mem_ctx) ir_to_mesa_instruction();
327 int num_reladdr = 0;
328
329 /* If we have to do relative addressing, we want to load the ARL
330 * reg directly for one of the regs, and preload the other reladdr
331 * sources into temps.
332 */
333 num_reladdr += dst.reladdr != NULL;
334 num_reladdr += src0.reladdr != NULL;
335 num_reladdr += src1.reladdr != NULL;
336 num_reladdr += src2.reladdr != NULL;
337
338 reladdr_to_temp(ir, &src2, &num_reladdr);
339 reladdr_to_temp(ir, &src1, &num_reladdr);
340 reladdr_to_temp(ir, &src0, &num_reladdr);
341
342 if (dst.reladdr) {
343 ir_to_mesa_emit_op1(ir, OPCODE_ARL, ir_to_mesa_address_reg,
344 *dst.reladdr);
345
346 num_reladdr--;
347 }
348 assert(num_reladdr == 0);
349
350 inst->op = op;
351 inst->dst_reg = dst;
352 inst->src_reg[0] = src0;
353 inst->src_reg[1] = src1;
354 inst->src_reg[2] = src2;
355 inst->ir = ir;
356
357 inst->function = NULL;
358
359 this->instructions.push_tail(inst);
360
361 return inst;
362 }
363
364
365 ir_to_mesa_instruction *
366 ir_to_mesa_visitor::ir_to_mesa_emit_op2(ir_instruction *ir,
367 enum prog_opcode op,
368 ir_to_mesa_dst_reg dst,
369 ir_to_mesa_src_reg src0,
370 ir_to_mesa_src_reg src1)
371 {
372 return ir_to_mesa_emit_op3(ir, op, dst, src0, src1, ir_to_mesa_undef);
373 }
374
375 ir_to_mesa_instruction *
376 ir_to_mesa_visitor::ir_to_mesa_emit_op1(ir_instruction *ir,
377 enum prog_opcode op,
378 ir_to_mesa_dst_reg dst,
379 ir_to_mesa_src_reg src0)
380 {
381 assert(dst.writemask != 0);
382 return ir_to_mesa_emit_op3(ir, op, dst,
383 src0, ir_to_mesa_undef, ir_to_mesa_undef);
384 }
385
386 ir_to_mesa_instruction *
387 ir_to_mesa_visitor::ir_to_mesa_emit_op0(ir_instruction *ir,
388 enum prog_opcode op)
389 {
390 return ir_to_mesa_emit_op3(ir, op, ir_to_mesa_undef_dst,
391 ir_to_mesa_undef,
392 ir_to_mesa_undef,
393 ir_to_mesa_undef);
394 }
395
396 inline ir_to_mesa_dst_reg
397 ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg reg)
398 {
399 ir_to_mesa_dst_reg dst_reg;
400
401 dst_reg.file = reg.file;
402 dst_reg.index = reg.index;
403 dst_reg.writemask = WRITEMASK_XYZW;
404 dst_reg.cond_mask = COND_TR;
405 dst_reg.reladdr = reg.reladdr;
406
407 return dst_reg;
408 }
409
410 inline ir_to_mesa_src_reg
411 ir_to_mesa_src_reg_from_dst(ir_to_mesa_dst_reg reg)
412 {
413 return ir_to_mesa_src_reg(reg.file, reg.index, NULL);
414 }
415
416 /**
417 * Emits Mesa scalar opcodes to produce unique answers across channels.
418 *
419 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
420 * channel determines the result across all channels. So to do a vec4
421 * of this operation, we want to emit a scalar per source channel used
422 * to produce dest channels.
423 */
424 void
425 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op2(ir_instruction *ir,
426 enum prog_opcode op,
427 ir_to_mesa_dst_reg dst,
428 ir_to_mesa_src_reg orig_src0,
429 ir_to_mesa_src_reg orig_src1)
430 {
431 int i, j;
432 int done_mask = ~dst.writemask;
433
434 /* Mesa RCP is a scalar operation splatting results to all channels,
435 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
436 * dst channels.
437 */
438 for (i = 0; i < 4; i++) {
439 GLuint this_mask = (1 << i);
440 ir_to_mesa_instruction *inst;
441 ir_to_mesa_src_reg src0 = orig_src0;
442 ir_to_mesa_src_reg src1 = orig_src1;
443
444 if (done_mask & this_mask)
445 continue;
446
447 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
448 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
449 for (j = i + 1; j < 4; j++) {
450 if (!(done_mask & (1 << j)) &&
451 GET_SWZ(src0.swizzle, j) == src0_swiz &&
452 GET_SWZ(src1.swizzle, j) == src1_swiz) {
453 this_mask |= (1 << j);
454 }
455 }
456 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
457 src0_swiz, src0_swiz);
458 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
459 src1_swiz, src1_swiz);
460
461 inst = ir_to_mesa_emit_op2(ir, op,
462 dst,
463 src0,
464 src1);
465 inst->dst_reg.writemask = this_mask;
466 done_mask |= this_mask;
467 }
468 }
469
470 void
471 ir_to_mesa_visitor::ir_to_mesa_emit_scalar_op1(ir_instruction *ir,
472 enum prog_opcode op,
473 ir_to_mesa_dst_reg dst,
474 ir_to_mesa_src_reg src0)
475 {
476 ir_to_mesa_src_reg undef = ir_to_mesa_undef;
477
478 undef.swizzle = SWIZZLE_XXXX;
479
480 ir_to_mesa_emit_scalar_op2(ir, op, dst, src0, undef);
481 }
482
483 struct ir_to_mesa_src_reg
484 ir_to_mesa_visitor::src_reg_for_float(float val)
485 {
486 ir_to_mesa_src_reg src_reg(PROGRAM_CONSTANT, -1, NULL);
487
488 src_reg.index = _mesa_add_unnamed_constant(this->prog->Parameters,
489 &val, 1, &src_reg.swizzle);
490
491 return src_reg;
492 }
493
494 static int
495 type_size(const struct glsl_type *type)
496 {
497 unsigned int i;
498 int size;
499
500 switch (type->base_type) {
501 case GLSL_TYPE_UINT:
502 case GLSL_TYPE_INT:
503 case GLSL_TYPE_FLOAT:
504 case GLSL_TYPE_BOOL:
505 if (type->is_matrix()) {
506 return type->matrix_columns;
507 } else {
508 /* Regardless of size of vector, it gets a vec4. This is bad
509 * packing for things like floats, but otherwise arrays become a
510 * mess. Hopefully a later pass over the code can pack scalars
511 * down if appropriate.
512 */
513 return 1;
514 }
515 case GLSL_TYPE_ARRAY:
516 return type_size(type->fields.array) * type->length;
517 case GLSL_TYPE_STRUCT:
518 size = 0;
519 for (i = 0; i < type->length; i++) {
520 size += type_size(type->fields.structure[i].type);
521 }
522 return size;
523 case GLSL_TYPE_SAMPLER:
524 /* Samplers take up one slot in UNIFORMS[], but they're baked in
525 * at link time.
526 */
527 return 1;
528 default:
529 assert(0);
530 return 0;
531 }
532 }
533
534 /**
535 * In the initial pass of codegen, we assign temporary numbers to
536 * intermediate results. (not SSA -- variable assignments will reuse
537 * storage). Actual register allocation for the Mesa VM occurs in a
538 * pass over the Mesa IR later.
539 */
540 ir_to_mesa_src_reg
541 ir_to_mesa_visitor::get_temp(const glsl_type *type)
542 {
543 ir_to_mesa_src_reg src_reg;
544 int swizzle[4];
545 int i;
546
547 src_reg.file = PROGRAM_TEMPORARY;
548 src_reg.index = next_temp;
549 src_reg.reladdr = NULL;
550 next_temp += type_size(type);
551
552 if (type->is_array() || type->is_record()) {
553 src_reg.swizzle = SWIZZLE_NOOP;
554 } else {
555 for (i = 0; i < type->vector_elements; i++)
556 swizzle[i] = i;
557 for (; i < 4; i++)
558 swizzle[i] = type->vector_elements - 1;
559 src_reg.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1],
560 swizzle[2], swizzle[3]);
561 }
562 src_reg.negate = 0;
563
564 return src_reg;
565 }
566
567 variable_storage *
568 ir_to_mesa_visitor::find_variable_storage(ir_variable *var)
569 {
570
571 variable_storage *entry;
572
573 foreach_iter(exec_list_iterator, iter, this->variables) {
574 entry = (variable_storage *)iter.get();
575
576 if (entry->var == var)
577 return entry;
578 }
579
580 return NULL;
581 }
582
583 void
584 ir_to_mesa_visitor::visit(ir_variable *ir)
585 {
586 if (strcmp(ir->name, "gl_FragCoord") == 0) {
587 struct gl_fragment_program *fp = (struct gl_fragment_program *)this->prog;
588
589 fp->OriginUpperLeft = ir->origin_upper_left;
590 fp->PixelCenterInteger = ir->pixel_center_integer;
591 }
592
593 if (ir->mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
594 unsigned int i;
595 const struct gl_builtin_uniform_desc *statevar;
596
597 for (i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
598 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
599 break;
600 }
601
602 if (!_mesa_builtin_uniform_desc[i].name) {
603 fail_link(this->shader_program,
604 "Failed to find builtin uniform `%s'\n", ir->name);
605 return;
606 }
607
608 statevar = &_mesa_builtin_uniform_desc[i];
609
610 int array_count;
611 if (ir->type->is_array()) {
612 array_count = ir->type->length;
613 } else {
614 array_count = 1;
615 }
616
617 /* Check if this statevar's setup in the STATE file exactly
618 * matches how we'll want to reference it as a
619 * struct/array/whatever. If not, then we need to move it into
620 * temporary storage and hope that it'll get copy-propagated
621 * out.
622 */
623 for (i = 0; i < statevar->num_elements; i++) {
624 if (statevar->elements[i].swizzle != SWIZZLE_XYZW) {
625 break;
626 }
627 }
628
629 struct variable_storage *storage;
630 ir_to_mesa_dst_reg dst;
631 if (i == statevar->num_elements) {
632 /* We'll set the index later. */
633 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
634 this->variables.push_tail(storage);
635
636 dst = ir_to_mesa_undef_dst;
637 } else {
638 storage = new(mem_ctx) variable_storage(ir, PROGRAM_TEMPORARY,
639 this->next_temp);
640 this->variables.push_tail(storage);
641 this->next_temp += type_size(ir->type);
642
643 dst = ir_to_mesa_dst_reg_from_src(ir_to_mesa_src_reg(PROGRAM_TEMPORARY,
644 storage->index,
645 NULL));
646 }
647
648
649 for (int a = 0; a < array_count; a++) {
650 for (unsigned int i = 0; i < statevar->num_elements; i++) {
651 struct gl_builtin_uniform_element *element = &statevar->elements[i];
652 int tokens[STATE_LENGTH];
653
654 memcpy(tokens, element->tokens, sizeof(element->tokens));
655 if (ir->type->is_array()) {
656 tokens[1] = a;
657 }
658
659 int index = _mesa_add_state_reference(this->prog->Parameters,
660 (gl_state_index *)tokens);
661
662 if (storage->file == PROGRAM_STATE_VAR) {
663 if (storage->index == -1) {
664 storage->index = index;
665 } else {
666 assert(index ==
667 (int)(storage->index + a * statevar->num_elements + i));
668 }
669 } else {
670 ir_to_mesa_src_reg src(PROGRAM_STATE_VAR, index, NULL);
671 src.swizzle = element->swizzle;
672 ir_to_mesa_emit_op1(ir, OPCODE_MOV, dst, src);
673 /* even a float takes up a whole vec4 reg in a struct/array. */
674 dst.index++;
675 }
676 }
677 }
678 if (storage->file == PROGRAM_TEMPORARY &&
679 dst.index != storage->index + type_size(ir->type)) {
680 fail_link(this->shader_program,
681 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
682 ir->name, dst.index - storage->index,
683 type_size(ir->type));
684 }
685 }
686 }
687
688 void
689 ir_to_mesa_visitor::visit(ir_loop *ir)
690 {
691 ir_dereference_variable *counter = NULL;
692
693 if (ir->counter != NULL)
694 counter = new(ir) ir_dereference_variable(ir->counter);
695
696 if (ir->from != NULL) {
697 assert(ir->counter != NULL);
698
699 ir_assignment *a = new(ir) ir_assignment(counter, ir->from, NULL);
700
701 a->accept(this);
702 delete a;
703 }
704
705 ir_to_mesa_emit_op0(NULL, OPCODE_BGNLOOP);
706
707 if (ir->to) {
708 ir_expression *e =
709 new(ir) ir_expression(ir->cmp, glsl_type::bool_type,
710 counter, ir->to);
711 ir_if *if_stmt = new(ir) ir_if(e);
712
713 ir_loop_jump *brk = new(ir) ir_loop_jump(ir_loop_jump::jump_break);
714
715 if_stmt->then_instructions.push_tail(brk);
716
717 if_stmt->accept(this);
718
719 delete if_stmt;
720 delete e;
721 delete brk;
722 }
723
724 visit_exec_list(&ir->body_instructions, this);
725
726 if (ir->increment) {
727 ir_expression *e =
728 new(ir) ir_expression(ir_binop_add, counter->type,
729 counter, ir->increment);
730
731 ir_assignment *a = new(ir) ir_assignment(counter, e, NULL);
732
733 a->accept(this);
734 delete a;
735 delete e;
736 }
737
738 ir_to_mesa_emit_op0(NULL, OPCODE_ENDLOOP);
739 }
740
741 void
742 ir_to_mesa_visitor::visit(ir_loop_jump *ir)
743 {
744 switch (ir->mode) {
745 case ir_loop_jump::jump_break:
746 ir_to_mesa_emit_op0(NULL, OPCODE_BRK);
747 break;
748 case ir_loop_jump::jump_continue:
749 ir_to_mesa_emit_op0(NULL, OPCODE_CONT);
750 break;
751 }
752 }
753
754
755 void
756 ir_to_mesa_visitor::visit(ir_function_signature *ir)
757 {
758 assert(0);
759 (void)ir;
760 }
761
762 void
763 ir_to_mesa_visitor::visit(ir_function *ir)
764 {
765 /* Ignore function bodies other than main() -- we shouldn't see calls to
766 * them since they should all be inlined before we get to ir_to_mesa.
767 */
768 if (strcmp(ir->name, "main") == 0) {
769 const ir_function_signature *sig;
770 exec_list empty;
771
772 sig = ir->matching_signature(&empty);
773
774 assert(sig);
775
776 foreach_iter(exec_list_iterator, iter, sig->body) {
777 ir_instruction *ir = (ir_instruction *)iter.get();
778
779 ir->accept(this);
780 }
781 }
782 }
783
784 GLboolean
785 ir_to_mesa_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
786 {
787 int nonmul_operand = 1 - mul_operand;
788 ir_to_mesa_src_reg a, b, c;
789
790 ir_expression *expr = ir->operands[mul_operand]->as_expression();
791 if (!expr || expr->operation != ir_binop_mul)
792 return false;
793
794 expr->operands[0]->accept(this);
795 a = this->result;
796 expr->operands[1]->accept(this);
797 b = this->result;
798 ir->operands[nonmul_operand]->accept(this);
799 c = this->result;
800
801 this->result = get_temp(ir->type);
802 ir_to_mesa_emit_op3(ir, OPCODE_MAD,
803 ir_to_mesa_dst_reg_from_src(this->result), a, b, c);
804
805 return true;
806 }
807
808 void
809 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction *ir,
810 ir_to_mesa_src_reg *reg, int *num_reladdr)
811 {
812 if (!reg->reladdr)
813 return;
814
815 ir_to_mesa_emit_op1(ir, OPCODE_ARL, ir_to_mesa_address_reg, *reg->reladdr);
816
817 if (*num_reladdr != 1) {
818 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
819
820 ir_to_mesa_emit_op1(ir, OPCODE_MOV,
821 ir_to_mesa_dst_reg_from_src(temp), *reg);
822 *reg = temp;
823 }
824
825 (*num_reladdr)--;
826 }
827
828 void
829 ir_to_mesa_visitor::visit(ir_expression *ir)
830 {
831 unsigned int operand;
832 struct ir_to_mesa_src_reg op[2];
833 struct ir_to_mesa_src_reg result_src;
834 struct ir_to_mesa_dst_reg result_dst;
835 const glsl_type *vec4_type = glsl_type::get_instance(GLSL_TYPE_FLOAT, 4, 1);
836 const glsl_type *vec3_type = glsl_type::get_instance(GLSL_TYPE_FLOAT, 3, 1);
837 const glsl_type *vec2_type = glsl_type::get_instance(GLSL_TYPE_FLOAT, 2, 1);
838
839 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
840 */
841 if (ir->operation == ir_binop_add) {
842 if (try_emit_mad(ir, 1))
843 return;
844 if (try_emit_mad(ir, 0))
845 return;
846 }
847
848 for (operand = 0; operand < ir->get_num_operands(); operand++) {
849 this->result.file = PROGRAM_UNDEFINED;
850 ir->operands[operand]->accept(this);
851 if (this->result.file == PROGRAM_UNDEFINED) {
852 ir_print_visitor v;
853 printf("Failed to get tree for expression operand:\n");
854 ir->operands[operand]->accept(&v);
855 exit(1);
856 }
857 op[operand] = this->result;
858
859 /* Matrix expression operands should have been broken down to vector
860 * operations already.
861 */
862 assert(!ir->operands[operand]->type->is_matrix());
863 }
864
865 int vector_elements = ir->operands[0]->type->vector_elements;
866 if (ir->operands[1]) {
867 vector_elements = MAX2(vector_elements,
868 ir->operands[1]->type->vector_elements);
869 }
870
871 this->result.file = PROGRAM_UNDEFINED;
872
873 /* Storage for our result. Ideally for an assignment we'd be using
874 * the actual storage for the result here, instead.
875 */
876 result_src = get_temp(ir->type);
877 /* convenience for the emit functions below. */
878 result_dst = ir_to_mesa_dst_reg_from_src(result_src);
879 /* Limit writes to the channels that will be used by result_src later.
880 * This does limit this temp's use as a temporary for multi-instruction
881 * sequences.
882 */
883 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
884
885 switch (ir->operation) {
886 case ir_unop_logic_not:
887 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst,
888 op[0], src_reg_for_float(0.0));
889 break;
890 case ir_unop_neg:
891 op[0].negate = ~op[0].negate;
892 result_src = op[0];
893 break;
894 case ir_unop_abs:
895 ir_to_mesa_emit_op1(ir, OPCODE_ABS, result_dst, op[0]);
896 break;
897 case ir_unop_sign:
898 ir_to_mesa_emit_op1(ir, OPCODE_SSG, result_dst, op[0]);
899 break;
900 case ir_unop_rcp:
901 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RCP, result_dst, op[0]);
902 break;
903
904 case ir_unop_exp2:
905 ir_to_mesa_emit_scalar_op1(ir, OPCODE_EX2, result_dst, op[0]);
906 break;
907 case ir_unop_exp:
908 case ir_unop_log:
909 assert(!"not reached: should be handled by ir_explog_to_explog2");
910 break;
911 case ir_unop_log2:
912 ir_to_mesa_emit_scalar_op1(ir, OPCODE_LG2, result_dst, op[0]);
913 break;
914 case ir_unop_sin:
915 ir_to_mesa_emit_scalar_op1(ir, OPCODE_SIN, result_dst, op[0]);
916 break;
917 case ir_unop_cos:
918 ir_to_mesa_emit_scalar_op1(ir, OPCODE_COS, result_dst, op[0]);
919 break;
920
921 case ir_unop_dFdx:
922 ir_to_mesa_emit_op1(ir, OPCODE_DDX, result_dst, op[0]);
923 break;
924 case ir_unop_dFdy:
925 ir_to_mesa_emit_op1(ir, OPCODE_DDY, result_dst, op[0]);
926 break;
927
928 case ir_unop_noise: {
929 const enum prog_opcode opcode =
930 prog_opcode(OPCODE_NOISE1
931 + (ir->operands[0]->type->vector_elements) - 1);
932 assert((opcode >= OPCODE_NOISE1) && (opcode <= OPCODE_NOISE4));
933
934 ir_to_mesa_emit_op1(ir, opcode, result_dst, op[0]);
935 break;
936 }
937
938 case ir_binop_add:
939 ir_to_mesa_emit_op2(ir, OPCODE_ADD, result_dst, op[0], op[1]);
940 break;
941 case ir_binop_sub:
942 ir_to_mesa_emit_op2(ir, OPCODE_SUB, result_dst, op[0], op[1]);
943 break;
944
945 case ir_binop_mul:
946 ir_to_mesa_emit_op2(ir, OPCODE_MUL, result_dst, op[0], op[1]);
947 break;
948 case ir_binop_div:
949 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
950 case ir_binop_mod:
951 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
952 break;
953
954 case ir_binop_less:
955 ir_to_mesa_emit_op2(ir, OPCODE_SLT, result_dst, op[0], op[1]);
956 break;
957 case ir_binop_greater:
958 ir_to_mesa_emit_op2(ir, OPCODE_SGT, result_dst, op[0], op[1]);
959 break;
960 case ir_binop_lequal:
961 ir_to_mesa_emit_op2(ir, OPCODE_SLE, result_dst, op[0], op[1]);
962 break;
963 case ir_binop_gequal:
964 ir_to_mesa_emit_op2(ir, OPCODE_SGE, result_dst, op[0], op[1]);
965 break;
966 case ir_binop_equal:
967 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst, op[0], op[1]);
968 break;
969 case ir_binop_nequal:
970 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
971 break;
972 case ir_binop_all_equal:
973 /* "==" operator producing a scalar boolean. */
974 if (ir->operands[0]->type->is_vector() ||
975 ir->operands[1]->type->is_vector()) {
976 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
977 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
978 ir_to_mesa_dst_reg_from_src(temp), op[0], op[1]);
979 if (vector_elements == 4)
980 ir_to_mesa_emit_op2(ir, OPCODE_DP4, result_dst, temp, temp);
981 else if (vector_elements == 3)
982 ir_to_mesa_emit_op2(ir, OPCODE_DP3, result_dst, temp, temp);
983 else
984 ir_to_mesa_emit_op2(ir, OPCODE_DP2, result_dst, temp, temp);
985 ir_to_mesa_emit_op2(ir, OPCODE_SEQ,
986 result_dst, result_src, src_reg_for_float(0.0));
987 } else {
988 ir_to_mesa_emit_op2(ir, OPCODE_SEQ, result_dst, op[0], op[1]);
989 }
990 break;
991 case ir_binop_any_nequal:
992 /* "!=" operator producing a scalar boolean. */
993 if (ir->operands[0]->type->is_vector() ||
994 ir->operands[1]->type->is_vector()) {
995 ir_to_mesa_src_reg temp = get_temp(glsl_type::vec4_type);
996 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
997 ir_to_mesa_dst_reg_from_src(temp), op[0], op[1]);
998 if (vector_elements == 4)
999 ir_to_mesa_emit_op2(ir, OPCODE_DP4, result_dst, temp, temp);
1000 else if (vector_elements == 3)
1001 ir_to_mesa_emit_op2(ir, OPCODE_DP3, result_dst, temp, temp);
1002 else
1003 ir_to_mesa_emit_op2(ir, OPCODE_DP2, result_dst, temp, temp);
1004 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1005 result_dst, result_src, src_reg_for_float(0.0));
1006 } else {
1007 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
1008 }
1009 break;
1010
1011 case ir_unop_any:
1012 switch (ir->operands[0]->type->vector_elements) {
1013 case 4:
1014 ir_to_mesa_emit_op2(ir, OPCODE_DP4, result_dst, op[0], op[0]);
1015 break;
1016 case 3:
1017 ir_to_mesa_emit_op2(ir, OPCODE_DP3, result_dst, op[0], op[0]);
1018 break;
1019 case 2:
1020 ir_to_mesa_emit_op2(ir, OPCODE_DP2, result_dst, op[0], op[0]);
1021 break;
1022 default:
1023 assert(!"unreached: ir_unop_any of non-bvec");
1024 break;
1025 }
1026 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1027 result_dst, result_src, src_reg_for_float(0.0));
1028 break;
1029
1030 case ir_binop_logic_xor:
1031 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst, op[0], op[1]);
1032 break;
1033
1034 case ir_binop_logic_or:
1035 /* This could be a saturated add and skip the SNE. */
1036 ir_to_mesa_emit_op2(ir, OPCODE_ADD,
1037 result_dst,
1038 op[0], op[1]);
1039
1040 ir_to_mesa_emit_op2(ir, OPCODE_SNE,
1041 result_dst,
1042 result_src, src_reg_for_float(0.0));
1043 break;
1044
1045 case ir_binop_logic_and:
1046 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1047 ir_to_mesa_emit_op2(ir, OPCODE_MUL,
1048 result_dst,
1049 op[0], op[1]);
1050 break;
1051
1052 case ir_binop_dot:
1053 if (ir->operands[0]->type == vec4_type) {
1054 assert(ir->operands[1]->type == vec4_type);
1055 ir_to_mesa_emit_op2(ir, OPCODE_DP4,
1056 result_dst,
1057 op[0], op[1]);
1058 } else if (ir->operands[0]->type == vec3_type) {
1059 assert(ir->operands[1]->type == vec3_type);
1060 ir_to_mesa_emit_op2(ir, OPCODE_DP3,
1061 result_dst,
1062 op[0], op[1]);
1063 } else if (ir->operands[0]->type == vec2_type) {
1064 assert(ir->operands[1]->type == vec2_type);
1065 ir_to_mesa_emit_op2(ir, OPCODE_DP2,
1066 result_dst,
1067 op[0], op[1]);
1068 }
1069 break;
1070
1071 case ir_binop_cross:
1072 ir_to_mesa_emit_op2(ir, OPCODE_XPD, result_dst, op[0], op[1]);
1073 break;
1074
1075 case ir_unop_sqrt:
1076 /* sqrt(x) = x * rsq(x). */
1077 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RSQ, result_dst, op[0]);
1078 ir_to_mesa_emit_op2(ir, OPCODE_MUL, result_dst, result_src, op[0]);
1079 /* For incoming channels <= 0, set the result to 0. */
1080 op[0].negate = ~op[0].negate;
1081 ir_to_mesa_emit_op3(ir, OPCODE_CMP, result_dst,
1082 op[0], result_src, src_reg_for_float(0.0));
1083 break;
1084 case ir_unop_rsq:
1085 ir_to_mesa_emit_scalar_op1(ir, OPCODE_RSQ, result_dst, op[0]);
1086 break;
1087 case ir_unop_i2f:
1088 case ir_unop_b2f:
1089 case ir_unop_b2i:
1090 /* Mesa IR lacks types, ints are stored as truncated floats. */
1091 result_src = op[0];
1092 break;
1093 case ir_unop_f2i:
1094 ir_to_mesa_emit_op1(ir, OPCODE_TRUNC, result_dst, op[0]);
1095 break;
1096 case ir_unop_f2b:
1097 case ir_unop_i2b:
1098 ir_to_mesa_emit_op2(ir, OPCODE_SNE, result_dst,
1099 op[0], src_reg_for_float(0.0));
1100 break;
1101 case ir_unop_trunc:
1102 ir_to_mesa_emit_op1(ir, OPCODE_TRUNC, result_dst, op[0]);
1103 break;
1104 case ir_unop_ceil:
1105 op[0].negate = ~op[0].negate;
1106 ir_to_mesa_emit_op1(ir, OPCODE_FLR, result_dst, op[0]);
1107 result_src.negate = ~result_src.negate;
1108 break;
1109 case ir_unop_floor:
1110 ir_to_mesa_emit_op1(ir, OPCODE_FLR, result_dst, op[0]);
1111 break;
1112 case ir_unop_fract:
1113 ir_to_mesa_emit_op1(ir, OPCODE_FRC, result_dst, op[0]);
1114 break;
1115
1116 case ir_binop_min:
1117 ir_to_mesa_emit_op2(ir, OPCODE_MIN, result_dst, op[0], op[1]);
1118 break;
1119 case ir_binop_max:
1120 ir_to_mesa_emit_op2(ir, OPCODE_MAX, result_dst, op[0], op[1]);
1121 break;
1122 case ir_binop_pow:
1123 ir_to_mesa_emit_scalar_op2(ir, OPCODE_POW, result_dst, op[0], op[1]);
1124 break;
1125
1126 case ir_unop_bit_not:
1127 case ir_unop_u2f:
1128 case ir_binop_lshift:
1129 case ir_binop_rshift:
1130 case ir_binop_bit_and:
1131 case ir_binop_bit_xor:
1132 case ir_binop_bit_or:
1133 case ir_unop_round_even:
1134 assert(!"GLSL 1.30 features unsupported");
1135 break;
1136 }
1137
1138 this->result = result_src;
1139 }
1140
1141
1142 void
1143 ir_to_mesa_visitor::visit(ir_swizzle *ir)
1144 {
1145 ir_to_mesa_src_reg src_reg;
1146 int i;
1147 int swizzle[4];
1148
1149 /* Note that this is only swizzles in expressions, not those on the left
1150 * hand side of an assignment, which do write masking. See ir_assignment
1151 * for that.
1152 */
1153
1154 ir->val->accept(this);
1155 src_reg = this->result;
1156 assert(src_reg.file != PROGRAM_UNDEFINED);
1157
1158 for (i = 0; i < 4; i++) {
1159 if (i < ir->type->vector_elements) {
1160 switch (i) {
1161 case 0:
1162 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.x);
1163 break;
1164 case 1:
1165 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.y);
1166 break;
1167 case 2:
1168 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.z);
1169 break;
1170 case 3:
1171 swizzle[i] = GET_SWZ(src_reg.swizzle, ir->mask.w);
1172 break;
1173 }
1174 } else {
1175 /* If the type is smaller than a vec4, replicate the last
1176 * channel out.
1177 */
1178 swizzle[i] = swizzle[ir->type->vector_elements - 1];
1179 }
1180 }
1181
1182 src_reg.swizzle = MAKE_SWIZZLE4(swizzle[0],
1183 swizzle[1],
1184 swizzle[2],
1185 swizzle[3]);
1186
1187 this->result = src_reg;
1188 }
1189
1190 void
1191 ir_to_mesa_visitor::visit(ir_dereference_variable *ir)
1192 {
1193 variable_storage *entry = find_variable_storage(ir->var);
1194
1195 if (!entry) {
1196 switch (ir->var->mode) {
1197 case ir_var_uniform:
1198 entry = new(mem_ctx) variable_storage(ir->var, PROGRAM_UNIFORM,
1199 ir->var->location);
1200 this->variables.push_tail(entry);
1201 break;
1202 case ir_var_in:
1203 case ir_var_out:
1204 case ir_var_inout:
1205 /* The linker assigns locations for varyings and attributes,
1206 * including deprecated builtins (like gl_Color), user-assign
1207 * generic attributes (glBindVertexLocation), and
1208 * user-defined varyings.
1209 *
1210 * FINISHME: We would hit this path for function arguments. Fix!
1211 */
1212 assert(ir->var->location != -1);
1213 if (ir->var->mode == ir_var_in ||
1214 ir->var->mode == ir_var_inout) {
1215 entry = new(mem_ctx) variable_storage(ir->var,
1216 PROGRAM_INPUT,
1217 ir->var->location);
1218
1219 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
1220 ir->var->location >= VERT_ATTRIB_GENERIC0) {
1221 _mesa_add_attribute(prog->Attributes,
1222 ir->var->name,
1223 _mesa_sizeof_glsl_type(ir->var->type->gl_type),
1224 ir->var->type->gl_type,
1225 ir->var->location - VERT_ATTRIB_GENERIC0);
1226 }
1227 } else {
1228 entry = new(mem_ctx) variable_storage(ir->var,
1229 PROGRAM_OUTPUT,
1230 ir->var->location);
1231 }
1232
1233 break;
1234 case ir_var_auto:
1235 case ir_var_temporary:
1236 entry = new(mem_ctx) variable_storage(ir->var, PROGRAM_TEMPORARY,
1237 this->next_temp);
1238 this->variables.push_tail(entry);
1239
1240 next_temp += type_size(ir->var->type);
1241 break;
1242 }
1243
1244 if (!entry) {
1245 printf("Failed to make storage for %s\n", ir->var->name);
1246 exit(1);
1247 }
1248 }
1249
1250 this->result = ir_to_mesa_src_reg(entry->file, entry->index, ir->var->type);
1251 }
1252
1253 void
1254 ir_to_mesa_visitor::visit(ir_dereference_array *ir)
1255 {
1256 ir_constant *index;
1257 ir_to_mesa_src_reg src_reg;
1258 int element_size = type_size(ir->type);
1259
1260 index = ir->array_index->constant_expression_value();
1261
1262 ir->array->accept(this);
1263 src_reg = this->result;
1264
1265 if (index) {
1266 src_reg.index += index->value.i[0] * element_size;
1267 } else {
1268 ir_to_mesa_src_reg array_base = this->result;
1269 /* Variable index array dereference. It eats the "vec4" of the
1270 * base of the array and an index that offsets the Mesa register
1271 * index.
1272 */
1273 ir->array_index->accept(this);
1274
1275 ir_to_mesa_src_reg index_reg;
1276
1277 if (element_size == 1) {
1278 index_reg = this->result;
1279 } else {
1280 index_reg = get_temp(glsl_type::float_type);
1281
1282 ir_to_mesa_emit_op2(ir, OPCODE_MUL,
1283 ir_to_mesa_dst_reg_from_src(index_reg),
1284 this->result, src_reg_for_float(element_size));
1285 }
1286
1287 src_reg.reladdr = talloc(mem_ctx, ir_to_mesa_src_reg);
1288 memcpy(src_reg.reladdr, &index_reg, sizeof(index_reg));
1289 }
1290
1291 /* If the type is smaller than a vec4, replicate the last channel out. */
1292 if (ir->type->is_scalar() || ir->type->is_vector())
1293 src_reg.swizzle = swizzle_for_size(ir->type->vector_elements);
1294 else
1295 src_reg.swizzle = SWIZZLE_NOOP;
1296
1297 this->result = src_reg;
1298 }
1299
1300 void
1301 ir_to_mesa_visitor::visit(ir_dereference_record *ir)
1302 {
1303 unsigned int i;
1304 const glsl_type *struct_type = ir->record->type;
1305 int offset = 0;
1306
1307 ir->record->accept(this);
1308
1309 for (i = 0; i < struct_type->length; i++) {
1310 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
1311 break;
1312 offset += type_size(struct_type->fields.structure[i].type);
1313 }
1314 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
1315 this->result.index += offset;
1316 }
1317
1318 /**
1319 * We want to be careful in assignment setup to hit the actual storage
1320 * instead of potentially using a temporary like we might with the
1321 * ir_dereference handler.
1322 */
1323 static struct ir_to_mesa_dst_reg
1324 get_assignment_lhs(ir_dereference *ir, ir_to_mesa_visitor *v)
1325 {
1326 /* The LHS must be a dereference. If the LHS is a variable indexed array
1327 * access of a vector, it must be separated into a series conditional moves
1328 * before reaching this point (see ir_vec_index_to_cond_assign).
1329 */
1330 assert(ir->as_dereference());
1331 ir_dereference_array *deref_array = ir->as_dereference_array();
1332 if (deref_array) {
1333 assert(!deref_array->array->type->is_vector());
1334 }
1335
1336 /* Use the rvalue deref handler for the most part. We'll ignore
1337 * swizzles in it and write swizzles using writemask, though.
1338 */
1339 ir->accept(v);
1340 return ir_to_mesa_dst_reg_from_src(v->result);
1341 }
1342
1343 void
1344 ir_to_mesa_visitor::visit(ir_assignment *ir)
1345 {
1346 struct ir_to_mesa_dst_reg l;
1347 struct ir_to_mesa_src_reg r;
1348 int i;
1349
1350 ir->rhs->accept(this);
1351 r = this->result;
1352
1353 l = get_assignment_lhs(ir->lhs, this);
1354
1355 /* FINISHME: This should really set to the correct maximal writemask for each
1356 * FINISHME: component written (in the loops below). This case can only
1357 * FINISHME: occur for matrices, arrays, and structures.
1358 */
1359 if (ir->write_mask == 0) {
1360 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
1361 l.writemask = WRITEMASK_XYZW;
1362 } else if (ir->lhs->type->is_scalar()) {
1363 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1364 * FINISHME: W component of fragment shader output zero, work correctly.
1365 */
1366 l.writemask = WRITEMASK_XYZW;
1367 } else {
1368 int swizzles[4];
1369 int first_enabled_chan = 0;
1370 int rhs_chan = 0;
1371
1372 assert(ir->lhs->type->is_vector());
1373 l.writemask = ir->write_mask;
1374
1375 for (int i = 0; i < 4; i++) {
1376 if (l.writemask & (1 << i)) {
1377 first_enabled_chan = GET_SWZ(r.swizzle, i);
1378 break;
1379 }
1380 }
1381
1382 /* Swizzle a small RHS vector into the channels being written.
1383 *
1384 * glsl ir treats write_mask as dictating how many channels are
1385 * present on the RHS while Mesa IR treats write_mask as just
1386 * showing which channels of the vec4 RHS get written.
1387 */
1388 for (int i = 0; i < 4; i++) {
1389 if (l.writemask & (1 << i))
1390 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
1391 else
1392 swizzles[i] = first_enabled_chan;
1393 }
1394 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
1395 swizzles[2], swizzles[3]);
1396 }
1397
1398 assert(l.file != PROGRAM_UNDEFINED);
1399 assert(r.file != PROGRAM_UNDEFINED);
1400
1401 if (ir->condition) {
1402 ir_to_mesa_src_reg condition;
1403
1404 ir->condition->accept(this);
1405 condition = this->result;
1406
1407 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves,
1408 * and the condition we produced is 0.0 or 1.0. By flipping the
1409 * sign, we can choose which value OPCODE_CMP produces without
1410 * an extra computing the condition.
1411 */
1412 condition.negate = ~condition.negate;
1413 for (i = 0; i < type_size(ir->lhs->type); i++) {
1414 ir_to_mesa_emit_op3(ir, OPCODE_CMP, l,
1415 condition, r, ir_to_mesa_src_reg_from_dst(l));
1416 l.index++;
1417 r.index++;
1418 }
1419 } else {
1420 for (i = 0; i < type_size(ir->lhs->type); i++) {
1421 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1422 l.index++;
1423 r.index++;
1424 }
1425 }
1426 }
1427
1428
1429 void
1430 ir_to_mesa_visitor::visit(ir_constant *ir)
1431 {
1432 ir_to_mesa_src_reg src_reg;
1433 GLfloat stack_vals[4] = { 0 };
1434 GLfloat *values = stack_vals;
1435 unsigned int i;
1436
1437 /* Unfortunately, 4 floats is all we can get into
1438 * _mesa_add_unnamed_constant. So, make a temp to store an
1439 * aggregate constant and move each constant value into it. If we
1440 * get lucky, copy propagation will eliminate the extra moves.
1441 */
1442
1443 if (ir->type->base_type == GLSL_TYPE_STRUCT) {
1444 ir_to_mesa_src_reg temp_base = get_temp(ir->type);
1445 ir_to_mesa_dst_reg temp = ir_to_mesa_dst_reg_from_src(temp_base);
1446
1447 foreach_iter(exec_list_iterator, iter, ir->components) {
1448 ir_constant *field_value = (ir_constant *)iter.get();
1449 int size = type_size(field_value->type);
1450
1451 assert(size > 0);
1452
1453 field_value->accept(this);
1454 src_reg = this->result;
1455
1456 for (i = 0; i < (unsigned int)size; i++) {
1457 ir_to_mesa_emit_op1(ir, OPCODE_MOV, temp, src_reg);
1458
1459 src_reg.index++;
1460 temp.index++;
1461 }
1462 }
1463 this->result = temp_base;
1464 return;
1465 }
1466
1467 if (ir->type->is_array()) {
1468 ir_to_mesa_src_reg temp_base = get_temp(ir->type);
1469 ir_to_mesa_dst_reg temp = ir_to_mesa_dst_reg_from_src(temp_base);
1470 int size = type_size(ir->type->fields.array);
1471
1472 assert(size > 0);
1473
1474 for (i = 0; i < ir->type->length; i++) {
1475 ir->array_elements[i]->accept(this);
1476 src_reg = this->result;
1477 for (int j = 0; j < size; j++) {
1478 ir_to_mesa_emit_op1(ir, OPCODE_MOV, temp, src_reg);
1479
1480 src_reg.index++;
1481 temp.index++;
1482 }
1483 }
1484 this->result = temp_base;
1485 return;
1486 }
1487
1488 if (ir->type->is_matrix()) {
1489 ir_to_mesa_src_reg mat = get_temp(ir->type);
1490 ir_to_mesa_dst_reg mat_column = ir_to_mesa_dst_reg_from_src(mat);
1491
1492 for (i = 0; i < ir->type->matrix_columns; i++) {
1493 assert(ir->type->base_type == GLSL_TYPE_FLOAT);
1494 values = &ir->value.f[i * ir->type->vector_elements];
1495
1496 src_reg = ir_to_mesa_src_reg(PROGRAM_CONSTANT, -1, NULL);
1497 src_reg.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1498 values,
1499 ir->type->vector_elements,
1500 &src_reg.swizzle);
1501 ir_to_mesa_emit_op1(ir, OPCODE_MOV, mat_column, src_reg);
1502
1503 mat_column.index++;
1504 }
1505
1506 this->result = mat;
1507 return;
1508 }
1509
1510 src_reg.file = PROGRAM_CONSTANT;
1511 switch (ir->type->base_type) {
1512 case GLSL_TYPE_FLOAT:
1513 values = &ir->value.f[0];
1514 break;
1515 case GLSL_TYPE_UINT:
1516 for (i = 0; i < ir->type->vector_elements; i++) {
1517 values[i] = ir->value.u[i];
1518 }
1519 break;
1520 case GLSL_TYPE_INT:
1521 for (i = 0; i < ir->type->vector_elements; i++) {
1522 values[i] = ir->value.i[i];
1523 }
1524 break;
1525 case GLSL_TYPE_BOOL:
1526 for (i = 0; i < ir->type->vector_elements; i++) {
1527 values[i] = ir->value.b[i];
1528 }
1529 break;
1530 default:
1531 assert(!"Non-float/uint/int/bool constant");
1532 }
1533
1534 this->result = ir_to_mesa_src_reg(PROGRAM_CONSTANT, -1, ir->type);
1535 this->result.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1536 values,
1537 ir->type->vector_elements,
1538 &this->result.swizzle);
1539 }
1540
1541 function_entry *
1542 ir_to_mesa_visitor::get_function_signature(ir_function_signature *sig)
1543 {
1544 function_entry *entry;
1545
1546 foreach_iter(exec_list_iterator, iter, this->function_signatures) {
1547 entry = (function_entry *)iter.get();
1548
1549 if (entry->sig == sig)
1550 return entry;
1551 }
1552
1553 entry = talloc(mem_ctx, function_entry);
1554 entry->sig = sig;
1555 entry->sig_id = this->next_signature_id++;
1556 entry->bgn_inst = NULL;
1557
1558 /* Allocate storage for all the parameters. */
1559 foreach_iter(exec_list_iterator, iter, sig->parameters) {
1560 ir_variable *param = (ir_variable *)iter.get();
1561 variable_storage *storage;
1562
1563 storage = find_variable_storage(param);
1564 assert(!storage);
1565
1566 storage = new(mem_ctx) variable_storage(param, PROGRAM_TEMPORARY,
1567 this->next_temp);
1568 this->variables.push_tail(storage);
1569
1570 this->next_temp += type_size(param->type);
1571 }
1572
1573 if (!sig->return_type->is_void()) {
1574 entry->return_reg = get_temp(sig->return_type);
1575 } else {
1576 entry->return_reg = ir_to_mesa_undef;
1577 }
1578
1579 this->function_signatures.push_tail(entry);
1580 return entry;
1581 }
1582
1583 void
1584 ir_to_mesa_visitor::visit(ir_call *ir)
1585 {
1586 ir_to_mesa_instruction *call_inst;
1587 ir_function_signature *sig = ir->get_callee();
1588 function_entry *entry = get_function_signature(sig);
1589 int i;
1590
1591 /* Process in parameters. */
1592 exec_list_iterator sig_iter = sig->parameters.iterator();
1593 foreach_iter(exec_list_iterator, iter, *ir) {
1594 ir_rvalue *param_rval = (ir_rvalue *)iter.get();
1595 ir_variable *param = (ir_variable *)sig_iter.get();
1596
1597 if (param->mode == ir_var_in ||
1598 param->mode == ir_var_inout) {
1599 variable_storage *storage = find_variable_storage(param);
1600 assert(storage);
1601
1602 param_rval->accept(this);
1603 ir_to_mesa_src_reg r = this->result;
1604
1605 ir_to_mesa_dst_reg l;
1606 l.file = storage->file;
1607 l.index = storage->index;
1608 l.reladdr = NULL;
1609 l.writemask = WRITEMASK_XYZW;
1610 l.cond_mask = COND_TR;
1611
1612 for (i = 0; i < type_size(param->type); i++) {
1613 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1614 l.index++;
1615 r.index++;
1616 }
1617 }
1618
1619 sig_iter.next();
1620 }
1621 assert(!sig_iter.has_next());
1622
1623 /* Emit call instruction */
1624 call_inst = ir_to_mesa_emit_op1(ir, OPCODE_CAL,
1625 ir_to_mesa_undef_dst, ir_to_mesa_undef);
1626 call_inst->function = entry;
1627
1628 /* Process out parameters. */
1629 sig_iter = sig->parameters.iterator();
1630 foreach_iter(exec_list_iterator, iter, *ir) {
1631 ir_rvalue *param_rval = (ir_rvalue *)iter.get();
1632 ir_variable *param = (ir_variable *)sig_iter.get();
1633
1634 if (param->mode == ir_var_out ||
1635 param->mode == ir_var_inout) {
1636 variable_storage *storage = find_variable_storage(param);
1637 assert(storage);
1638
1639 ir_to_mesa_src_reg r;
1640 r.file = storage->file;
1641 r.index = storage->index;
1642 r.reladdr = NULL;
1643 r.swizzle = SWIZZLE_NOOP;
1644 r.negate = 0;
1645
1646 param_rval->accept(this);
1647 ir_to_mesa_dst_reg l = ir_to_mesa_dst_reg_from_src(this->result);
1648
1649 for (i = 0; i < type_size(param->type); i++) {
1650 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1651 l.index++;
1652 r.index++;
1653 }
1654 }
1655
1656 sig_iter.next();
1657 }
1658 assert(!sig_iter.has_next());
1659
1660 /* Process return value. */
1661 this->result = entry->return_reg;
1662 }
1663
1664 void
1665 ir_to_mesa_visitor::visit(ir_texture *ir)
1666 {
1667 ir_to_mesa_src_reg result_src, coord, lod_info, projector;
1668 ir_to_mesa_dst_reg result_dst, coord_dst;
1669 ir_to_mesa_instruction *inst = NULL;
1670 prog_opcode opcode = OPCODE_NOP;
1671
1672 ir->coordinate->accept(this);
1673
1674 /* Put our coords in a temp. We'll need to modify them for shadow,
1675 * projection, or LOD, so the only case we'd use it as is is if
1676 * we're doing plain old texturing. Mesa IR optimization should
1677 * handle cleaning up our mess in that case.
1678 */
1679 coord = get_temp(glsl_type::vec4_type);
1680 coord_dst = ir_to_mesa_dst_reg_from_src(coord);
1681 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst,
1682 this->result);
1683
1684 if (ir->projector) {
1685 ir->projector->accept(this);
1686 projector = this->result;
1687 }
1688
1689 /* Storage for our result. Ideally for an assignment we'd be using
1690 * the actual storage for the result here, instead.
1691 */
1692 result_src = get_temp(glsl_type::vec4_type);
1693 result_dst = ir_to_mesa_dst_reg_from_src(result_src);
1694
1695 switch (ir->op) {
1696 case ir_tex:
1697 opcode = OPCODE_TEX;
1698 break;
1699 case ir_txb:
1700 opcode = OPCODE_TXB;
1701 ir->lod_info.bias->accept(this);
1702 lod_info = this->result;
1703 break;
1704 case ir_txl:
1705 opcode = OPCODE_TXL;
1706 ir->lod_info.lod->accept(this);
1707 lod_info = this->result;
1708 break;
1709 case ir_txd:
1710 case ir_txf:
1711 assert(!"GLSL 1.30 features unsupported");
1712 break;
1713 }
1714
1715 if (ir->projector) {
1716 if (opcode == OPCODE_TEX) {
1717 /* Slot the projector in as the last component of the coord. */
1718 coord_dst.writemask = WRITEMASK_W;
1719 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, projector);
1720 coord_dst.writemask = WRITEMASK_XYZW;
1721 opcode = OPCODE_TXP;
1722 } else {
1723 ir_to_mesa_src_reg coord_w = coord;
1724 coord_w.swizzle = SWIZZLE_WWWW;
1725
1726 /* For the other TEX opcodes there's no projective version
1727 * since the last slot is taken up by lod info. Do the
1728 * projective divide now.
1729 */
1730 coord_dst.writemask = WRITEMASK_W;
1731 ir_to_mesa_emit_op1(ir, OPCODE_RCP, coord_dst, projector);
1732
1733 coord_dst.writemask = WRITEMASK_XYZ;
1734 ir_to_mesa_emit_op2(ir, OPCODE_MUL, coord_dst, coord, coord_w);
1735
1736 coord_dst.writemask = WRITEMASK_XYZW;
1737 coord.swizzle = SWIZZLE_XYZW;
1738 }
1739 }
1740
1741 if (ir->shadow_comparitor) {
1742 /* Slot the shadow value in as the second to last component of the
1743 * coord.
1744 */
1745 ir->shadow_comparitor->accept(this);
1746 coord_dst.writemask = WRITEMASK_Z;
1747 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, this->result);
1748 coord_dst.writemask = WRITEMASK_XYZW;
1749 }
1750
1751 if (opcode == OPCODE_TXL || opcode == OPCODE_TXB) {
1752 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
1753 coord_dst.writemask = WRITEMASK_W;
1754 ir_to_mesa_emit_op1(ir, OPCODE_MOV, coord_dst, lod_info);
1755 coord_dst.writemask = WRITEMASK_XYZW;
1756 }
1757
1758 inst = ir_to_mesa_emit_op1(ir, opcode, result_dst, coord);
1759
1760 if (ir->shadow_comparitor)
1761 inst->tex_shadow = GL_TRUE;
1762
1763 inst->sampler = _mesa_get_sampler_uniform_value(ir->sampler,
1764 this->shader_program,
1765 this->prog);
1766
1767 const glsl_type *sampler_type = ir->sampler->type;
1768
1769 switch (sampler_type->sampler_dimensionality) {
1770 case GLSL_SAMPLER_DIM_1D:
1771 inst->tex_target = (sampler_type->sampler_array)
1772 ? TEXTURE_1D_ARRAY_INDEX : TEXTURE_1D_INDEX;
1773 break;
1774 case GLSL_SAMPLER_DIM_2D:
1775 inst->tex_target = (sampler_type->sampler_array)
1776 ? TEXTURE_2D_ARRAY_INDEX : TEXTURE_2D_INDEX;
1777 break;
1778 case GLSL_SAMPLER_DIM_3D:
1779 inst->tex_target = TEXTURE_3D_INDEX;
1780 break;
1781 case GLSL_SAMPLER_DIM_CUBE:
1782 inst->tex_target = TEXTURE_CUBE_INDEX;
1783 break;
1784 case GLSL_SAMPLER_DIM_RECT:
1785 inst->tex_target = TEXTURE_RECT_INDEX;
1786 break;
1787 case GLSL_SAMPLER_DIM_BUF:
1788 assert(!"FINISHME: Implement ARB_texture_buffer_object");
1789 break;
1790 default:
1791 assert(!"Should not get here.");
1792 }
1793
1794 this->result = result_src;
1795 }
1796
1797 void
1798 ir_to_mesa_visitor::visit(ir_return *ir)
1799 {
1800 if (ir->get_value()) {
1801 ir_to_mesa_dst_reg l;
1802 int i;
1803
1804 assert(current_function);
1805
1806 ir->get_value()->accept(this);
1807 ir_to_mesa_src_reg r = this->result;
1808
1809 l = ir_to_mesa_dst_reg_from_src(current_function->return_reg);
1810
1811 for (i = 0; i < type_size(current_function->sig->return_type); i++) {
1812 ir_to_mesa_emit_op1(ir, OPCODE_MOV, l, r);
1813 l.index++;
1814 r.index++;
1815 }
1816 }
1817
1818 ir_to_mesa_emit_op0(ir, OPCODE_RET);
1819 }
1820
1821 void
1822 ir_to_mesa_visitor::visit(ir_discard *ir)
1823 {
1824 struct gl_fragment_program *fp = (struct gl_fragment_program *)this->prog;
1825
1826 assert(ir->condition == NULL); /* FINISHME */
1827
1828 ir_to_mesa_emit_op0(ir, OPCODE_KIL_NV);
1829 fp->UsesKill = GL_TRUE;
1830 }
1831
1832 void
1833 ir_to_mesa_visitor::visit(ir_if *ir)
1834 {
1835 ir_to_mesa_instruction *cond_inst, *if_inst, *else_inst = NULL;
1836 ir_to_mesa_instruction *prev_inst;
1837
1838 prev_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1839
1840 ir->condition->accept(this);
1841 assert(this->result.file != PROGRAM_UNDEFINED);
1842
1843 if (this->options->EmitCondCodes) {
1844 cond_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1845
1846 /* See if we actually generated any instruction for generating
1847 * the condition. If not, then cook up a move to a temp so we
1848 * have something to set cond_update on.
1849 */
1850 if (cond_inst == prev_inst) {
1851 ir_to_mesa_src_reg temp = get_temp(glsl_type::bool_type);
1852 cond_inst = ir_to_mesa_emit_op1(ir->condition, OPCODE_MOV,
1853 ir_to_mesa_dst_reg_from_src(temp),
1854 result);
1855 }
1856 cond_inst->cond_update = GL_TRUE;
1857
1858 if_inst = ir_to_mesa_emit_op0(ir->condition, OPCODE_IF);
1859 if_inst->dst_reg.cond_mask = COND_NE;
1860 } else {
1861 if_inst = ir_to_mesa_emit_op1(ir->condition,
1862 OPCODE_IF, ir_to_mesa_undef_dst,
1863 this->result);
1864 }
1865
1866 this->instructions.push_tail(if_inst);
1867
1868 visit_exec_list(&ir->then_instructions, this);
1869
1870 if (!ir->else_instructions.is_empty()) {
1871 else_inst = ir_to_mesa_emit_op0(ir->condition, OPCODE_ELSE);
1872 visit_exec_list(&ir->else_instructions, this);
1873 }
1874
1875 if_inst = ir_to_mesa_emit_op1(ir->condition, OPCODE_ENDIF,
1876 ir_to_mesa_undef_dst, ir_to_mesa_undef);
1877 }
1878
1879 ir_to_mesa_visitor::ir_to_mesa_visitor()
1880 {
1881 result.file = PROGRAM_UNDEFINED;
1882 next_temp = 1;
1883 next_signature_id = 1;
1884 current_function = NULL;
1885 mem_ctx = talloc_new(NULL);
1886 }
1887
1888 ir_to_mesa_visitor::~ir_to_mesa_visitor()
1889 {
1890 talloc_free(mem_ctx);
1891 }
1892
1893 static struct prog_src_register
1894 mesa_src_reg_from_ir_src_reg(ir_to_mesa_src_reg reg)
1895 {
1896 struct prog_src_register mesa_reg;
1897
1898 mesa_reg.File = reg.file;
1899 assert(reg.index < (1 << INST_INDEX_BITS) - 1);
1900 mesa_reg.Index = reg.index;
1901 mesa_reg.Swizzle = reg.swizzle;
1902 mesa_reg.RelAddr = reg.reladdr != NULL;
1903 mesa_reg.Negate = reg.negate;
1904 mesa_reg.Abs = 0;
1905 mesa_reg.HasIndex2 = GL_FALSE;
1906 mesa_reg.RelAddr2 = 0;
1907 mesa_reg.Index2 = 0;
1908
1909 return mesa_reg;
1910 }
1911
1912 static void
1913 set_branchtargets(ir_to_mesa_visitor *v,
1914 struct prog_instruction *mesa_instructions,
1915 int num_instructions)
1916 {
1917 int if_count = 0, loop_count = 0;
1918 int *if_stack, *loop_stack;
1919 int if_stack_pos = 0, loop_stack_pos = 0;
1920 int i, j;
1921
1922 for (i = 0; i < num_instructions; i++) {
1923 switch (mesa_instructions[i].Opcode) {
1924 case OPCODE_IF:
1925 if_count++;
1926 break;
1927 case OPCODE_BGNLOOP:
1928 loop_count++;
1929 break;
1930 case OPCODE_BRK:
1931 case OPCODE_CONT:
1932 mesa_instructions[i].BranchTarget = -1;
1933 break;
1934 default:
1935 break;
1936 }
1937 }
1938
1939 if_stack = talloc_zero_array(v->mem_ctx, int, if_count);
1940 loop_stack = talloc_zero_array(v->mem_ctx, int, loop_count);
1941
1942 for (i = 0; i < num_instructions; i++) {
1943 switch (mesa_instructions[i].Opcode) {
1944 case OPCODE_IF:
1945 if_stack[if_stack_pos] = i;
1946 if_stack_pos++;
1947 break;
1948 case OPCODE_ELSE:
1949 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
1950 if_stack[if_stack_pos - 1] = i;
1951 break;
1952 case OPCODE_ENDIF:
1953 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
1954 if_stack_pos--;
1955 break;
1956 case OPCODE_BGNLOOP:
1957 loop_stack[loop_stack_pos] = i;
1958 loop_stack_pos++;
1959 break;
1960 case OPCODE_ENDLOOP:
1961 loop_stack_pos--;
1962 /* Rewrite any breaks/conts at this nesting level (haven't
1963 * already had a BranchTarget assigned) to point to the end
1964 * of the loop.
1965 */
1966 for (j = loop_stack[loop_stack_pos]; j < i; j++) {
1967 if (mesa_instructions[j].Opcode == OPCODE_BRK ||
1968 mesa_instructions[j].Opcode == OPCODE_CONT) {
1969 if (mesa_instructions[j].BranchTarget == -1) {
1970 mesa_instructions[j].BranchTarget = i;
1971 }
1972 }
1973 }
1974 /* The loop ends point at each other. */
1975 mesa_instructions[i].BranchTarget = loop_stack[loop_stack_pos];
1976 mesa_instructions[loop_stack[loop_stack_pos]].BranchTarget = i;
1977 break;
1978 case OPCODE_CAL:
1979 foreach_iter(exec_list_iterator, iter, v->function_signatures) {
1980 function_entry *entry = (function_entry *)iter.get();
1981
1982 if (entry->sig_id == mesa_instructions[i].BranchTarget) {
1983 mesa_instructions[i].BranchTarget = entry->inst;
1984 break;
1985 }
1986 }
1987 break;
1988 default:
1989 break;
1990 }
1991 }
1992 }
1993
1994 static void
1995 print_program(struct prog_instruction *mesa_instructions,
1996 ir_instruction **mesa_instruction_annotation,
1997 int num_instructions)
1998 {
1999 ir_instruction *last_ir = NULL;
2000 int i;
2001 int indent = 0;
2002
2003 for (i = 0; i < num_instructions; i++) {
2004 struct prog_instruction *mesa_inst = mesa_instructions + i;
2005 ir_instruction *ir = mesa_instruction_annotation[i];
2006
2007 fprintf(stdout, "%3d: ", i);
2008
2009 if (last_ir != ir && ir) {
2010 int j;
2011
2012 for (j = 0; j < indent; j++) {
2013 fprintf(stdout, " ");
2014 }
2015 ir->print();
2016 printf("\n");
2017 last_ir = ir;
2018
2019 fprintf(stdout, " "); /* line number spacing. */
2020 }
2021
2022 indent = _mesa_fprint_instruction_opt(stdout, mesa_inst, indent,
2023 PROG_PRINT_DEBUG, NULL);
2024 }
2025 }
2026
2027 static void
2028 count_resources(struct gl_program *prog)
2029 {
2030 unsigned int i;
2031
2032 prog->SamplersUsed = 0;
2033
2034 for (i = 0; i < prog->NumInstructions; i++) {
2035 struct prog_instruction *inst = &prog->Instructions[i];
2036
2037 if (_mesa_is_tex_instruction(inst->Opcode)) {
2038 prog->SamplerTargets[inst->TexSrcUnit] =
2039 (gl_texture_index)inst->TexSrcTarget;
2040 prog->SamplersUsed |= 1 << inst->TexSrcUnit;
2041 if (inst->TexShadow) {
2042 prog->ShadowSamplers |= 1 << inst->TexSrcUnit;
2043 }
2044 }
2045 }
2046
2047 _mesa_update_shader_textures_used(prog);
2048 }
2049
2050 struct uniform_sort {
2051 struct gl_uniform *u;
2052 int pos;
2053 };
2054
2055 /* The shader_program->Uniforms list is almost sorted in increasing
2056 * uniform->{Frag,Vert}Pos locations, but not quite when there are
2057 * uniforms shared between targets. We need to add parameters in
2058 * increasing order for the targets.
2059 */
2060 static int
2061 sort_uniforms(const void *a, const void *b)
2062 {
2063 struct uniform_sort *u1 = (struct uniform_sort *)a;
2064 struct uniform_sort *u2 = (struct uniform_sort *)b;
2065
2066 return u1->pos - u2->pos;
2067 }
2068
2069 /* Add the uniforms to the parameters. The linker chose locations
2070 * in our parameters lists (which weren't created yet), which the
2071 * uniforms code will use to poke values into our parameters list
2072 * when uniforms are updated.
2073 */
2074 static void
2075 add_uniforms_to_parameters_list(struct gl_shader_program *shader_program,
2076 struct gl_shader *shader,
2077 struct gl_program *prog)
2078 {
2079 unsigned int i;
2080 unsigned int next_sampler = 0, num_uniforms = 0;
2081 struct uniform_sort *sorted_uniforms;
2082
2083 sorted_uniforms = talloc_array(NULL, struct uniform_sort,
2084 shader_program->Uniforms->NumUniforms);
2085
2086 for (i = 0; i < shader_program->Uniforms->NumUniforms; i++) {
2087 struct gl_uniform *uniform = shader_program->Uniforms->Uniforms + i;
2088 int parameter_index = -1;
2089
2090 switch (shader->Type) {
2091 case GL_VERTEX_SHADER:
2092 parameter_index = uniform->VertPos;
2093 break;
2094 case GL_FRAGMENT_SHADER:
2095 parameter_index = uniform->FragPos;
2096 break;
2097 case GL_GEOMETRY_SHADER:
2098 parameter_index = uniform->GeomPos;
2099 break;
2100 }
2101
2102 /* Only add uniforms used in our target. */
2103 if (parameter_index != -1) {
2104 sorted_uniforms[num_uniforms].pos = parameter_index;
2105 sorted_uniforms[num_uniforms].u = uniform;
2106 num_uniforms++;
2107 }
2108 }
2109
2110 qsort(sorted_uniforms, num_uniforms, sizeof(struct uniform_sort),
2111 sort_uniforms);
2112
2113 for (i = 0; i < num_uniforms; i++) {
2114 struct gl_uniform *uniform = sorted_uniforms[i].u;
2115 int parameter_index = sorted_uniforms[i].pos;
2116 const glsl_type *type = uniform->Type;
2117 unsigned int size;
2118
2119 if (type->is_vector() ||
2120 type->is_scalar()) {
2121 size = type->vector_elements;
2122 } else {
2123 size = type_size(type) * 4;
2124 }
2125
2126 gl_register_file file;
2127 if (type->is_sampler() ||
2128 (type->is_array() && type->fields.array->is_sampler())) {
2129 file = PROGRAM_SAMPLER;
2130 } else {
2131 file = PROGRAM_UNIFORM;
2132 }
2133
2134 GLint index = _mesa_lookup_parameter_index(prog->Parameters, -1,
2135 uniform->Name);
2136
2137 if (index < 0) {
2138 index = _mesa_add_parameter(prog->Parameters, file,
2139 uniform->Name, size, type->gl_type,
2140 NULL, NULL, 0x0);
2141
2142 /* Sampler uniform values are stored in prog->SamplerUnits,
2143 * and the entry in that array is selected by this index we
2144 * store in ParameterValues[].
2145 */
2146 if (file == PROGRAM_SAMPLER) {
2147 for (unsigned int j = 0; j < size / 4; j++)
2148 prog->Parameters->ParameterValues[index + j][0] = next_sampler++;
2149 }
2150
2151 /* The location chosen in the Parameters list here (returned
2152 * from _mesa_add_uniform) has to match what the linker chose.
2153 */
2154 if (index != parameter_index) {
2155 fail_link(shader_program, "Allocation of uniform `%s' to target "
2156 "failed (%d vs %d)\n",
2157 uniform->Name, index, parameter_index);
2158 }
2159 }
2160 }
2161
2162 talloc_free(sorted_uniforms);
2163 }
2164
2165 static void
2166 set_uniform_initializer(struct gl_context *ctx, void *mem_ctx,
2167 struct gl_shader_program *shader_program,
2168 const char *name, const glsl_type *type,
2169 ir_constant *val)
2170 {
2171 if (type->is_record()) {
2172 ir_constant *field_constant;
2173
2174 field_constant = (ir_constant *)val->components.get_head();
2175
2176 for (unsigned int i = 0; i < type->length; i++) {
2177 const glsl_type *field_type = type->fields.structure[i].type;
2178 const char *field_name = talloc_asprintf(mem_ctx, "%s.%s", name,
2179 type->fields.structure[i].name);
2180 set_uniform_initializer(ctx, mem_ctx, shader_program, field_name,
2181 field_type, field_constant);
2182 field_constant = (ir_constant *)field_constant->next;
2183 }
2184 return;
2185 }
2186
2187 int loc = _mesa_get_uniform_location(ctx, shader_program, name);
2188
2189 if (loc == -1) {
2190 fail_link(shader_program,
2191 "Couldn't find uniform for initializer %s\n", name);
2192 return;
2193 }
2194
2195 for (unsigned int i = 0; i < (type->is_array() ? type->length : 1); i++) {
2196 ir_constant *element;
2197 const glsl_type *element_type;
2198 if (type->is_array()) {
2199 element = val->array_elements[i];
2200 element_type = type->fields.array;
2201 } else {
2202 element = val;
2203 element_type = type;
2204 }
2205
2206 void *values;
2207
2208 if (element_type->base_type == GLSL_TYPE_BOOL) {
2209 int *conv = talloc_array(mem_ctx, int, element_type->components());
2210 for (unsigned int j = 0; j < element_type->components(); j++) {
2211 conv[j] = element->value.b[j];
2212 }
2213 values = (void *)conv;
2214 element_type = glsl_type::get_instance(GLSL_TYPE_INT,
2215 element_type->vector_elements,
2216 1);
2217 } else {
2218 values = &element->value;
2219 }
2220
2221 if (element_type->is_matrix()) {
2222 _mesa_uniform_matrix(ctx, shader_program,
2223 element_type->matrix_columns,
2224 element_type->vector_elements,
2225 loc, 1, GL_FALSE, (GLfloat *)values);
2226 loc += element_type->matrix_columns;
2227 } else {
2228 _mesa_uniform(ctx, shader_program, loc, element_type->matrix_columns,
2229 values, element_type->gl_type);
2230 loc += type_size(element_type);
2231 }
2232 }
2233 }
2234
2235 static void
2236 set_uniform_initializers(struct gl_context *ctx,
2237 struct gl_shader_program *shader_program)
2238 {
2239 void *mem_ctx = NULL;
2240
2241 for (unsigned int i = 0; i < MESA_SHADER_TYPES; i++) {
2242 struct gl_shader *shader = shader_program->_LinkedShaders[i];
2243
2244 if (shader == NULL)
2245 continue;
2246
2247 foreach_iter(exec_list_iterator, iter, *shader->ir) {
2248 ir_instruction *ir = (ir_instruction *)iter.get();
2249 ir_variable *var = ir->as_variable();
2250
2251 if (!var || var->mode != ir_var_uniform || !var->constant_value)
2252 continue;
2253
2254 if (!mem_ctx)
2255 mem_ctx = talloc_new(NULL);
2256
2257 set_uniform_initializer(ctx, mem_ctx, shader_program, var->name,
2258 var->type, var->constant_value);
2259 }
2260 }
2261
2262 talloc_free(mem_ctx);
2263 }
2264
2265
2266 /**
2267 * Convert a shader's GLSL IR into a Mesa gl_program.
2268 */
2269 struct gl_program *
2270 get_mesa_program(struct gl_context *ctx, struct gl_shader_program *shader_program,
2271 struct gl_shader *shader)
2272 {
2273 ir_to_mesa_visitor v;
2274 struct prog_instruction *mesa_instructions, *mesa_inst;
2275 ir_instruction **mesa_instruction_annotation;
2276 int i;
2277 struct gl_program *prog;
2278 GLenum target;
2279 const char *target_string;
2280 GLboolean progress;
2281 struct gl_shader_compiler_options *options =
2282 &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(shader->Type)];
2283
2284 switch (shader->Type) {
2285 case GL_VERTEX_SHADER:
2286 target = GL_VERTEX_PROGRAM_ARB;
2287 target_string = "vertex";
2288 break;
2289 case GL_FRAGMENT_SHADER:
2290 target = GL_FRAGMENT_PROGRAM_ARB;
2291 target_string = "fragment";
2292 break;
2293 default:
2294 assert(!"should not be reached");
2295 return NULL;
2296 }
2297
2298 validate_ir_tree(shader->ir);
2299
2300 prog = ctx->Driver.NewProgram(ctx, target, shader_program->Name);
2301 if (!prog)
2302 return NULL;
2303 prog->Parameters = _mesa_new_parameter_list();
2304 prog->Varying = _mesa_new_parameter_list();
2305 prog->Attributes = _mesa_new_parameter_list();
2306 v.ctx = ctx;
2307 v.prog = prog;
2308 v.shader_program = shader_program;
2309 v.options = options;
2310
2311 add_uniforms_to_parameters_list(shader_program, shader, prog);
2312
2313 /* Emit Mesa IR for main(). */
2314 visit_exec_list(shader->ir, &v);
2315 v.ir_to_mesa_emit_op0(NULL, OPCODE_END);
2316
2317 /* Now emit bodies for any functions that were used. */
2318 do {
2319 progress = GL_FALSE;
2320
2321 foreach_iter(exec_list_iterator, iter, v.function_signatures) {
2322 function_entry *entry = (function_entry *)iter.get();
2323
2324 if (!entry->bgn_inst) {
2325 v.current_function = entry;
2326
2327 entry->bgn_inst = v.ir_to_mesa_emit_op0(NULL, OPCODE_BGNSUB);
2328 entry->bgn_inst->function = entry;
2329
2330 visit_exec_list(&entry->sig->body, &v);
2331
2332 ir_to_mesa_instruction *last;
2333 last = (ir_to_mesa_instruction *)v.instructions.get_tail();
2334 if (last->op != OPCODE_RET)
2335 v.ir_to_mesa_emit_op0(NULL, OPCODE_RET);
2336
2337 ir_to_mesa_instruction *end;
2338 end = v.ir_to_mesa_emit_op0(NULL, OPCODE_ENDSUB);
2339 end->function = entry;
2340
2341 progress = GL_TRUE;
2342 }
2343 }
2344 } while (progress);
2345
2346 prog->NumTemporaries = v.next_temp;
2347
2348 int num_instructions = 0;
2349 foreach_iter(exec_list_iterator, iter, v.instructions) {
2350 num_instructions++;
2351 }
2352
2353 mesa_instructions =
2354 (struct prog_instruction *)calloc(num_instructions,
2355 sizeof(*mesa_instructions));
2356 mesa_instruction_annotation = talloc_array(v.mem_ctx, ir_instruction *,
2357 num_instructions);
2358
2359 /* Convert ir_mesa_instructions into prog_instructions.
2360 */
2361 mesa_inst = mesa_instructions;
2362 i = 0;
2363 foreach_iter(exec_list_iterator, iter, v.instructions) {
2364 const ir_to_mesa_instruction *inst = (ir_to_mesa_instruction *)iter.get();
2365
2366 mesa_inst->Opcode = inst->op;
2367 mesa_inst->CondUpdate = inst->cond_update;
2368 mesa_inst->DstReg.File = inst->dst_reg.file;
2369 mesa_inst->DstReg.Index = inst->dst_reg.index;
2370 mesa_inst->DstReg.CondMask = inst->dst_reg.cond_mask;
2371 mesa_inst->DstReg.WriteMask = inst->dst_reg.writemask;
2372 mesa_inst->DstReg.RelAddr = inst->dst_reg.reladdr != NULL;
2373 mesa_inst->SrcReg[0] = mesa_src_reg_from_ir_src_reg(inst->src_reg[0]);
2374 mesa_inst->SrcReg[1] = mesa_src_reg_from_ir_src_reg(inst->src_reg[1]);
2375 mesa_inst->SrcReg[2] = mesa_src_reg_from_ir_src_reg(inst->src_reg[2]);
2376 mesa_inst->TexSrcUnit = inst->sampler;
2377 mesa_inst->TexSrcTarget = inst->tex_target;
2378 mesa_inst->TexShadow = inst->tex_shadow;
2379 mesa_instruction_annotation[i] = inst->ir;
2380
2381 /* Set IndirectRegisterFiles. */
2382 if (mesa_inst->DstReg.RelAddr)
2383 prog->IndirectRegisterFiles |= 1 << mesa_inst->DstReg.File;
2384
2385 /* Update program's bitmask of indirectly accessed register files */
2386 for (unsigned src = 0; src < 3; src++)
2387 if (mesa_inst->SrcReg[src].RelAddr)
2388 prog->IndirectRegisterFiles |= 1 << mesa_inst->SrcReg[src].File;
2389
2390 if (options->EmitNoIfs && mesa_inst->Opcode == OPCODE_IF) {
2391 fail_link(shader_program, "Couldn't flatten if statement\n");
2392 }
2393
2394 switch (mesa_inst->Opcode) {
2395 case OPCODE_BGNSUB:
2396 inst->function->inst = i;
2397 mesa_inst->Comment = strdup(inst->function->sig->function_name());
2398 break;
2399 case OPCODE_ENDSUB:
2400 mesa_inst->Comment = strdup(inst->function->sig->function_name());
2401 break;
2402 case OPCODE_CAL:
2403 mesa_inst->BranchTarget = inst->function->sig_id; /* rewritten later */
2404 break;
2405 case OPCODE_ARL:
2406 prog->NumAddressRegs = 1;
2407 break;
2408 default:
2409 break;
2410 }
2411
2412 mesa_inst++;
2413 i++;
2414 }
2415
2416 set_branchtargets(&v, mesa_instructions, num_instructions);
2417
2418 if (ctx->Shader.Flags & GLSL_DUMP) {
2419 printf("\n");
2420 printf("GLSL IR for linked %s program %d:\n", target_string,
2421 shader_program->Name);
2422 _mesa_print_ir(shader->ir, NULL);
2423 printf("\n");
2424 printf("\n");
2425 printf("Mesa IR for linked %s program %d:\n", target_string,
2426 shader_program->Name);
2427 print_program(mesa_instructions, mesa_instruction_annotation,
2428 num_instructions);
2429 }
2430
2431 prog->Instructions = mesa_instructions;
2432 prog->NumInstructions = num_instructions;
2433
2434 do_set_program_inouts(shader->ir, prog);
2435 count_resources(prog);
2436
2437 _mesa_reference_program(ctx, &shader->Program, prog);
2438
2439 if ((ctx->Shader.Flags & GLSL_NO_OPT) == 0) {
2440 _mesa_optimize_program(ctx, prog);
2441 }
2442
2443 return prog;
2444 }
2445
2446 extern "C" {
2447
2448 /**
2449 * Called via ctx->Driver.CompilerShader().
2450 * This is a no-op.
2451 * XXX can we remove the ctx->Driver.CompileShader() hook?
2452 */
2453 GLboolean
2454 _mesa_ir_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
2455 {
2456 assert(shader->CompileStatus);
2457 (void) ctx;
2458
2459 return GL_TRUE;
2460 }
2461
2462
2463 /**
2464 * Link a shader.
2465 * Called via ctx->Driver.LinkShader()
2466 * This actually involves converting GLSL IR into Mesa gl_programs with
2467 * code lowering and other optimizations.
2468 */
2469 GLboolean
2470 _mesa_ir_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
2471 {
2472 assert(prog->LinkStatus);
2473
2474 for (unsigned i = 0; i < MESA_SHADER_TYPES; i++) {
2475 if (prog->_LinkedShaders[i] == NULL)
2476 continue;
2477
2478 bool progress;
2479 exec_list *ir = prog->_LinkedShaders[i]->ir;
2480 const struct gl_shader_compiler_options *options =
2481 &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(prog->_LinkedShaders[i]->Type)];
2482
2483 do {
2484 progress = false;
2485
2486 /* Lowering */
2487 do_mat_op_to_vec(ir);
2488 do_mod_to_fract(ir);
2489 do_div_to_mul_rcp(ir);
2490 do_explog_to_explog2(ir);
2491
2492 progress = do_lower_jumps(ir, true, true, options->EmitNoMainReturn, options->EmitNoCont, options->EmitNoLoops) || progress;
2493
2494 progress = do_common_optimization(ir, true, options->MaxUnrollIterations) || progress;
2495
2496 if (options->EmitNoIfs)
2497 progress = do_if_to_cond_assign(ir) || progress;
2498
2499 if (options->EmitNoNoise)
2500 progress = lower_noise(ir) || progress;
2501
2502 /* If there are forms of indirect addressing that the driver
2503 * cannot handle, perform the lowering pass.
2504 */
2505 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput
2506 || options->EmitNoIndirectTemp || options->EmitNoIndirectUniform)
2507 progress =
2508 lower_variable_index_to_cond_assign(ir,
2509 options->EmitNoIndirectInput,
2510 options->EmitNoIndirectOutput,
2511 options->EmitNoIndirectTemp,
2512 options->EmitNoIndirectUniform)
2513 || progress;
2514
2515 progress = do_vec_index_to_cond_assign(ir) || progress;
2516 } while (progress);
2517
2518 validate_ir_tree(ir);
2519 }
2520
2521 for (unsigned i = 0; i < MESA_SHADER_TYPES; i++) {
2522 struct gl_program *linked_prog;
2523 bool ok = true;
2524
2525 if (prog->_LinkedShaders[i] == NULL)
2526 continue;
2527
2528 linked_prog = get_mesa_program(ctx, prog, prog->_LinkedShaders[i]);
2529
2530 switch (prog->_LinkedShaders[i]->Type) {
2531 case GL_VERTEX_SHADER:
2532 _mesa_reference_vertprog(ctx, &prog->VertexProgram,
2533 (struct gl_vertex_program *)linked_prog);
2534 ok = ctx->Driver.ProgramStringNotify(ctx, GL_VERTEX_PROGRAM_ARB,
2535 linked_prog);
2536 break;
2537 case GL_FRAGMENT_SHADER:
2538 _mesa_reference_fragprog(ctx, &prog->FragmentProgram,
2539 (struct gl_fragment_program *)linked_prog);
2540 ok = ctx->Driver.ProgramStringNotify(ctx, GL_FRAGMENT_PROGRAM_ARB,
2541 linked_prog);
2542 break;
2543 }
2544 if (!ok) {
2545 return GL_FALSE;
2546 }
2547 _mesa_reference_program(ctx, &linked_prog, NULL);
2548 }
2549
2550 return GL_TRUE;
2551 }
2552
2553
2554 /**
2555 * Compile a GLSL shader. Called via glCompileShader().
2556 */
2557 void
2558 _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
2559 {
2560 struct _mesa_glsl_parse_state *state =
2561 new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shader);
2562
2563 const char *source = shader->Source;
2564 /* Check if the user called glCompileShader without first calling
2565 * glShaderSource. This should fail to compile, but not raise a GL_ERROR.
2566 */
2567 if (source == NULL) {
2568 shader->CompileStatus = GL_FALSE;
2569 return;
2570 }
2571
2572 state->error = preprocess(state, &source, &state->info_log,
2573 &ctx->Extensions, ctx->API);
2574
2575 if (ctx->Shader.Flags & GLSL_DUMP) {
2576 printf("GLSL source for shader %d:\n", shader->Name);
2577 printf("%s\n", shader->Source);
2578 }
2579
2580 if (!state->error) {
2581 _mesa_glsl_lexer_ctor(state, source);
2582 _mesa_glsl_parse(state);
2583 _mesa_glsl_lexer_dtor(state);
2584 }
2585
2586 talloc_free(shader->ir);
2587 shader->ir = new(shader) exec_list;
2588 if (!state->error && !state->translation_unit.is_empty())
2589 _mesa_ast_to_hir(shader->ir, state);
2590
2591 if (!state->error && !shader->ir->is_empty()) {
2592 validate_ir_tree(shader->ir);
2593
2594 /* Do some optimization at compile time to reduce shader IR size
2595 * and reduce later work if the same shader is linked multiple times
2596 */
2597 while (do_common_optimization(shader->ir, false, 32))
2598 ;
2599
2600 validate_ir_tree(shader->ir);
2601 }
2602
2603 shader->symbols = state->symbols;
2604
2605 shader->CompileStatus = !state->error;
2606 shader->InfoLog = state->info_log;
2607 shader->Version = state->language_version;
2608 memcpy(shader->builtins_to_link, state->builtins_to_link,
2609 sizeof(shader->builtins_to_link[0]) * state->num_builtins_to_link);
2610 shader->num_builtins_to_link = state->num_builtins_to_link;
2611
2612 if (ctx->Shader.Flags & GLSL_LOG) {
2613 _mesa_write_shader_to_file(shader);
2614 }
2615
2616 if (ctx->Shader.Flags & GLSL_DUMP) {
2617 if (shader->CompileStatus) {
2618 printf("GLSL IR for shader %d:\n", shader->Name);
2619 _mesa_print_ir(shader->ir, NULL);
2620 printf("\n\n");
2621 } else {
2622 printf("GLSL shader %d failed to compile.\n", shader->Name);
2623 }
2624 if (shader->InfoLog && shader->InfoLog[0] != 0) {
2625 printf("GLSL shader %d info log:\n", shader->Name);
2626 printf("%s\n", shader->InfoLog);
2627 }
2628 }
2629
2630 /* Retain any live IR, but trash the rest. */
2631 reparent_ir(shader->ir, shader->ir);
2632
2633 talloc_free(state);
2634
2635 if (shader->CompileStatus) {
2636 if (!ctx->Driver.CompileShader(ctx, shader))
2637 shader->CompileStatus = GL_FALSE;
2638 }
2639 }
2640
2641
2642 /**
2643 * Link a GLSL shader program. Called via glLinkProgram().
2644 */
2645 void
2646 _mesa_glsl_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
2647 {
2648 unsigned int i;
2649
2650 _mesa_clear_shader_program_data(ctx, prog);
2651
2652 prog->LinkStatus = GL_TRUE;
2653
2654 for (i = 0; i < prog->NumShaders; i++) {
2655 if (!prog->Shaders[i]->CompileStatus) {
2656 fail_link(prog, "linking with uncompiled shader");
2657 prog->LinkStatus = GL_FALSE;
2658 }
2659 }
2660
2661 prog->Varying = _mesa_new_parameter_list();
2662 _mesa_reference_vertprog(ctx, &prog->VertexProgram, NULL);
2663 _mesa_reference_fragprog(ctx, &prog->FragmentProgram, NULL);
2664
2665 if (prog->LinkStatus) {
2666 link_shaders(ctx, prog);
2667 }
2668
2669 if (prog->LinkStatus) {
2670 if (!ctx->Driver.LinkShader(ctx, prog)) {
2671 prog->LinkStatus = GL_FALSE;
2672 }
2673 }
2674
2675 set_uniform_initializers(ctx, prog);
2676
2677 if (ctx->Shader.Flags & GLSL_DUMP) {
2678 if (!prog->LinkStatus) {
2679 printf("GLSL shader program %d failed to link\n", prog->Name);
2680 }
2681
2682 if (prog->InfoLog && prog->InfoLog[0] != 0) {
2683 printf("GLSL shader program %d info log:\n", prog->Name);
2684 printf("%s\n", prog->InfoLog);
2685 }
2686 }
2687 }
2688
2689 } /* extern "C" */