2 * Mesa 3-D graphics library
4 * Copyright (C) 1999-2008 Brian Paul All Rights Reserved.
5 * Copyright (C) 1999-2009 VMware, Inc. All Rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "main/glheader.h"
28 #include "main/imports.h"
29 #include "main/mtypes.h"
30 #include "prog_instruction.h"
34 * Initialize program instruction fields to defaults.
35 * \param inst first instruction to initialize
36 * \param count number of instructions to initialize
39 _mesa_init_instructions(struct prog_instruction
*inst
, GLuint count
)
43 memset(inst
, 0, count
* sizeof(struct prog_instruction
));
45 for (i
= 0; i
< count
; i
++) {
46 inst
[i
].SrcReg
[0].File
= PROGRAM_UNDEFINED
;
47 inst
[i
].SrcReg
[0].Swizzle
= SWIZZLE_NOOP
;
48 inst
[i
].SrcReg
[1].File
= PROGRAM_UNDEFINED
;
49 inst
[i
].SrcReg
[1].Swizzle
= SWIZZLE_NOOP
;
50 inst
[i
].SrcReg
[2].File
= PROGRAM_UNDEFINED
;
51 inst
[i
].SrcReg
[2].Swizzle
= SWIZZLE_NOOP
;
53 inst
[i
].DstReg
.File
= PROGRAM_UNDEFINED
;
54 inst
[i
].DstReg
.WriteMask
= WRITEMASK_XYZW
;
55 inst
[i
].DstReg
.CondMask
= COND_TR
;
56 inst
[i
].DstReg
.CondSwizzle
= SWIZZLE_NOOP
;
58 inst
[i
].SaturateMode
= SATURATE_OFF
;
59 inst
[i
].Precision
= FLOAT32
;
65 * Allocate an array of program instructions.
66 * \param numInst number of instructions
67 * \return pointer to instruction memory
69 struct prog_instruction
*
70 _mesa_alloc_instructions(GLuint numInst
)
73 calloc(numInst
, sizeof(struct prog_instruction
));
78 * Copy an array of program instructions.
79 * \param dest pointer to destination.
80 * \param src pointer to source.
81 * \param n number of instructions to copy.
82 * \return pointer to destination.
84 struct prog_instruction
*
85 _mesa_copy_instructions(struct prog_instruction
*dest
,
86 const struct prog_instruction
*src
, GLuint n
)
89 memcpy(dest
, src
, n
* sizeof(struct prog_instruction
));
90 for (i
= 0; i
< n
; i
++) {
92 dest
[i
].Comment
= _mesa_strdup(src
[i
].Comment
);
99 * Free an array of instructions
102 _mesa_free_instructions(struct prog_instruction
*inst
, GLuint count
)
105 for (i
= 0; i
< count
; i
++) {
106 free((char *)inst
[i
].Comment
);
113 * Basic info about each instruction
115 struct instruction_info
117 gl_inst_opcode Opcode
;
125 * \note Opcode should equal array index!
127 static const struct instruction_info InstInfo
[MAX_OPCODE
] = {
128 { OPCODE_NOP
, "NOP", 0, 0 },
129 { OPCODE_ABS
, "ABS", 1, 1 },
130 { OPCODE_ADD
, "ADD", 2, 1 },
131 { OPCODE_ARL
, "ARL", 1, 1 },
132 { OPCODE_BGNLOOP
,"BGNLOOP", 0, 0 },
133 { OPCODE_BGNSUB
, "BGNSUB", 0, 0 },
134 { OPCODE_BRK
, "BRK", 0, 0 },
135 { OPCODE_CAL
, "CAL", 0, 0 },
136 { OPCODE_CMP
, "CMP", 3, 1 },
137 { OPCODE_CONT
, "CONT", 0, 0 },
138 { OPCODE_COS
, "COS", 1, 1 },
139 { OPCODE_DDX
, "DDX", 1, 1 },
140 { OPCODE_DDY
, "DDY", 1, 1 },
141 { OPCODE_DP2
, "DP2", 2, 1 },
142 { OPCODE_DP3
, "DP3", 2, 1 },
143 { OPCODE_DP4
, "DP4", 2, 1 },
144 { OPCODE_DPH
, "DPH", 2, 1 },
145 { OPCODE_DST
, "DST", 2, 1 },
146 { OPCODE_ELSE
, "ELSE", 0, 0 },
147 { OPCODE_END
, "END", 0, 0 },
148 { OPCODE_ENDIF
, "ENDIF", 0, 0 },
149 { OPCODE_ENDLOOP
,"ENDLOOP", 0, 0 },
150 { OPCODE_ENDSUB
, "ENDSUB", 0, 0 },
151 { OPCODE_EX2
, "EX2", 1, 1 },
152 { OPCODE_EXP
, "EXP", 1, 1 },
153 { OPCODE_FLR
, "FLR", 1, 1 },
154 { OPCODE_FRC
, "FRC", 1, 1 },
155 { OPCODE_IF
, "IF", 1, 0 },
156 { OPCODE_KIL
, "KIL", 1, 0 },
157 { OPCODE_KIL_NV
, "KIL_NV", 0, 0 },
158 { OPCODE_LG2
, "LG2", 1, 1 },
159 { OPCODE_LIT
, "LIT", 1, 1 },
160 { OPCODE_LOG
, "LOG", 1, 1 },
161 { OPCODE_LRP
, "LRP", 3, 1 },
162 { OPCODE_MAD
, "MAD", 3, 1 },
163 { OPCODE_MAX
, "MAX", 2, 1 },
164 { OPCODE_MIN
, "MIN", 2, 1 },
165 { OPCODE_MOV
, "MOV", 1, 1 },
166 { OPCODE_MUL
, "MUL", 2, 1 },
167 { OPCODE_NOISE1
, "NOISE1", 1, 1 },
168 { OPCODE_NOISE2
, "NOISE2", 1, 1 },
169 { OPCODE_NOISE3
, "NOISE3", 1, 1 },
170 { OPCODE_NOISE4
, "NOISE4", 1, 1 },
171 { OPCODE_POW
, "POW", 2, 1 },
172 { OPCODE_RCP
, "RCP", 1, 1 },
173 { OPCODE_RET
, "RET", 0, 0 },
174 { OPCODE_RSQ
, "RSQ", 1, 1 },
175 { OPCODE_SCS
, "SCS", 1, 1 },
176 { OPCODE_SEQ
, "SEQ", 2, 1 },
177 { OPCODE_SGE
, "SGE", 2, 1 },
178 { OPCODE_SGT
, "SGT", 2, 1 },
179 { OPCODE_SIN
, "SIN", 1, 1 },
180 { OPCODE_SLE
, "SLE", 2, 1 },
181 { OPCODE_SLT
, "SLT", 2, 1 },
182 { OPCODE_SNE
, "SNE", 2, 1 },
183 { OPCODE_SSG
, "SSG", 1, 1 },
184 { OPCODE_SUB
, "SUB", 2, 1 },
185 { OPCODE_SWZ
, "SWZ", 1, 1 },
186 { OPCODE_TEX
, "TEX", 1, 1 },
187 { OPCODE_TXB
, "TXB", 1, 1 },
188 { OPCODE_TXD
, "TXD", 3, 1 },
189 { OPCODE_TXL
, "TXL", 1, 1 },
190 { OPCODE_TXP
, "TXP", 1, 1 },
191 { OPCODE_TXP_NV
, "TXP_NV", 1, 1 },
192 { OPCODE_TRUNC
, "TRUNC", 1, 1 },
193 { OPCODE_XPD
, "XPD", 2, 1 }
198 * Return the number of src registers for the given instruction/opcode.
201 _mesa_num_inst_src_regs(gl_inst_opcode opcode
)
203 assert(opcode
< MAX_OPCODE
);
204 assert(opcode
== InstInfo
[opcode
].Opcode
);
205 assert(OPCODE_XPD
== InstInfo
[OPCODE_XPD
].Opcode
);
206 return InstInfo
[opcode
].NumSrcRegs
;
211 * Return the number of dst registers for the given instruction/opcode.
214 _mesa_num_inst_dst_regs(gl_inst_opcode opcode
)
216 assert(opcode
< MAX_OPCODE
);
217 assert(opcode
== InstInfo
[opcode
].Opcode
);
218 assert(OPCODE_XPD
== InstInfo
[OPCODE_XPD
].Opcode
);
219 return InstInfo
[opcode
].NumDstRegs
;
224 _mesa_is_tex_instruction(gl_inst_opcode opcode
)
226 return (opcode
== OPCODE_TEX
||
227 opcode
== OPCODE_TXB
||
228 opcode
== OPCODE_TXD
||
229 opcode
== OPCODE_TXL
||
230 opcode
== OPCODE_TXP
);
235 * Check if there's a potential src/dst register data dependency when
236 * using SOA execution.
239 * This would expand into:
244 * The second instruction will have the wrong value for t0 if executed as-is.
247 _mesa_check_soa_dependencies(const struct prog_instruction
*inst
)
251 if (inst
->DstReg
.WriteMask
== WRITEMASK_X
||
252 inst
->DstReg
.WriteMask
== WRITEMASK_Y
||
253 inst
->DstReg
.WriteMask
== WRITEMASK_Z
||
254 inst
->DstReg
.WriteMask
== WRITEMASK_W
||
255 inst
->DstReg
.WriteMask
== 0x0) {
256 /* no chance of data dependency */
260 /* loop over src regs */
261 for (i
= 0; i
< 3; i
++) {
262 if (inst
->SrcReg
[i
].File
== inst
->DstReg
.File
&&
263 inst
->SrcReg
[i
].Index
== inst
->DstReg
.Index
) {
264 /* loop over dest channels */
265 GLuint channelsWritten
= 0x0;
266 for (chan
= 0; chan
< 4; chan
++) {
267 if (inst
->DstReg
.WriteMask
& (1 << chan
)) {
268 /* check if we're reading a channel that's been written */
269 GLuint swizzle
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, chan
);
270 if (swizzle
<= SWIZZLE_W
&&
271 (channelsWritten
& (1 << swizzle
))) {
275 channelsWritten
|= (1 << chan
);
285 * Return string name for given program opcode.
288 _mesa_opcode_string(gl_inst_opcode opcode
)
290 if (opcode
< MAX_OPCODE
)
291 return InstInfo
[opcode
].Name
;
294 _mesa_snprintf(s
, sizeof(s
), "OP%u", opcode
);