src/mesa/program/prog_to_nir.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  * Copyright © 2014-2015 Broadcom
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25
  26 #include "compiler/nir/nir.h"
  27 #include "compiler/nir/nir_builder.h"
  28 #include "compiler/glsl/list.h"
  29 #include "main/imports.h"
  30 #include "util/ralloc.h"
  31
  32 #include "prog_to_nir.h"
  33 #include "prog_instruction.h"
  34 #include "prog_parameter.h"
  35 #include "prog_print.h"
  36 #include "program.h"
  37
  38 /**
  39  * \file prog_to_nir.c
  40  *
  41  * A translator from Mesa IR (prog_instruction.h) to NIR.  This is primarily
  42  * intended to support ARB_vertex_program, ARB_fragment_program, and fixed-function
  43  * vertex processing.  Full GLSL support should use glsl_to_nir instead.
  44  */
  45
  46 struct ptn_compile {
  47    const struct gl_program *prog;
  48    nir_builder build;
  49    bool error;
  50
  51    nir_variable *parameters;
  52    nir_variable *input_vars[VARYING_SLOT_MAX];
  53    nir_variable *output_vars[VARYING_SLOT_MAX];
  54    nir_register **output_regs;
  55    nir_register **temp_regs;
  56
  57    nir_register *addr_reg;
  58 };
  59
  60 #define SWIZ(X, Y, Z, W) \
  61    (unsigned[4]){ SWIZZLE_##X, SWIZZLE_##Y, SWIZZLE_##Z, SWIZZLE_##W }
  62 #define ptn_channel(b, src, ch) nir_swizzle(b, src, SWIZ(ch, ch, ch, ch), 1, true)
  63
  64 static nir_ssa_def *
  65 ptn_src_for_dest(struct ptn_compile *c, nir_alu_dest *dest)
  66 {
  67    nir_builder *b = &c->build;
  68
  69    nir_alu_src src;
  70    memset(&src, 0, sizeof(src));
  71
  72    if (dest->dest.is_ssa)
  73       src.src = nir_src_for_ssa(&dest->dest.ssa);
  74    else {
  75       assert(!dest->dest.reg.indirect);
  76       src.src = nir_src_for_reg(dest->dest.reg.reg);
  77       src.src.reg.base_offset = dest->dest.reg.base_offset;
  78    }
  79
  80    for (int i = 0; i < 4; i++)
  81       src.swizzle[i] = i;
  82
  83    return nir_fmov_alu(b, src, 4);
  84 }
  85
  86 static nir_alu_dest
  87 ptn_get_dest(struct ptn_compile *c, const struct prog_dst_register *prog_dst)
  88 {
  89    nir_alu_dest dest;
  90
  91    memset(&dest, 0, sizeof(dest));
  92
  93    switch (prog_dst->File) {
  94    case PROGRAM_TEMPORARY:
  95       dest.dest.reg.reg = c->temp_regs[prog_dst->Index];
  96       break;
  97    case PROGRAM_OUTPUT:
  98       dest.dest.reg.reg = c->output_regs[prog_dst->Index];
  99       break;
 100    case PROGRAM_ADDRESS:
 101       assert(prog_dst->Index == 0);
 102       dest.dest.reg.reg = c->addr_reg;
 103       break;
 104    case PROGRAM_UNDEFINED:
 105       break;
 106    }
 107
 108    dest.write_mask = prog_dst->WriteMask;
 109    dest.saturate = false;
 110
 111    assert(!prog_dst->RelAddr);
 112
 113    return dest;
 114 }
 115
 116 static nir_ssa_def *
 117 ptn_get_src(struct ptn_compile *c, const struct prog_src_register *prog_src)
 118 {
 119    nir_builder *b = &c->build;
 120    nir_alu_src src;
 121
 122    memset(&src, 0, sizeof(src));
 123
 124    switch (prog_src->File) {
 125    case PROGRAM_UNDEFINED:
 126       return nir_imm_float(b, 0.0);
 127    case PROGRAM_TEMPORARY:
 128       assert(!prog_src->RelAddr && prog_src->Index >= 0);
 129       src.src.reg.reg = c->temp_regs[prog_src->Index];
 130       break;
 131    case PROGRAM_INPUT: {
 132       /* ARB_vertex_program doesn't allow relative addressing on vertex
 133        * attributes; ARB_fragment_program has no relative addressing at all.
 134        */
 135       assert(!prog_src->RelAddr);
 136
 137       assert(prog_src->Index >= 0 && prog_src->Index < VARYING_SLOT_MAX);
 138
 139       nir_intrinsic_instr *load =
 140          nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_var);
 141       load->num_components = 4;
 142       load->variables[0] = nir_deref_var_create(load, c->input_vars[prog_src->Index]);
 143
 144       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
 145       nir_builder_instr_insert(b, &load->instr);
 146
 147       src.src = nir_src_for_ssa(&load->dest.ssa);
 148       break;
 149    }
 150    case PROGRAM_STATE_VAR:
 151    case PROGRAM_CONSTANT: {
 152       /* We actually want to look at the type in the Parameters list for this,
 153        * because it lets us upload constant builtin uniforms as actual
 154        * constants.
 155        */
 156       struct gl_program_parameter_list *plist = c->prog->Parameters;
 157       gl_register_file file = prog_src->RelAddr ? prog_src->File :
 158          plist->Parameters[prog_src->Index].Type;
 159
 160       switch (file) {
 161       case PROGRAM_CONSTANT:
 162          if ((c->prog->IndirectRegisterFiles & (1 << PROGRAM_CONSTANT)) == 0) {
 163             float *v = (float *) plist->ParameterValues[prog_src->Index];
 164             src.src = nir_src_for_ssa(nir_imm_vec4(b, v[0], v[1], v[2], v[3]));
 165             break;
 166          }
 167          /* FALLTHROUGH */
 168       case PROGRAM_STATE_VAR: {
 169          assert(c->parameters != NULL);
 170
 171          nir_intrinsic_instr *load =
 172             nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_var);
 173          nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
 174          load->num_components = 4;
 175
 176          load->variables[0] = nir_deref_var_create(load, c->parameters);
 177          nir_deref_array *deref_arr =
 178             nir_deref_array_create(load->variables[0]);
 179          deref_arr->deref.type = glsl_vec4_type();
 180          load->variables[0]->deref.child = &deref_arr->deref;
 181
 182          if (prog_src->RelAddr) {
 183             deref_arr->deref_array_type = nir_deref_array_type_indirect;
 184
 185             nir_alu_src addr_src = { NIR_SRC_INIT };
 186             addr_src.src = nir_src_for_reg(c->addr_reg);
 187             nir_ssa_def *reladdr = nir_imov_alu(b, addr_src, 1);
 188
 189             if (prog_src->Index < 0) {
 190                /* This is a negative offset which should be added to the address
 191                 * register's value.
 192                 */
 193                reladdr = nir_iadd(b, reladdr, nir_imm_int(b, prog_src->Index));
 194
 195                deref_arr->base_offset = 0;
 196             } else {
 197                deref_arr->base_offset = prog_src->Index;
 198             }
 199             deref_arr->indirect = nir_src_for_ssa(reladdr);
 200          } else {
 201             deref_arr->deref_array_type = nir_deref_array_type_direct;
 202             deref_arr->base_offset = prog_src->Index;
 203          }
 204
 205          nir_builder_instr_insert(b, &load->instr);
 206
 207          src.src = nir_src_for_ssa(&load->dest.ssa);
 208          break;
 209       }
 210       default:
 211          fprintf(stderr, "bad uniform src register file: %s (%d)\n",
 212                  _mesa_register_file_name(file), file);
 213          abort();
 214       }
 215       break;
 216    }
 217    default:
 218       fprintf(stderr, "unknown src register file: %s (%d)\n",
 219               _mesa_register_file_name(prog_src->File), prog_src->File);
 220       abort();
 221    }
 222
 223    nir_ssa_def *def;
 224    if (!HAS_EXTENDED_SWIZZLE(prog_src->Swizzle) &&
 225        (prog_src->Negate == NEGATE_NONE || prog_src->Negate == NEGATE_XYZW)) {
 226       /* The simple non-SWZ case. */
 227       for (int i = 0; i < 4; i++)
 228          src.swizzle[i] = GET_SWZ(prog_src->Swizzle, i);
 229
 230       def = nir_fmov_alu(b, src, 4);
 231
 232       if (prog_src->Negate)
 233          def = nir_fneg(b, def);
 234    } else {
 235       /* The SWZ instruction allows per-component zero/one swizzles, and also
 236        * per-component negation.
 237        */
 238       nir_ssa_def *chans[4];
 239       for (int i = 0; i < 4; i++) {
 240          int swizzle = GET_SWZ(prog_src->Swizzle, i);
 241          if (swizzle == SWIZZLE_ZERO) {
 242             chans[i] = nir_imm_float(b, 0.0);
 243          } else if (swizzle == SWIZZLE_ONE) {
 244             chans[i] = nir_imm_float(b, 1.0);
 245          } else {
 246             assert(swizzle != SWIZZLE_NIL);
 247             nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_fmov);
 248             nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, 32, NULL);
 249             mov->dest.write_mask = 0x1;
 250             mov->src[0] = src;
 251             mov->src[0].swizzle[0] = swizzle;
 252             nir_builder_instr_insert(b, &mov->instr);
 253
 254             chans[i] = &mov->dest.dest.ssa;
 255          }
 256
 257          if (prog_src->Negate & (1 << i))
 258             chans[i] = nir_fneg(b, chans[i]);
 259       }
 260       def = nir_vec4(b, chans[0], chans[1], chans[2], chans[3]);
 261    }
 262
 263    return def;
 264 }
 265
 266 static void
 267 ptn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
 268 {
 269    unsigned num_srcs = nir_op_infos[op].num_inputs;
 270    nir_alu_instr *instr = nir_alu_instr_create(b->shader, op);
 271    unsigned i;
 272
 273    for (i = 0; i < num_srcs; i++)
 274       instr->src[i].src = nir_src_for_ssa(src[i]);
 275
 276    instr->dest = dest;
 277    nir_builder_instr_insert(b, &instr->instr);
 278 }
 279
 280 static void
 281 ptn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
 282                      nir_ssa_def *def, unsigned write_mask)
 283 {
 284    if (!(dest.write_mask & write_mask))
 285       return;
 286
 287    nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_fmov);
 288    if (!mov)
 289       return;
 290
 291    mov->dest = dest;
 292    mov->dest.write_mask &= write_mask;
 293    mov->src[0].src = nir_src_for_ssa(def);
 294    for (unsigned i = def->num_components; i < 4; i++)
 295       mov->src[0].swizzle[i] = def->num_components - 1;
 296    nir_builder_instr_insert(b, &mov->instr);
 297 }
 298
 299 static void
 300 ptn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
 301 {
 302    ptn_move_dest_masked(b, dest, def, WRITEMASK_XYZW);
 303 }
 304
 305 static void
 306 ptn_arl(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 307 {
 308    ptn_move_dest(b, dest, nir_f2i(b, nir_ffloor(b, src[0])));
 309 }
 310
 311 /* EXP - Approximate Exponential Base 2
 312  *  dst.x = 2^{\lfloor src.x\rfloor}
 313  *  dst.y = src.x - \lfloor src.x\rfloor
 314  *  dst.z = 2^{src.x}
 315  *  dst.w = 1.0
 316  */
 317 static void
 318 ptn_exp(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 319 {
 320    nir_ssa_def *srcx = ptn_channel(b, src[0], X);
 321
 322    ptn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)), WRITEMASK_X);
 323    ptn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)), WRITEMASK_Y);
 324    ptn_move_dest_masked(b, dest, nir_fexp2(b, srcx), WRITEMASK_Z);
 325    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_W);
 326 }
 327
 328 /* LOG - Approximate Logarithm Base 2
 329  *  dst.x = \lfloor\log_2{|src.x|}\rfloor
 330  *  dst.y = |src.x| * 2^{-\lfloor\log_2{|src.x|}\rfloor}}
 331  *  dst.z = \log_2{|src.x|}
 332  *  dst.w = 1.0
 333  */
 334 static void
 335 ptn_log(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 336 {
 337    nir_ssa_def *abs_srcx = nir_fabs(b, ptn_channel(b, src[0], X));
 338    nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
 339    nir_ssa_def *floor_log2 = nir_ffloor(b, log2);
 340
 341    ptn_move_dest_masked(b, dest, floor_log2, WRITEMASK_X);
 342    ptn_move_dest_masked(b, dest,
 343                         nir_fmul(b, abs_srcx,
 344                                  nir_fexp2(b, nir_fneg(b, floor_log2))),
 345                         WRITEMASK_Y);
 346    ptn_move_dest_masked(b, dest, log2, WRITEMASK_Z);
 347    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_W);
 348 }
 349
 350 /* DST - Distance Vector
 351  *   dst.x = 1.0
 352  *   dst.y = src0.y \times src1.y
 353  *   dst.z = src0.z
 354  *   dst.w = src1.w
 355  */
 356 static void
 357 ptn_dst(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 358 {
 359    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_X);
 360    ptn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), WRITEMASK_Y);
 361    ptn_move_dest_masked(b, dest, nir_fmov(b, src[0]), WRITEMASK_Z);
 362    ptn_move_dest_masked(b, dest, nir_fmov(b, src[1]), WRITEMASK_W);
 363 }
 364
 365 /* LIT - Light Coefficients
 366  *  dst.x = 1.0
 367  *  dst.y = max(src.x, 0.0)
 368  *  dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
 369  *  dst.w = 1.0
 370  */
 371 static void
 372 ptn_lit(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 373 {
 374    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_XW);
 375
 376    ptn_move_dest_masked(b, dest, nir_fmax(b, ptn_channel(b, src[0], X),
 377                                           nir_imm_float(b, 0.0)), WRITEMASK_Y);
 378
 379    if (dest.write_mask & WRITEMASK_Z) {
 380       nir_ssa_def *src0_y = ptn_channel(b, src[0], Y);
 381       nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ptn_channel(b, src[0], W),
 382                                                  nir_imm_float(b, 128.0)),
 383                                      nir_imm_float(b, -128.0));
 384       nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
 385                                   wclamp);
 386
 387       nir_ssa_def *z;
 388       if (b->shader->options->native_integers) {
 389          z = nir_bcsel(b,
 390                        nir_fge(b, nir_imm_float(b, 0.0), ptn_channel(b, src[0], X)),
 391                        nir_imm_float(b, 0.0),
 392                        pow);
 393       } else {
 394          z = nir_fcsel(b,
 395                        nir_sge(b, nir_imm_float(b, 0.0), ptn_channel(b, src[0], X)),
 396                        nir_imm_float(b, 0.0),
 397                        pow);
 398       }
 399
 400       ptn_move_dest_masked(b, dest, z, WRITEMASK_Z);
 401    }
 402 }
 403
 404 /* SCS - Sine Cosine
 405  *   dst.x = \cos{src.x}
 406  *   dst.y = \sin{src.x}
 407  *   dst.z = 0.0
 408  *   dst.w = 1.0
 409  */
 410 static void
 411 ptn_scs(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 412 {
 413    ptn_move_dest_masked(b, dest, nir_fcos(b, ptn_channel(b, src[0], X)),
 414                         WRITEMASK_X);
 415    ptn_move_dest_masked(b, dest, nir_fsin(b, ptn_channel(b, src[0], X)),
 416                         WRITEMASK_Y);
 417    ptn_move_dest_masked(b, dest, nir_imm_float(b, 0.0), WRITEMASK_Z);
 418    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_W);
 419 }
 420
 421 /**
 422  * Emit SLT.  For platforms with integers, prefer b2f(flt(...)).
 423  */
 424 static void
 425 ptn_slt(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 426 {
 427    if (b->shader->options->native_integers) {
 428       ptn_move_dest(b, dest, nir_b2f(b, nir_flt(b, src[0], src[1])));
 429    } else {
 430       ptn_move_dest(b, dest, nir_slt(b, src[0], src[1]));
 431    }
 432 }
 433
 434 /**
 435  * Emit SGE.  For platforms with integers, prefer b2f(fge(...)).
 436  */
 437 static void
 438 ptn_sge(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 439 {
 440    if (b->shader->options->native_integers) {
 441       ptn_move_dest(b, dest, nir_b2f(b, nir_fge(b, src[0], src[1])));
 442    } else {
 443       ptn_move_dest(b, dest, nir_sge(b, src[0], src[1]));
 444    }
 445 }
 446
 447 static void
 448 ptn_xpd(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 449 {
 450    ptn_move_dest_masked(b, dest,
 451                         nir_fsub(b,
 452                                  nir_fmul(b,
 453                                           nir_swizzle(b, src[0], SWIZ(Y, Z, X, W), 3, true),
 454                                           nir_swizzle(b, src[1], SWIZ(Z, X, Y, W), 3, true)),
 455                                  nir_fmul(b,
 456                                           nir_swizzle(b, src[1], SWIZ(Y, Z, X, W), 3, true),
 457                                           nir_swizzle(b, src[0], SWIZ(Z, X, Y, W), 3, true))),
 458                         WRITEMASK_XYZ);
 459    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_W);
 460 }
 461
 462 static void
 463 ptn_dp2(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 464 {
 465    ptn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
 466 }
 467
 468 static void
 469 ptn_dp3(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 470 {
 471    ptn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
 472 }
 473
 474 static void
 475 ptn_dp4(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 476 {
 477    ptn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
 478 }
 479
 480 static void
 481 ptn_dph(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 482 {
 483    ptn_move_dest(b, dest, nir_fdph(b, src[0], src[1]));
 484 }
 485
 486 static void
 487 ptn_cmp(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 488 {
 489    if (b->shader->options->native_integers) {
 490       ptn_move_dest(b, dest, nir_bcsel(b,
 491                                        nir_flt(b, src[0], nir_imm_float(b, 0.0)),
 492                                        src[1], src[2]));
 493    } else {
 494       ptn_move_dest(b, dest, nir_fcsel(b,
 495                                        nir_slt(b, src[0], nir_imm_float(b, 0.0)),
 496                                        src[1], src[2]));
 497    }
 498 }
 499
 500 static void
 501 ptn_lrp(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 502 {
 503    ptn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
 504 }
 505
 506 static void
 507 ptn_kil(nir_builder *b, nir_ssa_def **src)
 508 {
 509    nir_ssa_def *cmp = b->shader->options->native_integers ?
 510       nir_bany_inequal4(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)), nir_imm_int(b, 0)) :
 511       nir_fany_nequal4(b, nir_slt(b, src[0], nir_imm_float(b, 0.0)), nir_imm_float(b, 0.0));
 512
 513    nir_intrinsic_instr *discard =
 514       nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
 515    discard->src[0] = nir_src_for_ssa(cmp);
 516    nir_builder_instr_insert(b, &discard->instr);
 517 }
 518
 519 static void
 520 ptn_tex(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src,
 521         struct prog_instruction *prog_inst)
 522 {
 523    nir_tex_instr *instr;
 524    nir_texop op;
 525    unsigned num_srcs;
 526
 527    switch (prog_inst->Opcode) {
 528    case OPCODE_TEX:
 529       op = nir_texop_tex;
 530       num_srcs = 1;
 531       break;
 532    case OPCODE_TXB:
 533       op = nir_texop_txb;
 534       num_srcs = 2;
 535       break;
 536    case OPCODE_TXD:
 537       op = nir_texop_txd;
 538       num_srcs = 3;
 539       break;
 540    case OPCODE_TXL:
 541       op = nir_texop_txl;
 542       num_srcs = 2;
 543       break;
 544    case OPCODE_TXP:
 545       op = nir_texop_tex;
 546       num_srcs = 2;
 547       break;
 548    default:
 549       fprintf(stderr, "unknown tex op %d\n", prog_inst->Opcode);
 550       abort();
 551    }
 552
 553    if (prog_inst->TexShadow)
 554       num_srcs++;
 555
 556    instr = nir_tex_instr_create(b->shader, num_srcs);
 557    instr->op = op;
 558    instr->dest_type = nir_type_float;
 559    instr->is_shadow = prog_inst->TexShadow;
 560    instr->texture_index = prog_inst->TexSrcUnit;
 561    instr->sampler_index = prog_inst->TexSrcUnit;
 562
 563    switch (prog_inst->TexSrcTarget) {
 564    case TEXTURE_1D_INDEX:
 565       instr->sampler_dim = GLSL_SAMPLER_DIM_1D;
 566       break;
 567    case TEXTURE_2D_INDEX:
 568       instr->sampler_dim = GLSL_SAMPLER_DIM_2D;
 569       break;
 570    case TEXTURE_3D_INDEX:
 571       instr->sampler_dim = GLSL_SAMPLER_DIM_3D;
 572       break;
 573    case TEXTURE_CUBE_INDEX:
 574       instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE;
 575       break;
 576    case TEXTURE_RECT_INDEX:
 577       instr->sampler_dim = GLSL_SAMPLER_DIM_RECT;
 578       break;
 579    default:
 580       fprintf(stderr, "Unknown texture target %d\n", prog_inst->TexSrcTarget);
 581       abort();
 582    }
 583
 584    switch (instr->sampler_dim) {
 585    case GLSL_SAMPLER_DIM_1D:
 586    case GLSL_SAMPLER_DIM_BUF:
 587       instr->coord_components = 1;
 588       break;
 589    case GLSL_SAMPLER_DIM_2D:
 590    case GLSL_SAMPLER_DIM_RECT:
 591    case GLSL_SAMPLER_DIM_EXTERNAL:
 592    case GLSL_SAMPLER_DIM_MS:
 593       instr->coord_components = 2;
 594       break;
 595    case GLSL_SAMPLER_DIM_3D:
 596    case GLSL_SAMPLER_DIM_CUBE:
 597       instr->coord_components = 3;
 598       break;
 599    case GLSL_SAMPLER_DIM_SUBPASS:
 600       unreachable("can't reach");
 601    }
 602
 603    unsigned src_number = 0;
 604
 605    instr->src[src_number].src =
 606       nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
 607                                   instr->coord_components, true));
 608    instr->src[src_number].src_type = nir_tex_src_coord;
 609    src_number++;
 610
 611    if (prog_inst->Opcode == OPCODE_TXP) {
 612       instr->src[src_number].src = nir_src_for_ssa(ptn_channel(b, src[0], W));
 613       instr->src[src_number].src_type = nir_tex_src_projector;
 614       src_number++;
 615    }
 616
 617    if (prog_inst->Opcode == OPCODE_TXB) {
 618       instr->src[src_number].src = nir_src_for_ssa(ptn_channel(b, src[0], W));
 619       instr->src[src_number].src_type = nir_tex_src_bias;
 620       src_number++;
 621    }
 622
 623    if (prog_inst->Opcode == OPCODE_TXL) {
 624       instr->src[src_number].src = nir_src_for_ssa(ptn_channel(b, src[0], W));
 625       instr->src[src_number].src_type = nir_tex_src_lod;
 626       src_number++;
 627    }
 628
 629    if (instr->is_shadow) {
 630       if (instr->coord_components < 3)
 631          instr->src[src_number].src = nir_src_for_ssa(ptn_channel(b, src[0], Z));
 632       else
 633          instr->src[src_number].src = nir_src_for_ssa(ptn_channel(b, src[0], W));
 634
 635       instr->src[src_number].src_type = nir_tex_src_comparitor;
 636       src_number++;
 637    }
 638
 639    assert(src_number == num_srcs);
 640
 641    nir_ssa_dest_init(&instr->instr, &instr->dest, 4, 32, NULL);
 642    nir_builder_instr_insert(b, &instr->instr);
 643
 644    /* Resolve the writemask on the texture op. */
 645    ptn_move_dest(b, dest, &instr->dest.ssa);
 646 }
 647
 648 static const nir_op op_trans[MAX_OPCODE] = {
 649    [OPCODE_NOP] = 0,
 650    [OPCODE_ABS] = nir_op_fabs,
 651    [OPCODE_ADD] = nir_op_fadd,
 652    [OPCODE_ARL] = 0,
 653    [OPCODE_CMP] = 0,
 654    [OPCODE_COS] = 0,
 655    [OPCODE_DDX] = nir_op_fddx,
 656    [OPCODE_DDY] = nir_op_fddy,
 657    [OPCODE_DP2] = 0,
 658    [OPCODE_DP3] = 0,
 659    [OPCODE_DP4] = 0,
 660    [OPCODE_DPH] = 0,
 661    [OPCODE_DST] = 0,
 662    [OPCODE_END] = 0,
 663    [OPCODE_EX2] = 0,
 664    [OPCODE_EXP] = 0,
 665    [OPCODE_FLR] = nir_op_ffloor,
 666    [OPCODE_FRC] = nir_op_ffract,
 667    [OPCODE_LG2] = 0,
 668    [OPCODE_LIT] = 0,
 669    [OPCODE_LOG] = 0,
 670    [OPCODE_LRP] = 0,
 671    [OPCODE_MAD] = 0,
 672    [OPCODE_MAX] = nir_op_fmax,
 673    [OPCODE_MIN] = nir_op_fmin,
 674    [OPCODE_MOV] = nir_op_fmov,
 675    [OPCODE_MUL] = nir_op_fmul,
 676    [OPCODE_POW] = 0,
 677    [OPCODE_RCP] = 0,
 678
 679    [OPCODE_RSQ] = 0,
 680    [OPCODE_SCS] = 0,
 681    [OPCODE_SGE] = 0,
 682    [OPCODE_SIN] = 0,
 683    [OPCODE_SLT] = 0,
 684    [OPCODE_SSG] = nir_op_fsign,
 685    [OPCODE_SUB] = nir_op_fsub,
 686    [OPCODE_SWZ] = 0,
 687    [OPCODE_TEX] = 0,
 688    [OPCODE_TRUNC] = nir_op_ftrunc,
 689    [OPCODE_TXB] = 0,
 690    [OPCODE_TXD] = 0,
 691    [OPCODE_TXL] = 0,
 692    [OPCODE_TXP] = 0,
 693    [OPCODE_XPD] = 0,
 694 };
 695
 696 static void
 697 ptn_emit_instruction(struct ptn_compile *c, struct prog_instruction *prog_inst)
 698 {
 699    nir_builder *b = &c->build;
 700    unsigned i;
 701    const unsigned op = prog_inst->Opcode;
 702
 703    if (op == OPCODE_END)
 704       return;
 705
 706    nir_ssa_def *src[3];
 707    for (i = 0; i < 3; i++) {
 708       src[i] = ptn_get_src(c, &prog_inst->SrcReg[i]);
 709    }
 710    nir_alu_dest dest = ptn_get_dest(c, &prog_inst->DstReg);
 711    if (c->error)
 712       return;
 713
 714    switch (op) {
 715    case OPCODE_RSQ:
 716       ptn_move_dest(b, dest,
 717                     nir_frsq(b, nir_fabs(b, ptn_channel(b, src[0], X))));
 718       break;
 719
 720    case OPCODE_RCP:
 721       ptn_move_dest(b, dest, nir_frcp(b, ptn_channel(b, src[0], X)));
 722       break;
 723
 724    case OPCODE_EX2:
 725       ptn_move_dest(b, dest, nir_fexp2(b, ptn_channel(b, src[0], X)));
 726       break;
 727
 728    case OPCODE_LG2:
 729       ptn_move_dest(b, dest, nir_flog2(b, ptn_channel(b, src[0], X)));
 730       break;
 731
 732    case OPCODE_POW:
 733       ptn_move_dest(b, dest, nir_fpow(b,
 734                                       ptn_channel(b, src[0], X),
 735                                       ptn_channel(b, src[1], X)));
 736       break;
 737
 738    case OPCODE_COS:
 739       ptn_move_dest(b, dest, nir_fcos(b, ptn_channel(b, src[0], X)));
 740       break;
 741
 742    case OPCODE_SIN:
 743       ptn_move_dest(b, dest, nir_fsin(b, ptn_channel(b, src[0], X)));
 744       break;
 745
 746    case OPCODE_ARL:
 747       ptn_arl(b, dest, src);
 748       break;
 749
 750    case OPCODE_EXP:
 751       ptn_exp(b, dest, src);
 752       break;
 753
 754    case OPCODE_LOG:
 755       ptn_log(b, dest, src);
 756       break;
 757
 758    case OPCODE_LRP:
 759       ptn_lrp(b, dest, src);
 760       break;
 761
 762    case OPCODE_MAD:
 763       ptn_move_dest(b, dest, nir_fadd(b, nir_fmul(b, src[0], src[1]), src[2]));
 764       break;
 765
 766    case OPCODE_DST:
 767       ptn_dst(b, dest, src);
 768       break;
 769
 770    case OPCODE_LIT:
 771       ptn_lit(b, dest, src);
 772       break;
 773
 774    case OPCODE_XPD:
 775       ptn_xpd(b, dest, src);
 776       break;
 777
 778    case OPCODE_DP2:
 779       ptn_dp2(b, dest, src);
 780       break;
 781
 782    case OPCODE_DP3:
 783       ptn_dp3(b, dest, src);
 784       break;
 785
 786    case OPCODE_DP4:
 787       ptn_dp4(b, dest, src);
 788       break;
 789
 790    case OPCODE_DPH:
 791       ptn_dph(b, dest, src);
 792       break;
 793
 794    case OPCODE_KIL:
 795       ptn_kil(b, src);
 796       break;
 797
 798    case OPCODE_CMP:
 799       ptn_cmp(b, dest, src);
 800       break;
 801
 802    case OPCODE_SCS:
 803       ptn_scs(b, dest, src);
 804       break;
 805
 806    case OPCODE_SLT:
 807       ptn_slt(b, dest, src);
 808       break;
 809
 810    case OPCODE_SGE:
 811       ptn_sge(b, dest, src);
 812       break;
 813
 814    case OPCODE_TEX:
 815    case OPCODE_TXB:
 816    case OPCODE_TXD:
 817    case OPCODE_TXL:
 818    case OPCODE_TXP:
 819       ptn_tex(b, dest, src, prog_inst);
 820       break;
 821
 822    case OPCODE_SWZ:
 823       /* Extended swizzles were already handled in ptn_get_src(). */
 824       ptn_alu(b, nir_op_fmov, dest, src);
 825       break;
 826
 827    case OPCODE_NOP:
 828       break;
 829
 830    default:
 831       if (op_trans[op] != 0) {
 832          ptn_alu(b, op_trans[op], dest, src);
 833       } else {
 834          fprintf(stderr, "unknown opcode: %s\n", _mesa_opcode_string(op));
 835          abort();
 836       }
 837       break;
 838    }
 839
 840    if (prog_inst->Saturate) {
 841       assert(prog_inst->Saturate);
 842       assert(!dest.dest.is_ssa);
 843       ptn_move_dest(b, dest, nir_fsat(b, ptn_src_for_dest(c, &dest)));
 844    }
 845 }
 846
 847 /**
 848  * Puts a NIR intrinsic to store of each PROGRAM_OUTPUT value to the output
 849  * variables at the end of the shader.
 850  *
 851  * We don't generate these incrementally as the PROGRAM_OUTPUT values are
 852  * written, because there's no output load intrinsic, which means we couldn't
 853  * handle writemasks.
 854  */
 855 static void
 856 ptn_add_output_stores(struct ptn_compile *c)
 857 {
 858    nir_builder *b = &c->build;
 859
 860    nir_foreach_variable(var, &b->shader->outputs) {
 861       nir_intrinsic_instr *store =
 862          nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_var);
 863       store->num_components = glsl_get_vector_elements(var->type);
 864       nir_intrinsic_set_write_mask(store, (1 << store->num_components) - 1);
 865       store->variables[0] =
 866          nir_deref_var_create(store, c->output_vars[var->data.location]);
 867
 868       if (c->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
 869           var->data.location == FRAG_RESULT_DEPTH) {
 870          /* result.depth has this strange convention of being the .z component of
 871           * a vec4 with undefined .xyw components.  We resolve it to a scalar, to
 872           * match GLSL's gl_FragDepth and the expectations of most backends.
 873           */
 874          nir_alu_src alu_src = { NIR_SRC_INIT };
 875          alu_src.src = nir_src_for_reg(c->output_regs[FRAG_RESULT_DEPTH]);
 876          alu_src.swizzle[0] = SWIZZLE_Z;
 877          store->src[0] = nir_src_for_ssa(nir_fmov_alu(b, alu_src, 1));
 878       } else {
 879          store->src[0].reg.reg = c->output_regs[var->data.location];
 880       }
 881       nir_builder_instr_insert(b, &store->instr);
 882    }
 883 }
 884
 885 static void
 886 setup_registers_and_variables(struct ptn_compile *c)
 887 {
 888    nir_builder *b = &c->build;
 889    struct nir_shader *shader = b->shader;
 890
 891    /* Create input variables. */
 892    const int num_inputs = util_last_bit64(c->prog->info.inputs_read);
 893    for (int i = 0; i < num_inputs; i++) {
 894       if (!(c->prog->info.inputs_read & BITFIELD64_BIT(i)))
 895          continue;
 896
 897       nir_variable *var =
 898          nir_variable_create(shader, nir_var_shader_in, glsl_vec4_type(),
 899                              ralloc_asprintf(shader, "in_%d", i));
 900       var->data.location = i;
 901       var->data.index = 0;
 902
 903       if (c->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
 904          if (i == VARYING_SLOT_POS) {
 905             var->data.origin_upper_left = c->prog->OriginUpperLeft;
 906             var->data.pixel_center_integer = c->prog->PixelCenterInteger;
 907          } else if (i == VARYING_SLOT_FOGC) {
 908             /* fogcoord is defined as <f, 0.0, 0.0, 1.0>.  Make the actual
 909              * input variable a float, and create a local containing the
 910              * full vec4 value.
 911              */
 912             var->type = glsl_float_type();
 913
 914             nir_intrinsic_instr *load_x =
 915                nir_intrinsic_instr_create(shader, nir_intrinsic_load_var);
 916             load_x->num_components = 1;
 917             load_x->variables[0] = nir_deref_var_create(load_x, var);
 918             nir_ssa_dest_init(&load_x->instr, &load_x->dest, 1, 32, NULL);
 919             nir_builder_instr_insert(b, &load_x->instr);
 920
 921             nir_ssa_def *f001 = nir_vec4(b, &load_x->dest.ssa, nir_imm_float(b, 0.0),
 922                                          nir_imm_float(b, 0.0), nir_imm_float(b, 1.0));
 923
 924             nir_variable *fullvar =
 925                nir_local_variable_create(b->impl, glsl_vec4_type(),
 926                                          "fogcoord_tmp");
 927             nir_intrinsic_instr *store =
 928                nir_intrinsic_instr_create(shader, nir_intrinsic_store_var);
 929             store->num_components = 4;
 930             nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
 931             store->variables[0] = nir_deref_var_create(store, fullvar);
 932             store->src[0] = nir_src_for_ssa(f001);
 933             nir_builder_instr_insert(b, &store->instr);
 934
 935             /* We inserted the real input into the list so the driver has real
 936              * inputs, but we set c->input_vars[i] to the temporary so we use
 937              * the splatted value.
 938              */
 939             c->input_vars[i] = fullvar;
 940             continue;
 941          }
 942       }
 943
 944       c->input_vars[i] = var;
 945    }
 946
 947    /* Create output registers and variables. */
 948    int max_outputs = util_last_bit(c->prog->OutputsWritten);
 949    c->output_regs = rzalloc_array(c, nir_register *, max_outputs);
 950
 951    for (int i = 0; i < max_outputs; i++) {
 952       if (!(c->prog->OutputsWritten & BITFIELD64_BIT(i)))
 953          continue;
 954
 955       /* Since we can't load from outputs in the IR, we make temporaries
 956        * for the outputs and emit stores to the real outputs at the end of
 957        * the shader.
 958        */
 959       nir_register *reg = nir_local_reg_create(b->impl);
 960       reg->num_components = 4;
 961
 962       nir_variable *var = rzalloc(shader, nir_variable);
 963       if (c->prog->Target == GL_FRAGMENT_PROGRAM_ARB && i == FRAG_RESULT_DEPTH)
 964          var->type = glsl_float_type();
 965       else
 966          var->type = glsl_vec4_type();
 967       var->data.mode = nir_var_shader_out;
 968       var->name = ralloc_asprintf(var, "out_%d", i);
 969
 970       var->data.location = i;
 971       var->data.index = 0;
 972
 973       c->output_regs[i] = reg;
 974
 975       exec_list_push_tail(&shader->outputs, &var->node);
 976       c->output_vars[i] = var;
 977    }
 978
 979    /* Create temporary registers. */
 980    c->temp_regs = rzalloc_array(c, nir_register *, c->prog->NumTemporaries);
 981
 982    nir_register *reg;
 983    for (unsigned i = 0; i < c->prog->NumTemporaries; i++) {
 984       reg = nir_local_reg_create(b->impl);
 985       if (!reg) {
 986          c->error = true;
 987          return;
 988       }
 989       reg->num_components = 4;
 990       c->temp_regs[i] = reg;
 991    }
 992
 993    /* Create the address register (for ARB_vertex_program). */
 994    reg = nir_local_reg_create(b->impl);
 995    if (!reg) {
 996       c->error = true;
 997       return;
 998    }
 999    reg->num_components = 1;
1000    c->addr_reg = reg;
1001 }
1002
1003 struct nir_shader *
1004 prog_to_nir(const struct gl_program *prog,
1005             const nir_shader_compiler_options *options)
1006 {
1007    struct ptn_compile *c;
1008    struct nir_shader *s;
1009    gl_shader_stage stage = _mesa_program_enum_to_shader_stage(prog->Target);
1010
1011    c = rzalloc(NULL, struct ptn_compile);
1012    if (!c)
1013       return NULL;
1014    c->prog = prog;
1015
1016    nir_builder_init_simple_shader(&c->build, NULL, stage, options);
1017
1018    /* Use the shader_info from gl_program rather than the one nir_builder
1019     * created for us. nir_sweep should clean up the other one for us.
1020     */
1021    c->build.shader->info = (shader_info *) &prog->info;
1022
1023    s = c->build.shader;
1024
1025    if (prog->Parameters->NumParameters > 0) {
1026       c->parameters = rzalloc(s, nir_variable);
1027       c->parameters->type =
1028          glsl_array_type(glsl_vec4_type(), prog->Parameters->NumParameters);
1029       c->parameters->name = "parameters";
1030       c->parameters->data.read_only = true;
1031       c->parameters->data.mode = nir_var_uniform;
1032       exec_list_push_tail(&s->uniforms, &c->parameters->node);
1033    }
1034
1035    setup_registers_and_variables(c);
1036    if (unlikely(c->error))
1037       goto fail;
1038
1039    for (unsigned int i = 0; i < prog->NumInstructions; i++) {
1040       ptn_emit_instruction(c, &prog->Instructions[i]);
1041
1042       if (unlikely(c->error))
1043          break;
1044    }
1045
1046    ptn_add_output_stores(c);
1047
1048    s->info->name = ralloc_asprintf(s, "ARB%d", prog->Id);
1049    s->info->num_textures = util_last_bit(prog->SamplersUsed);
1050    s->info->num_ubos = 0;
1051    s->info->num_abos = 0;
1052    s->info->num_ssbos = 0;
1053    s->info->num_images = 0;
1054    s->info->outputs_written = prog->OutputsWritten;
1055    s->info->system_values_read = prog->SystemValuesRead;
1056    s->info->uses_texture_gather = false;
1057    s->info->uses_clip_distance_out = false;
1058    s->info->separate_shader = false;
1059
1060 fail:
1061    if (c->error) {
1062       ralloc_free(s);
1063       s = NULL;
1064    }
1065    ralloc_free(c);
1066    return s;
1067 }