src/mesa/shader/slang/slang_emit.c

   1 /*
   2  * Mesa 3-D graphics library
   3  * Version:  7.1
   4  *
   5  * Copyright (C) 2005-2008  Brian Paul   All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file slang_emit.c
  27  * Emit program instructions (PI code) from IR trees.
  28  * \author Brian Paul
  29  */
  30
  31 /***
  32  *** NOTES
  33  ***
  34  *** To emit GPU instructions, we basically just do an in-order traversal
  35  *** of the IR tree.
  36  ***/
  37
  38
  39 #include "main/imports.h"
  40 #include "main/context.h"
  41 #include "main/macros.h"
  42 #include "shader/program.h"
  43 #include "shader/prog_instruction.h"
  44 #include "shader/prog_parameter.h"
  45 #include "shader/prog_print.h"
  46 #include "slang_builtin.h"
  47 #include "slang_emit.h"
  48 #include "slang_mem.h"
  49
  50
  51 #define PEEPHOLE_OPTIMIZATIONS 1
  52 #define ANNOTATE 0
  53
  54
  55 typedef struct
  56 {
  57    slang_info_log *log;
  58    slang_var_table *vt;
  59    struct gl_program *prog;
  60    struct gl_program **Subroutines;
  61    GLuint NumSubroutines;
  62
  63    /* code-gen options */
  64    GLboolean EmitHighLevelInstructions;
  65    GLboolean EmitCondCodes;
  66    GLboolean EmitComments;
  67    GLboolean EmitBeginEndSub; /* XXX TEMPORARY */
  68 } slang_emit_info;
  69
  70
  71
  72 static struct gl_program *
  73 new_subroutine(slang_emit_info *emitInfo, GLuint *id)
  74 {
  75    GET_CURRENT_CONTEXT(ctx);
  76    const GLuint n = emitInfo->NumSubroutines;
  77
  78    emitInfo->Subroutines = (struct gl_program **)
  79       _mesa_realloc(emitInfo->Subroutines,
  80                     n * sizeof(struct gl_program),
  81                     (n + 1) * sizeof(struct gl_program));
  82    emitInfo->Subroutines[n] = ctx->Driver.NewProgram(ctx, emitInfo->prog->Target, 0);
  83    emitInfo->Subroutines[n]->Parameters = emitInfo->prog->Parameters;
  84    emitInfo->NumSubroutines++;
  85    *id = n;
  86    return emitInfo->Subroutines[n];
  87 }
  88
  89
  90 /**
  91  * Convert a writemask to a swizzle.  Used for testing cond codes because
  92  * we only want to test the cond code component(s) that was set by the
  93  * previous instruction.
  94  */
  95 static GLuint
  96 writemask_to_swizzle(GLuint writemask)
  97 {
  98    if (writemask == WRITEMASK_X)
  99       return SWIZZLE_XXXX;
 100    if (writemask == WRITEMASK_Y)
 101       return SWIZZLE_YYYY;
 102    if (writemask == WRITEMASK_Z)
 103       return SWIZZLE_ZZZZ;
 104    if (writemask == WRITEMASK_W)
 105       return SWIZZLE_WWWW;
 106    return SWIZZLE_XYZW;  /* shouldn't be hit */
 107 }
 108
 109
 110 /**
 111  * Swizzle a swizzle.  That is, return swz2(swz1)
 112  */
 113 GLuint
 114 _slang_swizzle_swizzle(GLuint swz1, GLuint swz2)
 115 {
 116    GLuint i, swz, s[4];
 117    for (i = 0; i < 4; i++) {
 118       GLuint c = GET_SWZ(swz2, i);
 119       if (c <= SWIZZLE_W)
 120          s[i] = GET_SWZ(swz1, c);
 121       else
 122          s[i] = c;
 123    }
 124    swz = MAKE_SWIZZLE4(s[0], s[1], s[2], s[3]);
 125    return swz;
 126 }
 127
 128
 129 /**
 130  * Allocate storage for the given node (if it hasn't already been allocated).
 131  *
 132  * Typically this is temporary storage for an intermediate result (such as
 133  * for a multiply or add, etc).
 134  *
 135  * If n->Store does not exist it will be created and will be of the size
 136  * specified by defaultSize.
 137  */
 138 static GLboolean
 139 alloc_node_storage(slang_emit_info *emitInfo, slang_ir_node *n,
 140                    GLint defaultSize)
 141 {
 142    assert(!n->Var);
 143    if (!n->Store) {
 144       assert(defaultSize > 0);
 145       n->Store = _slang_new_ir_storage(PROGRAM_TEMPORARY, -1, defaultSize);
 146    }
 147
 148    /* now allocate actual register(s).  I.e. set n->Store->Index >= 0 */
 149    if (n->Store->Index < 0) {
 150       if (!_slang_alloc_temp(emitInfo->vt, n->Store)) {
 151          slang_info_log_error(emitInfo->log,
 152                               "Ran out of registers, too many temporaries");
 153          _slang_free(n->Store);
 154          n->Store = NULL;
 155          return GL_FALSE;
 156       }
 157    }
 158    return GL_TRUE;
 159 }
 160
 161
 162 /**
 163  * Free temporary storage, if n->Store is, in fact, temp storage.
 164  * Otherwise, no-op.
 165  */
 166 static void
 167 free_node_storage(slang_var_table *vt, slang_ir_node *n)
 168 {
 169    if (n->Store->File == PROGRAM_TEMPORARY &&
 170        n->Store->Index >= 0 &&
 171        n->Opcode != IR_SWIZZLE) {
 172       if (_slang_is_temp(vt, n->Store)) {
 173          _slang_free_temp(vt, n->Store);
 174          n->Store->Index = -1;
 175          n->Store = NULL; /* XXX this may not be needed */
 176       }
 177    }
 178 }
 179
 180
 181 /**
 182  * Helper function to allocate a short-term temporary.
 183  * Free it with _slang_free_temp().
 184  */
 185 static GLboolean
 186 alloc_local_temp(slang_emit_info *emitInfo, slang_ir_storage *temp, GLint size)
 187 {
 188    assert(size >= 1);
 189    assert(size <= 4);
 190    _mesa_bzero(temp, sizeof(*temp));
 191    temp->Size = size;
 192    temp->File = PROGRAM_TEMPORARY;
 193    temp->Index = -1;
 194    return _slang_alloc_temp(emitInfo->vt, temp);
 195 }
 196
 197
 198 /**
 199  * Remove any SWIZZLE_NIL terms from given swizzle mask.
 200  * For a swizzle like .z??? generate .zzzz (replicate single component).
 201  * Else, for .wx?? generate .wxzw (insert default component for the position).
 202  */
 203 static GLuint
 204 fix_swizzle(GLuint swizzle)
 205 {
 206    GLuint c0 = GET_SWZ(swizzle, 0),
 207       c1 = GET_SWZ(swizzle, 1),
 208       c2 = GET_SWZ(swizzle, 2),
 209       c3 = GET_SWZ(swizzle, 3);
 210    if (c1 == SWIZZLE_NIL && c2 == SWIZZLE_NIL && c3 == SWIZZLE_NIL) {
 211       /* smear first component across all positions */
 212       c1 = c2 = c3 = c0;
 213    }
 214    else {
 215       /* insert default swizzle components */
 216       if (c0 == SWIZZLE_NIL)
 217          c0 = SWIZZLE_X;
 218       if (c1 == SWIZZLE_NIL)
 219          c1 = SWIZZLE_Y;
 220       if (c2 == SWIZZLE_NIL)
 221          c2 = SWIZZLE_Z;
 222       if (c3 == SWIZZLE_NIL)
 223          c3 = SWIZZLE_W;
 224    }
 225    return MAKE_SWIZZLE4(c0, c1, c2, c3);
 226 }
 227
 228
 229
 230 /**
 231  * Convert IR storage to an instruction dst register.
 232  */
 233 static void
 234 storage_to_dst_reg(struct prog_dst_register *dst, const slang_ir_storage *st,
 235                    GLuint writemask)
 236 {
 237    const GLint size = st->Size;
 238    GLint index = st->Index;
 239    GLuint swizzle = st->Swizzle;
 240
 241    /* if this is storage relative to some parent storage, walk up the tree */
 242    while (st->Parent) {
 243       st = st->Parent;
 244       index += st->Index;
 245       swizzle = _slang_swizzle_swizzle(st->Swizzle, swizzle);
 246    }
 247
 248    assert(st->File != PROGRAM_UNDEFINED);
 249    dst->File = st->File;
 250
 251    assert(index >= 0);
 252    dst->Index = index;
 253
 254    assert(size >= 1);
 255    assert(size <= 4);
 256
 257    if (size == 1) {
 258       GLuint comp = GET_SWZ(swizzle, 0);
 259       assert(comp < 4);
 260       dst->WriteMask = WRITEMASK_X << comp;
 261    }
 262    else {
 263       dst->WriteMask = writemask;
 264    }
 265 }
 266
 267
 268 /**
 269  * Convert IR storage to an instruction src register.
 270  */
 271 static void
 272 storage_to_src_reg(struct prog_src_register *src, const slang_ir_storage *st)
 273 {
 274    const GLboolean relAddr = st->RelAddr;
 275    GLint index = st->Index;
 276    GLuint swizzle = st->Swizzle;
 277
 278    /* if this is storage relative to some parent storage, walk up the tree */
 279    while (st->Parent) {
 280       st = st->Parent;
 281       index += st->Index;
 282       swizzle = _slang_swizzle_swizzle(st->Swizzle, swizzle);
 283    }
 284
 285    assert(st->File >= 0);
 286 #if 1 /* XXX temporary */
 287    if (st->File == PROGRAM_UNDEFINED) {
 288       slang_ir_storage *st0 = (slang_ir_storage *) st;
 289       st0->File = PROGRAM_TEMPORARY;
 290    }
 291 #endif
 292    assert(st->File < PROGRAM_UNDEFINED);
 293    src->File = st->File;
 294
 295    assert(index >= 0);
 296    src->Index = index;
 297
 298    swizzle = fix_swizzle(swizzle);
 299    assert(GET_SWZ(swizzle, 0) <= SWIZZLE_W);
 300    assert(GET_SWZ(swizzle, 1) <= SWIZZLE_W);
 301    assert(GET_SWZ(swizzle, 2) <= SWIZZLE_W);
 302    assert(GET_SWZ(swizzle, 3) <= SWIZZLE_W);
 303    src->Swizzle = swizzle;
 304
 305    src->RelAddr = relAddr;
 306 }
 307
 308
 309 /*
 310  * Setup an instrucion src register to point to a scalar constant.
 311  */
 312 static void
 313 constant_to_src_reg(struct prog_src_register *src, GLfloat val,
 314                     slang_emit_info *emitInfo)
 315 {
 316    GLuint zeroSwizzle;
 317    GLint zeroReg;
 318    GLfloat value[4];
 319
 320    value[0] = val;
 321    zeroReg = _mesa_add_unnamed_constant(emitInfo->prog->Parameters,
 322                                         value, 1, &zeroSwizzle);
 323    assert(zeroReg >= 0);
 324
 325    src->File = PROGRAM_CONSTANT;
 326    src->Index = zeroReg;
 327    src->Swizzle = zeroSwizzle;
 328 }
 329
 330
 331 /**
 332  * Add new instruction at end of given program.
 333  * \param prog  the program to append instruction onto
 334  * \param opcode  opcode for the new instruction
 335  * \return pointer to the new instruction
 336  */
 337 static struct prog_instruction *
 338 new_instruction(slang_emit_info *emitInfo, gl_inst_opcode opcode)
 339 {
 340    struct gl_program *prog = emitInfo->prog;
 341    struct prog_instruction *inst;
 342
 343 #if 0
 344    /* print prev inst */
 345    if (prog->NumInstructions > 0) {
 346       _mesa_print_instruction(prog->Instructions + prog->NumInstructions - 1);
 347    }
 348 #endif
 349    prog->Instructions = _mesa_realloc_instructions(prog->Instructions,
 350                                                    prog->NumInstructions,
 351                                                    prog->NumInstructions + 1);
 352    inst = prog->Instructions + prog->NumInstructions;
 353    prog->NumInstructions++;
 354    _mesa_init_instructions(inst, 1);
 355    inst->Opcode = opcode;
 356    inst->BranchTarget = -1; /* invalid */
 357    /*
 358    printf("New inst %d: %p %s\n", prog->NumInstructions-1,(void*)inst,
 359           _mesa_opcode_string(inst->Opcode));
 360    */
 361    return inst;
 362 }
 363
 364
 365 /**
 366  * Return pointer to last instruction in program.
 367  */
 368 static struct prog_instruction *
 369 prev_instruction(slang_emit_info *emitInfo)
 370 {
 371    struct gl_program *prog = emitInfo->prog;
 372    if (prog->NumInstructions == 0)
 373       return NULL;
 374    else
 375       return prog->Instructions + prog->NumInstructions - 1;
 376 }
 377
 378
 379 static struct prog_instruction *
 380 emit(slang_emit_info *emitInfo, slang_ir_node *n);
 381
 382
 383 /**
 384  * Return an annotation string for given node's storage.
 385  */
 386 static char *
 387 storage_annotation(const slang_ir_node *n, const struct gl_program *prog)
 388 {
 389 #if ANNOTATE
 390    const slang_ir_storage *st = n->Store;
 391    static char s[100] = "";
 392
 393    if (!st)
 394       return _mesa_strdup("");
 395
 396    switch (st->File) {
 397    case PROGRAM_CONSTANT:
 398       if (st->Index >= 0) {
 399          const GLfloat *val = prog->Parameters->ParameterValues[st->Index];
 400          if (st->Swizzle == SWIZZLE_NOOP)
 401             sprintf(s, "{%g, %g, %g, %g}", val[0], val[1], val[2], val[3]);
 402          else {
 403             sprintf(s, "%g", val[GET_SWZ(st->Swizzle, 0)]);
 404          }
 405       }
 406       break;
 407    case PROGRAM_TEMPORARY:
 408       if (n->Var)
 409          sprintf(s, "%s", (char *) n->Var->a_name);
 410       else
 411          sprintf(s, "t[%d]", st->Index);
 412       break;
 413    case PROGRAM_STATE_VAR:
 414    case PROGRAM_UNIFORM:
 415       sprintf(s, "%s", prog->Parameters->Parameters[st->Index].Name);
 416       break;
 417    case PROGRAM_VARYING:
 418       sprintf(s, "%s", prog->Varying->Parameters[st->Index].Name);
 419       break;
 420    case PROGRAM_INPUT:
 421       sprintf(s, "input[%d]", st->Index);
 422       break;
 423    case PROGRAM_OUTPUT:
 424       sprintf(s, "output[%d]", st->Index);
 425       break;
 426    default:
 427       s[0] = 0;
 428    }
 429    return _mesa_strdup(s);
 430 #else
 431    return NULL;
 432 #endif
 433 }
 434
 435
 436 /**
 437  * Return an annotation string for an instruction.
 438  */
 439 static char *
 440 instruction_annotation(gl_inst_opcode opcode, char *dstAnnot,
 441                        char *srcAnnot0, char *srcAnnot1, char *srcAnnot2)
 442 {
 443 #if ANNOTATE
 444    const char *operator;
 445    char *s;
 446    int len = 50;
 447
 448    if (dstAnnot)
 449       len += strlen(dstAnnot);
 450    else
 451       dstAnnot = _mesa_strdup("");
 452
 453    if (srcAnnot0)
 454       len += strlen(srcAnnot0);
 455    else
 456       srcAnnot0 = _mesa_strdup("");
 457
 458    if (srcAnnot1)
 459       len += strlen(srcAnnot1);
 460    else
 461       srcAnnot1 = _mesa_strdup("");
 462
 463    if (srcAnnot2)
 464       len += strlen(srcAnnot2);
 465    else
 466       srcAnnot2 = _mesa_strdup("");
 467
 468    switch (opcode) {
 469    case OPCODE_ADD:
 470       operator = "+";
 471       break;
 472    case OPCODE_SUB:
 473       operator = "-";
 474       break;
 475    case OPCODE_MUL:
 476       operator = "*";
 477       break;
 478    case OPCODE_DP3:
 479       operator = "DP3";
 480       break;
 481    case OPCODE_DP4:
 482       operator = "DP4";
 483       break;
 484    case OPCODE_XPD:
 485       operator = "XPD";
 486       break;
 487    case OPCODE_RSQ:
 488       operator = "RSQ";
 489       break;
 490    case OPCODE_SGT:
 491       operator = ">";
 492       break;
 493    default:
 494       operator = ",";
 495    }
 496
 497    s = (char *) malloc(len);
 498    sprintf(s, "%s = %s %s %s %s", dstAnnot,
 499            srcAnnot0, operator, srcAnnot1, srcAnnot2);
 500    assert(_mesa_strlen(s) < len);
 501
 502    free(dstAnnot);
 503    free(srcAnnot0);
 504    free(srcAnnot1);
 505    free(srcAnnot2);
 506
 507    return s;
 508 #else
 509    return NULL;
 510 #endif
 511 }
 512
 513
 514 /**
 515  * Emit an instruction that's just a comment.
 516  */
 517 static struct prog_instruction *
 518 emit_comment(slang_emit_info *emitInfo, const char *s)
 519 {
 520    struct prog_instruction *inst = new_instruction(emitInfo, OPCODE_NOP);
 521    if (inst) {
 522       inst->Comment = _mesa_strdup(s);
 523    }
 524    return inst;
 525 }
 526
 527
 528 /**
 529  * Generate code for a simple arithmetic instruction.
 530  * Either 1, 2 or 3 operands.
 531  */
 532 static struct prog_instruction *
 533 emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
 534 {
 535    struct prog_instruction *inst;
 536    const slang_ir_info *info = _slang_ir_info(n->Opcode);
 537    char *srcAnnot[3], *dstAnnot;
 538    GLuint i;
 539    slang_ir_node *temps[3];
 540
 541    /* we'll save pointers to nodes/storage to free in temps[] until
 542     * the very end.
 543     */
 544    temps[0] = temps[1] = temps[2] = NULL;
 545
 546    assert(info);
 547    assert(info->InstOpcode != OPCODE_NOP);
 548
 549    srcAnnot[0] = srcAnnot[1] = srcAnnot[2] = dstAnnot = NULL;
 550
 551 #if PEEPHOLE_OPTIMIZATIONS
 552    /* Look for MAD opportunity */
 553    if (info->NumParams == 2 &&
 554        n->Opcode == IR_ADD && n->Children[0]->Opcode == IR_MUL) {
 555       /* found pattern IR_ADD(IR_MUL(A, B), C) */
 556       emit(emitInfo, n->Children[0]->Children[0]);  /* A */
 557       emit(emitInfo, n->Children[0]->Children[1]);  /* B */
 558       emit(emitInfo, n->Children[1]);  /* C */
 559       /* generate MAD instruction */
 560       inst = new_instruction(emitInfo, OPCODE_MAD);
 561       /* operands: A, B, C: */
 562       storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Children[0]->Store);
 563       storage_to_src_reg(&inst->SrcReg[1], n->Children[0]->Children[1]->Store);
 564       storage_to_src_reg(&inst->SrcReg[2], n->Children[1]->Store);
 565       temps[0] = n->Children[0]->Children[0];
 566       temps[1] = n->Children[0]->Children[1];
 567       temps[2] = n->Children[1];
 568    }
 569    else if (info->NumParams == 2 &&
 570             n->Opcode == IR_ADD && n->Children[1]->Opcode == IR_MUL) {
 571       /* found pattern IR_ADD(A, IR_MUL(B, C)) */
 572       emit(emitInfo, n->Children[0]);  /* A */
 573       emit(emitInfo, n->Children[1]->Children[0]);  /* B */
 574       emit(emitInfo, n->Children[1]->Children[1]);  /* C */
 575       /* generate MAD instruction */
 576       inst = new_instruction(emitInfo, OPCODE_MAD);
 577       /* operands: B, C, A */
 578       storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Children[0]->Store);
 579       storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Children[1]->Store);
 580       storage_to_src_reg(&inst->SrcReg[2], n->Children[0]->Store);
 581       temps[0] = n->Children[1]->Children[0];
 582       temps[1] = n->Children[1]->Children[1];
 583       temps[2] = n->Children[0];
 584    }
 585    else
 586 #endif
 587    {
 588       /* normal case */
 589
 590       /* gen code for children */
 591       for (i = 0; i < info->NumParams; i++) {
 592          emit(emitInfo, n->Children[i]);
 593          if (!n->Children[i] || !n->Children[i]->Store) {
 594             /* error recovery */
 595             return NULL;
 596          }
 597       }
 598
 599       /* gen this instruction and src registers */
 600       inst = new_instruction(emitInfo, info->InstOpcode);
 601       for (i = 0; i < info->NumParams; i++)
 602          storage_to_src_reg(&inst->SrcReg[i], n->Children[i]->Store);
 603
 604       /* annotation */
 605       for (i = 0; i < info->NumParams; i++)
 606          srcAnnot[i] = storage_annotation(n->Children[i], emitInfo->prog);
 607
 608       /* record (potential) temps to free */
 609       for (i = 0; i < info->NumParams; i++)
 610          temps[i] = n->Children[i];
 611    }
 612
 613    /* result storage */
 614    alloc_node_storage(emitInfo, n, -1);
 615    assert(n->Store->Index >= 0);
 616    if (n->Store->Size == 2)
 617       n->Writemask = WRITEMASK_XY;
 618    else if (n->Store->Size == 3)
 619       n->Writemask = WRITEMASK_XYZ;
 620    else if (n->Store->Size == 1)
 621       n->Writemask = WRITEMASK_X << GET_SWZ(n->Store->Swizzle, 0);
 622
 623
 624    storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 625
 626    dstAnnot = storage_annotation(n, emitInfo->prog);
 627
 628    inst->Comment = instruction_annotation(inst->Opcode, dstAnnot, srcAnnot[0],
 629                                           srcAnnot[1], srcAnnot[2]);
 630
 631    /* really free temps now */
 632    for (i = 0; i < 3; i++)
 633       if (temps[i])
 634          free_node_storage(emitInfo->vt, temps[i]);
 635
 636    /*_mesa_print_instruction(inst);*/
 637    return inst;
 638 }
 639
 640
 641 /**
 642  * Emit code for == and != operators.  These could normally be handled
 643  * by emit_arith() except we need to be able to handle structure comparisons.
 644  */
 645 static struct prog_instruction *
 646 emit_compare(slang_emit_info *emitInfo, slang_ir_node *n)
 647 {
 648    struct prog_instruction *inst;
 649    GLint size;
 650
 651    assert(n->Opcode == IR_EQUAL || n->Opcode == IR_NOTEQUAL);
 652
 653    /* gen code for children */
 654    emit(emitInfo, n->Children[0]);
 655    emit(emitInfo, n->Children[1]);
 656
 657    if (n->Children[0]->Store->Size != n->Children[1]->Store->Size) {
 658       slang_info_log_error(emitInfo->log, "invalid operands to == or !=");
 659       return NULL;
 660    }
 661
 662    /* final result is 1 bool */
 663    if (!alloc_node_storage(emitInfo, n, 1))
 664       return NULL;
 665
 666    size = n->Children[0]->Store->Size;
 667
 668    if (size == 1) {
 669       gl_inst_opcode opcode;
 670
 671       opcode = n->Opcode == IR_EQUAL ? OPCODE_SEQ : OPCODE_SNE;
 672       inst = new_instruction(emitInfo, opcode);
 673       storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
 674       storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Store);
 675       storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 676    }
 677    else if (size <= 4) {
 678       GLuint swizzle;
 679       gl_inst_opcode dotOp;
 680       slang_ir_storage tempStore;
 681
 682       if (!alloc_local_temp(emitInfo, &tempStore, 4)) {
 683          return NULL;
 684          /* out of temps */
 685       }
 686
 687       if (size == 4) {
 688          dotOp = OPCODE_DP4;
 689          swizzle = SWIZZLE_XYZW;
 690       }
 691       else if (size == 3) {
 692          dotOp = OPCODE_DP3;
 693          swizzle = SWIZZLE_XYZW;
 694       }
 695       else {
 696          assert(size == 2);
 697          dotOp = OPCODE_DP3;
 698          swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y);
 699       }
 700
 701       /* Compute inequality (temp = (A != B)) */
 702       inst = new_instruction(emitInfo, OPCODE_SNE);
 703       storage_to_dst_reg(&inst->DstReg, &tempStore, n->Writemask);
 704       storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
 705       storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Store);
 706       inst->Comment = _mesa_strdup("Compare values");
 707
 708       /* Compute val = DOT(temp, temp)  (reduction) */
 709       inst = new_instruction(emitInfo, dotOp);
 710       storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 711       storage_to_src_reg(&inst->SrcReg[0], &tempStore);
 712       storage_to_src_reg(&inst->SrcReg[1], &tempStore);
 713       inst->SrcReg[0].Swizzle = inst->SrcReg[1].Swizzle = swizzle; /*override*/
 714       inst->Comment = _mesa_strdup("Reduce vec to bool");
 715
 716       _slang_free_temp(emitInfo->vt, &tempStore); /* free temp */
 717
 718       if (n->Opcode == IR_EQUAL) {
 719          /* compute val = !val.x  with SEQ val, val, 0; */
 720          inst = new_instruction(emitInfo, OPCODE_SEQ);
 721          storage_to_src_reg(&inst->SrcReg[0], n->Store);
 722          constant_to_src_reg(&inst->SrcReg[1], 0.0, emitInfo);
 723          storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 724          inst->Comment = _mesa_strdup("Invert true/false");
 725       }
 726    }
 727    else {
 728       /* size > 4, struct or array compare.
 729        * XXX this won't work reliably for structs with padding!!
 730        */
 731       GLint i, num = (n->Children[0]->Store->Size + 3) / 4;
 732       slang_ir_storage accTemp, sneTemp;
 733
 734       if (!alloc_local_temp(emitInfo, &accTemp, 4))
 735          return NULL;
 736
 737       if (!alloc_local_temp(emitInfo, &sneTemp, 4))
 738          return NULL;
 739
 740       for (i = 0; i < num; i++) {
 741          /* SNE sneTemp, left[i], right[i] */
 742          inst = new_instruction(emitInfo, OPCODE_SNE);
 743          storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
 744          storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Store);
 745          inst->SrcReg[0].Index += i;
 746          inst->SrcReg[1].Index += i;
 747          if (i == 0) {
 748             storage_to_dst_reg(&inst->DstReg, &accTemp, WRITEMASK_XYZW);
 749             inst->Comment = _mesa_strdup("Begin struct/array comparison");
 750          }
 751          else {
 752             storage_to_dst_reg(&inst->DstReg, &sneTemp, WRITEMASK_XYZW);
 753
 754             /* ADD accTemp, accTemp, sneTemp; # like logical-OR */
 755             inst = new_instruction(emitInfo, OPCODE_ADD);
 756             storage_to_dst_reg(&inst->DstReg, &accTemp, WRITEMASK_XYZW);
 757             storage_to_src_reg(&inst->SrcReg[0], &accTemp);
 758             storage_to_src_reg(&inst->SrcReg[1], &sneTemp);
 759          }
 760       }
 761
 762       /* compute accTemp.x || accTemp.y || accTemp.z || accTemp.w with DOT4 */
 763       inst = new_instruction(emitInfo, OPCODE_DP4);
 764       storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 765       storage_to_src_reg(&inst->SrcReg[0], &accTemp);
 766       storage_to_src_reg(&inst->SrcReg[1], &accTemp);
 767       inst->Comment = _mesa_strdup("End struct/array comparison");
 768
 769       if (n->Opcode == IR_EQUAL) {
 770          /* compute tmp.x = !tmp.x  via tmp.x = (tmp.x == 0) */
 771          inst = new_instruction(emitInfo, OPCODE_SEQ);
 772          storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 773          storage_to_src_reg(&inst->SrcReg[0], n->Store);
 774          constant_to_src_reg(&inst->SrcReg[1], 0.0, emitInfo);
 775          inst->Comment = _mesa_strdup("Invert true/false");
 776       }
 777
 778       _slang_free_temp(emitInfo->vt, &accTemp);
 779       _slang_free_temp(emitInfo->vt, &sneTemp);
 780    }
 781
 782    /* free temps */
 783    free_node_storage(emitInfo->vt, n->Children[0]);
 784    free_node_storage(emitInfo->vt, n->Children[1]);
 785
 786    return inst;
 787 }
 788
 789
 790
 791 /**
 792  * Generate code for an IR_CLAMP instruction.
 793  */
 794 static struct prog_instruction *
 795 emit_clamp(slang_emit_info *emitInfo, slang_ir_node *n)
 796 {
 797    struct prog_instruction *inst;
 798    slang_ir_node tmpNode;
 799
 800    assert(n->Opcode == IR_CLAMP);
 801    /* ch[0] = value
 802     * ch[1] = min limit
 803     * ch[2] = max limit
 804     */
 805
 806    inst = emit(emitInfo, n->Children[0]);
 807
 808    /* If lower limit == 0.0 and upper limit == 1.0,
 809     *    set prev instruction's SaturateMode field to SATURATE_ZERO_ONE.
 810     * Else,
 811     *    emit OPCODE_MIN, OPCODE_MAX sequence.
 812     */
 813 #if 0
 814    /* XXX this isn't quite finished yet */
 815    if (n->Children[1]->Opcode == IR_FLOAT &&
 816        n->Children[1]->Value[0] == 0.0 &&
 817        n->Children[1]->Value[1] == 0.0 &&
 818        n->Children[1]->Value[2] == 0.0 &&
 819        n->Children[1]->Value[3] == 0.0 &&
 820        n->Children[2]->Opcode == IR_FLOAT &&
 821        n->Children[2]->Value[0] == 1.0 &&
 822        n->Children[2]->Value[1] == 1.0 &&
 823        n->Children[2]->Value[2] == 1.0 &&
 824        n->Children[2]->Value[3] == 1.0) {
 825       if (!inst) {
 826          inst = prev_instruction(prog);
 827       }
 828       if (inst && inst->Opcode != OPCODE_NOP) {
 829          /* and prev instruction's DstReg matches n->Children[0]->Store */
 830          inst->SaturateMode = SATURATE_ZERO_ONE;
 831          n->Store = n->Children[0]->Store;
 832          return inst;
 833       }
 834    }
 835 #endif
 836
 837    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
 838       return NULL;
 839
 840    emit(emitInfo, n->Children[1]);
 841    emit(emitInfo, n->Children[2]);
 842
 843    /* Some GPUs don't allow reading from output registers.  So if the
 844     * dest for this clamp() is an output reg, we can't use that reg for
 845     * the intermediate result.  Use a temp register instead.
 846     */
 847    _mesa_bzero(&tmpNode, sizeof(tmpNode));
 848    alloc_node_storage(emitInfo, &tmpNode, n->Store->Size);
 849
 850    /* tmp = max(ch[0], ch[1]) */
 851    inst = new_instruction(emitInfo, OPCODE_MAX);
 852    storage_to_dst_reg(&inst->DstReg, tmpNode.Store, n->Writemask);
 853    storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
 854    storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Store);
 855
 856    /* n->dest = min(tmp, ch[2]) */
 857    inst = new_instruction(emitInfo, OPCODE_MIN);
 858    storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 859    storage_to_src_reg(&inst->SrcReg[0], tmpNode.Store);
 860    storage_to_src_reg(&inst->SrcReg[1], n->Children[2]->Store);
 861
 862    free_node_storage(emitInfo->vt, &tmpNode);
 863
 864    return inst;
 865 }
 866
 867
 868 static struct prog_instruction *
 869 emit_negation(slang_emit_info *emitInfo, slang_ir_node *n)
 870 {
 871    /* Implement as MOV dst, -src; */
 872    /* XXX we could look at the previous instruction and in some circumstances
 873     * modify it to accomplish the negation.
 874     */
 875    struct prog_instruction *inst;
 876
 877    emit(emitInfo, n->Children[0]);
 878
 879    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
 880       return NULL;
 881
 882    inst = new_instruction(emitInfo, OPCODE_MOV);
 883    storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
 884    storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
 885    inst->SrcReg[0].NegateBase = NEGATE_XYZW;
 886    return inst;
 887 }
 888
 889
 890 static struct prog_instruction *
 891 emit_label(slang_emit_info *emitInfo, const slang_ir_node *n)
 892 {
 893    assert(n->Label);
 894 #if 0
 895    /* XXX this fails in loop tail code - investigate someday */
 896    assert(_slang_label_get_location(n->Label) < 0);
 897    _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
 898                              emitInfo->prog);
 899 #else
 900    if (_slang_label_get_location(n->Label) < 0)
 901       _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
 902                                 emitInfo->prog);
 903 #endif
 904    return NULL;
 905 }
 906
 907
 908 /**
 909  * Emit code for a function call.
 910  * Note that for each time a function is called, we emit the function's
 911  * body code again because the set of available registers may be different.
 912  */
 913 static struct prog_instruction *
 914 emit_fcall(slang_emit_info *emitInfo, slang_ir_node *n)
 915 {
 916    struct gl_program *progSave;
 917    struct prog_instruction *inst;
 918    GLuint subroutineId;
 919
 920    assert(n->Opcode == IR_CALL);
 921    assert(n->Label);
 922
 923    /* save/push cur program */
 924    progSave = emitInfo->prog;
 925    emitInfo->prog = new_subroutine(emitInfo, &subroutineId);
 926
 927    _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
 928                              emitInfo->prog);
 929
 930    if (emitInfo->EmitBeginEndSub) {
 931       /* BGNSUB isn't a real instruction.
 932        * We require a label (i.e. "foobar:") though, if we're going to
 933        * print the program in the NV format.  The BNGSUB instruction is
 934        * really just a NOP to attach the label to.
 935        */
 936       inst = new_instruction(emitInfo, OPCODE_BGNSUB);
 937       inst->Comment = _mesa_strdup(n->Label->Name);
 938    }
 939
 940    /* body of function: */
 941    emit(emitInfo, n->Children[0]);
 942    n->Store = n->Children[0]->Store;
 943
 944    /* add RET instruction now, if needed */
 945    inst = prev_instruction(emitInfo);
 946    if (inst && inst->Opcode != OPCODE_RET) {
 947       inst = new_instruction(emitInfo, OPCODE_RET);
 948    }
 949
 950    if (emitInfo->EmitBeginEndSub) {
 951       inst = new_instruction(emitInfo, OPCODE_ENDSUB);
 952       inst->Comment = _mesa_strdup(n->Label->Name);
 953    }
 954
 955    /* pop/restore cur program */
 956    emitInfo->prog = progSave;
 957
 958    /* emit the function call */
 959    inst = new_instruction(emitInfo, OPCODE_CAL);
 960    /* The branch target is just the subroutine number (changed later) */
 961    inst->BranchTarget = subroutineId;
 962    inst->Comment = _mesa_strdup(n->Label->Name);
 963    assert(inst->BranchTarget >= 0);
 964
 965    return inst;
 966 }
 967
 968
 969 /**
 970  * Emit code for a 'return' statement.
 971  */
 972 static struct prog_instruction *
 973 emit_return(slang_emit_info *emitInfo, slang_ir_node *n)
 974 {
 975    struct prog_instruction *inst;
 976    assert(n);
 977    assert(n->Opcode == IR_RETURN);
 978    assert(n->Label);
 979    inst = new_instruction(emitInfo, OPCODE_RET);
 980    inst->DstReg.CondMask = COND_TR;  /* always return */
 981    return inst;
 982 }
 983
 984
 985 static struct prog_instruction *
 986 emit_kill(slang_emit_info *emitInfo)
 987 {
 988    struct gl_fragment_program *fp;
 989    struct prog_instruction *inst;
 990    /* NV-KILL - discard fragment depending on condition code.
 991     * Note that ARB-KILL depends on sign of vector operand.
 992     */
 993    inst = new_instruction(emitInfo, OPCODE_KIL_NV);
 994    inst->DstReg.CondMask = COND_TR;  /* always kill */
 995
 996    assert(emitInfo->prog->Target == GL_FRAGMENT_PROGRAM_ARB);
 997    fp = (struct gl_fragment_program *) emitInfo->prog;
 998    fp->UsesKill = GL_TRUE;
 999
1000    return inst;
1001 }
1002
1003
1004 static struct prog_instruction *
1005 emit_tex(slang_emit_info *emitInfo, slang_ir_node *n)
1006 {
1007    struct prog_instruction *inst;
1008
1009    (void) emit(emitInfo, n->Children[1]);
1010
1011    if (n->Opcode == IR_TEX) {
1012       inst = new_instruction(emitInfo, OPCODE_TEX);
1013    }
1014    else if (n->Opcode == IR_TEXB) {
1015       inst = new_instruction(emitInfo, OPCODE_TXB);
1016    }
1017    else {
1018       assert(n->Opcode == IR_TEXP);
1019       inst = new_instruction(emitInfo, OPCODE_TXP);
1020    }
1021
1022    if (!alloc_node_storage(emitInfo, n, 4))
1023       return NULL;
1024
1025    storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
1026
1027    /* Child[1] is the coord */
1028    assert(n->Children[1]->Store->Index >= 0);
1029    storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Store);
1030
1031    /* Child[0] is the sampler (a uniform which'll indicate the texture unit) */
1032    assert(n->Children[0]->Store);
1033    /* Store->Index is the sampler index */
1034    assert(n->Children[0]->Store->Index >= 0);
1035    /* Store->Size is the texture target */
1036    assert(n->Children[0]->Store->Size >= TEXTURE_1D_INDEX);
1037    assert(n->Children[0]->Store->Size <= TEXTURE_RECT_INDEX);
1038
1039    inst->TexSrcTarget = n->Children[0]->Store->Size;
1040 #if 0
1041    inst->TexSrcUnit = 27; /* Dummy value; the TexSrcUnit will be computed at
1042                            * link time, using the sampler uniform's value.
1043                            */
1044    inst->Sampler = n->Children[0]->Store->Index; /* i.e. uniform's index */
1045 #else
1046    inst->TexSrcUnit = n->Children[0]->Store->Index; /* i.e. uniform's index */
1047 #endif
1048    return inst;
1049 }
1050
1051
1052 /**
1053  * Assignment/copy
1054  */
1055 static struct prog_instruction *
1056 emit_copy(slang_emit_info *emitInfo, slang_ir_node *n)
1057 {
1058    struct prog_instruction *inst;
1059
1060    assert(n->Opcode == IR_COPY);
1061
1062    /* lhs */
1063    emit(emitInfo, n->Children[0]);
1064    if (!n->Children[0]->Store || n->Children[0]->Store->Index < 0) {
1065       /* an error should have been already recorded */
1066       return NULL;
1067    }
1068
1069    /* rhs */
1070    assert(n->Children[1]);
1071    inst = emit(emitInfo, n->Children[1]);
1072
1073    if (!n->Children[1]->Store || n->Children[1]->Store->Index < 0) {
1074       if (!emitInfo->log->text) {
1075          slang_info_log_error(emitInfo->log, "invalid assignment");
1076       }
1077       return NULL;
1078    }
1079
1080    assert(n->Children[1]->Store->Index >= 0);
1081
1082    /*assert(n->Children[0]->Store->Size == n->Children[1]->Store->Size);*/
1083
1084    n->Store = n->Children[0]->Store;
1085
1086 #if PEEPHOLE_OPTIMIZATIONS
1087    if (inst &&
1088        _slang_is_temp(emitInfo->vt, n->Children[1]->Store) &&
1089        (inst->DstReg.File == n->Children[1]->Store->File) &&
1090        (inst->DstReg.Index == n->Children[1]->Store->Index)) {
1091       /* Peephole optimization:
1092        * The Right-Hand-Side has its results in a temporary place.
1093        * Modify the RHS (and the prev instruction) to store its results
1094        * in the destination specified by n->Children[0].
1095        * Then, this MOVE is a no-op.
1096        */
1097       if (n->Children[1]->Opcode != IR_SWIZZLE)
1098          _slang_free_temp(emitInfo->vt, n->Children[1]->Store);
1099       *n->Children[1]->Store = *n->Children[0]->Store;
1100
1101       /* fixup the previous instruction (which stored the RHS result) */
1102       assert(n->Children[0]->Store->Index >= 0);
1103
1104       /* use tighter writemask when possible */
1105       if (n->Writemask == WRITEMASK_XYZW)
1106          n->Writemask = inst->DstReg.WriteMask;
1107
1108       storage_to_dst_reg(&inst->DstReg, n->Children[0]->Store, n->Writemask);
1109       return inst;
1110    }
1111    else
1112 #endif
1113    {
1114       if (n->Children[0]->Store->Size > 4) {
1115          /* move matrix/struct etc (block of registers) */
1116          slang_ir_storage dstStore = *n->Children[0]->Store;
1117          slang_ir_storage srcStore = *n->Children[1]->Store;
1118          GLint size = srcStore.Size;
1119          ASSERT(n->Children[0]->Writemask == WRITEMASK_XYZW);
1120          ASSERT(n->Children[1]->Store->Swizzle == SWIZZLE_NOOP);
1121          dstStore.Size = 4;
1122          srcStore.Size = 4;
1123          while (size >= 4) {
1124             inst = new_instruction(emitInfo, OPCODE_MOV);
1125             inst->Comment = _mesa_strdup("IR_COPY block");
1126             storage_to_dst_reg(&inst->DstReg, &dstStore, n->Writemask);
1127             storage_to_src_reg(&inst->SrcReg[0], &srcStore);
1128             srcStore.Index++;
1129             dstStore.Index++;
1130             size -= 4;
1131          }
1132       }
1133       else {
1134          /* single register move */
1135          char *srcAnnot, *dstAnnot;
1136          inst = new_instruction(emitInfo, OPCODE_MOV);
1137          assert(n->Children[0]->Store->Index >= 0);
1138          storage_to_dst_reg(&inst->DstReg, n->Children[0]->Store, n->Writemask);
1139          storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Store);
1140          dstAnnot = storage_annotation(n->Children[0], emitInfo->prog);
1141          srcAnnot = storage_annotation(n->Children[1], emitInfo->prog);
1142          inst->Comment = instruction_annotation(inst->Opcode, dstAnnot,
1143                                                 srcAnnot, NULL, NULL);
1144       }
1145       free_node_storage(emitInfo->vt, n->Children[1]);
1146       return inst;
1147    }
1148 }
1149
1150
1151 /**
1152  * An IR_COND node wraps a boolean expression which is used by an
1153  * IF or WHILE test.  This is where we'll set condition codes, if needed.
1154  */
1155 static struct prog_instruction *
1156 emit_cond(slang_emit_info *emitInfo, slang_ir_node *n)
1157 {
1158    struct prog_instruction *inst;
1159
1160    assert(n->Opcode == IR_COND);
1161
1162    if (!n->Children[0])
1163       return NULL;
1164
1165    /* emit code for the expression */
1166    inst = emit(emitInfo, n->Children[0]);
1167
1168    if (!n->Children[0]->Store) {
1169       /* error recovery */
1170       return NULL;
1171    }
1172
1173    assert(n->Children[0]->Store);
1174    /*assert(n->Children[0]->Store->Size == 1);*/
1175
1176    if (emitInfo->EmitCondCodes) {
1177       if (inst &&
1178           n->Children[0]->Store &&
1179           inst->DstReg.File == n->Children[0]->Store->File &&
1180           inst->DstReg.Index == n->Children[0]->Store->Index) {
1181          /* The previous instruction wrote to the register who's value
1182           * we're testing.  Just fix that instruction so that the
1183           * condition codes are computed.
1184           */
1185          inst->CondUpdate = GL_TRUE;
1186          n->Store = n->Children[0]->Store;
1187          return inst;
1188       }
1189       else {
1190          /* This'll happen for things like "if (i) ..." where no code
1191           * is normally generated for the expression "i".
1192           * Generate a move instruction just to set condition codes.
1193           */
1194          if (!alloc_node_storage(emitInfo, n, 1))
1195             return NULL;
1196          inst = new_instruction(emitInfo, OPCODE_MOV);
1197          inst->CondUpdate = GL_TRUE;
1198          storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
1199          storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
1200          _slang_free_temp(emitInfo->vt, n->Store);
1201          inst->Comment = _mesa_strdup("COND expr");
1202          return inst;
1203       }
1204    }
1205    else {
1206       /* No-op: the boolean result of the expression is in a regular reg */
1207       n->Store = n->Children[0]->Store;
1208       return inst;
1209    }
1210 }
1211
1212
1213 /**
1214  * Logical-NOT
1215  */
1216 static struct prog_instruction *
1217 emit_not(slang_emit_info *emitInfo, slang_ir_node *n)
1218 {
1219    static const struct {
1220       gl_inst_opcode op, opNot;
1221    } operators[] = {
1222       { OPCODE_SLT, OPCODE_SGE },
1223       { OPCODE_SLE, OPCODE_SGT },
1224       { OPCODE_SGT, OPCODE_SLE },
1225       { OPCODE_SGE, OPCODE_SLT },
1226       { OPCODE_SEQ, OPCODE_SNE },
1227       { OPCODE_SNE, OPCODE_SEQ },
1228       { 0, 0 }
1229    };
1230    struct prog_instruction *inst;
1231    GLuint i;
1232
1233    /* child expr */
1234    inst = emit(emitInfo, n->Children[0]);
1235
1236 #if PEEPHOLE_OPTIMIZATIONS
1237    if (inst) {
1238       /* if the prev instruction was a comparison instruction, invert it */
1239       for (i = 0; operators[i].op; i++) {
1240          if (inst->Opcode == operators[i].op) {
1241             inst->Opcode = operators[i].opNot;
1242             n->Store = n->Children[0]->Store;
1243             return inst;
1244          }
1245       }
1246    }
1247 #endif
1248
1249    /* else, invert using SEQ (v = v == 0) */
1250    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
1251       return NULL;
1252
1253    inst = new_instruction(emitInfo, OPCODE_SEQ);
1254    storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
1255    storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
1256    constant_to_src_reg(&inst->SrcReg[1], 0.0, emitInfo);
1257    free_node_storage(emitInfo->vt, n->Children[0]);
1258
1259    inst->Comment = _mesa_strdup("NOT");
1260    return inst;
1261 }
1262
1263
1264 static struct prog_instruction *
1265 emit_if(slang_emit_info *emitInfo, slang_ir_node *n)
1266 {
1267    struct gl_program *prog = emitInfo->prog;
1268    GLuint ifInstLoc, elseInstLoc = 0;
1269    GLuint condWritemask = 0;
1270
1271    /* emit condition expression code */
1272    {
1273       struct prog_instruction *inst;
1274       inst = emit(emitInfo, n->Children[0]);
1275       if (emitInfo->EmitCondCodes) {
1276          if (!inst) {
1277             /* error recovery */
1278             return NULL;
1279          }
1280          condWritemask = inst->DstReg.WriteMask;
1281       }
1282    }
1283
1284    if (!n->Children[0]->Store)
1285       return NULL;
1286
1287 #if 0
1288    assert(n->Children[0]->Store->Size == 1); /* a bool! */
1289 #endif
1290
1291    ifInstLoc = prog->NumInstructions;
1292    if (emitInfo->EmitHighLevelInstructions) {
1293       struct prog_instruction *ifInst = new_instruction(emitInfo, OPCODE_IF);
1294       if (emitInfo->EmitCondCodes) {
1295          ifInst->DstReg.CondMask = COND_NE;  /* if cond is non-zero */
1296          /* only test the cond code (1 of 4) that was updated by the
1297           * previous instruction.
1298           */
1299          ifInst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1300       }
1301       else {
1302          /* test reg.x */
1303          storage_to_src_reg(&ifInst->SrcReg[0], n->Children[0]->Store);
1304       }
1305    }
1306    else {
1307       /* conditional jump to else, or endif */
1308       struct prog_instruction *ifInst = new_instruction(emitInfo, OPCODE_BRA);
1309       ifInst->DstReg.CondMask = COND_EQ;  /* BRA if cond is zero */
1310       ifInst->Comment = _mesa_strdup("if zero");
1311       ifInst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1312    }
1313
1314    /* if body */
1315    emit(emitInfo, n->Children[1]);
1316
1317    if (n->Children[2]) {
1318       /* have else body */
1319       elseInstLoc = prog->NumInstructions;
1320       if (emitInfo->EmitHighLevelInstructions) {
1321          (void) new_instruction(emitInfo, OPCODE_ELSE);
1322       }
1323       else {
1324          /* jump to endif instruction */
1325          struct prog_instruction *inst;
1326          inst = new_instruction(emitInfo, OPCODE_BRA);
1327          inst->Comment = _mesa_strdup("else");
1328          inst->DstReg.CondMask = COND_TR;  /* always branch */
1329       }
1330       prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
1331       emit(emitInfo, n->Children[2]);
1332    }
1333    else {
1334       /* no else body */
1335       prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
1336    }
1337
1338    if (emitInfo->EmitHighLevelInstructions) {
1339       (void) new_instruction(emitInfo, OPCODE_ENDIF);
1340    }
1341
1342    if (n->Children[2]) {
1343       prog->Instructions[elseInstLoc].BranchTarget = prog->NumInstructions;
1344    }
1345    return NULL;
1346 }
1347
1348
1349 static struct prog_instruction *
1350 emit_loop(slang_emit_info *emitInfo, slang_ir_node *n)
1351 {
1352    struct gl_program *prog = emitInfo->prog;
1353    struct prog_instruction *endInst;
1354    GLuint beginInstLoc, tailInstLoc, endInstLoc;
1355    slang_ir_node *ir;
1356
1357    /* emit OPCODE_BGNLOOP */
1358    beginInstLoc = prog->NumInstructions;
1359    if (emitInfo->EmitHighLevelInstructions) {
1360       (void) new_instruction(emitInfo, OPCODE_BGNLOOP);
1361    }
1362
1363    /* body */
1364    emit(emitInfo, n->Children[0]);
1365
1366    /* tail */
1367    tailInstLoc = prog->NumInstructions;
1368    if (n->Children[1]) {
1369       if (emitInfo->EmitComments)
1370          emit_comment(emitInfo, "Loop tail code:");
1371       emit(emitInfo, n->Children[1]);
1372    }
1373
1374    endInstLoc = prog->NumInstructions;
1375    if (emitInfo->EmitHighLevelInstructions) {
1376       /* emit OPCODE_ENDLOOP */
1377       endInst = new_instruction(emitInfo, OPCODE_ENDLOOP);
1378    }
1379    else {
1380       /* emit unconditional BRA-nch */
1381       endInst = new_instruction(emitInfo, OPCODE_BRA);
1382       endInst->DstReg.CondMask = COND_TR;  /* always true */
1383    }
1384    /* ENDLOOP's BranchTarget points to the BGNLOOP inst */
1385    endInst->BranchTarget = beginInstLoc;
1386
1387    if (emitInfo->EmitHighLevelInstructions) {
1388       /* BGNLOOP's BranchTarget points to the ENDLOOP inst */
1389       prog->Instructions[beginInstLoc].BranchTarget = prog->NumInstructions -1;
1390    }
1391
1392    /* Done emitting loop code.  Now walk over the loop's linked list of
1393     * BREAK and CONT nodes, filling in their BranchTarget fields (which
1394     * will point to the ENDLOOP+1 or BGNLOOP instructions, respectively).
1395     */
1396    for (ir = n->List; ir; ir = ir->List) {
1397       struct prog_instruction *inst = prog->Instructions + ir->InstLocation;
1398       assert(inst->BranchTarget < 0);
1399       if (ir->Opcode == IR_BREAK ||
1400           ir->Opcode == IR_BREAK_IF_TRUE) {
1401          assert(inst->Opcode == OPCODE_BRK ||
1402                 inst->Opcode == OPCODE_BRA);
1403          /* go to instruction after end of loop */
1404          inst->BranchTarget = endInstLoc + 1;
1405       }
1406       else {
1407          assert(ir->Opcode == IR_CONT ||
1408                 ir->Opcode == IR_CONT_IF_TRUE);
1409          assert(inst->Opcode == OPCODE_CONT ||
1410                 inst->Opcode == OPCODE_BRA);
1411          /* go to instruction at tail of loop */
1412          inst->BranchTarget = endInstLoc;
1413       }
1414    }
1415    return NULL;
1416 }
1417
1418
1419 /**
1420  * Unconditional "continue" or "break" statement.
1421  * Either OPCODE_CONT, OPCODE_BRK or OPCODE_BRA will be emitted.
1422  */
1423 static struct prog_instruction *
1424 emit_cont_break(slang_emit_info *emitInfo, slang_ir_node *n)
1425 {
1426    gl_inst_opcode opcode;
1427    struct prog_instruction *inst;
1428
1429    if (n->Opcode == IR_CONT) {
1430       /* we need to execute the loop's tail code before doing CONT */
1431       assert(n->Parent);
1432       assert(n->Parent->Opcode == IR_LOOP);
1433       if (n->Parent->Children[1]) {
1434          /* emit tail code */
1435          if (emitInfo->EmitComments) {
1436             emit_comment(emitInfo, "continue - tail code:");
1437          }
1438          emit(emitInfo, n->Parent->Children[1]);
1439       }
1440    }
1441
1442    /* opcode selection */
1443    if (emitInfo->EmitHighLevelInstructions) {
1444       opcode = (n->Opcode == IR_CONT) ? OPCODE_CONT : OPCODE_BRK;
1445    }
1446    else {
1447       opcode = OPCODE_BRA;
1448    }
1449    n->InstLocation = emitInfo->prog->NumInstructions;
1450    inst = new_instruction(emitInfo, opcode);
1451    inst->DstReg.CondMask = COND_TR;  /* always true */
1452    return inst;
1453 }
1454
1455
1456 /**
1457  * Conditional "continue" or "break" statement.
1458  * Either OPCODE_CONT, OPCODE_BRK or OPCODE_BRA will be emitted.
1459  */
1460 static struct prog_instruction *
1461 emit_cont_break_if_true(slang_emit_info *emitInfo, slang_ir_node *n)
1462 {
1463    struct prog_instruction *inst;
1464
1465    assert(n->Opcode == IR_CONT_IF_TRUE ||
1466           n->Opcode == IR_BREAK_IF_TRUE);
1467
1468    /* evaluate condition expr, setting cond codes */
1469    inst = emit(emitInfo, n->Children[0]);
1470    if (emitInfo->EmitCondCodes) {
1471       assert(inst);
1472       inst->CondUpdate = GL_TRUE;
1473    }
1474
1475    n->InstLocation = emitInfo->prog->NumInstructions;
1476
1477    /* opcode selection */
1478    if (emitInfo->EmitHighLevelInstructions) {
1479       const gl_inst_opcode opcode
1480          = (n->Opcode == IR_CONT_IF_TRUE) ? OPCODE_CONT : OPCODE_BRK;
1481       if (emitInfo->EmitCondCodes) {
1482          /* Get the writemask from the previous instruction which set
1483           * the condcodes.  Use that writemask as the CondSwizzle.
1484           */
1485          const GLuint condWritemask = inst->DstReg.WriteMask;
1486          inst = new_instruction(emitInfo, opcode);
1487          inst->DstReg.CondMask = COND_NE;
1488          inst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1489          return inst;
1490       }
1491       else {
1492          /* IF reg
1493           *    BRK/CONT;
1494           * ENDIF
1495           */
1496          GLint ifInstLoc;
1497          ifInstLoc = emitInfo->prog->NumInstructions;
1498          inst = new_instruction(emitInfo, OPCODE_IF);
1499          storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Store);
1500          n->InstLocation = emitInfo->prog->NumInstructions;
1501
1502          inst = new_instruction(emitInfo, opcode);
1503          inst = new_instruction(emitInfo, OPCODE_ENDIF);
1504
1505          emitInfo->prog->Instructions[ifInstLoc].BranchTarget
1506             = emitInfo->prog->NumInstructions;
1507          return inst;
1508       }
1509    }
1510    else {
1511       const GLuint condWritemask = inst->DstReg.WriteMask;
1512       assert(emitInfo->EmitCondCodes);
1513       inst = new_instruction(emitInfo, OPCODE_BRA);
1514       inst->DstReg.CondMask = COND_NE;
1515       inst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1516       return inst;
1517    }
1518 }
1519
1520
1521 static struct prog_instruction *
1522 emit_swizzle(slang_emit_info *emitInfo, slang_ir_node *n)
1523 {
1524    struct prog_instruction *inst;
1525
1526    inst = emit(emitInfo, n->Children[0]);
1527
1528    /* setup storage info, if needed */
1529    if (!n->Store->Parent)
1530       n->Store->Parent = n->Children[0]->Store;
1531
1532    assert(n->Store->Parent);
1533
1534    return inst;
1535 }
1536
1537
1538 /**
1539  * Dereference array element.  Just resolve storage for the array
1540  * element represented by this node.
1541  */
1542 static struct prog_instruction *
1543 emit_array_element(slang_emit_info *emitInfo, slang_ir_node *n)
1544 {
1545    slang_ir_storage *root;
1546
1547    assert(n->Opcode == IR_ELEMENT);
1548    assert(n->Store);
1549    assert(n->Store->File == PROGRAM_UNDEFINED);
1550    assert(n->Store->Parent);
1551    assert(n->Store->Size > 0);
1552
1553    root = n->Store;
1554    while (root->Parent)
1555       root = root->Parent;
1556
1557    if (root->File == PROGRAM_STATE_VAR) {
1558       GLint index = _slang_alloc_statevar(n, emitInfo->prog->Parameters);
1559       assert(n->Store->Index == index);
1560       return NULL;
1561    }
1562
1563    /* do codegen for array */
1564    emit(emitInfo, n->Children[0]);
1565
1566    if (n->Children[1]->Opcode == IR_FLOAT) {
1567       /* Constant array index.
1568        * Set Store's index to be the offset of the array element in
1569        * the register file.
1570        */
1571       const GLint element = (GLint) n->Children[1]->Value[0];
1572       const GLint sz = (n->Store->Size + 3) / 4; /* size in slots/registers */
1573
1574       n->Store->Index = sz * element;
1575       assert(n->Store->Parent);
1576    }
1577    else {
1578       /* Variable array index */
1579       struct prog_instruction *inst;
1580
1581       /* do codegen for array index expression */
1582       emit(emitInfo, n->Children[1]);
1583
1584       inst = new_instruction(emitInfo, OPCODE_ARL);
1585
1586       storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
1587       storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Store);
1588
1589       inst->DstReg.File = PROGRAM_ADDRESS;
1590       inst->DstReg.Index = 0; /* always address register [0] */
1591       inst->Comment = _mesa_strdup("ARL ADDR");
1592
1593       n->Store->RelAddr = GL_TRUE;
1594    }
1595
1596    /* if array element size is one, make sure we only access X */
1597    if (n->Store->Size == 1)
1598       n->Store->Swizzle = SWIZZLE_XXXX;
1599
1600    return NULL; /* no instruction */
1601 }
1602
1603
1604 /**
1605  * Resolve storage for accessing a structure field.
1606  */
1607 static struct prog_instruction *
1608 emit_struct_field(slang_emit_info *emitInfo, slang_ir_node *n)
1609 {
1610    slang_ir_storage *root = n->Store;
1611
1612    assert(n->Opcode == IR_FIELD);
1613
1614    while (root->Parent)
1615       root = root->Parent;
1616
1617    /* If this is the field of a state var, allocate constant/uniform
1618     * storage for it now if we haven't already.
1619     * Note that we allocate storage (uniform/constant slots) for state
1620     * variables here rather than at declaration time so we only allocate
1621     * space for the ones that we actually use!
1622     */
1623    if (root->File == PROGRAM_STATE_VAR) {
1624       root->Index = _slang_alloc_statevar(n, emitInfo->prog->Parameters);
1625       if (root->Index < 0) {
1626          slang_info_log_error(emitInfo->log, "Error parsing state variable");
1627          return NULL;
1628       }
1629    }
1630    else {
1631       /* do codegen for struct */
1632       emit(emitInfo, n->Children[0]);
1633    }
1634
1635    return NULL; /* no instruction */
1636 }
1637
1638
1639 /**
1640  * Emit code for a variable declaration.
1641  * This usually doesn't result in any code generation, but just
1642  * memory allocation.
1643  */
1644 static struct prog_instruction *
1645 emit_var_decl(slang_emit_info *emitInfo, slang_ir_node *n)
1646 {
1647    struct prog_instruction *inst;
1648
1649    assert(n->Store);
1650    assert(n->Store->File != PROGRAM_UNDEFINED);
1651    assert(n->Store->Size > 0);
1652    /*assert(n->Store->Index < 0);*/
1653
1654    if (!n->Var || n->Var->isTemp) {
1655       /* a nameless/temporary variable, will be freed after first use */
1656       /*NEW*/
1657       if (n->Store->Index < 0 && !_slang_alloc_temp(emitInfo->vt, n->Store)) {
1658          slang_info_log_error(emitInfo->log,
1659                               "Ran out of registers, too many temporaries");
1660          return NULL;
1661       }
1662    }
1663    else {
1664       /* a regular variable */
1665       _slang_add_variable(emitInfo->vt, n->Var);
1666       if (!_slang_alloc_var(emitInfo->vt, n->Store)) {
1667          slang_info_log_error(emitInfo->log,
1668                               "Ran out of registers, too many variables");
1669          return NULL;
1670       }
1671       /*
1672         printf("IR_VAR_DECL %s %d store %p\n",
1673         (char*) n->Var->a_name, n->Store->Index, (void*) n->Store);
1674       */
1675       assert(n->Var->aux == n->Store);
1676    }
1677    if (emitInfo->EmitComments) {
1678       /* emit NOP with comment describing the variable's storage location */
1679       char s[1000];
1680       sprintf(s, "TEMP[%d]%s = variable %s (size %d)",
1681               n->Store->Index,
1682               _mesa_swizzle_string(n->Store->Swizzle, 0, GL_FALSE),
1683               (n->Var ? (char *) n->Var->a_name : "anonymous"),
1684               n->Store->Size);
1685       inst = emit_comment(emitInfo, s);
1686       return inst;
1687    }
1688    return NULL;
1689 }
1690
1691
1692 /**
1693  * Emit code for a reference to a variable.
1694  * Actually, no code is generated but we may do some memory alloation.
1695  * In particular, state vars (uniforms) are allocated on an as-needed basis.
1696  */
1697 static struct prog_instruction *
1698 emit_var_ref(slang_emit_info *emitInfo, slang_ir_node *n)
1699 {
1700    assert(n->Store);
1701    assert(n->Store->File != PROGRAM_UNDEFINED);
1702
1703    if (n->Store->File == PROGRAM_STATE_VAR && n->Store->Index < 0) {
1704       n->Store->Index = _slang_alloc_statevar(n, emitInfo->prog->Parameters);
1705    }
1706
1707    if (n->Store->Index < 0) {
1708       /* probably ran out of registers */
1709       return NULL;
1710    }
1711    assert(n->Store->Size > 0);
1712
1713    return NULL;
1714 }
1715
1716
1717 static struct prog_instruction *
1718 emit(slang_emit_info *emitInfo, slang_ir_node *n)
1719 {
1720    struct prog_instruction *inst;
1721    if (!n)
1722       return NULL;
1723
1724    if (emitInfo->log->error_flag) {
1725       return NULL;
1726    }
1727
1728    switch (n->Opcode) {
1729    case IR_SEQ:
1730       /* sequence of two sub-trees */
1731       assert(n->Children[0]);
1732       assert(n->Children[1]);
1733       emit(emitInfo, n->Children[0]);
1734       if (emitInfo->log->error_flag)
1735          return NULL;
1736       inst = emit(emitInfo, n->Children[1]);
1737 #if 0
1738       assert(!n->Store);
1739 #endif
1740       n->Store = n->Children[1]->Store;
1741       return inst;
1742
1743    case IR_SCOPE:
1744       /* new variable scope */
1745       _slang_push_var_table(emitInfo->vt);
1746       inst = emit(emitInfo, n->Children[0]);
1747       _slang_pop_var_table(emitInfo->vt);
1748       return inst;
1749
1750    case IR_VAR_DECL:
1751       /* Variable declaration - allocate a register for it */
1752       inst = emit_var_decl(emitInfo, n);
1753       return inst;
1754
1755    case IR_VAR:
1756       /* Reference to a variable
1757        * Storage should have already been resolved/allocated.
1758        */
1759       return emit_var_ref(emitInfo, n);
1760
1761    case IR_ELEMENT:
1762       return emit_array_element(emitInfo, n);
1763    case IR_FIELD:
1764       return emit_struct_field(emitInfo, n);
1765    case IR_SWIZZLE:
1766       return emit_swizzle(emitInfo, n);
1767
1768    /* Simple arithmetic */
1769    /* unary */
1770    case IR_MOVE:
1771    case IR_RSQ:
1772    case IR_RCP:
1773    case IR_FLOOR:
1774    case IR_FRAC:
1775    case IR_F_TO_I:
1776    case IR_I_TO_F:
1777    case IR_ABS:
1778    case IR_SIN:
1779    case IR_COS:
1780    case IR_DDX:
1781    case IR_DDY:
1782    case IR_EXP:
1783    case IR_EXP2:
1784    case IR_LOG2:
1785    case IR_NOISE1:
1786    case IR_NOISE2:
1787    case IR_NOISE3:
1788    case IR_NOISE4:
1789    /* binary */
1790    case IR_ADD:
1791    case IR_SUB:
1792    case IR_MUL:
1793    case IR_DOT4:
1794    case IR_DOT3:
1795    case IR_CROSS:
1796    case IR_MIN:
1797    case IR_MAX:
1798    case IR_SEQUAL:
1799    case IR_SNEQUAL:
1800    case IR_SGE:
1801    case IR_SGT:
1802    case IR_SLE:
1803    case IR_SLT:
1804    case IR_POW:
1805    /* trinary operators */
1806    case IR_LRP:
1807       return emit_arith(emitInfo, n);
1808
1809    case IR_EQUAL:
1810    case IR_NOTEQUAL:
1811       return emit_compare(emitInfo, n);
1812
1813    case IR_CLAMP:
1814       return emit_clamp(emitInfo, n);
1815    case IR_TEX:
1816    case IR_TEXB:
1817    case IR_TEXP:
1818       return emit_tex(emitInfo, n);
1819    case IR_NEG:
1820       return emit_negation(emitInfo, n);
1821    case IR_FLOAT:
1822       /* find storage location for this float constant */
1823       n->Store->Index = _mesa_add_unnamed_constant(emitInfo->prog->Parameters,
1824                                                    n->Value,
1825                                                    n->Store->Size,
1826                                                    &n->Store->Swizzle);
1827       if (n->Store->Index < 0) {
1828          slang_info_log_error(emitInfo->log, "Ran out of space for constants");
1829          return NULL;
1830       }
1831       return NULL;
1832
1833    case IR_COPY:
1834       return emit_copy(emitInfo, n);
1835
1836    case IR_COND:
1837       return emit_cond(emitInfo, n);
1838
1839    case IR_NOT:
1840       return emit_not(emitInfo, n);
1841
1842    case IR_LABEL:
1843       return emit_label(emitInfo, n);
1844
1845    case IR_KILL:
1846       return emit_kill(emitInfo);
1847
1848    case IR_CALL:
1849       /* new variable scope for subroutines/function calls */
1850       _slang_push_var_table(emitInfo->vt);
1851       inst = emit_fcall(emitInfo, n);
1852       _slang_pop_var_table(emitInfo->vt);
1853       return inst;
1854
1855    case IR_IF:
1856       return emit_if(emitInfo, n);
1857
1858    case IR_LOOP:
1859       return emit_loop(emitInfo, n);
1860    case IR_BREAK_IF_TRUE:
1861    case IR_CONT_IF_TRUE:
1862       return emit_cont_break_if_true(emitInfo, n);
1863    case IR_BREAK:
1864       /* fall-through */
1865    case IR_CONT:
1866       return emit_cont_break(emitInfo, n);
1867
1868    case IR_BEGIN_SUB:
1869       return new_instruction(emitInfo, OPCODE_BGNSUB);
1870    case IR_END_SUB:
1871       return new_instruction(emitInfo, OPCODE_ENDSUB);
1872    case IR_RETURN:
1873       return emit_return(emitInfo, n);
1874
1875    case IR_NOP:
1876       return NULL;
1877
1878    default:
1879       _mesa_problem(NULL, "Unexpected IR opcode in emit()\n");
1880    }
1881    return NULL;
1882 }
1883
1884
1885 /**
1886  * After code generation, any subroutines will be in separate program
1887  * objects.  This function appends all the subroutines onto the main
1888  * program and resolves the linking of all the branch/call instructions.
1889  * XXX this logic should really be part of the linking process...
1890  */
1891 static void
1892 _slang_resolve_subroutines(slang_emit_info *emitInfo)
1893 {
1894    GET_CURRENT_CONTEXT(ctx);
1895    struct gl_program *mainP = emitInfo->prog;
1896    GLuint *subroutineLoc, i, total;
1897
1898    subroutineLoc
1899       = (GLuint *) _mesa_malloc(emitInfo->NumSubroutines * sizeof(GLuint));
1900
1901    /* total number of instructions */
1902    total = mainP->NumInstructions;
1903    for (i = 0; i < emitInfo->NumSubroutines; i++) {
1904       subroutineLoc[i] = total;
1905       total += emitInfo->Subroutines[i]->NumInstructions;
1906    }
1907
1908    /* adjust BrancTargets within the functions */
1909    for (i = 0; i < emitInfo->NumSubroutines; i++) {
1910       struct gl_program *sub = emitInfo->Subroutines[i];
1911       GLuint j;
1912       for (j = 0; j < sub->NumInstructions; j++) {
1913          struct prog_instruction *inst = sub->Instructions + j;
1914          if (inst->Opcode != OPCODE_CAL && inst->BranchTarget >= 0) {
1915             inst->BranchTarget += subroutineLoc[i];
1916          }
1917       }
1918    }
1919
1920    /* append subroutines' instructions after main's instructions */
1921    mainP->Instructions = _mesa_realloc_instructions(mainP->Instructions,
1922                                                     mainP->NumInstructions,
1923                                                     total);
1924    mainP->NumInstructions = total;
1925    for (i = 0; i < emitInfo->NumSubroutines; i++) {
1926       struct gl_program *sub = emitInfo->Subroutines[i];
1927       _mesa_copy_instructions(mainP->Instructions + subroutineLoc[i],
1928                               sub->Instructions,
1929                               sub->NumInstructions);
1930       /* delete subroutine code */
1931       sub->Parameters = NULL; /* prevent double-free */
1932       _mesa_reference_program(ctx, &emitInfo->Subroutines[i], NULL);
1933    }
1934
1935    /* free subroutine list */
1936    if (emitInfo->Subroutines) {
1937       _mesa_free(emitInfo->Subroutines);
1938       emitInfo->Subroutines = NULL;
1939    }
1940    emitInfo->NumSubroutines = 0;
1941
1942    /* Examine CAL instructions.
1943     * At this point, the BranchTarget field of the CAL instruction is
1944     * the number/id of the subroutine to call (an index into the
1945     * emitInfo->Subroutines list).
1946     * Translate that into an actual instruction location now.
1947     */
1948    for (i = 0; i < mainP->NumInstructions; i++) {
1949       struct prog_instruction *inst = mainP->Instructions + i;
1950       if (inst->Opcode == OPCODE_CAL) {
1951          const GLuint f = inst->BranchTarget;
1952          inst->BranchTarget = subroutineLoc[f];
1953       }
1954    }
1955
1956    _mesa_free(subroutineLoc);
1957 }
1958
1959
1960
1961
1962 GLboolean
1963 _slang_emit_code(slang_ir_node *n, slang_var_table *vt,
1964                  struct gl_program *prog, GLboolean withEnd,
1965                  slang_info_log *log)
1966 {
1967    GET_CURRENT_CONTEXT(ctx);
1968    GLboolean success;
1969    slang_emit_info emitInfo;
1970
1971    emitInfo.log = log;
1972    emitInfo.vt = vt;
1973    emitInfo.prog = prog;
1974    emitInfo.Subroutines = NULL;
1975    emitInfo.NumSubroutines = 0;
1976
1977    emitInfo.EmitHighLevelInstructions = ctx->Shader.EmitHighLevelInstructions;
1978    emitInfo.EmitCondCodes = ctx->Shader.EmitCondCodes;
1979    emitInfo.EmitComments = ctx->Shader.EmitComments;
1980    emitInfo.EmitBeginEndSub = GL_TRUE;
1981
1982    if (!emitInfo.EmitCondCodes) {
1983       emitInfo.EmitHighLevelInstructions = GL_TRUE;
1984    }
1985
1986    (void) emit(&emitInfo, n);
1987
1988    /* finish up by adding the END opcode to program */
1989    if (withEnd) {
1990       struct prog_instruction *inst;
1991       inst = new_instruction(&emitInfo, OPCODE_END);
1992    }
1993
1994    _slang_resolve_subroutines(&emitInfo);
1995
1996    success = GL_TRUE;
1997
1998 #if 0
1999    printf("*********** End emit code (%u inst):\n", prog->NumInstructions);
2000    _mesa_print_program(prog);
2001    _mesa_print_program_parameters(ctx,prog);
2002 #endif
2003
2004    return success;
2005 }