2 * Mesa 3-D graphics library
5 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * Emit program instructions (PI code) from IR trees.
35 #include "prog_instruction.h"
36 #include "prog_parameter.h"
37 #include "prog_print.h"
38 #include "slang_emit.h"
39 #include "slang_error.h"
42 #define PEEPHOLE_OPTIMIZATIONS 1
47 * Assembly and IR info
51 slang_ir_opcode IrOpcode
;
53 gl_inst_opcode InstOpcode
;
54 GLuint ResultSize
, NumParams
;
59 static slang_ir_info IrInfo
[] = {
61 { IR_ADD
, "IR_ADD", OPCODE_ADD
, 4, 2 },
62 { IR_SUB
, "IR_SUB", OPCODE_SUB
, 4, 2 },
63 { IR_MUL
, "IR_MUL", OPCODE_MUL
, 4, 2 },
64 { IR_DIV
, "IR_DIV", OPCODE_NOP
, 0, 2 }, /* XXX broke */
65 { IR_DOT4
, "IR_DOT_4", OPCODE_DP4
, 1, 2 },
66 { IR_DOT3
, "IR_DOT_3", OPCODE_DP3
, 1, 2 },
67 { IR_CROSS
, "IR_CROSS", OPCODE_XPD
, 3, 2 },
68 { IR_LRP
, "IR_LRP", OPCODE_LRP
, 4, 3 },
69 { IR_MIN
, "IR_MIN", OPCODE_MIN
, 4, 2 },
70 { IR_MAX
, "IR_MAX", OPCODE_MAX
, 4, 2 },
71 { IR_CLAMP
, "IR_CLAMP", OPCODE_NOP
, 4, 3 }, /* special case: emit_clamp() */
72 { IR_SEQUAL
, "IR_SEQUAL", OPCODE_SEQ
, 4, 2 },
73 { IR_SNEQUAL
, "IR_SNEQUAL", OPCODE_SNE
, 4, 2 },
74 { IR_SGE
, "IR_SGE", OPCODE_SGE
, 4, 2 },
75 { IR_SGT
, "IR_SGT", OPCODE_SGT
, 4, 2 },
76 { IR_POW
, "IR_POW", OPCODE_POW
, 1, 2 },
78 { IR_I_TO_F
, "IR_I_TO_F", OPCODE_NOP
, 1, 1 },
79 { IR_F_TO_I
, "IR_F_TO_I", OPCODE_INT
, 4, 1 }, /* 4 floats to 4 ints */
80 { IR_EXP
, "IR_EXP", OPCODE_EXP
, 1, 1 },
81 { IR_EXP2
, "IR_EXP2", OPCODE_EX2
, 1, 1 },
82 { IR_LOG2
, "IR_LOG2", OPCODE_LG2
, 1, 1 },
83 { IR_RSQ
, "IR_RSQ", OPCODE_RSQ
, 1, 1 },
84 { IR_RCP
, "IR_RCP", OPCODE_RCP
, 1, 1 },
85 { IR_FLOOR
, "IR_FLOOR", OPCODE_FLR
, 4, 1 },
86 { IR_FRAC
, "IR_FRAC", OPCODE_FRC
, 4, 1 },
87 { IR_ABS
, "IR_ABS", OPCODE_ABS
, 4, 1 },
88 { IR_NEG
, "IR_NEG", OPCODE_NOP
, 4, 1 }, /* special case: emit_negation() */
89 { IR_DDX
, "IR_DDX", OPCODE_DDX
, 4, 1 },
90 { IR_DDX
, "IR_DDY", OPCODE_DDX
, 4, 1 },
91 { IR_SIN
, "IR_SIN", OPCODE_SIN
, 1, 1 },
92 { IR_COS
, "IR_COS", OPCODE_COS
, 1, 1 },
93 { IR_NOISE1
, "IR_NOISE1", OPCODE_NOISE1
, 1, 1 },
94 { IR_NOISE2
, "IR_NOISE2", OPCODE_NOISE2
, 1, 1 },
95 { IR_NOISE3
, "IR_NOISE3", OPCODE_NOISE3
, 1, 1 },
96 { IR_NOISE4
, "IR_NOISE4", OPCODE_NOISE4
, 1, 1 },
99 { IR_SEQ
, "IR_SEQ", OPCODE_NOP
, 0, 0 },
100 { IR_SCOPE
, "IR_SCOPE", OPCODE_NOP
, 0, 0 },
101 { IR_LABEL
, "IR_LABEL", OPCODE_NOP
, 0, 0 },
102 { IR_JUMP
, "IR_JUMP", OPCODE_NOP
, 0, 0 },
103 { IR_CJUMP0
, "IR_CJUMP0", OPCODE_NOP
, 0, 0 },
104 { IR_CJUMP1
, "IR_CJUMP1", OPCODE_NOP
, 0, 0 },
105 { IR_IF
, "IR_IF", OPCODE_NOP
, 0, 0 },
106 { IR_ELSE
, "IR_ELSE", OPCODE_NOP
, 0, 0 },
107 { IR_ENDIF
, "IR_ENDIF", OPCODE_NOP
, 0, 0 },
108 { IR_KILL
, "IR_KILL", OPCODE_NOP
, 0, 0 },
109 { IR_COND
, "IR_COND", OPCODE_NOP
, 0, 0 },
110 { IR_CALL
, "IR_CALL", OPCODE_NOP
, 0, 0 },
111 { IR_MOVE
, "IR_MOVE", OPCODE_NOP
, 0, 1 },
112 { IR_NOT
, "IR_NOT", OPCODE_NOP
, 1, 1 },
113 { IR_VAR
, "IR_VAR", OPCODE_NOP
, 0, 0 },
114 { IR_VAR_DECL
, "IR_VAR_DECL", OPCODE_NOP
, 0, 0 },
115 { IR_TEX
, "IR_TEX", OPCODE_TEX
, 4, 1 },
116 { IR_TEXB
, "IR_TEXB", OPCODE_TXB
, 4, 1 },
117 { IR_TEXP
, "IR_TEXP", OPCODE_TXP
, 4, 1 },
118 { IR_FLOAT
, "IR_FLOAT", OPCODE_NOP
, 0, 0 },
119 { IR_FIELD
, "IR_FIELD", OPCODE_NOP
, 0, 0 },
120 { IR_ELEMENT
, "IR_ELEMENT", OPCODE_NOP
, 0, 0 },
121 { IR_SWIZZLE
, "IR_SWIZZLE", OPCODE_NOP
, 0, 0 },
122 { IR_NOP
, NULL
, OPCODE_NOP
, 0, 0 }
126 static slang_ir_info
*
127 slang_find_ir_info(slang_ir_opcode opcode
)
130 for (i
= 0; IrInfo
[i
].IrName
; i
++) {
131 if (IrInfo
[i
].IrOpcode
== opcode
) {
139 slang_ir_name(slang_ir_opcode opcode
)
141 return slang_find_ir_info(opcode
)->IrName
;
146 * Swizzle a swizzle. That is, return swz2(swz1)
149 swizzle_swizzle(GLuint swz1
, GLuint swz2
)
152 for (i
= 0; i
< 4; i
++) {
153 GLuint c
= GET_SWZ(swz2
, i
);
154 s
[i
] = GET_SWZ(swz1
, c
);
156 swz
= MAKE_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
162 _slang_new_ir_storage(enum register_file file
, GLint index
, GLint size
)
164 slang_ir_storage
*st
;
165 st
= (slang_ir_storage
*) _mesa_calloc(sizeof(slang_ir_storage
));
170 st
->Swizzle
= SWIZZLE_NOOP
;
177 swizzle_string(GLuint swizzle
)
182 for (i
= 1; i
< 5; i
++) {
183 s
[i
] = "xyzw"[GET_SWZ(swizzle
, i
-1)];
190 writemask_string(GLuint writemask
)
195 for (i
= 0; i
< 4; i
++) {
196 if (writemask
& (1 << i
))
204 storage_string(const slang_ir_storage
*st
)
206 static const char *files
[] = {
224 sprintf(s
, "%s[%d]", files
[st
->File
], st
->Index
);
226 sprintf(s
, "%s[%d..%d]", files
[st
->File
], st
->Index
,
227 st
->Index
+ st
->Size
- 1);
229 assert(st
->File
< (GLint
) (sizeof(files
) / sizeof(files
[0])));
230 sprintf(s
, "%s[%d]", files
[st
->File
], st
->Index
);
237 slang_print_ir(const slang_ir_node
*n
, int indent
)
243 if (n
->Opcode
!= IR_SEQ
)
245 printf("%3d:", indent
);
247 for (i
= 0; i
< indent
; i
++)
253 printf("SEQ at %p\n", (void*) n
);
255 assert(n
->Children
[0]);
256 assert(n
->Children
[1]);
257 slang_print_ir(n
->Children
[0], indent
+ IND
);
258 slang_print_ir(n
->Children
[1], indent
+ IND
);
261 printf("NEW SCOPE\n");
262 assert(!n
->Children
[1]);
263 slang_print_ir(n
->Children
[0], indent
+ 3);
266 printf("MOVE (writemask = %s)\n", writemask_string(n
->Writemask
));
267 slang_print_ir(n
->Children
[0], indent
+3);
268 slang_print_ir(n
->Children
[1], indent
+3);
271 printf("LABEL: %s\n", n
->Target
);
275 slang_print_ir(n
->Children
[0], indent
+ 3);
278 printf("JUMP %s\n", n
->Target
);
281 printf("CJUMP0 %s\n", n
->Target
);
282 slang_print_ir(n
->Children
[0], indent
+3);
285 printf("CJUMP1 %s\n", n
->Target
);
286 slang_print_ir(n
->Children
[0], indent
+3);
291 slang_print_ir(n
->Children
[0], indent
+3);
301 printf("VAR %s%s at %s store %p\n",
302 (n
->Var
? (char *) n
->Var
->a_name
: "TEMP"),
303 swizzle_string(n
->Store
->Swizzle
),
304 storage_string(n
->Store
), (void*) n
->Store
);
307 printf("VAR_DECL %s (%p) at %s store %p\n",
308 (n
->Var
? (char *) n
->Var
->a_name
: "TEMP"),
309 (void*) n
->Var
, storage_string(n
->Store
),
313 printf("FIELD %s of\n", n
->Target
);
314 slang_print_ir(n
->Children
[0], indent
+3);
317 printf("ASMCALL %s(%d args)\n", n
->Target
, 0/*XXX*/);
320 printf("FLOAT %f %f %f %f\n",
321 n
->Value
[0], n
->Value
[1], n
->Value
[2], n
->Value
[3]);
324 printf("INT_TO_FLOAT %d\n", (int) n
->Value
[0]);
327 printf("SWIZZLE %s of (store %p) \n",
328 swizzle_string(n
->Store
->Swizzle
), (void*) n
->Store
);
329 slang_print_ir(n
->Children
[0], indent
+ 3);
332 printf("%s (%p, %p) (store %p)\n", slang_ir_name(n
->Opcode
),
333 (void*) n
->Children
[0], (void*) n
->Children
[1], (void*) n
->Store
);
334 slang_print_ir(n
->Children
[0], indent
+3);
335 slang_print_ir(n
->Children
[1], indent
+3);
341 * Allocate temporary storage for an intermediate result (such as for
342 * a multiply or add, etc.
345 alloc_temp_storage(slang_var_table
*vt
, slang_ir_node
*n
, GLint size
)
350 n
->Store
= _slang_new_ir_storage(PROGRAM_TEMPORARY
, -1, size
);
351 if (!_slang_alloc_temp(vt
, n
->Store
)) {
352 RETURN_ERROR("Ran out of registers, too many temporaries", 0);
359 * Free temporary storage, if n->Store is, in fact, temp storage.
363 free_temp_storage(slang_var_table
*vt
, slang_ir_node
*n
)
365 if (n
->Store
->File
== PROGRAM_TEMPORARY
&& n
->Store
->Index
>= 0) {
366 if (_slang_is_temp(vt
, n
->Store
)) {
367 _slang_free_temp(vt
, n
->Store
);
368 n
->Store
->Index
= -1;
376 * Convert IR storage to an instruction dst register.
379 storage_to_dst_reg(struct prog_dst_register
*dst
, const slang_ir_storage
*st
,
382 static const GLuint defaultWritemask
[4] = {
384 WRITEMASK_X
| WRITEMASK_Y
,
385 WRITEMASK_X
| WRITEMASK_Y
| WRITEMASK_Z
,
386 WRITEMASK_X
| WRITEMASK_Y
| WRITEMASK_Z
| WRITEMASK_W
388 assert(st
->Index
>= 0 && st
->Index
<= 16);
389 dst
->File
= st
->File
;
390 dst
->Index
= st
->Index
;
391 assert(st
->File
!= PROGRAM_UNDEFINED
);
392 assert(st
->Size
>= 1);
393 assert(st
->Size
<= 4);
395 GLuint comp
= GET_SWZ(st
->Swizzle
, 0);
397 assert(writemask
& WRITEMASK_X
);
398 dst
->WriteMask
= WRITEMASK_X
<< comp
;
401 dst
->WriteMask
= defaultWritemask
[st
->Size
- 1] & writemask
;
407 * Convert IR storage to an instruction src register.
410 storage_to_src_reg(struct prog_src_register
*src
, const slang_ir_storage
*st
)
412 static const GLuint defaultSwizzle
[4] = {
413 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
414 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
415 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
416 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
)
418 assert(st
->File
>= 0 && st
->File
<= 16);
419 src
->File
= st
->File
;
420 src
->Index
= st
->Index
;
421 assert(st
->File
!= PROGRAM_UNDEFINED
);
422 assert(st
->Size
>= 1);
423 assert(st
->Size
<= 4);
424 if (st
->Swizzle
!= SWIZZLE_NOOP
)
425 src
->Swizzle
= st
->Swizzle
;
427 src
->Swizzle
= defaultSwizzle
[st
->Size
- 1]; /*XXX really need this?*/
429 assert(GET_SWZ(src
->Swizzle
, 0) != SWIZZLE_NIL
);
430 assert(GET_SWZ(src
->Swizzle
, 1) != SWIZZLE_NIL
);
431 assert(GET_SWZ(src
->Swizzle
, 2) != SWIZZLE_NIL
);
432 assert(GET_SWZ(src
->Swizzle
, 3) != SWIZZLE_NIL
);
438 * Add new instruction at end of given program.
439 * \param prog the program to append instruction onto
440 * \param opcode opcode for the new instruction
441 * \return pointer to the new instruction
443 static struct prog_instruction
*
444 new_instruction(struct gl_program
*prog
, gl_inst_opcode opcode
)
446 struct prog_instruction
*inst
;
447 prog
->Instructions
= _mesa_realloc_instructions(prog
->Instructions
,
448 prog
->NumInstructions
,
449 prog
->NumInstructions
+ 1);
450 inst
= prog
->Instructions
+ prog
->NumInstructions
;
451 prog
->NumInstructions
++;
452 _mesa_init_instructions(inst
, 1);
453 inst
->Opcode
= opcode
;
459 * Return pointer to last instruction in program.
461 static struct prog_instruction
*
462 prev_instruction(struct gl_program
*prog
)
464 if (prog
->NumInstructions
== 0)
467 return prog
->Instructions
+ prog
->NumInstructions
- 1;
471 static struct prog_instruction
*
472 emit(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
);
476 * Return an annotation string for given node's storage.
479 storage_annotation(const slang_ir_node
*n
, const struct gl_program
*prog
)
482 const slang_ir_storage
*st
= n
->Store
;
483 static char s
[100] = "";
486 return _mesa_strdup("");
489 case PROGRAM_CONSTANT
:
490 if (st
->Index
>= 0) {
491 const GLfloat
*val
= prog
->Parameters
->ParameterValues
[st
->Index
];
492 if (st
->Swizzle
== SWIZZLE_NOOP
)
493 sprintf(s
, "{%f, %f, %f, %f}", val
[0], val
[1], val
[2], val
[3]);
495 sprintf(s
, "%f", val
[GET_SWZ(st
->Swizzle
, 0)]);
499 case PROGRAM_TEMPORARY
:
501 sprintf(s
, "%s", (char *) n
->Var
->a_name
);
503 sprintf(s
, "t[%d]", st
->Index
);
505 case PROGRAM_STATE_VAR
:
506 case PROGRAM_UNIFORM
:
507 sprintf(s
, "%s", prog
->Parameters
->Parameters
[st
->Index
].Name
);
509 case PROGRAM_VARYING
:
510 sprintf(s
, "%s", prog
->Varying
->Parameters
[st
->Index
].Name
);
513 sprintf(s
, "input[%d]", st
->Index
);
516 sprintf(s
, "output[%d]", st
->Index
);
521 return _mesa_strdup(s
);
529 * Return an annotation string for an instruction.
532 instruction_annotation(gl_inst_opcode opcode
, char *dstAnnot
,
533 char *srcAnnot0
, char *srcAnnot1
, char *srcAnnot2
)
536 const char *operator;
541 len
+= strlen(dstAnnot
);
543 dstAnnot
= _mesa_strdup("");
546 len
+= strlen(srcAnnot0
);
548 srcAnnot0
= _mesa_strdup("");
551 len
+= strlen(srcAnnot1
);
553 srcAnnot1
= _mesa_strdup("");
556 len
+= strlen(srcAnnot2
);
558 srcAnnot2
= _mesa_strdup("");
589 s
= (char *) malloc(len
);
590 sprintf(s
, "%s = %s %s %s %s", dstAnnot
,
591 srcAnnot0
, operator, srcAnnot1
, srcAnnot2
);
592 assert(_mesa_strlen(s
) < len
);
608 * Generate code for a simple arithmetic instruction.
609 * Either 1, 2 or 3 operands.
611 static struct prog_instruction
*
612 emit_arith(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
614 struct prog_instruction
*inst
;
615 const slang_ir_info
*info
= slang_find_ir_info(n
->Opcode
);
616 char *srcAnnot
[3], *dstAnnot
;
620 assert(info
->InstOpcode
!= OPCODE_NOP
);
622 srcAnnot
[0] = srcAnnot
[1] = srcAnnot
[2] = dstAnnot
= NULL
;
624 #if PEEPHOLE_OPTIMIZATIONS
625 /* Look for MAD opportunity */
626 if (info
->NumParams
== 2 &&
627 n
->Opcode
== IR_ADD
&& n
->Children
[0]->Opcode
== IR_MUL
) {
628 /* found pattern IR_ADD(IR_MUL(A, B), C) */
629 emit(vt
, n
->Children
[0]->Children
[0], prog
); /* A */
630 emit(vt
, n
->Children
[0]->Children
[1], prog
); /* B */
631 emit(vt
, n
->Children
[1], prog
); /* C */
632 /* generate MAD instruction */
633 inst
= new_instruction(prog
, OPCODE_MAD
);
634 /* operands: A, B, C: */
635 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[0]->Children
[0]->Store
);
636 storage_to_src_reg(&inst
->SrcReg
[1], n
->Children
[0]->Children
[1]->Store
);
637 storage_to_src_reg(&inst
->SrcReg
[2], n
->Children
[1]->Store
);
638 free_temp_storage(vt
, n
->Children
[0]->Children
[0]);
639 free_temp_storage(vt
, n
->Children
[0]->Children
[1]);
640 free_temp_storage(vt
, n
->Children
[1]);
642 else if (info
->NumParams
== 2 &&
643 n
->Opcode
== IR_ADD
&& n
->Children
[1]->Opcode
== IR_MUL
) {
644 /* found pattern IR_ADD(A, IR_MUL(B, C)) */
645 emit(vt
, n
->Children
[0], prog
); /* A */
646 emit(vt
, n
->Children
[1]->Children
[0], prog
); /* B */
647 emit(vt
, n
->Children
[1]->Children
[1], prog
); /* C */
648 /* generate MAD instruction */
649 inst
= new_instruction(prog
, OPCODE_MAD
);
650 /* operands: B, C, A */
651 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[1]->Children
[0]->Store
);
652 storage_to_src_reg(&inst
->SrcReg
[1], n
->Children
[1]->Children
[1]->Store
);
653 storage_to_src_reg(&inst
->SrcReg
[2], n
->Children
[0]->Store
);
654 free_temp_storage(vt
, n
->Children
[1]->Children
[0]);
655 free_temp_storage(vt
, n
->Children
[1]->Children
[1]);
656 free_temp_storage(vt
, n
->Children
[0]);
663 /* gen code for children */
664 for (i
= 0; i
< info
->NumParams
; i
++)
665 emit(vt
, n
->Children
[i
], prog
);
667 /* gen this instruction and src registers */
668 inst
= new_instruction(prog
, info
->InstOpcode
);
669 for (i
= 0; i
< info
->NumParams
; i
++)
670 storage_to_src_reg(&inst
->SrcReg
[i
], n
->Children
[i
]->Store
);
673 for (i
= 0; i
< info
->NumParams
; i
++)
674 srcAnnot
[i
] = storage_annotation(n
->Children
[i
], prog
);
677 for (i
= 0; i
< info
->NumParams
; i
++)
678 free_temp_storage(vt
, n
->Children
[i
]);
683 if (!alloc_temp_storage(vt
, n
, info
->ResultSize
))
686 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
688 dstAnnot
= storage_annotation(n
, prog
);
690 inst
->Comment
= instruction_annotation(inst
->Opcode
, dstAnnot
, srcAnnot
[0],
691 srcAnnot
[1], srcAnnot
[2]);
693 /*_mesa_print_instruction(inst);*/
699 * Generate code for an IR_CLAMP instruction.
701 static struct prog_instruction
*
702 emit_clamp(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
704 struct prog_instruction
*inst
;
706 assert(n
->Opcode
== IR_CLAMP
);
712 inst
= emit(vt
, n
->Children
[0], prog
);
714 /* If lower limit == 0.0 and upper limit == 1.0,
715 * set prev instruction's SaturateMode field to SATURATE_ZERO_ONE.
717 * emit OPCODE_MIN, OPCODE_MAX sequence.
720 /* XXX this isn't quite finished yet */
721 if (n
->Children
[1]->Opcode
== IR_FLOAT
&&
722 n
->Children
[1]->Value
[0] == 0.0 &&
723 n
->Children
[1]->Value
[1] == 0.0 &&
724 n
->Children
[1]->Value
[2] == 0.0 &&
725 n
->Children
[1]->Value
[3] == 0.0 &&
726 n
->Children
[2]->Opcode
== IR_FLOAT
&&
727 n
->Children
[2]->Value
[0] == 1.0 &&
728 n
->Children
[2]->Value
[1] == 1.0 &&
729 n
->Children
[2]->Value
[2] == 1.0 &&
730 n
->Children
[2]->Value
[3] == 1.0) {
732 inst
= prev_instruction(prog
);
734 if (inst
&& inst
->Opcode
!= OPCODE_NOP
) {
735 /* and prev instruction's DstReg matches n->Children[0]->Store */
736 inst
->SaturateMode
= SATURATE_ZERO_ONE
;
737 n
->Store
= n
->Children
[0]->Store
;
744 if (!alloc_temp_storage(vt
, n
, n
->Children
[0]->Store
->Size
))
747 emit(vt
, n
->Children
[1], prog
);
748 emit(vt
, n
->Children
[2], prog
);
750 /* tmp = max(ch[0], ch[1]) */
751 inst
= new_instruction(prog
, OPCODE_MAX
);
752 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
753 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[0]->Store
);
754 storage_to_src_reg(&inst
->SrcReg
[1], n
->Children
[1]->Store
);
756 /* tmp = min(tmp, ch[2]) */
757 inst
= new_instruction(prog
, OPCODE_MIN
);
758 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
759 storage_to_src_reg(&inst
->SrcReg
[0], n
->Store
);
760 storage_to_src_reg(&inst
->SrcReg
[1], n
->Children
[2]->Store
);
766 static struct prog_instruction
*
767 emit_negation(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
769 /* Implement as MOV dst, -src; */
770 /* XXX we could look at the previous instruction and in some circumstances
771 * modify it to accomplish the negation.
773 struct prog_instruction
*inst
;
775 emit(vt
, n
->Children
[0], prog
);
778 if (!alloc_temp_storage(vt
, n
, n
->Children
[0]->Store
->Size
))
781 inst
= new_instruction(prog
, OPCODE_MOV
);
782 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
783 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[0]->Store
);
784 inst
->SrcReg
[0].NegateBase
= NEGATE_XYZW
;
785 inst
->Comment
= n
->Comment
;
790 static struct prog_instruction
*
791 emit_label(const char *target
, struct gl_program
*prog
)
793 struct prog_instruction
*inst
;
794 inst
= new_instruction(prog
, OPCODE_NOP
);
795 inst
->Comment
= _mesa_strdup(target
);
800 static struct prog_instruction
*
801 emit_cjump(const char *target
, struct gl_program
*prog
, GLuint zeroOrOne
)
803 struct prog_instruction
*inst
;
804 inst
= new_instruction(prog
, OPCODE_BRA
);
806 inst
->DstReg
.CondMask
= COND_NE
; /* branch if non-zero */
808 inst
->DstReg
.CondMask
= COND_EQ
; /* branch if equal to zero */
809 inst
->DstReg
.CondSwizzle
= SWIZZLE_X
;
810 inst
->Comment
= _mesa_strdup(target
);
815 static struct prog_instruction
*
816 emit_jump(const char *target
, struct gl_program
*prog
)
818 struct prog_instruction
*inst
;
819 inst
= new_instruction(prog
, OPCODE_BRA
);
820 inst
->DstReg
.CondMask
= COND_TR
; /* always branch */
821 /*inst->DstReg.CondSwizzle = SWIZZLE_X;*/
822 inst
->Comment
= _mesa_strdup(target
);
827 static struct prog_instruction
*
828 emit_kill(struct gl_program
*prog
)
830 struct prog_instruction
*inst
;
831 /* NV-KILL - discard fragment depending on condition code.
832 * Note that ARB-KILL depends on sign of vector operand.
834 inst
= new_instruction(prog
, OPCODE_KIL_NV
);
835 inst
->DstReg
.CondMask
= COND_TR
; /* always branch */
840 static struct prog_instruction
*
841 emit_tex(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
843 struct prog_instruction
*inst
;
844 if (n
->Opcode
== IR_TEX
) {
845 inst
= new_instruction(prog
, OPCODE_TEX
);
847 else if (n
->Opcode
== IR_TEXB
) {
848 inst
= new_instruction(prog
, OPCODE_TXB
);
851 assert(n
->Opcode
== IR_TEXP
);
852 inst
= new_instruction(prog
, OPCODE_TXP
);
856 if (!alloc_temp_storage(vt
, n
, 4))
859 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
861 /* Child[1] is the coord */
862 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[1]->Store
);
864 /* Child[0] is the sampler (a uniform which'll indicate the texture unit) */
865 assert(n
->Children
[0]->Store
);
866 assert(n
->Children
[0]->Store
->Size
>= TEXTURE_1D_INDEX
);
868 inst
->Sampler
= n
->Children
[0]->Store
->Index
; /* i.e. uniform's index */
869 inst
->TexSrcTarget
= n
->Children
[0]->Store
->Size
;
870 inst
->TexSrcUnit
= 27; /* Dummy value; the TexSrcUnit will be computed at
871 * link time, using the sampler uniform's value.
877 static struct prog_instruction
*
878 emit_move(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
880 struct prog_instruction
*inst
;
883 assert(n
->Children
[1]);
884 inst
= emit(vt
, n
->Children
[1], prog
);
886 assert(n
->Children
[1]->Store
->Index
>= 0);
889 emit(vt
, n
->Children
[0], prog
);
892 n
->Store
= n
->Children
[0]->Store
;
894 #if PEEPHOLE_OPTIMIZATIONS
895 if (inst
&& _slang_is_temp(vt
, n
->Children
[1]->Store
)) {
896 /* Peephole optimization:
897 * Just modify the RHS to put its result into the dest of this
898 * MOVE operation. Then, this MOVE is a no-op.
900 _slang_free_temp(vt
, n
->Children
[1]->Store
);
901 *n
->Children
[1]->Store
= *n
->Children
[0]->Store
;
902 /* fixup the prev (RHS) instruction */
903 assert(n
->Children
[0]->Store
->Index
>= 0);
904 assert(n
->Children
[0]->Store
->Index
< 16);
905 storage_to_dst_reg(&inst
->DstReg
, n
->Children
[0]->Store
, n
->Writemask
);
911 if (n
->Children
[0]->Store
->Size
> 4) {
912 /* move matrix/struct etc (block of registers) */
913 slang_ir_storage dstStore
= *n
->Children
[0]->Store
;
914 slang_ir_storage srcStore
= *n
->Children
[1]->Store
;
915 GLint size
= srcStore
.Size
;
916 ASSERT(n
->Children
[0]->Writemask
== WRITEMASK_XYZW
);
917 ASSERT(n
->Children
[1]->Store
->Swizzle
== SWIZZLE_NOOP
);
921 inst
= new_instruction(prog
, OPCODE_MOV
);
922 inst
->Comment
= _mesa_strdup("IR_MOVE block");
923 storage_to_dst_reg(&inst
->DstReg
, &dstStore
, n
->Writemask
);
924 storage_to_src_reg(&inst
->SrcReg
[0], &srcStore
);
931 /* single register move */
932 char *srcAnnot
, *dstAnnot
;
933 inst
= new_instruction(prog
, OPCODE_MOV
);
934 assert(n
->Children
[0]->Store
->Index
>= 0);
935 assert(n
->Children
[0]->Store
->Index
< 16);
936 storage_to_dst_reg(&inst
->DstReg
, n
->Children
[0]->Store
, n
->Writemask
);
937 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[1]->Store
);
938 dstAnnot
= storage_annotation(n
->Children
[0], prog
);
939 srcAnnot
= storage_annotation(n
->Children
[1], prog
);
940 inst
->Comment
= instruction_annotation(inst
->Opcode
, dstAnnot
,
941 srcAnnot
, NULL
, NULL
);
943 free_temp_storage(vt
, n
->Children
[1]);
949 static struct prog_instruction
*
950 emit_cond(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
952 /* Conditional expression (in if/while/for stmts).
953 * Need to update condition code register.
954 * Next instruction is typically an IR_CJUMP0/1.
956 /* last child expr instruction: */
957 struct prog_instruction
*inst
= emit(vt
, n
->Children
[0], prog
);
959 /* set inst's CondUpdate flag */
960 inst
->CondUpdate
= GL_TRUE
;
961 return inst
; /* XXX or null? */
964 /* This'll happen for things like "if (i) ..." where no code
965 * is normally generated for the expression "i".
966 * Generate a move instruction just to set condition codes.
967 * Note: must use full 4-component vector since all four
968 * condition codes must be set identically.
970 if (!alloc_temp_storage(vt
, n
, 4))
972 inst
= new_instruction(prog
, OPCODE_MOV
);
973 inst
->CondUpdate
= GL_TRUE
;
974 storage_to_dst_reg(&inst
->DstReg
, n
->Store
, n
->Writemask
);
975 storage_to_src_reg(&inst
->SrcReg
[0], n
->Children
[0]->Store
);
976 _slang_free_temp(vt
, n
->Store
);
977 inst
->Comment
= _mesa_strdup("COND expr");
978 return inst
; /* XXX or null? */
984 * Remove any SWIZZLE_NIL terms from given swizzle mask (smear prev term).
985 * Ex: fix_swizzle("zyNN") -> "zyyy"
988 fix_swizzle(GLuint swizzle
)
991 for (i
= 0; i
< 4; i
++) {
992 swz
[i
] = GET_SWZ(swizzle
, i
);
993 if (swz
[i
] == SWIZZLE_NIL
) {
997 return MAKE_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
1001 static struct prog_instruction
*
1002 emit_swizzle(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
1006 /* swizzled storage access */
1007 (void) emit(vt
, n
->Children
[0], prog
);
1009 /* "pull-up" the child's storage info, applying our swizzle info */
1010 n
->Store
->File
= n
->Children
[0]->Store
->File
;
1011 n
->Store
->Index
= n
->Children
[0]->Store
->Index
;
1012 n
->Store
->Size
= n
->Children
[0]->Store
->Size
;
1013 /*n->Var = n->Children[0]->Var; XXX for debug */
1014 assert(n
->Store
->Index
>= 0);
1016 swizzle
= fix_swizzle(n
->Store
->Swizzle
);
1019 GLuint s
= n
->Children
[0]->Store
->Swizzle
;
1020 assert(GET_SWZ(s
, 0) != SWIZZLE_NIL
);
1021 assert(GET_SWZ(s
, 1) != SWIZZLE_NIL
);
1022 assert(GET_SWZ(s
, 2) != SWIZZLE_NIL
);
1023 assert(GET_SWZ(s
, 3) != SWIZZLE_NIL
);
1027 /* apply this swizzle to child's swizzle to get composed swizzle */
1028 n
->Store
->Swizzle
= swizzle_swizzle(n
->Children
[0]->Store
->Swizzle
,
1034 static struct prog_instruction
*
1035 emit(slang_var_table
*vt
, slang_ir_node
*n
, struct gl_program
*prog
)
1037 struct prog_instruction
*inst
;
1041 switch (n
->Opcode
) {
1043 /* sequence of two sub-trees */
1044 assert(n
->Children
[0]);
1045 assert(n
->Children
[1]);
1046 emit(vt
, n
->Children
[0], prog
);
1047 inst
= emit(vt
, n
->Children
[1], prog
);
1049 n
->Store
= n
->Children
[1]->Store
;
1053 /* new variable scope */
1054 _slang_push_var_table(vt
);
1055 inst
= emit(vt
, n
->Children
[0], prog
);
1056 _slang_pop_var_table(vt
);
1060 /* Variable declaration - allocate a register for it */
1062 assert(n
->Store
->File
!= PROGRAM_UNDEFINED
);
1063 assert(n
->Store
->Size
> 0);
1064 assert(n
->Store
->Index
< 0);
1065 if (!n
->Var
|| n
->Var
->isTemp
) {
1066 /* a nameless/temporary variable, will be freed after first use */
1067 if (!_slang_alloc_temp(vt
, n
->Store
))
1068 RETURN_ERROR("Ran out of registers, too many temporaries", 0);
1071 /* a regular variable */
1072 _slang_add_variable(vt
, n
->Var
);
1073 if (!_slang_alloc_var(vt
, n
->Store
))
1074 RETURN_ERROR("Ran out of registers, too many variables", 0);
1076 printf("IR_VAR_DECL %s %d store %p\n",
1077 (char*) n->Var->a_name, n->Store->Index, (void*) n->Store);
1079 assert(n
->Var
->aux
== n
->Store
);
1084 /* Reference to a variable
1085 * Storage should have already been resolved/allocated.
1088 assert(n
->Store
->File
!= PROGRAM_UNDEFINED
);
1089 if (n
->Store
->Index
< 0) {
1090 printf("#### VAR %s not allocated!\n", (char*)n
->Var
->a_name
);
1092 assert(n
->Store
->Index
>= 0);
1093 assert(n
->Store
->Size
> 0);
1097 /* Dereference array element. Just resolve storage for the array
1098 * element represented by this node.
1101 assert(n
->Store
->File
!= PROGRAM_UNDEFINED
);
1102 assert(n
->Store
->Size
> 0);
1103 if (n
->Children
[1]->Opcode
== IR_FLOAT
) {
1104 /* OK, constant index */
1105 const GLint arrayAddr
= n
->Children
[0]->Store
->Index
;
1106 const GLint index
= (GLint
) n
->Children
[1]->Value
[0];
1107 n
->Store
->Index
= arrayAddr
+ index
;
1110 /* Problem: variable index */
1111 const GLint arrayAddr
= n
->Children
[0]->Store
->Index
;
1112 const GLint index
= 0;
1113 _mesa_problem(NULL
, "variable array indexes not supported yet!");
1114 n
->Store
->Index
= arrayAddr
+ index
;
1116 return NULL
; /* no instruction */
1119 return emit_swizzle(vt
, n
, prog
);
1121 /* Simple arithmetic */
1153 /* trinary operators */
1155 return emit_arith(vt
, n
, prog
);
1157 return emit_clamp(vt
, n
, prog
);
1161 return emit_tex(vt
, n
, prog
);
1163 return emit_negation(vt
, n
, prog
);
1165 /* find storage location for this float constant */
1166 n
->Store
->Index
= _mesa_add_unnamed_constant(prog
->Parameters
, n
->Value
,
1168 &n
->Store
->Swizzle
);
1169 if (n
->Store
->Index
< 0) {
1170 RETURN_ERROR("Ran out of space for constants.", 0);
1175 return emit_move(vt
, n
, prog
);
1178 return emit_cond(vt
, n
, prog
);
1181 return emit_label(n
->Target
, prog
);
1183 return emit_jump(n
->Target
, prog
);
1185 return emit_cjump(n
->Target
, prog
, 0);
1187 return emit_cjump(n
->Target
, prog
, 1);
1189 return emit_kill(prog
);
1193 struct prog_instruction
*inst
;
1194 emit(vt
, n
->Children
[0], prog
); /* the condition */
1195 inst
= new_instruction(prog
, OPCODE_IF
);
1196 inst
->DstReg
.CondMask
= COND_NE
; /* if cond is non-zero */
1197 inst
->DstReg
.CondSwizzle
= SWIZZLE_X
;
1202 struct prog_instruction
*inst
;
1203 inst
= new_instruction(prog
, OPCODE_ELSE
);
1208 struct prog_instruction
*inst
;
1209 inst
= new_instruction(prog
, OPCODE_ENDIF
);
1214 _mesa_problem(NULL
, "Unexpected IR opcode in emit()\n");
1222 _slang_emit_code(slang_ir_node
*n
, slang_var_table
*vt
,
1223 struct gl_program
*prog
, GLboolean withEnd
)
1227 if (emit(vt
, n
, prog
)) {
1228 /* finish up by adding the END opcode to program */
1230 struct prog_instruction
*inst
;
1231 inst
= new_instruction(prog
, OPCODE_END
);
1236 /* record an error? */
1240 printf("*********** End generate code (%u inst):\n", prog
->NumInstructions
);
1242 _mesa_print_program(prog
);
1243 _mesa_print_program_parameters(ctx
,prog
);