2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
59 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
60 (1 << PROGRAM_CONSTANT) | \
61 (1 << PROGRAM_UNIFORM))
63 #define MAX_GLSL_TEXTURE_OFFSET 4
68 static int swizzle_for_size(int size
);
71 * This struct is a corresponding struct to TGSI ureg_src.
75 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
79 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
80 this->swizzle
= swizzle_for_size(type
->vector_elements
);
82 this->swizzle
= SWIZZLE_XYZW
;
85 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
87 this->reladdr2
= NULL
;
88 this->has_index2
= false;
89 this->double_reg2
= false;
91 this->is_double_vertex_input
= false;
94 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
100 this->swizzle
= SWIZZLE_XYZW
;
102 this->reladdr
= NULL
;
103 this->reladdr2
= NULL
;
104 this->has_index2
= false;
105 this->double_reg2
= false;
107 this->is_double_vertex_input
= false;
110 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
115 this->index2D
= index2D
;
116 this->swizzle
= SWIZZLE_XYZW
;
118 this->reladdr
= NULL
;
119 this->reladdr2
= NULL
;
120 this->has_index2
= false;
121 this->double_reg2
= false;
123 this->is_double_vertex_input
= false;
128 this->type
= GLSL_TYPE_ERROR
;
129 this->file
= PROGRAM_UNDEFINED
;
134 this->reladdr
= NULL
;
135 this->reladdr2
= NULL
;
136 this->has_index2
= false;
137 this->double_reg2
= false;
139 this->is_double_vertex_input
= false;
142 explicit st_src_reg(st_dst_reg reg
);
144 gl_register_file file
; /**< PROGRAM_* from Mesa */
145 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
147 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
148 int negate
; /**< NEGATE_XYZW mask from mesa */
149 enum glsl_base_type type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
150 /** Register index should be offset by the integer in this reg. */
152 st_src_reg
*reladdr2
;
155 * Is this the second half of a double register pair?
156 * currently used for input mapping only.
160 bool is_double_vertex_input
;
165 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
170 this->writemask
= writemask
;
171 this->reladdr
= NULL
;
172 this->reladdr2
= NULL
;
173 this->has_index2
= false;
178 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
183 this->writemask
= writemask
;
184 this->reladdr
= NULL
;
185 this->reladdr2
= NULL
;
186 this->has_index2
= false;
193 this->type
= GLSL_TYPE_ERROR
;
194 this->file
= PROGRAM_UNDEFINED
;
198 this->reladdr
= NULL
;
199 this->reladdr2
= NULL
;
200 this->has_index2
= false;
204 explicit st_dst_reg(st_src_reg reg
);
206 gl_register_file file
; /**< PROGRAM_* from Mesa */
207 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
209 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
210 enum glsl_base_type type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
211 /** Register index should be offset by the integer in this reg. */
213 st_src_reg
*reladdr2
;
218 st_src_reg::st_src_reg(st_dst_reg reg
)
220 this->type
= reg
.type
;
221 this->file
= reg
.file
;
222 this->index
= reg
.index
;
223 this->swizzle
= SWIZZLE_XYZW
;
225 this->reladdr
= reg
.reladdr
;
226 this->index2D
= reg
.index2D
;
227 this->reladdr2
= reg
.reladdr2
;
228 this->has_index2
= reg
.has_index2
;
229 this->double_reg2
= false;
230 this->array_id
= reg
.array_id
;
231 this->is_double_vertex_input
= false;
234 st_dst_reg::st_dst_reg(st_src_reg reg
)
236 this->type
= reg
.type
;
237 this->file
= reg
.file
;
238 this->index
= reg
.index
;
239 this->writemask
= WRITEMASK_XYZW
;
240 this->reladdr
= reg
.reladdr
;
241 this->index2D
= reg
.index2D
;
242 this->reladdr2
= reg
.reladdr2
;
243 this->has_index2
= reg
.has_index2
;
244 this->array_id
= reg
.array_id
;
247 class glsl_to_tgsi_instruction
: public exec_node
{
249 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
254 /** Pointer to the ir source this tree came from for debugging */
256 GLboolean cond_update
;
258 st_src_reg sampler
; /**< sampler register */
260 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
261 int tex_target
; /**< One of TEXTURE_*_INDEX */
262 glsl_base_type tex_type
;
263 GLboolean tex_shadow
;
264 unsigned image_format
;
266 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
267 unsigned tex_offset_num_offset
;
268 int dead_mask
; /**< Used in dead code elimination */
270 st_src_reg buffer
; /**< buffer register */
271 unsigned buffer_access
; /**< buffer access type */
273 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
274 const struct tgsi_opcode_info
*info
;
277 class variable_storage
: public exec_node
{
279 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
280 unsigned array_id
= 0)
281 : file(file
), index(index
), var(var
), array_id(array_id
)
286 gl_register_file file
;
288 ir_variable
*var
; /* variable that maps to this, if any */
292 class immediate_storage
: public exec_node
{
294 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
296 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
297 this->size32
= size32
;
301 /* doubles are stored across 2 gl_constant_values */
302 gl_constant_value values
[4];
303 int size32
; /**< Number of 32-bit components (1-4) */
304 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
307 class function_entry
: public exec_node
{
309 ir_function_signature
*sig
;
312 * identifier of this function signature used by the program.
314 * At the point that TGSI instructions for function calls are
315 * generated, we don't know the address of the first instruction of
316 * the function body. So we make the BranchTarget that is called a
317 * small integer and rewrite them during set_branchtargets().
322 * Pointer to first instruction of the function body.
324 * Set during function body emits after main() is processed.
326 glsl_to_tgsi_instruction
*bgn_inst
;
329 * Index of the first instruction of the function body in actual TGSI.
331 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
335 /** Storage for the return value. */
336 st_src_reg return_reg
;
339 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
340 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
346 enum glsl_base_type array_type
;
349 static enum glsl_base_type
350 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
354 for (i
= 0; i
< count
; i
++) {
355 struct array_decl
*decl
= &arrays
[i
];
357 if (array_id
== decl
->array_id
) {
358 return decl
->array_type
;
361 return GLSL_TYPE_ERROR
;
364 struct rename_reg_pair
{
369 struct glsl_to_tgsi_visitor
: public ir_visitor
{
371 glsl_to_tgsi_visitor();
372 ~glsl_to_tgsi_visitor();
374 function_entry
*current_function
;
376 struct gl_context
*ctx
;
377 struct gl_program
*prog
;
378 struct gl_shader_program
*shader_program
;
379 struct gl_shader
*shader
;
380 struct gl_shader_compiler_options
*options
;
384 unsigned *array_sizes
;
385 unsigned max_num_arrays
;
388 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
389 unsigned num_input_arrays
;
390 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
391 unsigned num_output_arrays
;
393 int num_address_regs
;
394 uint32_t samplers_used
;
395 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
396 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
399 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
400 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
401 bool indirect_addr_consts
;
402 int wpos_transform_const
;
405 bool native_integers
;
408 bool use_shared_memory
;
410 variable_storage
*find_variable_storage(ir_variable
*var
);
412 int add_constant(gl_register_file file
, gl_constant_value values
[8],
413 int size
, int datatype
, GLuint
*swizzle_out
);
415 function_entry
*get_function_signature(ir_function_signature
*sig
);
417 st_src_reg
get_temp(const glsl_type
*type
);
418 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
420 st_src_reg
st_src_reg_for_double(double val
);
421 st_src_reg
st_src_reg_for_float(float val
);
422 st_src_reg
st_src_reg_for_int(int val
);
423 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
426 * \name Visit methods
428 * As typical for the visitor pattern, there must be one \c visit method for
429 * each concrete subclass of \c ir_instruction. Virtual base classes within
430 * the hierarchy should not have \c visit methods.
433 virtual void visit(ir_variable
*);
434 virtual void visit(ir_loop
*);
435 virtual void visit(ir_loop_jump
*);
436 virtual void visit(ir_function_signature
*);
437 virtual void visit(ir_function
*);
438 virtual void visit(ir_expression
*);
439 virtual void visit(ir_swizzle
*);
440 virtual void visit(ir_dereference_variable
*);
441 virtual void visit(ir_dereference_array
*);
442 virtual void visit(ir_dereference_record
*);
443 virtual void visit(ir_assignment
*);
444 virtual void visit(ir_constant
*);
445 virtual void visit(ir_call
*);
446 virtual void visit(ir_return
*);
447 virtual void visit(ir_discard
*);
448 virtual void visit(ir_texture
*);
449 virtual void visit(ir_if
*);
450 virtual void visit(ir_emit_vertex
*);
451 virtual void visit(ir_end_primitive
*);
452 virtual void visit(ir_barrier
*);
455 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
457 void visit_atomic_counter_intrinsic(ir_call
*);
458 void visit_ssbo_intrinsic(ir_call
*);
459 void visit_membar_intrinsic(ir_call
*);
460 void visit_shared_intrinsic(ir_call
*);
461 void visit_image_intrinsic(ir_call
*);
465 /** List of variable_storage */
468 /** List of immediate_storage */
469 exec_list immediates
;
470 unsigned num_immediates
;
472 /** List of function_entry */
473 exec_list function_signatures
;
474 int next_signature_id
;
476 /** List of glsl_to_tgsi_instruction */
477 exec_list instructions
;
479 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
480 st_dst_reg dst
= undef_dst
,
481 st_src_reg src0
= undef_src
,
482 st_src_reg src1
= undef_src
,
483 st_src_reg src2
= undef_src
,
484 st_src_reg src3
= undef_src
);
486 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
487 st_dst_reg dst
, st_dst_reg dst1
,
488 st_src_reg src0
= undef_src
,
489 st_src_reg src1
= undef_src
,
490 st_src_reg src2
= undef_src
,
491 st_src_reg src3
= undef_src
);
493 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
495 st_src_reg src0
, st_src_reg src1
);
498 * Emit the correct dot-product instruction for the type of arguments
500 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
506 void emit_scalar(ir_instruction
*ir
, unsigned op
,
507 st_dst_reg dst
, st_src_reg src0
);
509 void emit_scalar(ir_instruction
*ir
, unsigned op
,
510 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
512 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
514 void get_deref_offsets(ir_dereference
*ir
,
515 unsigned *array_size
,
518 st_src_reg
*reladdr
);
519 void calc_deref_offsets(ir_dereference
*head
,
520 ir_dereference
*tail
,
521 unsigned *array_elements
,
524 st_src_reg
*indirect
,
527 bool try_emit_mad(ir_expression
*ir
,
529 bool try_emit_mad_for_and_not(ir_expression
*ir
,
532 void emit_swz(ir_expression
*ir
);
534 bool process_move_condition(ir_rvalue
*ir
);
536 void simplify_cmp(void);
538 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
539 void get_first_temp_read(int *first_reads
);
540 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
541 void get_last_temp_write(int *last_writes
);
543 void copy_propagate(void);
544 int eliminate_dead_code(void);
546 void merge_two_dsts(void);
547 void merge_registers(void);
548 void renumber_registers(void);
550 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
551 st_dst_reg
*l
, st_src_reg
*r
,
552 st_src_reg
*cond
, bool cond_swap
);
557 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
558 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
559 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
562 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
565 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
569 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
572 prog
->LinkStatus
= GL_FALSE
;
576 swizzle_for_size(int size
)
578 static const int size_swizzles
[4] = {
579 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
580 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
581 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
582 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
585 assert((size
>= 1) && (size
<= 4));
586 return size_swizzles
[size
- 1];
590 is_resource_instruction(unsigned opcode
)
593 case TGSI_OPCODE_RESQ
:
594 case TGSI_OPCODE_LOAD
:
595 case TGSI_OPCODE_ATOMUADD
:
596 case TGSI_OPCODE_ATOMXCHG
:
597 case TGSI_OPCODE_ATOMCAS
:
598 case TGSI_OPCODE_ATOMAND
:
599 case TGSI_OPCODE_ATOMOR
:
600 case TGSI_OPCODE_ATOMXOR
:
601 case TGSI_OPCODE_ATOMUMIN
:
602 case TGSI_OPCODE_ATOMUMAX
:
603 case TGSI_OPCODE_ATOMIMIN
:
604 case TGSI_OPCODE_ATOMIMAX
:
612 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
614 return op
->info
->num_dst
;
618 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
620 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
621 op
->info
->num_src
- 1 : op
->info
->num_src
;
624 glsl_to_tgsi_instruction
*
625 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
626 st_dst_reg dst
, st_dst_reg dst1
,
627 st_src_reg src0
, st_src_reg src1
,
628 st_src_reg src2
, st_src_reg src3
)
630 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
631 int num_reladdr
= 0, i
, j
;
632 bool dst_is_double
[2];
634 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
636 /* If we have to do relative addressing, we want to load the ARL
637 * reg directly for one of the regs, and preload the other reladdr
638 * sources into temps.
640 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
641 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
642 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
643 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
644 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
645 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
647 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
648 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
649 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
650 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
652 if (dst
.reladdr
|| dst
.reladdr2
) {
654 emit_arl(ir
, address_reg
, *dst
.reladdr
);
656 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
660 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
663 assert(num_reladdr
== 0);
666 inst
->info
= tgsi_get_opcode_info(op
);
675 /* default to float, for paths where this is not initialized
676 * (since 0==UINT which is likely wrong):
678 inst
->tex_type
= GLSL_TYPE_FLOAT
;
680 inst
->function
= NULL
;
682 /* Update indirect addressing status used by TGSI */
683 if (dst
.reladdr
|| dst
.reladdr2
) {
685 case PROGRAM_STATE_VAR
:
686 case PROGRAM_CONSTANT
:
687 case PROGRAM_UNIFORM
:
688 this->indirect_addr_consts
= true;
690 case PROGRAM_IMMEDIATE
:
691 assert(!"immediates should not have indirect addressing");
698 for (i
= 0; i
< 4; i
++) {
699 if(inst
->src
[i
].reladdr
) {
700 switch(inst
->src
[i
].file
) {
701 case PROGRAM_STATE_VAR
:
702 case PROGRAM_CONSTANT
:
703 case PROGRAM_UNIFORM
:
704 this->indirect_addr_consts
= true;
706 case PROGRAM_IMMEDIATE
:
707 assert(!"immediates should not have indirect addressing");
717 * This section contains the double processing.
718 * GLSL just represents doubles as single channel values,
719 * however most HW and TGSI represent doubles as pairs of register channels.
721 * so we have to fixup destination writemask/index and src swizzle/indexes.
722 * dest writemasks need to translate from single channel write mask
723 * to a dual-channel writemask, but also need to modify the index,
724 * if we are touching the Z,W fields in the pre-translated writemask.
726 * src channels have similiar index modifications along with swizzle
727 * changes to we pick the XY, ZW pairs from the correct index.
729 * GLSL [0].x -> TGSI [0].xy
730 * GLSL [0].y -> TGSI [0].zw
731 * GLSL [0].z -> TGSI [1].xy
732 * GLSL [0].w -> TGSI [1].zw
734 for (j
= 0; j
< 2; j
++) {
735 dst_is_double
[j
] = false;
736 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
737 dst_is_double
[j
] = true;
738 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
739 enum glsl_base_type type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
740 if (type
== GLSL_TYPE_DOUBLE
)
741 dst_is_double
[j
] = true;
745 if (dst_is_double
[0] || dst_is_double
[1] ||
746 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
747 glsl_to_tgsi_instruction
*dinst
= NULL
;
748 int initial_src_swz
[4], initial_src_idx
[4];
749 int initial_dst_idx
[2], initial_dst_writemask
[2];
750 /* select the writemask for dst0 or dst1 */
751 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
753 /* copy out the writemask, index and swizzles for all src/dsts. */
754 for (j
= 0; j
< 2; j
++) {
755 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
756 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
759 for (j
= 0; j
< 4; j
++) {
760 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
761 initial_src_idx
[j
] = inst
->src
[j
].index
;
765 * scan all the components in the dst writemask
766 * generate an instruction for each of them if required.
771 int i
= u_bit_scan(&writemask
);
773 /* before emitting the instruction, see if we have to adjust store
775 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
776 addr
.file
== PROGRAM_UNDEFINED
) {
777 /* We have to advance the buffer address by 16 */
778 addr
= get_temp(glsl_type::uint_type
);
779 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
780 inst
->src
[0], st_src_reg_for_int(16));
784 /* first time use previous instruction */
788 /* create a new instructions for subsequent attempts */
789 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
794 this->instructions
.push_tail(dinst
);
796 /* modify the destination if we are splitting */
797 for (j
= 0; j
< 2; j
++) {
798 if (dst_is_double
[j
]) {
799 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
800 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
802 if (dinst
->op
== TGSI_OPCODE_STORE
) {
803 dinst
->src
[0] = addr
;
805 dinst
->dst
[j
].index
++;
809 /* if we aren't writing to a double, just get the bit of the initial writemask
811 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
815 /* modify the src registers */
816 for (j
= 0; j
< 4; j
++) {
817 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
819 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
820 dinst
->src
[j
].index
= initial_src_idx
[j
];
822 dinst
->src
[j
].double_reg2
= true;
823 dinst
->src
[j
].index
++;
827 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
829 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
832 /* some opcodes are special case in what they use as sources
833 - F2D is a float src0, DLDEXP is integer src1 */
834 if (op
== TGSI_OPCODE_F2D
||
835 op
== TGSI_OPCODE_DLDEXP
||
836 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
837 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
844 this->instructions
.push_tail(inst
);
851 glsl_to_tgsi_instruction
*
852 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
854 st_src_reg src0
, st_src_reg src1
,
855 st_src_reg src2
, st_src_reg src3
)
857 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
861 * Determines whether to use an integer, unsigned integer, or float opcode
862 * based on the operands and input opcode, then emits the result.
865 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
867 st_src_reg src0
, st_src_reg src1
)
869 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
871 if (op
== TGSI_OPCODE_MOV
)
874 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
875 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
876 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
877 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
879 if (is_resource_instruction(op
))
881 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
882 type
= GLSL_TYPE_DOUBLE
;
883 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
884 type
= GLSL_TYPE_FLOAT
;
885 else if (native_integers
)
886 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
888 #define case5(c, f, i, u, d) \
889 case TGSI_OPCODE_##c: \
890 if (type == GLSL_TYPE_DOUBLE) \
891 op = TGSI_OPCODE_##d; \
892 else if (type == GLSL_TYPE_INT) \
893 op = TGSI_OPCODE_##i; \
894 else if (type == GLSL_TYPE_UINT) \
895 op = TGSI_OPCODE_##u; \
897 op = TGSI_OPCODE_##f; \
900 #define case4(c, f, i, u) \
901 case TGSI_OPCODE_##c: \
902 if (type == GLSL_TYPE_INT) \
903 op = TGSI_OPCODE_##i; \
904 else if (type == GLSL_TYPE_UINT) \
905 op = TGSI_OPCODE_##u; \
907 op = TGSI_OPCODE_##f; \
910 #define case3(f, i, u) case4(f, f, i, u)
911 #define case4d(f, i, u, d) case5(f, f, i, u, d)
912 #define case3fid(f, i, d) case5(f, f, i, i, d)
913 #define case2fi(f, i) case4(f, f, i, i)
914 #define case2iu(i, u) case4(i, LAST, i, u)
916 #define casecomp(c, f, i, u, d) \
917 case TGSI_OPCODE_##c: \
918 if (type == GLSL_TYPE_DOUBLE) \
919 op = TGSI_OPCODE_##d; \
920 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
921 op = TGSI_OPCODE_##i; \
922 else if (type == GLSL_TYPE_UINT) \
923 op = TGSI_OPCODE_##u; \
924 else if (native_integers) \
925 op = TGSI_OPCODE_##f; \
927 op = TGSI_OPCODE_##c; \
931 case3fid(ADD
, UADD
, DADD
);
932 case3fid(MUL
, UMUL
, DMUL
);
933 case3fid(MAD
, UMAD
, DMAD
);
934 case3fid(FMA
, UMAD
, DFMA
);
935 case3(DIV
, IDIV
, UDIV
);
936 case4d(MAX
, IMAX
, UMAX
, DMAX
);
937 case4d(MIN
, IMIN
, UMIN
, DMIN
);
940 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
941 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
942 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
943 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
947 case3fid(SSG
, ISSG
, DSSG
);
948 case3fid(ABS
, IABS
, DABS
);
952 case2iu(IMUL_HI
, UMUL_HI
);
954 case3fid(SQRT
, SQRT
, DSQRT
);
956 case3fid(RCP
, RCP
, DRCP
);
957 case3fid(RSQ
, RSQ
, DRSQ
);
959 case3fid(FRC
, FRC
, DFRAC
);
960 case3fid(TRUNC
, TRUNC
, DTRUNC
);
961 case3fid(CEIL
, CEIL
, DCEIL
);
962 case3fid(FLR
, FLR
, DFLR
);
963 case3fid(ROUND
, ROUND
, DROUND
);
965 case2iu(ATOMIMAX
, ATOMUMAX
);
966 case2iu(ATOMIMIN
, ATOMUMIN
);
971 assert(op
!= TGSI_OPCODE_LAST
);
975 glsl_to_tgsi_instruction
*
976 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
977 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
980 static const unsigned dot_opcodes
[] = {
981 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
984 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
988 * Emits TGSI scalar opcodes to produce unique answers across channels.
990 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
991 * channel determines the result across all channels. So to do a vec4
992 * of this operation, we want to emit a scalar per source channel used
993 * to produce dest channels.
996 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
998 st_src_reg orig_src0
, st_src_reg orig_src1
)
1001 int done_mask
= ~dst
.writemask
;
1003 /* TGSI RCP is a scalar operation splatting results to all channels,
1004 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1007 for (i
= 0; i
< 4; i
++) {
1008 GLuint this_mask
= (1 << i
);
1009 st_src_reg src0
= orig_src0
;
1010 st_src_reg src1
= orig_src1
;
1012 if (done_mask
& this_mask
)
1015 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1016 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1017 for (j
= i
+ 1; j
< 4; j
++) {
1018 /* If there is another enabled component in the destination that is
1019 * derived from the same inputs, generate its value on this pass as
1022 if (!(done_mask
& (1 << j
)) &&
1023 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1024 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1025 this_mask
|= (1 << j
);
1028 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1029 src0_swiz
, src0_swiz
);
1030 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1031 src1_swiz
, src1_swiz
);
1033 dst
.writemask
= this_mask
;
1034 emit_asm(ir
, op
, dst
, src0
, src1
);
1035 done_mask
|= this_mask
;
1040 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1041 st_dst_reg dst
, st_src_reg src0
)
1043 st_src_reg undef
= undef_src
;
1045 undef
.swizzle
= SWIZZLE_XXXX
;
1047 emit_scalar(ir
, op
, dst
, src0
, undef
);
1051 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1052 st_dst_reg dst
, st_src_reg src0
)
1054 int op
= TGSI_OPCODE_ARL
;
1056 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1057 op
= TGSI_OPCODE_UARL
;
1059 assert(dst
.file
== PROGRAM_ADDRESS
);
1060 if (dst
.index
>= this->num_address_regs
)
1061 this->num_address_regs
= dst
.index
+ 1;
1063 emit_asm(NULL
, op
, dst
, src0
);
1067 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1068 gl_constant_value values
[8], int size
, int datatype
,
1069 GLuint
*swizzle_out
)
1071 if (file
== PROGRAM_CONSTANT
) {
1072 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1073 size
, datatype
, swizzle_out
);
1076 assert(file
== PROGRAM_IMMEDIATE
);
1079 immediate_storage
*entry
;
1080 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1083 /* Search immediate storage to see if we already have an identical
1084 * immediate that we can use instead of adding a duplicate entry.
1086 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1087 immediate_storage
*tmp
= entry
;
1089 for (i
= 0; i
* 4 < size32
; i
++) {
1090 int slot_size
= MIN2(size32
- (i
* 4), 4);
1091 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1093 if (memcmp(tmp
->values
, &values
[i
* 4],
1094 slot_size
* sizeof(gl_constant_value
)))
1097 /* Everything matches, keep going until the full size is matched */
1098 tmp
= (immediate_storage
*)tmp
->next
;
1101 /* The full value matched */
1102 if (i
* 4 >= size32
)
1108 for (i
= 0; i
* 4 < size32
; i
++) {
1109 int slot_size
= MIN2(size32
- (i
* 4), 4);
1110 /* Add this immediate to the list. */
1111 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1112 this->immediates
.push_tail(entry
);
1113 this->num_immediates
++;
1119 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1121 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1122 union gl_constant_value uval
;
1125 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1131 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1133 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1134 union gl_constant_value uval
[2];
1136 uval
[0].u
= *(uint32_t *)&val
;
1137 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1138 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1144 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1146 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1147 union gl_constant_value uval
;
1149 assert(native_integers
);
1152 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1158 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1160 if (native_integers
)
1161 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1162 st_src_reg_for_int(val
);
1164 return st_src_reg_for_float(val
);
1168 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1170 return st_glsl_attrib_type_size(type
, is_vs_input
);
1174 type_size(const struct glsl_type
*type
)
1176 return st_glsl_type_size(type
);
1180 * If the given GLSL type is an array or matrix or a structure containing
1181 * an array/matrix member, return true. Else return false.
1183 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1184 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1185 * we have an array that might be indexed with a variable, we need to use
1186 * the later storage type.
1189 type_has_array_or_matrix(const glsl_type
*type
)
1191 if (type
->is_array() || type
->is_matrix())
1194 if (type
->is_record()) {
1195 for (unsigned i
= 0; i
< type
->length
; i
++) {
1196 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1207 * In the initial pass of codegen, we assign temporary numbers to
1208 * intermediate results. (not SSA -- variable assignments will reuse
1212 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1216 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1220 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1221 if (next_array
>= max_num_arrays
) {
1222 max_num_arrays
+= 32;
1223 array_sizes
= (unsigned*)
1224 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1227 src
.file
= PROGRAM_ARRAY
;
1228 src
.index
= next_array
<< 16 | 0x8000;
1229 array_sizes
[next_array
] = type_size(type
);
1233 src
.file
= PROGRAM_TEMPORARY
;
1234 src
.index
= next_temp
;
1235 next_temp
+= type_size(type
);
1238 if (type
->is_array() || type
->is_record()) {
1239 src
.swizzle
= SWIZZLE_NOOP
;
1241 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1248 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1251 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1252 if (entry
->var
== var
)
1260 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1262 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1263 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1265 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1266 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1269 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1271 const ir_state_slot
*const slots
= ir
->get_state_slots();
1272 assert(slots
!= NULL
);
1274 /* Check if this statevar's setup in the STATE file exactly
1275 * matches how we'll want to reference it as a
1276 * struct/array/whatever. If not, then we need to move it into
1277 * temporary storage and hope that it'll get copy-propagated
1280 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1281 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1286 variable_storage
*storage
;
1288 if (i
== ir
->get_num_state_slots()) {
1289 /* We'll set the index later. */
1290 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1291 this->variables
.push_tail(storage
);
1295 /* The variable_storage constructor allocates slots based on the size
1296 * of the type. However, this had better match the number of state
1297 * elements that we're going to copy into the new temporary.
1299 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1301 dst
= st_dst_reg(get_temp(ir
->type
));
1303 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1305 this->variables
.push_tail(storage
);
1309 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1310 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1311 (gl_state_index
*)slots
[i
].tokens
);
1313 if (storage
->file
== PROGRAM_STATE_VAR
) {
1314 if (storage
->index
== -1) {
1315 storage
->index
= index
;
1317 assert(index
== storage
->index
+ (int)i
);
1320 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1321 * the data being moved since MOV does not care about the type of
1322 * data it is moving, and we don't want to declare registers with
1323 * array or struct types.
1325 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1326 src
.swizzle
= slots
[i
].swizzle
;
1327 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1328 /* even a float takes up a whole vec4 reg in a struct/array. */
1333 if (storage
->file
== PROGRAM_TEMPORARY
&&
1334 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1335 fail_link(this->shader_program
,
1336 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1337 ir
->name
, dst
.index
- storage
->index
,
1338 type_size(ir
->type
));
1344 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1346 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1348 visit_exec_list(&ir
->body_instructions
, this);
1350 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1354 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1357 case ir_loop_jump::jump_break
:
1358 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1360 case ir_loop_jump::jump_continue
:
1361 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1368 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1375 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1377 /* Ignore function bodies other than main() -- we shouldn't see calls to
1378 * them since they should all be inlined before we get to glsl_to_tgsi.
1380 if (strcmp(ir
->name
, "main") == 0) {
1381 const ir_function_signature
*sig
;
1384 sig
= ir
->matching_signature(NULL
, &empty
, false);
1388 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1395 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1397 int nonmul_operand
= 1 - mul_operand
;
1399 st_dst_reg result_dst
;
1401 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1402 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1405 expr
->operands
[0]->accept(this);
1407 expr
->operands
[1]->accept(this);
1409 ir
->operands
[nonmul_operand
]->accept(this);
1412 this->result
= get_temp(ir
->type
);
1413 result_dst
= st_dst_reg(this->result
);
1414 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1415 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1421 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1423 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1424 * implemented using multiplication, and logical-or is implemented using
1425 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1426 * As result, the logical expression (a & !b) can be rewritten as:
1430 * - (a * 1) - (a * b)
1434 * This final expression can be implemented as a single MAD(a, -b, a)
1438 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1440 const int other_operand
= 1 - try_operand
;
1443 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1444 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1447 ir
->operands
[other_operand
]->accept(this);
1449 expr
->operands
[0]->accept(this);
1452 b
.negate
= ~b
.negate
;
1454 this->result
= get_temp(ir
->type
);
1455 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1461 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1462 st_src_reg
*reg
, int *num_reladdr
)
1464 if (!reg
->reladdr
&& !reg
->reladdr2
)
1467 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1468 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1470 if (*num_reladdr
!= 1) {
1471 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1473 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1481 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1483 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1485 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1487 if (ir
->operation
== ir_binop_add
) {
1488 if (try_emit_mad(ir
, 1))
1490 if (try_emit_mad(ir
, 0))
1494 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1496 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1497 if (try_emit_mad_for_and_not(ir
, 1))
1499 if (try_emit_mad_for_and_not(ir
, 0))
1503 if (ir
->operation
== ir_quadop_vector
)
1504 assert(!"ir_quadop_vector should have been lowered");
1506 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1507 this->result
.file
= PROGRAM_UNDEFINED
;
1508 ir
->operands
[operand
]->accept(this);
1509 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1510 printf("Failed to get tree for expression operand:\n");
1511 ir
->operands
[operand
]->print();
1515 op
[operand
] = this->result
;
1517 /* Matrix expression operands should have been broken down to vector
1518 * operations already.
1520 assert(!ir
->operands
[operand
]->type
->is_matrix());
1523 visit_expression(ir
, op
);
1526 /* The non-recursive part of the expression visitor lives in a separate
1527 * function and should be prevented from being inlined, to avoid a stack
1528 * explosion when deeply nested expressions are visited.
1531 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1533 st_src_reg result_src
;
1534 st_dst_reg result_dst
;
1536 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1537 if (ir
->operands
[1]) {
1538 vector_elements
= MAX2(vector_elements
,
1539 ir
->operands
[1]->type
->vector_elements
);
1542 this->result
.file
= PROGRAM_UNDEFINED
;
1544 /* Storage for our result. Ideally for an assignment we'd be using
1545 * the actual storage for the result here, instead.
1547 result_src
= get_temp(ir
->type
);
1548 /* convenience for the emit functions below. */
1549 result_dst
= st_dst_reg(result_src
);
1550 /* Limit writes to the channels that will be used by result_src later.
1551 * This does limit this temp's use as a temporary for multi-instruction
1554 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1556 switch (ir
->operation
) {
1557 case ir_unop_logic_not
:
1558 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1559 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1561 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1562 * older GPUs implement SEQ using multiple instructions (i915 uses two
1563 * SGE instructions and a MUL instruction). Since our logic values are
1564 * 0.0 and 1.0, 1-x also implements !x.
1566 op
[0].negate
= ~op
[0].negate
;
1567 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1571 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1572 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1573 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1574 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1576 op
[0].negate
= ~op
[0].negate
;
1580 case ir_unop_subroutine_to_int
:
1581 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1584 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1587 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1590 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1594 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1598 assert(!"not reached: should be handled by ir_explog_to_explog2");
1601 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1604 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1607 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1609 case ir_unop_saturate
: {
1610 glsl_to_tgsi_instruction
*inst
;
1611 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1612 inst
->saturate
= true;
1617 case ir_unop_dFdx_coarse
:
1618 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1620 case ir_unop_dFdx_fine
:
1621 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1624 case ir_unop_dFdy_coarse
:
1625 case ir_unop_dFdy_fine
:
1627 /* The X component contains 1 or -1 depending on whether the framebuffer
1628 * is a FBO or the window system buffer, respectively.
1629 * It is then multiplied with the source operand of DDY.
1631 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1632 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1634 unsigned transform_y_index
=
1635 _mesa_add_state_reference(this->prog
->Parameters
,
1638 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1640 glsl_type::vec4_type
);
1641 transform_y
.swizzle
= SWIZZLE_XXXX
;
1643 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1645 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1646 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1647 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1651 case ir_unop_frexp_sig
:
1652 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1655 case ir_unop_frexp_exp
:
1656 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1659 case ir_unop_noise
: {
1660 /* At some point, a motivated person could add a better
1661 * implementation of noise. Currently not even the nvidia
1662 * binary drivers do anything more than this. In any case, the
1663 * place to do this is in the GL state tracker, not the poor
1666 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1671 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1674 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1678 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1681 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1682 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1684 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1687 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1688 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1690 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1694 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1696 case ir_binop_greater
:
1697 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1699 case ir_binop_lequal
:
1700 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1702 case ir_binop_gequal
:
1703 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1705 case ir_binop_equal
:
1706 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1708 case ir_binop_nequal
:
1709 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1711 case ir_binop_all_equal
:
1712 /* "==" operator producing a scalar boolean. */
1713 if (ir
->operands
[0]->type
->is_vector() ||
1714 ir
->operands
[1]->type
->is_vector()) {
1715 st_src_reg temp
= get_temp(native_integers
?
1716 glsl_type::uvec4_type
:
1717 glsl_type::vec4_type
);
1719 if (native_integers
) {
1720 st_dst_reg temp_dst
= st_dst_reg(temp
);
1721 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1723 if (ir
->operands
[0]->type
->is_boolean() &&
1724 ir
->operands
[1]->as_constant() &&
1725 ir
->operands
[1]->as_constant()->is_one()) {
1726 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1728 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1731 /* Emit 1-3 AND operations to combine the SEQ results. */
1732 switch (ir
->operands
[0]->type
->vector_elements
) {
1736 temp_dst
.writemask
= WRITEMASK_Y
;
1737 temp1
.swizzle
= SWIZZLE_YYYY
;
1738 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1739 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1742 temp_dst
.writemask
= WRITEMASK_X
;
1743 temp1
.swizzle
= SWIZZLE_XXXX
;
1744 temp2
.swizzle
= SWIZZLE_YYYY
;
1745 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1746 temp_dst
.writemask
= WRITEMASK_Y
;
1747 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1748 temp2
.swizzle
= SWIZZLE_WWWW
;
1749 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1752 temp1
.swizzle
= SWIZZLE_XXXX
;
1753 temp2
.swizzle
= SWIZZLE_YYYY
;
1754 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1756 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1758 /* After the dot-product, the value will be an integer on the
1759 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1761 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1763 /* Negating the result of the dot-product gives values on the range
1764 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1765 * This is achieved using SGE.
1767 st_src_reg sge_src
= result_src
;
1768 sge_src
.negate
= ~sge_src
.negate
;
1769 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1772 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1775 case ir_binop_any_nequal
:
1776 /* "!=" operator producing a scalar boolean. */
1777 if (ir
->operands
[0]->type
->is_vector() ||
1778 ir
->operands
[1]->type
->is_vector()) {
1779 st_src_reg temp
= get_temp(native_integers
?
1780 glsl_type::uvec4_type
:
1781 glsl_type::vec4_type
);
1782 if (ir
->operands
[0]->type
->is_boolean() &&
1783 ir
->operands
[1]->as_constant() &&
1784 ir
->operands
[1]->as_constant()->is_zero()) {
1785 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1787 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1790 if (native_integers
) {
1791 st_dst_reg temp_dst
= st_dst_reg(temp
);
1792 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1794 /* Emit 1-3 OR operations to combine the SNE results. */
1795 switch (ir
->operands
[0]->type
->vector_elements
) {
1799 temp_dst
.writemask
= WRITEMASK_Y
;
1800 temp1
.swizzle
= SWIZZLE_YYYY
;
1801 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1802 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1805 temp_dst
.writemask
= WRITEMASK_X
;
1806 temp1
.swizzle
= SWIZZLE_XXXX
;
1807 temp2
.swizzle
= SWIZZLE_YYYY
;
1808 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1809 temp_dst
.writemask
= WRITEMASK_Y
;
1810 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1811 temp2
.swizzle
= SWIZZLE_WWWW
;
1812 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1815 temp1
.swizzle
= SWIZZLE_XXXX
;
1816 temp2
.swizzle
= SWIZZLE_YYYY
;
1817 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1819 /* After the dot-product, the value will be an integer on the
1820 * range [0,4]. Zero stays zero, and positive values become 1.0.
1822 glsl_to_tgsi_instruction
*const dp
=
1823 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1824 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1825 /* The clamping to [0,1] can be done for free in the fragment
1826 * shader with a saturate.
1828 dp
->saturate
= true;
1830 /* Negating the result of the dot-product gives values on the range
1831 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1832 * achieved using SLT.
1834 st_src_reg slt_src
= result_src
;
1835 slt_src
.negate
= ~slt_src
.negate
;
1836 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1840 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1844 case ir_binop_logic_xor
:
1845 if (native_integers
)
1846 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1848 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1851 case ir_binop_logic_or
: {
1852 if (native_integers
) {
1853 /* If integers are used as booleans, we can use an actual "or"
1856 assert(native_integers
);
1857 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1859 /* After the addition, the value will be an integer on the
1860 * range [0,2]. Zero stays zero, and positive values become 1.0.
1862 glsl_to_tgsi_instruction
*add
=
1863 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1864 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1865 /* The clamping to [0,1] can be done for free in the fragment
1866 * shader with a saturate if floats are being used as boolean values.
1868 add
->saturate
= true;
1870 /* Negating the result of the addition gives values on the range
1871 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1872 * is achieved using SLT.
1874 st_src_reg slt_src
= result_src
;
1875 slt_src
.negate
= ~slt_src
.negate
;
1876 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1882 case ir_binop_logic_and
:
1883 /* If native integers are disabled, the bool args are stored as float 0.0
1884 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1885 * actual AND opcode.
1887 if (native_integers
)
1888 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1890 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1894 assert(ir
->operands
[0]->type
->is_vector());
1895 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1896 emit_dp(ir
, result_dst
, op
[0], op
[1],
1897 ir
->operands
[0]->type
->vector_elements
);
1902 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1904 /* This is the only instruction sequence that makes the game "Risen"
1905 * render correctly. ABS is not required for the game, but since GLSL
1906 * declares negative values as "undefined", allowing us to do whatever
1907 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1910 emit_scalar(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1911 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, result_src
);
1912 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1916 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1919 if (native_integers
) {
1920 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1923 /* fallthrough to next case otherwise */
1925 if (native_integers
) {
1926 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1929 /* fallthrough to next case otherwise */
1932 /* Converting between signed and unsigned integers is a no-op. */
1934 result_src
.type
= result_dst
.type
;
1937 if (native_integers
) {
1938 /* Booleans are stored as integers using ~0 for true and 0 for false.
1939 * GLSL requires that int(bool) return 1 for true and 0 for false.
1940 * This conversion is done with AND, but it could be done with NEG.
1942 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1944 /* Booleans and integers are both stored as floats when native
1945 * integers are disabled.
1951 if (native_integers
)
1952 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1954 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1957 if (native_integers
)
1958 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1960 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1962 case ir_unop_bitcast_f2i
:
1964 result_src
.type
= GLSL_TYPE_INT
;
1966 case ir_unop_bitcast_f2u
:
1968 result_src
.type
= GLSL_TYPE_UINT
;
1970 case ir_unop_bitcast_i2f
:
1971 case ir_unop_bitcast_u2f
:
1973 result_src
.type
= GLSL_TYPE_FLOAT
;
1976 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1979 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1982 if (native_integers
)
1983 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1985 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1988 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1991 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1994 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1996 case ir_unop_round_even
:
1997 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2000 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2004 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2007 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2010 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2013 case ir_unop_bit_not
:
2014 if (native_integers
) {
2015 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2019 if (native_integers
) {
2020 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2023 case ir_binop_lshift
:
2024 if (native_integers
) {
2025 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2028 case ir_binop_rshift
:
2029 if (native_integers
) {
2030 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2033 case ir_binop_bit_and
:
2034 if (native_integers
) {
2035 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2038 case ir_binop_bit_xor
:
2039 if (native_integers
) {
2040 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2043 case ir_binop_bit_or
:
2044 if (native_integers
) {
2045 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2049 assert(!"GLSL 1.30 features unsupported");
2052 case ir_binop_ubo_load
: {
2053 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2054 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2055 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2056 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2057 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2060 cbuf
.type
= ir
->type
->base_type
;
2061 cbuf
.file
= PROGRAM_CONSTANT
;
2063 cbuf
.reladdr
= NULL
;
2066 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2068 if (const_offset_ir
) {
2069 /* Constant index into constant buffer */
2070 cbuf
.reladdr
= NULL
;
2071 cbuf
.index
= const_offset
/ 16;
2074 /* Relative/variable index into constant buffer */
2075 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2076 st_src_reg_for_int(4));
2077 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2078 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2081 if (const_uniform_block
) {
2082 /* Constant constant buffer */
2083 cbuf
.reladdr2
= NULL
;
2084 cbuf
.index2D
= const_block
;
2085 cbuf
.has_index2
= true;
2088 /* Relative/variable constant buffer */
2089 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2091 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2092 cbuf
.has_index2
= true;
2095 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2096 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2097 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2098 const_offset
% 16 / 8,
2099 const_offset
% 16 / 8,
2100 const_offset
% 16 / 8);
2102 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2103 const_offset
% 16 / 4,
2104 const_offset
% 16 / 4,
2105 const_offset
% 16 / 4);
2107 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2108 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2110 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2115 /* note: we have to reorder the three args here */
2116 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2119 if (this->ctx
->Const
.NativeIntegers
)
2120 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2122 op
[0].negate
= ~op
[0].negate
;
2123 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2126 case ir_triop_bitfield_extract
:
2127 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2129 case ir_quadop_bitfield_insert
:
2130 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2132 case ir_unop_bitfield_reverse
:
2133 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2135 case ir_unop_bit_count
:
2136 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2138 case ir_unop_find_msb
:
2139 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2141 case ir_unop_find_lsb
:
2142 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2144 case ir_binop_imul_high
:
2145 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2148 /* In theory, MAD is incorrect here. */
2150 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2152 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2154 case ir_unop_interpolate_at_centroid
:
2155 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2157 case ir_binop_interpolate_at_offset
: {
2158 /* The y coordinate needs to be flipped for the default fb */
2159 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2160 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2162 unsigned transform_y_index
=
2163 _mesa_add_state_reference(this->prog
->Parameters
,
2166 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2168 glsl_type::vec4_type
);
2169 transform_y
.swizzle
= SWIZZLE_XXXX
;
2171 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2172 st_dst_reg temp_dst
= st_dst_reg(temp
);
2174 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2175 temp_dst
.writemask
= WRITEMASK_Y
;
2176 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2177 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2180 case ir_binop_interpolate_at_sample
:
2181 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2185 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2188 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2191 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2194 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2197 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2200 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2202 case ir_unop_unpack_double_2x32
:
2203 case ir_unop_pack_double_2x32
:
2204 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2207 case ir_binop_ldexp
:
2208 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2209 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2211 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2215 case ir_unop_pack_half_2x16
:
2216 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2218 case ir_unop_unpack_half_2x16
:
2219 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2222 case ir_unop_get_buffer_size
: {
2223 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2226 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2227 (const_offset
? const_offset
->value
.u
[0] : 0),
2229 if (!const_offset
) {
2230 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2231 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
2232 emit_arl(ir
, sampler_reladdr
, op
[0]);
2234 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2238 case ir_unop_vote_any
:
2239 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2241 case ir_unop_vote_all
:
2242 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2244 case ir_unop_vote_eq
:
2245 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2248 case ir_unop_pack_snorm_2x16
:
2249 case ir_unop_pack_unorm_2x16
:
2250 case ir_unop_pack_snorm_4x8
:
2251 case ir_unop_pack_unorm_4x8
:
2253 case ir_unop_unpack_snorm_2x16
:
2254 case ir_unop_unpack_unorm_2x16
:
2255 case ir_unop_unpack_snorm_4x8
:
2256 case ir_unop_unpack_unorm_4x8
:
2258 case ir_quadop_vector
:
2259 case ir_binop_vector_extract
:
2260 case ir_triop_vector_insert
:
2261 case ir_binop_carry
:
2262 case ir_binop_borrow
:
2263 case ir_unop_ssbo_unsized_array_length
:
2264 /* This operation is not supported, or should have already been handled.
2266 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2270 this->result
= result_src
;
2275 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2281 /* Note that this is only swizzles in expressions, not those on the left
2282 * hand side of an assignment, which do write masking. See ir_assignment
2286 ir
->val
->accept(this);
2288 assert(src
.file
!= PROGRAM_UNDEFINED
);
2289 assert(ir
->type
->vector_elements
> 0);
2291 for (i
= 0; i
< 4; i
++) {
2292 if (i
< ir
->type
->vector_elements
) {
2295 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2298 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2301 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2304 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2308 /* If the type is smaller than a vec4, replicate the last
2311 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2315 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2320 /* Test if the variable is an array. Note that geometry and
2321 * tessellation shader inputs are outputs are always arrays (except
2322 * for patch inputs), so only the array element type is considered.
2325 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2327 const glsl_type
*type
= var
->type
;
2329 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2330 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2335 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2336 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2337 stage
== MESA_SHADER_TESS_CTRL
) &&
2339 if (!var
->type
->is_array())
2340 return false; /* a system value probably */
2342 type
= var
->type
->fields
.array
;
2346 return type
->is_array() || type
->is_matrix();
2350 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2352 variable_storage
*entry
= find_variable_storage(ir
->var
);
2353 ir_variable
*var
= ir
->var
;
2357 switch (var
->data
.mode
) {
2358 case ir_var_uniform
:
2359 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2360 var
->data
.param_index
);
2361 this->variables
.push_tail(entry
);
2363 case ir_var_shader_in
:
2364 /* The linker assigns locations for varyings and attributes,
2365 * including deprecated builtins (like gl_Color), user-assign
2366 * generic attributes (glBindVertexLocation), and
2367 * user-defined varyings.
2369 assert(var
->data
.location
!= -1);
2371 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2372 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2374 decl
->mesa_index
= var
->data
.location
;
2375 decl
->array_id
= num_input_arrays
+ 1;
2377 decl
->array_size
= type_size(var
->type
->fields
.array
);
2378 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2380 decl
->array_size
= type_size(var
->type
);
2381 decl
->array_type
= var
->type
->without_array()->base_type
;
2385 entry
= new(mem_ctx
) variable_storage(var
,
2391 entry
= new(mem_ctx
) variable_storage(var
,
2393 var
->data
.location
);
2395 this->variables
.push_tail(entry
);
2397 case ir_var_shader_out
:
2398 assert(var
->data
.location
!= -1);
2400 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2401 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2403 decl
->mesa_index
= var
->data
.location
;
2404 decl
->array_id
= num_output_arrays
+ 1;
2406 decl
->array_size
= type_size(var
->type
->fields
.array
);
2407 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2409 decl
->array_size
= type_size(var
->type
);
2410 decl
->array_type
= var
->type
->without_array()->base_type
;
2412 num_output_arrays
++;
2414 entry
= new(mem_ctx
) variable_storage(var
,
2420 entry
= new(mem_ctx
) variable_storage(var
,
2425 this->variables
.push_tail(entry
);
2427 case ir_var_system_value
:
2428 entry
= new(mem_ctx
) variable_storage(var
,
2429 PROGRAM_SYSTEM_VALUE
,
2430 var
->data
.location
);
2433 case ir_var_temporary
:
2434 st_src_reg src
= get_temp(var
->type
);
2436 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2437 this->variables
.push_tail(entry
);
2443 printf("Failed to make storage for %s\n", var
->name
);
2448 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2449 this->result
.array_id
= entry
->array_id
;
2450 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2451 this->result
.is_double_vertex_input
= true;
2452 if (!native_integers
)
2453 this->result
.type
= GLSL_TYPE_FLOAT
;
2457 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2458 GLbitfield64 usage_mask
,
2459 GLbitfield64 double_usage_mask
,
2460 GLbitfield patch_usage_mask
)
2465 /* Fix array declarations by removing unused array elements at both ends
2466 * of the arrays. For example, mat4[3] where only mat[1] is used.
2468 for (i
= 0; i
< count
; i
++) {
2469 struct array_decl
*decl
= &arrays
[i
];
2471 /* Shrink the beginning. */
2472 for (j
= 0; j
< (int)decl
->array_size
; j
++) {
2473 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2474 if (patch_usage_mask
&
2475 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2479 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2481 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2490 /* Shrink the end. */
2491 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2492 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2493 if (patch_usage_mask
&
2494 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2498 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2500 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2510 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2514 int element_size
= type_size(ir
->type
);
2517 index
= ir
->array_index
->constant_expression_value();
2519 ir
->array
->accept(this);
2522 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2523 switch (this->prog
->Target
) {
2524 case GL_TESS_CONTROL_PROGRAM_NV
:
2525 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2526 !ir
->variable_referenced()->data
.patch
;
2528 case GL_TESS_EVALUATION_PROGRAM_NV
:
2529 is_2D
= src
.file
== PROGRAM_INPUT
&&
2530 !ir
->variable_referenced()->data
.patch
;
2532 case GL_GEOMETRY_PROGRAM_NV
:
2533 is_2D
= src
.file
== PROGRAM_INPUT
;
2543 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2544 src
.file
== PROGRAM_INPUT
)
2545 element_size
= attrib_type_size(ir
->type
, true);
2547 src
.index2D
= index
->value
.i
[0];
2548 src
.has_index2
= true;
2550 src
.index
+= index
->value
.i
[0] * element_size
;
2552 /* Variable index array dereference. It eats the "vec4" of the
2553 * base of the array and an index that offsets the TGSI register
2556 ir
->array_index
->accept(this);
2558 st_src_reg index_reg
;
2560 if (element_size
== 1) {
2561 index_reg
= this->result
;
2563 index_reg
= get_temp(native_integers
?
2564 glsl_type::int_type
: glsl_type::float_type
);
2566 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2567 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2570 /* If there was already a relative address register involved, add the
2571 * new and the old together to get the new offset.
2573 if (!is_2D
&& src
.reladdr
!= NULL
) {
2574 st_src_reg accum_reg
= get_temp(native_integers
?
2575 glsl_type::int_type
: glsl_type::float_type
);
2577 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2578 index_reg
, *src
.reladdr
);
2580 index_reg
= accum_reg
;
2584 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2585 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2587 src
.has_index2
= true;
2589 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2590 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2594 /* If the type is smaller than a vec4, replicate the last channel out. */
2595 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2596 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2598 src
.swizzle
= SWIZZLE_NOOP
;
2600 /* Change the register type to the element type of the array. */
2601 src
.type
= ir
->type
->base_type
;
2607 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2610 const glsl_type
*struct_type
= ir
->record
->type
;
2613 ir
->record
->accept(this);
2615 for (i
= 0; i
< struct_type
->length
; i
++) {
2616 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2618 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2621 /* If the type is smaller than a vec4, replicate the last channel out. */
2622 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2623 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2625 this->result
.swizzle
= SWIZZLE_NOOP
;
2627 this->result
.index
+= offset
;
2628 this->result
.type
= ir
->type
->base_type
;
2632 * We want to be careful in assignment setup to hit the actual storage
2633 * instead of potentially using a temporary like we might with the
2634 * ir_dereference handler.
2637 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2639 /* The LHS must be a dereference. If the LHS is a variable indexed array
2640 * access of a vector, it must be separated into a series conditional moves
2641 * before reaching this point (see ir_vec_index_to_cond_assign).
2643 assert(ir
->as_dereference());
2644 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2646 assert(!deref_array
->array
->type
->is_vector());
2649 /* Use the rvalue deref handler for the most part. We'll ignore
2650 * swizzles in it and write swizzles using writemask, though.
2653 return st_dst_reg(v
->result
);
2657 * Process the condition of a conditional assignment
2659 * Examines the condition of a conditional assignment to generate the optimal
2660 * first operand of a \c CMP instruction. If the condition is a relational
2661 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2662 * used as the source for the \c CMP instruction. Otherwise the comparison
2663 * is processed to a boolean result, and the boolean result is used as the
2664 * operand to the CMP instruction.
2667 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2669 ir_rvalue
*src_ir
= ir
;
2671 bool switch_order
= false;
2673 ir_expression
*const expr
= ir
->as_expression();
2675 if (native_integers
) {
2676 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2677 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2678 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2679 type
== GLSL_TYPE_BOOL
) {
2680 if (expr
->operation
== ir_binop_equal
) {
2681 if (expr
->operands
[0]->is_zero()) {
2682 src_ir
= expr
->operands
[1];
2683 switch_order
= true;
2685 else if (expr
->operands
[1]->is_zero()) {
2686 src_ir
= expr
->operands
[0];
2687 switch_order
= true;
2690 else if (expr
->operation
== ir_binop_nequal
) {
2691 if (expr
->operands
[0]->is_zero()) {
2692 src_ir
= expr
->operands
[1];
2694 else if (expr
->operands
[1]->is_zero()) {
2695 src_ir
= expr
->operands
[0];
2701 src_ir
->accept(this);
2702 return switch_order
;
2705 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2706 bool zero_on_left
= false;
2708 if (expr
->operands
[0]->is_zero()) {
2709 src_ir
= expr
->operands
[1];
2710 zero_on_left
= true;
2711 } else if (expr
->operands
[1]->is_zero()) {
2712 src_ir
= expr
->operands
[0];
2713 zero_on_left
= false;
2717 * (a < 0) T F F ( a < 0) T F F
2718 * (0 < a) F F T (-a < 0) F F T
2719 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2720 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2721 * (a > 0) F F T (-a < 0) F F T
2722 * (0 > a) T F F ( a < 0) T F F
2723 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2724 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2726 * Note that exchanging the order of 0 and 'a' in the comparison simply
2727 * means that the value of 'a' should be negated.
2730 switch (expr
->operation
) {
2732 switch_order
= false;
2733 negate
= zero_on_left
;
2736 case ir_binop_greater
:
2737 switch_order
= false;
2738 negate
= !zero_on_left
;
2741 case ir_binop_lequal
:
2742 switch_order
= true;
2743 negate
= !zero_on_left
;
2746 case ir_binop_gequal
:
2747 switch_order
= true;
2748 negate
= zero_on_left
;
2752 /* This isn't the right kind of comparison afterall, so make sure
2753 * the whole condition is visited.
2761 src_ir
->accept(this);
2763 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2764 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2765 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2766 * computing the condition.
2769 this->result
.negate
= ~this->result
.negate
;
2771 return switch_order
;
2775 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2776 st_dst_reg
*l
, st_src_reg
*r
,
2777 st_src_reg
*cond
, bool cond_swap
)
2779 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2780 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2781 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2787 if (type
->is_array()) {
2788 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2789 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2794 if (type
->is_matrix()) {
2795 const struct glsl_type
*vec_type
;
2797 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2798 type
->vector_elements
, 1);
2800 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2801 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2806 assert(type
->is_scalar() || type
->is_vector());
2808 r
->type
= type
->base_type
;
2810 st_src_reg l_src
= st_src_reg(*l
);
2811 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2813 if (native_integers
) {
2814 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2815 cond_swap
? l_src
: *r
,
2816 cond_swap
? *r
: l_src
);
2818 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2819 cond_swap
? l_src
: *r
,
2820 cond_swap
? *r
: l_src
);
2823 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2827 if (type
->is_dual_slot_double()) {
2829 if (r
->is_double_vertex_input
== false)
2835 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2840 ir
->rhs
->accept(this);
2843 l
= get_assignment_lhs(ir
->lhs
, this);
2845 /* FINISHME: This should really set to the correct maximal writemask for each
2846 * FINISHME: component written (in the loops below). This case can only
2847 * FINISHME: occur for matrices, arrays, and structures.
2849 if (ir
->write_mask
== 0) {
2850 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2852 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2853 if (ir
->lhs
->type
->without_array()->is_double()) {
2854 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2856 l
.writemask
= WRITEMASK_X
;
2859 l
.writemask
= WRITEMASK_XY
;
2862 l
.writemask
= WRITEMASK_XYZ
;
2865 l
.writemask
= WRITEMASK_XYZW
;
2869 l
.writemask
= WRITEMASK_XYZW
;
2871 } else if (ir
->lhs
->type
->is_scalar() &&
2872 !ir
->lhs
->type
->is_double() &&
2873 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2874 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2875 * FINISHME: W component of fragment shader output zero, work correctly.
2877 l
.writemask
= WRITEMASK_XYZW
;
2880 int first_enabled_chan
= 0;
2883 l
.writemask
= ir
->write_mask
;
2885 for (int i
= 0; i
< 4; i
++) {
2886 if (l
.writemask
& (1 << i
)) {
2887 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2892 /* Swizzle a small RHS vector into the channels being written.
2894 * glsl ir treats write_mask as dictating how many channels are
2895 * present on the RHS while TGSI treats write_mask as just
2896 * showing which channels of the vec4 RHS get written.
2898 for (int i
= 0; i
< 4; i
++) {
2899 if (l
.writemask
& (1 << i
))
2900 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2902 swizzles
[i
] = first_enabled_chan
;
2904 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2905 swizzles
[2], swizzles
[3]);
2908 assert(l
.file
!= PROGRAM_UNDEFINED
);
2909 assert(r
.file
!= PROGRAM_UNDEFINED
);
2911 if (ir
->condition
) {
2912 const bool switch_order
= this->process_move_condition(ir
->condition
);
2913 st_src_reg condition
= this->result
;
2915 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2916 } else if (ir
->rhs
->as_expression() &&
2917 this->instructions
.get_tail() &&
2918 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2919 type_size(ir
->lhs
->type
) == 1 &&
2920 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2921 /* To avoid emitting an extra MOV when assigning an expression to a
2922 * variable, emit the last instruction of the expression again, but
2923 * replace the destination register with the target of the assignment.
2924 * Dead code elimination will remove the original instruction.
2926 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2927 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2928 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2929 new_inst
->saturate
= inst
->saturate
;
2930 inst
->dead_mask
= inst
->dst
[0].writemask
;
2932 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2938 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2941 GLdouble stack_vals
[4] = { 0 };
2942 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2943 GLenum gl_type
= GL_NONE
;
2945 static int in_array
= 0;
2946 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2948 /* Unfortunately, 4 floats is all we can get into
2949 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2950 * aggregate constant and move each constant value into it. If we
2951 * get lucky, copy propagation will eliminate the extra moves.
2953 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2954 st_src_reg temp_base
= get_temp(ir
->type
);
2955 st_dst_reg temp
= st_dst_reg(temp_base
);
2957 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2958 int size
= type_size(field_value
->type
);
2962 field_value
->accept(this);
2965 for (i
= 0; i
< (unsigned int)size
; i
++) {
2966 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2972 this->result
= temp_base
;
2976 if (ir
->type
->is_array()) {
2977 st_src_reg temp_base
= get_temp(ir
->type
);
2978 st_dst_reg temp
= st_dst_reg(temp_base
);
2979 int size
= type_size(ir
->type
->fields
.array
);
2984 for (i
= 0; i
< ir
->type
->length
; i
++) {
2985 ir
->array_elements
[i
]->accept(this);
2987 for (int j
= 0; j
< size
; j
++) {
2988 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2994 this->result
= temp_base
;
2999 if (ir
->type
->is_matrix()) {
3000 st_src_reg mat
= get_temp(ir
->type
);
3001 st_dst_reg mat_column
= st_dst_reg(mat
);
3003 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3004 switch (ir
->type
->base_type
) {
3005 case GLSL_TYPE_FLOAT
:
3006 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3008 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3009 src
.index
= add_constant(file
,
3011 ir
->type
->vector_elements
,
3014 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3016 case GLSL_TYPE_DOUBLE
:
3017 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3018 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3019 src
.index
= add_constant(file
,
3021 ir
->type
->vector_elements
,
3024 if (ir
->type
->vector_elements
>= 2) {
3025 mat_column
.writemask
= WRITEMASK_XY
;
3026 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3027 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3029 mat_column
.writemask
= WRITEMASK_X
;
3030 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3031 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3034 if (ir
->type
->vector_elements
> 2) {
3035 if (ir
->type
->vector_elements
== 4) {
3036 mat_column
.writemask
= WRITEMASK_ZW
;
3037 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3038 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3040 mat_column
.writemask
= WRITEMASK_Z
;
3041 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3042 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3043 mat_column
.writemask
= WRITEMASK_XYZW
;
3044 src
.swizzle
= SWIZZLE_XYZW
;
3050 unreachable("Illegal matrix constant type.\n");
3059 switch (ir
->type
->base_type
) {
3060 case GLSL_TYPE_FLOAT
:
3062 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3063 values
[i
].f
= ir
->value
.f
[i
];
3066 case GLSL_TYPE_DOUBLE
:
3067 gl_type
= GL_DOUBLE
;
3068 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3069 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3070 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3073 case GLSL_TYPE_UINT
:
3074 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3075 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3076 if (native_integers
)
3077 values
[i
].u
= ir
->value
.u
[i
];
3079 values
[i
].f
= ir
->value
.u
[i
];
3083 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3084 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3085 if (native_integers
)
3086 values
[i
].i
= ir
->value
.i
[i
];
3088 values
[i
].f
= ir
->value
.i
[i
];
3091 case GLSL_TYPE_BOOL
:
3092 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3093 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3094 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3098 assert(!"Non-float/uint/int/bool constant");
3101 this->result
= st_src_reg(file
, -1, ir
->type
);
3102 this->result
.index
= add_constant(file
,
3104 ir
->type
->vector_elements
,
3106 &this->result
.swizzle
);
3110 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3112 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3113 if (entry
->sig
== sig
)
3117 entry
= ralloc(mem_ctx
, function_entry
);
3119 entry
->sig_id
= this->next_signature_id
++;
3120 entry
->bgn_inst
= NULL
;
3122 /* Allocate storage for all the parameters. */
3123 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3124 variable_storage
*storage
;
3126 storage
= find_variable_storage(param
);
3129 st_src_reg src
= get_temp(param
->type
);
3131 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3132 this->variables
.push_tail(storage
);
3135 if (!sig
->return_type
->is_void()) {
3136 entry
->return_reg
= get_temp(sig
->return_type
);
3138 entry
->return_reg
= undef_src
;
3141 this->function_signatures
.push_tail(entry
);
3146 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3148 const char *callee
= ir
->callee
->function_name();
3149 exec_node
*param
= ir
->actual_parameters
.get_head();
3150 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3151 ir_variable
*location
= deref
->variable_referenced();
3154 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3156 /* Calculate the surface offset */
3158 unsigned array_size
= 0, base
= 0, index
= 0;
3160 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
);
3162 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3163 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3164 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3165 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3166 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3168 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3171 ir
->return_deref
->accept(this);
3172 st_dst_reg
dst(this->result
);
3173 dst
.writemask
= WRITEMASK_X
;
3175 glsl_to_tgsi_instruction
*inst
;
3177 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3178 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3179 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3180 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3181 st_src_reg_for_int(1));
3182 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3183 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3184 st_src_reg_for_int(-1));
3185 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3187 param
= param
->get_next();
3188 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3191 st_src_reg data
= this->result
, data2
= undef_src
;
3193 if (!strcmp("__intrinsic_atomic_add", callee
))
3194 opcode
= TGSI_OPCODE_ATOMUADD
;
3195 else if (!strcmp("__intrinsic_atomic_min", callee
))
3196 opcode
= TGSI_OPCODE_ATOMIMIN
;
3197 else if (!strcmp("__intrinsic_atomic_max", callee
))
3198 opcode
= TGSI_OPCODE_ATOMIMAX
;
3199 else if (!strcmp("__intrinsic_atomic_and", callee
))
3200 opcode
= TGSI_OPCODE_ATOMAND
;
3201 else if (!strcmp("__intrinsic_atomic_or", callee
))
3202 opcode
= TGSI_OPCODE_ATOMOR
;
3203 else if (!strcmp("__intrinsic_atomic_xor", callee
))
3204 opcode
= TGSI_OPCODE_ATOMXOR
;
3205 else if (!strcmp("__intrinsic_atomic_exchange", callee
))
3206 opcode
= TGSI_OPCODE_ATOMXCHG
;
3207 else if (!strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3208 opcode
= TGSI_OPCODE_ATOMCAS
;
3209 param
= param
->get_next();
3210 val
= ((ir_instruction
*)param
)->as_rvalue();
3212 data2
= this->result
;
3213 } else if (!strcmp("__intrinsic_atomic_sub", callee
)) {
3214 opcode
= TGSI_OPCODE_ATOMUADD
;
3215 st_src_reg res
= get_temp(glsl_type::uvec4_type
);
3216 st_dst_reg dstres
= st_dst_reg(res
);
3217 dstres
.writemask
= dst
.writemask
;
3218 emit_asm(ir
, TGSI_OPCODE_INEG
, dstres
, data
);
3221 assert(!"Unexpected intrinsic");
3225 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3228 inst
->buffer
= buffer
;
3232 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3234 const char *callee
= ir
->callee
->function_name();
3235 exec_node
*param
= ir
->actual_parameters
.get_head();
3237 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3239 param
= param
->get_next();
3240 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3242 ir_constant
*const_block
= block
->as_constant();
3246 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3247 (const_block
? const_block
->value
.u
[0] : 0),
3251 block
->accept(this);
3252 emit_arl(ir
, sampler_reladdr
, this->result
);
3253 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3254 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3257 /* Calculate the surface offset */
3258 offset
->accept(this);
3259 st_src_reg off
= this->result
;
3261 st_dst_reg dst
= undef_dst
;
3262 if (ir
->return_deref
) {
3263 ir
->return_deref
->accept(this);
3264 dst
= st_dst_reg(this->result
);
3265 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3268 glsl_to_tgsi_instruction
*inst
;
3270 if (!strcmp("__intrinsic_load_ssbo", callee
)) {
3271 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3272 if (dst
.type
== GLSL_TYPE_BOOL
)
3273 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3274 } else if (!strcmp("__intrinsic_store_ssbo", callee
)) {
3275 param
= param
->get_next();
3276 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3279 param
= param
->get_next();
3280 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3282 dst
.writemask
= write_mask
->value
.u
[0];
3284 dst
.type
= this->result
.type
;
3285 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3287 param
= param
->get_next();
3288 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3291 st_src_reg data
= this->result
, data2
= undef_src
;
3293 if (!strcmp("__intrinsic_atomic_add_ssbo", callee
))
3294 opcode
= TGSI_OPCODE_ATOMUADD
;
3295 else if (!strcmp("__intrinsic_atomic_min_ssbo", callee
))
3296 opcode
= TGSI_OPCODE_ATOMIMIN
;
3297 else if (!strcmp("__intrinsic_atomic_max_ssbo", callee
))
3298 opcode
= TGSI_OPCODE_ATOMIMAX
;
3299 else if (!strcmp("__intrinsic_atomic_and_ssbo", callee
))
3300 opcode
= TGSI_OPCODE_ATOMAND
;
3301 else if (!strcmp("__intrinsic_atomic_or_ssbo", callee
))
3302 opcode
= TGSI_OPCODE_ATOMOR
;
3303 else if (!strcmp("__intrinsic_atomic_xor_ssbo", callee
))
3304 opcode
= TGSI_OPCODE_ATOMXOR
;
3305 else if (!strcmp("__intrinsic_atomic_exchange_ssbo", callee
))
3306 opcode
= TGSI_OPCODE_ATOMXCHG
;
3307 else if (!strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3308 opcode
= TGSI_OPCODE_ATOMCAS
;
3309 param
= param
->get_next();
3310 val
= ((ir_instruction
*)param
)->as_rvalue();
3312 data2
= this->result
;
3314 assert(!"Unexpected intrinsic");
3318 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3321 param
= param
->get_next();
3322 ir_constant
*access
= NULL
;
3323 if (!param
->is_tail_sentinel()) {
3324 access
= ((ir_instruction
*)param
)->as_constant();
3328 /* The emit_asm() might have actually split the op into pieces, e.g. for
3329 * double stores. We have to go back and fix up all the generated ops.
3331 unsigned op
= inst
->op
;
3333 inst
->buffer
= buffer
;
3335 inst
->buffer_access
= access
->value
.u
[0];
3336 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3337 if (inst
->op
== TGSI_OPCODE_UADD
)
3338 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3339 } while (inst
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
&& inst
->op
== op
);
3343 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3345 const char *callee
= ir
->callee
->function_name();
3347 if (!strcmp("__intrinsic_memory_barrier", callee
))
3348 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3349 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3350 TGSI_MEMBAR_ATOMIC_BUFFER
|
3351 TGSI_MEMBAR_SHADER_IMAGE
|
3352 TGSI_MEMBAR_SHARED
));
3353 else if (!strcmp("__intrinsic_memory_barrier_atomic_counter", callee
))
3354 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3355 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3356 else if (!strcmp("__intrinsic_memory_barrier_buffer", callee
))
3357 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3358 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3359 else if (!strcmp("__intrinsic_memory_barrier_image", callee
))
3360 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3361 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3362 else if (!strcmp("__intrinsic_memory_barrier_shared", callee
))
3363 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3364 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3365 else if (!strcmp("__intrinsic_group_memory_barrier", callee
))
3366 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3367 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3368 TGSI_MEMBAR_ATOMIC_BUFFER
|
3369 TGSI_MEMBAR_SHADER_IMAGE
|
3370 TGSI_MEMBAR_SHARED
|
3371 TGSI_MEMBAR_THREAD_GROUP
));
3373 assert(!"Unexpected memory barrier intrinsic");
3377 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3379 const char *callee
= ir
->callee
->function_name();
3380 exec_node
*param
= ir
->actual_parameters
.get_head();
3382 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3384 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3386 /* Calculate the surface offset */
3387 offset
->accept(this);
3388 st_src_reg off
= this->result
;
3390 st_dst_reg dst
= undef_dst
;
3391 if (ir
->return_deref
) {
3392 ir
->return_deref
->accept(this);
3393 dst
= st_dst_reg(this->result
);
3394 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3397 glsl_to_tgsi_instruction
*inst
;
3399 if (!strcmp("__intrinsic_load_shared", callee
)) {
3400 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3401 inst
->buffer
= buffer
;
3402 } else if (!strcmp("__intrinsic_store_shared", callee
)) {
3403 param
= param
->get_next();
3404 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3407 param
= param
->get_next();
3408 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3410 dst
.writemask
= write_mask
->value
.u
[0];
3412 dst
.type
= this->result
.type
;
3413 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3414 inst
->buffer
= buffer
;
3416 param
= param
->get_next();
3417 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3420 st_src_reg data
= this->result
, data2
= undef_src
;
3422 if (!strcmp("__intrinsic_atomic_add_shared", callee
))
3423 opcode
= TGSI_OPCODE_ATOMUADD
;
3424 else if (!strcmp("__intrinsic_atomic_min_shared", callee
))
3425 opcode
= TGSI_OPCODE_ATOMIMIN
;
3426 else if (!strcmp("__intrinsic_atomic_max_shared", callee
))
3427 opcode
= TGSI_OPCODE_ATOMIMAX
;
3428 else if (!strcmp("__intrinsic_atomic_and_shared", callee
))
3429 opcode
= TGSI_OPCODE_ATOMAND
;
3430 else if (!strcmp("__intrinsic_atomic_or_shared", callee
))
3431 opcode
= TGSI_OPCODE_ATOMOR
;
3432 else if (!strcmp("__intrinsic_atomic_xor_shared", callee
))
3433 opcode
= TGSI_OPCODE_ATOMXOR
;
3434 else if (!strcmp("__intrinsic_atomic_exchange_shared", callee
))
3435 opcode
= TGSI_OPCODE_ATOMXCHG
;
3436 else if (!strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3437 opcode
= TGSI_OPCODE_ATOMCAS
;
3438 param
= param
->get_next();
3439 val
= ((ir_instruction
*)param
)->as_rvalue();
3441 data2
= this->result
;
3443 assert(!"Unexpected intrinsic");
3447 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3448 inst
->buffer
= buffer
;
3453 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3455 const char *callee
= ir
->callee
->function_name();
3456 exec_node
*param
= ir
->actual_parameters
.get_head();
3458 ir_dereference
*img
= (ir_dereference
*)param
;
3459 const ir_variable
*imgvar
= img
->variable_referenced();
3460 const glsl_type
*type
= imgvar
->type
->without_array();
3461 unsigned sampler_array_size
= 1, sampler_base
= 0;
3464 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3466 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3467 (unsigned int *)&image
.index
, &reladdr
);
3468 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3469 emit_arl(ir
, sampler_reladdr
, reladdr
);
3470 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3471 memcpy(image
.reladdr
, &sampler_reladdr
, sizeof(reladdr
));
3474 st_dst_reg dst
= undef_dst
;
3475 if (ir
->return_deref
) {
3476 ir
->return_deref
->accept(this);
3477 dst
= st_dst_reg(this->result
);
3478 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3481 glsl_to_tgsi_instruction
*inst
;
3483 if (!strcmp("__intrinsic_image_size", callee
)) {
3484 dst
.writemask
= WRITEMASK_XYZ
;
3485 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3486 } else if (!strcmp("__intrinsic_image_samples", callee
)) {
3487 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3488 st_dst_reg dstres
= st_dst_reg(res
);
3489 dstres
.writemask
= WRITEMASK_W
;
3490 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3491 res
.swizzle
= SWIZZLE_WWWW
;
3492 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3494 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3496 st_dst_reg coord_dst
;
3497 coord
= get_temp(glsl_type::ivec4_type
);
3498 coord_dst
= st_dst_reg(coord
);
3499 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3500 param
= param
->get_next();
3501 ((ir_dereference
*)param
)->accept(this);
3502 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3503 coord
.swizzle
= SWIZZLE_XXXX
;
3504 switch (type
->coordinate_components()) {
3505 case 4: assert(!"unexpected coord count");
3507 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3509 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3512 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3513 param
= param
->get_next();
3514 ((ir_dereference
*)param
)->accept(this);
3515 st_src_reg sample
= this->result
;
3516 sample
.swizzle
= SWIZZLE_XXXX
;
3517 coord_dst
.writemask
= WRITEMASK_W
;
3518 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3519 coord
.swizzle
|= SWIZZLE_W
<< 9;
3522 param
= param
->get_next();
3523 if (!param
->is_tail_sentinel()) {
3524 ((ir_dereference
*)param
)->accept(this);
3525 arg1
= this->result
;
3526 param
= param
->get_next();
3529 if (!param
->is_tail_sentinel()) {
3530 ((ir_dereference
*)param
)->accept(this);
3531 arg2
= this->result
;
3532 param
= param
->get_next();
3535 assert(param
->is_tail_sentinel());
3538 if (!strcmp("__intrinsic_image_load", callee
))
3539 opcode
= TGSI_OPCODE_LOAD
;
3540 else if (!strcmp("__intrinsic_image_store", callee
))
3541 opcode
= TGSI_OPCODE_STORE
;
3542 else if (!strcmp("__intrinsic_image_atomic_add", callee
))
3543 opcode
= TGSI_OPCODE_ATOMUADD
;
3544 else if (!strcmp("__intrinsic_image_atomic_min", callee
))
3545 opcode
= TGSI_OPCODE_ATOMIMIN
;
3546 else if (!strcmp("__intrinsic_image_atomic_max", callee
))
3547 opcode
= TGSI_OPCODE_ATOMIMAX
;
3548 else if (!strcmp("__intrinsic_image_atomic_and", callee
))
3549 opcode
= TGSI_OPCODE_ATOMAND
;
3550 else if (!strcmp("__intrinsic_image_atomic_or", callee
))
3551 opcode
= TGSI_OPCODE_ATOMOR
;
3552 else if (!strcmp("__intrinsic_image_atomic_xor", callee
))
3553 opcode
= TGSI_OPCODE_ATOMXOR
;
3554 else if (!strcmp("__intrinsic_image_atomic_exchange", callee
))
3555 opcode
= TGSI_OPCODE_ATOMXCHG
;
3556 else if (!strcmp("__intrinsic_image_atomic_comp_swap", callee
))
3557 opcode
= TGSI_OPCODE_ATOMCAS
;
3559 assert(!"Unexpected intrinsic");
3563 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3564 if (opcode
== TGSI_OPCODE_STORE
)
3565 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3568 inst
->buffer
= image
;
3569 inst
->sampler_array_size
= sampler_array_size
;
3570 inst
->sampler_base
= sampler_base
;
3572 switch (type
->sampler_dimensionality
) {
3573 case GLSL_SAMPLER_DIM_1D
:
3574 inst
->tex_target
= (type
->sampler_array
)
3575 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3577 case GLSL_SAMPLER_DIM_2D
:
3578 inst
->tex_target
= (type
->sampler_array
)
3579 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3581 case GLSL_SAMPLER_DIM_3D
:
3582 inst
->tex_target
= TEXTURE_3D_INDEX
;
3584 case GLSL_SAMPLER_DIM_CUBE
:
3585 inst
->tex_target
= (type
->sampler_array
)
3586 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3588 case GLSL_SAMPLER_DIM_RECT
:
3589 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3591 case GLSL_SAMPLER_DIM_BUF
:
3592 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3594 case GLSL_SAMPLER_DIM_EXTERNAL
:
3595 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3597 case GLSL_SAMPLER_DIM_MS
:
3598 inst
->tex_target
= (type
->sampler_array
)
3599 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3602 assert(!"Should not get here.");
3605 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3606 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3608 if (imgvar
->data
.image_coherent
)
3609 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3610 if (imgvar
->data
.image_restrict
)
3611 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3612 if (imgvar
->data
.image_volatile
)
3613 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3617 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3619 glsl_to_tgsi_instruction
*call_inst
;
3620 ir_function_signature
*sig
= ir
->callee
;
3621 const char *callee
= sig
->function_name();
3622 function_entry
*entry
;
3625 /* Filter out intrinsics */
3626 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3627 !strcmp("__intrinsic_atomic_increment", callee
) ||
3628 !strcmp("__intrinsic_atomic_predecrement", callee
) ||
3629 !strcmp("__intrinsic_atomic_add", callee
) ||
3630 !strcmp("__intrinsic_atomic_sub", callee
) ||
3631 !strcmp("__intrinsic_atomic_min", callee
) ||
3632 !strcmp("__intrinsic_atomic_max", callee
) ||
3633 !strcmp("__intrinsic_atomic_and", callee
) ||
3634 !strcmp("__intrinsic_atomic_or", callee
) ||
3635 !strcmp("__intrinsic_atomic_xor", callee
) ||
3636 !strcmp("__intrinsic_atomic_exchange", callee
) ||
3637 !strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3638 visit_atomic_counter_intrinsic(ir
);
3642 if (!strcmp("__intrinsic_load_ssbo", callee
) ||
3643 !strcmp("__intrinsic_store_ssbo", callee
) ||
3644 !strcmp("__intrinsic_atomic_add_ssbo", callee
) ||
3645 !strcmp("__intrinsic_atomic_min_ssbo", callee
) ||
3646 !strcmp("__intrinsic_atomic_max_ssbo", callee
) ||
3647 !strcmp("__intrinsic_atomic_and_ssbo", callee
) ||
3648 !strcmp("__intrinsic_atomic_or_ssbo", callee
) ||
3649 !strcmp("__intrinsic_atomic_xor_ssbo", callee
) ||
3650 !strcmp("__intrinsic_atomic_exchange_ssbo", callee
) ||
3651 !strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3652 visit_ssbo_intrinsic(ir
);
3656 if (!strcmp("__intrinsic_memory_barrier", callee
) ||
3657 !strcmp("__intrinsic_memory_barrier_atomic_counter", callee
) ||
3658 !strcmp("__intrinsic_memory_barrier_buffer", callee
) ||
3659 !strcmp("__intrinsic_memory_barrier_image", callee
) ||
3660 !strcmp("__intrinsic_memory_barrier_shared", callee
) ||
3661 !strcmp("__intrinsic_group_memory_barrier", callee
)) {
3662 visit_membar_intrinsic(ir
);
3666 if (!strcmp("__intrinsic_load_shared", callee
) ||
3667 !strcmp("__intrinsic_store_shared", callee
) ||
3668 !strcmp("__intrinsic_atomic_add_shared", callee
) ||
3669 !strcmp("__intrinsic_atomic_min_shared", callee
) ||
3670 !strcmp("__intrinsic_atomic_max_shared", callee
) ||
3671 !strcmp("__intrinsic_atomic_and_shared", callee
) ||
3672 !strcmp("__intrinsic_atomic_or_shared", callee
) ||
3673 !strcmp("__intrinsic_atomic_xor_shared", callee
) ||
3674 !strcmp("__intrinsic_atomic_exchange_shared", callee
) ||
3675 !strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3676 visit_shared_intrinsic(ir
);
3680 if (!strcmp("__intrinsic_image_load", callee
) ||
3681 !strcmp("__intrinsic_image_store", callee
) ||
3682 !strcmp("__intrinsic_image_atomic_add", callee
) ||
3683 !strcmp("__intrinsic_image_atomic_min", callee
) ||
3684 !strcmp("__intrinsic_image_atomic_max", callee
) ||
3685 !strcmp("__intrinsic_image_atomic_and", callee
) ||
3686 !strcmp("__intrinsic_image_atomic_or", callee
) ||
3687 !strcmp("__intrinsic_image_atomic_xor", callee
) ||
3688 !strcmp("__intrinsic_image_atomic_exchange", callee
) ||
3689 !strcmp("__intrinsic_image_atomic_comp_swap", callee
) ||
3690 !strcmp("__intrinsic_image_size", callee
) ||
3691 !strcmp("__intrinsic_image_samples", callee
)) {
3692 visit_image_intrinsic(ir
);
3696 entry
= get_function_signature(sig
);
3697 /* Process in parameters. */
3698 foreach_two_lists(formal_node
, &sig
->parameters
,
3699 actual_node
, &ir
->actual_parameters
) {
3700 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3701 ir_variable
*param
= (ir_variable
*) formal_node
;
3703 if (param
->data
.mode
== ir_var_function_in
||
3704 param
->data
.mode
== ir_var_function_inout
) {
3705 variable_storage
*storage
= find_variable_storage(param
);
3708 param_rval
->accept(this);
3709 st_src_reg r
= this->result
;
3712 l
.file
= storage
->file
;
3713 l
.index
= storage
->index
;
3715 l
.writemask
= WRITEMASK_XYZW
;
3717 for (i
= 0; i
< type_size(param
->type
); i
++) {
3718 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3725 /* Emit call instruction */
3726 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3727 call_inst
->function
= entry
;
3729 /* Process out parameters. */
3730 foreach_two_lists(formal_node
, &sig
->parameters
,
3731 actual_node
, &ir
->actual_parameters
) {
3732 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3733 ir_variable
*param
= (ir_variable
*) formal_node
;
3735 if (param
->data
.mode
== ir_var_function_out
||
3736 param
->data
.mode
== ir_var_function_inout
) {
3737 variable_storage
*storage
= find_variable_storage(param
);
3741 r
.file
= storage
->file
;
3742 r
.index
= storage
->index
;
3744 r
.swizzle
= SWIZZLE_NOOP
;
3747 param_rval
->accept(this);
3748 st_dst_reg l
= st_dst_reg(this->result
);
3750 for (i
= 0; i
< type_size(param
->type
); i
++) {
3751 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3758 /* Process return value. */
3759 this->result
= entry
->return_reg
;
3763 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3764 ir_dereference
*tail
,
3765 unsigned *array_elements
,
3768 st_src_reg
*indirect
,
3771 switch (tail
->ir_type
) {
3772 case ir_type_dereference_record
: {
3773 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3774 const glsl_type
*struct_type
= deref_record
->record
->type
;
3775 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3777 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3779 assert(field_index
>= 0);
3780 *location
+= struct_type
->record_location_offset(field_index
);
3784 case ir_type_dereference_array
: {
3785 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3786 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3789 st_src_reg temp_reg
;
3790 st_dst_reg temp_dst
;
3792 temp_reg
= get_temp(glsl_type::uint_type
);
3793 temp_dst
= st_dst_reg(temp_reg
);
3794 temp_dst
.writemask
= 1;
3796 deref_arr
->array_index
->accept(this);
3797 if (*array_elements
!= 1)
3798 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3800 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3802 if (indirect
->file
== PROGRAM_UNDEFINED
)
3803 *indirect
= temp_reg
;
3805 temp_dst
= st_dst_reg(*indirect
);
3806 temp_dst
.writemask
= 1;
3807 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3810 *index
+= array_index
->value
.u
[0] * *array_elements
;
3812 *array_elements
*= deref_arr
->array
->type
->length
;
3814 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3823 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3824 unsigned *array_size
,
3827 st_src_reg
*reladdr
)
3829 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3830 unsigned location
= 0;
3831 ir_variable
*var
= ir
->variable_referenced();
3833 memset(reladdr
, 0, sizeof(*reladdr
));
3834 reladdr
->file
= PROGRAM_UNDEFINED
;
3840 location
= var
->data
.location
;
3841 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3844 * If we end up with no indirect then adjust the base to the index,
3845 * and set the array size to 1.
3847 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3852 if (location
!= 0xffffffff) {
3853 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3854 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3859 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3861 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3862 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3863 st_src_reg levels_src
, reladdr
;
3864 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3865 glsl_to_tgsi_instruction
*inst
= NULL
;
3866 unsigned opcode
= TGSI_OPCODE_NOP
;
3867 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3868 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
3869 bool is_cube_array
= false;
3872 /* if we are a cube array sampler */
3873 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3874 sampler_type
->sampler_array
)) {
3875 is_cube_array
= true;
3878 if (ir
->coordinate
) {
3879 ir
->coordinate
->accept(this);
3881 /* Put our coords in a temp. We'll need to modify them for shadow,
3882 * projection, or LOD, so the only case we'd use it as is is if
3883 * we're doing plain old texturing. The optimization passes on
3884 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3886 coord
= get_temp(glsl_type::vec4_type
);
3887 coord_dst
= st_dst_reg(coord
);
3888 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3889 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3892 if (ir
->projector
) {
3893 ir
->projector
->accept(this);
3894 projector
= this->result
;
3897 /* Storage for our result. Ideally for an assignment we'd be using
3898 * the actual storage for the result here, instead.
3900 result_src
= get_temp(ir
->type
);
3901 result_dst
= st_dst_reg(result_src
);
3905 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3907 ir
->offset
->accept(this);
3908 offset
[0] = this->result
;
3912 if (is_cube_array
||
3913 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3914 opcode
= TGSI_OPCODE_TXB2
;
3917 opcode
= TGSI_OPCODE_TXB
;
3919 ir
->lod_info
.bias
->accept(this);
3920 lod_info
= this->result
;
3922 ir
->offset
->accept(this);
3923 offset
[0] = this->result
;
3927 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3928 ir
->lod_info
.lod
->accept(this);
3929 lod_info
= this->result
;
3931 ir
->offset
->accept(this);
3932 offset
[0] = this->result
;
3936 opcode
= TGSI_OPCODE_TXD
;
3937 ir
->lod_info
.grad
.dPdx
->accept(this);
3939 ir
->lod_info
.grad
.dPdy
->accept(this);
3942 ir
->offset
->accept(this);
3943 offset
[0] = this->result
;
3947 opcode
= TGSI_OPCODE_TXQ
;
3948 ir
->lod_info
.lod
->accept(this);
3949 lod_info
= this->result
;
3951 case ir_query_levels
:
3952 opcode
= TGSI_OPCODE_TXQ
;
3953 lod_info
= undef_src
;
3954 levels_src
= get_temp(ir
->type
);
3957 opcode
= TGSI_OPCODE_TXF
;
3958 ir
->lod_info
.lod
->accept(this);
3959 lod_info
= this->result
;
3961 ir
->offset
->accept(this);
3962 offset
[0] = this->result
;
3966 opcode
= TGSI_OPCODE_TXF
;
3967 ir
->lod_info
.sample_index
->accept(this);
3968 sample_index
= this->result
;
3971 opcode
= TGSI_OPCODE_TG4
;
3972 ir
->lod_info
.component
->accept(this);
3973 component
= this->result
;
3975 ir
->offset
->accept(this);
3976 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3977 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3978 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3979 offset
[i
] = this->result
;
3980 offset
[i
].index
+= i
* type_size(elt_type
);
3981 offset
[i
].type
= elt_type
->base_type
;
3982 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3985 offset
[0] = this->result
;
3990 opcode
= TGSI_OPCODE_LODQ
;
3992 case ir_texture_samples
:
3993 opcode
= TGSI_OPCODE_TXQS
;
3995 case ir_samples_identical
:
3996 unreachable("Unexpected ir_samples_identical opcode");
3999 if (ir
->projector
) {
4000 if (opcode
== TGSI_OPCODE_TEX
) {
4001 /* Slot the projector in as the last component of the coord. */
4002 coord_dst
.writemask
= WRITEMASK_W
;
4003 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4004 coord_dst
.writemask
= WRITEMASK_XYZW
;
4005 opcode
= TGSI_OPCODE_TXP
;
4007 st_src_reg coord_w
= coord
;
4008 coord_w
.swizzle
= SWIZZLE_WWWW
;
4010 /* For the other TEX opcodes there's no projective version
4011 * since the last slot is taken up by LOD info. Do the
4012 * projective divide now.
4014 coord_dst
.writemask
= WRITEMASK_W
;
4015 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4017 /* In the case where we have to project the coordinates "by hand,"
4018 * the shadow comparator value must also be projected.
4020 st_src_reg tmp_src
= coord
;
4021 if (ir
->shadow_comparitor
) {
4022 /* Slot the shadow value in as the second to last component of the
4025 ir
->shadow_comparitor
->accept(this);
4027 tmp_src
= get_temp(glsl_type::vec4_type
);
4028 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4030 /* Projective division not allowed for array samplers. */
4031 assert(!sampler_type
->sampler_array
);
4033 tmp_dst
.writemask
= WRITEMASK_Z
;
4034 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4036 tmp_dst
.writemask
= WRITEMASK_XY
;
4037 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4040 coord_dst
.writemask
= WRITEMASK_XYZ
;
4041 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4043 coord_dst
.writemask
= WRITEMASK_XYZW
;
4044 coord
.swizzle
= SWIZZLE_XYZW
;
4048 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4049 * comparator was put in the correct place (and projected) by the code,
4050 * above, that handles by-hand projection.
4052 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4053 /* Slot the shadow value in as the second to last component of the
4056 ir
->shadow_comparitor
->accept(this);
4058 if (is_cube_array
) {
4059 cube_sc
= get_temp(glsl_type::float_type
);
4060 cube_sc_dst
= st_dst_reg(cube_sc
);
4061 cube_sc_dst
.writemask
= WRITEMASK_X
;
4062 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4063 cube_sc_dst
.writemask
= WRITEMASK_X
;
4066 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4067 sampler_type
->sampler_array
) ||
4068 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4069 coord_dst
.writemask
= WRITEMASK_W
;
4071 coord_dst
.writemask
= WRITEMASK_Z
;
4073 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4074 coord_dst
.writemask
= WRITEMASK_XYZW
;
4078 if (ir
->op
== ir_txf_ms
) {
4079 coord_dst
.writemask
= WRITEMASK_W
;
4080 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4081 coord_dst
.writemask
= WRITEMASK_XYZW
;
4082 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4083 opcode
== TGSI_OPCODE_TXF
) {
4084 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4085 coord_dst
.writemask
= WRITEMASK_W
;
4086 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4087 coord_dst
.writemask
= WRITEMASK_XYZW
;
4090 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4091 &sampler_index
, &reladdr
);
4092 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4093 emit_arl(ir
, sampler_reladdr
, reladdr
);
4095 if (opcode
== TGSI_OPCODE_TXD
)
4096 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4097 else if (opcode
== TGSI_OPCODE_TXQ
) {
4098 if (ir
->op
== ir_query_levels
) {
4099 /* the level is stored in W */
4100 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4101 result_dst
.writemask
= WRITEMASK_X
;
4102 levels_src
.swizzle
= SWIZZLE_WWWW
;
4103 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4105 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4106 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4107 inst
= emit_asm(ir
, opcode
, result_dst
);
4108 } else if (opcode
== TGSI_OPCODE_TXF
) {
4109 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4110 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4111 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4112 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4113 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4114 } else if (opcode
== TGSI_OPCODE_TG4
) {
4115 if (is_cube_array
&& ir
->shadow_comparitor
) {
4116 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4118 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4121 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4123 if (ir
->shadow_comparitor
)
4124 inst
->tex_shadow
= GL_TRUE
;
4126 inst
->sampler
.index
= sampler_index
;
4127 inst
->sampler_array_size
= sampler_array_size
;
4128 inst
->sampler_base
= sampler_base
;
4130 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4131 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4132 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4136 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4137 inst
->tex_offsets
[i
] = offset
[i
];
4138 inst
->tex_offset_num_offset
= i
;
4141 switch (sampler_type
->sampler_dimensionality
) {
4142 case GLSL_SAMPLER_DIM_1D
:
4143 inst
->tex_target
= (sampler_type
->sampler_array
)
4144 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4146 case GLSL_SAMPLER_DIM_2D
:
4147 inst
->tex_target
= (sampler_type
->sampler_array
)
4148 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4150 case GLSL_SAMPLER_DIM_3D
:
4151 inst
->tex_target
= TEXTURE_3D_INDEX
;
4153 case GLSL_SAMPLER_DIM_CUBE
:
4154 inst
->tex_target
= (sampler_type
->sampler_array
)
4155 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4157 case GLSL_SAMPLER_DIM_RECT
:
4158 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4160 case GLSL_SAMPLER_DIM_BUF
:
4161 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4163 case GLSL_SAMPLER_DIM_EXTERNAL
:
4164 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4166 case GLSL_SAMPLER_DIM_MS
:
4167 inst
->tex_target
= (sampler_type
->sampler_array
)
4168 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4171 assert(!"Should not get here.");
4174 inst
->tex_type
= ir
->type
->base_type
;
4176 this->result
= result_src
;
4180 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4182 if (ir
->get_value()) {
4186 assert(current_function
);
4188 ir
->get_value()->accept(this);
4189 st_src_reg r
= this->result
;
4191 l
= st_dst_reg(current_function
->return_reg
);
4193 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4194 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4200 emit_asm(ir
, TGSI_OPCODE_RET
);
4204 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4206 if (ir
->condition
) {
4207 ir
->condition
->accept(this);
4208 st_src_reg condition
= this->result
;
4210 /* Convert the bool condition to a float so we can negate. */
4211 if (native_integers
) {
4212 st_src_reg temp
= get_temp(ir
->condition
->type
);
4213 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4214 condition
, st_src_reg_for_float(1.0));
4218 condition
.negate
= ~condition
.negate
;
4219 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4221 /* unconditional kil */
4222 emit_asm(ir
, TGSI_OPCODE_KILL
);
4227 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4230 glsl_to_tgsi_instruction
*if_inst
;
4232 ir
->condition
->accept(this);
4233 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4235 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4237 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4239 this->instructions
.push_tail(if_inst
);
4241 visit_exec_list(&ir
->then_instructions
, this);
4243 if (!ir
->else_instructions
.is_empty()) {
4244 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4245 visit_exec_list(&ir
->else_instructions
, this);
4248 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4253 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4255 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4257 ir
->stream
->accept(this);
4258 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4262 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4264 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4266 ir
->stream
->accept(this);
4267 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4271 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4273 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4274 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4276 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4279 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4281 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4283 result
.file
= PROGRAM_UNDEFINED
;
4288 num_input_arrays
= 0;
4289 num_output_arrays
= 0;
4290 next_signature_id
= 1;
4292 current_function
= NULL
;
4293 num_address_regs
= 0;
4297 indirect_addr_consts
= false;
4298 wpos_transform_const
= -1;
4300 native_integers
= false;
4301 mem_ctx
= ralloc_context(NULL
);
4304 shader_program
= NULL
;
4309 use_shared_memory
= false;
4312 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4315 ralloc_free(mem_ctx
);
4318 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4325 * Count resources used by the given gpu program (number of texture
4329 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4331 v
->samplers_used
= 0;
4332 v
->buffers_used
= 0;
4335 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4336 if (inst
->info
->is_tex
) {
4337 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4338 unsigned idx
= inst
->sampler_base
+ i
;
4339 v
->samplers_used
|= 1u << idx
;
4341 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4342 v
->sampler_types
[idx
] = inst
->tex_type
;
4343 v
->sampler_targets
[idx
] =
4344 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4346 if (inst
->tex_shadow
) {
4347 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4351 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4352 is_resource_instruction(inst
->op
) ||
4353 inst
->op
== TGSI_OPCODE_STORE
)) {
4354 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4355 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4356 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4357 v
->use_shared_memory
= true;
4359 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4360 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4361 unsigned idx
= inst
->sampler_base
+ i
;
4362 v
->images_used
|= 1 << idx
;
4363 v
->image_targets
[idx
] =
4364 st_translate_texture_target(inst
->tex_target
, false);
4365 v
->image_formats
[idx
] = inst
->image_format
;
4370 prog
->SamplersUsed
= v
->samplers_used
;
4372 if (v
->shader_program
!= NULL
)
4373 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4377 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4378 * are read from the given src in this instruction
4381 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4383 int read_mask
= 0, comp
;
4385 /* Now, given the src swizzle and the written channels, find which
4386 * components are actually read
4388 for (comp
= 0; comp
< 4; ++comp
) {
4389 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4391 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4392 read_mask
|= 1 << coord
;
4399 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4400 * instruction is the first instruction to write to register T0. There are
4401 * several lowering passes done in GLSL IR (e.g. branches and
4402 * relative addressing) that create a large number of conditional assignments
4403 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4405 * Here is why this conversion is safe:
4406 * CMP T0, T1 T2 T0 can be expanded to:
4412 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4413 * as the original program. If (T1 < 0.0) evaluates to false, executing
4414 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4415 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4416 * because any instruction that was going to read from T0 after this was going
4417 * to read a garbage value anyway.
4420 glsl_to_tgsi_visitor::simplify_cmp(void)
4422 int tempWritesSize
= 0;
4423 unsigned *tempWrites
= NULL
;
4424 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4426 memset(outputWrites
, 0, sizeof(outputWrites
));
4428 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4429 unsigned prevWriteMask
= 0;
4431 /* Give up if we encounter relative addressing or flow control. */
4432 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4433 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4434 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4435 inst
->op
== TGSI_OPCODE_BGNSUB
||
4436 inst
->op
== TGSI_OPCODE_CONT
||
4437 inst
->op
== TGSI_OPCODE_END
||
4438 inst
->op
== TGSI_OPCODE_ENDSUB
||
4439 inst
->op
== TGSI_OPCODE_RET
) {
4443 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4444 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4445 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4446 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4447 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4448 if (inst
->dst
[0].index
>= tempWritesSize
) {
4449 const int inc
= 4096;
4451 tempWrites
= (unsigned*)
4453 (tempWritesSize
+ inc
) * sizeof(unsigned));
4457 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4458 tempWritesSize
+= inc
;
4461 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4462 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4466 /* For a CMP to be considered a conditional write, the destination
4467 * register and source register two must be the same. */
4468 if (inst
->op
== TGSI_OPCODE_CMP
4469 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4470 && inst
->src
[2].file
== inst
->dst
[0].file
4471 && inst
->src
[2].index
== inst
->dst
[0].index
4472 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4474 inst
->op
= TGSI_OPCODE_MOV
;
4475 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4476 inst
->src
[0] = inst
->src
[1];
4483 /* Replaces all references to a temporary register index with another index. */
4485 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4487 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4490 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4491 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4492 for (k
= 0; k
< num_renames
; k
++)
4493 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4494 inst
->src
[j
].index
= renames
[k
].new_reg
;
4497 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4498 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4499 for (k
= 0; k
< num_renames
; k
++)
4500 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4501 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4504 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4505 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4506 for (k
= 0; k
< num_renames
; k
++)
4507 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4508 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4514 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4516 int depth
= 0; /* loop depth */
4517 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4520 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4521 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4522 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4523 if (first_reads
[inst
->src
[j
].index
] == -1)
4524 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4527 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4528 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4529 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4530 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4533 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4536 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4546 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4548 int depth
= 0; /* loop depth */
4549 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4552 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4553 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4554 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4555 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4557 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4558 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4559 if (first_writes
[inst
->dst
[j
].index
] == -1)
4560 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4561 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4564 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4565 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4566 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4568 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4571 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4574 for (k
= 0; k
< this->next_temp
; k
++) {
4575 if (last_reads
[k
] == -2) {
4587 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4589 int depth
= 0; /* loop depth */
4593 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4594 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4595 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4596 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4599 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4601 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4603 for (k
= 0; k
< this->next_temp
; k
++) {
4604 if (last_writes
[k
] == -2) {
4615 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4616 * channels for copy propagation and updates following instructions to
4617 * use the original versions.
4619 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4620 * will occur. As an example, a TXP production before this pass:
4622 * 0: MOV TEMP[1], INPUT[4].xyyy;
4623 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4624 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4628 * 0: MOV TEMP[1], INPUT[4].xyyy;
4629 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4630 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4632 * which allows for dead code elimination on TEMP[1]'s writes.
4635 glsl_to_tgsi_visitor::copy_propagate(void)
4637 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4638 glsl_to_tgsi_instruction
*,
4639 this->next_temp
* 4);
4640 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4643 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4644 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4645 || inst
->dst
[0].index
< this->next_temp
);
4647 /* First, do any copy propagation possible into the src regs. */
4648 for (int r
= 0; r
< 3; r
++) {
4649 glsl_to_tgsi_instruction
*first
= NULL
;
4651 int acp_base
= inst
->src
[r
].index
* 4;
4653 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4654 inst
->src
[r
].reladdr
||
4655 inst
->src
[r
].reladdr2
)
4658 /* See if we can find entries in the ACP consisting of MOVs
4659 * from the same src register for all the swizzled channels
4660 * of this src register reference.
4662 for (int i
= 0; i
< 4; i
++) {
4663 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4664 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4671 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4676 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4677 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4678 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4679 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4687 /* We've now validated that we can copy-propagate to
4688 * replace this src register reference. Do it.
4690 inst
->src
[r
].file
= first
->src
[0].file
;
4691 inst
->src
[r
].index
= first
->src
[0].index
;
4692 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4693 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4694 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4695 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4698 for (int i
= 0; i
< 4; i
++) {
4699 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4700 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4701 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4703 inst
->src
[r
].swizzle
= swizzle
;
4708 case TGSI_OPCODE_BGNLOOP
:
4709 case TGSI_OPCODE_ENDLOOP
:
4710 /* End of a basic block, clear the ACP entirely. */
4711 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4714 case TGSI_OPCODE_IF
:
4715 case TGSI_OPCODE_UIF
:
4719 case TGSI_OPCODE_ENDIF
:
4720 case TGSI_OPCODE_ELSE
:
4721 /* Clear all channels written inside the block from the ACP, but
4722 * leaving those that were not touched.
4724 for (int r
= 0; r
< this->next_temp
; r
++) {
4725 for (int c
= 0; c
< 4; c
++) {
4726 if (!acp
[4 * r
+ c
])
4729 if (acp_level
[4 * r
+ c
] >= level
)
4730 acp
[4 * r
+ c
] = NULL
;
4733 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4738 /* Continuing the block, clear any written channels from
4741 for (int d
= 0; d
< 2; d
++) {
4742 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4743 /* Any temporary might be written, so no copy propagation
4744 * across this instruction.
4746 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4747 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4748 inst
->dst
[d
].reladdr
) {
4749 /* Any output might be written, so no copy propagation
4750 * from outputs across this instruction.
4752 for (int r
= 0; r
< this->next_temp
; r
++) {
4753 for (int c
= 0; c
< 4; c
++) {
4754 if (!acp
[4 * r
+ c
])
4757 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4758 acp
[4 * r
+ c
] = NULL
;
4761 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4762 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4763 /* Clear where it's used as dst. */
4764 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4765 for (int c
= 0; c
< 4; c
++) {
4766 if (inst
->dst
[d
].writemask
& (1 << c
))
4767 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4771 /* Clear where it's used as src. */
4772 for (int r
= 0; r
< this->next_temp
; r
++) {
4773 for (int c
= 0; c
< 4; c
++) {
4774 if (!acp
[4 * r
+ c
])
4777 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4779 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4780 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4781 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4782 acp
[4 * r
+ c
] = NULL
;
4791 /* If this is a copy, add it to the ACP. */
4792 if (inst
->op
== TGSI_OPCODE_MOV
&&
4793 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4794 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4795 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4796 !inst
->dst
[0].reladdr
&&
4797 !inst
->dst
[0].reladdr2
&&
4799 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4800 !inst
->src
[0].reladdr
&&
4801 !inst
->src
[0].reladdr2
&&
4802 !inst
->src
[0].negate
) {
4803 for (int i
= 0; i
< 4; i
++) {
4804 if (inst
->dst
[0].writemask
& (1 << i
)) {
4805 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4806 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4812 ralloc_free(acp_level
);
4817 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4820 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4821 * will occur. As an example, a TXP production after copy propagation but
4824 * 0: MOV TEMP[1], INPUT[4].xyyy;
4825 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4826 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4828 * and after this pass:
4830 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4833 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4835 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4836 glsl_to_tgsi_instruction
*,
4837 this->next_temp
* 4);
4838 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4842 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4843 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4844 || inst
->dst
[0].index
< this->next_temp
);
4847 case TGSI_OPCODE_BGNLOOP
:
4848 case TGSI_OPCODE_ENDLOOP
:
4849 case TGSI_OPCODE_CONT
:
4850 case TGSI_OPCODE_BRK
:
4851 /* End of a basic block, clear the write array entirely.
4853 * This keeps us from killing dead code when the writes are
4854 * on either side of a loop, even when the register isn't touched
4855 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4856 * dead code of this type, so it shouldn't make a difference as long as
4857 * the dead code elimination pass in the GLSL compiler does its job.
4859 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4862 case TGSI_OPCODE_ENDIF
:
4863 case TGSI_OPCODE_ELSE
:
4864 /* Promote the recorded level of all channels written inside the
4865 * preceding if or else block to the level above the if/else block.
4867 for (int r
= 0; r
< this->next_temp
; r
++) {
4868 for (int c
= 0; c
< 4; c
++) {
4869 if (!writes
[4 * r
+ c
])
4872 if (write_level
[4 * r
+ c
] == level
)
4873 write_level
[4 * r
+ c
] = level
-1;
4876 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4880 case TGSI_OPCODE_IF
:
4881 case TGSI_OPCODE_UIF
:
4883 /* fallthrough to default case to mark the condition as read */
4885 /* Continuing the block, clear any channels from the write array that
4886 * are read by this instruction.
4888 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4889 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4890 /* Any temporary might be read, so no dead code elimination
4891 * across this instruction.
4893 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4894 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4895 /* Clear where it's used as src. */
4896 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4897 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4898 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4899 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4901 for (int c
= 0; c
< 4; c
++) {
4902 if (src_chans
& (1 << c
))
4903 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4907 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4908 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4909 /* Any temporary might be read, so no dead code elimination
4910 * across this instruction.
4912 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4913 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4914 /* Clear where it's used as src. */
4915 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4916 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4917 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4918 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4920 for (int c
= 0; c
< 4; c
++) {
4921 if (src_chans
& (1 << c
))
4922 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4929 /* If this instruction writes to a temporary, add it to the write array.
4930 * If there is already an instruction in the write array for one or more
4931 * of the channels, flag that channel write as dead.
4933 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4934 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4935 !inst
->dst
[i
].reladdr
) {
4936 for (int c
= 0; c
< 4; c
++) {
4937 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4938 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4939 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4942 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4944 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4945 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4952 /* Anything still in the write array at this point is dead code. */
4953 for (int r
= 0; r
< this->next_temp
; r
++) {
4954 for (int c
= 0; c
< 4; c
++) {
4955 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4957 inst
->dead_mask
|= (1 << c
);
4961 /* Now actually remove the instructions that are completely dead and update
4962 * the writemask of other instructions with dead channels.
4964 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4965 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4967 /* No amount of dead masks should remove memory stores */
4968 if (inst
->info
->is_store
)
4971 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4976 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4977 if (inst
->dead_mask
== WRITEMASK_XY
||
4978 inst
->dead_mask
== WRITEMASK_ZW
)
4979 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4981 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4985 ralloc_free(write_level
);
4986 ralloc_free(writes
);
4991 /* merge DFRACEXP instructions into one. */
4993 glsl_to_tgsi_visitor::merge_two_dsts(void)
4995 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4996 glsl_to_tgsi_instruction
*inst2
;
4998 if (num_inst_dst_regs(inst
) != 2)
5001 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5002 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5005 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5008 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5009 inst
->src
[0].index
== inst2
->src
[0].index
&&
5010 inst
->src
[0].type
== inst2
->src
[0].type
&&
5011 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5013 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5019 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5021 inst
->dst
[0] = inst2
->dst
[0];
5022 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5023 inst
->dst
[1] = inst2
->dst
[1];
5034 /* Merges temporary registers together where possible to reduce the number of
5035 * registers needed to run a program.
5037 * Produces optimal code only after copy propagation and dead code elimination
5040 glsl_to_tgsi_visitor::merge_registers(void)
5042 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5043 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5044 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5046 int num_renames
= 0;
5048 /* Read the indices of the last read and first write to each temp register
5049 * into an array so that we don't have to traverse the instruction list as
5051 for (i
= 0; i
< this->next_temp
; i
++) {
5053 first_writes
[i
] = -1;
5055 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5057 /* Start looking for registers with non-overlapping usages that can be
5058 * merged together. */
5059 for (i
= 0; i
< this->next_temp
; i
++) {
5060 /* Don't touch unused registers. */
5061 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5063 for (j
= 0; j
< this->next_temp
; j
++) {
5064 /* Don't touch unused registers. */
5065 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5067 /* We can merge the two registers if the first write to j is after or
5068 * in the same instruction as the last read from i. Note that the
5069 * register at index i will always be used earlier or at the same time
5070 * as the register at index j. */
5071 if (first_writes
[i
] <= first_writes
[j
] &&
5072 last_reads
[i
] <= first_writes
[j
]) {
5073 renames
[num_renames
].old_reg
= j
;
5074 renames
[num_renames
].new_reg
= i
;
5077 /* Update the first_writes and last_reads arrays with the new
5078 * values for the merged register index, and mark the newly unused
5079 * register index as such. */
5080 assert(last_reads
[j
] >= last_reads
[i
]);
5081 last_reads
[i
] = last_reads
[j
];
5082 first_writes
[j
] = -1;
5088 rename_temp_registers(num_renames
, renames
);
5089 ralloc_free(renames
);
5090 ralloc_free(last_reads
);
5091 ralloc_free(first_writes
);
5094 /* Reassign indices to temporary registers by reusing unused indices created
5095 * by optimization passes. */
5097 glsl_to_tgsi_visitor::renumber_registers(void)
5101 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5102 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5103 int num_renames
= 0;
5104 for (i
= 0; i
< this->next_temp
; i
++) {
5105 first_reads
[i
] = -1;
5107 get_first_temp_read(first_reads
);
5109 for (i
= 0; i
< this->next_temp
; i
++) {
5110 if (first_reads
[i
] < 0) continue;
5111 if (i
!= new_index
) {
5112 renames
[num_renames
].old_reg
= i
;
5113 renames
[num_renames
].new_reg
= new_index
;
5119 rename_temp_registers(num_renames
, renames
);
5120 this->next_temp
= new_index
;
5121 ralloc_free(renames
);
5122 ralloc_free(first_reads
);
5125 /* ------------------------- TGSI conversion stuff -------------------------- */
5127 unsigned branch_target
;
5132 * Intermediate state used during shader translation.
5134 struct st_translate
{
5135 struct ureg_program
*ureg
;
5137 unsigned temps_size
;
5138 struct ureg_dst
*temps
;
5140 struct ureg_dst
*arrays
;
5141 unsigned num_temp_arrays
;
5142 struct ureg_src
*constants
;
5144 struct ureg_src
*immediates
;
5146 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5147 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5148 struct ureg_dst address
[3];
5149 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5150 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5151 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5152 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5153 struct ureg_src shared_memory
;
5154 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5155 unsigned *array_sizes
;
5156 struct array_decl
*input_arrays
;
5157 struct array_decl
*output_arrays
;
5159 const GLuint
*inputMapping
;
5160 const GLuint
*outputMapping
;
5162 /* For every instruction that contains a label (eg CALL), keep
5163 * details so that we can go back afterwards and emit the correct
5164 * tgsi instruction number for each label.
5166 struct label
*labels
;
5167 unsigned labels_size
;
5168 unsigned labels_count
;
5170 /* Keep a record of the tgsi instruction number that each mesa
5171 * instruction starts at, will be used to fix up labels after
5176 unsigned insn_count
;
5178 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5183 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5185 _mesa_sysval_to_semantic(unsigned sysval
)
5189 case SYSTEM_VALUE_VERTEX_ID
:
5190 return TGSI_SEMANTIC_VERTEXID
;
5191 case SYSTEM_VALUE_INSTANCE_ID
:
5192 return TGSI_SEMANTIC_INSTANCEID
;
5193 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5194 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5195 case SYSTEM_VALUE_BASE_VERTEX
:
5196 return TGSI_SEMANTIC_BASEVERTEX
;
5197 case SYSTEM_VALUE_BASE_INSTANCE
:
5198 return TGSI_SEMANTIC_BASEINSTANCE
;
5199 case SYSTEM_VALUE_DRAW_ID
:
5200 return TGSI_SEMANTIC_DRAWID
;
5202 /* Geometry shader */
5203 case SYSTEM_VALUE_INVOCATION_ID
:
5204 return TGSI_SEMANTIC_INVOCATIONID
;
5206 /* Fragment shader */
5207 case SYSTEM_VALUE_FRAG_COORD
:
5208 return TGSI_SEMANTIC_POSITION
;
5209 case SYSTEM_VALUE_FRONT_FACE
:
5210 return TGSI_SEMANTIC_FACE
;
5211 case SYSTEM_VALUE_SAMPLE_ID
:
5212 return TGSI_SEMANTIC_SAMPLEID
;
5213 case SYSTEM_VALUE_SAMPLE_POS
:
5214 return TGSI_SEMANTIC_SAMPLEPOS
;
5215 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5216 return TGSI_SEMANTIC_SAMPLEMASK
;
5217 case SYSTEM_VALUE_HELPER_INVOCATION
:
5218 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5220 /* Tessellation shader */
5221 case SYSTEM_VALUE_TESS_COORD
:
5222 return TGSI_SEMANTIC_TESSCOORD
;
5223 case SYSTEM_VALUE_VERTICES_IN
:
5224 return TGSI_SEMANTIC_VERTICESIN
;
5225 case SYSTEM_VALUE_PRIMITIVE_ID
:
5226 return TGSI_SEMANTIC_PRIMID
;
5227 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5228 return TGSI_SEMANTIC_TESSOUTER
;
5229 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5230 return TGSI_SEMANTIC_TESSINNER
;
5232 /* Compute shader */
5233 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5234 return TGSI_SEMANTIC_THREAD_ID
;
5235 case SYSTEM_VALUE_WORK_GROUP_ID
:
5236 return TGSI_SEMANTIC_BLOCK_ID
;
5237 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5238 return TGSI_SEMANTIC_GRID_SIZE
;
5241 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5242 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5243 case SYSTEM_VALUE_VERTEX_CNT
:
5245 assert(!"Unexpected SYSTEM_VALUE_ enum");
5246 return TGSI_SEMANTIC_COUNT
;
5252 * Make note of a branch to a label in the TGSI code.
5253 * After we've emitted all instructions, we'll go over the list
5254 * of labels built here and patch the TGSI code with the actual
5255 * location of each label.
5257 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5261 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5262 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5263 t
->labels
= (struct label
*)realloc(t
->labels
,
5264 t
->labels_size
* sizeof(struct label
));
5265 if (t
->labels
== NULL
) {
5266 static unsigned dummy
;
5272 i
= t
->labels_count
++;
5273 t
->labels
[i
].branch_target
= branch_target
;
5274 return &t
->labels
[i
].token
;
5278 * Called prior to emitting the TGSI code for each instruction.
5279 * Allocate additional space for instructions if needed.
5280 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5281 * the next TGSI instruction.
5283 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5285 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5286 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5287 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5288 if (t
->insn
== NULL
) {
5294 t
->insn
[t
->insn_count
++] = start
;
5298 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5300 static struct ureg_src
5301 emit_immediate(struct st_translate
*t
,
5302 gl_constant_value values
[4],
5305 struct ureg_program
*ureg
= t
->ureg
;
5310 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5312 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5314 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5315 case GL_UNSIGNED_INT
:
5317 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5319 assert(!"should not get here - type must be float, int, uint, or bool");
5320 return ureg_src_undef();
5325 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5327 static struct ureg_dst
5328 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5334 case PROGRAM_UNDEFINED
:
5335 return ureg_dst_undef();
5337 case PROGRAM_TEMPORARY
:
5338 /* Allocate space for temporaries on demand. */
5339 if (index
>= t
->temps_size
) {
5340 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5342 t
->temps
= (struct ureg_dst
*)
5344 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5346 return ureg_dst_undef();
5348 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5349 t
->temps_size
+= inc
;
5352 if (ureg_dst_is_undef(t
->temps
[index
]))
5353 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5355 return t
->temps
[index
];
5358 array
= index
>> 16;
5360 assert(array
< t
->num_temp_arrays
);
5362 if (ureg_dst_is_undef(t
->arrays
[array
]))
5363 t
->arrays
[array
] = ureg_DECL_array_temporary(
5364 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5366 return ureg_dst_array_offset(t
->arrays
[array
],
5367 (int)(index
& 0xFFFF) - 0x8000);
5369 case PROGRAM_OUTPUT
:
5371 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5372 assert(index
< FRAG_RESULT_MAX
);
5373 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5374 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5375 assert(index
< VARYING_SLOT_TESS_MAX
);
5377 assert(index
< VARYING_SLOT_MAX
);
5379 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5380 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5381 return t
->outputs
[t
->outputMapping
[index
]];
5384 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
5385 unsigned mesa_index
= decl
->mesa_index
;
5386 int slot
= t
->outputMapping
[mesa_index
];
5388 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5389 assert(t
->outputs
[slot
].ArrayID
== array_id
);
5390 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
5393 case PROGRAM_ADDRESS
:
5394 return t
->address
[index
];
5397 assert(!"unknown dst register file");
5398 return ureg_dst_undef();
5403 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5405 static struct ureg_src
5406 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5408 int index
= reg
->index
;
5409 int double_reg2
= reg
->double_reg2
? 1 : 0;
5412 case PROGRAM_UNDEFINED
:
5413 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5415 case PROGRAM_TEMPORARY
:
5417 case PROGRAM_OUTPUT
:
5418 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5420 case PROGRAM_UNIFORM
:
5421 assert(reg
->index
>= 0);
5422 return reg
->index
< t
->num_constants
?
5423 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5424 case PROGRAM_STATE_VAR
:
5425 case PROGRAM_CONSTANT
: /* ie, immediate */
5426 if (reg
->has_index2
)
5427 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5429 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5430 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5432 case PROGRAM_IMMEDIATE
:
5433 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5434 return t
->immediates
[reg
->index
];
5437 /* GLSL inputs are 64-bit containers, so we have to
5438 * map back to the original index and add the offset after
5440 index
-= double_reg2
;
5441 if (!reg
->array_id
) {
5442 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5443 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5444 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5447 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
5448 unsigned mesa_index
= decl
->mesa_index
;
5449 int slot
= t
->inputMapping
[mesa_index
];
5451 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5452 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
5453 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
5456 case PROGRAM_ADDRESS
:
5457 return ureg_src(t
->address
[reg
->index
]);
5459 case PROGRAM_SYSTEM_VALUE
:
5460 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5461 return t
->systemValues
[reg
->index
];
5464 assert(!"unknown src register file");
5465 return ureg_src_undef();
5470 * Create a TGSI ureg_dst register from an st_dst_reg.
5472 static struct ureg_dst
5473 translate_dst(struct st_translate
*t
,
5474 const st_dst_reg
*dst_reg
,
5477 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5480 if (dst
.File
== TGSI_FILE_NULL
)
5483 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5486 dst
= ureg_saturate(dst
);
5488 if (dst_reg
->reladdr
!= NULL
) {
5489 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5490 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5493 if (dst_reg
->has_index2
) {
5494 if (dst_reg
->reladdr2
)
5495 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5498 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5505 * Create a TGSI ureg_src register from an st_src_reg.
5507 static struct ureg_src
5508 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5510 struct ureg_src src
= src_register(t
, src_reg
);
5512 if (src_reg
->has_index2
) {
5513 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5514 * and UBO constant buffers (buffer, position).
5516 if (src_reg
->reladdr2
)
5517 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5520 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5523 src
= ureg_swizzle(src
,
5524 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5525 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5526 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5527 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5529 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5530 src
= ureg_negate(src
);
5532 if (src_reg
->reladdr
!= NULL
) {
5533 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5534 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5540 static struct tgsi_texture_offset
5541 translate_tex_offset(struct st_translate
*t
,
5542 const st_src_reg
*in_offset
, int idx
)
5544 struct tgsi_texture_offset offset
;
5545 struct ureg_src imm_src
;
5546 struct ureg_dst dst
;
5549 switch (in_offset
->file
) {
5550 case PROGRAM_IMMEDIATE
:
5551 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
5552 imm_src
= t
->immediates
[in_offset
->index
];
5554 offset
.File
= imm_src
.File
;
5555 offset
.Index
= imm_src
.Index
;
5556 offset
.SwizzleX
= imm_src
.SwizzleX
;
5557 offset
.SwizzleY
= imm_src
.SwizzleY
;
5558 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
5562 imm_src
= t
->inputs
[t
->inputMapping
[in_offset
->index
]];
5563 offset
.File
= imm_src
.File
;
5564 offset
.Index
= imm_src
.Index
;
5565 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5566 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5567 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5570 case PROGRAM_TEMPORARY
:
5571 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
5572 offset
.File
= imm_src
.File
;
5573 offset
.Index
= imm_src
.Index
;
5574 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5575 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5576 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5580 array
= in_offset
->index
>> 16;
5583 assert(array
< (int)t
->num_temp_arrays
);
5585 dst
= t
->arrays
[array
];
5586 offset
.File
= dst
.File
;
5587 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
5588 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5589 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5590 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5600 compile_tgsi_instruction(struct st_translate
*t
,
5601 const glsl_to_tgsi_instruction
*inst
)
5603 struct ureg_program
*ureg
= t
->ureg
;
5605 struct ureg_dst dst
[2];
5606 struct ureg_src src
[4];
5607 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5611 unsigned tex_target
= 0;
5613 num_dst
= num_inst_dst_regs(inst
);
5614 num_src
= num_inst_src_regs(inst
);
5616 for (i
= 0; i
< num_dst
; i
++)
5617 dst
[i
] = translate_dst(t
,
5621 for (i
= 0; i
< num_src
; i
++)
5622 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5625 case TGSI_OPCODE_BGNLOOP
:
5626 case TGSI_OPCODE_CAL
:
5627 case TGSI_OPCODE_ELSE
:
5628 case TGSI_OPCODE_ENDLOOP
:
5629 case TGSI_OPCODE_IF
:
5630 case TGSI_OPCODE_UIF
:
5631 assert(num_dst
== 0);
5632 ureg_label_insn(ureg
,
5636 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5639 case TGSI_OPCODE_TEX
:
5640 case TGSI_OPCODE_TXB
:
5641 case TGSI_OPCODE_TXD
:
5642 case TGSI_OPCODE_TXL
:
5643 case TGSI_OPCODE_TXP
:
5644 case TGSI_OPCODE_TXQ
:
5645 case TGSI_OPCODE_TXQS
:
5646 case TGSI_OPCODE_TXF
:
5647 case TGSI_OPCODE_TEX2
:
5648 case TGSI_OPCODE_TXB2
:
5649 case TGSI_OPCODE_TXL2
:
5650 case TGSI_OPCODE_TG4
:
5651 case TGSI_OPCODE_LODQ
:
5652 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5653 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5654 if (inst
->sampler
.reladdr
)
5656 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5658 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5659 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5661 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5667 texoffsets
, inst
->tex_offset_num_offset
,
5671 case TGSI_OPCODE_RESQ
:
5672 case TGSI_OPCODE_LOAD
:
5673 case TGSI_OPCODE_ATOMUADD
:
5674 case TGSI_OPCODE_ATOMXCHG
:
5675 case TGSI_OPCODE_ATOMCAS
:
5676 case TGSI_OPCODE_ATOMAND
:
5677 case TGSI_OPCODE_ATOMOR
:
5678 case TGSI_OPCODE_ATOMXOR
:
5679 case TGSI_OPCODE_ATOMUMIN
:
5680 case TGSI_OPCODE_ATOMUMAX
:
5681 case TGSI_OPCODE_ATOMIMIN
:
5682 case TGSI_OPCODE_ATOMIMAX
:
5683 for (i
= num_src
- 1; i
>= 0; i
--)
5684 src
[i
+ 1] = src
[i
];
5686 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5687 src
[0] = t
->shared_memory
;
5688 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5689 src
[0] = t
->buffers
[inst
->buffer
.index
];
5691 src
[0] = t
->images
[inst
->buffer
.index
];
5692 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5694 if (inst
->buffer
.reladdr
)
5695 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5696 assert(src
[0].File
!= TGSI_FILE_NULL
);
5697 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5698 inst
->buffer_access
,
5699 tex_target
, inst
->image_format
);
5702 case TGSI_OPCODE_STORE
:
5703 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5704 dst
[0] = ureg_dst(t
->shared_memory
);
5705 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5706 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5708 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5709 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5711 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5712 if (inst
->buffer
.reladdr
)
5713 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5714 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5715 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5716 inst
->buffer_access
,
5717 tex_target
, inst
->image_format
);
5720 case TGSI_OPCODE_SCS
:
5721 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5722 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5735 * Emit the TGSI instructions for inverting and adjusting WPOS.
5736 * This code is unavoidable because it also depends on whether
5737 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5740 emit_wpos_adjustment(struct gl_context
*ctx
,
5741 struct st_translate
*t
,
5742 int wpos_transform_const
,
5744 GLfloat adjX
, GLfloat adjY
[2])
5746 struct ureg_program
*ureg
= t
->ureg
;
5748 assert(wpos_transform_const
>= 0);
5750 /* Fragment program uses fragment position input.
5751 * Need to replace instances of INPUT[WPOS] with temp T
5752 * where T = INPUT[WPOS] is inverted by Y.
5754 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5755 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5756 struct ureg_src
*wpos
=
5757 ctx
->Const
.GLSLFragCoordIsSysVal
?
5758 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5759 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5760 struct ureg_src wpos_input
= *wpos
;
5762 /* First, apply the coordinate shift: */
5763 if (adjX
|| adjY
[0] || adjY
[1]) {
5764 if (adjY
[0] != adjY
[1]) {
5765 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5766 * depending on whether inversion is actually going to be applied
5767 * or not, which is determined by testing against the inversion
5768 * state variable used below, which will be either +1 or -1.
5770 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5772 ureg_CMP(ureg
, adj_temp
,
5773 ureg_scalar(wpostrans
, invert
? 2 : 0),
5774 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5775 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5776 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5778 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5779 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5781 wpos_input
= ureg_src(wpos_temp
);
5783 /* MOV wpos_temp, input[wpos]
5785 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5788 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5789 * inversion/identity, or the other way around if we're drawing to an FBO.
5792 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5795 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5797 ureg_scalar(wpostrans
, 0),
5798 ureg_scalar(wpostrans
, 1));
5800 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5803 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5805 ureg_scalar(wpostrans
, 2),
5806 ureg_scalar(wpostrans
, 3));
5809 /* Use wpos_temp as position input from here on:
5811 *wpos
= ureg_src(wpos_temp
);
5816 * Emit fragment position/ooordinate code.
5819 emit_wpos(struct st_context
*st
,
5820 struct st_translate
*t
,
5821 const struct gl_program
*program
,
5822 struct ureg_program
*ureg
,
5823 int wpos_transform_const
)
5825 const struct gl_fragment_program
*fp
=
5826 (const struct gl_fragment_program
*) program
;
5827 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5828 GLfloat adjX
= 0.0f
;
5829 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5830 boolean invert
= FALSE
;
5832 /* Query the pixel center conventions supported by the pipe driver and set
5833 * adjX, adjY to help out if it cannot handle the requested one internally.
5835 * The bias of the y-coordinate depends on whether y-inversion takes place
5836 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5837 * drawing to an FBO (causes additional inversion), and whether the the pipe
5838 * driver origin and the requested origin differ (the latter condition is
5839 * stored in the 'invert' variable).
5841 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5843 * center shift only:
5848 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5849 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5850 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5851 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5853 * inversion and center shift:
5854 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5855 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5856 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5857 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5859 if (fp
->OriginUpperLeft
) {
5860 /* Fragment shader wants origin in upper-left */
5861 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5862 /* the driver supports upper-left origin */
5864 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5865 /* the driver supports lower-left origin, need to invert Y */
5866 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5867 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5874 /* Fragment shader wants origin in lower-left */
5875 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5876 /* the driver supports lower-left origin */
5877 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5878 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5879 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5880 /* the driver supports upper-left origin, need to invert Y */
5886 if (fp
->PixelCenterInteger
) {
5887 /* Fragment shader wants pixel center integer */
5888 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5889 /* the driver supports pixel center integer */
5891 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5892 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5894 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5895 /* the driver supports pixel center half integer, need to bias X,Y */
5904 /* Fragment shader wants pixel center half integer */
5905 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5906 /* the driver supports pixel center half integer */
5908 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5909 /* the driver supports pixel center integer, need to bias X,Y */
5910 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5911 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5912 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5918 /* we invert after adjustment so that we avoid the MOV to temporary,
5919 * and reuse the adjustment ADD instead */
5920 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5924 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5925 * TGSI uses +1 for front, -1 for back.
5926 * This function converts the TGSI value to the GL value. Simply clamping/
5927 * saturating the value to [0,1] does the job.
5930 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5932 struct ureg_program
*ureg
= t
->ureg
;
5933 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5934 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5936 if (ctx
->Const
.NativeIntegers
) {
5937 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5940 /* MOV_SAT face_temp, input[face] */
5941 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5944 /* Use face_temp as face input from here on: */
5945 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5949 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5950 unsigned *array_id
, unsigned *array_size
)
5954 for (i
= 0; i
< count
; i
++) {
5955 struct array_decl
*decl
= &arrays
[i
];
5957 if (attr
== decl
->mesa_index
) {
5958 *array_id
= decl
->array_id
;
5959 *array_size
= decl
->array_size
;
5960 assert(*array_size
);
5968 emit_compute_block_size(const struct gl_program
*program
,
5969 struct ureg_program
*ureg
) {
5970 const struct gl_compute_program
*cp
=
5971 (const struct gl_compute_program
*)program
;
5973 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5975 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
5977 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
5982 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5983 * \param program the program to translate
5984 * \param numInputs number of input registers used
5985 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5987 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5988 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5990 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5991 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5992 * \param numOutputs number of output registers used
5993 * \param outputMapping maps Mesa fragment program outputs to TGSI
5995 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5996 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5999 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6001 extern "C" enum pipe_error
6002 st_translate_program(
6003 struct gl_context
*ctx
,
6005 struct ureg_program
*ureg
,
6006 glsl_to_tgsi_visitor
*program
,
6007 const struct gl_program
*proginfo
,
6009 const GLuint inputMapping
[],
6010 const GLuint inputSlotToAttr
[],
6011 const ubyte inputSemanticName
[],
6012 const ubyte inputSemanticIndex
[],
6013 const GLuint interpMode
[],
6014 const GLuint interpLocation
[],
6016 const GLuint outputMapping
[],
6017 const GLuint outputSlotToAttr
[],
6018 const ubyte outputSemanticName
[],
6019 const ubyte outputSemanticIndex
[])
6021 struct st_translate
*t
;
6023 struct gl_program_constants
*frag_const
=
6024 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6025 enum pipe_error ret
= PIPE_OK
;
6027 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6028 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6030 t
= CALLOC_STRUCT(st_translate
);
6032 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6036 t
->procType
= procType
;
6037 t
->inputMapping
= inputMapping
;
6038 t
->outputMapping
= outputMapping
;
6040 t
->num_temp_arrays
= program
->next_array
;
6041 if (t
->num_temp_arrays
)
6042 t
->arrays
= (struct ureg_dst
*)
6043 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
6046 * Declare input attributes.
6049 case PIPE_SHADER_FRAGMENT
:
6050 for (i
= 0; i
< numInputs
; i
++) {
6051 unsigned array_id
= 0;
6052 unsigned array_size
;
6054 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6055 program
->num_input_arrays
, &array_id
, &array_size
)) {
6056 /* We've found an array. Declare it so. */
6057 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6058 inputSemanticName
[i
], inputSemanticIndex
[i
],
6059 interpMode
[i
], 0, interpLocation
[i
],
6060 array_id
, array_size
);
6061 i
+= array_size
- 1;
6064 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6065 inputSemanticName
[i
], inputSemanticIndex
[i
],
6066 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
6070 case PIPE_SHADER_GEOMETRY
:
6071 case PIPE_SHADER_TESS_EVAL
:
6072 case PIPE_SHADER_TESS_CTRL
:
6073 for (i
= 0; i
< numInputs
; i
++) {
6074 unsigned array_id
= 0;
6075 unsigned array_size
;
6077 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6078 program
->num_input_arrays
, &array_id
, &array_size
)) {
6079 /* We've found an array. Declare it so. */
6080 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6081 inputSemanticIndex
[i
],
6082 array_id
, array_size
);
6083 i
+= array_size
- 1;
6086 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6087 inputSemanticIndex
[i
], 0, 1);
6091 case PIPE_SHADER_VERTEX
:
6092 for (i
= 0; i
< numInputs
; i
++) {
6093 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6096 case PIPE_SHADER_COMPUTE
:
6103 * Declare output attributes.
6106 case PIPE_SHADER_FRAGMENT
:
6107 case PIPE_SHADER_COMPUTE
:
6109 case PIPE_SHADER_GEOMETRY
:
6110 case PIPE_SHADER_TESS_EVAL
:
6111 case PIPE_SHADER_TESS_CTRL
:
6112 case PIPE_SHADER_VERTEX
:
6113 for (i
= 0; i
< numOutputs
; i
++) {
6114 unsigned array_id
= 0;
6115 unsigned array_size
;
6117 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
6118 program
->num_output_arrays
, &array_id
, &array_size
)) {
6119 /* We've found an array. Declare it so. */
6120 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
6121 outputSemanticName
[i
],
6122 outputSemanticIndex
[i
],
6123 array_id
, array_size
);
6124 i
+= array_size
- 1;
6127 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6128 outputSemanticName
[i
],
6129 outputSemanticIndex
[i
]);
6137 if (procType
== PIPE_SHADER_FRAGMENT
) {
6138 if (program
->shader
->EarlyFragmentTests
)
6139 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6141 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6142 /* Must do this after setting up t->inputs. */
6143 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6144 program
->wpos_transform_const
);
6147 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6148 emit_face_var(ctx
, t
);
6150 for (i
= 0; i
< numOutputs
; i
++) {
6151 switch (outputSemanticName
[i
]) {
6152 case TGSI_SEMANTIC_POSITION
:
6153 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6154 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6155 outputSemanticIndex
[i
]);
6156 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6158 case TGSI_SEMANTIC_STENCIL
:
6159 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6160 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6161 outputSemanticIndex
[i
]);
6162 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6164 case TGSI_SEMANTIC_COLOR
:
6165 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6166 TGSI_SEMANTIC_COLOR
,
6167 outputSemanticIndex
[i
]);
6169 case TGSI_SEMANTIC_SAMPLEMASK
:
6170 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6171 TGSI_SEMANTIC_SAMPLEMASK
,
6172 outputSemanticIndex
[i
]);
6173 /* TODO: If we ever support more than 32 samples, this will have
6174 * to become an array.
6176 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6179 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6180 ret
= PIPE_ERROR_BAD_INPUT
;
6185 else if (procType
== PIPE_SHADER_VERTEX
) {
6186 for (i
= 0; i
< numOutputs
; i
++) {
6187 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6188 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6190 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6191 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6192 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6197 if (procType
== PIPE_SHADER_COMPUTE
) {
6198 emit_compute_block_size(proginfo
, ureg
);
6201 /* Declare address register.
6203 if (program
->num_address_regs
> 0) {
6204 assert(program
->num_address_regs
<= 3);
6205 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6206 t
->address
[i
] = ureg_DECL_address(ureg
);
6209 /* Declare misc input registers
6212 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6214 for (i
= 0; sysInputs
; i
++) {
6215 if (sysInputs
& (1 << i
)) {
6216 unsigned semName
= _mesa_sysval_to_semantic(i
);
6218 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6220 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6221 semName
== TGSI_SEMANTIC_VERTEXID
) {
6222 /* From Gallium perspective, these system values are always
6223 * integer, and require native integer support. However, if
6224 * native integer is supported on the vertex stage but not the
6225 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6226 * assumes these system values are floats. To resolve the
6227 * inconsistency, we insert a U2F.
6229 struct st_context
*st
= st_context(ctx
);
6230 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6231 assert(procType
== PIPE_SHADER_VERTEX
);
6232 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6234 if (!ctx
->Const
.NativeIntegers
) {
6235 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6236 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6237 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6241 if (procType
== PIPE_SHADER_FRAGMENT
&&
6242 semName
== TGSI_SEMANTIC_POSITION
)
6243 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6244 program
->wpos_transform_const
);
6246 sysInputs
&= ~(1 << i
);
6251 t
->array_sizes
= program
->array_sizes
;
6252 t
->input_arrays
= program
->input_arrays
;
6253 t
->output_arrays
= program
->output_arrays
;
6255 /* Emit constants and uniforms. TGSI uses a single index space for these,
6256 * so we put all the translated regs in t->constants.
6258 if (proginfo
->Parameters
) {
6259 t
->constants
= (struct ureg_src
*)
6260 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6261 if (t
->constants
== NULL
) {
6262 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6265 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6267 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6268 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6269 case PROGRAM_STATE_VAR
:
6270 case PROGRAM_UNIFORM
:
6271 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6274 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6275 * addressing of the const buffer.
6276 * FIXME: Be smarter and recognize param arrays:
6277 * indirect addressing is only valid within the referenced
6280 case PROGRAM_CONSTANT
:
6281 if (program
->indirect_addr_consts
)
6282 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6284 t
->constants
[i
] = emit_immediate(t
,
6285 proginfo
->Parameters
->ParameterValues
[i
],
6286 proginfo
->Parameters
->Parameters
[i
].DataType
,
6295 if (program
->shader
) {
6296 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6298 for (i
= 0; i
< num_ubos
; i
++) {
6299 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6300 unsigned num_const_vecs
= (size
+ 15) / 16;
6301 unsigned first
, last
;
6302 assert(num_const_vecs
> 0);
6304 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6305 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6309 /* Emit immediate values.
6311 t
->immediates
= (struct ureg_src
*)
6312 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6313 if (t
->immediates
== NULL
) {
6314 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6317 t
->num_immediates
= program
->num_immediates
;
6320 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6321 assert(i
< program
->num_immediates
);
6322 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6324 assert(i
== program
->num_immediates
);
6326 /* texture samplers */
6327 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6328 if (program
->samplers_used
& (1u << i
)) {
6331 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6333 switch (program
->sampler_types
[i
]) {
6335 type
= TGSI_RETURN_TYPE_SINT
;
6337 case GLSL_TYPE_UINT
:
6338 type
= TGSI_RETURN_TYPE_UINT
;
6340 case GLSL_TYPE_FLOAT
:
6341 type
= TGSI_RETURN_TYPE_FLOAT
;
6344 unreachable("not reached");
6347 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6348 type
, type
, type
, type
);
6352 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6353 if (program
->buffers_used
& (1 << i
)) {
6354 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6358 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6360 if (program
->buffers_used
& (1 << i
)) {
6361 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6365 if (program
->use_shared_memory
)
6366 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6368 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6369 if (program
->images_used
& (1 << i
)) {
6370 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6371 program
->image_targets
[i
],
6372 program
->image_formats
[i
],
6377 /* Emit each instruction in turn:
6379 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6380 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6381 compile_tgsi_instruction(t
, inst
);
6384 /* Fix up all emitted labels:
6386 for (i
= 0; i
< t
->labels_count
; i
++) {
6387 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6388 t
->insn
[t
->labels
[i
].branch_target
]);
6391 /* Set the next shader stage hint for VS and TES. */
6393 case PIPE_SHADER_VERTEX
:
6394 case PIPE_SHADER_TESS_EVAL
:
6395 if (program
->shader_program
->SeparateShader
)
6398 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6399 if (program
->shader_program
->_LinkedShaders
[i
]) {
6403 case MESA_SHADER_TESS_CTRL
:
6404 next
= PIPE_SHADER_TESS_CTRL
;
6406 case MESA_SHADER_TESS_EVAL
:
6407 next
= PIPE_SHADER_TESS_EVAL
;
6409 case MESA_SHADER_GEOMETRY
:
6410 next
= PIPE_SHADER_GEOMETRY
;
6412 case MESA_SHADER_FRAGMENT
:
6413 next
= PIPE_SHADER_FRAGMENT
;
6420 ureg_set_next_shader_processor(ureg
, next
);
6434 t
->num_constants
= 0;
6435 free(t
->immediates
);
6436 t
->num_immediates
= 0;
6439 debug_printf("%s: translate error flag set\n", __func__
);
6447 /* ----------------------------- End TGSI code ------------------------------ */
6451 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6452 * generating Mesa IR.
6454 static struct gl_program
*
6455 get_mesa_program_tgsi(struct gl_context
*ctx
,
6456 struct gl_shader_program
*shader_program
,
6457 struct gl_shader
*shader
)
6459 glsl_to_tgsi_visitor
* v
;
6460 struct gl_program
*prog
;
6461 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6463 struct gl_shader_compiler_options
*options
=
6464 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
6465 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6466 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6468 validate_ir_tree(shader
->ir
);
6470 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6473 prog
->Parameters
= _mesa_new_parameter_list();
6474 v
= new glsl_to_tgsi_visitor();
6477 v
->shader_program
= shader_program
;
6479 v
->options
= options
;
6480 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6481 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6483 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6484 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6485 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6486 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6488 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6489 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6492 /* Remove reads from output registers. */
6493 lower_output_reads(shader
->Stage
, shader
->ir
);
6495 /* Emit intermediate IR for main(). */
6496 visit_exec_list(shader
->ir
, v
);
6498 /* Now emit bodies for any functions that were used. */
6500 progress
= GL_FALSE
;
6502 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6503 if (!entry
->bgn_inst
) {
6504 v
->current_function
= entry
;
6506 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6507 entry
->bgn_inst
->function
= entry
;
6509 visit_exec_list(&entry
->sig
->body
, v
);
6511 glsl_to_tgsi_instruction
*last
;
6512 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6513 if (last
->op
!= TGSI_OPCODE_RET
)
6514 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6516 glsl_to_tgsi_instruction
*end
;
6517 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6518 end
->function
= entry
;
6526 /* Print out some information (for debugging purposes) used by the
6527 * optimization passes. */
6530 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6531 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6532 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6533 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6535 for (i
= 0; i
< v
->next_temp
; i
++) {
6536 first_writes
[i
] = -1;
6537 first_reads
[i
] = -1;
6538 last_writes
[i
] = -1;
6541 v
->get_first_temp_read(first_reads
);
6542 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6543 v
->get_last_temp_write(last_writes
);
6544 for (i
= 0; i
< v
->next_temp
; i
++)
6545 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6549 ralloc_free(first_writes
);
6550 ralloc_free(first_reads
);
6551 ralloc_free(last_writes
);
6552 ralloc_free(last_reads
);
6556 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6559 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
6560 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
6561 v
->copy_propagate();
6563 while (v
->eliminate_dead_code());
6565 v
->merge_two_dsts();
6566 v
->merge_registers();
6567 v
->renumber_registers();
6569 /* Write the END instruction. */
6570 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6572 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6574 _mesa_log("GLSL IR for linked %s program %d:\n",
6575 _mesa_shader_stage_to_string(shader
->Stage
),
6576 shader_program
->Name
);
6577 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6581 prog
->Instructions
= NULL
;
6582 prog
->NumInstructions
= 0;
6584 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6585 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
6586 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
6587 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
6588 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
6589 count_resources(v
, prog
);
6591 /* The GLSL IR won't be needed anymore. */
6592 ralloc_free(shader
->ir
);
6595 /* This must be done before the uniform storage is associated. */
6596 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
6597 (prog
->InputsRead
& VARYING_BIT_POS
||
6598 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6599 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6600 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6603 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6604 wposTransformState
);
6607 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6609 /* Avoid reallocation of the program parameter list, because the uniform
6610 * storage is only associated with the original parameter list.
6611 * This should be enough for Bitmap and DrawPixels constants.
6613 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6615 /* This has to be done last. Any operation the can cause
6616 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6617 * program constant) has to happen before creating this linkage.
6619 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6620 if (!shader_program
->LinkStatus
) {
6621 free_glsl_to_tgsi_visitor(v
);
6625 struct st_vertex_program
*stvp
;
6626 struct st_fragment_program
*stfp
;
6627 struct st_geometry_program
*stgp
;
6628 struct st_tessctrl_program
*sttcp
;
6629 struct st_tesseval_program
*sttep
;
6630 struct st_compute_program
*stcp
;
6632 switch (shader
->Type
) {
6633 case GL_VERTEX_SHADER
:
6634 stvp
= (struct st_vertex_program
*)prog
;
6635 stvp
->glsl_to_tgsi
= v
;
6637 case GL_FRAGMENT_SHADER
:
6638 stfp
= (struct st_fragment_program
*)prog
;
6639 stfp
->glsl_to_tgsi
= v
;
6641 case GL_GEOMETRY_SHADER
:
6642 stgp
= (struct st_geometry_program
*)prog
;
6643 stgp
->glsl_to_tgsi
= v
;
6645 case GL_TESS_CONTROL_SHADER
:
6646 sttcp
= (struct st_tessctrl_program
*)prog
;
6647 sttcp
->glsl_to_tgsi
= v
;
6649 case GL_TESS_EVALUATION_SHADER
:
6650 sttep
= (struct st_tesseval_program
*)prog
;
6651 sttep
->glsl_to_tgsi
= v
;
6653 case GL_COMPUTE_SHADER
:
6654 stcp
= (struct st_compute_program
*)prog
;
6655 stcp
->glsl_to_tgsi
= v
;
6658 assert(!"should not be reached");
6665 static struct gl_program
*
6666 get_mesa_program(struct gl_context
*ctx
,
6667 struct gl_shader_program
*shader_program
,
6668 struct gl_shader
*shader
)
6670 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6671 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6672 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6673 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6674 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6675 /* TODO only for GLSL VS/FS for now: */
6676 switch (shader
->Type
) {
6677 case GL_VERTEX_SHADER
:
6678 case GL_FRAGMENT_SHADER
:
6679 return st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6684 return get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6691 st_dump_program_for_shader_db(struct gl_context
*ctx
,
6692 struct gl_shader_program
*prog
)
6694 /* Dump only successfully compiled and linked shaders to the specified
6695 * file. This is for shader-db.
6697 * These options allow some pre-processing of shaders while dumping,
6698 * because some apps have ill-formed shaders.
6700 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
6701 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
6703 if (dump_filename
&& prog
->Name
!= 0) {
6704 FILE *f
= fopen(dump_filename
, "a");
6707 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
6708 const struct gl_shader
*sh
= prog
->Shaders
[i
];
6710 bool skip_version
= false;
6715 source
= sh
->Source
;
6717 /* This string mustn't be changed. shader-db uses it to find
6718 * where the shader begins.
6720 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
6721 _mesa_shader_stage_to_string(sh
->Stage
),
6724 /* Dump the forced version if set. */
6725 if (ctx
->Const
.ForceGLSLVersion
) {
6726 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
6727 skip_version
= true;
6730 /* Insert directives (optional). */
6731 if (insert_directives
) {
6732 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
6733 fprintf(f
, "#version %i\n", prog
->Version
);
6734 fprintf(f
, "%s\n", insert_directives
);
6735 skip_version
= true;
6738 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
6739 const char *next_line
= strstr(source
, "\n");
6742 source
= next_line
+ 1;
6747 fprintf(f
, "%s", source
);
6757 * Called via ctx->Driver.LinkShader()
6758 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6759 * with code lowering and other optimizations.
6762 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6764 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6765 assert(prog
->LinkStatus
);
6767 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6768 if (prog
->_LinkedShaders
[i
] == NULL
)
6772 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6773 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6774 const struct gl_shader_compiler_options
*options
=
6775 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6776 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6777 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6778 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6779 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6780 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6782 /* If there are forms of indirect addressing that the driver
6783 * cannot handle, perform the lowering pass.
6785 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6786 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6787 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6788 options
->EmitNoIndirectInput
,
6789 options
->EmitNoIndirectOutput
,
6790 options
->EmitNoIndirectTemp
,
6791 options
->EmitNoIndirectUniform
);
6794 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6795 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6796 LOWER_UNPACK_SNORM_2x16
|
6797 LOWER_PACK_UNORM_2x16
|
6798 LOWER_UNPACK_UNORM_2x16
|
6799 LOWER_PACK_SNORM_4x8
|
6800 LOWER_UNPACK_SNORM_4x8
|
6801 LOWER_UNPACK_UNORM_4x8
|
6802 LOWER_PACK_UNORM_4x8
;
6804 if (ctx
->Extensions
.ARB_gpu_shader5
)
6805 lower_inst
|= LOWER_PACK_USE_BFI
|
6807 if (!ctx
->st
->has_half_float_packing
)
6808 lower_inst
|= LOWER_PACK_HALF_2x16
|
6809 LOWER_UNPACK_HALF_2x16
;
6811 lower_packing_builtins(ir
, lower_inst
);
6814 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6815 lower_offset_arrays(ir
);
6816 do_mat_op_to_vec(ir
);
6817 lower_instructions(ir
,
6823 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6826 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6827 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6828 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6829 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6831 do_vec_index_to_cond_assign(ir
);
6832 lower_vector_insert(ir
, true);
6833 lower_quadop_vector(ir
, false);
6835 if (options
->MaxIfDepth
== 0) {
6842 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6844 progress
= do_common_optimization(ir
, true, true, options
,
6845 ctx
->Const
.NativeIntegers
)
6848 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6852 validate_ir_tree(ir
);
6855 build_program_resource_list(ctx
, prog
);
6857 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6858 struct gl_program
*linked_prog
;
6860 if (prog
->_LinkedShaders
[i
] == NULL
)
6863 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6866 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6868 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6869 _mesa_shader_stage_to_program(i
),
6871 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6873 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6878 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6881 st_dump_program_for_shader_db(ctx
, prog
);
6886 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6887 const GLuint outputMapping
[],
6888 struct pipe_stream_output_info
*so
)
6890 struct gl_transform_feedback_info
*info
=
6891 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6892 st_translate_stream_output_info2(info
, outputMapping
, so
);
6896 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
6897 const GLuint outputMapping
[],
6898 struct pipe_stream_output_info
*so
)
6902 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6903 so
->output
[i
].register_index
=
6904 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6905 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6906 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6907 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6908 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6909 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6912 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6913 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6915 so
->num_outputs
= info
->NumOutputs
;