2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
70 #include "util/u_atomic.h"
71 #include "util/simple_mtx.h"
75 /* Prepare to make it possible to specify log file */
76 static std::ofstream stats_log
;
78 /* Helper function to check whether we want to write some statistics
79 * of the shader conversion.
82 static simple_mtx_t print_stats_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
84 static inline bool print_stats_enabled ()
86 static int stats_enabled
= 0;
89 simple_mtx_lock(&print_stats_mutex
);
91 const char *stats_filename
= getenv("GLSL_TO_TGSI_PRINT_STATS");
93 bool write_header
= std::ifstream(stats_filename
).fail();
94 stats_log
.open(stats_filename
, std::ios_base::out
| std::ios_base::app
);
95 stats_enabled
= stats_log
.good() ? 1 : -1;
97 stats_log
<< "arrays,temps,temps in arrays,total,instructions\n";
102 simple_mtx_unlock(&print_stats_mutex
);
104 return stats_enabled
> 0;
106 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
108 #define PRINT_STATS(X)
112 static unsigned is_precise(const ir_variable
*ir
)
116 return ir
->data
.precise
|| ir
->data
.invariant
;
119 class variable_storage
{
120 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
123 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
124 unsigned array_id
= 0)
125 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
127 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
130 gl_register_file file
;
133 /* Explicit component location. This is given in terms of the GLSL-style
134 * swizzles where each double is a single component, i.e. for 64-bit types
135 * it can only be 0 or 1.
138 ir_variable
*var
; /* variable that maps to this, if any */
142 class immediate_storage
: public exec_node
{
144 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
146 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
147 this->size32
= size32
;
151 /* doubles are stored across 2 gl_constant_values */
152 gl_constant_value values
[4];
153 int size32
; /**< Number of 32-bit components (1-4) */
154 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
157 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
158 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
162 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
165 unsigned gs_out_streams
;
166 enum glsl_interp_mode interp
;
167 enum glsl_base_type base_type
;
168 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
172 static struct inout_decl
*
173 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
175 assert(array_id
!= 0);
177 for (unsigned i
= 0; i
< count
; i
++) {
178 struct inout_decl
*decl
= &decls
[i
];
180 if (array_id
== decl
->array_id
) {
188 static enum glsl_base_type
189 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
192 return GLSL_TYPE_ERROR
;
193 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
195 return decl
->base_type
;
196 return GLSL_TYPE_ERROR
;
199 struct hwatomic_decl
{
206 struct glsl_to_tgsi_visitor
: public ir_visitor
{
208 glsl_to_tgsi_visitor();
209 ~glsl_to_tgsi_visitor();
211 struct gl_context
*ctx
;
212 struct gl_program
*prog
;
213 struct gl_shader_program
*shader_program
;
214 struct gl_linked_shader
*shader
;
215 struct gl_shader_compiler_options
*options
;
219 unsigned *array_sizes
;
220 unsigned max_num_arrays
;
223 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
225 unsigned num_input_arrays
;
226 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
227 unsigned num_outputs
;
228 unsigned num_output_arrays
;
230 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
231 unsigned num_atomics
;
232 unsigned num_atomic_arrays
;
233 int num_address_regs
;
234 uint32_t samplers_used
;
235 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
236 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
238 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
239 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
240 bool image_wr
[PIPE_MAX_SHADER_IMAGES
];
241 bool indirect_addr_consts
;
242 int wpos_transform_const
;
244 bool native_integers
;
247 bool use_shared_memory
;
252 variable_storage
*find_variable_storage(ir_variable
*var
);
254 int add_constant(gl_register_file file
, gl_constant_value values
[8],
255 int size
, GLenum datatype
, uint16_t *swizzle_out
);
257 st_src_reg
get_temp(const glsl_type
*type
);
258 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
260 st_src_reg
st_src_reg_for_double(double val
);
261 st_src_reg
st_src_reg_for_float(float val
);
262 st_src_reg
st_src_reg_for_int(int val
);
263 st_src_reg
st_src_reg_for_int64(int64_t val
);
264 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
267 * \name Visit methods
269 * As typical for the visitor pattern, there must be one \c visit method for
270 * each concrete subclass of \c ir_instruction. Virtual base classes within
271 * the hierarchy should not have \c visit methods.
274 virtual void visit(ir_variable
*);
275 virtual void visit(ir_loop
*);
276 virtual void visit(ir_loop_jump
*);
277 virtual void visit(ir_function_signature
*);
278 virtual void visit(ir_function
*);
279 virtual void visit(ir_expression
*);
280 virtual void visit(ir_swizzle
*);
281 virtual void visit(ir_dereference_variable
*);
282 virtual void visit(ir_dereference_array
*);
283 virtual void visit(ir_dereference_record
*);
284 virtual void visit(ir_assignment
*);
285 virtual void visit(ir_constant
*);
286 virtual void visit(ir_call
*);
287 virtual void visit(ir_return
*);
288 virtual void visit(ir_discard
*);
289 virtual void visit(ir_texture
*);
290 virtual void visit(ir_if
*);
291 virtual void visit(ir_emit_vertex
*);
292 virtual void visit(ir_end_primitive
*);
293 virtual void visit(ir_barrier
*);
296 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
298 void visit_atomic_counter_intrinsic(ir_call
*);
299 void visit_ssbo_intrinsic(ir_call
*);
300 void visit_membar_intrinsic(ir_call
*);
301 void visit_shared_intrinsic(ir_call
*);
302 void visit_image_intrinsic(ir_call
*);
303 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
307 /** List of variable_storage */
308 struct hash_table
*variables
;
310 /** List of immediate_storage */
311 exec_list immediates
;
312 unsigned num_immediates
;
314 /** List of glsl_to_tgsi_instruction */
315 exec_list instructions
;
317 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
318 st_dst_reg dst
= undef_dst
,
319 st_src_reg src0
= undef_src
,
320 st_src_reg src1
= undef_src
,
321 st_src_reg src2
= undef_src
,
322 st_src_reg src3
= undef_src
);
324 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
325 st_dst_reg dst
, st_dst_reg dst1
,
326 st_src_reg src0
= undef_src
,
327 st_src_reg src1
= undef_src
,
328 st_src_reg src2
= undef_src
,
329 st_src_reg src3
= undef_src
);
331 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
333 st_src_reg src0
, st_src_reg src1
);
336 * Emit the correct dot-product instruction for the type of arguments
338 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
344 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
345 st_dst_reg dst
, st_src_reg src0
);
347 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
348 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
350 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
352 void get_deref_offsets(ir_dereference
*ir
,
353 unsigned *array_size
,
358 void calc_deref_offsets(ir_dereference
*tail
,
359 unsigned *array_elements
,
361 st_src_reg
*indirect
,
363 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
364 bool handle_bound_deref(ir_dereference
*ir
);
366 bool try_emit_mad(ir_expression
*ir
,
368 bool try_emit_mad_for_and_not(ir_expression
*ir
,
371 void emit_swz(ir_expression
*ir
);
373 bool process_move_condition(ir_rvalue
*ir
);
375 void simplify_cmp(void);
377 void rename_temp_registers(struct rename_reg_pair
*renames
);
378 void get_first_temp_read(int *first_reads
);
379 void get_first_temp_write(int *first_writes
);
380 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
381 void get_last_temp_write(int *last_writes
);
383 void copy_propagate(void);
384 int eliminate_dead_code(void);
386 void split_arrays(void);
387 void merge_two_dsts(void);
388 void merge_registers(void);
389 void renumber_registers(void);
391 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
392 st_dst_reg
*l
, st_src_reg
*r
,
393 st_src_reg
*cond
, bool cond_swap
);
400 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
402 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
404 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
408 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
412 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
416 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
419 prog
->data
->LinkStatus
= LINKING_FAILURE
;
423 swizzle_for_size(int size
)
425 static const int size_swizzles
[4] = {
426 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
427 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
428 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
429 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
432 assert((size
>= 1) && (size
<= 4));
433 return size_swizzles
[size
- 1];
437 glsl_to_tgsi_instruction
*
438 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
439 st_dst_reg dst
, st_dst_reg dst1
,
440 st_src_reg src0
, st_src_reg src1
,
441 st_src_reg src2
, st_src_reg src3
)
443 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
444 int num_reladdr
= 0, i
, j
;
445 bool dst_is_64bit
[2];
447 op
= get_opcode(op
, dst
, src0
, src1
);
449 /* If we have to do relative addressing, we want to load the ARL
450 * reg directly for one of the regs, and preload the other reladdr
451 * sources into temps.
453 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
454 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
455 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
456 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
457 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
458 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
460 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
461 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
462 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
463 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
465 if (dst
.reladdr
|| dst
.reladdr2
) {
467 emit_arl(ir
, address_reg
, *dst
.reladdr
);
469 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
473 assert(num_reladdr
== 0);
475 /* inst->op has only 8 bits. */
476 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
479 inst
->precise
= this->precise
;
480 inst
->info
= tgsi_get_opcode_info(op
);
487 inst
->is_64bit_expanded
= false;
490 inst
->tex_offsets
= NULL
;
491 inst
->tex_offset_num_offset
= 0;
493 inst
->tex_shadow
= 0;
494 /* default to float, for paths where this is not initialized
495 * (since 0==UINT which is likely wrong):
497 inst
->tex_type
= GLSL_TYPE_FLOAT
;
499 /* Update indirect addressing status used by TGSI */
500 if (dst
.reladdr
|| dst
.reladdr2
) {
502 case PROGRAM_STATE_VAR
:
503 case PROGRAM_CONSTANT
:
504 case PROGRAM_UNIFORM
:
505 this->indirect_addr_consts
= true;
507 case PROGRAM_IMMEDIATE
:
508 assert(!"immediates should not have indirect addressing");
515 for (i
= 0; i
< 4; i
++) {
516 if (inst
->src
[i
].reladdr
) {
517 switch (inst
->src
[i
].file
) {
518 case PROGRAM_STATE_VAR
:
519 case PROGRAM_CONSTANT
:
520 case PROGRAM_UNIFORM
:
521 this->indirect_addr_consts
= true;
523 case PROGRAM_IMMEDIATE
:
524 assert(!"immediates should not have indirect addressing");
534 * This section contains the double processing.
535 * GLSL just represents doubles as single channel values,
536 * however most HW and TGSI represent doubles as pairs of register channels.
538 * so we have to fixup destination writemask/index and src swizzle/indexes.
539 * dest writemasks need to translate from single channel write mask
540 * to a dual-channel writemask, but also need to modify the index,
541 * if we are touching the Z,W fields in the pre-translated writemask.
543 * src channels have similiar index modifications along with swizzle
544 * changes to we pick the XY, ZW pairs from the correct index.
546 * GLSL [0].x -> TGSI [0].xy
547 * GLSL [0].y -> TGSI [0].zw
548 * GLSL [0].z -> TGSI [1].xy
549 * GLSL [0].w -> TGSI [1].zw
551 for (j
= 0; j
< 2; j
++) {
552 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
553 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
554 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
555 enum glsl_base_type type
= find_array_type(this->outputs
,
557 inst
->dst
[j
].array_id
);
558 if (glsl_base_type_is_64bit(type
))
559 dst_is_64bit
[j
] = true;
563 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
564 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
565 glsl_to_tgsi_instruction
*dinst
= NULL
;
566 int initial_src_swz
[4], initial_src_idx
[4];
567 int initial_dst_idx
[2], initial_dst_writemask
[2];
568 /* select the writemask for dst0 or dst1 */
569 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
570 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
572 /* copy out the writemask, index and swizzles for all src/dsts. */
573 for (j
= 0; j
< 2; j
++) {
574 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
575 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
578 for (j
= 0; j
< 4; j
++) {
579 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
580 initial_src_idx
[j
] = inst
->src
[j
].index
;
584 * scan all the components in the dst writemask
585 * generate an instruction for each of them if required.
590 int i
= u_bit_scan(&writemask
);
592 /* before emitting the instruction, see if we have to adjust
593 * load / store address */
594 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
595 inst
->op
== TGSI_OPCODE_STORE
) &&
596 addr
.file
== PROGRAM_UNDEFINED
) {
597 /* We have to advance the buffer address by 16 */
598 addr
= get_temp(glsl_type::uint_type
);
599 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
600 inst
->src
[0], st_src_reg_for_int(16));
603 /* first time use previous instruction */
607 /* create a new instructions for subsequent attempts */
608 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
613 this->instructions
.push_tail(dinst
);
614 dinst
->is_64bit_expanded
= true;
616 /* modify the destination if we are splitting */
617 for (j
= 0; j
< 2; j
++) {
618 if (dst_is_64bit
[j
]) {
619 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
620 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
622 if (dinst
->op
== TGSI_OPCODE_LOAD
||
623 dinst
->op
== TGSI_OPCODE_STORE
)
624 dinst
->src
[0] = addr
;
625 if (dinst
->op
!= TGSI_OPCODE_STORE
)
626 dinst
->dst
[j
].index
++;
629 /* if we aren't writing to a double, just get the bit of the
630 * initial writemask for this channel
632 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
636 /* modify the src registers */
637 for (j
= 0; j
< 4; j
++) {
638 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
640 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
641 dinst
->src
[j
].index
= initial_src_idx
[j
];
643 dinst
->src
[j
].double_reg2
= true;
644 dinst
->src
[j
].index
++;
648 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
649 SWIZZLE_Z
, SWIZZLE_W
);
651 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
652 SWIZZLE_X
, SWIZZLE_Y
);
655 /* some opcodes are special case in what they use as sources
656 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
659 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
660 op
== TGSI_OPCODE_I2D
||
661 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
662 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
663 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
664 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
671 this->instructions
.push_tail(inst
);
678 glsl_to_tgsi_instruction
*
679 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
681 st_src_reg src0
, st_src_reg src1
,
682 st_src_reg src2
, st_src_reg src3
)
684 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
688 * Determines whether to use an integer, unsigned integer, or float opcode
689 * based on the operands and input opcode, then emits the result.
692 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
694 st_src_reg src0
, st_src_reg src1
)
696 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
698 if (op
== TGSI_OPCODE_MOV
)
701 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
702 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
703 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
704 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
706 if (is_resource_instruction(op
))
708 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
709 type
= GLSL_TYPE_INT64
;
710 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
711 type
= GLSL_TYPE_UINT64
;
712 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
713 type
= GLSL_TYPE_DOUBLE
;
714 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
715 type
= GLSL_TYPE_FLOAT
;
716 else if (native_integers
)
717 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
719 #define case7(c, f, i, u, d, i64, ui64) \
720 case TGSI_OPCODE_##c: \
721 if (type == GLSL_TYPE_UINT64) \
722 op = TGSI_OPCODE_##ui64; \
723 else if (type == GLSL_TYPE_INT64) \
724 op = TGSI_OPCODE_##i64; \
725 else if (type == GLSL_TYPE_DOUBLE) \
726 op = TGSI_OPCODE_##d; \
727 else if (type == GLSL_TYPE_INT) \
728 op = TGSI_OPCODE_##i; \
729 else if (type == GLSL_TYPE_UINT) \
730 op = TGSI_OPCODE_##u; \
732 op = TGSI_OPCODE_##f; \
735 #define casecomp(c, f, i, u, d, i64, ui64) \
736 case TGSI_OPCODE_##c: \
737 if (type == GLSL_TYPE_INT64) \
738 op = TGSI_OPCODE_##i64; \
739 else if (type == GLSL_TYPE_UINT64) \
740 op = TGSI_OPCODE_##ui64; \
741 else if (type == GLSL_TYPE_DOUBLE) \
742 op = TGSI_OPCODE_##d; \
743 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
744 op = TGSI_OPCODE_##i; \
745 else if (type == GLSL_TYPE_UINT) \
746 op = TGSI_OPCODE_##u; \
747 else if (native_integers) \
748 op = TGSI_OPCODE_##f; \
750 op = TGSI_OPCODE_##c; \
754 /* Some instructions are initially selected without considering the type.
755 * This fixes the type:
757 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
759 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
760 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
761 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
762 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
763 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
764 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
765 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
766 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
767 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
768 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
769 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
770 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
771 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
772 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
773 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
774 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
776 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
777 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
778 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
779 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
780 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
781 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
782 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
783 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
784 case7(ATOMUADD
,ATOMFADD
,ATOMUADD
,ATOMUADD
,LAST
, LAST
, LAST
);
786 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
787 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
788 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
789 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
795 assert(op
!= TGSI_OPCODE_LAST
);
799 glsl_to_tgsi_instruction
*
800 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
801 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
804 static const enum tgsi_opcode dot_opcodes
[] = {
805 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
808 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
812 * Emits TGSI scalar opcodes to produce unique answers across channels.
814 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
815 * channel determines the result across all channels. So to do a vec4
816 * of this operation, we want to emit a scalar per source channel used
817 * to produce dest channels.
820 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
822 st_src_reg orig_src0
, st_src_reg orig_src1
)
825 int done_mask
= ~dst
.writemask
;
827 /* TGSI RCP is a scalar operation splatting results to all channels,
828 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
831 for (i
= 0; i
< 4; i
++) {
832 GLuint this_mask
= (1 << i
);
833 st_src_reg src0
= orig_src0
;
834 st_src_reg src1
= orig_src1
;
836 if (done_mask
& this_mask
)
839 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
840 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
841 for (j
= i
+ 1; j
< 4; j
++) {
842 /* If there is another enabled component in the destination that is
843 * derived from the same inputs, generate its value on this pass as
846 if (!(done_mask
& (1 << j
)) &&
847 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
848 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
849 this_mask
|= (1 << j
);
852 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
853 src0_swiz
, src0_swiz
);
854 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
855 src1_swiz
, src1_swiz
);
857 dst
.writemask
= this_mask
;
858 emit_asm(ir
, op
, dst
, src0
, src1
);
859 done_mask
|= this_mask
;
864 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
865 st_dst_reg dst
, st_src_reg src0
)
867 st_src_reg undef
= undef_src
;
869 undef
.swizzle
= SWIZZLE_XXXX
;
871 emit_scalar(ir
, op
, dst
, src0
, undef
);
875 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
876 st_dst_reg dst
, st_src_reg src0
)
878 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
880 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
881 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
884 op
= TGSI_OPCODE_UARL
;
887 assert(dst
.file
== PROGRAM_ADDRESS
);
888 if (dst
.index
>= this->num_address_regs
)
889 this->num_address_regs
= dst
.index
+ 1;
891 emit_asm(NULL
, op
, dst
, src0
);
895 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
896 gl_constant_value values
[8], int size
,
898 uint16_t *swizzle_out
)
900 if (file
== PROGRAM_CONSTANT
) {
901 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
902 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
903 values
, size
, datatype
,
906 *swizzle_out
= swizzle
;
910 assert(file
== PROGRAM_IMMEDIATE
);
913 immediate_storage
*entry
;
914 int size32
= size
* ((datatype
== GL_DOUBLE
||
915 datatype
== GL_INT64_ARB
||
916 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
919 /* Search immediate storage to see if we already have an identical
920 * immediate that we can use instead of adding a duplicate entry.
922 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
923 immediate_storage
*tmp
= entry
;
925 for (i
= 0; i
* 4 < size32
; i
++) {
926 int slot_size
= MIN2(size32
- (i
* 4), 4);
927 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
929 if (memcmp(tmp
->values
, &values
[i
* 4],
930 slot_size
* sizeof(gl_constant_value
)))
933 /* Everything matches, keep going until the full size is matched */
934 tmp
= (immediate_storage
*)tmp
->next
;
937 /* The full value matched */
944 for (i
= 0; i
* 4 < size32
; i
++) {
945 int slot_size
= MIN2(size32
- (i
* 4), 4);
946 /* Add this immediate to the list. */
947 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
948 slot_size
, datatype
);
949 this->immediates
.push_tail(entry
);
950 this->num_immediates
++;
956 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
958 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
959 union gl_constant_value uval
;
962 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
968 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
970 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
971 union gl_constant_value uval
[2];
973 memcpy(uval
, &val
, sizeof(uval
));
974 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
975 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
980 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
982 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
983 union gl_constant_value uval
;
985 assert(native_integers
);
988 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
994 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
996 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
997 union gl_constant_value uval
[2];
999 memcpy(uval
, &val
, sizeof(uval
));
1000 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1001 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1007 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1009 if (native_integers
)
1010 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1011 st_src_reg_for_int(val
);
1013 return st_src_reg_for_float(val
);
1017 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1019 return type
->count_attribute_slots(is_vs_input
);
1023 type_size(const struct glsl_type
*type
)
1025 return type
->count_attribute_slots(false);
1029 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
1030 exec_list
*instructions
, ir_constant
*access
)
1033 * emit_asm() might have actually split the op into pieces, e.g. for
1034 * double stores. We have to go back and fix up all the generated ops.
1036 enum tgsi_opcode op
= inst
->op
;
1038 inst
->resource
= *buf
;
1040 inst
->buffer_access
= access
->value
.u
[0];
1042 if (inst
== instructions
->get_head_raw())
1044 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1046 if (inst
->op
== TGSI_OPCODE_UADD
) {
1047 if (inst
== instructions
->get_head_raw())
1049 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1051 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1055 * If the given GLSL type is an array or matrix or a structure containing
1056 * an array/matrix member, return true. Else return false.
1058 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1059 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1060 * we have an array that might be indexed with a variable, we need to use
1061 * the later storage type.
1064 type_has_array_or_matrix(const glsl_type
*type
)
1066 if (type
->is_array() || type
->is_matrix())
1069 if (type
->is_record()) {
1070 for (unsigned i
= 0; i
< type
->length
; i
++) {
1071 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1082 * In the initial pass of codegen, we assign temporary numbers to
1083 * intermediate results. (not SSA -- variable assignments will reuse
1087 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1091 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1096 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1097 if (next_array
>= max_num_arrays
) {
1098 max_num_arrays
+= 32;
1099 array_sizes
= (unsigned*)
1100 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1103 src
.file
= PROGRAM_ARRAY
;
1105 src
.array_id
= next_array
+ 1;
1106 array_sizes
[next_array
] = type_size(type
);
1110 src
.file
= PROGRAM_TEMPORARY
;
1111 src
.index
= next_temp
;
1112 next_temp
+= type_size(type
);
1115 if (type
->is_array() || type
->is_record()) {
1116 src
.swizzle
= SWIZZLE_NOOP
;
1118 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1125 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1127 struct hash_entry
*entry
;
1129 entry
= _mesa_hash_table_search(this->variables
, var
);
1133 return (variable_storage
*)entry
->data
;
1137 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1139 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1140 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1141 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1144 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1146 const ir_state_slot
*const slots
= ir
->get_state_slots();
1147 assert(slots
!= NULL
);
1149 /* Check if this statevar's setup in the STATE file exactly
1150 * matches how we'll want to reference it as a
1151 * struct/array/whatever. If not, then we need to move it into
1152 * temporary storage and hope that it'll get copy-propagated
1155 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1156 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1161 variable_storage
*storage
;
1163 if (i
== ir
->get_num_state_slots()) {
1164 /* We'll set the index later. */
1165 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1167 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1171 /* The variable_storage constructor allocates slots based on the size
1172 * of the type. However, this had better match the number of state
1173 * elements that we're going to copy into the new temporary.
1175 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1177 dst
= st_dst_reg(get_temp(ir
->type
));
1179 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1182 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1186 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1187 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1190 if (storage
->file
== PROGRAM_STATE_VAR
) {
1191 if (storage
->index
== -1) {
1192 storage
->index
= index
;
1194 assert(index
== storage
->index
+ (int)i
);
1197 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1198 * the data being moved since MOV does not care about the type of
1199 * data it is moving, and we don't want to declare registers with
1200 * array or struct types.
1202 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1203 src
.swizzle
= slots
[i
].swizzle
;
1204 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1205 /* even a float takes up a whole vec4 reg in a struct/array. */
1210 if (storage
->file
== PROGRAM_TEMPORARY
&&
1211 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1212 fail_link(this->shader_program
,
1213 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1214 ir
->name
, dst
.index
- storage
->index
,
1215 type_size(ir
->type
));
1221 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1223 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1225 visit_exec_list(&ir
->body_instructions
, this);
1227 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1231 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1234 case ir_loop_jump::jump_break
:
1235 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1237 case ir_loop_jump::jump_continue
:
1238 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1245 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1252 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1254 /* Ignore function bodies other than main() -- we shouldn't see calls to
1255 * them since they should all be inlined before we get to glsl_to_tgsi.
1257 if (strcmp(ir
->name
, "main") == 0) {
1258 const ir_function_signature
*sig
;
1261 sig
= ir
->matching_signature(NULL
, &empty
, false);
1265 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1272 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1274 int nonmul_operand
= 1 - mul_operand
;
1276 st_dst_reg result_dst
;
1278 // there is no TGSI opcode for this
1279 if (ir
->type
->is_integer_64())
1282 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1283 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1286 expr
->operands
[0]->accept(this);
1288 expr
->operands
[1]->accept(this);
1290 ir
->operands
[nonmul_operand
]->accept(this);
1293 this->result
= get_temp(ir
->type
);
1294 result_dst
= st_dst_reg(this->result
);
1295 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1296 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1302 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1304 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1305 * implemented using multiplication, and logical-or is implemented using
1306 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1307 * As result, the logical expression (a & !b) can be rewritten as:
1311 * - (a * 1) - (a * b)
1315 * This final expression can be implemented as a single MAD(a, -b, a)
1319 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1322 const int other_operand
= 1 - try_operand
;
1325 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1326 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1329 ir
->operands
[other_operand
]->accept(this);
1331 expr
->operands
[0]->accept(this);
1334 b
.negate
= ~b
.negate
;
1336 this->result
= get_temp(ir
->type
);
1337 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1343 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1344 st_src_reg
*reg
, int *num_reladdr
)
1346 if (!reg
->reladdr
&& !reg
->reladdr2
)
1350 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1352 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1354 if (*num_reladdr
!= 1) {
1355 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1357 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1365 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1367 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1369 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1371 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1372 if (try_emit_mad(ir
, 1))
1374 if (try_emit_mad(ir
, 0))
1378 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1380 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1381 if (try_emit_mad_for_and_not(ir
, 1))
1383 if (try_emit_mad_for_and_not(ir
, 0))
1387 if (ir
->operation
== ir_quadop_vector
)
1388 assert(!"ir_quadop_vector should have been lowered");
1390 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1391 this->result
.file
= PROGRAM_UNDEFINED
;
1392 ir
->operands
[operand
]->accept(this);
1393 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1394 printf("Failed to get tree for expression operand:\n");
1395 ir
->operands
[operand
]->print();
1399 op
[operand
] = this->result
;
1401 /* Matrix expression operands should have been broken down to vector
1402 * operations already.
1404 assert(!ir
->operands
[operand
]->type
->is_matrix());
1407 visit_expression(ir
, op
);
1410 /* The non-recursive part of the expression visitor lives in a separate
1411 * function and should be prevented from being inlined, to avoid a stack
1412 * explosion when deeply nested expressions are visited.
1415 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1417 st_src_reg result_src
;
1418 st_dst_reg result_dst
;
1420 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1421 if (ir
->operands
[1] &&
1422 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1423 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1424 st_src_reg
*swz_op
= NULL
;
1425 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1426 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1428 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1429 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1433 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1434 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1435 swizzle_x
, swizzle_x
);
1437 vector_elements
= MAX2(vector_elements
,
1438 ir
->operands
[1]->type
->vector_elements
);
1440 if (ir
->operands
[2] &&
1441 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1442 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1443 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1444 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1445 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1446 swizzle_x
, swizzle_x
);
1449 this->result
.file
= PROGRAM_UNDEFINED
;
1451 /* Storage for our result. Ideally for an assignment we'd be using
1452 * the actual storage for the result here, instead.
1454 result_src
= get_temp(ir
->type
);
1455 /* convenience for the emit functions below. */
1456 result_dst
= st_dst_reg(result_src
);
1457 /* Limit writes to the channels that will be used by result_src later.
1458 * This does limit this temp's use as a temporary for multi-instruction
1461 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1463 switch (ir
->operation
) {
1464 case ir_unop_logic_not
:
1465 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1466 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1468 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1469 * older GPUs implement SEQ using multiple instructions (i915 uses two
1470 * SGE instructions and a MUL instruction). Since our logic values are
1471 * 0.0 and 1.0, 1-x also implements !x.
1473 op
[0].negate
= ~op
[0].negate
;
1474 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1475 st_src_reg_for_float(1.0));
1479 if (result_dst
.type
== GLSL_TYPE_INT64
||
1480 result_dst
.type
== GLSL_TYPE_UINT64
)
1481 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1482 else if (result_dst
.type
== GLSL_TYPE_INT
||
1483 result_dst
.type
== GLSL_TYPE_UINT
)
1484 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1485 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1486 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1488 op
[0].negate
= ~op
[0].negate
;
1492 case ir_unop_subroutine_to_int
:
1493 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1496 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1497 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1498 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1499 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1500 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1501 result_dst
.type
== GLSL_TYPE_UINT64
)
1502 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1504 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1507 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1510 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1514 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1517 assert(!"not reached: should be handled by exp_to_exp2");
1520 assert(!"not reached: should be handled by log_to_log2");
1523 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1526 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1529 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1531 case ir_unop_saturate
: {
1532 glsl_to_tgsi_instruction
*inst
;
1533 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1534 inst
->saturate
= true;
1539 case ir_unop_dFdx_coarse
:
1540 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1542 case ir_unop_dFdx_fine
:
1543 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1546 case ir_unop_dFdy_coarse
:
1547 case ir_unop_dFdy_fine
:
1549 /* The X component contains 1 or -1 depending on whether the framebuffer
1550 * is a FBO or the window system buffer, respectively.
1551 * It is then multiplied with the source operand of DDY.
1553 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1554 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1556 unsigned transform_y_index
=
1557 _mesa_add_state_reference(this->prog
->Parameters
,
1560 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1562 glsl_type::vec4_type
);
1563 transform_y
.swizzle
= SWIZZLE_XXXX
;
1565 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1567 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1568 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1569 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1573 case ir_unop_frexp_sig
:
1574 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1577 case ir_unop_frexp_exp
:
1578 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1581 case ir_unop_noise
: {
1582 /* At some point, a motivated person could add a better
1583 * implementation of noise. Currently not even the nvidia
1584 * binary drivers do anything more than this. In any case, the
1585 * place to do this is in the GL state tracker, not the poor
1588 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1593 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1596 op
[1].negate
= ~op
[1].negate
;
1597 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1601 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1604 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1607 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1608 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1610 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1614 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1616 case ir_binop_gequal
:
1617 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1619 case ir_binop_equal
:
1620 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1622 case ir_binop_nequal
:
1623 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1625 case ir_binop_all_equal
:
1626 /* "==" operator producing a scalar boolean. */
1627 if (ir
->operands
[0]->type
->is_vector() ||
1628 ir
->operands
[1]->type
->is_vector()) {
1629 st_src_reg temp
= get_temp(native_integers
?
1630 glsl_type::uvec4_type
:
1631 glsl_type::vec4_type
);
1633 if (native_integers
) {
1634 st_dst_reg temp_dst
= st_dst_reg(temp
);
1635 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1637 if (ir
->operands
[0]->type
->is_boolean() &&
1638 ir
->operands
[1]->as_constant() &&
1639 ir
->operands
[1]->as_constant()->is_one()) {
1640 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1642 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1645 /* Emit 1-3 AND operations to combine the SEQ results. */
1646 switch (ir
->operands
[0]->type
->vector_elements
) {
1650 temp_dst
.writemask
= WRITEMASK_Y
;
1651 temp1
.swizzle
= SWIZZLE_YYYY
;
1652 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1653 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1656 temp_dst
.writemask
= WRITEMASK_X
;
1657 temp1
.swizzle
= SWIZZLE_XXXX
;
1658 temp2
.swizzle
= SWIZZLE_YYYY
;
1659 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1660 temp_dst
.writemask
= WRITEMASK_Y
;
1661 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1662 temp2
.swizzle
= SWIZZLE_WWWW
;
1663 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1666 temp1
.swizzle
= SWIZZLE_XXXX
;
1667 temp2
.swizzle
= SWIZZLE_YYYY
;
1668 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1670 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1672 /* After the dot-product, the value will be an integer on the
1673 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1675 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1677 /* Negating the result of the dot-product gives values on the range
1678 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1679 * This is achieved using SGE.
1681 st_src_reg sge_src
= result_src
;
1682 sge_src
.negate
= ~sge_src
.negate
;
1683 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1684 st_src_reg_for_float(0.0));
1687 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1690 case ir_binop_any_nequal
:
1691 /* "!=" operator producing a scalar boolean. */
1692 if (ir
->operands
[0]->type
->is_vector() ||
1693 ir
->operands
[1]->type
->is_vector()) {
1694 st_src_reg temp
= get_temp(native_integers
?
1695 glsl_type::uvec4_type
:
1696 glsl_type::vec4_type
);
1697 if (ir
->operands
[0]->type
->is_boolean() &&
1698 ir
->operands
[1]->as_constant() &&
1699 ir
->operands
[1]->as_constant()->is_zero()) {
1700 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1702 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1705 if (native_integers
) {
1706 st_dst_reg temp_dst
= st_dst_reg(temp
);
1707 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1709 /* Emit 1-3 OR operations to combine the SNE results. */
1710 switch (ir
->operands
[0]->type
->vector_elements
) {
1714 temp_dst
.writemask
= WRITEMASK_Y
;
1715 temp1
.swizzle
= SWIZZLE_YYYY
;
1716 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1717 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1720 temp_dst
.writemask
= WRITEMASK_X
;
1721 temp1
.swizzle
= SWIZZLE_XXXX
;
1722 temp2
.swizzle
= SWIZZLE_YYYY
;
1723 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1724 temp_dst
.writemask
= WRITEMASK_Y
;
1725 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1726 temp2
.swizzle
= SWIZZLE_WWWW
;
1727 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1730 temp1
.swizzle
= SWIZZLE_XXXX
;
1731 temp2
.swizzle
= SWIZZLE_YYYY
;
1732 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1734 /* After the dot-product, the value will be an integer on the
1735 * range [0,4]. Zero stays zero, and positive values become 1.0.
1737 glsl_to_tgsi_instruction
*const dp
=
1738 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1739 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1740 /* The clamping to [0,1] can be done for free in the fragment
1741 * shader with a saturate.
1743 dp
->saturate
= true;
1745 /* Negating the result of the dot-product gives values on the
1746 * range [-4, 0]. Zero stays zero, and negative values become
1747 * 1.0. This achieved using SLT.
1749 st_src_reg slt_src
= result_src
;
1750 slt_src
.negate
= ~slt_src
.negate
;
1751 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1752 st_src_reg_for_float(0.0));
1756 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1760 case ir_binop_logic_xor
:
1761 if (native_integers
)
1762 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1764 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1767 case ir_binop_logic_or
: {
1768 if (native_integers
) {
1769 /* If integers are used as booleans, we can use an actual "or"
1772 assert(native_integers
);
1773 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1775 /* After the addition, the value will be an integer on the
1776 * range [0,2]. Zero stays zero, and positive values become 1.0.
1778 glsl_to_tgsi_instruction
*add
=
1779 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1780 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1781 /* The clamping to [0,1] can be done for free in the fragment
1782 * shader with a saturate if floats are being used as boolean
1785 add
->saturate
= true;
1787 /* Negating the result of the addition gives values on the range
1788 * [-2, 0]. Zero stays zero, and negative values become 1.0
1789 * This is achieved using SLT.
1791 st_src_reg slt_src
= result_src
;
1792 slt_src
.negate
= ~slt_src
.negate
;
1793 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1794 st_src_reg_for_float(0.0));
1800 case ir_binop_logic_and
:
1801 /* If native integers are disabled, the bool args are stored as float 0.0
1802 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1803 * actual AND opcode.
1805 if (native_integers
)
1806 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1808 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1812 assert(ir
->operands
[0]->type
->is_vector());
1813 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1814 emit_dp(ir
, result_dst
, op
[0], op
[1],
1815 ir
->operands
[0]->type
->vector_elements
);
1820 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1822 /* This is the only instruction sequence that makes the game "Risen"
1823 * render correctly. ABS is not required for the game, but since GLSL
1824 * declares negative values as "undefined", allowing us to do whatever
1825 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1828 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1829 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1833 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1836 if (native_integers
) {
1837 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1840 /* fallthrough to next case otherwise */
1842 if (native_integers
) {
1843 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1844 st_src_reg_for_float(1.0));
1847 /* fallthrough to next case otherwise */
1850 case ir_unop_i642u64
:
1851 case ir_unop_u642i64
:
1852 /* Converting between signed and unsigned integers is a no-op. */
1854 result_src
.type
= result_dst
.type
;
1857 if (native_integers
) {
1858 /* Booleans are stored as integers using ~0 for true and 0 for false.
1859 * GLSL requires that int(bool) return 1 for true and 0 for false.
1860 * This conversion is done with AND, but it could be done with NEG.
1862 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1863 st_src_reg_for_int(1));
1865 /* Booleans and integers are both stored as floats when native
1866 * integers are disabled.
1872 if (native_integers
)
1873 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1875 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1878 if (native_integers
)
1879 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1881 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1883 case ir_unop_bitcast_f2i
:
1884 case ir_unop_bitcast_f2u
:
1885 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1886 if (op
[0].negate
|| op
[0].abs
)
1887 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1890 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1893 case ir_unop_bitcast_i2f
:
1894 case ir_unop_bitcast_u2f
:
1896 result_src
.type
= GLSL_TYPE_FLOAT
;
1899 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1900 st_src_reg_for_float(0.0));
1903 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1904 st_src_reg_for_double(0.0));
1907 if (native_integers
)
1908 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1909 st_src_reg_for_int(0));
1911 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1912 st_src_reg_for_float(0.0));
1914 case ir_unop_bitcast_u642d
:
1915 case ir_unop_bitcast_i642d
:
1917 result_src
.type
= GLSL_TYPE_DOUBLE
;
1919 case ir_unop_bitcast_d2i64
:
1921 result_src
.type
= GLSL_TYPE_INT64
;
1923 case ir_unop_bitcast_d2u64
:
1925 result_src
.type
= GLSL_TYPE_UINT64
;
1928 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1931 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1934 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1936 case ir_unop_round_even
:
1937 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1940 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1944 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1947 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1950 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1953 case ir_unop_bit_not
:
1954 if (native_integers
) {
1955 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1959 if (native_integers
) {
1960 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1963 case ir_binop_lshift
:
1964 case ir_binop_rshift
:
1965 if (native_integers
) {
1966 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1967 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1970 if (glsl_base_type_is_64bit(op
[0].type
)) {
1971 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1974 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1975 ->type
->components()));
1976 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1981 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1984 case ir_binop_bit_and
:
1985 if (native_integers
) {
1986 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1989 case ir_binop_bit_xor
:
1990 if (native_integers
) {
1991 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1994 case ir_binop_bit_or
:
1995 if (native_integers
) {
1996 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2000 assert(!"GLSL 1.30 features unsupported");
2003 case ir_binop_ubo_load
: {
2004 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
2005 ir_rvalue
*block
= ir
->operands
[0];
2006 ir_rvalue
*offset
= ir
->operands
[1];
2007 ir_constant
*const_block
= block
->as_constant();
2009 st_src_reg
cbuf(PROGRAM_CONSTANT
,
2010 (const_block
? const_block
->value
.u
[0] + 1 : 1),
2011 ir
->type
->base_type
);
2013 cbuf
.has_index2
= true;
2016 block
->accept(this);
2017 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2018 *cbuf
.reladdr
= this->result
;
2019 emit_arl(ir
, sampler_reladdr
, this->result
);
2022 /* Calculate the surface offset */
2023 offset
->accept(this);
2024 st_src_reg off
= this->result
;
2026 glsl_to_tgsi_instruction
*inst
=
2027 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
2029 if (result_dst
.type
== GLSL_TYPE_BOOL
)
2030 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
2031 st_src_reg_for_int(0));
2033 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
2036 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2037 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2038 unsigned const_offset
= const_offset_ir
?
2039 const_offset_ir
->value
.u
[0] : 0;
2040 unsigned const_block
= const_uniform_block
?
2041 const_uniform_block
->value
.u
[0] + 1 : 1;
2042 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2045 cbuf
.type
= ir
->type
->base_type
;
2046 cbuf
.file
= PROGRAM_CONSTANT
;
2048 cbuf
.reladdr
= NULL
;
2051 cbuf
.index2D
= const_block
;
2053 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2055 if (const_offset_ir
) {
2056 /* Constant index into constant buffer */
2057 cbuf
.reladdr
= NULL
;
2058 cbuf
.index
= const_offset
/ 16;
2060 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2061 st_src_reg offset
= op
[1];
2063 /* The OpenGL spec is written in such a way that accesses with
2064 * non-constant offset are almost always vec4-aligned. The only
2065 * exception to this are members of structs in arrays of structs:
2066 * each struct in an array of structs is at least vec4-aligned,
2067 * but single-element and [ui]vec2 members of the struct may be at
2068 * an offset that is not a multiple of 16 bytes.
2070 * Here, we extract that offset, relying on previous passes to
2071 * always generate offset expressions of the form
2072 * (+ expr constant_offset).
2074 * Note that the std430 layout, which allows more cases of
2075 * alignment less than vec4 in arrays, is not supported for
2076 * uniform blocks, so we do not have to deal with it here.
2078 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2079 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2080 if (const_offset_ir
) {
2081 const_offset
= const_offset_ir
->value
.u
[0];
2082 cbuf
.index
= const_offset
/ 16;
2083 offset_expr
->operands
[0]->accept(this);
2084 offset
= this->result
;
2088 /* Relative/variable index into constant buffer */
2089 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2090 st_src_reg_for_int(4));
2091 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2092 *cbuf
.reladdr
= index_reg
;
2095 if (const_uniform_block
) {
2096 /* Constant constant buffer */
2097 cbuf
.reladdr2
= NULL
;
2099 /* Relative/variable constant buffer */
2100 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2101 *cbuf
.reladdr2
= op
[0];
2103 cbuf
.has_index2
= true;
2105 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2106 if (glsl_base_type_is_64bit(cbuf
.type
))
2107 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2108 const_offset
% 16 / 8,
2109 const_offset
% 16 / 8,
2110 const_offset
% 16 / 8);
2112 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2113 const_offset
% 16 / 4,
2114 const_offset
% 16 / 4,
2115 const_offset
% 16 / 4);
2117 if (ir
->type
->is_boolean()) {
2118 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2119 st_src_reg_for_int(0));
2121 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2127 /* note: we have to reorder the three args here */
2128 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2131 if (this->ctx
->Const
.NativeIntegers
)
2132 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2134 op
[0].negate
= ~op
[0].negate
;
2135 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2138 case ir_triop_bitfield_extract
:
2139 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2141 case ir_quadop_bitfield_insert
:
2142 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2144 case ir_unop_bitfield_reverse
:
2145 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2147 case ir_unop_bit_count
:
2148 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2150 case ir_unop_find_msb
:
2151 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2153 case ir_unop_find_lsb
:
2154 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2156 case ir_binop_imul_high
:
2157 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2160 /* In theory, MAD is incorrect here. */
2162 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2164 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2166 case ir_unop_interpolate_at_centroid
:
2167 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2169 case ir_binop_interpolate_at_offset
: {
2170 /* The y coordinate needs to be flipped for the default fb */
2171 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2172 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2174 unsigned transform_y_index
=
2175 _mesa_add_state_reference(this->prog
->Parameters
,
2178 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2180 glsl_type::vec4_type
);
2181 transform_y
.swizzle
= SWIZZLE_XXXX
;
2183 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2184 st_dst_reg temp_dst
= st_dst_reg(temp
);
2186 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2187 temp_dst
.writemask
= WRITEMASK_Y
;
2188 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2189 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2192 case ir_binop_interpolate_at_sample
:
2193 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2197 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2200 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2203 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2206 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2209 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2212 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2214 case ir_unop_unpack_double_2x32
:
2215 case ir_unop_pack_double_2x32
:
2216 case ir_unop_unpack_int_2x32
:
2217 case ir_unop_pack_int_2x32
:
2218 case ir_unop_unpack_uint_2x32
:
2219 case ir_unop_pack_uint_2x32
:
2220 case ir_unop_unpack_sampler_2x32
:
2221 case ir_unop_pack_sampler_2x32
:
2222 case ir_unop_unpack_image_2x32
:
2223 case ir_unop_pack_image_2x32
:
2224 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2227 case ir_binop_ldexp
:
2228 if (ir
->operands
[0]->type
->is_double()) {
2229 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2230 } else if (ir
->operands
[0]->type
->is_float()) {
2231 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2233 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2237 case ir_unop_pack_half_2x16
:
2238 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2240 case ir_unop_unpack_half_2x16
:
2241 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2244 case ir_unop_get_buffer_size
: {
2245 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2246 int buf_base
= ctx
->st
->has_hw_atomics
2247 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
2250 buf_base
+ (const_offset
? const_offset
->value
.u
[0] : 0),
2252 if (!const_offset
) {
2253 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2254 *buffer
.reladdr
= op
[0];
2255 emit_arl(ir
, sampler_reladdr
, op
[0]);
2257 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2263 case ir_unop_b2i64
: {
2264 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2265 st_dst_reg temp_dst
= st_dst_reg(temp
);
2266 unsigned orig_swz
= op
[0].swizzle
;
2268 * To convert unsigned to 64-bit:
2269 * zero Y channel, copy X channel.
2271 temp_dst
.writemask
= WRITEMASK_Y
;
2272 if (vector_elements
> 1)
2273 temp_dst
.writemask
|= WRITEMASK_W
;
2274 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2275 temp_dst
.writemask
= WRITEMASK_X
;
2276 if (vector_elements
> 1)
2277 temp_dst
.writemask
|= WRITEMASK_Z
;
2278 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2279 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2280 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2281 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2283 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2285 result_src
.type
= GLSL_TYPE_UINT64
;
2286 if (vector_elements
> 2) {
2287 /* Subtle: We rely on the fact that get_temp here returns the next
2288 * TGSI temporary register directly after the temp register used for
2289 * the first two components, so that the result gets picked up
2292 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2293 st_dst_reg temp_dst
= st_dst_reg(temp
);
2294 temp_dst
.writemask
= WRITEMASK_Y
;
2295 if (vector_elements
> 3)
2296 temp_dst
.writemask
|= WRITEMASK_W
;
2297 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2299 temp_dst
.writemask
= WRITEMASK_X
;
2300 if (vector_elements
> 3)
2301 temp_dst
.writemask
|= WRITEMASK_Z
;
2302 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2303 GET_SWZ(orig_swz
, 2),
2304 GET_SWZ(orig_swz
, 3),
2305 GET_SWZ(orig_swz
, 3));
2306 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2307 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2309 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2310 st_src_reg_for_int(1));
2317 case ir_unop_i642u
: {
2318 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2319 st_dst_reg temp_dst
= st_dst_reg(temp
);
2320 unsigned orig_swz
= op
[0].swizzle
;
2321 unsigned orig_idx
= op
[0].index
;
2323 temp_dst
.writemask
= WRITEMASK_X
;
2325 for (el
= 0; el
< vector_elements
; el
++) {
2326 unsigned swz
= GET_SWZ(orig_swz
, el
);
2328 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2329 SWIZZLE_Z
, SWIZZLE_Z
);
2331 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2332 SWIZZLE_X
, SWIZZLE_X
);
2334 op
[0].index
= orig_idx
+ 1;
2335 op
[0].type
= GLSL_TYPE_UINT
;
2336 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2337 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2340 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2341 result_src
.type
= GLSL_TYPE_UINT
;
2343 result_src
.type
= GLSL_TYPE_INT
;
2347 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2348 st_src_reg_for_int64(0));
2351 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2354 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2357 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2360 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2363 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2366 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2369 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2372 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2375 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2378 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2380 /* these might be needed */
2381 case ir_unop_pack_snorm_2x16
:
2382 case ir_unop_pack_unorm_2x16
:
2383 case ir_unop_pack_snorm_4x8
:
2384 case ir_unop_pack_unorm_4x8
:
2386 case ir_unop_unpack_snorm_2x16
:
2387 case ir_unop_unpack_unorm_2x16
:
2388 case ir_unop_unpack_snorm_4x8
:
2389 case ir_unop_unpack_unorm_4x8
:
2391 case ir_quadop_vector
:
2392 case ir_binop_vector_extract
:
2393 case ir_triop_vector_insert
:
2394 case ir_binop_carry
:
2395 case ir_binop_borrow
:
2396 case ir_unop_ssbo_unsized_array_length
:
2397 /* This operation is not supported, or should have already been handled.
2399 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2403 this->result
= result_src
;
2408 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2414 /* Note that this is only swizzles in expressions, not those on the left
2415 * hand side of an assignment, which do write masking. See ir_assignment
2419 ir
->val
->accept(this);
2421 assert(src
.file
!= PROGRAM_UNDEFINED
);
2422 assert(ir
->type
->vector_elements
> 0);
2424 for (i
= 0; i
< 4; i
++) {
2425 if (i
< ir
->type
->vector_elements
) {
2428 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2431 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2434 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2437 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2441 /* If the type is smaller than a vec4, replicate the last
2444 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2448 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2453 /* Test if the variable is an array. Note that geometry and
2454 * tessellation shader inputs are outputs are always arrays (except
2455 * for patch inputs), so only the array element type is considered.
2458 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2460 const glsl_type
*type
= var
->type
;
2462 *remove_array
= false;
2464 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2465 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2468 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2469 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2470 stage
== MESA_SHADER_TESS_CTRL
) &&
2472 if (!var
->type
->is_array())
2473 return false; /* a system value probably */
2475 type
= var
->type
->fields
.array
;
2476 *remove_array
= true;
2479 return type
->is_array() || type
->is_matrix();
2483 st_translate_interp_loc(ir_variable
*var
)
2485 if (var
->data
.centroid
)
2486 return TGSI_INTERPOLATE_LOC_CENTROID
;
2487 else if (var
->data
.sample
)
2488 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2490 return TGSI_INTERPOLATE_LOC_CENTER
;
2494 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2496 variable_storage
*entry
;
2497 ir_variable
*var
= ir
->var
;
2500 if (handle_bound_deref(ir
->as_dereference()))
2503 entry
= find_variable_storage(ir
->var
);
2506 switch (var
->data
.mode
) {
2507 case ir_var_uniform
:
2508 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2509 var
->data
.param_index
);
2510 _mesa_hash_table_insert(this->variables
, var
, entry
);
2512 case ir_var_shader_in
: {
2513 /* The linker assigns locations for varyings and attributes,
2514 * including deprecated builtins (like gl_Color), user-assign
2515 * generic attributes (glBindVertexLocation), and
2516 * user-defined varyings.
2518 assert(var
->data
.location
!= -1);
2520 const glsl_type
*type_without_array
= var
->type
->without_array();
2521 struct inout_decl
*decl
= &inputs
[num_inputs
];
2522 unsigned component
= var
->data
.location_frac
;
2523 unsigned num_components
;
2526 if (type_without_array
->is_64bit())
2527 component
= component
/ 2;
2528 if (type_without_array
->vector_elements
)
2529 num_components
= type_without_array
->vector_elements
;
2533 decl
->mesa_index
= var
->data
.location
;
2534 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2535 decl
->interp_loc
= st_translate_interp_loc(var
);
2536 decl
->base_type
= type_without_array
->base_type
;
2537 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2539 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2540 decl
->array_id
= num_input_arrays
+ 1;
2547 decl
->size
= type_size(var
->type
->fields
.array
);
2549 decl
->size
= type_size(var
->type
);
2551 entry
= new(mem_ctx
) variable_storage(var
,
2555 entry
->component
= component
;
2557 _mesa_hash_table_insert(this->variables
, var
, entry
);
2561 case ir_var_shader_out
: {
2562 assert(var
->data
.location
!= -1);
2564 const glsl_type
*type_without_array
= var
->type
->without_array();
2565 struct inout_decl
*decl
= &outputs
[num_outputs
];
2566 unsigned component
= var
->data
.location_frac
;
2567 unsigned num_components
;
2570 decl
->invariant
= var
->data
.invariant
;
2572 if (type_without_array
->is_64bit())
2573 component
= component
/ 2;
2574 if (type_without_array
->vector_elements
)
2575 num_components
= type_without_array
->vector_elements
;
2579 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2580 decl
->base_type
= type_without_array
->base_type
;
2581 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2582 if (var
->data
.stream
& (1u << 31)) {
2583 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2585 assert(var
->data
.stream
< 4);
2586 decl
->gs_out_streams
= 0;
2587 for (unsigned i
= 0; i
< num_components
; ++i
)
2588 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2591 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2592 decl
->array_id
= num_output_arrays
+ 1;
2593 num_output_arrays
++;
2599 decl
->size
= type_size(var
->type
->fields
.array
);
2601 decl
->size
= type_size(var
->type
);
2603 if (var
->data
.fb_fetch_output
) {
2604 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2605 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2606 var
->type
, component
, decl
->array_id
);
2607 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2608 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2611 entry
= new(mem_ctx
) variable_storage(var
,
2616 entry
->component
= component
;
2618 _mesa_hash_table_insert(this->variables
, var
, entry
);
2622 case ir_var_system_value
:
2623 entry
= new(mem_ctx
) variable_storage(var
,
2624 PROGRAM_SYSTEM_VALUE
,
2625 var
->data
.location
);
2628 case ir_var_temporary
:
2629 st_src_reg src
= get_temp(var
->type
);
2631 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2633 _mesa_hash_table_insert(this->variables
, var
, entry
);
2639 printf("Failed to make storage for %s\n", var
->name
);
2644 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2645 entry
->component
, entry
->array_id
);
2646 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2647 var
->data
.mode
== ir_var_shader_in
&&
2648 var
->type
->without_array()->is_double())
2649 this->result
.is_double_vertex_input
= true;
2650 if (!native_integers
)
2651 this->result
.type
= GLSL_TYPE_FLOAT
;
2655 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2656 GLbitfield64
* usage_mask
,
2657 GLbitfield64 double_usage_mask
,
2658 GLbitfield
* patch_usage_mask
)
2663 /* Fix array declarations by removing unused array elements at both ends
2664 * of the arrays. For example, mat4[3] where only mat[1] is used.
2666 for (i
= 0; i
< count
; i
++) {
2667 struct inout_decl
*decl
= &decls
[i
];
2668 if (!decl
->array_id
)
2671 /* Shrink the beginning. */
2672 for (j
= 0; j
< (int)decl
->size
; j
++) {
2673 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2674 if (*patch_usage_mask
&
2675 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2679 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2681 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2690 /* Shrink the end. */
2691 for (j
= decl
->size
-1; j
>= 0; j
--) {
2692 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2693 if (*patch_usage_mask
&
2694 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2698 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2700 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2707 /* When not all entries of an array are accessed, we mark them as used
2708 * here anyway, to ensure that the input/output mapping logic doesn't get
2711 * TODO This happens when an array isn't used via indirect access, which
2712 * some game ports do (at least eON-based). There is an optimization
2713 * opportunity here by replacing the array declaration with non-array
2714 * declarations of those slots that are actually used.
2716 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2717 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2718 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2720 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2726 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2731 ir_variable
*var
= ir
->variable_referenced();
2733 if (handle_bound_deref(ir
->as_dereference()))
2736 /* We only need the logic provided by st_glsl_storage_type_size()
2737 * for arrays of structs. Indirect sampler and image indexing is handled
2740 int element_size
= ir
->type
->without_array()->is_record() ?
2741 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2742 type_size(ir
->type
);
2744 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2746 ir
->array
->accept(this);
2749 if (!src
.has_index2
) {
2750 switch (this->prog
->Target
) {
2751 case GL_TESS_CONTROL_PROGRAM_NV
:
2752 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2753 !ir
->variable_referenced()->data
.patch
;
2755 case GL_TESS_EVALUATION_PROGRAM_NV
:
2756 is_2D
= src
.file
== PROGRAM_INPUT
&&
2757 !ir
->variable_referenced()->data
.patch
;
2759 case GL_GEOMETRY_PROGRAM_NV
:
2760 is_2D
= src
.file
== PROGRAM_INPUT
;
2770 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2771 src
.file
== PROGRAM_INPUT
)
2772 element_size
= attrib_type_size(ir
->type
, true);
2774 src
.index2D
= index
->value
.i
[0];
2775 src
.has_index2
= true;
2777 src
.index
+= index
->value
.i
[0] * element_size
;
2779 /* Variable index array dereference. It eats the "vec4" of the
2780 * base of the array and an index that offsets the TGSI register
2783 ir
->array_index
->accept(this);
2785 st_src_reg index_reg
;
2787 if (element_size
== 1) {
2788 index_reg
= this->result
;
2790 index_reg
= get_temp(native_integers
?
2791 glsl_type::int_type
: glsl_type::float_type
);
2793 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2794 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2797 /* If there was already a relative address register involved, add the
2798 * new and the old together to get the new offset.
2800 if (!is_2D
&& src
.reladdr
!= NULL
) {
2801 st_src_reg accum_reg
= get_temp(native_integers
?
2802 glsl_type::int_type
: glsl_type::float_type
);
2804 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2805 index_reg
, *src
.reladdr
);
2807 index_reg
= accum_reg
;
2811 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2812 *src
.reladdr2
= index_reg
;
2814 src
.has_index2
= true;
2816 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2817 *src
.reladdr
= index_reg
;
2821 /* Change the register type to the element type of the array. */
2822 src
.type
= ir
->type
->base_type
;
2828 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2831 const glsl_type
*struct_type
= ir
->record
->type
;
2832 ir_variable
*var
= ir
->record
->variable_referenced();
2835 if (handle_bound_deref(ir
->as_dereference()))
2838 ir
->record
->accept(this);
2840 assert(ir
->field_idx
>= 0);
2842 for (i
= 0; i
< struct_type
->length
; i
++) {
2843 if (i
== (unsigned) ir
->field_idx
)
2845 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2846 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2849 /* If the type is smaller than a vec4, replicate the last channel out. */
2850 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2851 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2853 this->result
.swizzle
= SWIZZLE_NOOP
;
2855 this->result
.index
+= offset
;
2856 this->result
.type
= ir
->type
->base_type
;
2860 * We want to be careful in assignment setup to hit the actual storage
2861 * instead of potentially using a temporary like we might with the
2862 * ir_dereference handler.
2865 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2867 /* The LHS must be a dereference. If the LHS is a variable indexed array
2868 * access of a vector, it must be separated into a series conditional moves
2869 * before reaching this point (see ir_vec_index_to_cond_assign).
2871 assert(ir
->as_dereference());
2872 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2874 assert(!deref_array
->array
->type
->is_vector());
2877 /* Use the rvalue deref handler for the most part. We write swizzles using
2878 * the writemask, but we do extract the base component for enhanced layouts
2879 * from the source swizzle.
2882 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2883 return st_dst_reg(v
->result
);
2887 * Process the condition of a conditional assignment
2889 * Examines the condition of a conditional assignment to generate the optimal
2890 * first operand of a \c CMP instruction. If the condition is a relational
2891 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2892 * used as the source for the \c CMP instruction. Otherwise the comparison
2893 * is processed to a boolean result, and the boolean result is used as the
2894 * operand to the CMP instruction.
2897 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2899 ir_rvalue
*src_ir
= ir
;
2901 bool switch_order
= false;
2903 ir_expression
*const expr
= ir
->as_expression();
2905 if (native_integers
) {
2906 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2907 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2908 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2909 type
== GLSL_TYPE_BOOL
) {
2910 if (expr
->operation
== ir_binop_equal
) {
2911 if (expr
->operands
[0]->is_zero()) {
2912 src_ir
= expr
->operands
[1];
2913 switch_order
= true;
2915 else if (expr
->operands
[1]->is_zero()) {
2916 src_ir
= expr
->operands
[0];
2917 switch_order
= true;
2920 else if (expr
->operation
== ir_binop_nequal
) {
2921 if (expr
->operands
[0]->is_zero()) {
2922 src_ir
= expr
->operands
[1];
2924 else if (expr
->operands
[1]->is_zero()) {
2925 src_ir
= expr
->operands
[0];
2931 src_ir
->accept(this);
2932 return switch_order
;
2935 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2936 bool zero_on_left
= false;
2938 if (expr
->operands
[0]->is_zero()) {
2939 src_ir
= expr
->operands
[1];
2940 zero_on_left
= true;
2941 } else if (expr
->operands
[1]->is_zero()) {
2942 src_ir
= expr
->operands
[0];
2943 zero_on_left
= false;
2947 * (a < 0) T F F ( a < 0) T F F
2948 * (0 < a) F F T (-a < 0) F F T
2949 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2950 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2952 * Note that exchanging the order of 0 and 'a' in the comparison simply
2953 * means that the value of 'a' should be negated.
2956 switch (expr
->operation
) {
2958 switch_order
= false;
2959 negate
= zero_on_left
;
2962 case ir_binop_gequal
:
2963 switch_order
= true;
2964 negate
= zero_on_left
;
2968 /* This isn't the right kind of comparison afterall, so make sure
2969 * the whole condition is visited.
2977 src_ir
->accept(this);
2979 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2980 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2981 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2982 * computing the condition.
2985 this->result
.negate
= ~this->result
.negate
;
2987 return switch_order
;
2991 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2992 st_dst_reg
*l
, st_src_reg
*r
,
2993 st_src_reg
*cond
, bool cond_swap
)
2995 if (type
->is_record()) {
2996 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2997 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3003 if (type
->is_array()) {
3004 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3005 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3010 if (type
->is_matrix()) {
3011 const struct glsl_type
*vec_type
;
3013 vec_type
= glsl_type::get_instance(type
->is_double()
3014 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3015 type
->vector_elements
, 1);
3017 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3018 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3023 assert(type
->is_scalar() || type
->is_vector());
3025 l
->type
= type
->base_type
;
3026 r
->type
= type
->base_type
;
3028 st_src_reg l_src
= st_src_reg(*l
);
3030 if (l_src
.file
== PROGRAM_OUTPUT
&&
3031 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
3032 (l_src
.index
== FRAG_RESULT_DEPTH
||
3033 l_src
.index
== FRAG_RESULT_STENCIL
)) {
3034 /* This is a special case because the source swizzles will be shifted
3035 * later to account for the difference between GLSL (where they're
3036 * plain floats) and TGSI (where they're Z and Y components). */
3037 l_src
.swizzle
= SWIZZLE_XXXX
;
3040 if (native_integers
) {
3041 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3042 cond_swap
? l_src
: *r
,
3043 cond_swap
? *r
: l_src
);
3045 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3046 cond_swap
? l_src
: *r
,
3047 cond_swap
? *r
: l_src
);
3050 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3054 if (type
->is_dual_slot()) {
3056 if (r
->is_double_vertex_input
== false)
3062 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3068 /* all generated instructions need to be flaged as precise */
3069 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3070 ir
->rhs
->accept(this);
3073 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3077 int first_enabled_chan
= 0;
3079 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3081 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3082 variable
->data
.mode
== ir_var_shader_out
&&
3083 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3084 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3085 assert(ir
->lhs
->type
->is_scalar());
3086 assert(ir
->write_mask
== WRITEMASK_X
);
3088 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3089 l
.writemask
= WRITEMASK_Z
;
3091 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3092 l
.writemask
= WRITEMASK_Y
;
3094 } else if (ir
->write_mask
== 0) {
3095 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3097 unsigned num_elements
=
3098 ir
->lhs
->type
->without_array()->vector_elements
;
3101 l
.writemask
= u_bit_consecutive(0, num_elements
);
3103 /* The type is a struct or an array of (array of) structs. */
3104 l
.writemask
= WRITEMASK_XYZW
;
3107 l
.writemask
= ir
->write_mask
;
3110 for (int i
= 0; i
< 4; i
++) {
3111 if (l
.writemask
& (1 << i
)) {
3112 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3117 l
.writemask
= l
.writemask
<< dst_component
;
3119 /* Swizzle a small RHS vector into the channels being written.
3121 * glsl ir treats write_mask as dictating how many channels are
3122 * present on the RHS while TGSI treats write_mask as just
3123 * showing which channels of the vec4 RHS get written.
3125 for (int i
= 0; i
< 4; i
++) {
3126 if (l
.writemask
& (1 << i
))
3127 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3129 swizzles
[i
] = first_enabled_chan
;
3131 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3132 swizzles
[2], swizzles
[3]);
3135 assert(l
.file
!= PROGRAM_UNDEFINED
);
3136 assert(r
.file
!= PROGRAM_UNDEFINED
);
3138 if (ir
->condition
) {
3139 const bool switch_order
= this->process_move_condition(ir
->condition
);
3140 st_src_reg condition
= this->result
;
3142 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3143 } else if (ir
->rhs
->as_expression() &&
3144 this->instructions
.get_tail() &&
3145 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3146 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3147 type_size(ir
->lhs
->type
) == 1 &&
3148 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3149 /* To avoid emitting an extra MOV when assigning an expression to a
3150 * variable, emit the last instruction of the expression again, but
3151 * replace the destination register with the target of the assignment.
3152 * Dead code elimination will remove the original instruction.
3154 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3155 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3156 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3157 new_inst
->saturate
= inst
->saturate
;
3158 new_inst
->resource
= inst
->resource
;
3159 inst
->dead_mask
= inst
->dst
[0].writemask
;
3161 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3168 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3171 GLdouble stack_vals
[4] = { 0 };
3172 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3173 GLenum gl_type
= GL_NONE
;
3174 unsigned int i
, elements
;
3175 static int in_array
= 0;
3176 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3178 /* Unfortunately, 4 floats is all we can get into
3179 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3180 * aggregate constant and move each constant value into it. If we
3181 * get lucky, copy propagation will eliminate the extra moves.
3183 if (ir
->type
->is_record()) {
3184 st_src_reg temp_base
= get_temp(ir
->type
);
3185 st_dst_reg temp
= st_dst_reg(temp_base
);
3187 for (i
= 0; i
< ir
->type
->length
; i
++) {
3188 ir_constant
*const field_value
= ir
->get_record_field(i
);
3189 int size
= type_size(field_value
->type
);
3193 field_value
->accept(this);
3196 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3197 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3203 this->result
= temp_base
;
3207 if (ir
->type
->is_array()) {
3208 st_src_reg temp_base
= get_temp(ir
->type
);
3209 st_dst_reg temp
= st_dst_reg(temp_base
);
3210 int size
= type_size(ir
->type
->fields
.array
);
3215 for (i
= 0; i
< ir
->type
->length
; i
++) {
3216 ir
->const_elements
[i
]->accept(this);
3218 for (int j
= 0; j
< size
; j
++) {
3219 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3225 this->result
= temp_base
;
3230 if (ir
->type
->is_matrix()) {
3231 st_src_reg mat
= get_temp(ir
->type
);
3232 st_dst_reg mat_column
= st_dst_reg(mat
);
3234 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3235 switch (ir
->type
->base_type
) {
3236 case GLSL_TYPE_FLOAT
:
3237 values
= (gl_constant_value
*)
3238 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3240 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3241 src
.index
= add_constant(file
,
3243 ir
->type
->vector_elements
,
3246 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3248 case GLSL_TYPE_DOUBLE
:
3249 values
= (gl_constant_value
*)
3250 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3251 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3252 src
.index
= add_constant(file
,
3254 ir
->type
->vector_elements
,
3257 if (ir
->type
->vector_elements
>= 2) {
3258 mat_column
.writemask
= WRITEMASK_XY
;
3259 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3260 SWIZZLE_X
, SWIZZLE_Y
);
3261 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3263 mat_column
.writemask
= WRITEMASK_X
;
3264 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3265 SWIZZLE_X
, SWIZZLE_X
);
3266 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3269 if (ir
->type
->vector_elements
> 2) {
3270 if (ir
->type
->vector_elements
== 4) {
3271 mat_column
.writemask
= WRITEMASK_ZW
;
3272 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3273 SWIZZLE_X
, SWIZZLE_Y
);
3274 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3276 mat_column
.writemask
= WRITEMASK_Z
;
3277 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3278 SWIZZLE_Y
, SWIZZLE_Y
);
3279 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3280 mat_column
.writemask
= WRITEMASK_XYZW
;
3281 src
.swizzle
= SWIZZLE_XYZW
;
3287 unreachable("Illegal matrix constant type.\n");
3296 elements
= ir
->type
->vector_elements
;
3297 switch (ir
->type
->base_type
) {
3298 case GLSL_TYPE_FLOAT
:
3300 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3301 values
[i
].f
= ir
->value
.f
[i
];
3304 case GLSL_TYPE_DOUBLE
:
3305 gl_type
= GL_DOUBLE
;
3306 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3307 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3310 case GLSL_TYPE_INT64
:
3311 gl_type
= GL_INT64_ARB
;
3312 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3313 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3316 case GLSL_TYPE_UINT64
:
3317 gl_type
= GL_UNSIGNED_INT64_ARB
;
3318 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3319 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3322 case GLSL_TYPE_UINT
:
3323 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3324 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3325 if (native_integers
)
3326 values
[i
].u
= ir
->value
.u
[i
];
3328 values
[i
].f
= ir
->value
.u
[i
];
3332 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3333 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3334 if (native_integers
)
3335 values
[i
].i
= ir
->value
.i
[i
];
3337 values
[i
].f
= ir
->value
.i
[i
];
3340 case GLSL_TYPE_BOOL
:
3341 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3342 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3343 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3346 case GLSL_TYPE_SAMPLER
:
3347 case GLSL_TYPE_IMAGE
:
3348 gl_type
= GL_UNSIGNED_INT
;
3350 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3351 values
[1].u
= ir
->value
.u64
[0] >> 32;
3354 assert(!"Non-float/uint/int/bool/sampler/image constant");
3357 this->result
= st_src_reg(file
, -1, ir
->type
);
3358 this->result
.index
= add_constant(file
,
3362 &this->result
.swizzle
);
3366 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3368 exec_node
*param
= ir
->actual_parameters
.get_head();
3369 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3370 ir_variable
*location
= deref
->variable_referenced();
3371 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3372 /* Calculate the surface offset */
3374 unsigned array_size
= 0, base
= 0;
3376 st_src_reg resource
;
3378 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3380 if (has_hw_atomics
) {
3381 variable_storage
*entry
= find_variable_storage(location
);
3382 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3383 location
->data
.binding
);
3386 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3388 _mesa_hash_table_insert(this->variables
, location
, entry
);
3390 atomic_info
[num_atomics
].location
= location
->data
.location
;
3391 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3392 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3393 if (atomic_info
[num_atomics
].size
== 0)
3394 atomic_info
[num_atomics
].size
= 1;
3395 atomic_info
[num_atomics
].array_id
= 0;
3399 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3400 if (atomic_info
[entry
->index
].array_id
== 0) {
3401 num_atomic_arrays
++;
3402 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3404 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3407 buffer
.index
= index
;
3408 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3409 buffer
.has_index2
= true;
3411 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3412 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3413 *buffer
.reladdr
= offset
;
3414 emit_arl(ir
, sampler_reladdr
, offset
);
3416 offset
= st_src_reg_for_int(0);
3420 st_src_reg
buffer(PROGRAM_BUFFER
, location
->data
.binding
,
3421 GLSL_TYPE_ATOMIC_UINT
);
3423 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3424 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3425 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3426 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3427 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3429 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3434 ir
->return_deref
->accept(this);
3435 st_dst_reg
dst(this->result
);
3436 dst
.writemask
= WRITEMASK_X
;
3438 glsl_to_tgsi_instruction
*inst
;
3440 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3441 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3442 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3443 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3444 st_src_reg_for_int(1));
3445 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3446 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3447 st_src_reg_for_int(-1));
3448 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3450 param
= param
->get_next();
3451 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3454 st_src_reg data
= this->result
, data2
= undef_src
;
3455 enum tgsi_opcode opcode
;
3456 switch (ir
->callee
->intrinsic_id
) {
3457 case ir_intrinsic_atomic_counter_add
:
3458 opcode
= TGSI_OPCODE_ATOMUADD
;
3460 case ir_intrinsic_atomic_counter_min
:
3461 opcode
= TGSI_OPCODE_ATOMIMIN
;
3463 case ir_intrinsic_atomic_counter_max
:
3464 opcode
= TGSI_OPCODE_ATOMIMAX
;
3466 case ir_intrinsic_atomic_counter_and
:
3467 opcode
= TGSI_OPCODE_ATOMAND
;
3469 case ir_intrinsic_atomic_counter_or
:
3470 opcode
= TGSI_OPCODE_ATOMOR
;
3472 case ir_intrinsic_atomic_counter_xor
:
3473 opcode
= TGSI_OPCODE_ATOMXOR
;
3475 case ir_intrinsic_atomic_counter_exchange
:
3476 opcode
= TGSI_OPCODE_ATOMXCHG
;
3478 case ir_intrinsic_atomic_counter_comp_swap
: {
3479 opcode
= TGSI_OPCODE_ATOMCAS
;
3480 param
= param
->get_next();
3481 val
= ((ir_instruction
*)param
)->as_rvalue();
3483 data2
= this->result
;
3487 assert(!"Unexpected intrinsic");
3491 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3494 inst
->resource
= resource
;
3498 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3500 exec_node
*param
= ir
->actual_parameters
.get_head();
3502 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3504 param
= param
->get_next();
3505 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3507 ir_constant
*const_block
= block
->as_constant();
3508 int buf_base
= st_context(ctx
)->has_hw_atomics
3509 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
3512 buf_base
+ (const_block
? const_block
->value
.u
[0] : 0),
3516 block
->accept(this);
3517 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3518 *buffer
.reladdr
= this->result
;
3519 emit_arl(ir
, sampler_reladdr
, this->result
);
3522 /* Calculate the surface offset */
3523 offset
->accept(this);
3524 st_src_reg off
= this->result
;
3526 st_dst_reg dst
= undef_dst
;
3527 if (ir
->return_deref
) {
3528 ir
->return_deref
->accept(this);
3529 dst
= st_dst_reg(this->result
);
3530 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3533 glsl_to_tgsi_instruction
*inst
;
3535 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3536 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3537 if (dst
.type
== GLSL_TYPE_BOOL
)
3538 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3539 st_src_reg_for_int(0));
3540 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3541 param
= param
->get_next();
3542 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3545 param
= param
->get_next();
3546 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3548 dst
.writemask
= write_mask
->value
.u
[0];
3550 dst
.type
= this->result
.type
;
3551 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3553 param
= param
->get_next();
3554 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3557 st_src_reg data
= this->result
, data2
= undef_src
;
3558 enum tgsi_opcode opcode
;
3559 switch (ir
->callee
->intrinsic_id
) {
3560 case ir_intrinsic_ssbo_atomic_add
:
3561 opcode
= TGSI_OPCODE_ATOMUADD
;
3563 case ir_intrinsic_ssbo_atomic_min
:
3564 opcode
= TGSI_OPCODE_ATOMIMIN
;
3566 case ir_intrinsic_ssbo_atomic_max
:
3567 opcode
= TGSI_OPCODE_ATOMIMAX
;
3569 case ir_intrinsic_ssbo_atomic_and
:
3570 opcode
= TGSI_OPCODE_ATOMAND
;
3572 case ir_intrinsic_ssbo_atomic_or
:
3573 opcode
= TGSI_OPCODE_ATOMOR
;
3575 case ir_intrinsic_ssbo_atomic_xor
:
3576 opcode
= TGSI_OPCODE_ATOMXOR
;
3578 case ir_intrinsic_ssbo_atomic_exchange
:
3579 opcode
= TGSI_OPCODE_ATOMXCHG
;
3581 case ir_intrinsic_ssbo_atomic_comp_swap
:
3582 opcode
= TGSI_OPCODE_ATOMCAS
;
3583 param
= param
->get_next();
3584 val
= ((ir_instruction
*)param
)->as_rvalue();
3586 data2
= this->result
;
3589 assert(!"Unexpected intrinsic");
3593 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3596 param
= param
->get_next();
3597 ir_constant
*access
= NULL
;
3598 if (!param
->is_tail_sentinel()) {
3599 access
= ((ir_instruction
*)param
)->as_constant();
3603 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3607 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3609 switch (ir
->callee
->intrinsic_id
) {
3610 case ir_intrinsic_memory_barrier
:
3611 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3612 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3613 TGSI_MEMBAR_ATOMIC_BUFFER
|
3614 TGSI_MEMBAR_SHADER_IMAGE
|
3615 TGSI_MEMBAR_SHARED
));
3617 case ir_intrinsic_memory_barrier_atomic_counter
:
3618 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3619 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3621 case ir_intrinsic_memory_barrier_buffer
:
3622 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3623 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3625 case ir_intrinsic_memory_barrier_image
:
3626 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3627 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3629 case ir_intrinsic_memory_barrier_shared
:
3630 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3631 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3633 case ir_intrinsic_group_memory_barrier
:
3634 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3635 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3636 TGSI_MEMBAR_ATOMIC_BUFFER
|
3637 TGSI_MEMBAR_SHADER_IMAGE
|
3638 TGSI_MEMBAR_SHARED
|
3639 TGSI_MEMBAR_THREAD_GROUP
));
3642 assert(!"Unexpected memory barrier intrinsic");
3647 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3649 exec_node
*param
= ir
->actual_parameters
.get_head();
3651 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3653 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3655 /* Calculate the surface offset */
3656 offset
->accept(this);
3657 st_src_reg off
= this->result
;
3659 st_dst_reg dst
= undef_dst
;
3660 if (ir
->return_deref
) {
3661 ir
->return_deref
->accept(this);
3662 dst
= st_dst_reg(this->result
);
3663 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3666 glsl_to_tgsi_instruction
*inst
;
3668 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3669 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3670 inst
->resource
= buffer
;
3671 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3672 param
= param
->get_next();
3673 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3676 param
= param
->get_next();
3677 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3679 dst
.writemask
= write_mask
->value
.u
[0];
3681 dst
.type
= this->result
.type
;
3682 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3683 inst
->resource
= buffer
;
3685 param
= param
->get_next();
3686 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3689 st_src_reg data
= this->result
, data2
= undef_src
;
3690 enum tgsi_opcode opcode
;
3691 switch (ir
->callee
->intrinsic_id
) {
3692 case ir_intrinsic_shared_atomic_add
:
3693 opcode
= TGSI_OPCODE_ATOMUADD
;
3695 case ir_intrinsic_shared_atomic_min
:
3696 opcode
= TGSI_OPCODE_ATOMIMIN
;
3698 case ir_intrinsic_shared_atomic_max
:
3699 opcode
= TGSI_OPCODE_ATOMIMAX
;
3701 case ir_intrinsic_shared_atomic_and
:
3702 opcode
= TGSI_OPCODE_ATOMAND
;
3704 case ir_intrinsic_shared_atomic_or
:
3705 opcode
= TGSI_OPCODE_ATOMOR
;
3707 case ir_intrinsic_shared_atomic_xor
:
3708 opcode
= TGSI_OPCODE_ATOMXOR
;
3710 case ir_intrinsic_shared_atomic_exchange
:
3711 opcode
= TGSI_OPCODE_ATOMXCHG
;
3713 case ir_intrinsic_shared_atomic_comp_swap
:
3714 opcode
= TGSI_OPCODE_ATOMCAS
;
3715 param
= param
->get_next();
3716 val
= ((ir_instruction
*)param
)->as_rvalue();
3718 data2
= this->result
;
3721 assert(!"Unexpected intrinsic");
3725 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3726 inst
->resource
= buffer
;
3731 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3732 bool *memory_coherent
, bool *memory_volatile
,
3733 bool *memory_restrict
, bool *memory_read_only
,
3734 unsigned *image_format
)
3737 switch (ir
->ir_type
) {
3738 case ir_type_dereference_record
: {
3739 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3740 const glsl_type
*struct_type
= deref_record
->record
->type
;
3741 int fild_idx
= deref_record
->field_idx
;
3743 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3745 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3747 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3749 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3751 struct_type
->fields
.structure
[fild_idx
].memory_read_only
;
3753 struct_type
->fields
.structure
[fild_idx
].image_format
;
3757 case ir_type_dereference_array
: {
3758 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3759 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3760 memory_coherent
, memory_volatile
, memory_restrict
,
3761 memory_read_only
, image_format
);
3765 case ir_type_dereference_variable
: {
3766 ir_variable
*var
= ir
->variable_referenced();
3768 *type
= var
->type
->without_array();
3769 *memory_coherent
= var
->data
.memory_coherent
;
3770 *memory_volatile
= var
->data
.memory_volatile
;
3771 *memory_restrict
= var
->data
.memory_restrict
;
3772 *memory_read_only
= var
->data
.memory_read_only
;
3773 *image_format
= var
->data
.image_format
;
3783 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3785 exec_node
*param
= ir
->actual_parameters
.get_head();
3787 ir_dereference
*img
= (ir_dereference
*)param
;
3788 const ir_variable
*imgvar
= img
->variable_referenced();
3789 unsigned sampler_array_size
= 1, sampler_base
= 0;
3790 bool memory_coherent
= false, memory_volatile
= false,
3791 memory_restrict
= false, memory_read_only
= false;
3792 unsigned image_format
= 0;
3793 const glsl_type
*type
= NULL
;
3795 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3796 &memory_restrict
, &memory_read_only
, &image_format
);
3799 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3801 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3802 &index
, &reladdr
, !imgvar
->contains_bindless());
3804 image
.index
= index
;
3805 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3806 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3807 *image
.reladdr
= reladdr
;
3808 emit_arl(ir
, sampler_reladdr
, reladdr
);
3811 st_dst_reg dst
= undef_dst
;
3812 if (ir
->return_deref
) {
3813 ir
->return_deref
->accept(this);
3814 dst
= st_dst_reg(this->result
);
3815 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3818 glsl_to_tgsi_instruction
*inst
;
3820 st_src_reg bindless
;
3821 if (imgvar
->contains_bindless()) {
3823 bindless
= this->result
;
3826 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3827 dst
.writemask
= WRITEMASK_XYZ
;
3828 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3829 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3830 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3831 st_dst_reg dstres
= st_dst_reg(res
);
3832 dstres
.writemask
= WRITEMASK_W
;
3833 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3834 res
.swizzle
= SWIZZLE_WWWW
;
3835 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3837 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3839 st_dst_reg coord_dst
;
3840 coord
= get_temp(glsl_type::ivec4_type
);
3841 coord_dst
= st_dst_reg(coord
);
3842 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3843 param
= param
->get_next();
3844 ((ir_dereference
*)param
)->accept(this);
3845 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3846 coord
.swizzle
= SWIZZLE_XXXX
;
3847 switch (type
->coordinate_components()) {
3848 case 4: assert(!"unexpected coord count");
3850 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3852 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3855 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3856 param
= param
->get_next();
3857 ((ir_dereference
*)param
)->accept(this);
3858 st_src_reg sample
= this->result
;
3859 sample
.swizzle
= SWIZZLE_XXXX
;
3860 coord_dst
.writemask
= WRITEMASK_W
;
3861 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3862 coord
.swizzle
|= SWIZZLE_W
<< 9;
3865 param
= param
->get_next();
3866 if (!param
->is_tail_sentinel()) {
3867 ((ir_dereference
*)param
)->accept(this);
3868 arg1
= this->result
;
3869 param
= param
->get_next();
3872 if (!param
->is_tail_sentinel()) {
3873 ((ir_dereference
*)param
)->accept(this);
3874 arg2
= this->result
;
3875 param
= param
->get_next();
3878 assert(param
->is_tail_sentinel());
3880 enum tgsi_opcode opcode
;
3881 switch (ir
->callee
->intrinsic_id
) {
3882 case ir_intrinsic_image_load
:
3883 opcode
= TGSI_OPCODE_LOAD
;
3885 case ir_intrinsic_image_store
:
3886 opcode
= TGSI_OPCODE_STORE
;
3888 case ir_intrinsic_image_atomic_add
:
3889 opcode
= TGSI_OPCODE_ATOMUADD
;
3891 case ir_intrinsic_image_atomic_min
:
3892 opcode
= TGSI_OPCODE_ATOMIMIN
;
3894 case ir_intrinsic_image_atomic_max
:
3895 opcode
= TGSI_OPCODE_ATOMIMAX
;
3897 case ir_intrinsic_image_atomic_and
:
3898 opcode
= TGSI_OPCODE_ATOMAND
;
3900 case ir_intrinsic_image_atomic_or
:
3901 opcode
= TGSI_OPCODE_ATOMOR
;
3903 case ir_intrinsic_image_atomic_xor
:
3904 opcode
= TGSI_OPCODE_ATOMXOR
;
3906 case ir_intrinsic_image_atomic_exchange
:
3907 opcode
= TGSI_OPCODE_ATOMXCHG
;
3909 case ir_intrinsic_image_atomic_comp_swap
:
3910 opcode
= TGSI_OPCODE_ATOMCAS
;
3913 assert(!"Unexpected intrinsic");
3917 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3918 if (opcode
== TGSI_OPCODE_STORE
)
3919 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3922 if (imgvar
->contains_bindless()) {
3923 inst
->resource
= bindless
;
3924 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3925 SWIZZLE_X
, SWIZZLE_Y
);
3927 inst
->resource
= image
;
3928 inst
->sampler_array_size
= sampler_array_size
;
3929 inst
->sampler_base
= sampler_base
;
3932 inst
->tex_target
= type
->sampler_index();
3933 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3934 _mesa_get_shader_image_format(image_format
));
3935 inst
->read_only
= memory_read_only
;
3937 if (memory_coherent
)
3938 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3939 if (memory_restrict
)
3940 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3941 if (memory_volatile
)
3942 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3946 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
3948 ir
->return_deref
->accept(this);
3949 st_dst_reg dst
= st_dst_reg(this->result
);
3951 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3953 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3954 unsigned num_src
= 0;
3955 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3956 assert(num_src
< ARRAY_SIZE(src
));
3958 this->result
.file
= PROGRAM_UNDEFINED
;
3959 param
->accept(this);
3960 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3962 src
[num_src
] = this->result
;
3966 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3970 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3972 ir_function_signature
*sig
= ir
->callee
;
3974 /* Filter out intrinsics */
3975 switch (sig
->intrinsic_id
) {
3976 case ir_intrinsic_atomic_counter_read
:
3977 case ir_intrinsic_atomic_counter_increment
:
3978 case ir_intrinsic_atomic_counter_predecrement
:
3979 case ir_intrinsic_atomic_counter_add
:
3980 case ir_intrinsic_atomic_counter_min
:
3981 case ir_intrinsic_atomic_counter_max
:
3982 case ir_intrinsic_atomic_counter_and
:
3983 case ir_intrinsic_atomic_counter_or
:
3984 case ir_intrinsic_atomic_counter_xor
:
3985 case ir_intrinsic_atomic_counter_exchange
:
3986 case ir_intrinsic_atomic_counter_comp_swap
:
3987 visit_atomic_counter_intrinsic(ir
);
3990 case ir_intrinsic_ssbo_load
:
3991 case ir_intrinsic_ssbo_store
:
3992 case ir_intrinsic_ssbo_atomic_add
:
3993 case ir_intrinsic_ssbo_atomic_min
:
3994 case ir_intrinsic_ssbo_atomic_max
:
3995 case ir_intrinsic_ssbo_atomic_and
:
3996 case ir_intrinsic_ssbo_atomic_or
:
3997 case ir_intrinsic_ssbo_atomic_xor
:
3998 case ir_intrinsic_ssbo_atomic_exchange
:
3999 case ir_intrinsic_ssbo_atomic_comp_swap
:
4000 visit_ssbo_intrinsic(ir
);
4003 case ir_intrinsic_memory_barrier
:
4004 case ir_intrinsic_memory_barrier_atomic_counter
:
4005 case ir_intrinsic_memory_barrier_buffer
:
4006 case ir_intrinsic_memory_barrier_image
:
4007 case ir_intrinsic_memory_barrier_shared
:
4008 case ir_intrinsic_group_memory_barrier
:
4009 visit_membar_intrinsic(ir
);
4012 case ir_intrinsic_shared_load
:
4013 case ir_intrinsic_shared_store
:
4014 case ir_intrinsic_shared_atomic_add
:
4015 case ir_intrinsic_shared_atomic_min
:
4016 case ir_intrinsic_shared_atomic_max
:
4017 case ir_intrinsic_shared_atomic_and
:
4018 case ir_intrinsic_shared_atomic_or
:
4019 case ir_intrinsic_shared_atomic_xor
:
4020 case ir_intrinsic_shared_atomic_exchange
:
4021 case ir_intrinsic_shared_atomic_comp_swap
:
4022 visit_shared_intrinsic(ir
);
4025 case ir_intrinsic_image_load
:
4026 case ir_intrinsic_image_store
:
4027 case ir_intrinsic_image_atomic_add
:
4028 case ir_intrinsic_image_atomic_min
:
4029 case ir_intrinsic_image_atomic_max
:
4030 case ir_intrinsic_image_atomic_and
:
4031 case ir_intrinsic_image_atomic_or
:
4032 case ir_intrinsic_image_atomic_xor
:
4033 case ir_intrinsic_image_atomic_exchange
:
4034 case ir_intrinsic_image_atomic_comp_swap
:
4035 case ir_intrinsic_image_size
:
4036 case ir_intrinsic_image_samples
:
4037 visit_image_intrinsic(ir
);
4040 case ir_intrinsic_shader_clock
:
4041 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4044 case ir_intrinsic_vote_all
:
4045 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4047 case ir_intrinsic_vote_any
:
4048 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4050 case ir_intrinsic_vote_eq
:
4051 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4053 case ir_intrinsic_ballot
:
4054 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4056 case ir_intrinsic_read_first_invocation
:
4057 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4059 case ir_intrinsic_read_invocation
:
4060 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4063 case ir_intrinsic_invalid
:
4064 case ir_intrinsic_generic_load
:
4065 case ir_intrinsic_generic_store
:
4066 case ir_intrinsic_generic_atomic_add
:
4067 case ir_intrinsic_generic_atomic_and
:
4068 case ir_intrinsic_generic_atomic_or
:
4069 case ir_intrinsic_generic_atomic_xor
:
4070 case ir_intrinsic_generic_atomic_min
:
4071 case ir_intrinsic_generic_atomic_max
:
4072 case ir_intrinsic_generic_atomic_exchange
:
4073 case ir_intrinsic_generic_atomic_comp_swap
:
4074 case ir_intrinsic_begin_invocation_interlock
:
4075 case ir_intrinsic_end_invocation_interlock
:
4076 unreachable("Invalid intrinsic");
4081 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4082 unsigned *array_elements
,
4084 st_src_reg
*indirect
,
4087 switch (tail
->ir_type
) {
4088 case ir_type_dereference_record
: {
4089 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4090 const glsl_type
*struct_type
= deref_record
->record
->type
;
4091 int field_index
= deref_record
->field_idx
;
4093 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4095 assert(field_index
>= 0);
4096 *location
+= struct_type
->record_location_offset(field_index
);
4100 case ir_type_dereference_array
: {
4101 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4103 void *mem_ctx
= ralloc_parent(deref_arr
);
4104 ir_constant
*array_index
=
4105 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4108 st_src_reg temp_reg
;
4109 st_dst_reg temp_dst
;
4111 temp_reg
= get_temp(glsl_type::uint_type
);
4112 temp_dst
= st_dst_reg(temp_reg
);
4113 temp_dst
.writemask
= 1;
4115 deref_arr
->array_index
->accept(this);
4116 if (*array_elements
!= 1)
4117 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4119 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4121 if (indirect
->file
== PROGRAM_UNDEFINED
)
4122 *indirect
= temp_reg
;
4124 temp_dst
= st_dst_reg(*indirect
);
4125 temp_dst
.writemask
= 1;
4126 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4129 *index
+= array_index
->value
.u
[0] * *array_elements
;
4131 *array_elements
*= deref_arr
->array
->type
->length
;
4133 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4142 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4143 unsigned *array_size
,
4146 st_src_reg
*reladdr
,
4149 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4150 unsigned location
= 0;
4151 ir_variable
*var
= ir
->variable_referenced();
4159 location
= var
->data
.location
;
4160 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4163 * If we end up with no indirect then adjust the base to the index,
4164 * and set the array size to 1.
4166 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4172 assert(location
!= 0xffffffff);
4173 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4174 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4179 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4181 if (offset
.reladdr
|| offset
.reladdr2
||
4182 offset
.has_index2
||
4183 offset
.file
== PROGRAM_UNIFORM
||
4184 offset
.file
== PROGRAM_CONSTANT
||
4185 offset
.file
== PROGRAM_STATE_VAR
) {
4186 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4187 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4188 tmp_dst
.writemask
= WRITEMASK_XY
;
4189 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4197 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4199 ir_variable
*var
= ir
->variable_referenced();
4201 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4202 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4205 /* Convert from bound sampler/image to bindless handle. */
4206 bool is_image
= ir
->type
->is_image();
4207 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4209 unsigned array_size
= 1, base
= 0;
4211 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4213 resource
.index
= index
;
4214 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4215 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4216 *resource
.reladdr
= reladdr
;
4217 emit_arl(ir
, sampler_reladdr
, reladdr
);
4220 this->result
= get_temp(glsl_type::uvec2_type
);
4221 st_dst_reg
dst(this->result
);
4222 dst
.writemask
= WRITEMASK_XY
;
4224 glsl_to_tgsi_instruction
*inst
= emit_asm(
4225 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4227 inst
->tex_target
= ir
->type
->sampler_index();
4228 inst
->resource
= resource
;
4229 inst
->sampler_array_size
= array_size
;
4230 inst
->sampler_base
= base
;
4236 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4238 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4239 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4240 st_src_reg levels_src
, reladdr
;
4241 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4242 glsl_to_tgsi_instruction
*inst
= NULL
;
4243 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4244 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4245 unsigned sampler_array_size
= 1, sampler_base
= 0;
4246 bool is_cube_array
= false, is_cube_shadow
= false;
4247 ir_variable
*var
= ir
->sampler
->variable_referenced();
4250 /* if we are a cube array sampler or a cube shadow */
4251 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4252 is_cube_array
= sampler_type
->sampler_array
;
4253 is_cube_shadow
= sampler_type
->sampler_shadow
;
4256 if (ir
->coordinate
) {
4257 ir
->coordinate
->accept(this);
4259 /* Put our coords in a temp. We'll need to modify them for shadow,
4260 * projection, or LOD, so the only case we'd use it as-is is if
4261 * we're doing plain old texturing. The optimization passes on
4262 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4264 coord
= get_temp(glsl_type::vec4_type
);
4265 coord_dst
= st_dst_reg(coord
);
4266 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4267 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4270 if (ir
->projector
) {
4271 ir
->projector
->accept(this);
4272 projector
= this->result
;
4275 /* Storage for our result. Ideally for an assignment we'd be using
4276 * the actual storage for the result here, instead.
4278 result_src
= get_temp(ir
->type
);
4279 result_dst
= st_dst_reg(result_src
);
4280 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4284 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4286 ir
->offset
->accept(this);
4287 offset
[0] = this->result
;
4291 if (is_cube_array
|| is_cube_shadow
) {
4292 opcode
= TGSI_OPCODE_TXB2
;
4295 opcode
= TGSI_OPCODE_TXB
;
4297 ir
->lod_info
.bias
->accept(this);
4298 lod_info
= this->result
;
4300 ir
->offset
->accept(this);
4301 offset
[0] = this->result
;
4305 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4306 opcode
= TGSI_OPCODE_TEX_LZ
;
4308 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4309 ir
->lod_info
.lod
->accept(this);
4310 lod_info
= this->result
;
4313 ir
->offset
->accept(this);
4314 offset
[0] = this->result
;
4318 opcode
= TGSI_OPCODE_TXD
;
4319 ir
->lod_info
.grad
.dPdx
->accept(this);
4321 ir
->lod_info
.grad
.dPdy
->accept(this);
4324 ir
->offset
->accept(this);
4325 offset
[0] = this->result
;
4329 opcode
= TGSI_OPCODE_TXQ
;
4330 ir
->lod_info
.lod
->accept(this);
4331 lod_info
= this->result
;
4333 case ir_query_levels
:
4334 opcode
= TGSI_OPCODE_TXQ
;
4335 lod_info
= undef_src
;
4336 levels_src
= get_temp(ir
->type
);
4339 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4340 opcode
= TGSI_OPCODE_TXF_LZ
;
4342 opcode
= TGSI_OPCODE_TXF
;
4343 ir
->lod_info
.lod
->accept(this);
4344 lod_info
= this->result
;
4347 ir
->offset
->accept(this);
4348 offset
[0] = this->result
;
4352 opcode
= TGSI_OPCODE_TXF
;
4353 ir
->lod_info
.sample_index
->accept(this);
4354 sample_index
= this->result
;
4357 opcode
= TGSI_OPCODE_TG4
;
4358 ir
->lod_info
.component
->accept(this);
4359 component
= this->result
;
4361 ir
->offset
->accept(this);
4362 if (ir
->offset
->type
->is_array()) {
4363 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4364 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4365 offset
[i
] = this->result
;
4366 offset
[i
].index
+= i
* type_size(elt_type
);
4367 offset
[i
].type
= elt_type
->base_type
;
4368 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4369 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4372 offset
[0] = canonicalize_gather_offset(this->result
);
4377 opcode
= TGSI_OPCODE_LODQ
;
4379 case ir_texture_samples
:
4380 opcode
= TGSI_OPCODE_TXQS
;
4382 case ir_samples_identical
:
4383 unreachable("Unexpected ir_samples_identical opcode");
4386 if (ir
->projector
) {
4387 if (opcode
== TGSI_OPCODE_TEX
) {
4388 /* Slot the projector in as the last component of the coord. */
4389 coord_dst
.writemask
= WRITEMASK_W
;
4390 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4391 coord_dst
.writemask
= WRITEMASK_XYZW
;
4392 opcode
= TGSI_OPCODE_TXP
;
4394 st_src_reg coord_w
= coord
;
4395 coord_w
.swizzle
= SWIZZLE_WWWW
;
4397 /* For the other TEX opcodes there's no projective version
4398 * since the last slot is taken up by LOD info. Do the
4399 * projective divide now.
4401 coord_dst
.writemask
= WRITEMASK_W
;
4402 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4404 /* In the case where we have to project the coordinates "by hand,"
4405 * the shadow comparator value must also be projected.
4407 st_src_reg tmp_src
= coord
;
4408 if (ir
->shadow_comparator
) {
4409 /* Slot the shadow value in as the second to last component of the
4412 ir
->shadow_comparator
->accept(this);
4414 tmp_src
= get_temp(glsl_type::vec4_type
);
4415 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4417 /* Projective division not allowed for array samplers. */
4418 assert(!sampler_type
->sampler_array
);
4420 tmp_dst
.writemask
= WRITEMASK_Z
;
4421 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4423 tmp_dst
.writemask
= WRITEMASK_XY
;
4424 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4427 coord_dst
.writemask
= WRITEMASK_XYZ
;
4428 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4430 coord_dst
.writemask
= WRITEMASK_XYZW
;
4431 coord
.swizzle
= SWIZZLE_XYZW
;
4435 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4436 * shadow comparator was put in the correct place (and projected) by the
4437 * code, above, that handles by-hand projection.
4439 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4440 /* Slot the shadow value in as the second to last component of the
4443 ir
->shadow_comparator
->accept(this);
4445 if (is_cube_array
) {
4446 cube_sc
= get_temp(glsl_type::float_type
);
4447 cube_sc_dst
= st_dst_reg(cube_sc
);
4448 cube_sc_dst
.writemask
= WRITEMASK_X
;
4449 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4450 cube_sc_dst
.writemask
= WRITEMASK_X
;
4453 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4454 sampler_type
->sampler_array
) ||
4455 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4456 coord_dst
.writemask
= WRITEMASK_W
;
4458 coord_dst
.writemask
= WRITEMASK_Z
;
4460 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4461 coord_dst
.writemask
= WRITEMASK_XYZW
;
4465 if (ir
->op
== ir_txf_ms
) {
4466 coord_dst
.writemask
= WRITEMASK_W
;
4467 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4468 coord_dst
.writemask
= WRITEMASK_XYZW
;
4469 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4470 opcode
== TGSI_OPCODE_TXF
) {
4471 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4472 coord_dst
.writemask
= WRITEMASK_W
;
4473 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4474 coord_dst
.writemask
= WRITEMASK_XYZW
;
4477 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4480 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4481 &index
, &reladdr
, !var
->contains_bindless());
4483 sampler
.index
= index
;
4484 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4485 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4486 *sampler
.reladdr
= reladdr
;
4487 emit_arl(ir
, sampler_reladdr
, reladdr
);
4490 st_src_reg bindless
;
4491 if (var
->contains_bindless()) {
4492 ir
->sampler
->accept(this);
4493 bindless
= this->result
;
4496 if (opcode
== TGSI_OPCODE_TXD
)
4497 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4498 else if (opcode
== TGSI_OPCODE_TXQ
) {
4499 if (ir
->op
== ir_query_levels
) {
4500 /* the level is stored in W */
4501 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4502 result_dst
.writemask
= WRITEMASK_X
;
4503 levels_src
.swizzle
= SWIZZLE_WWWW
;
4504 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4506 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4507 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4508 inst
= emit_asm(ir
, opcode
, result_dst
);
4509 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4510 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4511 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4512 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4513 } else if (opcode
== TGSI_OPCODE_TG4
) {
4514 if (is_cube_array
&& ir
->shadow_comparator
) {
4515 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4517 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4520 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4522 if (ir
->shadow_comparator
)
4523 inst
->tex_shadow
= GL_TRUE
;
4525 if (var
->contains_bindless()) {
4526 inst
->resource
= bindless
;
4527 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4528 SWIZZLE_X
, SWIZZLE_Y
);
4530 inst
->resource
= sampler
;
4531 inst
->sampler_array_size
= sampler_array_size
;
4532 inst
->sampler_base
= sampler_base
;
4536 if (!inst
->tex_offsets
)
4537 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4538 MAX_GLSL_TEXTURE_OFFSET
);
4540 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4541 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4542 inst
->tex_offsets
[i
] = offset
[i
];
4543 inst
->tex_offset_num_offset
= i
;
4546 inst
->tex_target
= sampler_type
->sampler_index();
4547 inst
->tex_type
= ir
->type
->base_type
;
4549 this->result
= result_src
;
4553 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4555 assert(!ir
->get_value());
4557 emit_asm(ir
, TGSI_OPCODE_RET
);
4561 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4563 if (ir
->condition
) {
4564 ir
->condition
->accept(this);
4565 st_src_reg condition
= this->result
;
4567 /* Convert the bool condition to a float so we can negate. */
4568 if (native_integers
) {
4569 st_src_reg temp
= get_temp(ir
->condition
->type
);
4570 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4571 condition
, st_src_reg_for_float(1.0));
4575 condition
.negate
= ~condition
.negate
;
4576 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4578 /* unconditional kil */
4579 emit_asm(ir
, TGSI_OPCODE_KILL
);
4584 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4586 enum tgsi_opcode if_opcode
;
4587 glsl_to_tgsi_instruction
*if_inst
;
4589 ir
->condition
->accept(this);
4590 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4592 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4594 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4596 this->instructions
.push_tail(if_inst
);
4598 visit_exec_list(&ir
->then_instructions
, this);
4600 if (!ir
->else_instructions
.is_empty()) {
4601 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4602 visit_exec_list(&ir
->else_instructions
, this);
4605 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4610 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4612 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4614 ir
->stream
->accept(this);
4615 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4619 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4621 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4623 ir
->stream
->accept(this);
4624 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4628 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4630 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4631 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4633 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4636 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4638 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4640 result
.file
= PROGRAM_UNDEFINED
;
4647 num_input_arrays
= 0;
4648 num_output_arrays
= 0;
4650 num_atomic_arrays
= 0;
4652 num_address_regs
= 0;
4655 indirect_addr_consts
= false;
4656 wpos_transform_const
= -1;
4657 native_integers
= false;
4658 mem_ctx
= ralloc_context(NULL
);
4663 shader_program
= NULL
;
4668 use_shared_memory
= false;
4669 has_tex_txf_lz
= false;
4673 static void var_destroy(struct hash_entry
*entry
)
4675 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4680 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4682 _mesa_hash_table_destroy(variables
, var_destroy
);
4684 ralloc_free(mem_ctx
);
4687 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4694 * Count resources used by the given gpu program (number of texture
4698 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4700 v
->samplers_used
= 0;
4702 prog
->info
.textures_used_by_txf
= 0;
4704 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4705 if (inst
->info
->is_tex
) {
4706 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4707 unsigned idx
= inst
->sampler_base
+ i
;
4708 v
->samplers_used
|= 1u << idx
;
4710 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4711 v
->sampler_types
[idx
] = inst
->tex_type
;
4712 v
->sampler_targets
[idx
] =
4713 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4715 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4716 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4721 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4722 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4724 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4725 is_resource_instruction(inst
->op
) ||
4726 inst
->op
== TGSI_OPCODE_STORE
)) {
4727 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4728 v
->use_shared_memory
= true;
4729 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4730 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4731 unsigned idx
= inst
->sampler_base
+ i
;
4732 v
->images_used
|= 1 << idx
;
4733 v
->image_targets
[idx
] =
4734 st_translate_texture_target(inst
->tex_target
, false);
4735 v
->image_formats
[idx
] = inst
->image_format
;
4736 v
->image_wr
[idx
] = !inst
->read_only
;
4741 prog
->SamplersUsed
= v
->samplers_used
;
4743 if (v
->shader_program
!= NULL
)
4744 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4748 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4749 * are read from the given src in this instruction
4752 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4754 int read_mask
= 0, comp
;
4756 /* Now, given the src swizzle and the written channels, find which
4757 * components are actually read
4759 for (comp
= 0; comp
< 4; ++comp
) {
4760 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4762 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4763 read_mask
|= 1 << coord
;
4770 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4771 * instruction is the first instruction to write to register T0. There are
4772 * several lowering passes done in GLSL IR (e.g. branches and
4773 * relative addressing) that create a large number of conditional assignments
4774 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4776 * Here is why this conversion is safe:
4777 * CMP T0, T1 T2 T0 can be expanded to:
4783 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4784 * as the original program. If (T1 < 0.0) evaluates to false, executing
4785 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4786 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4787 * because any instruction that was going to read from T0 after this was going
4788 * to read a garbage value anyway.
4791 glsl_to_tgsi_visitor::simplify_cmp(void)
4793 int tempWritesSize
= 0;
4794 unsigned *tempWrites
= NULL
;
4795 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4797 memset(outputWrites
, 0, sizeof(outputWrites
));
4799 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4800 unsigned prevWriteMask
= 0;
4802 /* Give up if we encounter relative addressing or flow control. */
4803 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4804 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4805 inst
->info
->is_branch
||
4806 inst
->op
== TGSI_OPCODE_CONT
||
4807 inst
->op
== TGSI_OPCODE_END
||
4808 inst
->op
== TGSI_OPCODE_RET
) {
4812 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4813 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4814 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4815 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4816 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4817 if (inst
->dst
[0].index
>= tempWritesSize
) {
4818 const int inc
= 4096;
4820 tempWrites
= (unsigned*)
4822 (tempWritesSize
+ inc
) * sizeof(unsigned));
4826 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4827 tempWritesSize
+= inc
;
4830 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4831 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4835 /* For a CMP to be considered a conditional write, the destination
4836 * register and source register two must be the same. */
4837 if (inst
->op
== TGSI_OPCODE_CMP
4838 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4839 && inst
->src
[2].file
== inst
->dst
[0].file
4840 && inst
->src
[2].index
== inst
->dst
[0].index
4841 && inst
->dst
[0].writemask
==
4842 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4844 inst
->op
= TGSI_OPCODE_MOV
;
4845 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4846 inst
->src
[0] = inst
->src
[1];
4854 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4856 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4857 int old_idx
= src
->index
;
4858 if (renames
[old_idx
].valid
)
4859 src
->index
= renames
[old_idx
].new_reg
;
4863 /* Replaces all references to a temporary register index with another index. */
4865 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4867 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4869 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4870 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4871 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4872 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4875 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4876 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4877 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4878 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4881 rename_temp_handle_src(renames
, &inst
->resource
);
4882 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4883 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4885 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4886 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4887 int old_idx
= inst
->dst
[j
].index
;
4888 if (renames
[old_idx
].valid
)
4889 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4891 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4892 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4898 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4900 int depth
= 0; /* loop depth */
4901 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4904 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4905 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4906 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4907 if (first_writes
[inst
->dst
[j
].index
] == -1)
4908 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4912 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4915 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4925 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4927 int depth
= 0; /* loop depth */
4928 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4931 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4932 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4933 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4934 if (first_reads
[inst
->src
[j
].index
] == -1)
4935 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4938 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4939 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4940 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4941 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4944 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4947 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4957 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4959 int depth
= 0; /* loop depth */
4960 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4963 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4964 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4965 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4966 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4968 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4969 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4970 if (first_writes
[inst
->dst
[j
].index
] == -1)
4971 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4972 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4975 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4976 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4977 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4979 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4982 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4985 for (k
= 0; k
< this->next_temp
; k
++) {
4986 if (last_reads
[k
] == -2) {
4998 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
5000 int depth
= 0; /* loop depth */
5004 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5005 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5006 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
5007 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5010 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
5012 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
5014 for (k
= 0; k
< this->next_temp
; k
++) {
5015 if (last_writes
[k
] == -2) {
5026 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5027 * channels for copy propagation and updates following instructions to
5028 * use the original versions.
5030 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5031 * will occur. As an example, a TXP production before this pass:
5033 * 0: MOV TEMP[1], INPUT[4].xyyy;
5034 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5035 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5039 * 0: MOV TEMP[1], INPUT[4].xyyy;
5040 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5041 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5043 * which allows for dead code elimination on TEMP[1]'s writes.
5046 glsl_to_tgsi_visitor::copy_propagate(void)
5048 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5049 glsl_to_tgsi_instruction
*,
5050 this->next_temp
* 4);
5051 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5054 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5055 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5056 || inst
->dst
[0].index
< this->next_temp
);
5058 /* First, do any copy propagation possible into the src regs. */
5059 for (int r
= 0; r
< 3; r
++) {
5060 glsl_to_tgsi_instruction
*first
= NULL
;
5062 int acp_base
= inst
->src
[r
].index
* 4;
5064 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5065 inst
->src
[r
].reladdr
||
5066 inst
->src
[r
].reladdr2
)
5069 /* See if we can find entries in the ACP consisting of MOVs
5070 * from the same src register for all the swizzled channels
5071 * of this src register reference.
5073 for (int i
= 0; i
< 4; i
++) {
5074 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5075 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5082 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5087 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5088 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5089 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5090 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5098 /* We've now validated that we can copy-propagate to
5099 * replace this src register reference. Do it.
5101 inst
->src
[r
].file
= first
->src
[0].file
;
5102 inst
->src
[r
].index
= first
->src
[0].index
;
5103 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5104 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5105 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5106 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5109 for (int i
= 0; i
< 4; i
++) {
5110 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5111 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5112 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5114 inst
->src
[r
].swizzle
= swizzle
;
5119 case TGSI_OPCODE_BGNLOOP
:
5120 case TGSI_OPCODE_ENDLOOP
:
5121 /* End of a basic block, clear the ACP entirely. */
5122 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5125 case TGSI_OPCODE_IF
:
5126 case TGSI_OPCODE_UIF
:
5130 case TGSI_OPCODE_ENDIF
:
5131 case TGSI_OPCODE_ELSE
:
5132 /* Clear all channels written inside the block from the ACP, but
5133 * leaving those that were not touched.
5135 for (int r
= 0; r
< this->next_temp
; r
++) {
5136 for (int c
= 0; c
< 4; c
++) {
5137 if (!acp
[4 * r
+ c
])
5140 if (acp_level
[4 * r
+ c
] >= level
)
5141 acp
[4 * r
+ c
] = NULL
;
5144 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5149 /* Continuing the block, clear any written channels from
5152 for (int d
= 0; d
< 2; d
++) {
5153 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5154 /* Any temporary might be written, so no copy propagation
5155 * across this instruction.
5157 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5158 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5159 inst
->dst
[d
].reladdr
) {
5160 /* Any output might be written, so no copy propagation
5161 * from outputs across this instruction.
5163 for (int r
= 0; r
< this->next_temp
; r
++) {
5164 for (int c
= 0; c
< 4; c
++) {
5165 if (!acp
[4 * r
+ c
])
5168 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5169 acp
[4 * r
+ c
] = NULL
;
5172 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5173 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5174 /* Clear where it's used as dst. */
5175 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5176 for (int c
= 0; c
< 4; c
++) {
5177 if (inst
->dst
[d
].writemask
& (1 << c
))
5178 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5182 /* Clear where it's used as src. */
5183 for (int r
= 0; r
< this->next_temp
; r
++) {
5184 for (int c
= 0; c
< 4; c
++) {
5185 if (!acp
[4 * r
+ c
])
5188 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5190 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5191 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5192 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5193 acp
[4 * r
+ c
] = NULL
;
5202 /* If this is a copy, add it to the ACP. */
5203 if (inst
->op
== TGSI_OPCODE_MOV
&&
5204 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5205 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5206 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5207 !inst
->dst
[0].reladdr
&&
5208 !inst
->dst
[0].reladdr2
&&
5210 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5211 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5212 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5213 !inst
->src
[0].reladdr
&&
5214 !inst
->src
[0].reladdr2
&&
5215 !inst
->src
[0].negate
&&
5216 !inst
->src
[0].abs
) {
5217 for (int i
= 0; i
< 4; i
++) {
5218 if (inst
->dst
[0].writemask
& (1 << i
)) {
5219 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5220 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5226 ralloc_free(acp_level
);
5231 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5233 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5234 /* Clear where it's used as src. */
5235 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5236 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5241 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5244 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5245 * will occur. As an example, a TXP production after copy propagation but
5248 * 0: MOV TEMP[1], INPUT[4].xyyy;
5249 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5250 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5252 * and after this pass:
5254 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5257 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5259 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5260 glsl_to_tgsi_instruction
*,
5261 this->next_temp
* 4);
5262 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5266 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5267 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5268 || inst
->dst
[0].index
< this->next_temp
);
5271 case TGSI_OPCODE_BGNLOOP
:
5272 case TGSI_OPCODE_ENDLOOP
:
5273 case TGSI_OPCODE_CONT
:
5274 case TGSI_OPCODE_BRK
:
5275 /* End of a basic block, clear the write array entirely.
5277 * This keeps us from killing dead code when the writes are
5278 * on either side of a loop, even when the register isn't touched
5279 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5280 * dead code of this type, so it shouldn't make a difference as long as
5281 * the dead code elimination pass in the GLSL compiler does its job.
5283 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5286 case TGSI_OPCODE_ENDIF
:
5287 case TGSI_OPCODE_ELSE
:
5288 /* Promote the recorded level of all channels written inside the
5289 * preceding if or else block to the level above the if/else block.
5291 for (int r
= 0; r
< this->next_temp
; r
++) {
5292 for (int c
= 0; c
< 4; c
++) {
5293 if (!writes
[4 * r
+ c
])
5296 if (write_level
[4 * r
+ c
] == level
)
5297 write_level
[4 * r
+ c
] = level
-1;
5300 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5304 case TGSI_OPCODE_IF
:
5305 case TGSI_OPCODE_UIF
:
5307 /* fallthrough to default case to mark the condition as read */
5309 /* Continuing the block, clear any channels from the write array that
5310 * are read by this instruction.
5312 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5313 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5314 /* Any temporary might be read, so no dead code elimination
5315 * across this instruction.
5317 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5318 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5319 /* Clear where it's used as src. */
5320 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5321 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5322 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5323 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5325 for (int c
= 0; c
< 4; c
++) {
5326 if (src_chans
& (1 << c
))
5327 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5330 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5331 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5333 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5334 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5335 /* Any temporary might be read, so no dead code elimination
5336 * across this instruction.
5338 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5339 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5340 /* Clear where it's used as src. */
5341 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5342 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5343 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5344 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5346 for (int c
= 0; c
< 4; c
++) {
5347 if (src_chans
& (1 << c
))
5348 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5351 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5352 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5355 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5358 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5359 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5360 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5361 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5363 for (int c
= 0; c
< 4; c
++) {
5364 if (src_chans
& (1 << c
))
5365 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5368 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5369 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5371 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5372 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5373 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5378 /* If this instruction writes to a temporary, add it to the write array.
5379 * If there is already an instruction in the write array for one or more
5380 * of the channels, flag that channel write as dead.
5382 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5383 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5384 !inst
->dst
[i
].reladdr
) {
5385 for (int c
= 0; c
< 4; c
++) {
5386 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5387 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5388 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5391 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5393 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5394 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5401 /* Anything still in the write array at this point is dead code. */
5402 for (int r
= 0; r
< this->next_temp
; r
++) {
5403 for (int c
= 0; c
< 4; c
++) {
5404 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5406 inst
->dead_mask
|= (1 << c
);
5410 /* Now actually remove the instructions that are completely dead and update
5411 * the writemask of other instructions with dead channels.
5413 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5414 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5416 /* No amount of dead masks should remove memory stores */
5417 if (inst
->info
->is_store
)
5420 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5425 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5426 if (inst
->dead_mask
== WRITEMASK_XY
||
5427 inst
->dead_mask
== WRITEMASK_ZW
)
5428 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5430 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5434 ralloc_free(write_level
);
5435 ralloc_free(writes
);
5440 /* merge DFRACEXP instructions into one. */
5442 glsl_to_tgsi_visitor::merge_two_dsts(void)
5444 /* We never delete inst, but we may delete its successor. */
5445 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5446 glsl_to_tgsi_instruction
*inst2
;
5449 if (num_inst_dst_regs(inst
) != 2)
5452 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5453 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5456 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5457 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5459 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5464 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5465 while (!inst2
->is_tail_sentinel()) {
5466 if (inst
->op
== inst2
->op
&&
5467 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5468 inst
->src
[0].file
== inst2
->src
[0].file
&&
5469 inst
->src
[0].index
== inst2
->src
[0].index
&&
5470 inst
->src
[0].type
== inst2
->src
[0].type
&&
5471 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5473 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5476 if (inst2
->is_tail_sentinel()) {
5477 /* Undefined destinations are not allowed, substitute with an unused
5478 * temporary register.
5480 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5481 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5482 inst
->dst
[defined
^ 1].writemask
= 0;
5486 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5492 template <typename st_reg
>
5493 void test_indirect_access(const st_reg
& reg
, bool *has_indirect_access
)
5495 if (reg
.file
== PROGRAM_ARRAY
) {
5496 if (reg
.reladdr
|| reg
.reladdr2
|| reg
.has_index2
) {
5497 has_indirect_access
[reg
.array_id
] = true;
5499 test_indirect_access(*reg
.reladdr
, has_indirect_access
);
5501 test_indirect_access(*reg
.reladdr2
, has_indirect_access
);
5506 template <typename st_reg
>
5507 void remap_array(st_reg
& reg
, const int *array_remap_info
,
5508 const bool *has_indirect_access
)
5510 if (reg
.file
== PROGRAM_ARRAY
) {
5511 if (!has_indirect_access
[reg
.array_id
]) {
5512 reg
.file
= PROGRAM_TEMPORARY
;
5513 reg
.index
= reg
.index
+ array_remap_info
[reg
.array_id
];
5516 reg
.array_id
= array_remap_info
[reg
.array_id
];
5520 remap_array(*reg
.reladdr
, array_remap_info
, has_indirect_access
);
5523 remap_array(*reg
.reladdr2
, array_remap_info
, has_indirect_access
);
5527 /* One-dimensional arrays whose elements are only accessed directly are
5528 * replaced by an according set of temporary registers that then can become
5529 * subject to further optimization steps like copy propagation and
5533 glsl_to_tgsi_visitor::split_arrays(void)
5538 bool *has_indirect_access
= rzalloc_array(mem_ctx
, bool, next_array
+ 1);
5540 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5541 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5542 test_indirect_access(inst
->src
[j
], has_indirect_access
);
5544 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5545 test_indirect_access(inst
->tex_offsets
[j
], has_indirect_access
);
5547 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++)
5548 test_indirect_access(inst
->dst
[j
], has_indirect_access
);
5550 test_indirect_access(inst
->resource
, has_indirect_access
);
5553 unsigned array_offset
= 0;
5554 unsigned n_remaining_arrays
= 0;
5556 /* Double use: For arrays that get split this value will contain
5557 * the base index of the temporary registers this array is replaced
5558 * with. For arrays that remain it contains the new array ID.
5560 int *array_remap_info
= rzalloc_array(has_indirect_access
, int,
5563 for (unsigned i
= 1; i
<= next_array
; ++i
) {
5564 if (!has_indirect_access
[i
]) {
5565 array_remap_info
[i
] = this->next_temp
+ array_offset
;
5566 array_offset
+= array_sizes
[i
- 1];
5568 array_sizes
[n_remaining_arrays
] = array_sizes
[i
-1];
5569 array_remap_info
[i
] = ++n_remaining_arrays
;
5573 if (next_array
!= n_remaining_arrays
) {
5574 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5575 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5576 remap_array(inst
->src
[j
], array_remap_info
, has_indirect_access
);
5578 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5579 remap_array(inst
->tex_offsets
[j
], array_remap_info
, has_indirect_access
);
5581 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5582 remap_array(inst
->dst
[j
], array_remap_info
, has_indirect_access
);
5584 remap_array(inst
->resource
, array_remap_info
, has_indirect_access
);
5588 ralloc_free(has_indirect_access
);
5589 this->next_temp
+= array_offset
;
5590 next_array
= n_remaining_arrays
;
5593 /* Merges temporary registers together where possible to reduce the number of
5594 * registers needed to run a program.
5596 * Produces optimal code only after copy propagation and dead code elimination
5599 glsl_to_tgsi_visitor::merge_registers(void)
5601 class array_live_range
*arr_live_ranges
= NULL
;
5603 struct register_live_range
*reg_live_ranges
=
5604 rzalloc_array(mem_ctx
, struct register_live_range
, this->next_temp
);
5606 if (this->next_array
> 0) {
5607 arr_live_ranges
= new array_live_range
[this->next_array
];
5608 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5609 arr_live_ranges
[i
] = array_live_range(i
+1, this->array_sizes
[i
]);
5613 if (get_temp_registers_required_live_ranges(reg_live_ranges
, &this->instructions
,
5614 this->next_temp
, reg_live_ranges
,
5615 this->next_array
, arr_live_ranges
)) {
5616 struct rename_reg_pair
*renames
=
5617 rzalloc_array(reg_live_ranges
, struct rename_reg_pair
, this->next_temp
);
5618 get_temp_registers_remapping(reg_live_ranges
, this->next_temp
,
5619 reg_live_ranges
, renames
);
5620 rename_temp_registers(renames
);
5622 this->next_array
= merge_arrays(this->next_array
, this->array_sizes
,
5623 &this->instructions
, arr_live_ranges
);
5626 if (arr_live_ranges
)
5627 delete[] arr_live_ranges
;
5629 ralloc_free(reg_live_ranges
);
5632 /* Reassign indices to temporary registers by reusing unused indices created
5633 * by optimization passes. */
5635 glsl_to_tgsi_visitor::renumber_registers(void)
5639 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5640 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5642 for (i
= 0; i
< this->next_temp
; i
++) {
5643 first_writes
[i
] = -1;
5645 get_first_temp_write(first_writes
);
5647 for (i
= 0; i
< this->next_temp
; i
++) {
5648 if (first_writes
[i
] < 0) continue;
5649 if (i
!= new_index
) {
5650 renames
[i
].new_reg
= new_index
;
5651 renames
[i
].valid
= true;
5656 rename_temp_registers(renames
);
5657 this->next_temp
= new_index
;
5658 ralloc_free(renames
);
5659 ralloc_free(first_writes
);
5663 void glsl_to_tgsi_visitor::print_stats()
5665 int narray_registers
= 0;
5666 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5667 narray_registers
+= this->array_sizes
[i
];
5669 int ninstructions
= 0;
5670 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &instructions
) {
5674 simple_mtx_lock(&print_stats_mutex
);
5675 stats_log
<< next_array
<< ", "
5676 << next_temp
<< ", "
5677 << narray_registers
<< ", "
5678 << next_temp
+ narray_registers
<< ", "
5679 << ninstructions
<< "\n";
5680 simple_mtx_unlock(&print_stats_mutex
);
5683 /* ------------------------- TGSI conversion stuff -------------------------- */
5686 * Intermediate state used during shader translation.
5688 struct st_translate
{
5689 struct ureg_program
*ureg
;
5691 unsigned temps_size
;
5692 struct ureg_dst
*temps
;
5694 struct ureg_dst
*arrays
;
5695 unsigned num_temp_arrays
;
5696 struct ureg_src
*constants
;
5698 struct ureg_src
*immediates
;
5700 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5701 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5702 struct ureg_dst address
[3];
5703 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5704 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5705 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5706 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5707 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5708 struct ureg_src shared_memory
;
5709 unsigned *array_sizes
;
5710 struct inout_decl
*input_decls
;
5711 unsigned num_input_decls
;
5712 struct inout_decl
*output_decls
;
5713 unsigned num_output_decls
;
5715 const ubyte
*inputMapping
;
5716 const ubyte
*outputMapping
;
5718 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5722 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5724 _mesa_sysval_to_semantic(unsigned sysval
)
5728 case SYSTEM_VALUE_VERTEX_ID
:
5729 return TGSI_SEMANTIC_VERTEXID
;
5730 case SYSTEM_VALUE_INSTANCE_ID
:
5731 return TGSI_SEMANTIC_INSTANCEID
;
5732 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5733 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5734 case SYSTEM_VALUE_BASE_VERTEX
:
5735 return TGSI_SEMANTIC_BASEVERTEX
;
5736 case SYSTEM_VALUE_BASE_INSTANCE
:
5737 return TGSI_SEMANTIC_BASEINSTANCE
;
5738 case SYSTEM_VALUE_DRAW_ID
:
5739 return TGSI_SEMANTIC_DRAWID
;
5741 /* Geometry shader */
5742 case SYSTEM_VALUE_INVOCATION_ID
:
5743 return TGSI_SEMANTIC_INVOCATIONID
;
5745 /* Fragment shader */
5746 case SYSTEM_VALUE_FRAG_COORD
:
5747 return TGSI_SEMANTIC_POSITION
;
5748 case SYSTEM_VALUE_FRONT_FACE
:
5749 return TGSI_SEMANTIC_FACE
;
5750 case SYSTEM_VALUE_SAMPLE_ID
:
5751 return TGSI_SEMANTIC_SAMPLEID
;
5752 case SYSTEM_VALUE_SAMPLE_POS
:
5753 return TGSI_SEMANTIC_SAMPLEPOS
;
5754 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5755 return TGSI_SEMANTIC_SAMPLEMASK
;
5756 case SYSTEM_VALUE_HELPER_INVOCATION
:
5757 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5759 /* Tessellation shader */
5760 case SYSTEM_VALUE_TESS_COORD
:
5761 return TGSI_SEMANTIC_TESSCOORD
;
5762 case SYSTEM_VALUE_VERTICES_IN
:
5763 return TGSI_SEMANTIC_VERTICESIN
;
5764 case SYSTEM_VALUE_PRIMITIVE_ID
:
5765 return TGSI_SEMANTIC_PRIMID
;
5766 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5767 return TGSI_SEMANTIC_TESSOUTER
;
5768 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5769 return TGSI_SEMANTIC_TESSINNER
;
5771 /* Compute shader */
5772 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5773 return TGSI_SEMANTIC_THREAD_ID
;
5774 case SYSTEM_VALUE_WORK_GROUP_ID
:
5775 return TGSI_SEMANTIC_BLOCK_ID
;
5776 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5777 return TGSI_SEMANTIC_GRID_SIZE
;
5778 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5779 return TGSI_SEMANTIC_BLOCK_SIZE
;
5781 /* ARB_shader_ballot */
5782 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5783 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5784 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5785 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5786 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5787 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5788 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5789 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5790 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5791 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5792 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5793 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5794 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5795 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5798 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5799 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5800 case SYSTEM_VALUE_VERTEX_CNT
:
5801 case SYSTEM_VALUE_VARYING_COORD
:
5803 assert(!"Unexpected SYSTEM_VALUE_ enum");
5804 return TGSI_SEMANTIC_COUNT
;
5809 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5811 static struct ureg_src
5812 emit_immediate(struct st_translate
*t
,
5813 gl_constant_value values
[4],
5814 GLenum type
, int size
)
5816 struct ureg_program
*ureg
= t
->ureg
;
5820 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5822 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5824 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5825 case GL_UNSIGNED_INT64_ARB
:
5826 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5828 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5829 case GL_UNSIGNED_INT
:
5831 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5833 assert(!"should not get here - type must be float, int, uint, or bool");
5834 return ureg_src_undef();
5839 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5841 static struct ureg_dst
5842 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5848 case PROGRAM_UNDEFINED
:
5849 return ureg_dst_undef();
5851 case PROGRAM_TEMPORARY
:
5852 /* Allocate space for temporaries on demand. */
5853 if (index
>= t
->temps_size
) {
5854 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5856 t
->temps
= (struct ureg_dst
*)
5858 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5860 return ureg_dst_undef();
5862 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5863 t
->temps_size
+= inc
;
5866 if (ureg_dst_is_undef(t
->temps
[index
]))
5867 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5869 return t
->temps
[index
];
5872 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5873 array
= array_id
- 1;
5875 if (ureg_dst_is_undef(t
->arrays
[array
]))
5876 t
->arrays
[array
] = ureg_DECL_array_temporary(
5877 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5879 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5881 case PROGRAM_OUTPUT
:
5883 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5884 assert(index
< 2 * FRAG_RESULT_MAX
);
5885 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5886 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5887 assert(index
< VARYING_SLOT_TESS_MAX
);
5889 assert(index
< VARYING_SLOT_MAX
);
5891 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5892 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5893 return t
->outputs
[t
->outputMapping
[index
]];
5896 struct inout_decl
*decl
=
5897 find_inout_array(t
->output_decls
,
5898 t
->num_output_decls
, array_id
);
5899 unsigned mesa_index
= decl
->mesa_index
;
5900 int slot
= t
->outputMapping
[mesa_index
];
5902 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5904 struct ureg_dst dst
= t
->outputs
[slot
];
5905 dst
.ArrayID
= array_id
;
5906 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5909 case PROGRAM_ADDRESS
:
5910 return t
->address
[index
];
5913 assert(!"unknown dst register file");
5914 return ureg_dst_undef();
5918 static struct ureg_src
5919 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5921 static struct ureg_src
5922 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5923 unsigned addr_index
)
5925 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5926 return ureg_src(t
->address
[addr_index
]);
5928 return translate_src(t
, reladdr
);
5932 * Create a TGSI ureg_dst register from an st_dst_reg.
5934 static struct ureg_dst
5935 translate_dst(struct st_translate
*t
,
5936 const st_dst_reg
*dst_reg
,
5939 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5942 if (dst
.File
== TGSI_FILE_NULL
)
5945 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5948 dst
= ureg_saturate(dst
);
5950 if (dst_reg
->reladdr
!= NULL
) {
5951 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5952 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5955 if (dst_reg
->has_index2
) {
5956 if (dst_reg
->reladdr2
)
5957 dst
= ureg_dst_dimension_indirect(dst
,
5958 translate_addr(t
, dst_reg
->reladdr2
, 1),
5961 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5968 * Create a TGSI ureg_src register from an st_src_reg.
5970 static struct ureg_src
5971 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5973 struct ureg_src src
;
5974 int index
= src_reg
->index
;
5975 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5977 switch (src_reg
->file
) {
5978 case PROGRAM_UNDEFINED
:
5979 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5982 case PROGRAM_TEMPORARY
:
5984 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
5985 src_reg
->array_id
));
5988 case PROGRAM_OUTPUT
: {
5989 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
5991 assert(dst
.WriteMask
!= 0);
5992 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5993 src
= ureg_swizzle(ureg_src(dst
),
5997 MIN2(shift
+ 3, 3));
6001 case PROGRAM_UNIFORM
:
6002 assert(src_reg
->index
>= 0);
6003 src
= src_reg
->index
< t
->num_constants
?
6004 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6006 case PROGRAM_STATE_VAR
:
6007 case PROGRAM_CONSTANT
: /* ie, immediate */
6008 if (src_reg
->has_index2
)
6009 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
6011 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
6012 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6015 case PROGRAM_IMMEDIATE
:
6016 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
6017 src
= t
->immediates
[src_reg
->index
];
6021 /* GLSL inputs are 64-bit containers, so we have to
6022 * map back to the original index and add the offset after
6024 index
-= double_reg2
;
6025 if (!src_reg
->array_id
) {
6026 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
6027 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
6028 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
6031 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
6034 unsigned mesa_index
= decl
->mesa_index
;
6035 int slot
= t
->inputMapping
[mesa_index
];
6037 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
6039 src
= t
->inputs
[slot
];
6040 src
.ArrayID
= src_reg
->array_id
;
6041 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
6045 case PROGRAM_ADDRESS
:
6046 src
= ureg_src(t
->address
[src_reg
->index
]);
6049 case PROGRAM_SYSTEM_VALUE
:
6050 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
6051 src
= t
->systemValues
[src_reg
->index
];
6054 case PROGRAM_HW_ATOMIC
:
6055 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
6060 assert(!"unknown src register file");
6061 return ureg_src_undef();
6064 if (src_reg
->has_index2
) {
6065 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6066 * and UBO constant buffers (buffer, position).
6068 if (src_reg
->reladdr2
)
6069 src
= ureg_src_dimension_indirect(src
,
6070 translate_addr(t
, src_reg
->reladdr2
, 1),
6073 src
= ureg_src_dimension(src
, src_reg
->index2D
);
6076 src
= ureg_swizzle(src
,
6077 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
6078 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
6079 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
6080 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
6083 src
= ureg_abs(src
);
6085 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
6086 src
= ureg_negate(src
);
6088 if (src_reg
->reladdr
!= NULL
) {
6089 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
6090 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
6096 static struct tgsi_texture_offset
6097 translate_tex_offset(struct st_translate
*t
,
6098 const st_src_reg
*in_offset
)
6100 struct tgsi_texture_offset offset
;
6101 struct ureg_src src
= translate_src(t
, in_offset
);
6103 offset
.File
= src
.File
;
6104 offset
.Index
= src
.Index
;
6105 offset
.SwizzleX
= src
.SwizzleX
;
6106 offset
.SwizzleY
= src
.SwizzleY
;
6107 offset
.SwizzleZ
= src
.SwizzleZ
;
6110 assert(!src
.Indirect
);
6111 assert(!src
.DimIndirect
);
6112 assert(!src
.Dimension
);
6113 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
6114 assert(!src
.Negate
);
6120 compile_tgsi_instruction(struct st_translate
*t
,
6121 const glsl_to_tgsi_instruction
*inst
)
6123 struct ureg_program
*ureg
= t
->ureg
;
6125 struct ureg_dst dst
[2];
6126 struct ureg_src src
[4];
6127 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
6131 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
6133 num_dst
= num_inst_dst_regs(inst
);
6134 num_src
= num_inst_src_regs(inst
);
6136 for (i
= 0; i
< num_dst
; i
++)
6137 dst
[i
] = translate_dst(t
,
6141 for (i
= 0; i
< num_src
; i
++)
6142 src
[i
] = translate_src(t
, &inst
->src
[i
]);
6145 case TGSI_OPCODE_BGNLOOP
:
6146 case TGSI_OPCODE_ELSE
:
6147 case TGSI_OPCODE_ENDLOOP
:
6148 case TGSI_OPCODE_IF
:
6149 case TGSI_OPCODE_UIF
:
6150 assert(num_dst
== 0);
6151 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
6154 case TGSI_OPCODE_TEX
:
6155 case TGSI_OPCODE_TEX_LZ
:
6156 case TGSI_OPCODE_TXB
:
6157 case TGSI_OPCODE_TXD
:
6158 case TGSI_OPCODE_TXL
:
6159 case TGSI_OPCODE_TXP
:
6160 case TGSI_OPCODE_TXQ
:
6161 case TGSI_OPCODE_TXQS
:
6162 case TGSI_OPCODE_TXF
:
6163 case TGSI_OPCODE_TXF_LZ
:
6164 case TGSI_OPCODE_TEX2
:
6165 case TGSI_OPCODE_TXB2
:
6166 case TGSI_OPCODE_TXL2
:
6167 case TGSI_OPCODE_TG4
:
6168 case TGSI_OPCODE_LODQ
:
6169 case TGSI_OPCODE_SAMP2HND
:
6170 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
6171 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
6173 /* Bindless samplers. */
6174 src
[num_src
] = translate_src(t
, &inst
->resource
);
6176 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
6177 if (inst
->resource
.reladdr
)
6179 ureg_src_indirect(src
[num_src
],
6180 translate_addr(t
, inst
->resource
.reladdr
, 2));
6182 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
6183 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
6185 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6191 st_translate_texture_type(inst
->tex_type
),
6192 texoffsets
, inst
->tex_offset_num_offset
,
6196 case TGSI_OPCODE_RESQ
:
6197 case TGSI_OPCODE_LOAD
:
6198 case TGSI_OPCODE_ATOMUADD
:
6199 case TGSI_OPCODE_ATOMXCHG
:
6200 case TGSI_OPCODE_ATOMCAS
:
6201 case TGSI_OPCODE_ATOMAND
:
6202 case TGSI_OPCODE_ATOMOR
:
6203 case TGSI_OPCODE_ATOMXOR
:
6204 case TGSI_OPCODE_ATOMUMIN
:
6205 case TGSI_OPCODE_ATOMUMAX
:
6206 case TGSI_OPCODE_ATOMIMIN
:
6207 case TGSI_OPCODE_ATOMIMAX
:
6208 case TGSI_OPCODE_ATOMFADD
:
6209 case TGSI_OPCODE_IMG2HND
:
6210 for (i
= num_src
- 1; i
>= 0; i
--)
6211 src
[i
+ 1] = src
[i
];
6213 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6214 src
[0] = t
->shared_memory
;
6215 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6216 src
[0] = t
->buffers
[inst
->resource
.index
];
6217 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6218 src
[0] = translate_src(t
, &inst
->resource
);
6219 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6220 assert(inst
->resource
.has_index2
);
6221 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6223 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6224 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6225 src
[0] = t
->images
[inst
->resource
.index
];
6227 /* Bindless images. */
6228 src
[0] = translate_src(t
, &inst
->resource
);
6230 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6232 if (inst
->resource
.reladdr
)
6233 src
[0] = ureg_src_indirect(src
[0],
6234 translate_addr(t
, inst
->resource
.reladdr
, 2));
6235 assert(src
[0].File
!= TGSI_FILE_NULL
);
6236 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6237 inst
->buffer_access
,
6238 tex_target
, inst
->image_format
);
6241 case TGSI_OPCODE_STORE
:
6242 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6243 dst
[0] = ureg_dst(t
->shared_memory
);
6244 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6245 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6247 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6248 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6250 /* Bindless images. */
6251 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6253 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6255 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6256 if (inst
->resource
.reladdr
)
6257 dst
[0] = ureg_dst_indirect(dst
[0],
6258 translate_addr(t
, inst
->resource
.reladdr
, 2));
6259 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6260 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6261 inst
->buffer_access
,
6262 tex_target
, inst
->image_format
);
6269 src
, num_src
, inst
->precise
);
6274 /* Invert SamplePos.y when rendering to the default framebuffer. */
6276 emit_samplepos_adjustment(struct st_translate
*t
, int wpos_y_transform
)
6278 struct ureg_program
*ureg
= t
->ureg
;
6280 assert(wpos_y_transform
>= 0);
6281 struct ureg_src trans_const
= ureg_DECL_constant(ureg
, wpos_y_transform
);
6282 struct ureg_src samplepos_sysval
= t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
];
6283 struct ureg_dst samplepos_flipped
= ureg_DECL_temporary(ureg
);
6284 struct ureg_dst is_fbo
= ureg_DECL_temporary(ureg
);
6286 ureg_ADD(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6287 ureg_imm1f(ureg
, 1), ureg_negate(samplepos_sysval
));
6289 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6290 ureg_FSEQ(ureg
, ureg_writemask(is_fbo
, TGSI_WRITEMASK_Y
),
6291 ureg_scalar(trans_const
, TGSI_SWIZZLE_X
), ureg_imm1f(ureg
, 1));
6292 ureg_UCMP(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6293 ureg_src(is_fbo
), samplepos_sysval
, ureg_src(samplepos_flipped
));
6294 ureg_MOV(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_X
),
6297 /* Use the result in place of the system value. */
6298 t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
] = ureg_src(samplepos_flipped
);
6303 * Emit the TGSI instructions for inverting and adjusting WPOS.
6304 * This code is unavoidable because it also depends on whether
6305 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6308 emit_wpos_adjustment(struct gl_context
*ctx
,
6309 struct st_translate
*t
,
6310 int wpos_transform_const
,
6312 GLfloat adjX
, GLfloat adjY
[2])
6314 struct ureg_program
*ureg
= t
->ureg
;
6316 assert(wpos_transform_const
>= 0);
6318 /* Fragment program uses fragment position input.
6319 * Need to replace instances of INPUT[WPOS] with temp T
6320 * where T = INPUT[WPOS] is inverted by Y.
6322 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6323 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6324 struct ureg_src
*wpos
=
6325 ctx
->Const
.GLSLFragCoordIsSysVal
?
6326 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6327 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6328 struct ureg_src wpos_input
= *wpos
;
6330 /* First, apply the coordinate shift: */
6331 if (adjX
|| adjY
[0] || adjY
[1]) {
6332 if (adjY
[0] != adjY
[1]) {
6333 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6334 * depending on whether inversion is actually going to be applied
6335 * or not, which is determined by testing against the inversion
6336 * state variable used below, which will be either +1 or -1.
6338 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6340 ureg_CMP(ureg
, adj_temp
,
6341 ureg_scalar(wpostrans
, invert
? 2 : 0),
6342 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6343 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6344 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6346 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6347 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6349 wpos_input
= ureg_src(wpos_temp
);
6351 /* MOV wpos_temp, input[wpos]
6353 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6356 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6357 * inversion/identity, or the other way around if we're drawing to an FBO.
6360 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6363 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6365 ureg_scalar(wpostrans
, 0),
6366 ureg_scalar(wpostrans
, 1));
6368 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6371 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6373 ureg_scalar(wpostrans
, 2),
6374 ureg_scalar(wpostrans
, 3));
6377 /* Use wpos_temp as position input from here on:
6379 *wpos
= ureg_src(wpos_temp
);
6384 * Emit fragment position/ooordinate code.
6387 emit_wpos(struct st_context
*st
,
6388 struct st_translate
*t
,
6389 const struct gl_program
*program
,
6390 struct ureg_program
*ureg
,
6391 int wpos_transform_const
)
6393 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6394 GLfloat adjX
= 0.0f
;
6395 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6396 boolean invert
= FALSE
;
6398 /* Query the pixel center conventions supported by the pipe driver and set
6399 * adjX, adjY to help out if it cannot handle the requested one internally.
6401 * The bias of the y-coordinate depends on whether y-inversion takes place
6402 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6403 * drawing to an FBO (causes additional inversion), and whether the pipe
6404 * driver origin and the requested origin differ (the latter condition is
6405 * stored in the 'invert' variable).
6407 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6409 * center shift only:
6414 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6415 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6416 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6417 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6419 * inversion and center shift:
6420 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6421 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6422 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6423 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6425 if (program
->OriginUpperLeft
) {
6426 /* Fragment shader wants origin in upper-left */
6427 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6428 /* the driver supports upper-left origin */
6430 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6431 /* the driver supports lower-left origin, need to invert Y */
6432 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6433 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6440 /* Fragment shader wants origin in lower-left */
6441 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6442 /* the driver supports lower-left origin */
6443 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6444 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6445 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6446 /* the driver supports upper-left origin, need to invert Y */
6452 if (program
->PixelCenterInteger
) {
6453 /* Fragment shader wants pixel center integer */
6454 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6455 /* the driver supports pixel center integer */
6457 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6458 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6460 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6461 /* the driver supports pixel center half integer, need to bias X,Y */
6470 /* Fragment shader wants pixel center half integer */
6471 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6472 /* the driver supports pixel center half integer */
6474 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6475 /* the driver supports pixel center integer, need to bias X,Y */
6476 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6477 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6478 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6484 /* we invert after adjustment so that we avoid the MOV to temporary,
6485 * and reuse the adjustment ADD instead */
6486 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6490 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6491 * TGSI uses +1 for front, -1 for back.
6492 * This function converts the TGSI value to the GL value. Simply clamping/
6493 * saturating the value to [0,1] does the job.
6496 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6498 struct ureg_program
*ureg
= t
->ureg
;
6499 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6500 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6502 if (ctx
->Const
.NativeIntegers
) {
6503 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6506 /* MOV_SAT face_temp, input[face] */
6507 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6510 /* Use face_temp as face input from here on: */
6511 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6515 emit_compute_block_size(const struct gl_program
*prog
,
6516 struct ureg_program
*ureg
) {
6517 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6518 prog
->info
.cs
.local_size
[0]);
6519 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6520 prog
->info
.cs
.local_size
[1]);
6521 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6522 prog
->info
.cs
.local_size
[2]);
6525 struct sort_inout_decls
{
6526 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6527 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6530 const ubyte
*mapping
;
6533 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6535 * This is for the benefit of older drivers which are broken when the
6536 * declarations aren't sorted in this way.
6539 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6541 const ubyte mapping
[])
6543 sort_inout_decls sorter
;
6544 sorter
.mapping
= mapping
;
6545 std::sort(decls
, decls
+ count
, sorter
);
6548 static enum tgsi_interpolate_mode
6549 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6551 switch (glsl_qual
) {
6552 case INTERP_MODE_NONE
:
6553 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6554 return TGSI_INTERPOLATE_COLOR
;
6555 return TGSI_INTERPOLATE_PERSPECTIVE
;
6556 case INTERP_MODE_SMOOTH
:
6557 return TGSI_INTERPOLATE_PERSPECTIVE
;
6558 case INTERP_MODE_FLAT
:
6559 return TGSI_INTERPOLATE_CONSTANT
;
6560 case INTERP_MODE_NOPERSPECTIVE
:
6561 return TGSI_INTERPOLATE_LINEAR
;
6563 assert(0 && "unexpected interp mode in st_translate_interp()");
6564 return TGSI_INTERPOLATE_PERSPECTIVE
;
6569 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6570 * \param program the program to translate
6571 * \param numInputs number of input registers used
6572 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6574 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6575 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6577 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6578 * \param numOutputs number of output registers used
6579 * \param outputMapping maps Mesa fragment program outputs to TGSI
6581 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6582 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6585 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6587 extern "C" enum pipe_error
6588 st_translate_program(
6589 struct gl_context
*ctx
,
6590 enum pipe_shader_type procType
,
6591 struct ureg_program
*ureg
,
6592 glsl_to_tgsi_visitor
*program
,
6593 const struct gl_program
*proginfo
,
6595 const ubyte inputMapping
[],
6596 const ubyte inputSlotToAttr
[],
6597 const ubyte inputSemanticName
[],
6598 const ubyte inputSemanticIndex
[],
6599 const ubyte interpMode
[],
6601 const ubyte outputMapping
[],
6602 const ubyte outputSemanticName
[],
6603 const ubyte outputSemanticIndex
[])
6605 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6606 struct st_translate
*t
;
6608 struct gl_program_constants
*frag_const
=
6609 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6610 enum pipe_error ret
= PIPE_OK
;
6612 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6613 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6615 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6616 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6617 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6618 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6619 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6620 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6621 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6622 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6623 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6624 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6626 t
= CALLOC_STRUCT(st_translate
);
6628 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6632 t
->procType
= procType
;
6633 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6634 t
->inputMapping
= inputMapping
;
6635 t
->outputMapping
= outputMapping
;
6637 t
->num_temp_arrays
= program
->next_array
;
6638 if (t
->num_temp_arrays
)
6639 t
->arrays
= (struct ureg_dst
*)
6640 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6643 * Declare input attributes.
6646 case PIPE_SHADER_FRAGMENT
:
6647 case PIPE_SHADER_GEOMETRY
:
6648 case PIPE_SHADER_TESS_EVAL
:
6649 case PIPE_SHADER_TESS_CTRL
:
6650 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6652 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6653 struct inout_decl
*decl
= &program
->inputs
[i
];
6654 unsigned slot
= inputMapping
[decl
->mesa_index
];
6655 struct ureg_src src
;
6656 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6658 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6659 if (tgsi_usage_mask
== 1)
6660 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6661 else if (tgsi_usage_mask
== 2)
6662 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6664 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6667 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6668 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6669 if (procType
== PIPE_SHADER_FRAGMENT
) {
6671 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6672 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6673 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6675 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6678 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6679 (enum tgsi_semantic
) inputSemanticName
[slot
],
6680 inputSemanticIndex
[slot
],
6681 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6682 decl
->array_id
, decl
->size
);
6684 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6685 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6686 /* The ArrayID is set up in dst_register */
6687 t
->inputs
[slot
+ j
] = src
;
6688 t
->inputs
[slot
+ j
].ArrayID
= 0;
6689 t
->inputs
[slot
+ j
].Index
+= j
;
6694 case PIPE_SHADER_VERTEX
:
6695 for (i
= 0; i
< numInputs
; i
++) {
6696 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6699 case PIPE_SHADER_COMPUTE
:
6706 * Declare output attributes.
6709 case PIPE_SHADER_FRAGMENT
:
6710 case PIPE_SHADER_COMPUTE
:
6712 case PIPE_SHADER_GEOMETRY
:
6713 case PIPE_SHADER_TESS_EVAL
:
6714 case PIPE_SHADER_TESS_CTRL
:
6715 case PIPE_SHADER_VERTEX
:
6716 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6718 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6719 struct inout_decl
*decl
= &program
->outputs
[i
];
6720 unsigned slot
= outputMapping
[decl
->mesa_index
];
6721 struct ureg_dst dst
;
6722 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6724 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6725 if (tgsi_usage_mask
== 1)
6726 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6727 else if (tgsi_usage_mask
== 2)
6728 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6730 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6733 dst
= ureg_DECL_output_layout(ureg
,
6734 (enum tgsi_semantic
) outputSemanticName
[slot
],
6735 outputSemanticIndex
[slot
],
6736 decl
->gs_out_streams
,
6737 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6738 dst
.Invariant
= decl
->invariant
;
6739 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6740 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6741 /* The ArrayID is set up in dst_register */
6742 t
->outputs
[slot
+ j
] = dst
;
6743 t
->outputs
[slot
+ j
].ArrayID
= 0;
6744 t
->outputs
[slot
+ j
].Index
+= j
;
6745 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6754 if (procType
== PIPE_SHADER_FRAGMENT
) {
6755 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6756 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6757 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6759 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6760 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6763 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6764 /* Must do this after setting up t->inputs. */
6765 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6766 program
->wpos_transform_const
);
6769 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6770 emit_face_var(ctx
, t
);
6772 for (i
= 0; i
< numOutputs
; i
++) {
6773 switch (outputSemanticName
[i
]) {
6774 case TGSI_SEMANTIC_POSITION
:
6775 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6776 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6777 outputSemanticIndex
[i
]);
6778 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6780 case TGSI_SEMANTIC_STENCIL
:
6781 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6782 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6783 outputSemanticIndex
[i
]);
6784 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6786 case TGSI_SEMANTIC_COLOR
:
6787 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6788 TGSI_SEMANTIC_COLOR
,
6789 outputSemanticIndex
[i
]);
6791 case TGSI_SEMANTIC_SAMPLEMASK
:
6792 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6793 TGSI_SEMANTIC_SAMPLEMASK
,
6794 outputSemanticIndex
[i
]);
6795 /* TODO: If we ever support more than 32 samples, this will have
6796 * to become an array.
6798 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6801 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6802 ret
= PIPE_ERROR_BAD_INPUT
;
6807 else if (procType
== PIPE_SHADER_VERTEX
) {
6808 for (i
= 0; i
< numOutputs
; i
++) {
6809 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6810 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6812 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6813 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6814 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6819 if (procType
== PIPE_SHADER_COMPUTE
) {
6820 emit_compute_block_size(proginfo
, ureg
);
6823 /* Declare address register.
6825 if (program
->num_address_regs
> 0) {
6826 assert(program
->num_address_regs
<= 3);
6827 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6828 t
->address
[i
] = ureg_DECL_address(ureg
);
6831 /* Declare misc input registers
6834 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6836 for (i
= 0; sysInputs
; i
++) {
6837 if (sysInputs
& (1ull << i
)) {
6838 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6840 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6842 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6843 semName
== TGSI_SEMANTIC_VERTEXID
) {
6844 /* From Gallium perspective, these system values are always
6845 * integer, and require native integer support. However, if
6846 * native integer is supported on the vertex stage but not the
6847 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6848 * assumes these system values are floats. To resolve the
6849 * inconsistency, we insert a U2F.
6851 struct st_context
*st
= st_context(ctx
);
6852 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6853 assert(procType
== PIPE_SHADER_VERTEX
);
6854 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6856 if (!ctx
->Const
.NativeIntegers
) {
6857 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6858 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6859 t
->systemValues
[i
]);
6860 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6864 if (procType
== PIPE_SHADER_FRAGMENT
&&
6865 semName
== TGSI_SEMANTIC_POSITION
)
6866 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6867 program
->wpos_transform_const
);
6869 if (procType
== PIPE_SHADER_FRAGMENT
&&
6870 semName
== TGSI_SEMANTIC_SAMPLEPOS
)
6871 emit_samplepos_adjustment(t
, program
->wpos_transform_const
);
6873 sysInputs
&= ~(1ull << i
);
6878 t
->array_sizes
= program
->array_sizes
;
6879 t
->input_decls
= program
->inputs
;
6880 t
->num_input_decls
= program
->num_inputs
;
6881 t
->output_decls
= program
->outputs
;
6882 t
->num_output_decls
= program
->num_outputs
;
6884 /* Emit constants and uniforms. TGSI uses a single index space for these,
6885 * so we put all the translated regs in t->constants.
6887 if (proginfo
->Parameters
) {
6888 t
->constants
= (struct ureg_src
*)
6889 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6890 if (t
->constants
== NULL
) {
6891 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6894 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6896 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6897 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6899 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6900 case PROGRAM_STATE_VAR
:
6901 case PROGRAM_UNIFORM
:
6902 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6905 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6906 * addressing of the const buffer.
6907 * FIXME: Be smarter and recognize param arrays:
6908 * indirect addressing is only valid within the referenced
6911 case PROGRAM_CONSTANT
:
6912 if (program
->indirect_addr_consts
)
6913 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6915 t
->constants
[i
] = emit_immediate(t
,
6916 proginfo
->Parameters
->ParameterValues
+ pvo
,
6917 proginfo
->Parameters
->Parameters
[i
].DataType
,
6926 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6927 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6928 unsigned num_const_vecs
= (size
+ 15) / 16;
6929 unsigned first
, last
;
6930 assert(num_const_vecs
> 0);
6932 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6933 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6936 /* Emit immediate values.
6938 t
->immediates
= (struct ureg_src
*)
6939 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6940 if (t
->immediates
== NULL
) {
6941 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6944 t
->num_immediates
= program
->num_immediates
;
6947 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6948 assert(i
< program
->num_immediates
);
6949 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6951 assert(i
== program
->num_immediates
);
6953 /* texture samplers */
6954 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6955 if (program
->samplers_used
& (1u << i
)) {
6956 enum tgsi_return_type type
=
6957 st_translate_texture_type(program
->sampler_types
[i
]);
6959 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6961 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
6962 type
, type
, type
, type
);
6966 /* Declare atomic and shader storage buffers. */
6968 struct gl_program
*prog
= program
->prog
;
6970 if (!st_context(ctx
)->has_hw_atomics
) {
6971 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6972 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6973 assert(index
< frag_const
->MaxAtomicBuffers
);
6974 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6977 for (i
= 0; i
< program
->num_atomics
; i
++) {
6978 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
6979 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
6980 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
6981 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
6986 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6987 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6989 if (!st_context(ctx
)->has_hw_atomics
)
6990 index
+= frag_const
->MaxAtomicBuffers
;
6992 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6996 if (program
->use_shared_memory
)
6997 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6999 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
7000 if (program
->images_used
& (1 << i
)) {
7001 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
7002 program
->image_targets
[i
],
7003 program
->image_formats
[i
],
7004 program
->image_wr
[i
],
7009 /* Emit each instruction in turn:
7011 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
7012 compile_tgsi_instruction(t
, inst
);
7014 /* Set the next shader stage hint for VS and TES. */
7016 case PIPE_SHADER_VERTEX
:
7017 case PIPE_SHADER_TESS_EVAL
:
7018 if (program
->shader_program
->SeparateShader
)
7021 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
7022 if (program
->shader_program
->_LinkedShaders
[i
]) {
7023 ureg_set_next_shader_processor(
7024 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
7030 ; /* nothing - silence compiler warning */
7038 t
->num_constants
= 0;
7039 free(t
->immediates
);
7040 t
->num_immediates
= 0;
7046 /* ----------------------------- End TGSI code ------------------------------ */
7050 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7051 * generating Mesa IR.
7053 static struct gl_program
*
7054 get_mesa_program_tgsi(struct gl_context
*ctx
,
7055 struct gl_shader_program
*shader_program
,
7056 struct gl_linked_shader
*shader
)
7058 glsl_to_tgsi_visitor
* v
;
7059 struct gl_program
*prog
;
7060 struct gl_shader_compiler_options
*options
=
7061 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
7062 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7063 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
7064 unsigned skip_merge_registers
;
7066 validate_ir_tree(shader
->ir
);
7068 prog
= shader
->Program
;
7070 prog
->Parameters
= _mesa_new_parameter_list();
7071 v
= new glsl_to_tgsi_visitor();
7074 v
->shader_program
= shader_program
;
7076 v
->options
= options
;
7077 v
->native_integers
= ctx
->Const
.NativeIntegers
;
7079 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
7080 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
7081 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
7082 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
7083 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
7084 PIPE_CAP_TGSI_TEX_TXF_LZ
);
7085 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
7087 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
7088 _mesa_key_pointer_equal
);
7089 skip_merge_registers
=
7090 pscreen
->get_shader_param(pscreen
, ptarget
,
7091 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
7093 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
7096 /* Remove reads from output registers. */
7097 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
7098 lower_output_reads(shader
->Stage
, shader
->ir
);
7100 /* Emit intermediate IR for main(). */
7101 visit_exec_list(shader
->ir
, v
);
7104 /* Print out some information (for debugging purposes) used by the
7105 * optimization passes. */
7108 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7109 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7110 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7111 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7113 for (i
= 0; i
< v
->next_temp
; i
++) {
7114 first_writes
[i
] = -1;
7115 first_reads
[i
] = -1;
7116 last_writes
[i
] = -1;
7119 v
->get_first_temp_read(first_reads
);
7120 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
7121 v
->get_last_temp_write(last_writes
);
7122 for (i
= 0; i
< v
->next_temp
; i
++)
7123 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
7127 ralloc_free(first_writes
);
7128 ralloc_free(first_reads
);
7129 ralloc_free(last_writes
);
7130 ralloc_free(last_reads
);
7134 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7136 v
->copy_propagate();
7138 while (v
->eliminate_dead_code());
7140 v
->merge_two_dsts();
7142 if (!skip_merge_registers
) {
7144 v
->copy_propagate();
7145 while (v
->eliminate_dead_code());
7147 v
->merge_registers();
7148 v
->copy_propagate();
7149 while (v
->eliminate_dead_code());
7152 v
->renumber_registers();
7154 /* Write the END instruction. */
7155 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
7157 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
7159 _mesa_log("GLSL IR for linked %s program %d:\n",
7160 _mesa_shader_stage_to_string(shader
->Stage
),
7161 shader_program
->Name
);
7162 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
7166 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
7167 _mesa_copy_linked_program_data(shader_program
, shader
);
7168 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
7169 &prog
->info
.inputs_read
,
7170 prog
->DualSlotInputs
,
7171 &prog
->info
.patch_inputs_read
);
7172 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
7173 &prog
->info
.outputs_written
, 0ULL,
7174 &prog
->info
.patch_outputs_written
);
7175 count_resources(v
, prog
);
7177 /* The GLSL IR won't be needed anymore. */
7178 ralloc_free(shader
->ir
);
7181 /* This must be done before the uniform storage is associated. */
7182 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
7183 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
7184 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
) ||
7185 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_SAMPLE_POS
))) {
7186 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
7187 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
7190 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
7191 wposTransformState
);
7194 /* Avoid reallocation of the program parameter list, because the uniform
7195 * storage is only associated with the original parameter list.
7196 * This should be enough for Bitmap and DrawPixels constants.
7198 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
7200 /* This has to be done last. Any operation the can cause
7201 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7202 * program constant) has to happen before creating this linkage.
7204 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
7205 if (!shader_program
->data
->LinkStatus
) {
7206 free_glsl_to_tgsi_visitor(v
);
7207 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7211 struct st_vertex_program
*stvp
;
7212 struct st_fragment_program
*stfp
;
7213 struct st_common_program
*stp
;
7214 struct st_compute_program
*stcp
;
7216 switch (shader
->Stage
) {
7217 case MESA_SHADER_VERTEX
:
7218 stvp
= (struct st_vertex_program
*)prog
;
7219 stvp
->glsl_to_tgsi
= v
;
7221 case MESA_SHADER_FRAGMENT
:
7222 stfp
= (struct st_fragment_program
*)prog
;
7223 stfp
->glsl_to_tgsi
= v
;
7225 case MESA_SHADER_TESS_CTRL
:
7226 case MESA_SHADER_TESS_EVAL
:
7227 case MESA_SHADER_GEOMETRY
:
7228 stp
= st_common_program(prog
);
7229 stp
->glsl_to_tgsi
= v
;
7231 case MESA_SHADER_COMPUTE
:
7232 stcp
= (struct st_compute_program
*)prog
;
7233 stcp
->glsl_to_tgsi
= v
;
7236 assert(!"should not be reached");
7240 PRINT_STATS(v
->print_stats());
7245 /* See if there are unsupported control flow statements. */
7246 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7248 const struct gl_shader_compiler_options
*options
;
7250 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7256 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7258 /* Other functions are skipped (same as glsl_to_tgsi). */
7259 if (strcmp(ir
->name
, "main") == 0)
7260 return visit_continue
;
7262 return visit_continue_with_parent
;
7265 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7267 if (!ir
->callee
->is_intrinsic()) {
7268 unsupported
= true; /* it's a function call */
7271 return visit_continue
;
7274 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7276 if (options
->EmitNoMainReturn
) {
7280 return visit_continue
;
7287 has_unsupported_control_flow(exec_list
*ir
,
7288 const struct gl_shader_compiler_options
*options
)
7290 ir_control_flow_info_visitor
visitor(options
);
7291 visit_list_elements(&visitor
, ir
);
7292 return visitor
.unsupported
;
7299 * Called via ctx->Driver.LinkShader()
7300 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7301 * with code lowering and other optimizations.
7304 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7306 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7308 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7309 pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
,
7310 PIPE_SHADER_CAP_PREFERRED_IR
);
7311 bool use_nir
= preferred_ir
== PIPE_SHADER_IR_NIR
;
7313 /* Return early if we are loading the shader from on-disk cache */
7314 if (st_load_ir_from_disk_cache(ctx
, prog
, use_nir
)) {
7318 assert(prog
->data
->LinkStatus
);
7320 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7321 if (prog
->_LinkedShaders
[i
] == NULL
)
7324 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7325 exec_list
*ir
= shader
->ir
;
7326 gl_shader_stage stage
= shader
->Stage
;
7327 const struct gl_shader_compiler_options
*options
=
7328 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7329 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7330 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7331 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7332 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7333 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7334 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7335 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
7336 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7337 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7339 /* If there are forms of indirect addressing that the driver
7340 * cannot handle, perform the lowering pass.
7342 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7343 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7344 lower_variable_index_to_cond_assign(stage
, ir
,
7345 options
->EmitNoIndirectInput
,
7346 options
->EmitNoIndirectOutput
,
7347 options
->EmitNoIndirectTemp
,
7348 options
->EmitNoIndirectUniform
);
7351 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7352 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7354 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7355 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7356 LOWER_UNPACK_SNORM_2x16
|
7357 LOWER_PACK_UNORM_2x16
|
7358 LOWER_UNPACK_UNORM_2x16
|
7359 LOWER_PACK_SNORM_4x8
|
7360 LOWER_UNPACK_SNORM_4x8
|
7361 LOWER_UNPACK_UNORM_4x8
|
7362 LOWER_PACK_UNORM_4x8
;
7364 if (ctx
->Extensions
.ARB_gpu_shader5
)
7365 lower_inst
|= LOWER_PACK_USE_BFI
|
7367 if (!ctx
->st
->has_half_float_packing
)
7368 lower_inst
|= LOWER_PACK_HALF_2x16
|
7369 LOWER_UNPACK_HALF_2x16
;
7371 lower_packing_builtins(ir
, lower_inst
);
7374 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7375 lower_offset_arrays(ir
);
7376 do_mat_op_to_vec(ir
);
7378 if (stage
== MESA_SHADER_FRAGMENT
)
7379 lower_blend_equation_advanced(
7380 shader
, ctx
->Extensions
.KHR_blend_equation_advanced_coherent
);
7382 lower_instructions(ir
,
7387 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
7388 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7391 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7392 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7393 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7394 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7395 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7396 /* Assume that if ARB_gpu_shader5 is not supported
7397 * then all of the extended integer functions need
7398 * lowering. It may be necessary to add some caps
7399 * for individual instructions.
7401 (!ctx
->Extensions
.ARB_gpu_shader5
7402 ? BIT_COUNT_TO_MATH
|
7406 FIND_LSB_TO_FLOAT_CAST
|
7407 FIND_MSB_TO_FLOAT_CAST
|
7411 do_vec_index_to_cond_assign(ir
);
7412 lower_vector_insert(ir
, true);
7413 lower_quadop_vector(ir
, false);
7415 if (options
->MaxIfDepth
== 0) {
7419 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7420 /* Do it once and repeat only if there's unsupported control flow. */
7422 do_common_optimization(ir
, true, true, options
,
7423 ctx
->Const
.NativeIntegers
);
7424 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7425 options
->MaxIfDepth
, if_threshold
);
7426 } while (has_unsupported_control_flow(ir
, options
));
7428 /* Repeat it until it stops making changes. */
7431 progress
= do_common_optimization(ir
, true, true, options
,
7432 ctx
->Const
.NativeIntegers
);
7433 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7434 options
->MaxIfDepth
, if_threshold
);
7438 /* Do this again to lower ir_binop_vector_extract introduced
7439 * by optimization passes.
7441 do_vec_index_to_cond_assign(ir
);
7443 validate_ir_tree(ir
);
7446 build_program_resource_list(ctx
, prog
);
7449 return st_link_nir(ctx
, prog
);
7451 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7452 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7456 struct gl_program
*linked_prog
=
7457 get_mesa_program_tgsi(ctx
, prog
, shader
);
7458 st_set_prog_affected_state_flags(linked_prog
);
7461 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7462 _mesa_shader_stage_to_program(i
),
7464 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7474 st_translate_stream_output_info(struct gl_transform_feedback_info
*info
,
7475 const ubyte outputMapping
[],
7476 struct pipe_stream_output_info
*so
)
7481 so
->num_outputs
= 0;
7485 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7486 so
->output
[i
].register_index
=
7487 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7488 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7489 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7490 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7491 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7492 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7495 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7496 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7498 so
->num_outputs
= info
->NumOutputs
;