2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "glsl_parser_extras.h"
36 #include "ir_optimization.h"
38 #include "main/errors.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "main/shaderapi.h"
42 #include "program/prog_instruction.h"
43 #include "program/sampler.h"
45 #include "pipe/p_context.h"
46 #include "pipe/p_screen.h"
47 #include "tgsi/tgsi_ureg.h"
48 #include "tgsi/tgsi_info.h"
49 #include "util/u_math.h"
50 #include "util/u_memory.h"
51 #include "st_program.h"
52 #include "st_mesa_to_tgsi.h"
55 #define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
56 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
57 (1 << PROGRAM_CONSTANT) | \
58 (1 << PROGRAM_UNIFORM))
60 #define MAX_GLSL_TEXTURE_OFFSET 4
65 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to TGSI ureg_src.
72 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
84 this->reladdr2
= NULL
;
85 this->has_index2
= false;
86 this->double_reg2
= false;
90 st_src_reg(gl_register_file file
, int index
, int type
)
96 this->swizzle
= SWIZZLE_XYZW
;
99 this->reladdr2
= NULL
;
100 this->has_index2
= false;
101 this->double_reg2
= false;
105 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
110 this->index2D
= index2D
;
111 this->swizzle
= SWIZZLE_XYZW
;
113 this->reladdr
= NULL
;
114 this->reladdr2
= NULL
;
115 this->has_index2
= false;
116 this->double_reg2
= false;
122 this->type
= GLSL_TYPE_ERROR
;
123 this->file
= PROGRAM_UNDEFINED
;
128 this->reladdr
= NULL
;
129 this->reladdr2
= NULL
;
130 this->has_index2
= false;
131 this->double_reg2
= false;
135 explicit st_src_reg(st_dst_reg reg
);
137 gl_register_file file
; /**< PROGRAM_* from Mesa */
138 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
140 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
141 int negate
; /**< NEGATE_XYZW mask from mesa */
142 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
143 /** Register index should be offset by the integer in this reg. */
145 st_src_reg
*reladdr2
;
148 * Is this the second half of a double register pair?
149 * currently used for input mapping only.
157 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
162 this->writemask
= writemask
;
163 this->cond_mask
= COND_TR
;
164 this->reladdr
= NULL
;
165 this->reladdr2
= NULL
;
166 this->has_index2
= false;
171 st_dst_reg(gl_register_file file
, int writemask
, int type
)
176 this->writemask
= writemask
;
177 this->cond_mask
= COND_TR
;
178 this->reladdr
= NULL
;
179 this->reladdr2
= NULL
;
180 this->has_index2
= false;
187 this->type
= GLSL_TYPE_ERROR
;
188 this->file
= PROGRAM_UNDEFINED
;
192 this->cond_mask
= COND_TR
;
193 this->reladdr
= NULL
;
194 this->reladdr2
= NULL
;
195 this->has_index2
= false;
199 explicit st_dst_reg(st_src_reg reg
);
201 gl_register_file file
; /**< PROGRAM_* from Mesa */
202 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
204 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
206 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
207 /** Register index should be offset by the integer in this reg. */
209 st_src_reg
*reladdr2
;
214 st_src_reg::st_src_reg(st_dst_reg reg
)
216 this->type
= reg
.type
;
217 this->file
= reg
.file
;
218 this->index
= reg
.index
;
219 this->swizzle
= SWIZZLE_XYZW
;
221 this->reladdr
= reg
.reladdr
;
222 this->index2D
= reg
.index2D
;
223 this->reladdr2
= reg
.reladdr2
;
224 this->has_index2
= reg
.has_index2
;
225 this->double_reg2
= false;
226 this->array_id
= reg
.array_id
;
229 st_dst_reg::st_dst_reg(st_src_reg reg
)
231 this->type
= reg
.type
;
232 this->file
= reg
.file
;
233 this->index
= reg
.index
;
234 this->writemask
= WRITEMASK_XYZW
;
235 this->cond_mask
= COND_TR
;
236 this->reladdr
= reg
.reladdr
;
237 this->index2D
= reg
.index2D
;
238 this->reladdr2
= reg
.reladdr2
;
239 this->has_index2
= reg
.has_index2
;
240 this->array_id
= reg
.array_id
;
243 class glsl_to_tgsi_instruction
: public exec_node
{
245 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
250 /** Pointer to the ir source this tree came from for debugging */
252 GLboolean cond_update
;
254 st_src_reg sampler
; /**< sampler register */
255 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
256 int tex_target
; /**< One of TEXTURE_*_INDEX */
257 glsl_base_type tex_type
;
258 GLboolean tex_shadow
;
260 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
261 unsigned tex_offset_num_offset
;
262 int dead_mask
; /**< Used in dead code elimination */
264 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
265 const struct tgsi_opcode_info
*info
;
268 class variable_storage
: public exec_node
{
270 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
271 unsigned array_id
= 0)
272 : file(file
), index(index
), var(var
), array_id(array_id
)
277 gl_register_file file
;
279 ir_variable
*var
; /* variable that maps to this, if any */
283 class immediate_storage
: public exec_node
{
285 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
287 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
288 this->size32
= size32
;
292 /* doubles are stored across 2 gl_constant_values */
293 gl_constant_value values
[4];
294 int size32
; /**< Number of 32-bit components (1-4) */
295 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
298 class function_entry
: public exec_node
{
300 ir_function_signature
*sig
;
303 * identifier of this function signature used by the program.
305 * At the point that TGSI instructions for function calls are
306 * generated, we don't know the address of the first instruction of
307 * the function body. So we make the BranchTarget that is called a
308 * small integer and rewrite them during set_branchtargets().
313 * Pointer to first instruction of the function body.
315 * Set during function body emits after main() is processed.
317 glsl_to_tgsi_instruction
*bgn_inst
;
320 * Index of the first instruction of the function body in actual TGSI.
322 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
326 /** Storage for the return value. */
327 st_src_reg return_reg
;
330 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
331 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
339 struct rename_reg_pair
{
344 struct glsl_to_tgsi_visitor
: public ir_visitor
{
346 glsl_to_tgsi_visitor();
347 ~glsl_to_tgsi_visitor();
349 function_entry
*current_function
;
351 struct gl_context
*ctx
;
352 struct gl_program
*prog
;
353 struct gl_shader_program
*shader_program
;
354 struct gl_shader
*shader
;
355 struct gl_shader_compiler_options
*options
;
359 unsigned *array_sizes
;
360 unsigned max_num_arrays
;
363 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
364 unsigned num_input_arrays
;
365 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
366 unsigned num_output_arrays
;
368 int num_address_regs
;
370 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
371 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
372 bool indirect_addr_consts
;
373 int wpos_transform_const
;
376 bool native_integers
;
380 variable_storage
*find_variable_storage(ir_variable
*var
);
382 int add_constant(gl_register_file file
, gl_constant_value values
[8],
383 int size
, int datatype
, GLuint
*swizzle_out
);
385 function_entry
*get_function_signature(ir_function_signature
*sig
);
387 st_src_reg
get_temp(const glsl_type
*type
);
388 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
390 st_src_reg
st_src_reg_for_double(double val
);
391 st_src_reg
st_src_reg_for_float(float val
);
392 st_src_reg
st_src_reg_for_int(int val
);
393 st_src_reg
st_src_reg_for_type(int type
, int val
);
396 * \name Visit methods
398 * As typical for the visitor pattern, there must be one \c visit method for
399 * each concrete subclass of \c ir_instruction. Virtual base classes within
400 * the hierarchy should not have \c visit methods.
403 virtual void visit(ir_variable
*);
404 virtual void visit(ir_loop
*);
405 virtual void visit(ir_loop_jump
*);
406 virtual void visit(ir_function_signature
*);
407 virtual void visit(ir_function
*);
408 virtual void visit(ir_expression
*);
409 virtual void visit(ir_swizzle
*);
410 virtual void visit(ir_dereference_variable
*);
411 virtual void visit(ir_dereference_array
*);
412 virtual void visit(ir_dereference_record
*);
413 virtual void visit(ir_assignment
*);
414 virtual void visit(ir_constant
*);
415 virtual void visit(ir_call
*);
416 virtual void visit(ir_return
*);
417 virtual void visit(ir_discard
*);
418 virtual void visit(ir_texture
*);
419 virtual void visit(ir_if
*);
420 virtual void visit(ir_emit_vertex
*);
421 virtual void visit(ir_end_primitive
*);
422 virtual void visit(ir_barrier
*);
427 /** List of variable_storage */
430 /** List of immediate_storage */
431 exec_list immediates
;
432 unsigned num_immediates
;
434 /** List of function_entry */
435 exec_list function_signatures
;
436 int next_signature_id
;
438 /** List of glsl_to_tgsi_instruction */
439 exec_list instructions
;
441 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
442 st_dst_reg dst
= undef_dst
,
443 st_src_reg src0
= undef_src
,
444 st_src_reg src1
= undef_src
,
445 st_src_reg src2
= undef_src
,
446 st_src_reg src3
= undef_src
);
448 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
449 st_dst_reg dst
, st_dst_reg dst1
,
450 st_src_reg src0
= undef_src
,
451 st_src_reg src1
= undef_src
,
452 st_src_reg src2
= undef_src
,
453 st_src_reg src3
= undef_src
);
455 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
457 st_src_reg src0
, st_src_reg src1
);
460 * Emit the correct dot-product instruction for the type of arguments
462 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
468 void emit_scalar(ir_instruction
*ir
, unsigned op
,
469 st_dst_reg dst
, st_src_reg src0
);
471 void emit_scalar(ir_instruction
*ir
, unsigned op
,
472 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
474 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
476 bool try_emit_mad(ir_expression
*ir
,
478 bool try_emit_mad_for_and_not(ir_expression
*ir
,
481 void emit_swz(ir_expression
*ir
);
483 bool process_move_condition(ir_rvalue
*ir
);
485 void simplify_cmp(void);
487 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
488 void get_first_temp_read(int *first_reads
);
489 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
490 void get_last_temp_write(int *last_writes
);
492 void copy_propagate(void);
493 int eliminate_dead_code(void);
495 void merge_two_dsts(void);
496 void merge_registers(void);
497 void renumber_registers(void);
499 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
500 st_dst_reg
*l
, st_src_reg
*r
,
501 st_src_reg
*cond
, bool cond_swap
);
506 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
507 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
508 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
511 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
514 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
518 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
521 prog
->LinkStatus
= GL_FALSE
;
525 swizzle_for_size(int size
)
527 static const int size_swizzles
[4] = {
528 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
529 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
530 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
531 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
534 assert((size
>= 1) && (size
<= 4));
535 return size_swizzles
[size
- 1];
539 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
541 return op
->info
->num_dst
;
545 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
547 return op
->info
->is_tex
? op
->info
->num_src
- 1 : op
->info
->num_src
;
550 glsl_to_tgsi_instruction
*
551 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
552 st_dst_reg dst
, st_dst_reg dst1
,
553 st_src_reg src0
, st_src_reg src1
,
554 st_src_reg src2
, st_src_reg src3
)
556 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
557 int num_reladdr
= 0, i
, j
;
559 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
561 /* If we have to do relative addressing, we want to load the ARL
562 * reg directly for one of the regs, and preload the other reladdr
563 * sources into temps.
565 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
566 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
567 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
568 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
569 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
570 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
572 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
573 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
574 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
575 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
577 if (dst
.reladdr
|| dst
.reladdr2
) {
579 emit_arl(ir
, address_reg
, *dst
.reladdr
);
581 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
585 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
588 assert(num_reladdr
== 0);
591 inst
->info
= tgsi_get_opcode_info(op
);
600 /* default to float, for paths where this is not initialized
601 * (since 0==UINT which is likely wrong):
603 inst
->tex_type
= GLSL_TYPE_FLOAT
;
605 inst
->function
= NULL
;
607 /* Update indirect addressing status used by TGSI */
608 if (dst
.reladdr
|| dst
.reladdr2
) {
610 case PROGRAM_STATE_VAR
:
611 case PROGRAM_CONSTANT
:
612 case PROGRAM_UNIFORM
:
613 this->indirect_addr_consts
= true;
615 case PROGRAM_IMMEDIATE
:
616 assert(!"immediates should not have indirect addressing");
623 for (i
= 0; i
< 4; i
++) {
624 if(inst
->src
[i
].reladdr
) {
625 switch(inst
->src
[i
].file
) {
626 case PROGRAM_STATE_VAR
:
627 case PROGRAM_CONSTANT
:
628 case PROGRAM_UNIFORM
:
629 this->indirect_addr_consts
= true;
631 case PROGRAM_IMMEDIATE
:
632 assert(!"immediates should not have indirect addressing");
641 this->instructions
.push_tail(inst
);
644 * This section contains the double processing.
645 * GLSL just represents doubles as single channel values,
646 * however most HW and TGSI represent doubles as pairs of register channels.
648 * so we have to fixup destination writemask/index and src swizzle/indexes.
649 * dest writemasks need to translate from single channel write mask
650 * to a dual-channel writemask, but also need to modify the index,
651 * if we are touching the Z,W fields in the pre-translated writemask.
653 * src channels have similiar index modifications along with swizzle
654 * changes to we pick the XY, ZW pairs from the correct index.
656 * GLSL [0].x -> TGSI [0].xy
657 * GLSL [0].y -> TGSI [0].zw
658 * GLSL [0].z -> TGSI [1].xy
659 * GLSL [0].w -> TGSI [1].zw
661 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
|| inst
->dst
[1].type
== GLSL_TYPE_DOUBLE
||
662 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
663 glsl_to_tgsi_instruction
*dinst
= NULL
;
664 int initial_src_swz
[4], initial_src_idx
[4];
665 int initial_dst_idx
[2], initial_dst_writemask
[2];
666 /* select the writemask for dst0 or dst1 */
667 unsigned writemask
= inst
->dst
[0].file
== PROGRAM_UNDEFINED
? inst
->dst
[1].writemask
: inst
->dst
[0].writemask
;
669 /* copy out the writemask, index and swizzles for all src/dsts. */
670 for (j
= 0; j
< 2; j
++) {
671 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
672 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
675 for (j
= 0; j
< 4; j
++) {
676 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
677 initial_src_idx
[j
] = inst
->src
[j
].index
;
681 * scan all the components in the dst writemask
682 * generate an instruction for each of them if required.
686 int i
= u_bit_scan(&writemask
);
688 /* first time use previous instruction */
692 /* create a new instructions for subsequent attempts */
693 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
697 this->instructions
.push_tail(dinst
);
700 /* modify the destination if we are splitting */
701 for (j
= 0; j
< 2; j
++) {
702 if (dinst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
) {
703 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
704 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
706 dinst
->dst
[j
].index
++;
708 /* if we aren't writing to a double, just get the bit of the initial writemask
710 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
714 /* modify the src registers */
715 for (j
= 0; j
< 4; j
++) {
716 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
718 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
719 dinst
->src
[j
].index
= initial_src_idx
[j
];
721 dinst
->src
[j
].double_reg2
= true;
722 dinst
->src
[j
].index
++;
726 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
728 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
731 /* some opcodes are special case in what they use as sources
732 - F2D is a float src0, DLDEXP is integer src1 */
733 if (op
== TGSI_OPCODE_F2D
||
734 op
== TGSI_OPCODE_DLDEXP
||
735 (op
== TGSI_OPCODE_UCMP
&& dinst
->dst
[0].type
== GLSL_TYPE_DOUBLE
)) {
736 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
748 glsl_to_tgsi_instruction
*
749 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
751 st_src_reg src0
, st_src_reg src1
,
752 st_src_reg src2
, st_src_reg src3
)
754 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
758 * Determines whether to use an integer, unsigned integer, or float opcode
759 * based on the operands and input opcode, then emits the result.
762 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
764 st_src_reg src0
, st_src_reg src1
)
766 int type
= GLSL_TYPE_FLOAT
;
768 if (op
== TGSI_OPCODE_MOV
)
771 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
772 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
773 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
774 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
776 if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
777 type
= GLSL_TYPE_DOUBLE
;
778 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
779 type
= GLSL_TYPE_FLOAT
;
780 else if (native_integers
)
781 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
783 #define case5(c, f, i, u, d) \
784 case TGSI_OPCODE_##c: \
785 if (type == GLSL_TYPE_DOUBLE) \
786 op = TGSI_OPCODE_##d; \
787 else if (type == GLSL_TYPE_INT) \
788 op = TGSI_OPCODE_##i; \
789 else if (type == GLSL_TYPE_UINT) \
790 op = TGSI_OPCODE_##u; \
792 op = TGSI_OPCODE_##f; \
795 #define case4(c, f, i, u) \
796 case TGSI_OPCODE_##c: \
797 if (type == GLSL_TYPE_INT) \
798 op = TGSI_OPCODE_##i; \
799 else if (type == GLSL_TYPE_UINT) \
800 op = TGSI_OPCODE_##u; \
802 op = TGSI_OPCODE_##f; \
805 #define case3(f, i, u) case4(f, f, i, u)
806 #define case4d(f, i, u, d) case5(f, f, i, u, d)
807 #define case3fid(f, i, d) case5(f, f, i, i, d)
808 #define case2fi(f, i) case4(f, f, i, i)
809 #define case2iu(i, u) case4(i, LAST, i, u)
811 #define casecomp(c, f, i, u, d) \
812 case TGSI_OPCODE_##c: \
813 if (type == GLSL_TYPE_DOUBLE) \
814 op = TGSI_OPCODE_##d; \
815 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
816 op = TGSI_OPCODE_##i; \
817 else if (type == GLSL_TYPE_UINT) \
818 op = TGSI_OPCODE_##u; \
819 else if (native_integers) \
820 op = TGSI_OPCODE_##f; \
822 op = TGSI_OPCODE_##c; \
826 case3fid(ADD
, UADD
, DADD
);
827 case3fid(MUL
, UMUL
, DMUL
);
828 case3fid(MAD
, UMAD
, DMAD
);
829 case3fid(FMA
, UMAD
, DFMA
);
830 case3(DIV
, IDIV
, UDIV
);
831 case4d(MAX
, IMAX
, UMAX
, DMAX
);
832 case4d(MIN
, IMIN
, UMIN
, DMIN
);
835 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
836 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
837 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
838 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
842 case3fid(SSG
, ISSG
, DSSG
);
843 case3fid(ABS
, IABS
, DABS
);
847 case2iu(IMUL_HI
, UMUL_HI
);
849 case3fid(SQRT
, SQRT
, DSQRT
);
851 case3fid(RCP
, RCP
, DRCP
);
852 case3fid(RSQ
, RSQ
, DRSQ
);
854 case3fid(FRC
, FRC
, DFRAC
);
855 case3fid(TRUNC
, TRUNC
, DTRUNC
);
856 case3fid(CEIL
, CEIL
, DCEIL
);
857 case3fid(FLR
, FLR
, DFLR
);
858 case3fid(ROUND
, ROUND
, DROUND
);
863 assert(op
!= TGSI_OPCODE_LAST
);
867 glsl_to_tgsi_instruction
*
868 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
869 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
872 static const unsigned dot_opcodes
[] = {
873 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
876 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
880 * Emits TGSI scalar opcodes to produce unique answers across channels.
882 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
883 * channel determines the result across all channels. So to do a vec4
884 * of this operation, we want to emit a scalar per source channel used
885 * to produce dest channels.
888 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
890 st_src_reg orig_src0
, st_src_reg orig_src1
)
893 int done_mask
= ~dst
.writemask
;
895 /* TGSI RCP is a scalar operation splatting results to all channels,
896 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
899 for (i
= 0; i
< 4; i
++) {
900 GLuint this_mask
= (1 << i
);
901 st_src_reg src0
= orig_src0
;
902 st_src_reg src1
= orig_src1
;
904 if (done_mask
& this_mask
)
907 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
908 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
909 for (j
= i
+ 1; j
< 4; j
++) {
910 /* If there is another enabled component in the destination that is
911 * derived from the same inputs, generate its value on this pass as
914 if (!(done_mask
& (1 << j
)) &&
915 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
916 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
917 this_mask
|= (1 << j
);
920 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
921 src0_swiz
, src0_swiz
);
922 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
923 src1_swiz
, src1_swiz
);
925 dst
.writemask
= this_mask
;
926 emit_asm(ir
, op
, dst
, src0
, src1
);
927 done_mask
|= this_mask
;
932 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
933 st_dst_reg dst
, st_src_reg src0
)
935 st_src_reg undef
= undef_src
;
937 undef
.swizzle
= SWIZZLE_XXXX
;
939 emit_scalar(ir
, op
, dst
, src0
, undef
);
943 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
944 st_dst_reg dst
, st_src_reg src0
)
946 int op
= TGSI_OPCODE_ARL
;
948 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
949 op
= TGSI_OPCODE_UARL
;
951 assert(dst
.file
== PROGRAM_ADDRESS
);
952 if (dst
.index
>= this->num_address_regs
)
953 this->num_address_regs
= dst
.index
+ 1;
955 emit_asm(NULL
, op
, dst
, src0
);
959 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
960 gl_constant_value values
[8], int size
, int datatype
,
963 if (file
== PROGRAM_CONSTANT
) {
964 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
965 size
, datatype
, swizzle_out
);
968 assert(file
== PROGRAM_IMMEDIATE
);
971 immediate_storage
*entry
;
972 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
975 /* Search immediate storage to see if we already have an identical
976 * immediate that we can use instead of adding a duplicate entry.
978 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
979 immediate_storage
*tmp
= entry
;
981 for (i
= 0; i
* 4 < size32
; i
++) {
982 int slot_size
= MIN2(size32
- (i
* 4), 4);
983 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
985 if (memcmp(tmp
->values
, &values
[i
* 4],
986 slot_size
* sizeof(gl_constant_value
)))
989 /* Everything matches, keep going until the full size is matched */
990 tmp
= (immediate_storage
*)tmp
->next
;
993 /* The full value matched */
1000 for (i
= 0; i
* 4 < size32
; i
++) {
1001 int slot_size
= MIN2(size32
- (i
* 4), 4);
1002 /* Add this immediate to the list. */
1003 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1004 this->immediates
.push_tail(entry
);
1005 this->num_immediates
++;
1011 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1013 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1014 union gl_constant_value uval
;
1017 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1023 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1025 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1026 union gl_constant_value uval
[2];
1028 uval
[0].u
= *(uint32_t *)&val
;
1029 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1030 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1036 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1038 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1039 union gl_constant_value uval
;
1041 assert(native_integers
);
1044 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1050 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1052 if (native_integers
)
1053 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1054 st_src_reg_for_int(val
);
1056 return st_src_reg_for_float(val
);
1060 type_size(const struct glsl_type
*type
)
1065 switch (type
->base_type
) {
1066 case GLSL_TYPE_UINT
:
1068 case GLSL_TYPE_FLOAT
:
1069 case GLSL_TYPE_BOOL
:
1070 if (type
->is_matrix()) {
1071 return type
->matrix_columns
;
1073 /* Regardless of size of vector, it gets a vec4. This is bad
1074 * packing for things like floats, but otherwise arrays become a
1075 * mess. Hopefully a later pass over the code can pack scalars
1076 * down if appropriate.
1081 case GLSL_TYPE_DOUBLE
:
1082 if (type
->is_matrix()) {
1083 if (type
->vector_elements
<= 2)
1084 return type
->matrix_columns
;
1086 return type
->matrix_columns
* 2;
1088 /* For doubles if we have a double or dvec2 they fit in one
1089 * vec4, else they need 2 vec4s.
1091 if (type
->vector_elements
<= 2)
1097 case GLSL_TYPE_ARRAY
:
1098 assert(type
->length
> 0);
1099 return type_size(type
->fields
.array
) * type
->length
;
1100 case GLSL_TYPE_STRUCT
:
1102 for (i
= 0; i
< type
->length
; i
++) {
1103 size
+= type_size(type
->fields
.structure
[i
].type
);
1106 case GLSL_TYPE_SAMPLER
:
1107 case GLSL_TYPE_IMAGE
:
1108 case GLSL_TYPE_SUBROUTINE
:
1109 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1113 case GLSL_TYPE_ATOMIC_UINT
:
1114 case GLSL_TYPE_INTERFACE
:
1115 case GLSL_TYPE_VOID
:
1116 case GLSL_TYPE_ERROR
:
1117 assert(!"Invalid type in type_size");
1125 * If the given GLSL type is an array or matrix or a structure containing
1126 * an array/matrix member, return true. Else return false.
1128 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1129 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1130 * we have an array that might be indexed with a variable, we need to use
1131 * the later storage type.
1134 type_has_array_or_matrix(const glsl_type
*type
)
1136 if (type
->is_array() || type
->is_matrix())
1139 if (type
->is_record()) {
1140 for (unsigned i
= 0; i
< type
->length
; i
++) {
1141 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1152 * In the initial pass of codegen, we assign temporary numbers to
1153 * intermediate results. (not SSA -- variable assignments will reuse
1157 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1161 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1165 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1166 if (next_array
>= max_num_arrays
) {
1167 max_num_arrays
+= 32;
1168 array_sizes
= (unsigned*)
1169 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1172 src
.file
= PROGRAM_ARRAY
;
1173 src
.index
= next_array
<< 16 | 0x8000;
1174 array_sizes
[next_array
] = type_size(type
);
1178 src
.file
= PROGRAM_TEMPORARY
;
1179 src
.index
= next_temp
;
1180 next_temp
+= type_size(type
);
1183 if (type
->is_array() || type
->is_record()) {
1184 src
.swizzle
= SWIZZLE_NOOP
;
1186 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1193 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1196 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1197 if (entry
->var
== var
)
1205 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1207 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1208 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1210 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1211 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1214 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1216 const ir_state_slot
*const slots
= ir
->get_state_slots();
1217 assert(slots
!= NULL
);
1219 /* Check if this statevar's setup in the STATE file exactly
1220 * matches how we'll want to reference it as a
1221 * struct/array/whatever. If not, then we need to move it into
1222 * temporary storage and hope that it'll get copy-propagated
1225 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1226 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1231 variable_storage
*storage
;
1233 if (i
== ir
->get_num_state_slots()) {
1234 /* We'll set the index later. */
1235 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1236 this->variables
.push_tail(storage
);
1240 /* The variable_storage constructor allocates slots based on the size
1241 * of the type. However, this had better match the number of state
1242 * elements that we're going to copy into the new temporary.
1244 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1246 dst
= st_dst_reg(get_temp(ir
->type
));
1248 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1250 this->variables
.push_tail(storage
);
1254 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1255 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1256 (gl_state_index
*)slots
[i
].tokens
);
1258 if (storage
->file
== PROGRAM_STATE_VAR
) {
1259 if (storage
->index
== -1) {
1260 storage
->index
= index
;
1262 assert(index
== storage
->index
+ (int)i
);
1265 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1266 * the data being moved since MOV does not care about the type of
1267 * data it is moving, and we don't want to declare registers with
1268 * array or struct types.
1270 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1271 src
.swizzle
= slots
[i
].swizzle
;
1272 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1273 /* even a float takes up a whole vec4 reg in a struct/array. */
1278 if (storage
->file
== PROGRAM_TEMPORARY
&&
1279 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1280 fail_link(this->shader_program
,
1281 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1282 ir
->name
, dst
.index
- storage
->index
,
1283 type_size(ir
->type
));
1289 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1291 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1293 visit_exec_list(&ir
->body_instructions
, this);
1295 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1299 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1302 case ir_loop_jump::jump_break
:
1303 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1305 case ir_loop_jump::jump_continue
:
1306 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1313 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1320 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1322 /* Ignore function bodies other than main() -- we shouldn't see calls to
1323 * them since they should all be inlined before we get to glsl_to_tgsi.
1325 if (strcmp(ir
->name
, "main") == 0) {
1326 const ir_function_signature
*sig
;
1329 sig
= ir
->matching_signature(NULL
, &empty
, false);
1333 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1340 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1342 int nonmul_operand
= 1 - mul_operand
;
1344 st_dst_reg result_dst
;
1346 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1347 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1350 expr
->operands
[0]->accept(this);
1352 expr
->operands
[1]->accept(this);
1354 ir
->operands
[nonmul_operand
]->accept(this);
1357 this->result
= get_temp(ir
->type
);
1358 result_dst
= st_dst_reg(this->result
);
1359 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1360 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1366 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1368 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1369 * implemented using multiplication, and logical-or is implemented using
1370 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1371 * As result, the logical expression (a & !b) can be rewritten as:
1375 * - (a * 1) - (a * b)
1379 * This final expression can be implemented as a single MAD(a, -b, a)
1383 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1385 const int other_operand
= 1 - try_operand
;
1388 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1389 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1392 ir
->operands
[other_operand
]->accept(this);
1394 expr
->operands
[0]->accept(this);
1397 b
.negate
= ~b
.negate
;
1399 this->result
= get_temp(ir
->type
);
1400 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1406 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1407 st_src_reg
*reg
, int *num_reladdr
)
1409 if (!reg
->reladdr
&& !reg
->reladdr2
)
1412 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1413 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1415 if (*num_reladdr
!= 1) {
1416 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1418 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1426 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1428 unsigned int operand
;
1429 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1430 st_src_reg result_src
;
1431 st_dst_reg result_dst
;
1433 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1435 if (ir
->operation
== ir_binop_add
) {
1436 if (try_emit_mad(ir
, 1))
1438 if (try_emit_mad(ir
, 0))
1442 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1444 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1445 if (try_emit_mad_for_and_not(ir
, 1))
1447 if (try_emit_mad_for_and_not(ir
, 0))
1451 if (ir
->operation
== ir_quadop_vector
)
1452 assert(!"ir_quadop_vector should have been lowered");
1454 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1455 this->result
.file
= PROGRAM_UNDEFINED
;
1456 ir
->operands
[operand
]->accept(this);
1457 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1458 printf("Failed to get tree for expression operand:\n");
1459 ir
->operands
[operand
]->print();
1463 op
[operand
] = this->result
;
1465 /* Matrix expression operands should have been broken down to vector
1466 * operations already.
1468 assert(!ir
->operands
[operand
]->type
->is_matrix());
1471 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1472 if (ir
->operands
[1]) {
1473 vector_elements
= MAX2(vector_elements
,
1474 ir
->operands
[1]->type
->vector_elements
);
1477 this->result
.file
= PROGRAM_UNDEFINED
;
1479 /* Storage for our result. Ideally for an assignment we'd be using
1480 * the actual storage for the result here, instead.
1482 result_src
= get_temp(ir
->type
);
1483 /* convenience for the emit functions below. */
1484 result_dst
= st_dst_reg(result_src
);
1485 /* Limit writes to the channels that will be used by result_src later.
1486 * This does limit this temp's use as a temporary for multi-instruction
1489 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1491 switch (ir
->operation
) {
1492 case ir_unop_logic_not
:
1493 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1494 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1496 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1497 * older GPUs implement SEQ using multiple instructions (i915 uses two
1498 * SGE instructions and a MUL instruction). Since our logic values are
1499 * 0.0 and 1.0, 1-x also implements !x.
1501 op
[0].negate
= ~op
[0].negate
;
1502 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1506 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1507 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1508 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1509 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1511 op
[0].negate
= ~op
[0].negate
;
1515 case ir_unop_subroutine_to_int
:
1516 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1519 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1522 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1525 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1529 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1533 assert(!"not reached: should be handled by ir_explog_to_explog2");
1536 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1539 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1542 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1544 case ir_unop_saturate
: {
1545 glsl_to_tgsi_instruction
*inst
;
1546 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1547 inst
->saturate
= true;
1552 case ir_unop_dFdx_coarse
:
1553 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1555 case ir_unop_dFdx_fine
:
1556 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1559 case ir_unop_dFdy_coarse
:
1560 case ir_unop_dFdy_fine
:
1562 /* The X component contains 1 or -1 depending on whether the framebuffer
1563 * is a FBO or the window system buffer, respectively.
1564 * It is then multiplied with the source operand of DDY.
1566 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1567 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1569 unsigned transform_y_index
=
1570 _mesa_add_state_reference(this->prog
->Parameters
,
1573 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1575 glsl_type::vec4_type
);
1576 transform_y
.swizzle
= SWIZZLE_XXXX
;
1578 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1580 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1581 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1582 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1586 case ir_unop_frexp_sig
:
1587 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1590 case ir_unop_frexp_exp
:
1591 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1594 case ir_unop_noise
: {
1595 /* At some point, a motivated person could add a better
1596 * implementation of noise. Currently not even the nvidia
1597 * binary drivers do anything more than this. In any case, the
1598 * place to do this is in the GL state tracker, not the poor
1601 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1606 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1609 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1613 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1616 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1617 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1619 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1622 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1623 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1625 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1629 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1631 case ir_binop_greater
:
1632 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1634 case ir_binop_lequal
:
1635 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1637 case ir_binop_gequal
:
1638 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1640 case ir_binop_equal
:
1641 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1643 case ir_binop_nequal
:
1644 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1646 case ir_binop_all_equal
:
1647 /* "==" operator producing a scalar boolean. */
1648 if (ir
->operands
[0]->type
->is_vector() ||
1649 ir
->operands
[1]->type
->is_vector()) {
1650 st_src_reg temp
= get_temp(native_integers
?
1651 glsl_type::uvec4_type
:
1652 glsl_type::vec4_type
);
1654 if (native_integers
) {
1655 st_dst_reg temp_dst
= st_dst_reg(temp
);
1656 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1658 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1660 /* Emit 1-3 AND operations to combine the SEQ results. */
1661 switch (ir
->operands
[0]->type
->vector_elements
) {
1665 temp_dst
.writemask
= WRITEMASK_Y
;
1666 temp1
.swizzle
= SWIZZLE_YYYY
;
1667 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1668 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1671 temp_dst
.writemask
= WRITEMASK_X
;
1672 temp1
.swizzle
= SWIZZLE_XXXX
;
1673 temp2
.swizzle
= SWIZZLE_YYYY
;
1674 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1675 temp_dst
.writemask
= WRITEMASK_Y
;
1676 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1677 temp2
.swizzle
= SWIZZLE_WWWW
;
1678 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1681 temp1
.swizzle
= SWIZZLE_XXXX
;
1682 temp2
.swizzle
= SWIZZLE_YYYY
;
1683 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1685 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1687 /* After the dot-product, the value will be an integer on the
1688 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1690 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1692 /* Negating the result of the dot-product gives values on the range
1693 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1694 * This is achieved using SGE.
1696 st_src_reg sge_src
= result_src
;
1697 sge_src
.negate
= ~sge_src
.negate
;
1698 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1701 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1704 case ir_binop_any_nequal
:
1705 /* "!=" operator producing a scalar boolean. */
1706 if (ir
->operands
[0]->type
->is_vector() ||
1707 ir
->operands
[1]->type
->is_vector()) {
1708 st_src_reg temp
= get_temp(native_integers
?
1709 glsl_type::uvec4_type
:
1710 glsl_type::vec4_type
);
1711 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1713 if (native_integers
) {
1714 st_dst_reg temp_dst
= st_dst_reg(temp
);
1715 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1717 /* Emit 1-3 OR operations to combine the SNE results. */
1718 switch (ir
->operands
[0]->type
->vector_elements
) {
1722 temp_dst
.writemask
= WRITEMASK_Y
;
1723 temp1
.swizzle
= SWIZZLE_YYYY
;
1724 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1725 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1728 temp_dst
.writemask
= WRITEMASK_X
;
1729 temp1
.swizzle
= SWIZZLE_XXXX
;
1730 temp2
.swizzle
= SWIZZLE_YYYY
;
1731 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1732 temp_dst
.writemask
= WRITEMASK_Y
;
1733 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1734 temp2
.swizzle
= SWIZZLE_WWWW
;
1735 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1738 temp1
.swizzle
= SWIZZLE_XXXX
;
1739 temp2
.swizzle
= SWIZZLE_YYYY
;
1740 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1742 /* After the dot-product, the value will be an integer on the
1743 * range [0,4]. Zero stays zero, and positive values become 1.0.
1745 glsl_to_tgsi_instruction
*const dp
=
1746 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1747 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1748 /* The clamping to [0,1] can be done for free in the fragment
1749 * shader with a saturate.
1751 dp
->saturate
= true;
1753 /* Negating the result of the dot-product gives values on the range
1754 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1755 * achieved using SLT.
1757 st_src_reg slt_src
= result_src
;
1758 slt_src
.negate
= ~slt_src
.negate
;
1759 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1763 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1768 assert(ir
->operands
[0]->type
->is_vector());
1770 if (native_integers
) {
1771 int dst_swizzle
= 0, op0_swizzle
, i
;
1772 st_src_reg accum
= op
[0];
1774 op0_swizzle
= op
[0].swizzle
;
1775 accum
.swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 0),
1776 GET_SWZ(op0_swizzle
, 0),
1777 GET_SWZ(op0_swizzle
, 0),
1778 GET_SWZ(op0_swizzle
, 0));
1779 for (i
= 0; i
< 4; i
++) {
1780 if (result_dst
.writemask
& (1 << i
)) {
1781 dst_swizzle
= MAKE_SWIZZLE4(i
, i
, i
, i
);
1786 assert(ir
->operands
[0]->type
->is_boolean());
1788 /* OR all the components together, since they should be either 0 or ~0
1790 switch (ir
->operands
[0]->type
->vector_elements
) {
1792 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 3),
1793 GET_SWZ(op0_swizzle
, 3),
1794 GET_SWZ(op0_swizzle
, 3),
1795 GET_SWZ(op0_swizzle
, 3));
1796 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1797 accum
= st_src_reg(result_dst
);
1798 accum
.swizzle
= dst_swizzle
;
1801 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 2),
1802 GET_SWZ(op0_swizzle
, 2),
1803 GET_SWZ(op0_swizzle
, 2),
1804 GET_SWZ(op0_swizzle
, 2));
1805 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1806 accum
= st_src_reg(result_dst
);
1807 accum
.swizzle
= dst_swizzle
;
1810 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 1),
1811 GET_SWZ(op0_swizzle
, 1),
1812 GET_SWZ(op0_swizzle
, 1),
1813 GET_SWZ(op0_swizzle
, 1));
1814 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1817 assert(!"Unexpected vector size");
1821 /* After the dot-product, the value will be an integer on the
1822 * range [0,4]. Zero stays zero, and positive values become 1.0.
1824 glsl_to_tgsi_instruction
*const dp
=
1825 emit_dp(ir
, result_dst
, op
[0], op
[0],
1826 ir
->operands
[0]->type
->vector_elements
);
1827 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
1828 result_dst
.type
== GLSL_TYPE_FLOAT
) {
1829 /* The clamping to [0,1] can be done for free in the fragment
1830 * shader with a saturate.
1832 dp
->saturate
= true;
1833 } else if (result_dst
.type
== GLSL_TYPE_FLOAT
) {
1834 /* Negating the result of the dot-product gives values on the range
1835 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1836 * is achieved using SLT.
1838 st_src_reg slt_src
= result_src
;
1839 slt_src
.negate
= ~slt_src
.negate
;
1840 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1843 /* Use SNE 0 if integers are being used as boolean values. */
1844 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, result_src
, st_src_reg_for_int(0));
1850 case ir_binop_logic_xor
:
1851 if (native_integers
)
1852 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1854 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1857 case ir_binop_logic_or
: {
1858 if (native_integers
) {
1859 /* If integers are used as booleans, we can use an actual "or"
1862 assert(native_integers
);
1863 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1865 /* After the addition, the value will be an integer on the
1866 * range [0,2]. Zero stays zero, and positive values become 1.0.
1868 glsl_to_tgsi_instruction
*add
=
1869 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1870 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1871 /* The clamping to [0,1] can be done for free in the fragment
1872 * shader with a saturate if floats are being used as boolean values.
1874 add
->saturate
= true;
1876 /* Negating the result of the addition gives values on the range
1877 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1878 * is achieved using SLT.
1880 st_src_reg slt_src
= result_src
;
1881 slt_src
.negate
= ~slt_src
.negate
;
1882 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1888 case ir_binop_logic_and
:
1889 /* If native integers are disabled, the bool args are stored as float 0.0
1890 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1891 * actual AND opcode.
1893 if (native_integers
)
1894 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1896 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1900 assert(ir
->operands
[0]->type
->is_vector());
1901 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1902 emit_dp(ir
, result_dst
, op
[0], op
[1],
1903 ir
->operands
[0]->type
->vector_elements
);
1908 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1910 /* sqrt(x) = x * rsq(x). */
1911 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1912 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1913 /* For incoming channels <= 0, set the result to 0. */
1914 op
[0].negate
= ~op
[0].negate
;
1915 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1916 op
[0], result_src
, st_src_reg_for_float(0.0));
1920 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1923 if (native_integers
) {
1924 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1927 /* fallthrough to next case otherwise */
1929 if (native_integers
) {
1930 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1933 /* fallthrough to next case otherwise */
1936 /* Converting between signed and unsigned integers is a no-op. */
1940 if (native_integers
) {
1941 /* Booleans are stored as integers using ~0 for true and 0 for false.
1942 * GLSL requires that int(bool) return 1 for true and 0 for false.
1943 * This conversion is done with AND, but it could be done with NEG.
1945 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1947 /* Booleans and integers are both stored as floats when native
1948 * integers are disabled.
1954 if (native_integers
)
1955 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1957 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1960 if (native_integers
)
1961 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1963 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1965 case ir_unop_bitcast_f2i
:
1967 result_src
.type
= GLSL_TYPE_INT
;
1969 case ir_unop_bitcast_f2u
:
1971 result_src
.type
= GLSL_TYPE_UINT
;
1973 case ir_unop_bitcast_i2f
:
1974 case ir_unop_bitcast_u2f
:
1976 result_src
.type
= GLSL_TYPE_FLOAT
;
1979 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1982 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1985 if (native_integers
)
1986 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1988 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1991 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1994 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1997 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1999 case ir_unop_round_even
:
2000 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2003 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2007 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2010 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2013 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2016 case ir_unop_bit_not
:
2017 if (native_integers
) {
2018 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2022 if (native_integers
) {
2023 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2026 case ir_binop_lshift
:
2027 if (native_integers
) {
2028 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2031 case ir_binop_rshift
:
2032 if (native_integers
) {
2033 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2036 case ir_binop_bit_and
:
2037 if (native_integers
) {
2038 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2041 case ir_binop_bit_xor
:
2042 if (native_integers
) {
2043 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2046 case ir_binop_bit_or
:
2047 if (native_integers
) {
2048 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2052 assert(!"GLSL 1.30 features unsupported");
2055 case ir_binop_ubo_load
: {
2056 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2057 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2058 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2059 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2060 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2063 cbuf
.type
= ir
->type
->base_type
;
2064 cbuf
.file
= PROGRAM_CONSTANT
;
2066 cbuf
.reladdr
= NULL
;
2069 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2071 if (const_offset_ir
) {
2072 /* Constant index into constant buffer */
2073 cbuf
.reladdr
= NULL
;
2074 cbuf
.index
= const_offset
/ 16;
2077 /* Relative/variable index into constant buffer */
2078 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2079 st_src_reg_for_int(4));
2080 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2081 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2084 if (const_uniform_block
) {
2085 /* Constant constant buffer */
2086 cbuf
.reladdr2
= NULL
;
2087 cbuf
.index2D
= const_block
;
2088 cbuf
.has_index2
= true;
2091 /* Relative/variable constant buffer */
2092 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2094 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2095 cbuf
.has_index2
= true;
2098 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2099 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2100 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2101 const_offset
% 16 / 8,
2102 const_offset
% 16 / 8,
2103 const_offset
% 16 / 8);
2105 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2106 const_offset
% 16 / 4,
2107 const_offset
% 16 / 4,
2108 const_offset
% 16 / 4);
2110 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2111 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2113 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2118 /* note: we have to reorder the three args here */
2119 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2122 if (this->ctx
->Const
.NativeIntegers
)
2123 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2125 op
[0].negate
= ~op
[0].negate
;
2126 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2129 case ir_triop_bitfield_extract
:
2130 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2132 case ir_quadop_bitfield_insert
:
2133 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2135 case ir_unop_bitfield_reverse
:
2136 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2138 case ir_unop_bit_count
:
2139 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2141 case ir_unop_find_msb
:
2142 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2144 case ir_unop_find_lsb
:
2145 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2147 case ir_binop_imul_high
:
2148 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2151 /* In theory, MAD is incorrect here. */
2153 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2155 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2157 case ir_unop_interpolate_at_centroid
:
2158 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2160 case ir_binop_interpolate_at_offset
:
2161 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2163 case ir_binop_interpolate_at_sample
:
2164 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2168 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2171 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2174 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2177 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2180 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2183 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2185 case ir_unop_unpack_double_2x32
:
2186 case ir_unop_pack_double_2x32
:
2187 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2190 case ir_binop_ldexp
:
2191 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2192 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2194 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2198 case ir_unop_pack_snorm_2x16
:
2199 case ir_unop_pack_unorm_2x16
:
2200 case ir_unop_pack_half_2x16
:
2201 case ir_unop_pack_snorm_4x8
:
2202 case ir_unop_pack_unorm_4x8
:
2204 case ir_unop_unpack_snorm_2x16
:
2205 case ir_unop_unpack_unorm_2x16
:
2206 case ir_unop_unpack_half_2x16
:
2207 case ir_unop_unpack_half_2x16_split_x
:
2208 case ir_unop_unpack_half_2x16_split_y
:
2209 case ir_unop_unpack_snorm_4x8
:
2210 case ir_unop_unpack_unorm_4x8
:
2212 case ir_binop_pack_half_2x16_split
:
2215 case ir_quadop_vector
:
2216 case ir_binop_vector_extract
:
2217 case ir_triop_vector_insert
:
2218 case ir_binop_carry
:
2219 case ir_binop_borrow
:
2220 case ir_unop_ssbo_unsized_array_length
:
2221 /* This operation is not supported, or should have already been handled.
2223 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2226 case ir_unop_get_buffer_size
:
2227 assert(!"Not implemented yet");
2231 this->result
= result_src
;
2236 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2242 /* Note that this is only swizzles in expressions, not those on the left
2243 * hand side of an assignment, which do write masking. See ir_assignment
2247 ir
->val
->accept(this);
2249 assert(src
.file
!= PROGRAM_UNDEFINED
);
2250 assert(ir
->type
->vector_elements
> 0);
2252 for (i
= 0; i
< 4; i
++) {
2253 if (i
< ir
->type
->vector_elements
) {
2256 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2259 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2262 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2265 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2269 /* If the type is smaller than a vec4, replicate the last
2272 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2276 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2281 /* Test if the variable is an array. Note that geometry and
2282 * tessellation shader inputs are outputs are always arrays (except
2283 * for patch inputs), so only the array element type is considered.
2286 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2288 const glsl_type
*type
= var
->type
;
2290 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2291 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2296 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2297 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2298 stage
== MESA_SHADER_TESS_CTRL
) &&
2300 if (!var
->type
->is_array())
2301 return false; /* a system value probably */
2303 type
= var
->type
->fields
.array
;
2307 return type
->is_array() || type
->is_matrix();
2311 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2313 variable_storage
*entry
= find_variable_storage(ir
->var
);
2314 ir_variable
*var
= ir
->var
;
2318 switch (var
->data
.mode
) {
2319 case ir_var_uniform
:
2320 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2321 var
->data
.location
);
2322 this->variables
.push_tail(entry
);
2324 case ir_var_shader_in
:
2325 /* The linker assigns locations for varyings and attributes,
2326 * including deprecated builtins (like gl_Color), user-assign
2327 * generic attributes (glBindVertexLocation), and
2328 * user-defined varyings.
2330 assert(var
->data
.location
!= -1);
2332 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2333 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2335 decl
->mesa_index
= var
->data
.location
;
2336 decl
->array_id
= num_input_arrays
+ 1;
2338 decl
->array_size
= type_size(var
->type
->fields
.array
);
2340 decl
->array_size
= type_size(var
->type
);
2343 entry
= new(mem_ctx
) variable_storage(var
,
2349 entry
= new(mem_ctx
) variable_storage(var
,
2351 var
->data
.location
);
2353 this->variables
.push_tail(entry
);
2355 case ir_var_shader_out
:
2356 assert(var
->data
.location
!= -1);
2358 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2359 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2361 decl
->mesa_index
= var
->data
.location
;
2362 decl
->array_id
= num_output_arrays
+ 1;
2364 decl
->array_size
= type_size(var
->type
->fields
.array
);
2366 decl
->array_size
= type_size(var
->type
);
2367 num_output_arrays
++;
2369 entry
= new(mem_ctx
) variable_storage(var
,
2375 entry
= new(mem_ctx
) variable_storage(var
,
2380 this->variables
.push_tail(entry
);
2382 case ir_var_system_value
:
2383 entry
= new(mem_ctx
) variable_storage(var
,
2384 PROGRAM_SYSTEM_VALUE
,
2385 var
->data
.location
);
2388 case ir_var_temporary
:
2389 st_src_reg src
= get_temp(var
->type
);
2391 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2392 this->variables
.push_tail(entry
);
2398 printf("Failed to make storage for %s\n", var
->name
);
2403 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2404 this->result
.array_id
= entry
->array_id
;
2405 if (!native_integers
)
2406 this->result
.type
= GLSL_TYPE_FLOAT
;
2410 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2411 GLbitfield64 usage_mask
,
2412 GLbitfield patch_usage_mask
)
2416 /* Fix array declarations by removing unused array elements at both ends
2417 * of the arrays. For example, mat4[3] where only mat[1] is used.
2419 for (i
= 0; i
< count
; i
++) {
2420 struct array_decl
*decl
= &arrays
[i
];
2422 /* Shrink the beginning. */
2423 for (j
= 0; j
< decl
->array_size
; j
++) {
2424 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2425 if (patch_usage_mask
&
2426 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2430 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2439 /* Shrink the end. */
2440 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2441 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2442 if (patch_usage_mask
&
2443 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2447 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2457 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2461 int element_size
= type_size(ir
->type
);
2464 index
= ir
->array_index
->constant_expression_value();
2466 ir
->array
->accept(this);
2469 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2470 switch (this->prog
->Target
) {
2471 case GL_TESS_CONTROL_PROGRAM_NV
:
2472 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2473 !ir
->variable_referenced()->data
.patch
;
2475 case GL_TESS_EVALUATION_PROGRAM_NV
:
2476 is_2D
= src
.file
== PROGRAM_INPUT
&&
2477 !ir
->variable_referenced()->data
.patch
;
2479 case GL_GEOMETRY_PROGRAM_NV
:
2480 is_2D
= src
.file
== PROGRAM_INPUT
;
2490 src
.index2D
= index
->value
.i
[0];
2491 src
.has_index2
= true;
2493 src
.index
+= index
->value
.i
[0] * element_size
;
2495 /* Variable index array dereference. It eats the "vec4" of the
2496 * base of the array and an index that offsets the TGSI register
2499 ir
->array_index
->accept(this);
2501 st_src_reg index_reg
;
2503 if (element_size
== 1) {
2504 index_reg
= this->result
;
2506 index_reg
= get_temp(native_integers
?
2507 glsl_type::int_type
: glsl_type::float_type
);
2509 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2510 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2513 /* If there was already a relative address register involved, add the
2514 * new and the old together to get the new offset.
2516 if (!is_2D
&& src
.reladdr
!= NULL
) {
2517 st_src_reg accum_reg
= get_temp(native_integers
?
2518 glsl_type::int_type
: glsl_type::float_type
);
2520 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2521 index_reg
, *src
.reladdr
);
2523 index_reg
= accum_reg
;
2527 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2528 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2530 src
.has_index2
= true;
2532 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2533 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2537 /* If the type is smaller than a vec4, replicate the last channel out. */
2538 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2539 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2541 src
.swizzle
= SWIZZLE_NOOP
;
2543 /* Change the register type to the element type of the array. */
2544 src
.type
= ir
->type
->base_type
;
2550 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2553 const glsl_type
*struct_type
= ir
->record
->type
;
2556 ir
->record
->accept(this);
2558 for (i
= 0; i
< struct_type
->length
; i
++) {
2559 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2561 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2564 /* If the type is smaller than a vec4, replicate the last channel out. */
2565 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2566 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2568 this->result
.swizzle
= SWIZZLE_NOOP
;
2570 this->result
.index
+= offset
;
2571 this->result
.type
= ir
->type
->base_type
;
2575 * We want to be careful in assignment setup to hit the actual storage
2576 * instead of potentially using a temporary like we might with the
2577 * ir_dereference handler.
2580 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2582 /* The LHS must be a dereference. If the LHS is a variable indexed array
2583 * access of a vector, it must be separated into a series conditional moves
2584 * before reaching this point (see ir_vec_index_to_cond_assign).
2586 assert(ir
->as_dereference());
2587 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2589 assert(!deref_array
->array
->type
->is_vector());
2592 /* Use the rvalue deref handler for the most part. We'll ignore
2593 * swizzles in it and write swizzles using writemask, though.
2596 return st_dst_reg(v
->result
);
2600 * Process the condition of a conditional assignment
2602 * Examines the condition of a conditional assignment to generate the optimal
2603 * first operand of a \c CMP instruction. If the condition is a relational
2604 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2605 * used as the source for the \c CMP instruction. Otherwise the comparison
2606 * is processed to a boolean result, and the boolean result is used as the
2607 * operand to the CMP instruction.
2610 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2612 ir_rvalue
*src_ir
= ir
;
2614 bool switch_order
= false;
2616 ir_expression
*const expr
= ir
->as_expression();
2618 if (native_integers
) {
2619 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2620 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2621 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2622 type
== GLSL_TYPE_BOOL
) {
2623 if (expr
->operation
== ir_binop_equal
) {
2624 if (expr
->operands
[0]->is_zero()) {
2625 src_ir
= expr
->operands
[1];
2626 switch_order
= true;
2628 else if (expr
->operands
[1]->is_zero()) {
2629 src_ir
= expr
->operands
[0];
2630 switch_order
= true;
2633 else if (expr
->operation
== ir_binop_nequal
) {
2634 if (expr
->operands
[0]->is_zero()) {
2635 src_ir
= expr
->operands
[1];
2637 else if (expr
->operands
[1]->is_zero()) {
2638 src_ir
= expr
->operands
[0];
2644 src_ir
->accept(this);
2645 return switch_order
;
2648 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2649 bool zero_on_left
= false;
2651 if (expr
->operands
[0]->is_zero()) {
2652 src_ir
= expr
->operands
[1];
2653 zero_on_left
= true;
2654 } else if (expr
->operands
[1]->is_zero()) {
2655 src_ir
= expr
->operands
[0];
2656 zero_on_left
= false;
2660 * (a < 0) T F F ( a < 0) T F F
2661 * (0 < a) F F T (-a < 0) F F T
2662 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2663 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2664 * (a > 0) F F T (-a < 0) F F T
2665 * (0 > a) T F F ( a < 0) T F F
2666 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2667 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2669 * Note that exchanging the order of 0 and 'a' in the comparison simply
2670 * means that the value of 'a' should be negated.
2673 switch (expr
->operation
) {
2675 switch_order
= false;
2676 negate
= zero_on_left
;
2679 case ir_binop_greater
:
2680 switch_order
= false;
2681 negate
= !zero_on_left
;
2684 case ir_binop_lequal
:
2685 switch_order
= true;
2686 negate
= !zero_on_left
;
2689 case ir_binop_gequal
:
2690 switch_order
= true;
2691 negate
= zero_on_left
;
2695 /* This isn't the right kind of comparison afterall, so make sure
2696 * the whole condition is visited.
2704 src_ir
->accept(this);
2706 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2707 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2708 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2709 * computing the condition.
2712 this->result
.negate
= ~this->result
.negate
;
2714 return switch_order
;
2718 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2719 st_dst_reg
*l
, st_src_reg
*r
,
2720 st_src_reg
*cond
, bool cond_swap
)
2722 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2723 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2724 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2730 if (type
->is_array()) {
2731 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2732 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2737 if (type
->is_matrix()) {
2738 const struct glsl_type
*vec_type
;
2740 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2741 type
->vector_elements
, 1);
2743 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2744 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2749 assert(type
->is_scalar() || type
->is_vector());
2751 r
->type
= type
->base_type
;
2753 st_src_reg l_src
= st_src_reg(*l
);
2754 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2756 if (native_integers
) {
2757 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2758 cond_swap
? l_src
: *r
,
2759 cond_swap
? *r
: l_src
);
2761 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2762 cond_swap
? l_src
: *r
,
2763 cond_swap
? *r
: l_src
);
2766 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2773 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2778 ir
->rhs
->accept(this);
2781 l
= get_assignment_lhs(ir
->lhs
, this);
2783 /* FINISHME: This should really set to the correct maximal writemask for each
2784 * FINISHME: component written (in the loops below). This case can only
2785 * FINISHME: occur for matrices, arrays, and structures.
2787 if (ir
->write_mask
== 0) {
2788 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2789 l
.writemask
= WRITEMASK_XYZW
;
2790 } else if (ir
->lhs
->type
->is_scalar() &&
2791 !ir
->lhs
->type
->is_double() &&
2792 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2793 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2794 * FINISHME: W component of fragment shader output zero, work correctly.
2796 l
.writemask
= WRITEMASK_XYZW
;
2799 int first_enabled_chan
= 0;
2802 l
.writemask
= ir
->write_mask
;
2804 for (int i
= 0; i
< 4; i
++) {
2805 if (l
.writemask
& (1 << i
)) {
2806 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2811 /* Swizzle a small RHS vector into the channels being written.
2813 * glsl ir treats write_mask as dictating how many channels are
2814 * present on the RHS while TGSI treats write_mask as just
2815 * showing which channels of the vec4 RHS get written.
2817 for (int i
= 0; i
< 4; i
++) {
2818 if (l
.writemask
& (1 << i
))
2819 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2821 swizzles
[i
] = first_enabled_chan
;
2823 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2824 swizzles
[2], swizzles
[3]);
2827 assert(l
.file
!= PROGRAM_UNDEFINED
);
2828 assert(r
.file
!= PROGRAM_UNDEFINED
);
2830 if (ir
->condition
) {
2831 const bool switch_order
= this->process_move_condition(ir
->condition
);
2832 st_src_reg condition
= this->result
;
2834 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2835 } else if (ir
->rhs
->as_expression() &&
2836 this->instructions
.get_tail() &&
2837 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2838 type_size(ir
->lhs
->type
) == 1 &&
2839 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2840 /* To avoid emitting an extra MOV when assigning an expression to a
2841 * variable, emit the last instruction of the expression again, but
2842 * replace the destination register with the target of the assignment.
2843 * Dead code elimination will remove the original instruction.
2845 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2846 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2847 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2848 new_inst
->saturate
= inst
->saturate
;
2849 inst
->dead_mask
= inst
->dst
[0].writemask
;
2851 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2857 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2860 GLdouble stack_vals
[4] = { 0 };
2861 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2862 GLenum gl_type
= GL_NONE
;
2864 static int in_array
= 0;
2865 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2867 /* Unfortunately, 4 floats is all we can get into
2868 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2869 * aggregate constant and move each constant value into it. If we
2870 * get lucky, copy propagation will eliminate the extra moves.
2872 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2873 st_src_reg temp_base
= get_temp(ir
->type
);
2874 st_dst_reg temp
= st_dst_reg(temp_base
);
2876 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2877 int size
= type_size(field_value
->type
);
2881 field_value
->accept(this);
2884 for (i
= 0; i
< (unsigned int)size
; i
++) {
2885 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2891 this->result
= temp_base
;
2895 if (ir
->type
->is_array()) {
2896 st_src_reg temp_base
= get_temp(ir
->type
);
2897 st_dst_reg temp
= st_dst_reg(temp_base
);
2898 int size
= type_size(ir
->type
->fields
.array
);
2903 for (i
= 0; i
< ir
->type
->length
; i
++) {
2904 ir
->array_elements
[i
]->accept(this);
2906 for (int j
= 0; j
< size
; j
++) {
2907 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2913 this->result
= temp_base
;
2918 if (ir
->type
->is_matrix()) {
2919 st_src_reg mat
= get_temp(ir
->type
);
2920 st_dst_reg mat_column
= st_dst_reg(mat
);
2922 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2923 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
2924 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2926 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2927 src
.index
= add_constant(file
,
2929 ir
->type
->vector_elements
,
2932 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2941 switch (ir
->type
->base_type
) {
2942 case GLSL_TYPE_FLOAT
:
2944 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2945 values
[i
].f
= ir
->value
.f
[i
];
2948 case GLSL_TYPE_DOUBLE
:
2949 gl_type
= GL_DOUBLE
;
2950 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2951 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
2952 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
2955 case GLSL_TYPE_UINT
:
2956 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
2957 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2958 if (native_integers
)
2959 values
[i
].u
= ir
->value
.u
[i
];
2961 values
[i
].f
= ir
->value
.u
[i
];
2965 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
2966 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2967 if (native_integers
)
2968 values
[i
].i
= ir
->value
.i
[i
];
2970 values
[i
].f
= ir
->value
.i
[i
];
2973 case GLSL_TYPE_BOOL
:
2974 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
2975 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2976 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
2980 assert(!"Non-float/uint/int/bool constant");
2983 this->result
= st_src_reg(file
, -1, ir
->type
);
2984 this->result
.index
= add_constant(file
,
2986 ir
->type
->vector_elements
,
2988 &this->result
.swizzle
);
2992 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
2994 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
2995 if (entry
->sig
== sig
)
2999 entry
= ralloc(mem_ctx
, function_entry
);
3001 entry
->sig_id
= this->next_signature_id
++;
3002 entry
->bgn_inst
= NULL
;
3004 /* Allocate storage for all the parameters. */
3005 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3006 variable_storage
*storage
;
3008 storage
= find_variable_storage(param
);
3011 st_src_reg src
= get_temp(param
->type
);
3013 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3014 this->variables
.push_tail(storage
);
3017 if (!sig
->return_type
->is_void()) {
3018 entry
->return_reg
= get_temp(sig
->return_type
);
3020 entry
->return_reg
= undef_src
;
3023 this->function_signatures
.push_tail(entry
);
3028 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3030 glsl_to_tgsi_instruction
*call_inst
;
3031 ir_function_signature
*sig
= ir
->callee
;
3032 function_entry
*entry
= get_function_signature(sig
);
3035 /* Process in parameters. */
3036 foreach_two_lists(formal_node
, &sig
->parameters
,
3037 actual_node
, &ir
->actual_parameters
) {
3038 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3039 ir_variable
*param
= (ir_variable
*) formal_node
;
3041 if (param
->data
.mode
== ir_var_function_in
||
3042 param
->data
.mode
== ir_var_function_inout
) {
3043 variable_storage
*storage
= find_variable_storage(param
);
3046 param_rval
->accept(this);
3047 st_src_reg r
= this->result
;
3050 l
.file
= storage
->file
;
3051 l
.index
= storage
->index
;
3053 l
.writemask
= WRITEMASK_XYZW
;
3054 l
.cond_mask
= COND_TR
;
3056 for (i
= 0; i
< type_size(param
->type
); i
++) {
3057 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3064 /* Emit call instruction */
3065 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3066 call_inst
->function
= entry
;
3068 /* Process out parameters. */
3069 foreach_two_lists(formal_node
, &sig
->parameters
,
3070 actual_node
, &ir
->actual_parameters
) {
3071 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3072 ir_variable
*param
= (ir_variable
*) formal_node
;
3074 if (param
->data
.mode
== ir_var_function_out
||
3075 param
->data
.mode
== ir_var_function_inout
) {
3076 variable_storage
*storage
= find_variable_storage(param
);
3080 r
.file
= storage
->file
;
3081 r
.index
= storage
->index
;
3083 r
.swizzle
= SWIZZLE_NOOP
;
3086 param_rval
->accept(this);
3087 st_dst_reg l
= st_dst_reg(this->result
);
3089 for (i
= 0; i
< type_size(param
->type
); i
++) {
3090 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3097 /* Process return value. */
3098 this->result
= entry
->return_reg
;
3102 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3104 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3105 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3106 st_src_reg levels_src
;
3107 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3108 glsl_to_tgsi_instruction
*inst
= NULL
;
3109 unsigned opcode
= TGSI_OPCODE_NOP
;
3110 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3111 ir_rvalue
*sampler_index
=
3112 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
3113 bool is_cube_array
= false;
3116 /* if we are a cube array sampler */
3117 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3118 sampler_type
->sampler_array
)) {
3119 is_cube_array
= true;
3122 if (ir
->coordinate
) {
3123 ir
->coordinate
->accept(this);
3125 /* Put our coords in a temp. We'll need to modify them for shadow,
3126 * projection, or LOD, so the only case we'd use it as is is if
3127 * we're doing plain old texturing. The optimization passes on
3128 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3130 coord
= get_temp(glsl_type::vec4_type
);
3131 coord_dst
= st_dst_reg(coord
);
3132 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3133 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3136 if (ir
->projector
) {
3137 ir
->projector
->accept(this);
3138 projector
= this->result
;
3141 /* Storage for our result. Ideally for an assignment we'd be using
3142 * the actual storage for the result here, instead.
3144 result_src
= get_temp(ir
->type
);
3145 result_dst
= st_dst_reg(result_src
);
3149 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3151 ir
->offset
->accept(this);
3152 offset
[0] = this->result
;
3156 if (is_cube_array
||
3157 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3158 opcode
= TGSI_OPCODE_TXB2
;
3161 opcode
= TGSI_OPCODE_TXB
;
3163 ir
->lod_info
.bias
->accept(this);
3164 lod_info
= this->result
;
3166 ir
->offset
->accept(this);
3167 offset
[0] = this->result
;
3171 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3172 ir
->lod_info
.lod
->accept(this);
3173 lod_info
= this->result
;
3175 ir
->offset
->accept(this);
3176 offset
[0] = this->result
;
3180 opcode
= TGSI_OPCODE_TXD
;
3181 ir
->lod_info
.grad
.dPdx
->accept(this);
3183 ir
->lod_info
.grad
.dPdy
->accept(this);
3186 ir
->offset
->accept(this);
3187 offset
[0] = this->result
;
3191 opcode
= TGSI_OPCODE_TXQ
;
3192 ir
->lod_info
.lod
->accept(this);
3193 lod_info
= this->result
;
3195 case ir_query_levels
:
3196 opcode
= TGSI_OPCODE_TXQ
;
3197 lod_info
= undef_src
;
3198 levels_src
= get_temp(ir
->type
);
3201 opcode
= TGSI_OPCODE_TXF
;
3202 ir
->lod_info
.lod
->accept(this);
3203 lod_info
= this->result
;
3205 ir
->offset
->accept(this);
3206 offset
[0] = this->result
;
3210 opcode
= TGSI_OPCODE_TXF
;
3211 ir
->lod_info
.sample_index
->accept(this);
3212 sample_index
= this->result
;
3215 opcode
= TGSI_OPCODE_TG4
;
3216 ir
->lod_info
.component
->accept(this);
3217 component
= this->result
;
3219 ir
->offset
->accept(this);
3220 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3221 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3222 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3223 offset
[i
] = this->result
;
3224 offset
[i
].index
+= i
* type_size(elt_type
);
3225 offset
[i
].type
= elt_type
->base_type
;
3226 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3229 offset
[0] = this->result
;
3234 opcode
= TGSI_OPCODE_LODQ
;
3236 case ir_texture_samples
:
3237 opcode
= TGSI_OPCODE_TXQS
;
3241 if (ir
->projector
) {
3242 if (opcode
== TGSI_OPCODE_TEX
) {
3243 /* Slot the projector in as the last component of the coord. */
3244 coord_dst
.writemask
= WRITEMASK_W
;
3245 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3246 coord_dst
.writemask
= WRITEMASK_XYZW
;
3247 opcode
= TGSI_OPCODE_TXP
;
3249 st_src_reg coord_w
= coord
;
3250 coord_w
.swizzle
= SWIZZLE_WWWW
;
3252 /* For the other TEX opcodes there's no projective version
3253 * since the last slot is taken up by LOD info. Do the
3254 * projective divide now.
3256 coord_dst
.writemask
= WRITEMASK_W
;
3257 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3259 /* In the case where we have to project the coordinates "by hand,"
3260 * the shadow comparator value must also be projected.
3262 st_src_reg tmp_src
= coord
;
3263 if (ir
->shadow_comparitor
) {
3264 /* Slot the shadow value in as the second to last component of the
3267 ir
->shadow_comparitor
->accept(this);
3269 tmp_src
= get_temp(glsl_type::vec4_type
);
3270 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3272 /* Projective division not allowed for array samplers. */
3273 assert(!sampler_type
->sampler_array
);
3275 tmp_dst
.writemask
= WRITEMASK_Z
;
3276 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3278 tmp_dst
.writemask
= WRITEMASK_XY
;
3279 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
3282 coord_dst
.writemask
= WRITEMASK_XYZ
;
3283 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
3285 coord_dst
.writemask
= WRITEMASK_XYZW
;
3286 coord
.swizzle
= SWIZZLE_XYZW
;
3290 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
3291 * comparator was put in the correct place (and projected) by the code,
3292 * above, that handles by-hand projection.
3294 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
3295 /* Slot the shadow value in as the second to last component of the
3298 ir
->shadow_comparitor
->accept(this);
3300 if (is_cube_array
) {
3301 cube_sc
= get_temp(glsl_type::float_type
);
3302 cube_sc_dst
= st_dst_reg(cube_sc
);
3303 cube_sc_dst
.writemask
= WRITEMASK_X
;
3304 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
3305 cube_sc_dst
.writemask
= WRITEMASK_X
;
3308 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
3309 sampler_type
->sampler_array
) ||
3310 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3311 coord_dst
.writemask
= WRITEMASK_W
;
3313 coord_dst
.writemask
= WRITEMASK_Z
;
3315 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3316 coord_dst
.writemask
= WRITEMASK_XYZW
;
3320 if (ir
->op
== ir_txf_ms
) {
3321 coord_dst
.writemask
= WRITEMASK_W
;
3322 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
3323 coord_dst
.writemask
= WRITEMASK_XYZW
;
3324 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
3325 opcode
== TGSI_OPCODE_TXF
) {
3326 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
3327 coord_dst
.writemask
= WRITEMASK_W
;
3328 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
3329 coord_dst
.writemask
= WRITEMASK_XYZW
;
3332 if (sampler_index
) {
3333 sampler_index
->accept(this);
3334 emit_arl(ir
, sampler_reladdr
, this->result
);
3337 if (opcode
== TGSI_OPCODE_TXD
)
3338 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
3339 else if (opcode
== TGSI_OPCODE_TXQ
) {
3340 if (ir
->op
== ir_query_levels
) {
3341 /* the level is stored in W */
3342 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
3343 result_dst
.writemask
= WRITEMASK_X
;
3344 levels_src
.swizzle
= SWIZZLE_WWWW
;
3345 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
3347 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
3348 } else if (opcode
== TGSI_OPCODE_TXQS
) {
3349 inst
= emit_asm(ir
, opcode
, result_dst
);
3350 } else if (opcode
== TGSI_OPCODE_TXF
) {
3351 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3352 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
3353 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
3354 } else if (opcode
== TGSI_OPCODE_TEX2
) {
3355 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3356 } else if (opcode
== TGSI_OPCODE_TG4
) {
3357 if (is_cube_array
&& ir
->shadow_comparitor
) {
3358 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3360 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
3363 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3365 if (ir
->shadow_comparitor
)
3366 inst
->tex_shadow
= GL_TRUE
;
3368 inst
->sampler
.index
= _mesa_get_sampler_uniform_value(ir
->sampler
,
3369 this->shader_program
,
3371 if (sampler_index
) {
3372 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3373 memcpy(inst
->sampler
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3374 inst
->sampler_array_size
=
3375 ir
->sampler
->as_dereference_array()->array
->type
->array_size();
3377 inst
->sampler_array_size
= 1;
3381 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
3382 inst
->tex_offsets
[i
] = offset
[i
];
3383 inst
->tex_offset_num_offset
= i
;
3386 switch (sampler_type
->sampler_dimensionality
) {
3387 case GLSL_SAMPLER_DIM_1D
:
3388 inst
->tex_target
= (sampler_type
->sampler_array
)
3389 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3391 case GLSL_SAMPLER_DIM_2D
:
3392 inst
->tex_target
= (sampler_type
->sampler_array
)
3393 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3395 case GLSL_SAMPLER_DIM_3D
:
3396 inst
->tex_target
= TEXTURE_3D_INDEX
;
3398 case GLSL_SAMPLER_DIM_CUBE
:
3399 inst
->tex_target
= (sampler_type
->sampler_array
)
3400 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3402 case GLSL_SAMPLER_DIM_RECT
:
3403 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3405 case GLSL_SAMPLER_DIM_BUF
:
3406 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3408 case GLSL_SAMPLER_DIM_EXTERNAL
:
3409 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3411 case GLSL_SAMPLER_DIM_MS
:
3412 inst
->tex_target
= (sampler_type
->sampler_array
)
3413 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3416 assert(!"Should not get here.");
3419 inst
->tex_type
= ir
->type
->base_type
;
3421 this->result
= result_src
;
3425 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
3427 if (ir
->get_value()) {
3431 assert(current_function
);
3433 ir
->get_value()->accept(this);
3434 st_src_reg r
= this->result
;
3436 l
= st_dst_reg(current_function
->return_reg
);
3438 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
3439 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3445 emit_asm(ir
, TGSI_OPCODE_RET
);
3449 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
3451 if (ir
->condition
) {
3452 ir
->condition
->accept(this);
3453 st_src_reg condition
= this->result
;
3455 /* Convert the bool condition to a float so we can negate. */
3456 if (native_integers
) {
3457 st_src_reg temp
= get_temp(ir
->condition
->type
);
3458 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
3459 condition
, st_src_reg_for_float(1.0));
3463 condition
.negate
= ~condition
.negate
;
3464 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
3466 /* unconditional kil */
3467 emit_asm(ir
, TGSI_OPCODE_KILL
);
3472 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
3475 glsl_to_tgsi_instruction
*if_inst
;
3477 ir
->condition
->accept(this);
3478 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3480 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
3482 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
3484 this->instructions
.push_tail(if_inst
);
3486 visit_exec_list(&ir
->then_instructions
, this);
3488 if (!ir
->else_instructions
.is_empty()) {
3489 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
3490 visit_exec_list(&ir
->else_instructions
, this);
3493 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
3498 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
3500 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3502 ir
->stream
->accept(this);
3503 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
3507 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
3509 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3511 ir
->stream
->accept(this);
3512 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
3516 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
3518 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
3519 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
3521 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
3524 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
3526 result
.file
= PROGRAM_UNDEFINED
;
3531 num_input_arrays
= 0;
3532 num_output_arrays
= 0;
3533 next_signature_id
= 1;
3535 current_function
= NULL
;
3536 num_address_regs
= 0;
3538 indirect_addr_consts
= false;
3539 wpos_transform_const
= -1;
3541 native_integers
= false;
3542 mem_ctx
= ralloc_context(NULL
);
3545 shader_program
= NULL
;
3552 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
3555 ralloc_free(mem_ctx
);
3558 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
3565 * Count resources used by the given gpu program (number of texture
3569 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
3571 v
->samplers_used
= 0;
3573 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
3574 if (inst
->info
->is_tex
) {
3575 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
3576 unsigned idx
= inst
->sampler
.index
+ i
;
3577 v
->samplers_used
|= 1 << idx
;
3579 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
3580 v
->sampler_types
[idx
] = inst
->tex_type
;
3581 v
->sampler_targets
[idx
] =
3582 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
3584 if (inst
->tex_shadow
) {
3585 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
3590 prog
->SamplersUsed
= v
->samplers_used
;
3592 if (v
->shader_program
!= NULL
)
3593 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
3597 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
3598 * are read from the given src in this instruction
3601 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
3603 int read_mask
= 0, comp
;
3605 /* Now, given the src swizzle and the written channels, find which
3606 * components are actually read
3608 for (comp
= 0; comp
< 4; ++comp
) {
3609 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
3611 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
3612 read_mask
|= 1 << coord
;
3619 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
3620 * instruction is the first instruction to write to register T0. There are
3621 * several lowering passes done in GLSL IR (e.g. branches and
3622 * relative addressing) that create a large number of conditional assignments
3623 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
3625 * Here is why this conversion is safe:
3626 * CMP T0, T1 T2 T0 can be expanded to:
3632 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
3633 * as the original program. If (T1 < 0.0) evaluates to false, executing
3634 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
3635 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
3636 * because any instruction that was going to read from T0 after this was going
3637 * to read a garbage value anyway.
3640 glsl_to_tgsi_visitor::simplify_cmp(void)
3642 int tempWritesSize
= 0;
3643 unsigned *tempWrites
= NULL
;
3644 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
3646 memset(outputWrites
, 0, sizeof(outputWrites
));
3648 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3649 unsigned prevWriteMask
= 0;
3651 /* Give up if we encounter relative addressing or flow control. */
3652 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
3653 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
3654 tgsi_get_opcode_info(inst
->op
)->is_branch
||
3655 inst
->op
== TGSI_OPCODE_BGNSUB
||
3656 inst
->op
== TGSI_OPCODE_CONT
||
3657 inst
->op
== TGSI_OPCODE_END
||
3658 inst
->op
== TGSI_OPCODE_ENDSUB
||
3659 inst
->op
== TGSI_OPCODE_RET
) {
3663 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
3664 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
3665 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
3666 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3667 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
3668 if (inst
->dst
[0].index
>= tempWritesSize
) {
3669 const int inc
= 4096;
3671 tempWrites
= (unsigned*)
3673 (tempWritesSize
+ inc
) * sizeof(unsigned));
3677 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
3678 tempWritesSize
+= inc
;
3681 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
3682 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3686 /* For a CMP to be considered a conditional write, the destination
3687 * register and source register two must be the same. */
3688 if (inst
->op
== TGSI_OPCODE_CMP
3689 && !(inst
->dst
[0].writemask
& prevWriteMask
)
3690 && inst
->src
[2].file
== inst
->dst
[0].file
3691 && inst
->src
[2].index
== inst
->dst
[0].index
3692 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
3694 inst
->op
= TGSI_OPCODE_MOV
;
3695 inst
->src
[0] = inst
->src
[1];
3702 /* Replaces all references to a temporary register index with another index. */
3704 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
3706 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3709 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3710 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3711 for (k
= 0; k
< num_renames
; k
++)
3712 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
3713 inst
->src
[j
].index
= renames
[k
].new_reg
;
3716 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3717 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3718 for (k
= 0; k
< num_renames
; k
++)
3719 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
3720 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
3723 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3724 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3725 for (k
= 0; k
< num_renames
; k
++)
3726 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
3727 inst
->dst
[j
].index
= renames
[k
].new_reg
;
3733 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
3735 int depth
= 0; /* loop depth */
3736 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3739 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3740 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3741 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
3742 if (first_reads
[inst
->src
[j
].index
] == -1)
3743 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3746 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3747 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
3748 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
3749 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3752 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3755 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3765 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
3767 int depth
= 0; /* loop depth */
3768 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3771 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3772 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3773 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3774 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
3776 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3777 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3778 if (first_writes
[inst
->dst
[j
].index
] == -1)
3779 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3781 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3782 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3783 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
3785 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3788 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3791 for (k
= 0; k
< this->next_temp
; k
++) {
3792 if (last_reads
[k
] == -2) {
3804 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
3806 int depth
= 0; /* loop depth */
3810 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3811 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3812 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3813 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
3816 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3818 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3820 for (k
= 0; k
< this->next_temp
; k
++) {
3821 if (last_writes
[k
] == -2) {
3832 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
3833 * channels for copy propagation and updates following instructions to
3834 * use the original versions.
3836 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3837 * will occur. As an example, a TXP production before this pass:
3839 * 0: MOV TEMP[1], INPUT[4].xyyy;
3840 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3841 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
3845 * 0: MOV TEMP[1], INPUT[4].xyyy;
3846 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3847 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3849 * which allows for dead code elimination on TEMP[1]'s writes.
3852 glsl_to_tgsi_visitor::copy_propagate(void)
3854 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
3855 glsl_to_tgsi_instruction
*,
3856 this->next_temp
* 4);
3857 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3860 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3861 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3862 || inst
->dst
[0].index
< this->next_temp
);
3864 /* First, do any copy propagation possible into the src regs. */
3865 for (int r
= 0; r
< 3; r
++) {
3866 glsl_to_tgsi_instruction
*first
= NULL
;
3868 int acp_base
= inst
->src
[r
].index
* 4;
3870 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
3871 inst
->src
[r
].reladdr
||
3872 inst
->src
[r
].reladdr2
)
3875 /* See if we can find entries in the ACP consisting of MOVs
3876 * from the same src register for all the swizzled channels
3877 * of this src register reference.
3879 for (int i
= 0; i
< 4; i
++) {
3880 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3881 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
3888 assert(acp_level
[acp_base
+ src_chan
] <= level
);
3893 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
3894 first
->src
[0].index
!= copy_chan
->src
[0].index
||
3895 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
3896 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
3904 /* We've now validated that we can copy-propagate to
3905 * replace this src register reference. Do it.
3907 inst
->src
[r
].file
= first
->src
[0].file
;
3908 inst
->src
[r
].index
= first
->src
[0].index
;
3909 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
3910 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
3911 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
3912 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
3915 for (int i
= 0; i
< 4; i
++) {
3916 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3917 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
3918 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
3920 inst
->src
[r
].swizzle
= swizzle
;
3925 case TGSI_OPCODE_BGNLOOP
:
3926 case TGSI_OPCODE_ENDLOOP
:
3927 /* End of a basic block, clear the ACP entirely. */
3928 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3931 case TGSI_OPCODE_IF
:
3932 case TGSI_OPCODE_UIF
:
3936 case TGSI_OPCODE_ENDIF
:
3937 case TGSI_OPCODE_ELSE
:
3938 /* Clear all channels written inside the block from the ACP, but
3939 * leaving those that were not touched.
3941 for (int r
= 0; r
< this->next_temp
; r
++) {
3942 for (int c
= 0; c
< 4; c
++) {
3943 if (!acp
[4 * r
+ c
])
3946 if (acp_level
[4 * r
+ c
] >= level
)
3947 acp
[4 * r
+ c
] = NULL
;
3950 if (inst
->op
== TGSI_OPCODE_ENDIF
)
3955 /* Continuing the block, clear any written channels from
3958 for (int d
= 0; d
< 2; d
++) {
3959 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
3960 /* Any temporary might be written, so no copy propagation
3961 * across this instruction.
3963 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3964 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
3965 inst
->dst
[d
].reladdr
) {
3966 /* Any output might be written, so no copy propagation
3967 * from outputs across this instruction.
3969 for (int r
= 0; r
< this->next_temp
; r
++) {
3970 for (int c
= 0; c
< 4; c
++) {
3971 if (!acp
[4 * r
+ c
])
3974 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
3975 acp
[4 * r
+ c
] = NULL
;
3978 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
3979 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
3980 /* Clear where it's used as dst. */
3981 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
3982 for (int c
= 0; c
< 4; c
++) {
3983 if (inst
->dst
[d
].writemask
& (1 << c
))
3984 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
3988 /* Clear where it's used as src. */
3989 for (int r
= 0; r
< this->next_temp
; r
++) {
3990 for (int c
= 0; c
< 4; c
++) {
3991 if (!acp
[4 * r
+ c
])
3994 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
3996 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
3997 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
3998 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
3999 acp
[4 * r
+ c
] = NULL
;
4008 /* If this is a copy, add it to the ACP. */
4009 if (inst
->op
== TGSI_OPCODE_MOV
&&
4010 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4011 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4012 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4013 !inst
->dst
[0].reladdr
&&
4014 !inst
->dst
[0].reladdr2
&&
4016 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4017 !inst
->src
[0].reladdr
&&
4018 !inst
->src
[0].reladdr2
&&
4019 !inst
->src
[0].negate
) {
4020 for (int i
= 0; i
< 4; i
++) {
4021 if (inst
->dst
[0].writemask
& (1 << i
)) {
4022 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4023 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4029 ralloc_free(acp_level
);
4034 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4037 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4038 * will occur. As an example, a TXP production after copy propagation but
4041 * 0: MOV TEMP[1], INPUT[4].xyyy;
4042 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4043 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4045 * and after this pass:
4047 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4050 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4052 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4053 glsl_to_tgsi_instruction
*,
4054 this->next_temp
* 4);
4055 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4059 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4060 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4061 || inst
->dst
[0].index
< this->next_temp
);
4064 case TGSI_OPCODE_BGNLOOP
:
4065 case TGSI_OPCODE_ENDLOOP
:
4066 case TGSI_OPCODE_CONT
:
4067 case TGSI_OPCODE_BRK
:
4068 /* End of a basic block, clear the write array entirely.
4070 * This keeps us from killing dead code when the writes are
4071 * on either side of a loop, even when the register isn't touched
4072 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4073 * dead code of this type, so it shouldn't make a difference as long as
4074 * the dead code elimination pass in the GLSL compiler does its job.
4076 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4079 case TGSI_OPCODE_ENDIF
:
4080 case TGSI_OPCODE_ELSE
:
4081 /* Promote the recorded level of all channels written inside the
4082 * preceding if or else block to the level above the if/else block.
4084 for (int r
= 0; r
< this->next_temp
; r
++) {
4085 for (int c
= 0; c
< 4; c
++) {
4086 if (!writes
[4 * r
+ c
])
4089 if (write_level
[4 * r
+ c
] == level
)
4090 write_level
[4 * r
+ c
] = level
-1;
4093 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4097 case TGSI_OPCODE_IF
:
4098 case TGSI_OPCODE_UIF
:
4100 /* fallthrough to default case to mark the condition as read */
4102 /* Continuing the block, clear any channels from the write array that
4103 * are read by this instruction.
4105 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4106 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4107 /* Any temporary might be read, so no dead code elimination
4108 * across this instruction.
4110 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4111 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4112 /* Clear where it's used as src. */
4113 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4114 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4115 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4116 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4118 for (int c
= 0; c
< 4; c
++) {
4119 if (src_chans
& (1 << c
))
4120 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4124 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4125 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4126 /* Any temporary might be read, so no dead code elimination
4127 * across this instruction.
4129 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4130 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4131 /* Clear where it's used as src. */
4132 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4133 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4134 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4135 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4137 for (int c
= 0; c
< 4; c
++) {
4138 if (src_chans
& (1 << c
))
4139 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4146 /* If this instruction writes to a temporary, add it to the write array.
4147 * If there is already an instruction in the write array for one or more
4148 * of the channels, flag that channel write as dead.
4150 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4151 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4152 !inst
->dst
[i
].reladdr
) {
4153 for (int c
= 0; c
< 4; c
++) {
4154 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4155 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4156 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4159 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4161 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4162 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4169 /* Anything still in the write array at this point is dead code. */
4170 for (int r
= 0; r
< this->next_temp
; r
++) {
4171 for (int c
= 0; c
< 4; c
++) {
4172 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4174 inst
->dead_mask
|= (1 << c
);
4178 /* Now actually remove the instructions that are completely dead and update
4179 * the writemask of other instructions with dead channels.
4181 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4182 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4184 else if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4189 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4190 if (inst
->dead_mask
== WRITEMASK_XY
||
4191 inst
->dead_mask
== WRITEMASK_ZW
)
4192 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4194 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4198 ralloc_free(write_level
);
4199 ralloc_free(writes
);
4204 /* merge DFRACEXP instructions into one. */
4206 glsl_to_tgsi_visitor::merge_two_dsts(void)
4208 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4209 glsl_to_tgsi_instruction
*inst2
;
4211 if (num_inst_dst_regs(inst
) != 2)
4214 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4215 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4218 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4221 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4222 inst
->src
[0].index
== inst2
->src
[0].index
&&
4223 inst
->src
[0].type
== inst2
->src
[0].type
&&
4224 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4226 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4232 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4234 inst
->dst
[0] = inst2
->dst
[0];
4235 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4236 inst
->dst
[1] = inst2
->dst
[1];
4247 /* Merges temporary registers together where possible to reduce the number of
4248 * registers needed to run a program.
4250 * Produces optimal code only after copy propagation and dead code elimination
4253 glsl_to_tgsi_visitor::merge_registers(void)
4255 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4256 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4257 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4259 int num_renames
= 0;
4261 /* Read the indices of the last read and first write to each temp register
4262 * into an array so that we don't have to traverse the instruction list as
4264 for (i
= 0; i
< this->next_temp
; i
++) {
4266 first_writes
[i
] = -1;
4268 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
4270 /* Start looking for registers with non-overlapping usages that can be
4271 * merged together. */
4272 for (i
= 0; i
< this->next_temp
; i
++) {
4273 /* Don't touch unused registers. */
4274 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
4276 for (j
= 0; j
< this->next_temp
; j
++) {
4277 /* Don't touch unused registers. */
4278 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
4280 /* We can merge the two registers if the first write to j is after or
4281 * in the same instruction as the last read from i. Note that the
4282 * register at index i will always be used earlier or at the same time
4283 * as the register at index j. */
4284 if (first_writes
[i
] <= first_writes
[j
] &&
4285 last_reads
[i
] <= first_writes
[j
]) {
4286 renames
[num_renames
].old_reg
= j
;
4287 renames
[num_renames
].new_reg
= i
;
4290 /* Update the first_writes and last_reads arrays with the new
4291 * values for the merged register index, and mark the newly unused
4292 * register index as such. */
4293 last_reads
[i
] = last_reads
[j
];
4294 first_writes
[j
] = -1;
4300 rename_temp_registers(num_renames
, renames
);
4301 ralloc_free(renames
);
4302 ralloc_free(last_reads
);
4303 ralloc_free(first_writes
);
4306 /* Reassign indices to temporary registers by reusing unused indices created
4307 * by optimization passes. */
4309 glsl_to_tgsi_visitor::renumber_registers(void)
4313 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4314 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4315 int num_renames
= 0;
4316 for (i
= 0; i
< this->next_temp
; i
++) {
4317 first_reads
[i
] = -1;
4319 get_first_temp_read(first_reads
);
4321 for (i
= 0; i
< this->next_temp
; i
++) {
4322 if (first_reads
[i
] < 0) continue;
4323 if (i
!= new_index
) {
4324 renames
[num_renames
].old_reg
= i
;
4325 renames
[num_renames
].new_reg
= new_index
;
4331 rename_temp_registers(num_renames
, renames
);
4332 this->next_temp
= new_index
;
4333 ralloc_free(renames
);
4334 ralloc_free(first_reads
);
4338 * Returns a fragment program which implements the current pixel transfer ops.
4339 * Based on get_pixel_transfer_program in st_atom_pixeltransfer.c.
4342 get_pixel_transfer_visitor(struct st_fragment_program
*fp
,
4343 glsl_to_tgsi_visitor
*original
,
4344 int scale_and_bias
, int pixel_maps
)
4346 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4347 struct st_context
*st
= st_context(original
->ctx
);
4348 struct gl_program
*prog
= &fp
->Base
.Base
;
4349 struct gl_program_parameter_list
*params
= _mesa_new_parameter_list();
4350 st_src_reg coord
, src0
;
4352 glsl_to_tgsi_instruction
*inst
;
4354 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4355 v
->ctx
= original
->ctx
;
4357 v
->shader_program
= NULL
;
4359 v
->glsl_version
= original
->glsl_version
;
4360 v
->native_integers
= original
->native_integers
;
4361 v
->options
= original
->options
;
4362 v
->next_temp
= original
->next_temp
;
4363 v
->num_address_regs
= original
->num_address_regs
;
4364 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4365 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4366 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4367 v
->num_immediates
= original
->num_immediates
;
4370 * Get initial pixel color from the texture.
4371 * TEX colorTemp, fragment.texcoord[0], texture[0], 2D;
4373 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4374 src0
= v
->get_temp(glsl_type::vec4_type
);
4375 dst0
= st_dst_reg(src0
);
4376 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4377 inst
->sampler_array_size
= 1;
4378 inst
->tex_target
= TEXTURE_2D_INDEX
;
4380 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4381 prog
->SamplersUsed
|= (1 << 0); /* mark sampler 0 as used */
4382 v
->samplers_used
|= (1 << 0);
4384 if (scale_and_bias
) {
4385 static const gl_state_index scale_state
[STATE_LENGTH
] =
4386 { STATE_INTERNAL
, STATE_PT_SCALE
,
4387 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4388 static const gl_state_index bias_state
[STATE_LENGTH
] =
4389 { STATE_INTERNAL
, STATE_PT_BIAS
,
4390 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4391 GLint scale_p
, bias_p
;
4392 st_src_reg scale
, bias
;
4394 scale_p
= _mesa_add_state_reference(params
, scale_state
);
4395 bias_p
= _mesa_add_state_reference(params
, bias_state
);
4397 /* MAD colorTemp, colorTemp, scale, bias; */
4398 scale
= st_src_reg(PROGRAM_STATE_VAR
, scale_p
, GLSL_TYPE_FLOAT
);
4399 bias
= st_src_reg(PROGRAM_STATE_VAR
, bias_p
, GLSL_TYPE_FLOAT
);
4400 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MAD
, dst0
, src0
, scale
, bias
);
4404 st_src_reg temp
= v
->get_temp(glsl_type::vec4_type
);
4405 st_dst_reg temp_dst
= st_dst_reg(temp
);
4407 assert(st
->pixel_xfer
.pixelmap_texture
);
4410 /* With a little effort, we can do four pixel map look-ups with
4411 * two TEX instructions:
4414 /* TEX temp.rg, colorTemp.rgba, texture[1], 2D; */
4415 temp_dst
.writemask
= WRITEMASK_XY
; /* write R,G */
4416 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4417 inst
->sampler
.index
= 1;
4418 inst
->sampler_array_size
= 1;
4419 inst
->tex_target
= TEXTURE_2D_INDEX
;
4421 /* TEX temp.ba, colorTemp.baba, texture[1], 2D; */
4422 src0
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
4423 temp_dst
.writemask
= WRITEMASK_ZW
; /* write B,A */
4424 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4425 inst
->sampler
.index
= 1;
4426 inst
->sampler_array_size
= 1;
4427 inst
->tex_target
= TEXTURE_2D_INDEX
;
4429 prog
->SamplersUsed
|= (1 << 1); /* mark sampler 1 as used */
4430 v
->samplers_used
|= (1 << 1);
4432 /* MOV colorTemp, temp; */
4433 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MOV
, dst0
, temp
);
4436 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4438 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4439 glsl_to_tgsi_instruction
*newinst
;
4440 st_src_reg src_regs
[4];
4442 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4443 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4445 for (int i
= 0; i
< 4; i
++) {
4446 src_regs
[i
] = inst
->src
[i
];
4447 if (src_regs
[i
].file
== PROGRAM_INPUT
&&
4448 src_regs
[i
].index
== VARYING_SLOT_COL0
) {
4449 src_regs
[i
].file
= PROGRAM_TEMPORARY
;
4450 src_regs
[i
].index
= src0
.index
;
4452 else if (src_regs
[i
].file
== PROGRAM_INPUT
)
4453 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4456 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2], src_regs
[3]);
4457 newinst
->tex_target
= inst
->tex_target
;
4458 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4461 /* Make modifications to fragment program info. */
4462 prog
->Parameters
= _mesa_combine_parameter_lists(params
,
4463 original
->prog
->Parameters
);
4464 _mesa_free_parameter_list(params
);
4465 count_resources(v
, prog
);
4466 fp
->glsl_to_tgsi
= v
;
4470 * Make fragment program for glBitmap:
4471 * Sample the texture and kill the fragment if the bit is 0.
4472 * This program will be combined with the user's fragment program.
4474 * Based on make_bitmap_fragment_program in st_cb_bitmap.c.
4477 get_bitmap_visitor(struct st_fragment_program
*fp
,
4478 glsl_to_tgsi_visitor
*original
, int samplerIndex
)
4480 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4481 struct st_context
*st
= st_context(original
->ctx
);
4482 struct gl_program
*prog
= &fp
->Base
.Base
;
4483 st_src_reg coord
, src0
;
4485 glsl_to_tgsi_instruction
*inst
;
4487 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4488 v
->ctx
= original
->ctx
;
4490 v
->shader_program
= NULL
;
4492 v
->glsl_version
= original
->glsl_version
;
4493 v
->native_integers
= original
->native_integers
;
4494 v
->options
= original
->options
;
4495 v
->next_temp
= original
->next_temp
;
4496 v
->num_address_regs
= original
->num_address_regs
;
4497 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4498 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4499 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4500 v
->num_immediates
= original
->num_immediates
;
4502 /* TEX tmp0, fragment.texcoord[0], texture[0], 2D; */
4503 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4504 src0
= v
->get_temp(glsl_type::vec4_type
);
4505 dst0
= st_dst_reg(src0
);
4506 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4507 inst
->sampler
.index
= samplerIndex
;
4508 inst
->sampler_array_size
= 1;
4509 inst
->tex_target
= TEXTURE_2D_INDEX
;
4511 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4512 prog
->SamplersUsed
|= (1 << samplerIndex
); /* mark sampler as used */
4513 v
->samplers_used
|= (1 << samplerIndex
);
4515 /* KIL if -tmp0 < 0 # texel=0 -> keep / texel=0 -> discard */
4516 src0
.negate
= NEGATE_XYZW
;
4517 if (st
->bitmap
.tex_format
== PIPE_FORMAT_L8_UNORM
)
4518 src0
.swizzle
= SWIZZLE_XXXX
;
4519 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_KILL_IF
, undef_dst
, src0
);
4521 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4523 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4524 glsl_to_tgsi_instruction
*newinst
;
4525 st_src_reg src_regs
[4];
4527 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4528 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4530 for (int i
= 0; i
< 4; i
++) {
4531 src_regs
[i
] = inst
->src
[i
];
4532 if (src_regs
[i
].file
== PROGRAM_INPUT
)
4533 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4536 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2], src_regs
[3]);
4537 newinst
->tex_target
= inst
->tex_target
;
4538 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4541 /* Make modifications to fragment program info. */
4542 prog
->Parameters
= _mesa_clone_parameter_list(original
->prog
->Parameters
);
4543 count_resources(v
, prog
);
4544 fp
->glsl_to_tgsi
= v
;
4547 /* ------------------------- TGSI conversion stuff -------------------------- */
4549 unsigned branch_target
;
4554 * Intermediate state used during shader translation.
4556 struct st_translate
{
4557 struct ureg_program
*ureg
;
4559 unsigned temps_size
;
4560 struct ureg_dst
*temps
;
4562 struct ureg_dst
*arrays
;
4563 unsigned num_temp_arrays
;
4564 struct ureg_src
*constants
;
4566 struct ureg_src
*immediates
;
4568 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
4569 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
4570 struct ureg_dst address
[3];
4571 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
4572 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
4573 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
4574 unsigned *array_sizes
;
4575 struct array_decl
*input_arrays
;
4576 struct array_decl
*output_arrays
;
4578 const GLuint
*inputMapping
;
4579 const GLuint
*outputMapping
;
4581 /* For every instruction that contains a label (eg CALL), keep
4582 * details so that we can go back afterwards and emit the correct
4583 * tgsi instruction number for each label.
4585 struct label
*labels
;
4586 unsigned labels_size
;
4587 unsigned labels_count
;
4589 /* Keep a record of the tgsi instruction number that each mesa
4590 * instruction starts at, will be used to fix up labels after
4595 unsigned insn_count
;
4597 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
4602 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
4603 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
4606 TGSI_SEMANTIC_VERTEXID
,
4607 TGSI_SEMANTIC_INSTANCEID
,
4608 TGSI_SEMANTIC_VERTEXID_NOBASE
,
4609 TGSI_SEMANTIC_BASEVERTEX
,
4613 TGSI_SEMANTIC_INVOCATIONID
,
4618 TGSI_SEMANTIC_SAMPLEID
,
4619 TGSI_SEMANTIC_SAMPLEPOS
,
4620 TGSI_SEMANTIC_SAMPLEMASK
,
4622 /* Tessellation shaders
4624 TGSI_SEMANTIC_TESSCOORD
,
4625 TGSI_SEMANTIC_VERTICESIN
,
4626 TGSI_SEMANTIC_PRIMID
,
4627 TGSI_SEMANTIC_TESSOUTER
,
4628 TGSI_SEMANTIC_TESSINNER
,
4632 * Make note of a branch to a label in the TGSI code.
4633 * After we've emitted all instructions, we'll go over the list
4634 * of labels built here and patch the TGSI code with the actual
4635 * location of each label.
4637 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
4641 if (t
->labels_count
+ 1 >= t
->labels_size
) {
4642 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
4643 t
->labels
= (struct label
*)realloc(t
->labels
,
4644 t
->labels_size
* sizeof(struct label
));
4645 if (t
->labels
== NULL
) {
4646 static unsigned dummy
;
4652 i
= t
->labels_count
++;
4653 t
->labels
[i
].branch_target
= branch_target
;
4654 return &t
->labels
[i
].token
;
4658 * Called prior to emitting the TGSI code for each instruction.
4659 * Allocate additional space for instructions if needed.
4660 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
4661 * the next TGSI instruction.
4663 static void set_insn_start(struct st_translate
*t
, unsigned start
)
4665 if (t
->insn_count
+ 1 >= t
->insn_size
) {
4666 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
4667 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
4668 if (t
->insn
== NULL
) {
4674 t
->insn
[t
->insn_count
++] = start
;
4678 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
4680 static struct ureg_src
4681 emit_immediate(struct st_translate
*t
,
4682 gl_constant_value values
[4],
4685 struct ureg_program
*ureg
= t
->ureg
;
4690 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
4692 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
4694 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
4695 case GL_UNSIGNED_INT
:
4697 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
4699 assert(!"should not get here - type must be float, int, uint, or bool");
4700 return ureg_src_undef();
4705 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
4707 static struct ureg_dst
4708 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
4714 case PROGRAM_UNDEFINED
:
4715 return ureg_dst_undef();
4717 case PROGRAM_TEMPORARY
:
4718 /* Allocate space for temporaries on demand. */
4719 if (index
>= t
->temps_size
) {
4720 const int inc
= 4096;
4722 t
->temps
= (struct ureg_dst
*)
4724 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
4726 return ureg_dst_undef();
4728 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
4729 t
->temps_size
+= inc
;
4732 if (ureg_dst_is_undef(t
->temps
[index
]))
4733 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
4735 return t
->temps
[index
];
4738 array
= index
>> 16;
4740 assert(array
< t
->num_temp_arrays
);
4742 if (ureg_dst_is_undef(t
->arrays
[array
]))
4743 t
->arrays
[array
] = ureg_DECL_array_temporary(
4744 t
->ureg
, t
->array_sizes
[array
], TRUE
);
4746 return ureg_dst_array_offset(t
->arrays
[array
],
4747 (int)(index
& 0xFFFF) - 0x8000);
4749 case PROGRAM_OUTPUT
:
4751 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
4752 assert(index
< FRAG_RESULT_MAX
);
4753 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
4754 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
4755 assert(index
< VARYING_SLOT_TESS_MAX
);
4757 assert(index
< VARYING_SLOT_MAX
);
4759 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
4760 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4761 return t
->outputs
[t
->outputMapping
[index
]];
4764 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
4765 unsigned mesa_index
= decl
->mesa_index
;
4766 int slot
= t
->outputMapping
[mesa_index
];
4768 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
4769 assert(t
->outputs
[slot
].ArrayID
== array_id
);
4770 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
4773 case PROGRAM_ADDRESS
:
4774 return t
->address
[index
];
4777 assert(!"unknown dst register file");
4778 return ureg_dst_undef();
4783 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
4785 static struct ureg_src
4786 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
4788 int index
= reg
->index
;
4789 int double_reg2
= reg
->double_reg2
? 1 : 0;
4792 case PROGRAM_UNDEFINED
:
4793 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4795 case PROGRAM_TEMPORARY
:
4797 case PROGRAM_OUTPUT
:
4798 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
4800 case PROGRAM_UNIFORM
:
4801 assert(reg
->index
>= 0);
4802 return reg
->index
< t
->num_constants
?
4803 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4804 case PROGRAM_STATE_VAR
:
4805 case PROGRAM_CONSTANT
: /* ie, immediate */
4806 if (reg
->has_index2
)
4807 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
4809 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
4810 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4812 case PROGRAM_IMMEDIATE
:
4813 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
4814 return t
->immediates
[reg
->index
];
4817 /* GLSL inputs are 64-bit containers, so we have to
4818 * map back to the original index and add the offset after
4820 index
-= double_reg2
;
4821 if (!reg
->array_id
) {
4822 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
4823 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4824 return t
->inputs
[t
->inputMapping
[index
]];
4827 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
4828 unsigned mesa_index
= decl
->mesa_index
;
4829 int slot
= t
->inputMapping
[mesa_index
];
4831 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
4832 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
4833 return ureg_src_array_offset(t
->inputs
[slot
], index
- mesa_index
);
4836 case PROGRAM_ADDRESS
:
4837 return ureg_src(t
->address
[reg
->index
]);
4839 case PROGRAM_SYSTEM_VALUE
:
4840 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
4841 return t
->systemValues
[reg
->index
];
4844 assert(!"unknown src register file");
4845 return ureg_src_undef();
4850 * Create a TGSI ureg_dst register from an st_dst_reg.
4852 static struct ureg_dst
4853 translate_dst(struct st_translate
*t
,
4854 const st_dst_reg
*dst_reg
,
4855 bool saturate
, bool clamp_color
)
4857 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
4860 if (dst
.File
== TGSI_FILE_NULL
)
4863 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
4866 dst
= ureg_saturate(dst
);
4867 else if (clamp_color
&& dst_reg
->file
== PROGRAM_OUTPUT
) {
4868 /* Clamp colors for ARB_color_buffer_float. */
4869 switch (t
->procType
) {
4870 case TGSI_PROCESSOR_VERTEX
:
4871 /* This can only occur with a compatibility profile, which doesn't
4872 * support geometry shaders. */
4873 if (dst_reg
->index
== VARYING_SLOT_COL0
||
4874 dst_reg
->index
== VARYING_SLOT_COL1
||
4875 dst_reg
->index
== VARYING_SLOT_BFC0
||
4876 dst_reg
->index
== VARYING_SLOT_BFC1
) {
4877 dst
= ureg_saturate(dst
);
4881 case TGSI_PROCESSOR_FRAGMENT
:
4882 if (dst_reg
->index
== FRAG_RESULT_COLOR
||
4883 dst_reg
->index
>= FRAG_RESULT_DATA0
) {
4884 dst
= ureg_saturate(dst
);
4890 if (dst_reg
->reladdr
!= NULL
) {
4891 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
4892 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
4895 if (dst_reg
->has_index2
) {
4896 if (dst_reg
->reladdr2
)
4897 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
4900 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
4907 * Create a TGSI ureg_src register from an st_src_reg.
4909 static struct ureg_src
4910 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
4912 struct ureg_src src
= src_register(t
, src_reg
);
4914 if (src_reg
->has_index2
) {
4915 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
4916 * and UBO constant buffers (buffer, position).
4918 if (src_reg
->reladdr2
)
4919 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
4922 src
= ureg_src_dimension(src
, src_reg
->index2D
);
4925 src
= ureg_swizzle(src
,
4926 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
4927 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
4928 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
4929 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
4931 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
4932 src
= ureg_negate(src
);
4934 if (src_reg
->reladdr
!= NULL
) {
4935 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
4936 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
4942 static struct tgsi_texture_offset
4943 translate_tex_offset(struct st_translate
*t
,
4944 const st_src_reg
*in_offset
, int idx
)
4946 struct tgsi_texture_offset offset
;
4947 struct ureg_src imm_src
;
4948 struct ureg_dst dst
;
4951 switch (in_offset
->file
) {
4952 case PROGRAM_IMMEDIATE
:
4953 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
4954 imm_src
= t
->immediates
[in_offset
->index
];
4956 offset
.File
= imm_src
.File
;
4957 offset
.Index
= imm_src
.Index
;
4958 offset
.SwizzleX
= imm_src
.SwizzleX
;
4959 offset
.SwizzleY
= imm_src
.SwizzleY
;
4960 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
4963 case PROGRAM_TEMPORARY
:
4964 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
4965 offset
.File
= imm_src
.File
;
4966 offset
.Index
= imm_src
.Index
;
4967 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4968 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4969 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4973 array
= in_offset
->index
>> 16;
4976 assert(array
< (int)t
->num_temp_arrays
);
4978 dst
= t
->arrays
[array
];
4979 offset
.File
= dst
.File
;
4980 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
4981 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4982 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4983 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4993 compile_tgsi_instruction(struct st_translate
*t
,
4994 const glsl_to_tgsi_instruction
*inst
,
4995 bool clamp_dst_color_output
)
4997 struct ureg_program
*ureg
= t
->ureg
;
4999 struct ureg_dst dst
[2];
5000 struct ureg_src src
[4];
5001 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5005 unsigned tex_target
;
5007 num_dst
= num_inst_dst_regs(inst
);
5008 num_src
= num_inst_src_regs(inst
);
5010 for (i
= 0; i
< num_dst
; i
++)
5011 dst
[i
] = translate_dst(t
,
5014 clamp_dst_color_output
);
5016 for (i
= 0; i
< num_src
; i
++)
5017 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5020 case TGSI_OPCODE_BGNLOOP
:
5021 case TGSI_OPCODE_CAL
:
5022 case TGSI_OPCODE_ELSE
:
5023 case TGSI_OPCODE_ENDLOOP
:
5024 case TGSI_OPCODE_IF
:
5025 case TGSI_OPCODE_UIF
:
5026 assert(num_dst
== 0);
5027 ureg_label_insn(ureg
,
5031 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5034 case TGSI_OPCODE_TEX
:
5035 case TGSI_OPCODE_TXB
:
5036 case TGSI_OPCODE_TXD
:
5037 case TGSI_OPCODE_TXL
:
5038 case TGSI_OPCODE_TXP
:
5039 case TGSI_OPCODE_TXQ
:
5040 case TGSI_OPCODE_TXQS
:
5041 case TGSI_OPCODE_TXF
:
5042 case TGSI_OPCODE_TEX2
:
5043 case TGSI_OPCODE_TXB2
:
5044 case TGSI_OPCODE_TXL2
:
5045 case TGSI_OPCODE_TG4
:
5046 case TGSI_OPCODE_LODQ
:
5047 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5048 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5049 if (inst
->sampler
.reladdr
)
5051 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5053 for (i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5054 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5056 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5062 texoffsets
, inst
->tex_offset_num_offset
,
5066 case TGSI_OPCODE_SCS
:
5067 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5068 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5081 * Emit the TGSI instructions for inverting and adjusting WPOS.
5082 * This code is unavoidable because it also depends on whether
5083 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5086 emit_wpos_adjustment( struct st_translate
*t
,
5087 int wpos_transform_const
,
5089 GLfloat adjX
, GLfloat adjY
[2])
5091 struct ureg_program
*ureg
= t
->ureg
;
5093 assert(wpos_transform_const
>= 0);
5095 /* Fragment program uses fragment position input.
5096 * Need to replace instances of INPUT[WPOS] with temp T
5097 * where T = INPUT[WPOS] is inverted by Y.
5099 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5100 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5101 struct ureg_src wpos_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5103 /* First, apply the coordinate shift: */
5104 if (adjX
|| adjY
[0] || adjY
[1]) {
5105 if (adjY
[0] != adjY
[1]) {
5106 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5107 * depending on whether inversion is actually going to be applied
5108 * or not, which is determined by testing against the inversion
5109 * state variable used below, which will be either +1 or -1.
5111 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5113 ureg_CMP(ureg
, adj_temp
,
5114 ureg_scalar(wpostrans
, invert
? 2 : 0),
5115 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5116 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5117 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5119 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5120 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5122 wpos_input
= ureg_src(wpos_temp
);
5124 /* MOV wpos_temp, input[wpos]
5126 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5129 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5130 * inversion/identity, or the other way around if we're drawing to an FBO.
5133 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5136 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5138 ureg_scalar(wpostrans
, 0),
5139 ureg_scalar(wpostrans
, 1));
5141 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5144 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5146 ureg_scalar(wpostrans
, 2),
5147 ureg_scalar(wpostrans
, 3));
5150 /* Use wpos_temp as position input from here on:
5152 t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]] = ureg_src(wpos_temp
);
5157 * Emit fragment position/ooordinate code.
5160 emit_wpos(struct st_context
*st
,
5161 struct st_translate
*t
,
5162 const struct gl_program
*program
,
5163 struct ureg_program
*ureg
,
5164 int wpos_transform_const
)
5166 const struct gl_fragment_program
*fp
=
5167 (const struct gl_fragment_program
*) program
;
5168 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5169 GLfloat adjX
= 0.0f
;
5170 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5171 boolean invert
= FALSE
;
5173 /* Query the pixel center conventions supported by the pipe driver and set
5174 * adjX, adjY to help out if it cannot handle the requested one internally.
5176 * The bias of the y-coordinate depends on whether y-inversion takes place
5177 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5178 * drawing to an FBO (causes additional inversion), and whether the the pipe
5179 * driver origin and the requested origin differ (the latter condition is
5180 * stored in the 'invert' variable).
5182 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5184 * center shift only:
5189 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5190 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5191 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5192 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5194 * inversion and center shift:
5195 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5196 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5197 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5198 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5200 if (fp
->OriginUpperLeft
) {
5201 /* Fragment shader wants origin in upper-left */
5202 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5203 /* the driver supports upper-left origin */
5205 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5206 /* the driver supports lower-left origin, need to invert Y */
5207 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5208 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5215 /* Fragment shader wants origin in lower-left */
5216 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5217 /* the driver supports lower-left origin */
5218 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5219 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5220 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5221 /* the driver supports upper-left origin, need to invert Y */
5227 if (fp
->PixelCenterInteger
) {
5228 /* Fragment shader wants pixel center integer */
5229 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5230 /* the driver supports pixel center integer */
5232 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5233 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5235 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5236 /* the driver supports pixel center half integer, need to bias X,Y */
5245 /* Fragment shader wants pixel center half integer */
5246 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5247 /* the driver supports pixel center half integer */
5249 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5250 /* the driver supports pixel center integer, need to bias X,Y */
5251 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5252 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5253 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5259 /* we invert after adjustment so that we avoid the MOV to temporary,
5260 * and reuse the adjustment ADD instead */
5261 emit_wpos_adjustment(t
, wpos_transform_const
, invert
, adjX
, adjY
);
5265 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5266 * TGSI uses +1 for front, -1 for back.
5267 * This function converts the TGSI value to the GL value. Simply clamping/
5268 * saturating the value to [0,1] does the job.
5271 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5273 struct ureg_program
*ureg
= t
->ureg
;
5274 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5275 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5277 if (ctx
->Const
.NativeIntegers
) {
5278 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5281 /* MOV_SAT face_temp, input[face] */
5282 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5285 /* Use face_temp as face input from here on: */
5286 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5290 emit_edgeflags(struct st_translate
*t
)
5292 struct ureg_program
*ureg
= t
->ureg
;
5293 struct ureg_dst edge_dst
= t
->outputs
[t
->outputMapping
[VARYING_SLOT_EDGE
]];
5294 struct ureg_src edge_src
= t
->inputs
[t
->inputMapping
[VERT_ATTRIB_EDGEFLAG
]];
5296 ureg_MOV(ureg
, edge_dst
, edge_src
);
5300 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5301 unsigned *array_id
, unsigned *array_size
)
5305 for (i
= 0; i
< count
; i
++) {
5306 struct array_decl
*decl
= &arrays
[i
];
5308 if (attr
== decl
->mesa_index
) {
5309 *array_id
= decl
->array_id
;
5310 *array_size
= decl
->array_size
;
5311 assert(*array_size
);
5319 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5320 * \param program the program to translate
5321 * \param numInputs number of input registers used
5322 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5324 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5325 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5327 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5328 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5329 * \param numOutputs number of output registers used
5330 * \param outputMapping maps Mesa fragment program outputs to TGSI
5332 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5333 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5336 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5338 extern "C" enum pipe_error
5339 st_translate_program(
5340 struct gl_context
*ctx
,
5342 struct ureg_program
*ureg
,
5343 glsl_to_tgsi_visitor
*program
,
5344 const struct gl_program
*proginfo
,
5346 const GLuint inputMapping
[],
5347 const GLuint inputSlotToAttr
[],
5348 const ubyte inputSemanticName
[],
5349 const ubyte inputSemanticIndex
[],
5350 const GLuint interpMode
[],
5351 const GLuint interpLocation
[],
5353 const GLuint outputMapping
[],
5354 const GLuint outputSlotToAttr
[],
5355 const ubyte outputSemanticName
[],
5356 const ubyte outputSemanticIndex
[],
5357 boolean passthrough_edgeflags
,
5358 boolean clamp_color
)
5360 struct st_translate
*t
;
5362 enum pipe_error ret
= PIPE_OK
;
5364 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5365 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5367 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5368 TGSI_SEMANTIC_FACE
);
5369 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5370 TGSI_SEMANTIC_VERTEXID
);
5371 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5372 TGSI_SEMANTIC_INSTANCEID
);
5373 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5374 TGSI_SEMANTIC_SAMPLEID
);
5375 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5376 TGSI_SEMANTIC_SAMPLEPOS
);
5377 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5378 TGSI_SEMANTIC_SAMPLEMASK
);
5379 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5380 TGSI_SEMANTIC_INVOCATIONID
);
5381 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5382 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5383 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5384 TGSI_SEMANTIC_BASEVERTEX
);
5385 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5386 TGSI_SEMANTIC_TESSCOORD
);
5388 t
= CALLOC_STRUCT(st_translate
);
5390 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5394 t
->procType
= procType
;
5395 t
->inputMapping
= inputMapping
;
5396 t
->outputMapping
= outputMapping
;
5398 t
->num_temp_arrays
= program
->next_array
;
5399 if (t
->num_temp_arrays
)
5400 t
->arrays
= (struct ureg_dst
*)
5401 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5404 * Declare input attributes.
5407 case TGSI_PROCESSOR_FRAGMENT
:
5408 for (i
= 0; i
< numInputs
; i
++) {
5409 unsigned array_id
= 0;
5410 unsigned array_size
;
5412 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5413 program
->num_input_arrays
, &array_id
, &array_size
)) {
5414 /* We've found an array. Declare it so. */
5415 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5416 inputSemanticName
[i
], inputSemanticIndex
[i
],
5417 interpMode
[i
], 0, interpLocation
[i
],
5418 array_id
, array_size
);
5419 i
+= array_size
- 1;
5422 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5423 inputSemanticName
[i
], inputSemanticIndex
[i
],
5424 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
5428 case TGSI_PROCESSOR_GEOMETRY
:
5429 case TGSI_PROCESSOR_TESS_EVAL
:
5430 case TGSI_PROCESSOR_TESS_CTRL
:
5431 for (i
= 0; i
< numInputs
; i
++) {
5432 unsigned array_id
= 0;
5433 unsigned array_size
;
5435 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5436 program
->num_input_arrays
, &array_id
, &array_size
)) {
5437 /* We've found an array. Declare it so. */
5438 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5439 inputSemanticIndex
[i
],
5440 array_id
, array_size
);
5441 i
+= array_size
- 1;
5444 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5445 inputSemanticIndex
[i
], 0, 1);
5449 case TGSI_PROCESSOR_VERTEX
:
5450 for (i
= 0; i
< numInputs
; i
++) {
5451 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
5459 * Declare output attributes.
5462 case TGSI_PROCESSOR_FRAGMENT
:
5464 case TGSI_PROCESSOR_GEOMETRY
:
5465 case TGSI_PROCESSOR_TESS_EVAL
:
5466 case TGSI_PROCESSOR_TESS_CTRL
:
5467 case TGSI_PROCESSOR_VERTEX
:
5468 for (i
= 0; i
< numOutputs
; i
++) {
5469 unsigned array_id
= 0;
5470 unsigned array_size
;
5472 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
5473 program
->num_output_arrays
, &array_id
, &array_size
)) {
5474 /* We've found an array. Declare it so. */
5475 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
5476 outputSemanticName
[i
],
5477 outputSemanticIndex
[i
],
5478 array_id
, array_size
);
5479 i
+= array_size
- 1;
5482 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5483 outputSemanticName
[i
],
5484 outputSemanticIndex
[i
]);
5492 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
5493 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
5494 /* Must do this after setting up t->inputs. */
5495 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
5496 program
->wpos_transform_const
);
5499 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
5500 emit_face_var(ctx
, t
);
5502 for (i
= 0; i
< numOutputs
; i
++) {
5503 switch (outputSemanticName
[i
]) {
5504 case TGSI_SEMANTIC_POSITION
:
5505 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5506 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
5507 outputSemanticIndex
[i
]);
5508 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
5510 case TGSI_SEMANTIC_STENCIL
:
5511 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5512 TGSI_SEMANTIC_STENCIL
, /* Stencil */
5513 outputSemanticIndex
[i
]);
5514 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
5516 case TGSI_SEMANTIC_COLOR
:
5517 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5518 TGSI_SEMANTIC_COLOR
,
5519 outputSemanticIndex
[i
]);
5521 case TGSI_SEMANTIC_SAMPLEMASK
:
5522 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5523 TGSI_SEMANTIC_SAMPLEMASK
,
5524 outputSemanticIndex
[i
]);
5525 /* TODO: If we ever support more than 32 samples, this will have
5526 * to become an array.
5528 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5531 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
5532 ret
= PIPE_ERROR_BAD_INPUT
;
5537 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
5538 for (i
= 0; i
< numOutputs
; i
++) {
5539 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
5540 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
5542 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
5543 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
5544 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5547 if (passthrough_edgeflags
)
5551 /* Declare address register.
5553 if (program
->num_address_regs
> 0) {
5554 assert(program
->num_address_regs
<= 3);
5555 for (int i
= 0; i
< program
->num_address_regs
; i
++)
5556 t
->address
[i
] = ureg_DECL_address(ureg
);
5559 /* Declare misc input registers
5562 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
5563 unsigned numSys
= 0;
5564 for (i
= 0; sysInputs
; i
++) {
5565 if (sysInputs
& (1 << i
)) {
5566 unsigned semName
= _mesa_sysval_to_semantic
[i
];
5567 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, numSys
, semName
, 0);
5568 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
5569 semName
== TGSI_SEMANTIC_VERTEXID
) {
5570 /* From Gallium perspective, these system values are always
5571 * integer, and require native integer support. However, if
5572 * native integer is supported on the vertex stage but not the
5573 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
5574 * assumes these system values are floats. To resolve the
5575 * inconsistency, we insert a U2F.
5577 struct st_context
*st
= st_context(ctx
);
5578 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5579 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5580 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
5582 if (!ctx
->Const
.NativeIntegers
) {
5583 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
5584 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
5585 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
5589 sysInputs
&= ~(1 << i
);
5594 t
->array_sizes
= program
->array_sizes
;
5595 t
->input_arrays
= program
->input_arrays
;
5596 t
->output_arrays
= program
->output_arrays
;
5598 /* Emit constants and uniforms. TGSI uses a single index space for these,
5599 * so we put all the translated regs in t->constants.
5601 if (proginfo
->Parameters
) {
5602 t
->constants
= (struct ureg_src
*)
5603 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
5604 if (t
->constants
== NULL
) {
5605 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5608 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
5610 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
5611 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
5612 case PROGRAM_STATE_VAR
:
5613 case PROGRAM_UNIFORM
:
5614 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5617 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
5618 * addressing of the const buffer.
5619 * FIXME: Be smarter and recognize param arrays:
5620 * indirect addressing is only valid within the referenced
5623 case PROGRAM_CONSTANT
:
5624 if (program
->indirect_addr_consts
)
5625 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5627 t
->constants
[i
] = emit_immediate(t
,
5628 proginfo
->Parameters
->ParameterValues
[i
],
5629 proginfo
->Parameters
->Parameters
[i
].DataType
,
5638 if (program
->shader
) {
5639 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
5641 for (i
= 0; i
< num_ubos
; i
++) {
5642 unsigned size
= program
->shader
->UniformBlocks
[i
].UniformBufferSize
;
5643 unsigned num_const_vecs
= (size
+ 15) / 16;
5644 unsigned first
, last
;
5645 assert(num_const_vecs
> 0);
5647 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
5648 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
5652 /* Emit immediate values.
5654 t
->immediates
= (struct ureg_src
*)
5655 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
5656 if (t
->immediates
== NULL
) {
5657 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5660 t
->num_immediates
= program
->num_immediates
;
5663 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
5664 assert(i
< program
->num_immediates
);
5665 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
5667 assert(i
== program
->num_immediates
);
5669 /* texture samplers */
5670 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
5671 if (program
->samplers_used
& (1 << i
)) {
5674 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
5676 switch (program
->sampler_types
[i
]) {
5678 type
= TGSI_RETURN_TYPE_SINT
;
5680 case GLSL_TYPE_UINT
:
5681 type
= TGSI_RETURN_TYPE_UINT
;
5683 case GLSL_TYPE_FLOAT
:
5684 type
= TGSI_RETURN_TYPE_FLOAT
;
5687 unreachable("not reached");
5690 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
5691 type
, type
, type
, type
);
5695 /* Emit each instruction in turn:
5697 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
5698 set_insn_start(t
, ureg_get_instruction_number(ureg
));
5699 compile_tgsi_instruction(t
, inst
, clamp_color
);
5702 /* Fix up all emitted labels:
5704 for (i
= 0; i
< t
->labels_count
; i
++) {
5705 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
5706 t
->insn
[t
->labels
[i
].branch_target
]);
5716 t
->num_constants
= 0;
5717 free(t
->immediates
);
5718 t
->num_immediates
= 0;
5721 debug_printf("%s: translate error flag set\n", __func__
);
5729 /* ----------------------------- End TGSI code ------------------------------ */
5733 * Convert a shader's GLSL IR into a Mesa gl_program, although without
5734 * generating Mesa IR.
5736 static struct gl_program
*
5737 get_mesa_program(struct gl_context
*ctx
,
5738 struct gl_shader_program
*shader_program
,
5739 struct gl_shader
*shader
)
5741 glsl_to_tgsi_visitor
* v
;
5742 struct gl_program
*prog
;
5743 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
5745 struct gl_shader_compiler_options
*options
=
5746 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
5747 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5748 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
5750 validate_ir_tree(shader
->ir
);
5752 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
5755 prog
->Parameters
= _mesa_new_parameter_list();
5756 v
= new glsl_to_tgsi_visitor();
5759 v
->shader_program
= shader_program
;
5761 v
->options
= options
;
5762 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
5763 v
->native_integers
= ctx
->Const
.NativeIntegers
;
5765 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
5766 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
5767 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
5768 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
5770 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
5771 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
5774 /* Remove reads from output registers. */
5775 lower_output_reads(shader
->Stage
, shader
->ir
);
5777 /* Emit intermediate IR for main(). */
5778 visit_exec_list(shader
->ir
, v
);
5780 /* Now emit bodies for any functions that were used. */
5782 progress
= GL_FALSE
;
5784 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
5785 if (!entry
->bgn_inst
) {
5786 v
->current_function
= entry
;
5788 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
5789 entry
->bgn_inst
->function
= entry
;
5791 visit_exec_list(&entry
->sig
->body
, v
);
5793 glsl_to_tgsi_instruction
*last
;
5794 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
5795 if (last
->op
!= TGSI_OPCODE_RET
)
5796 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
5798 glsl_to_tgsi_instruction
*end
;
5799 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
5800 end
->function
= entry
;
5808 /* Print out some information (for debugging purposes) used by the
5809 * optimization passes. */
5812 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5813 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5814 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5815 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5817 for (i
= 0; i
< v
->next_temp
; i
++) {
5818 first_writes
[i
] = -1;
5819 first_reads
[i
] = -1;
5820 last_writes
[i
] = -1;
5823 v
->get_first_temp_read(first_reads
);
5824 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5825 v
->get_last_temp_write(last_writes
);
5826 for (i
= 0; i
< v
->next_temp
; i
++)
5827 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
5831 ralloc_free(first_writes
);
5832 ralloc_free(first_reads
);
5833 ralloc_free(last_writes
);
5834 ralloc_free(last_reads
);
5838 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
5841 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
5842 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
5843 v
->copy_propagate();
5845 while (v
->eliminate_dead_code());
5847 v
->merge_two_dsts();
5848 v
->merge_registers();
5849 v
->renumber_registers();
5851 /* Write the END instruction. */
5852 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
5854 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
5856 _mesa_log("GLSL IR for linked %s program %d:\n",
5857 _mesa_shader_stage_to_string(shader
->Stage
),
5858 shader_program
->Name
);
5859 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
5863 prog
->Instructions
= NULL
;
5864 prog
->NumInstructions
= 0;
5866 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
5867 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
5868 prog
->InputsRead
, prog
->PatchInputsRead
);
5869 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
5870 prog
->OutputsWritten
, prog
->PatchOutputsWritten
);
5871 count_resources(v
, prog
);
5873 /* This must be done before the uniform storage is associated. */
5874 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
5875 prog
->InputsRead
& VARYING_BIT_POS
){
5876 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
5877 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
5880 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
5881 wposTransformState
);
5884 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
5886 /* This has to be done last. Any operation the can cause
5887 * prog->ParameterValues to get reallocated (e.g., anything that adds a
5888 * program constant) has to happen before creating this linkage.
5890 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
5891 if (!shader_program
->LinkStatus
) {
5892 free_glsl_to_tgsi_visitor(v
);
5896 struct st_vertex_program
*stvp
;
5897 struct st_fragment_program
*stfp
;
5898 struct st_geometry_program
*stgp
;
5899 struct st_tessctrl_program
*sttcp
;
5900 struct st_tesseval_program
*sttep
;
5902 switch (shader
->Type
) {
5903 case GL_VERTEX_SHADER
:
5904 stvp
= (struct st_vertex_program
*)prog
;
5905 stvp
->glsl_to_tgsi
= v
;
5907 case GL_FRAGMENT_SHADER
:
5908 stfp
= (struct st_fragment_program
*)prog
;
5909 stfp
->glsl_to_tgsi
= v
;
5911 case GL_GEOMETRY_SHADER
:
5912 stgp
= (struct st_geometry_program
*)prog
;
5913 stgp
->glsl_to_tgsi
= v
;
5915 case GL_TESS_CONTROL_SHADER
:
5916 sttcp
= (struct st_tessctrl_program
*)prog
;
5917 sttcp
->glsl_to_tgsi
= v
;
5919 case GL_TESS_EVALUATION_SHADER
:
5920 sttep
= (struct st_tesseval_program
*)prog
;
5921 sttep
->glsl_to_tgsi
= v
;
5924 assert(!"should not be reached");
5934 st_dump_program_for_shader_db(struct gl_context
*ctx
,
5935 struct gl_shader_program
*prog
)
5937 /* Dump only successfully compiled and linked shaders to the specified
5938 * file. This is for shader-db.
5940 * These options allow some pre-processing of shaders while dumping,
5941 * because some apps have ill-formed shaders.
5943 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
5944 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
5946 if (dump_filename
&& prog
->Name
!= 0) {
5947 FILE *f
= fopen(dump_filename
, "a");
5950 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
5951 const struct gl_shader
*sh
= prog
->Shaders
[i
];
5953 bool skip_version
= false;
5958 source
= sh
->Source
;
5960 /* This string mustn't be changed. shader-db uses it to find
5961 * where the shader begins.
5963 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
5964 _mesa_shader_stage_to_string(sh
->Stage
),
5967 /* Dump the forced version if set. */
5968 if (ctx
->Const
.ForceGLSLVersion
) {
5969 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
5970 skip_version
= true;
5973 /* Insert directives (optional). */
5974 if (insert_directives
) {
5975 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
5976 fprintf(f
, "#version %i\n", prog
->Version
);
5977 fprintf(f
, "%s\n", insert_directives
);
5978 skip_version
= true;
5981 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
5982 const char *next_line
= strstr(source
, "\n");
5985 source
= next_line
+ 1;
5990 fprintf(f
, "%s", source
);
6000 * Called via ctx->Driver.LinkShader()
6001 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6002 * with code lowering and other optimizations.
6005 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6007 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6008 assert(prog
->LinkStatus
);
6010 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6011 if (prog
->_LinkedShaders
[i
] == NULL
)
6015 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6016 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6017 const struct gl_shader_compiler_options
*options
=
6018 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6019 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6020 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6021 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6022 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6023 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6025 /* If there are forms of indirect addressing that the driver
6026 * cannot handle, perform the lowering pass.
6028 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6029 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6030 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6031 options
->EmitNoIndirectInput
,
6032 options
->EmitNoIndirectOutput
,
6033 options
->EmitNoIndirectTemp
,
6034 options
->EmitNoIndirectUniform
);
6037 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6038 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6039 LOWER_UNPACK_SNORM_2x16
|
6040 LOWER_PACK_UNORM_2x16
|
6041 LOWER_UNPACK_UNORM_2x16
|
6042 LOWER_PACK_SNORM_4x8
|
6043 LOWER_UNPACK_SNORM_4x8
|
6044 LOWER_UNPACK_UNORM_4x8
|
6045 LOWER_PACK_UNORM_4x8
|
6046 LOWER_PACK_HALF_2x16
|
6047 LOWER_UNPACK_HALF_2x16
;
6049 if (ctx
->Extensions
.ARB_gpu_shader5
)
6050 lower_inst
|= LOWER_PACK_USE_BFI
|
6053 lower_packing_builtins(ir
, lower_inst
);
6056 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6057 lower_offset_arrays(ir
);
6058 do_mat_op_to_vec(ir
);
6059 lower_instructions(ir
,
6065 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6068 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6069 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6070 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6071 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6073 lower_ubo_reference(prog
->_LinkedShaders
[i
], ir
);
6074 do_vec_index_to_cond_assign(ir
);
6075 lower_vector_insert(ir
, true);
6076 lower_quadop_vector(ir
, false);
6078 if (options
->MaxIfDepth
== 0) {
6085 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6087 progress
= do_common_optimization(ir
, true, true, options
,
6088 ctx
->Const
.NativeIntegers
)
6091 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6095 validate_ir_tree(ir
);
6098 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6099 struct gl_program
*linked_prog
;
6101 if (prog
->_LinkedShaders
[i
] == NULL
)
6104 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6107 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6109 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6110 _mesa_shader_stage_to_program(i
),
6112 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6114 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6119 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6122 st_dump_program_for_shader_db(ctx
, prog
);
6127 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6128 const GLuint outputMapping
[],
6129 struct pipe_stream_output_info
*so
)
6132 struct gl_transform_feedback_info
*info
=
6133 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6135 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6136 so
->output
[i
].register_index
=
6137 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6138 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6139 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6140 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6141 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6142 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6145 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6146 so
->stride
[i
] = info
->BufferStride
[i
];
6148 so
->num_outputs
= info
->NumOutputs
;