2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "glsl_parser_extras.h"
36 #include "ir_optimization.h"
38 #include "main/errors.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "main/shaderapi.h"
42 #include "program/prog_instruction.h"
43 #include "program/sampler.h"
45 #include "pipe/p_context.h"
46 #include "pipe/p_screen.h"
47 #include "tgsi/tgsi_ureg.h"
48 #include "tgsi/tgsi_info.h"
49 #include "util/u_math.h"
50 #include "util/u_memory.h"
51 #include "st_program.h"
52 #include "st_mesa_to_tgsi.h"
55 #define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
56 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
57 (1 << PROGRAM_CONSTANT) | \
58 (1 << PROGRAM_UNIFORM))
60 #define MAX_GLSL_TEXTURE_OFFSET 4
65 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to TGSI ureg_src.
72 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
84 this->reladdr2
= NULL
;
85 this->has_index2
= false;
86 this->double_reg2
= false;
88 this->is_double_vertex_input
= false;
91 st_src_reg(gl_register_file file
, int index
, int type
)
97 this->swizzle
= SWIZZLE_XYZW
;
100 this->reladdr2
= NULL
;
101 this->has_index2
= false;
102 this->double_reg2
= false;
104 this->is_double_vertex_input
= false;
107 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
112 this->index2D
= index2D
;
113 this->swizzle
= SWIZZLE_XYZW
;
115 this->reladdr
= NULL
;
116 this->reladdr2
= NULL
;
117 this->has_index2
= false;
118 this->double_reg2
= false;
120 this->is_double_vertex_input
= false;
125 this->type
= GLSL_TYPE_ERROR
;
126 this->file
= PROGRAM_UNDEFINED
;
131 this->reladdr
= NULL
;
132 this->reladdr2
= NULL
;
133 this->has_index2
= false;
134 this->double_reg2
= false;
136 this->is_double_vertex_input
= false;
139 explicit st_src_reg(st_dst_reg reg
);
141 gl_register_file file
; /**< PROGRAM_* from Mesa */
142 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
144 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
145 int negate
; /**< NEGATE_XYZW mask from mesa */
146 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
147 /** Register index should be offset by the integer in this reg. */
149 st_src_reg
*reladdr2
;
152 * Is this the second half of a double register pair?
153 * currently used for input mapping only.
157 bool is_double_vertex_input
;
162 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
167 this->writemask
= writemask
;
168 this->cond_mask
= COND_TR
;
169 this->reladdr
= NULL
;
170 this->reladdr2
= NULL
;
171 this->has_index2
= false;
176 st_dst_reg(gl_register_file file
, int writemask
, int type
)
181 this->writemask
= writemask
;
182 this->cond_mask
= COND_TR
;
183 this->reladdr
= NULL
;
184 this->reladdr2
= NULL
;
185 this->has_index2
= false;
192 this->type
= GLSL_TYPE_ERROR
;
193 this->file
= PROGRAM_UNDEFINED
;
197 this->cond_mask
= COND_TR
;
198 this->reladdr
= NULL
;
199 this->reladdr2
= NULL
;
200 this->has_index2
= false;
204 explicit st_dst_reg(st_src_reg reg
);
206 gl_register_file file
; /**< PROGRAM_* from Mesa */
207 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
209 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
211 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
212 /** Register index should be offset by the integer in this reg. */
214 st_src_reg
*reladdr2
;
219 st_src_reg::st_src_reg(st_dst_reg reg
)
221 this->type
= reg
.type
;
222 this->file
= reg
.file
;
223 this->index
= reg
.index
;
224 this->swizzle
= SWIZZLE_XYZW
;
226 this->reladdr
= reg
.reladdr
;
227 this->index2D
= reg
.index2D
;
228 this->reladdr2
= reg
.reladdr2
;
229 this->has_index2
= reg
.has_index2
;
230 this->double_reg2
= false;
231 this->array_id
= reg
.array_id
;
232 this->is_double_vertex_input
= false;
235 st_dst_reg::st_dst_reg(st_src_reg reg
)
237 this->type
= reg
.type
;
238 this->file
= reg
.file
;
239 this->index
= reg
.index
;
240 this->writemask
= WRITEMASK_XYZW
;
241 this->cond_mask
= COND_TR
;
242 this->reladdr
= reg
.reladdr
;
243 this->index2D
= reg
.index2D
;
244 this->reladdr2
= reg
.reladdr2
;
245 this->has_index2
= reg
.has_index2
;
246 this->array_id
= reg
.array_id
;
249 class glsl_to_tgsi_instruction
: public exec_node
{
251 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
256 /** Pointer to the ir source this tree came from for debugging */
258 GLboolean cond_update
;
260 st_src_reg sampler
; /**< sampler register */
261 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
262 int tex_target
; /**< One of TEXTURE_*_INDEX */
263 glsl_base_type tex_type
;
264 GLboolean tex_shadow
;
266 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
267 unsigned tex_offset_num_offset
;
268 int dead_mask
; /**< Used in dead code elimination */
270 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
271 const struct tgsi_opcode_info
*info
;
274 class variable_storage
: public exec_node
{
276 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
277 unsigned array_id
= 0)
278 : file(file
), index(index
), var(var
), array_id(array_id
)
283 gl_register_file file
;
285 ir_variable
*var
; /* variable that maps to this, if any */
289 class immediate_storage
: public exec_node
{
291 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
293 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
294 this->size32
= size32
;
298 /* doubles are stored across 2 gl_constant_values */
299 gl_constant_value values
[4];
300 int size32
; /**< Number of 32-bit components (1-4) */
301 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
304 class function_entry
: public exec_node
{
306 ir_function_signature
*sig
;
309 * identifier of this function signature used by the program.
311 * At the point that TGSI instructions for function calls are
312 * generated, we don't know the address of the first instruction of
313 * the function body. So we make the BranchTarget that is called a
314 * small integer and rewrite them during set_branchtargets().
319 * Pointer to first instruction of the function body.
321 * Set during function body emits after main() is processed.
323 glsl_to_tgsi_instruction
*bgn_inst
;
326 * Index of the first instruction of the function body in actual TGSI.
328 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
332 /** Storage for the return value. */
333 st_src_reg return_reg
;
336 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
337 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
347 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
351 for (i
= 0; i
< count
; i
++) {
352 struct array_decl
*decl
= &arrays
[i
];
354 if (array_id
== decl
->array_id
) {
355 return decl
->array_type
;
358 return GLSL_TYPE_ERROR
;
361 struct rename_reg_pair
{
366 struct glsl_to_tgsi_visitor
: public ir_visitor
{
368 glsl_to_tgsi_visitor();
369 ~glsl_to_tgsi_visitor();
371 function_entry
*current_function
;
373 struct gl_context
*ctx
;
374 struct gl_program
*prog
;
375 struct gl_shader_program
*shader_program
;
376 struct gl_shader
*shader
;
377 struct gl_shader_compiler_options
*options
;
381 unsigned *array_sizes
;
382 unsigned max_num_arrays
;
385 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
386 unsigned num_input_arrays
;
387 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
388 unsigned num_output_arrays
;
390 int num_address_regs
;
392 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
393 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
394 bool indirect_addr_consts
;
395 int wpos_transform_const
;
398 bool native_integers
;
402 variable_storage
*find_variable_storage(ir_variable
*var
);
404 int add_constant(gl_register_file file
, gl_constant_value values
[8],
405 int size
, int datatype
, GLuint
*swizzle_out
);
407 function_entry
*get_function_signature(ir_function_signature
*sig
);
409 st_src_reg
get_temp(const glsl_type
*type
);
410 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
412 st_src_reg
st_src_reg_for_double(double val
);
413 st_src_reg
st_src_reg_for_float(float val
);
414 st_src_reg
st_src_reg_for_int(int val
);
415 st_src_reg
st_src_reg_for_type(int type
, int val
);
418 * \name Visit methods
420 * As typical for the visitor pattern, there must be one \c visit method for
421 * each concrete subclass of \c ir_instruction. Virtual base classes within
422 * the hierarchy should not have \c visit methods.
425 virtual void visit(ir_variable
*);
426 virtual void visit(ir_loop
*);
427 virtual void visit(ir_loop_jump
*);
428 virtual void visit(ir_function_signature
*);
429 virtual void visit(ir_function
*);
430 virtual void visit(ir_expression
*);
431 virtual void visit(ir_swizzle
*);
432 virtual void visit(ir_dereference_variable
*);
433 virtual void visit(ir_dereference_array
*);
434 virtual void visit(ir_dereference_record
*);
435 virtual void visit(ir_assignment
*);
436 virtual void visit(ir_constant
*);
437 virtual void visit(ir_call
*);
438 virtual void visit(ir_return
*);
439 virtual void visit(ir_discard
*);
440 virtual void visit(ir_texture
*);
441 virtual void visit(ir_if
*);
442 virtual void visit(ir_emit_vertex
*);
443 virtual void visit(ir_end_primitive
*);
444 virtual void visit(ir_barrier
*);
449 /** List of variable_storage */
452 /** List of immediate_storage */
453 exec_list immediates
;
454 unsigned num_immediates
;
456 /** List of function_entry */
457 exec_list function_signatures
;
458 int next_signature_id
;
460 /** List of glsl_to_tgsi_instruction */
461 exec_list instructions
;
463 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
464 st_dst_reg dst
= undef_dst
,
465 st_src_reg src0
= undef_src
,
466 st_src_reg src1
= undef_src
,
467 st_src_reg src2
= undef_src
,
468 st_src_reg src3
= undef_src
);
470 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
471 st_dst_reg dst
, st_dst_reg dst1
,
472 st_src_reg src0
= undef_src
,
473 st_src_reg src1
= undef_src
,
474 st_src_reg src2
= undef_src
,
475 st_src_reg src3
= undef_src
);
477 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
479 st_src_reg src0
, st_src_reg src1
);
482 * Emit the correct dot-product instruction for the type of arguments
484 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
490 void emit_scalar(ir_instruction
*ir
, unsigned op
,
491 st_dst_reg dst
, st_src_reg src0
);
493 void emit_scalar(ir_instruction
*ir
, unsigned op
,
494 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
496 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
498 bool try_emit_mad(ir_expression
*ir
,
500 bool try_emit_mad_for_and_not(ir_expression
*ir
,
503 void emit_swz(ir_expression
*ir
);
505 bool process_move_condition(ir_rvalue
*ir
);
507 void simplify_cmp(void);
509 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
510 void get_first_temp_read(int *first_reads
);
511 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
512 void get_last_temp_write(int *last_writes
);
514 void copy_propagate(void);
515 int eliminate_dead_code(void);
517 void merge_two_dsts(void);
518 void merge_registers(void);
519 void renumber_registers(void);
521 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
522 st_dst_reg
*l
, st_src_reg
*r
,
523 st_src_reg
*cond
, bool cond_swap
);
528 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
529 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
530 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
533 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
536 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
540 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
543 prog
->LinkStatus
= GL_FALSE
;
547 swizzle_for_size(int size
)
549 static const int size_swizzles
[4] = {
550 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
551 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
552 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
553 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
556 assert((size
>= 1) && (size
<= 4));
557 return size_swizzles
[size
- 1];
561 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
563 return op
->info
->num_dst
;
567 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
569 return op
->info
->is_tex
? op
->info
->num_src
- 1 : op
->info
->num_src
;
572 glsl_to_tgsi_instruction
*
573 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
574 st_dst_reg dst
, st_dst_reg dst1
,
575 st_src_reg src0
, st_src_reg src1
,
576 st_src_reg src2
, st_src_reg src3
)
578 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
579 int num_reladdr
= 0, i
, j
;
580 bool dst_is_double
[2];
582 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
584 /* If we have to do relative addressing, we want to load the ARL
585 * reg directly for one of the regs, and preload the other reladdr
586 * sources into temps.
588 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
589 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
590 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
591 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
592 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
593 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
595 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
596 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
597 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
598 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
600 if (dst
.reladdr
|| dst
.reladdr2
) {
602 emit_arl(ir
, address_reg
, *dst
.reladdr
);
604 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
608 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
611 assert(num_reladdr
== 0);
614 inst
->info
= tgsi_get_opcode_info(op
);
623 /* default to float, for paths where this is not initialized
624 * (since 0==UINT which is likely wrong):
626 inst
->tex_type
= GLSL_TYPE_FLOAT
;
628 inst
->function
= NULL
;
630 /* Update indirect addressing status used by TGSI */
631 if (dst
.reladdr
|| dst
.reladdr2
) {
633 case PROGRAM_STATE_VAR
:
634 case PROGRAM_CONSTANT
:
635 case PROGRAM_UNIFORM
:
636 this->indirect_addr_consts
= true;
638 case PROGRAM_IMMEDIATE
:
639 assert(!"immediates should not have indirect addressing");
646 for (i
= 0; i
< 4; i
++) {
647 if(inst
->src
[i
].reladdr
) {
648 switch(inst
->src
[i
].file
) {
649 case PROGRAM_STATE_VAR
:
650 case PROGRAM_CONSTANT
:
651 case PROGRAM_UNIFORM
:
652 this->indirect_addr_consts
= true;
654 case PROGRAM_IMMEDIATE
:
655 assert(!"immediates should not have indirect addressing");
664 this->instructions
.push_tail(inst
);
667 * This section contains the double processing.
668 * GLSL just represents doubles as single channel values,
669 * however most HW and TGSI represent doubles as pairs of register channels.
671 * so we have to fixup destination writemask/index and src swizzle/indexes.
672 * dest writemasks need to translate from single channel write mask
673 * to a dual-channel writemask, but also need to modify the index,
674 * if we are touching the Z,W fields in the pre-translated writemask.
676 * src channels have similiar index modifications along with swizzle
677 * changes to we pick the XY, ZW pairs from the correct index.
679 * GLSL [0].x -> TGSI [0].xy
680 * GLSL [0].y -> TGSI [0].zw
681 * GLSL [0].z -> TGSI [1].xy
682 * GLSL [0].w -> TGSI [1].zw
684 for (j
= 0; j
< 2; j
++) {
685 dst_is_double
[j
] = false;
686 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
687 dst_is_double
[j
] = true;
688 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
689 unsigned type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
690 if (type
== GLSL_TYPE_DOUBLE
)
691 dst_is_double
[j
] = true;
695 if (dst_is_double
[0] || dst_is_double
[1] ||
696 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
697 glsl_to_tgsi_instruction
*dinst
= NULL
;
698 int initial_src_swz
[4], initial_src_idx
[4];
699 int initial_dst_idx
[2], initial_dst_writemask
[2];
700 /* select the writemask for dst0 or dst1 */
701 unsigned writemask
= inst
->dst
[0].file
== PROGRAM_UNDEFINED
? inst
->dst
[1].writemask
: inst
->dst
[0].writemask
;
703 /* copy out the writemask, index and swizzles for all src/dsts. */
704 for (j
= 0; j
< 2; j
++) {
705 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
706 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
709 for (j
= 0; j
< 4; j
++) {
710 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
711 initial_src_idx
[j
] = inst
->src
[j
].index
;
715 * scan all the components in the dst writemask
716 * generate an instruction for each of them if required.
720 int i
= u_bit_scan(&writemask
);
722 /* first time use previous instruction */
726 /* create a new instructions for subsequent attempts */
727 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
731 this->instructions
.push_tail(dinst
);
734 /* modify the destination if we are splitting */
735 for (j
= 0; j
< 2; j
++) {
736 if (dst_is_double
[j
]) {
737 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
738 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
740 dinst
->dst
[j
].index
++;
742 /* if we aren't writing to a double, just get the bit of the initial writemask
744 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
748 /* modify the src registers */
749 for (j
= 0; j
< 4; j
++) {
750 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
752 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
753 dinst
->src
[j
].index
= initial_src_idx
[j
];
755 dinst
->src
[j
].double_reg2
= true;
756 dinst
->src
[j
].index
++;
760 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
762 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
765 /* some opcodes are special case in what they use as sources
766 - F2D is a float src0, DLDEXP is integer src1 */
767 if (op
== TGSI_OPCODE_F2D
||
768 op
== TGSI_OPCODE_DLDEXP
||
769 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
770 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
782 glsl_to_tgsi_instruction
*
783 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
785 st_src_reg src0
, st_src_reg src1
,
786 st_src_reg src2
, st_src_reg src3
)
788 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
792 * Determines whether to use an integer, unsigned integer, or float opcode
793 * based on the operands and input opcode, then emits the result.
796 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
798 st_src_reg src0
, st_src_reg src1
)
800 int type
= GLSL_TYPE_FLOAT
;
802 if (op
== TGSI_OPCODE_MOV
)
805 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
806 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
807 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
808 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
810 if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
811 type
= GLSL_TYPE_DOUBLE
;
812 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
813 type
= GLSL_TYPE_FLOAT
;
814 else if (native_integers
)
815 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
817 #define case5(c, f, i, u, d) \
818 case TGSI_OPCODE_##c: \
819 if (type == GLSL_TYPE_DOUBLE) \
820 op = TGSI_OPCODE_##d; \
821 else if (type == GLSL_TYPE_INT) \
822 op = TGSI_OPCODE_##i; \
823 else if (type == GLSL_TYPE_UINT) \
824 op = TGSI_OPCODE_##u; \
826 op = TGSI_OPCODE_##f; \
829 #define case4(c, f, i, u) \
830 case TGSI_OPCODE_##c: \
831 if (type == GLSL_TYPE_INT) \
832 op = TGSI_OPCODE_##i; \
833 else if (type == GLSL_TYPE_UINT) \
834 op = TGSI_OPCODE_##u; \
836 op = TGSI_OPCODE_##f; \
839 #define case3(f, i, u) case4(f, f, i, u)
840 #define case4d(f, i, u, d) case5(f, f, i, u, d)
841 #define case3fid(f, i, d) case5(f, f, i, i, d)
842 #define case2fi(f, i) case4(f, f, i, i)
843 #define case2iu(i, u) case4(i, LAST, i, u)
845 #define casecomp(c, f, i, u, d) \
846 case TGSI_OPCODE_##c: \
847 if (type == GLSL_TYPE_DOUBLE) \
848 op = TGSI_OPCODE_##d; \
849 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
850 op = TGSI_OPCODE_##i; \
851 else if (type == GLSL_TYPE_UINT) \
852 op = TGSI_OPCODE_##u; \
853 else if (native_integers) \
854 op = TGSI_OPCODE_##f; \
856 op = TGSI_OPCODE_##c; \
860 case3fid(ADD
, UADD
, DADD
);
861 case3fid(MUL
, UMUL
, DMUL
);
862 case3fid(MAD
, UMAD
, DMAD
);
863 case3fid(FMA
, UMAD
, DFMA
);
864 case3(DIV
, IDIV
, UDIV
);
865 case4d(MAX
, IMAX
, UMAX
, DMAX
);
866 case4d(MIN
, IMIN
, UMIN
, DMIN
);
869 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
870 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
871 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
872 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
876 case3fid(SSG
, ISSG
, DSSG
);
877 case3fid(ABS
, IABS
, DABS
);
881 case2iu(IMUL_HI
, UMUL_HI
);
883 case3fid(SQRT
, SQRT
, DSQRT
);
885 case3fid(RCP
, RCP
, DRCP
);
886 case3fid(RSQ
, RSQ
, DRSQ
);
888 case3fid(FRC
, FRC
, DFRAC
);
889 case3fid(TRUNC
, TRUNC
, DTRUNC
);
890 case3fid(CEIL
, CEIL
, DCEIL
);
891 case3fid(FLR
, FLR
, DFLR
);
892 case3fid(ROUND
, ROUND
, DROUND
);
897 assert(op
!= TGSI_OPCODE_LAST
);
901 glsl_to_tgsi_instruction
*
902 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
903 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
906 static const unsigned dot_opcodes
[] = {
907 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
910 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
914 * Emits TGSI scalar opcodes to produce unique answers across channels.
916 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
917 * channel determines the result across all channels. So to do a vec4
918 * of this operation, we want to emit a scalar per source channel used
919 * to produce dest channels.
922 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
924 st_src_reg orig_src0
, st_src_reg orig_src1
)
927 int done_mask
= ~dst
.writemask
;
929 /* TGSI RCP is a scalar operation splatting results to all channels,
930 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
933 for (i
= 0; i
< 4; i
++) {
934 GLuint this_mask
= (1 << i
);
935 st_src_reg src0
= orig_src0
;
936 st_src_reg src1
= orig_src1
;
938 if (done_mask
& this_mask
)
941 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
942 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
943 for (j
= i
+ 1; j
< 4; j
++) {
944 /* If there is another enabled component in the destination that is
945 * derived from the same inputs, generate its value on this pass as
948 if (!(done_mask
& (1 << j
)) &&
949 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
950 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
951 this_mask
|= (1 << j
);
954 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
955 src0_swiz
, src0_swiz
);
956 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
957 src1_swiz
, src1_swiz
);
959 dst
.writemask
= this_mask
;
960 emit_asm(ir
, op
, dst
, src0
, src1
);
961 done_mask
|= this_mask
;
966 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
967 st_dst_reg dst
, st_src_reg src0
)
969 st_src_reg undef
= undef_src
;
971 undef
.swizzle
= SWIZZLE_XXXX
;
973 emit_scalar(ir
, op
, dst
, src0
, undef
);
977 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
978 st_dst_reg dst
, st_src_reg src0
)
980 int op
= TGSI_OPCODE_ARL
;
982 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
983 op
= TGSI_OPCODE_UARL
;
985 assert(dst
.file
== PROGRAM_ADDRESS
);
986 if (dst
.index
>= this->num_address_regs
)
987 this->num_address_regs
= dst
.index
+ 1;
989 emit_asm(NULL
, op
, dst
, src0
);
993 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
994 gl_constant_value values
[8], int size
, int datatype
,
997 if (file
== PROGRAM_CONSTANT
) {
998 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
999 size
, datatype
, swizzle_out
);
1002 assert(file
== PROGRAM_IMMEDIATE
);
1005 immediate_storage
*entry
;
1006 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1009 /* Search immediate storage to see if we already have an identical
1010 * immediate that we can use instead of adding a duplicate entry.
1012 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1013 immediate_storage
*tmp
= entry
;
1015 for (i
= 0; i
* 4 < size32
; i
++) {
1016 int slot_size
= MIN2(size32
- (i
* 4), 4);
1017 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1019 if (memcmp(tmp
->values
, &values
[i
* 4],
1020 slot_size
* sizeof(gl_constant_value
)))
1023 /* Everything matches, keep going until the full size is matched */
1024 tmp
= (immediate_storage
*)tmp
->next
;
1027 /* The full value matched */
1028 if (i
* 4 >= size32
)
1034 for (i
= 0; i
* 4 < size32
; i
++) {
1035 int slot_size
= MIN2(size32
- (i
* 4), 4);
1036 /* Add this immediate to the list. */
1037 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1038 this->immediates
.push_tail(entry
);
1039 this->num_immediates
++;
1045 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1047 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1048 union gl_constant_value uval
;
1051 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1057 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1059 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1060 union gl_constant_value uval
[2];
1062 uval
[0].u
= *(uint32_t *)&val
;
1063 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1064 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1070 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1072 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1073 union gl_constant_value uval
;
1075 assert(native_integers
);
1078 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1084 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1086 if (native_integers
)
1087 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1088 st_src_reg_for_int(val
);
1090 return st_src_reg_for_float(val
);
1094 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1099 switch (type
->base_type
) {
1100 case GLSL_TYPE_UINT
:
1102 case GLSL_TYPE_FLOAT
:
1103 case GLSL_TYPE_BOOL
:
1104 if (type
->is_matrix()) {
1105 return type
->matrix_columns
;
1107 /* Regardless of size of vector, it gets a vec4. This is bad
1108 * packing for things like floats, but otherwise arrays become a
1109 * mess. Hopefully a later pass over the code can pack scalars
1110 * down if appropriate.
1115 case GLSL_TYPE_DOUBLE
:
1116 if (type
->is_matrix()) {
1117 if (type
->vector_elements
<= 2 || is_vs_input
)
1118 return type
->matrix_columns
;
1120 return type
->matrix_columns
* 2;
1122 /* For doubles if we have a double or dvec2 they fit in one
1123 * vec4, else they need 2 vec4s.
1125 if (type
->vector_elements
<= 2 || is_vs_input
)
1131 case GLSL_TYPE_ARRAY
:
1132 assert(type
->length
> 0);
1133 return attrib_type_size(type
->fields
.array
, is_vs_input
) * type
->length
;
1134 case GLSL_TYPE_STRUCT
:
1136 for (i
= 0; i
< type
->length
; i
++) {
1137 size
+= attrib_type_size(type
->fields
.structure
[i
].type
, is_vs_input
);
1140 case GLSL_TYPE_SAMPLER
:
1141 case GLSL_TYPE_IMAGE
:
1142 case GLSL_TYPE_SUBROUTINE
:
1143 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1147 case GLSL_TYPE_ATOMIC_UINT
:
1148 case GLSL_TYPE_INTERFACE
:
1149 case GLSL_TYPE_VOID
:
1150 case GLSL_TYPE_ERROR
:
1151 assert(!"Invalid type in type_size");
1158 type_size(const struct glsl_type
*type
)
1160 return attrib_type_size(type
, false);
1164 * If the given GLSL type is an array or matrix or a structure containing
1165 * an array/matrix member, return true. Else return false.
1167 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1168 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1169 * we have an array that might be indexed with a variable, we need to use
1170 * the later storage type.
1173 type_has_array_or_matrix(const glsl_type
*type
)
1175 if (type
->is_array() || type
->is_matrix())
1178 if (type
->is_record()) {
1179 for (unsigned i
= 0; i
< type
->length
; i
++) {
1180 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1191 * In the initial pass of codegen, we assign temporary numbers to
1192 * intermediate results. (not SSA -- variable assignments will reuse
1196 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1200 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1204 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1205 if (next_array
>= max_num_arrays
) {
1206 max_num_arrays
+= 32;
1207 array_sizes
= (unsigned*)
1208 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1211 src
.file
= PROGRAM_ARRAY
;
1212 src
.index
= next_array
<< 16 | 0x8000;
1213 array_sizes
[next_array
] = type_size(type
);
1217 src
.file
= PROGRAM_TEMPORARY
;
1218 src
.index
= next_temp
;
1219 next_temp
+= type_size(type
);
1222 if (type
->is_array() || type
->is_record()) {
1223 src
.swizzle
= SWIZZLE_NOOP
;
1225 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1232 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1235 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1236 if (entry
->var
== var
)
1244 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1246 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1247 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1249 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1250 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1253 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1255 const ir_state_slot
*const slots
= ir
->get_state_slots();
1256 assert(slots
!= NULL
);
1258 /* Check if this statevar's setup in the STATE file exactly
1259 * matches how we'll want to reference it as a
1260 * struct/array/whatever. If not, then we need to move it into
1261 * temporary storage and hope that it'll get copy-propagated
1264 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1265 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1270 variable_storage
*storage
;
1272 if (i
== ir
->get_num_state_slots()) {
1273 /* We'll set the index later. */
1274 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1275 this->variables
.push_tail(storage
);
1279 /* The variable_storage constructor allocates slots based on the size
1280 * of the type. However, this had better match the number of state
1281 * elements that we're going to copy into the new temporary.
1283 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1285 dst
= st_dst_reg(get_temp(ir
->type
));
1287 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1289 this->variables
.push_tail(storage
);
1293 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1294 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1295 (gl_state_index
*)slots
[i
].tokens
);
1297 if (storage
->file
== PROGRAM_STATE_VAR
) {
1298 if (storage
->index
== -1) {
1299 storage
->index
= index
;
1301 assert(index
== storage
->index
+ (int)i
);
1304 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1305 * the data being moved since MOV does not care about the type of
1306 * data it is moving, and we don't want to declare registers with
1307 * array or struct types.
1309 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1310 src
.swizzle
= slots
[i
].swizzle
;
1311 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1312 /* even a float takes up a whole vec4 reg in a struct/array. */
1317 if (storage
->file
== PROGRAM_TEMPORARY
&&
1318 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1319 fail_link(this->shader_program
,
1320 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1321 ir
->name
, dst
.index
- storage
->index
,
1322 type_size(ir
->type
));
1328 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1330 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1332 visit_exec_list(&ir
->body_instructions
, this);
1334 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1338 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1341 case ir_loop_jump::jump_break
:
1342 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1344 case ir_loop_jump::jump_continue
:
1345 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1352 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1359 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1361 /* Ignore function bodies other than main() -- we shouldn't see calls to
1362 * them since they should all be inlined before we get to glsl_to_tgsi.
1364 if (strcmp(ir
->name
, "main") == 0) {
1365 const ir_function_signature
*sig
;
1368 sig
= ir
->matching_signature(NULL
, &empty
, false);
1372 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1379 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1381 int nonmul_operand
= 1 - mul_operand
;
1383 st_dst_reg result_dst
;
1385 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1386 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1389 expr
->operands
[0]->accept(this);
1391 expr
->operands
[1]->accept(this);
1393 ir
->operands
[nonmul_operand
]->accept(this);
1396 this->result
= get_temp(ir
->type
);
1397 result_dst
= st_dst_reg(this->result
);
1398 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1399 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1405 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1407 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1408 * implemented using multiplication, and logical-or is implemented using
1409 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1410 * As result, the logical expression (a & !b) can be rewritten as:
1414 * - (a * 1) - (a * b)
1418 * This final expression can be implemented as a single MAD(a, -b, a)
1422 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1424 const int other_operand
= 1 - try_operand
;
1427 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1428 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1431 ir
->operands
[other_operand
]->accept(this);
1433 expr
->operands
[0]->accept(this);
1436 b
.negate
= ~b
.negate
;
1438 this->result
= get_temp(ir
->type
);
1439 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1445 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1446 st_src_reg
*reg
, int *num_reladdr
)
1448 if (!reg
->reladdr
&& !reg
->reladdr2
)
1451 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1452 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1454 if (*num_reladdr
!= 1) {
1455 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1457 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1465 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1467 unsigned int operand
;
1468 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1469 st_src_reg result_src
;
1470 st_dst_reg result_dst
;
1472 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1474 if (ir
->operation
== ir_binop_add
) {
1475 if (try_emit_mad(ir
, 1))
1477 if (try_emit_mad(ir
, 0))
1481 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1483 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1484 if (try_emit_mad_for_and_not(ir
, 1))
1486 if (try_emit_mad_for_and_not(ir
, 0))
1490 if (ir
->operation
== ir_quadop_vector
)
1491 assert(!"ir_quadop_vector should have been lowered");
1493 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1494 this->result
.file
= PROGRAM_UNDEFINED
;
1495 ir
->operands
[operand
]->accept(this);
1496 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1497 printf("Failed to get tree for expression operand:\n");
1498 ir
->operands
[operand
]->print();
1502 op
[operand
] = this->result
;
1504 /* Matrix expression operands should have been broken down to vector
1505 * operations already.
1507 assert(!ir
->operands
[operand
]->type
->is_matrix());
1510 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1511 if (ir
->operands
[1]) {
1512 vector_elements
= MAX2(vector_elements
,
1513 ir
->operands
[1]->type
->vector_elements
);
1516 this->result
.file
= PROGRAM_UNDEFINED
;
1518 /* Storage for our result. Ideally for an assignment we'd be using
1519 * the actual storage for the result here, instead.
1521 result_src
= get_temp(ir
->type
);
1522 /* convenience for the emit functions below. */
1523 result_dst
= st_dst_reg(result_src
);
1524 /* Limit writes to the channels that will be used by result_src later.
1525 * This does limit this temp's use as a temporary for multi-instruction
1528 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1530 switch (ir
->operation
) {
1531 case ir_unop_logic_not
:
1532 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1533 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1535 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1536 * older GPUs implement SEQ using multiple instructions (i915 uses two
1537 * SGE instructions and a MUL instruction). Since our logic values are
1538 * 0.0 and 1.0, 1-x also implements !x.
1540 op
[0].negate
= ~op
[0].negate
;
1541 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1545 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1546 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1547 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1548 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1550 op
[0].negate
= ~op
[0].negate
;
1554 case ir_unop_subroutine_to_int
:
1555 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1558 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1561 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1564 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1568 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1572 assert(!"not reached: should be handled by ir_explog_to_explog2");
1575 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1578 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1581 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1583 case ir_unop_saturate
: {
1584 glsl_to_tgsi_instruction
*inst
;
1585 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1586 inst
->saturate
= true;
1591 case ir_unop_dFdx_coarse
:
1592 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1594 case ir_unop_dFdx_fine
:
1595 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1598 case ir_unop_dFdy_coarse
:
1599 case ir_unop_dFdy_fine
:
1601 /* The X component contains 1 or -1 depending on whether the framebuffer
1602 * is a FBO or the window system buffer, respectively.
1603 * It is then multiplied with the source operand of DDY.
1605 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1606 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1608 unsigned transform_y_index
=
1609 _mesa_add_state_reference(this->prog
->Parameters
,
1612 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1614 glsl_type::vec4_type
);
1615 transform_y
.swizzle
= SWIZZLE_XXXX
;
1617 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1619 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1620 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1621 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1625 case ir_unop_frexp_sig
:
1626 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1629 case ir_unop_frexp_exp
:
1630 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1633 case ir_unop_noise
: {
1634 /* At some point, a motivated person could add a better
1635 * implementation of noise. Currently not even the nvidia
1636 * binary drivers do anything more than this. In any case, the
1637 * place to do this is in the GL state tracker, not the poor
1640 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1645 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1648 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1652 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1655 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1656 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1658 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1661 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1662 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1664 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1668 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1670 case ir_binop_greater
:
1671 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1673 case ir_binop_lequal
:
1674 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1676 case ir_binop_gequal
:
1677 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1679 case ir_binop_equal
:
1680 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1682 case ir_binop_nequal
:
1683 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1685 case ir_binop_all_equal
:
1686 /* "==" operator producing a scalar boolean. */
1687 if (ir
->operands
[0]->type
->is_vector() ||
1688 ir
->operands
[1]->type
->is_vector()) {
1689 st_src_reg temp
= get_temp(native_integers
?
1690 glsl_type::uvec4_type
:
1691 glsl_type::vec4_type
);
1693 if (native_integers
) {
1694 st_dst_reg temp_dst
= st_dst_reg(temp
);
1695 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1697 if (ir
->operands
[0]->type
->is_boolean() &&
1698 ir
->operands
[1]->as_constant() &&
1699 ir
->operands
[1]->as_constant()->is_one()) {
1700 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1702 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1705 /* Emit 1-3 AND operations to combine the SEQ results. */
1706 switch (ir
->operands
[0]->type
->vector_elements
) {
1710 temp_dst
.writemask
= WRITEMASK_Y
;
1711 temp1
.swizzle
= SWIZZLE_YYYY
;
1712 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1713 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1716 temp_dst
.writemask
= WRITEMASK_X
;
1717 temp1
.swizzle
= SWIZZLE_XXXX
;
1718 temp2
.swizzle
= SWIZZLE_YYYY
;
1719 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1720 temp_dst
.writemask
= WRITEMASK_Y
;
1721 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1722 temp2
.swizzle
= SWIZZLE_WWWW
;
1723 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1726 temp1
.swizzle
= SWIZZLE_XXXX
;
1727 temp2
.swizzle
= SWIZZLE_YYYY
;
1728 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1730 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1732 /* After the dot-product, the value will be an integer on the
1733 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1735 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1737 /* Negating the result of the dot-product gives values on the range
1738 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1739 * This is achieved using SGE.
1741 st_src_reg sge_src
= result_src
;
1742 sge_src
.negate
= ~sge_src
.negate
;
1743 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1746 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1749 case ir_binop_any_nequal
:
1750 /* "!=" operator producing a scalar boolean. */
1751 if (ir
->operands
[0]->type
->is_vector() ||
1752 ir
->operands
[1]->type
->is_vector()) {
1753 st_src_reg temp
= get_temp(native_integers
?
1754 glsl_type::uvec4_type
:
1755 glsl_type::vec4_type
);
1756 if (ir
->operands
[0]->type
->is_boolean() &&
1757 ir
->operands
[1]->as_constant() &&
1758 ir
->operands
[1]->as_constant()->is_zero()) {
1759 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1761 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1764 if (native_integers
) {
1765 st_dst_reg temp_dst
= st_dst_reg(temp
);
1766 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1768 /* Emit 1-3 OR operations to combine the SNE results. */
1769 switch (ir
->operands
[0]->type
->vector_elements
) {
1773 temp_dst
.writemask
= WRITEMASK_Y
;
1774 temp1
.swizzle
= SWIZZLE_YYYY
;
1775 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1776 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1779 temp_dst
.writemask
= WRITEMASK_X
;
1780 temp1
.swizzle
= SWIZZLE_XXXX
;
1781 temp2
.swizzle
= SWIZZLE_YYYY
;
1782 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1783 temp_dst
.writemask
= WRITEMASK_Y
;
1784 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1785 temp2
.swizzle
= SWIZZLE_WWWW
;
1786 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1789 temp1
.swizzle
= SWIZZLE_XXXX
;
1790 temp2
.swizzle
= SWIZZLE_YYYY
;
1791 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1793 /* After the dot-product, the value will be an integer on the
1794 * range [0,4]. Zero stays zero, and positive values become 1.0.
1796 glsl_to_tgsi_instruction
*const dp
=
1797 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1798 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1799 /* The clamping to [0,1] can be done for free in the fragment
1800 * shader with a saturate.
1802 dp
->saturate
= true;
1804 /* Negating the result of the dot-product gives values on the range
1805 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1806 * achieved using SLT.
1808 st_src_reg slt_src
= result_src
;
1809 slt_src
.negate
= ~slt_src
.negate
;
1810 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1814 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1818 case ir_binop_logic_xor
:
1819 if (native_integers
)
1820 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1822 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1825 case ir_binop_logic_or
: {
1826 if (native_integers
) {
1827 /* If integers are used as booleans, we can use an actual "or"
1830 assert(native_integers
);
1831 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1833 /* After the addition, the value will be an integer on the
1834 * range [0,2]. Zero stays zero, and positive values become 1.0.
1836 glsl_to_tgsi_instruction
*add
=
1837 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1838 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1839 /* The clamping to [0,1] can be done for free in the fragment
1840 * shader with a saturate if floats are being used as boolean values.
1842 add
->saturate
= true;
1844 /* Negating the result of the addition gives values on the range
1845 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1846 * is achieved using SLT.
1848 st_src_reg slt_src
= result_src
;
1849 slt_src
.negate
= ~slt_src
.negate
;
1850 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1856 case ir_binop_logic_and
:
1857 /* If native integers are disabled, the bool args are stored as float 0.0
1858 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1859 * actual AND opcode.
1861 if (native_integers
)
1862 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1864 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1868 assert(ir
->operands
[0]->type
->is_vector());
1869 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1870 emit_dp(ir
, result_dst
, op
[0], op
[1],
1871 ir
->operands
[0]->type
->vector_elements
);
1876 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1878 /* sqrt(x) = x * rsq(x). */
1879 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1880 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1881 /* For incoming channels <= 0, set the result to 0. */
1882 op
[0].negate
= ~op
[0].negate
;
1883 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1884 op
[0], result_src
, st_src_reg_for_float(0.0));
1888 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1891 if (native_integers
) {
1892 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1895 /* fallthrough to next case otherwise */
1897 if (native_integers
) {
1898 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1901 /* fallthrough to next case otherwise */
1904 /* Converting between signed and unsigned integers is a no-op. */
1908 if (native_integers
) {
1909 /* Booleans are stored as integers using ~0 for true and 0 for false.
1910 * GLSL requires that int(bool) return 1 for true and 0 for false.
1911 * This conversion is done with AND, but it could be done with NEG.
1913 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1915 /* Booleans and integers are both stored as floats when native
1916 * integers are disabled.
1922 if (native_integers
)
1923 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1925 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1928 if (native_integers
)
1929 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1931 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1933 case ir_unop_bitcast_f2i
:
1935 result_src
.type
= GLSL_TYPE_INT
;
1937 case ir_unop_bitcast_f2u
:
1939 result_src
.type
= GLSL_TYPE_UINT
;
1941 case ir_unop_bitcast_i2f
:
1942 case ir_unop_bitcast_u2f
:
1944 result_src
.type
= GLSL_TYPE_FLOAT
;
1947 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1950 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1953 if (native_integers
)
1954 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1956 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1959 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1962 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1965 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1967 case ir_unop_round_even
:
1968 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1971 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1975 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1978 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1981 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1984 case ir_unop_bit_not
:
1985 if (native_integers
) {
1986 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1990 if (native_integers
) {
1991 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1994 case ir_binop_lshift
:
1995 if (native_integers
) {
1996 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
1999 case ir_binop_rshift
:
2000 if (native_integers
) {
2001 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2004 case ir_binop_bit_and
:
2005 if (native_integers
) {
2006 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2009 case ir_binop_bit_xor
:
2010 if (native_integers
) {
2011 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2014 case ir_binop_bit_or
:
2015 if (native_integers
) {
2016 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2020 assert(!"GLSL 1.30 features unsupported");
2023 case ir_binop_ubo_load
: {
2024 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2025 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2026 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2027 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2028 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2031 cbuf
.type
= ir
->type
->base_type
;
2032 cbuf
.file
= PROGRAM_CONSTANT
;
2034 cbuf
.reladdr
= NULL
;
2037 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2039 if (const_offset_ir
) {
2040 /* Constant index into constant buffer */
2041 cbuf
.reladdr
= NULL
;
2042 cbuf
.index
= const_offset
/ 16;
2045 /* Relative/variable index into constant buffer */
2046 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2047 st_src_reg_for_int(4));
2048 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2049 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2052 if (const_uniform_block
) {
2053 /* Constant constant buffer */
2054 cbuf
.reladdr2
= NULL
;
2055 cbuf
.index2D
= const_block
;
2056 cbuf
.has_index2
= true;
2059 /* Relative/variable constant buffer */
2060 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2062 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2063 cbuf
.has_index2
= true;
2066 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2067 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2068 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2069 const_offset
% 16 / 8,
2070 const_offset
% 16 / 8,
2071 const_offset
% 16 / 8);
2073 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2074 const_offset
% 16 / 4,
2075 const_offset
% 16 / 4,
2076 const_offset
% 16 / 4);
2078 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2079 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2081 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2086 /* note: we have to reorder the three args here */
2087 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2090 if (this->ctx
->Const
.NativeIntegers
)
2091 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2093 op
[0].negate
= ~op
[0].negate
;
2094 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2097 case ir_triop_bitfield_extract
:
2098 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2100 case ir_quadop_bitfield_insert
:
2101 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2103 case ir_unop_bitfield_reverse
:
2104 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2106 case ir_unop_bit_count
:
2107 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2109 case ir_unop_find_msb
:
2110 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2112 case ir_unop_find_lsb
:
2113 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2115 case ir_binop_imul_high
:
2116 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2119 /* In theory, MAD is incorrect here. */
2121 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2123 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2125 case ir_unop_interpolate_at_centroid
:
2126 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2128 case ir_binop_interpolate_at_offset
:
2129 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2131 case ir_binop_interpolate_at_sample
:
2132 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2136 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2139 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2142 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2145 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2148 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2151 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2153 case ir_unop_unpack_double_2x32
:
2154 case ir_unop_pack_double_2x32
:
2155 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2158 case ir_binop_ldexp
:
2159 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2160 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2162 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2166 case ir_unop_pack_half_2x16
:
2167 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2169 case ir_unop_unpack_half_2x16
:
2170 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2173 case ir_unop_pack_snorm_2x16
:
2174 case ir_unop_pack_unorm_2x16
:
2175 case ir_unop_pack_snorm_4x8
:
2176 case ir_unop_pack_unorm_4x8
:
2178 case ir_unop_unpack_snorm_2x16
:
2179 case ir_unop_unpack_unorm_2x16
:
2180 case ir_unop_unpack_half_2x16_split_x
:
2181 case ir_unop_unpack_half_2x16_split_y
:
2182 case ir_unop_unpack_snorm_4x8
:
2183 case ir_unop_unpack_unorm_4x8
:
2185 case ir_binop_pack_half_2x16_split
:
2188 case ir_quadop_vector
:
2189 case ir_binop_vector_extract
:
2190 case ir_triop_vector_insert
:
2191 case ir_binop_carry
:
2192 case ir_binop_borrow
:
2193 case ir_unop_ssbo_unsized_array_length
:
2194 /* This operation is not supported, or should have already been handled.
2196 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2199 case ir_unop_get_buffer_size
:
2200 assert(!"Not implemented yet");
2204 this->result
= result_src
;
2209 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2215 /* Note that this is only swizzles in expressions, not those on the left
2216 * hand side of an assignment, which do write masking. See ir_assignment
2220 ir
->val
->accept(this);
2222 assert(src
.file
!= PROGRAM_UNDEFINED
);
2223 assert(ir
->type
->vector_elements
> 0);
2225 for (i
= 0; i
< 4; i
++) {
2226 if (i
< ir
->type
->vector_elements
) {
2229 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2232 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2235 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2238 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2242 /* If the type is smaller than a vec4, replicate the last
2245 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2249 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2254 /* Test if the variable is an array. Note that geometry and
2255 * tessellation shader inputs are outputs are always arrays (except
2256 * for patch inputs), so only the array element type is considered.
2259 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2261 const glsl_type
*type
= var
->type
;
2263 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2264 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2269 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2270 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2271 stage
== MESA_SHADER_TESS_CTRL
) &&
2273 if (!var
->type
->is_array())
2274 return false; /* a system value probably */
2276 type
= var
->type
->fields
.array
;
2280 return type
->is_array() || type
->is_matrix();
2284 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2286 variable_storage
*entry
= find_variable_storage(ir
->var
);
2287 ir_variable
*var
= ir
->var
;
2291 switch (var
->data
.mode
) {
2292 case ir_var_uniform
:
2293 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2294 var
->data
.location
);
2295 this->variables
.push_tail(entry
);
2297 case ir_var_shader_in
:
2298 /* The linker assigns locations for varyings and attributes,
2299 * including deprecated builtins (like gl_Color), user-assign
2300 * generic attributes (glBindVertexLocation), and
2301 * user-defined varyings.
2303 assert(var
->data
.location
!= -1);
2305 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2306 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2308 decl
->mesa_index
= var
->data
.location
;
2309 decl
->array_id
= num_input_arrays
+ 1;
2311 decl
->array_size
= type_size(var
->type
->fields
.array
);
2312 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2314 decl
->array_size
= type_size(var
->type
);
2315 decl
->array_type
= var
->type
->without_array()->base_type
;
2319 entry
= new(mem_ctx
) variable_storage(var
,
2325 entry
= new(mem_ctx
) variable_storage(var
,
2327 var
->data
.location
);
2329 this->variables
.push_tail(entry
);
2331 case ir_var_shader_out
:
2332 assert(var
->data
.location
!= -1);
2334 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2335 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2337 decl
->mesa_index
= var
->data
.location
;
2338 decl
->array_id
= num_output_arrays
+ 1;
2340 decl
->array_size
= type_size(var
->type
->fields
.array
);
2341 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2343 decl
->array_size
= type_size(var
->type
);
2344 decl
->array_type
= var
->type
->without_array()->base_type
;
2346 num_output_arrays
++;
2348 entry
= new(mem_ctx
) variable_storage(var
,
2354 entry
= new(mem_ctx
) variable_storage(var
,
2359 this->variables
.push_tail(entry
);
2361 case ir_var_system_value
:
2362 entry
= new(mem_ctx
) variable_storage(var
,
2363 PROGRAM_SYSTEM_VALUE
,
2364 var
->data
.location
);
2367 case ir_var_temporary
:
2368 st_src_reg src
= get_temp(var
->type
);
2370 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2371 this->variables
.push_tail(entry
);
2377 printf("Failed to make storage for %s\n", var
->name
);
2382 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2383 this->result
.array_id
= entry
->array_id
;
2384 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2385 this->result
.is_double_vertex_input
= true;
2386 if (!native_integers
)
2387 this->result
.type
= GLSL_TYPE_FLOAT
;
2391 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2392 GLbitfield64 usage_mask
,
2393 GLbitfield64 double_usage_mask
,
2394 GLbitfield patch_usage_mask
)
2398 /* Fix array declarations by removing unused array elements at both ends
2399 * of the arrays. For example, mat4[3] where only mat[1] is used.
2401 for (i
= 0; i
< count
; i
++) {
2402 struct array_decl
*decl
= &arrays
[i
];
2404 /* Shrink the beginning. */
2405 for (j
= 0; j
< decl
->array_size
; j
++) {
2406 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2407 if (patch_usage_mask
&
2408 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2412 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2414 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2423 /* Shrink the end. */
2424 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2425 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2426 if (patch_usage_mask
&
2427 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2431 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2433 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2443 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2447 int element_size
= type_size(ir
->type
);
2450 index
= ir
->array_index
->constant_expression_value();
2452 ir
->array
->accept(this);
2455 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2456 switch (this->prog
->Target
) {
2457 case GL_TESS_CONTROL_PROGRAM_NV
:
2458 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2459 !ir
->variable_referenced()->data
.patch
;
2461 case GL_TESS_EVALUATION_PROGRAM_NV
:
2462 is_2D
= src
.file
== PROGRAM_INPUT
&&
2463 !ir
->variable_referenced()->data
.patch
;
2465 case GL_GEOMETRY_PROGRAM_NV
:
2466 is_2D
= src
.file
== PROGRAM_INPUT
;
2476 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2477 src
.file
== PROGRAM_INPUT
)
2478 element_size
= attrib_type_size(ir
->type
, true);
2480 src
.index2D
= index
->value
.i
[0];
2481 src
.has_index2
= true;
2483 src
.index
+= index
->value
.i
[0] * element_size
;
2485 /* Variable index array dereference. It eats the "vec4" of the
2486 * base of the array and an index that offsets the TGSI register
2489 ir
->array_index
->accept(this);
2491 st_src_reg index_reg
;
2493 if (element_size
== 1) {
2494 index_reg
= this->result
;
2496 index_reg
= get_temp(native_integers
?
2497 glsl_type::int_type
: glsl_type::float_type
);
2499 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2500 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2503 /* If there was already a relative address register involved, add the
2504 * new and the old together to get the new offset.
2506 if (!is_2D
&& src
.reladdr
!= NULL
) {
2507 st_src_reg accum_reg
= get_temp(native_integers
?
2508 glsl_type::int_type
: glsl_type::float_type
);
2510 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2511 index_reg
, *src
.reladdr
);
2513 index_reg
= accum_reg
;
2517 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2518 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2520 src
.has_index2
= true;
2522 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2523 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2527 /* If the type is smaller than a vec4, replicate the last channel out. */
2528 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2529 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2531 src
.swizzle
= SWIZZLE_NOOP
;
2533 /* Change the register type to the element type of the array. */
2534 src
.type
= ir
->type
->base_type
;
2540 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2543 const glsl_type
*struct_type
= ir
->record
->type
;
2546 ir
->record
->accept(this);
2548 for (i
= 0; i
< struct_type
->length
; i
++) {
2549 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2551 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2554 /* If the type is smaller than a vec4, replicate the last channel out. */
2555 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2556 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2558 this->result
.swizzle
= SWIZZLE_NOOP
;
2560 this->result
.index
+= offset
;
2561 this->result
.type
= ir
->type
->base_type
;
2565 * We want to be careful in assignment setup to hit the actual storage
2566 * instead of potentially using a temporary like we might with the
2567 * ir_dereference handler.
2570 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2572 /* The LHS must be a dereference. If the LHS is a variable indexed array
2573 * access of a vector, it must be separated into a series conditional moves
2574 * before reaching this point (see ir_vec_index_to_cond_assign).
2576 assert(ir
->as_dereference());
2577 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2579 assert(!deref_array
->array
->type
->is_vector());
2582 /* Use the rvalue deref handler for the most part. We'll ignore
2583 * swizzles in it and write swizzles using writemask, though.
2586 return st_dst_reg(v
->result
);
2590 * Process the condition of a conditional assignment
2592 * Examines the condition of a conditional assignment to generate the optimal
2593 * first operand of a \c CMP instruction. If the condition is a relational
2594 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2595 * used as the source for the \c CMP instruction. Otherwise the comparison
2596 * is processed to a boolean result, and the boolean result is used as the
2597 * operand to the CMP instruction.
2600 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2602 ir_rvalue
*src_ir
= ir
;
2604 bool switch_order
= false;
2606 ir_expression
*const expr
= ir
->as_expression();
2608 if (native_integers
) {
2609 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2610 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2611 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2612 type
== GLSL_TYPE_BOOL
) {
2613 if (expr
->operation
== ir_binop_equal
) {
2614 if (expr
->operands
[0]->is_zero()) {
2615 src_ir
= expr
->operands
[1];
2616 switch_order
= true;
2618 else if (expr
->operands
[1]->is_zero()) {
2619 src_ir
= expr
->operands
[0];
2620 switch_order
= true;
2623 else if (expr
->operation
== ir_binop_nequal
) {
2624 if (expr
->operands
[0]->is_zero()) {
2625 src_ir
= expr
->operands
[1];
2627 else if (expr
->operands
[1]->is_zero()) {
2628 src_ir
= expr
->operands
[0];
2634 src_ir
->accept(this);
2635 return switch_order
;
2638 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2639 bool zero_on_left
= false;
2641 if (expr
->operands
[0]->is_zero()) {
2642 src_ir
= expr
->operands
[1];
2643 zero_on_left
= true;
2644 } else if (expr
->operands
[1]->is_zero()) {
2645 src_ir
= expr
->operands
[0];
2646 zero_on_left
= false;
2650 * (a < 0) T F F ( a < 0) T F F
2651 * (0 < a) F F T (-a < 0) F F T
2652 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2653 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2654 * (a > 0) F F T (-a < 0) F F T
2655 * (0 > a) T F F ( a < 0) T F F
2656 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2657 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2659 * Note that exchanging the order of 0 and 'a' in the comparison simply
2660 * means that the value of 'a' should be negated.
2663 switch (expr
->operation
) {
2665 switch_order
= false;
2666 negate
= zero_on_left
;
2669 case ir_binop_greater
:
2670 switch_order
= false;
2671 negate
= !zero_on_left
;
2674 case ir_binop_lequal
:
2675 switch_order
= true;
2676 negate
= !zero_on_left
;
2679 case ir_binop_gequal
:
2680 switch_order
= true;
2681 negate
= zero_on_left
;
2685 /* This isn't the right kind of comparison afterall, so make sure
2686 * the whole condition is visited.
2694 src_ir
->accept(this);
2696 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2697 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2698 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2699 * computing the condition.
2702 this->result
.negate
= ~this->result
.negate
;
2704 return switch_order
;
2708 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2709 st_dst_reg
*l
, st_src_reg
*r
,
2710 st_src_reg
*cond
, bool cond_swap
)
2712 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2713 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2714 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2720 if (type
->is_array()) {
2721 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2722 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2727 if (type
->is_matrix()) {
2728 const struct glsl_type
*vec_type
;
2730 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2731 type
->vector_elements
, 1);
2733 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2734 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2739 assert(type
->is_scalar() || type
->is_vector());
2741 r
->type
= type
->base_type
;
2743 st_src_reg l_src
= st_src_reg(*l
);
2744 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2746 if (native_integers
) {
2747 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2748 cond_swap
? l_src
: *r
,
2749 cond_swap
? *r
: l_src
);
2751 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2752 cond_swap
? l_src
: *r
,
2753 cond_swap
? *r
: l_src
);
2756 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2760 if (type
->is_dual_slot_double()) {
2762 if (r
->is_double_vertex_input
== false)
2768 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2773 ir
->rhs
->accept(this);
2776 l
= get_assignment_lhs(ir
->lhs
, this);
2778 /* FINISHME: This should really set to the correct maximal writemask for each
2779 * FINISHME: component written (in the loops below). This case can only
2780 * FINISHME: occur for matrices, arrays, and structures.
2782 if (ir
->write_mask
== 0) {
2783 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2785 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2786 if (ir
->lhs
->type
->without_array()->is_double()) {
2787 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2789 l
.writemask
= WRITEMASK_X
;
2792 l
.writemask
= WRITEMASK_XY
;
2795 l
.writemask
= WRITEMASK_XYZ
;
2798 l
.writemask
= WRITEMASK_XYZW
;
2802 l
.writemask
= WRITEMASK_XYZW
;
2804 } else if (ir
->lhs
->type
->is_scalar() &&
2805 !ir
->lhs
->type
->is_double() &&
2806 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2807 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2808 * FINISHME: W component of fragment shader output zero, work correctly.
2810 l
.writemask
= WRITEMASK_XYZW
;
2813 int first_enabled_chan
= 0;
2816 l
.writemask
= ir
->write_mask
;
2818 for (int i
= 0; i
< 4; i
++) {
2819 if (l
.writemask
& (1 << i
)) {
2820 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2825 /* Swizzle a small RHS vector into the channels being written.
2827 * glsl ir treats write_mask as dictating how many channels are
2828 * present on the RHS while TGSI treats write_mask as just
2829 * showing which channels of the vec4 RHS get written.
2831 for (int i
= 0; i
< 4; i
++) {
2832 if (l
.writemask
& (1 << i
))
2833 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2835 swizzles
[i
] = first_enabled_chan
;
2837 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2838 swizzles
[2], swizzles
[3]);
2841 assert(l
.file
!= PROGRAM_UNDEFINED
);
2842 assert(r
.file
!= PROGRAM_UNDEFINED
);
2844 if (ir
->condition
) {
2845 const bool switch_order
= this->process_move_condition(ir
->condition
);
2846 st_src_reg condition
= this->result
;
2848 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2849 } else if (ir
->rhs
->as_expression() &&
2850 this->instructions
.get_tail() &&
2851 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2852 type_size(ir
->lhs
->type
) == 1 &&
2853 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2854 /* To avoid emitting an extra MOV when assigning an expression to a
2855 * variable, emit the last instruction of the expression again, but
2856 * replace the destination register with the target of the assignment.
2857 * Dead code elimination will remove the original instruction.
2859 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2860 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2861 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2862 new_inst
->saturate
= inst
->saturate
;
2863 inst
->dead_mask
= inst
->dst
[0].writemask
;
2865 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2871 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2874 GLdouble stack_vals
[4] = { 0 };
2875 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2876 GLenum gl_type
= GL_NONE
;
2878 static int in_array
= 0;
2879 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2881 /* Unfortunately, 4 floats is all we can get into
2882 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2883 * aggregate constant and move each constant value into it. If we
2884 * get lucky, copy propagation will eliminate the extra moves.
2886 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2887 st_src_reg temp_base
= get_temp(ir
->type
);
2888 st_dst_reg temp
= st_dst_reg(temp_base
);
2890 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2891 int size
= type_size(field_value
->type
);
2895 field_value
->accept(this);
2898 for (i
= 0; i
< (unsigned int)size
; i
++) {
2899 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2905 this->result
= temp_base
;
2909 if (ir
->type
->is_array()) {
2910 st_src_reg temp_base
= get_temp(ir
->type
);
2911 st_dst_reg temp
= st_dst_reg(temp_base
);
2912 int size
= type_size(ir
->type
->fields
.array
);
2917 for (i
= 0; i
< ir
->type
->length
; i
++) {
2918 ir
->array_elements
[i
]->accept(this);
2920 for (int j
= 0; j
< size
; j
++) {
2921 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2927 this->result
= temp_base
;
2932 if (ir
->type
->is_matrix()) {
2933 st_src_reg mat
= get_temp(ir
->type
);
2934 st_dst_reg mat_column
= st_dst_reg(mat
);
2936 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2937 switch (ir
->type
->base_type
) {
2938 case GLSL_TYPE_FLOAT
:
2939 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2941 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2942 src
.index
= add_constant(file
,
2944 ir
->type
->vector_elements
,
2947 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2949 case GLSL_TYPE_DOUBLE
:
2950 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
2951 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2952 src
.index
= add_constant(file
,
2954 ir
->type
->vector_elements
,
2957 if (ir
->type
->vector_elements
>= 2) {
2958 mat_column
.writemask
= WRITEMASK_XY
;
2959 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
2960 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2962 mat_column
.writemask
= WRITEMASK_X
;
2963 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2964 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2967 if (ir
->type
->vector_elements
> 2) {
2968 if (ir
->type
->vector_elements
== 4) {
2969 mat_column
.writemask
= WRITEMASK_ZW
;
2970 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
2971 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2973 mat_column
.writemask
= WRITEMASK_Z
;
2974 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
2975 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2976 mat_column
.writemask
= WRITEMASK_XYZW
;
2977 src
.swizzle
= SWIZZLE_XYZW
;
2983 unreachable("Illegal matrix constant type.\n");
2992 switch (ir
->type
->base_type
) {
2993 case GLSL_TYPE_FLOAT
:
2995 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2996 values
[i
].f
= ir
->value
.f
[i
];
2999 case GLSL_TYPE_DOUBLE
:
3000 gl_type
= GL_DOUBLE
;
3001 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3002 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3003 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3006 case GLSL_TYPE_UINT
:
3007 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3008 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3009 if (native_integers
)
3010 values
[i
].u
= ir
->value
.u
[i
];
3012 values
[i
].f
= ir
->value
.u
[i
];
3016 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3017 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3018 if (native_integers
)
3019 values
[i
].i
= ir
->value
.i
[i
];
3021 values
[i
].f
= ir
->value
.i
[i
];
3024 case GLSL_TYPE_BOOL
:
3025 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3026 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3027 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3031 assert(!"Non-float/uint/int/bool constant");
3034 this->result
= st_src_reg(file
, -1, ir
->type
);
3035 this->result
.index
= add_constant(file
,
3037 ir
->type
->vector_elements
,
3039 &this->result
.swizzle
);
3043 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3045 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3046 if (entry
->sig
== sig
)
3050 entry
= ralloc(mem_ctx
, function_entry
);
3052 entry
->sig_id
= this->next_signature_id
++;
3053 entry
->bgn_inst
= NULL
;
3055 /* Allocate storage for all the parameters. */
3056 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3057 variable_storage
*storage
;
3059 storage
= find_variable_storage(param
);
3062 st_src_reg src
= get_temp(param
->type
);
3064 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3065 this->variables
.push_tail(storage
);
3068 if (!sig
->return_type
->is_void()) {
3069 entry
->return_reg
= get_temp(sig
->return_type
);
3071 entry
->return_reg
= undef_src
;
3074 this->function_signatures
.push_tail(entry
);
3079 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3081 glsl_to_tgsi_instruction
*call_inst
;
3082 ir_function_signature
*sig
= ir
->callee
;
3083 function_entry
*entry
= get_function_signature(sig
);
3086 /* Process in parameters. */
3087 foreach_two_lists(formal_node
, &sig
->parameters
,
3088 actual_node
, &ir
->actual_parameters
) {
3089 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3090 ir_variable
*param
= (ir_variable
*) formal_node
;
3092 if (param
->data
.mode
== ir_var_function_in
||
3093 param
->data
.mode
== ir_var_function_inout
) {
3094 variable_storage
*storage
= find_variable_storage(param
);
3097 param_rval
->accept(this);
3098 st_src_reg r
= this->result
;
3101 l
.file
= storage
->file
;
3102 l
.index
= storage
->index
;
3104 l
.writemask
= WRITEMASK_XYZW
;
3105 l
.cond_mask
= COND_TR
;
3107 for (i
= 0; i
< type_size(param
->type
); i
++) {
3108 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3115 /* Emit call instruction */
3116 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3117 call_inst
->function
= entry
;
3119 /* Process out parameters. */
3120 foreach_two_lists(formal_node
, &sig
->parameters
,
3121 actual_node
, &ir
->actual_parameters
) {
3122 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3123 ir_variable
*param
= (ir_variable
*) formal_node
;
3125 if (param
->data
.mode
== ir_var_function_out
||
3126 param
->data
.mode
== ir_var_function_inout
) {
3127 variable_storage
*storage
= find_variable_storage(param
);
3131 r
.file
= storage
->file
;
3132 r
.index
= storage
->index
;
3134 r
.swizzle
= SWIZZLE_NOOP
;
3137 param_rval
->accept(this);
3138 st_dst_reg l
= st_dst_reg(this->result
);
3140 for (i
= 0; i
< type_size(param
->type
); i
++) {
3141 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3148 /* Process return value. */
3149 this->result
= entry
->return_reg
;
3153 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3155 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3156 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3157 st_src_reg levels_src
;
3158 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3159 glsl_to_tgsi_instruction
*inst
= NULL
;
3160 unsigned opcode
= TGSI_OPCODE_NOP
;
3161 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3162 ir_rvalue
*sampler_index
=
3163 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
3164 bool is_cube_array
= false;
3167 /* if we are a cube array sampler */
3168 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3169 sampler_type
->sampler_array
)) {
3170 is_cube_array
= true;
3173 if (ir
->coordinate
) {
3174 ir
->coordinate
->accept(this);
3176 /* Put our coords in a temp. We'll need to modify them for shadow,
3177 * projection, or LOD, so the only case we'd use it as is is if
3178 * we're doing plain old texturing. The optimization passes on
3179 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3181 coord
= get_temp(glsl_type::vec4_type
);
3182 coord_dst
= st_dst_reg(coord
);
3183 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3184 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3187 if (ir
->projector
) {
3188 ir
->projector
->accept(this);
3189 projector
= this->result
;
3192 /* Storage for our result. Ideally for an assignment we'd be using
3193 * the actual storage for the result here, instead.
3195 result_src
= get_temp(ir
->type
);
3196 result_dst
= st_dst_reg(result_src
);
3200 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3202 ir
->offset
->accept(this);
3203 offset
[0] = this->result
;
3207 if (is_cube_array
||
3208 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3209 opcode
= TGSI_OPCODE_TXB2
;
3212 opcode
= TGSI_OPCODE_TXB
;
3214 ir
->lod_info
.bias
->accept(this);
3215 lod_info
= this->result
;
3217 ir
->offset
->accept(this);
3218 offset
[0] = this->result
;
3222 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3223 ir
->lod_info
.lod
->accept(this);
3224 lod_info
= this->result
;
3226 ir
->offset
->accept(this);
3227 offset
[0] = this->result
;
3231 opcode
= TGSI_OPCODE_TXD
;
3232 ir
->lod_info
.grad
.dPdx
->accept(this);
3234 ir
->lod_info
.grad
.dPdy
->accept(this);
3237 ir
->offset
->accept(this);
3238 offset
[0] = this->result
;
3242 opcode
= TGSI_OPCODE_TXQ
;
3243 ir
->lod_info
.lod
->accept(this);
3244 lod_info
= this->result
;
3246 case ir_query_levels
:
3247 opcode
= TGSI_OPCODE_TXQ
;
3248 lod_info
= undef_src
;
3249 levels_src
= get_temp(ir
->type
);
3252 opcode
= TGSI_OPCODE_TXF
;
3253 ir
->lod_info
.lod
->accept(this);
3254 lod_info
= this->result
;
3256 ir
->offset
->accept(this);
3257 offset
[0] = this->result
;
3261 opcode
= TGSI_OPCODE_TXF
;
3262 ir
->lod_info
.sample_index
->accept(this);
3263 sample_index
= this->result
;
3266 opcode
= TGSI_OPCODE_TG4
;
3267 ir
->lod_info
.component
->accept(this);
3268 component
= this->result
;
3270 ir
->offset
->accept(this);
3271 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3272 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3273 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3274 offset
[i
] = this->result
;
3275 offset
[i
].index
+= i
* type_size(elt_type
);
3276 offset
[i
].type
= elt_type
->base_type
;
3277 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3280 offset
[0] = this->result
;
3285 opcode
= TGSI_OPCODE_LODQ
;
3287 case ir_texture_samples
:
3288 opcode
= TGSI_OPCODE_TXQS
;
3290 case ir_samples_identical
:
3291 unreachable("Unexpected ir_samples_identical opcode");
3294 if (ir
->projector
) {
3295 if (opcode
== TGSI_OPCODE_TEX
) {
3296 /* Slot the projector in as the last component of the coord. */
3297 coord_dst
.writemask
= WRITEMASK_W
;
3298 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3299 coord_dst
.writemask
= WRITEMASK_XYZW
;
3300 opcode
= TGSI_OPCODE_TXP
;
3302 st_src_reg coord_w
= coord
;
3303 coord_w
.swizzle
= SWIZZLE_WWWW
;
3305 /* For the other TEX opcodes there's no projective version
3306 * since the last slot is taken up by LOD info. Do the
3307 * projective divide now.
3309 coord_dst
.writemask
= WRITEMASK_W
;
3310 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3312 /* In the case where we have to project the coordinates "by hand,"
3313 * the shadow comparator value must also be projected.
3315 st_src_reg tmp_src
= coord
;
3316 if (ir
->shadow_comparitor
) {
3317 /* Slot the shadow value in as the second to last component of the
3320 ir
->shadow_comparitor
->accept(this);
3322 tmp_src
= get_temp(glsl_type::vec4_type
);
3323 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3325 /* Projective division not allowed for array samplers. */
3326 assert(!sampler_type
->sampler_array
);
3328 tmp_dst
.writemask
= WRITEMASK_Z
;
3329 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3331 tmp_dst
.writemask
= WRITEMASK_XY
;
3332 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
3335 coord_dst
.writemask
= WRITEMASK_XYZ
;
3336 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
3338 coord_dst
.writemask
= WRITEMASK_XYZW
;
3339 coord
.swizzle
= SWIZZLE_XYZW
;
3343 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
3344 * comparator was put in the correct place (and projected) by the code,
3345 * above, that handles by-hand projection.
3347 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
3348 /* Slot the shadow value in as the second to last component of the
3351 ir
->shadow_comparitor
->accept(this);
3353 if (is_cube_array
) {
3354 cube_sc
= get_temp(glsl_type::float_type
);
3355 cube_sc_dst
= st_dst_reg(cube_sc
);
3356 cube_sc_dst
.writemask
= WRITEMASK_X
;
3357 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
3358 cube_sc_dst
.writemask
= WRITEMASK_X
;
3361 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
3362 sampler_type
->sampler_array
) ||
3363 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3364 coord_dst
.writemask
= WRITEMASK_W
;
3366 coord_dst
.writemask
= WRITEMASK_Z
;
3368 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3369 coord_dst
.writemask
= WRITEMASK_XYZW
;
3373 if (ir
->op
== ir_txf_ms
) {
3374 coord_dst
.writemask
= WRITEMASK_W
;
3375 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
3376 coord_dst
.writemask
= WRITEMASK_XYZW
;
3377 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
3378 opcode
== TGSI_OPCODE_TXF
) {
3379 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
3380 coord_dst
.writemask
= WRITEMASK_W
;
3381 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
3382 coord_dst
.writemask
= WRITEMASK_XYZW
;
3385 if (sampler_index
) {
3386 sampler_index
->accept(this);
3387 emit_arl(ir
, sampler_reladdr
, this->result
);
3390 if (opcode
== TGSI_OPCODE_TXD
)
3391 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
3392 else if (opcode
== TGSI_OPCODE_TXQ
) {
3393 if (ir
->op
== ir_query_levels
) {
3394 /* the level is stored in W */
3395 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
3396 result_dst
.writemask
= WRITEMASK_X
;
3397 levels_src
.swizzle
= SWIZZLE_WWWW
;
3398 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
3400 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
3401 } else if (opcode
== TGSI_OPCODE_TXQS
) {
3402 inst
= emit_asm(ir
, opcode
, result_dst
);
3403 } else if (opcode
== TGSI_OPCODE_TXF
) {
3404 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3405 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
3406 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
3407 } else if (opcode
== TGSI_OPCODE_TEX2
) {
3408 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3409 } else if (opcode
== TGSI_OPCODE_TG4
) {
3410 if (is_cube_array
&& ir
->shadow_comparitor
) {
3411 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3413 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
3416 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3418 if (ir
->shadow_comparitor
)
3419 inst
->tex_shadow
= GL_TRUE
;
3421 inst
->sampler
.index
= _mesa_get_sampler_uniform_value(ir
->sampler
,
3422 this->shader_program
,
3424 if (sampler_index
) {
3425 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3426 memcpy(inst
->sampler
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3427 inst
->sampler_array_size
=
3428 ir
->sampler
->as_dereference_array()->array
->type
->array_size();
3430 inst
->sampler_array_size
= 1;
3434 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
3435 inst
->tex_offsets
[i
] = offset
[i
];
3436 inst
->tex_offset_num_offset
= i
;
3439 switch (sampler_type
->sampler_dimensionality
) {
3440 case GLSL_SAMPLER_DIM_1D
:
3441 inst
->tex_target
= (sampler_type
->sampler_array
)
3442 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3444 case GLSL_SAMPLER_DIM_2D
:
3445 inst
->tex_target
= (sampler_type
->sampler_array
)
3446 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3448 case GLSL_SAMPLER_DIM_3D
:
3449 inst
->tex_target
= TEXTURE_3D_INDEX
;
3451 case GLSL_SAMPLER_DIM_CUBE
:
3452 inst
->tex_target
= (sampler_type
->sampler_array
)
3453 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3455 case GLSL_SAMPLER_DIM_RECT
:
3456 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3458 case GLSL_SAMPLER_DIM_BUF
:
3459 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3461 case GLSL_SAMPLER_DIM_EXTERNAL
:
3462 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3464 case GLSL_SAMPLER_DIM_MS
:
3465 inst
->tex_target
= (sampler_type
->sampler_array
)
3466 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3469 assert(!"Should not get here.");
3472 inst
->tex_type
= ir
->type
->base_type
;
3474 this->result
= result_src
;
3478 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
3480 if (ir
->get_value()) {
3484 assert(current_function
);
3486 ir
->get_value()->accept(this);
3487 st_src_reg r
= this->result
;
3489 l
= st_dst_reg(current_function
->return_reg
);
3491 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
3492 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3498 emit_asm(ir
, TGSI_OPCODE_RET
);
3502 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
3504 if (ir
->condition
) {
3505 ir
->condition
->accept(this);
3506 st_src_reg condition
= this->result
;
3508 /* Convert the bool condition to a float so we can negate. */
3509 if (native_integers
) {
3510 st_src_reg temp
= get_temp(ir
->condition
->type
);
3511 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
3512 condition
, st_src_reg_for_float(1.0));
3516 condition
.negate
= ~condition
.negate
;
3517 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
3519 /* unconditional kil */
3520 emit_asm(ir
, TGSI_OPCODE_KILL
);
3525 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
3528 glsl_to_tgsi_instruction
*if_inst
;
3530 ir
->condition
->accept(this);
3531 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3533 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
3535 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
3537 this->instructions
.push_tail(if_inst
);
3539 visit_exec_list(&ir
->then_instructions
, this);
3541 if (!ir
->else_instructions
.is_empty()) {
3542 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
3543 visit_exec_list(&ir
->else_instructions
, this);
3546 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
3551 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
3553 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3555 ir
->stream
->accept(this);
3556 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
3560 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
3562 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3564 ir
->stream
->accept(this);
3565 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
3569 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
3571 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
3572 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
3574 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
3577 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
3579 result
.file
= PROGRAM_UNDEFINED
;
3584 num_input_arrays
= 0;
3585 num_output_arrays
= 0;
3586 next_signature_id
= 1;
3588 current_function
= NULL
;
3589 num_address_regs
= 0;
3591 indirect_addr_consts
= false;
3592 wpos_transform_const
= -1;
3594 native_integers
= false;
3595 mem_ctx
= ralloc_context(NULL
);
3598 shader_program
= NULL
;
3605 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
3608 ralloc_free(mem_ctx
);
3611 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
3618 * Count resources used by the given gpu program (number of texture
3622 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
3624 v
->samplers_used
= 0;
3626 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
3627 if (inst
->info
->is_tex
) {
3628 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
3629 unsigned idx
= inst
->sampler
.index
+ i
;
3630 v
->samplers_used
|= 1 << idx
;
3632 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
3633 v
->sampler_types
[idx
] = inst
->tex_type
;
3634 v
->sampler_targets
[idx
] =
3635 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
3637 if (inst
->tex_shadow
) {
3638 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
3643 prog
->SamplersUsed
= v
->samplers_used
;
3645 if (v
->shader_program
!= NULL
)
3646 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
3650 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
3651 * are read from the given src in this instruction
3654 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
3656 int read_mask
= 0, comp
;
3658 /* Now, given the src swizzle and the written channels, find which
3659 * components are actually read
3661 for (comp
= 0; comp
< 4; ++comp
) {
3662 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
3664 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
3665 read_mask
|= 1 << coord
;
3672 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
3673 * instruction is the first instruction to write to register T0. There are
3674 * several lowering passes done in GLSL IR (e.g. branches and
3675 * relative addressing) that create a large number of conditional assignments
3676 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
3678 * Here is why this conversion is safe:
3679 * CMP T0, T1 T2 T0 can be expanded to:
3685 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
3686 * as the original program. If (T1 < 0.0) evaluates to false, executing
3687 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
3688 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
3689 * because any instruction that was going to read from T0 after this was going
3690 * to read a garbage value anyway.
3693 glsl_to_tgsi_visitor::simplify_cmp(void)
3695 int tempWritesSize
= 0;
3696 unsigned *tempWrites
= NULL
;
3697 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
3699 memset(outputWrites
, 0, sizeof(outputWrites
));
3701 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3702 unsigned prevWriteMask
= 0;
3704 /* Give up if we encounter relative addressing or flow control. */
3705 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
3706 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
3707 tgsi_get_opcode_info(inst
->op
)->is_branch
||
3708 inst
->op
== TGSI_OPCODE_BGNSUB
||
3709 inst
->op
== TGSI_OPCODE_CONT
||
3710 inst
->op
== TGSI_OPCODE_END
||
3711 inst
->op
== TGSI_OPCODE_ENDSUB
||
3712 inst
->op
== TGSI_OPCODE_RET
) {
3716 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
3717 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
3718 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
3719 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3720 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
3721 if (inst
->dst
[0].index
>= tempWritesSize
) {
3722 const int inc
= 4096;
3724 tempWrites
= (unsigned*)
3726 (tempWritesSize
+ inc
) * sizeof(unsigned));
3730 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
3731 tempWritesSize
+= inc
;
3734 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
3735 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3739 /* For a CMP to be considered a conditional write, the destination
3740 * register and source register two must be the same. */
3741 if (inst
->op
== TGSI_OPCODE_CMP
3742 && !(inst
->dst
[0].writemask
& prevWriteMask
)
3743 && inst
->src
[2].file
== inst
->dst
[0].file
3744 && inst
->src
[2].index
== inst
->dst
[0].index
3745 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
3747 inst
->op
= TGSI_OPCODE_MOV
;
3748 inst
->src
[0] = inst
->src
[1];
3755 /* Replaces all references to a temporary register index with another index. */
3757 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
3759 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3762 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3763 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3764 for (k
= 0; k
< num_renames
; k
++)
3765 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
3766 inst
->src
[j
].index
= renames
[k
].new_reg
;
3769 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3770 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3771 for (k
= 0; k
< num_renames
; k
++)
3772 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
3773 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
3776 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3777 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3778 for (k
= 0; k
< num_renames
; k
++)
3779 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
3780 inst
->dst
[j
].index
= renames
[k
].new_reg
;
3786 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
3788 int depth
= 0; /* loop depth */
3789 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3792 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3793 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3794 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
3795 if (first_reads
[inst
->src
[j
].index
] == -1)
3796 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3799 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3800 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
3801 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
3802 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3805 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3808 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3818 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
3820 int depth
= 0; /* loop depth */
3821 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3824 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3825 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3826 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3827 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
3829 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3830 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3831 if (first_writes
[inst
->dst
[j
].index
] == -1)
3832 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3834 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3835 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3836 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
3838 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3841 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3844 for (k
= 0; k
< this->next_temp
; k
++) {
3845 if (last_reads
[k
] == -2) {
3857 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
3859 int depth
= 0; /* loop depth */
3863 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3864 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3865 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3866 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
3869 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3871 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3873 for (k
= 0; k
< this->next_temp
; k
++) {
3874 if (last_writes
[k
] == -2) {
3885 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
3886 * channels for copy propagation and updates following instructions to
3887 * use the original versions.
3889 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3890 * will occur. As an example, a TXP production before this pass:
3892 * 0: MOV TEMP[1], INPUT[4].xyyy;
3893 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3894 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
3898 * 0: MOV TEMP[1], INPUT[4].xyyy;
3899 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3900 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3902 * which allows for dead code elimination on TEMP[1]'s writes.
3905 glsl_to_tgsi_visitor::copy_propagate(void)
3907 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
3908 glsl_to_tgsi_instruction
*,
3909 this->next_temp
* 4);
3910 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3913 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3914 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3915 || inst
->dst
[0].index
< this->next_temp
);
3917 /* First, do any copy propagation possible into the src regs. */
3918 for (int r
= 0; r
< 3; r
++) {
3919 glsl_to_tgsi_instruction
*first
= NULL
;
3921 int acp_base
= inst
->src
[r
].index
* 4;
3923 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
3924 inst
->src
[r
].reladdr
||
3925 inst
->src
[r
].reladdr2
)
3928 /* See if we can find entries in the ACP consisting of MOVs
3929 * from the same src register for all the swizzled channels
3930 * of this src register reference.
3932 for (int i
= 0; i
< 4; i
++) {
3933 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3934 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
3941 assert(acp_level
[acp_base
+ src_chan
] <= level
);
3946 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
3947 first
->src
[0].index
!= copy_chan
->src
[0].index
||
3948 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
3949 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
3957 /* We've now validated that we can copy-propagate to
3958 * replace this src register reference. Do it.
3960 inst
->src
[r
].file
= first
->src
[0].file
;
3961 inst
->src
[r
].index
= first
->src
[0].index
;
3962 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
3963 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
3964 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
3965 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
3968 for (int i
= 0; i
< 4; i
++) {
3969 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3970 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
3971 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
3973 inst
->src
[r
].swizzle
= swizzle
;
3978 case TGSI_OPCODE_BGNLOOP
:
3979 case TGSI_OPCODE_ENDLOOP
:
3980 /* End of a basic block, clear the ACP entirely. */
3981 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3984 case TGSI_OPCODE_IF
:
3985 case TGSI_OPCODE_UIF
:
3989 case TGSI_OPCODE_ENDIF
:
3990 case TGSI_OPCODE_ELSE
:
3991 /* Clear all channels written inside the block from the ACP, but
3992 * leaving those that were not touched.
3994 for (int r
= 0; r
< this->next_temp
; r
++) {
3995 for (int c
= 0; c
< 4; c
++) {
3996 if (!acp
[4 * r
+ c
])
3999 if (acp_level
[4 * r
+ c
] >= level
)
4000 acp
[4 * r
+ c
] = NULL
;
4003 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4008 /* Continuing the block, clear any written channels from
4011 for (int d
= 0; d
< 2; d
++) {
4012 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4013 /* Any temporary might be written, so no copy propagation
4014 * across this instruction.
4016 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4017 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4018 inst
->dst
[d
].reladdr
) {
4019 /* Any output might be written, so no copy propagation
4020 * from outputs across this instruction.
4022 for (int r
= 0; r
< this->next_temp
; r
++) {
4023 for (int c
= 0; c
< 4; c
++) {
4024 if (!acp
[4 * r
+ c
])
4027 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4028 acp
[4 * r
+ c
] = NULL
;
4031 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4032 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4033 /* Clear where it's used as dst. */
4034 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4035 for (int c
= 0; c
< 4; c
++) {
4036 if (inst
->dst
[d
].writemask
& (1 << c
))
4037 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4041 /* Clear where it's used as src. */
4042 for (int r
= 0; r
< this->next_temp
; r
++) {
4043 for (int c
= 0; c
< 4; c
++) {
4044 if (!acp
[4 * r
+ c
])
4047 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4049 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4050 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4051 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4052 acp
[4 * r
+ c
] = NULL
;
4061 /* If this is a copy, add it to the ACP. */
4062 if (inst
->op
== TGSI_OPCODE_MOV
&&
4063 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4064 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4065 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4066 !inst
->dst
[0].reladdr
&&
4067 !inst
->dst
[0].reladdr2
&&
4069 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4070 !inst
->src
[0].reladdr
&&
4071 !inst
->src
[0].reladdr2
&&
4072 !inst
->src
[0].negate
) {
4073 for (int i
= 0; i
< 4; i
++) {
4074 if (inst
->dst
[0].writemask
& (1 << i
)) {
4075 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4076 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4082 ralloc_free(acp_level
);
4087 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4090 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4091 * will occur. As an example, a TXP production after copy propagation but
4094 * 0: MOV TEMP[1], INPUT[4].xyyy;
4095 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4096 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4098 * and after this pass:
4100 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4103 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4105 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4106 glsl_to_tgsi_instruction
*,
4107 this->next_temp
* 4);
4108 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4112 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4113 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4114 || inst
->dst
[0].index
< this->next_temp
);
4117 case TGSI_OPCODE_BGNLOOP
:
4118 case TGSI_OPCODE_ENDLOOP
:
4119 case TGSI_OPCODE_CONT
:
4120 case TGSI_OPCODE_BRK
:
4121 /* End of a basic block, clear the write array entirely.
4123 * This keeps us from killing dead code when the writes are
4124 * on either side of a loop, even when the register isn't touched
4125 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4126 * dead code of this type, so it shouldn't make a difference as long as
4127 * the dead code elimination pass in the GLSL compiler does its job.
4129 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4132 case TGSI_OPCODE_ENDIF
:
4133 case TGSI_OPCODE_ELSE
:
4134 /* Promote the recorded level of all channels written inside the
4135 * preceding if or else block to the level above the if/else block.
4137 for (int r
= 0; r
< this->next_temp
; r
++) {
4138 for (int c
= 0; c
< 4; c
++) {
4139 if (!writes
[4 * r
+ c
])
4142 if (write_level
[4 * r
+ c
] == level
)
4143 write_level
[4 * r
+ c
] = level
-1;
4146 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4150 case TGSI_OPCODE_IF
:
4151 case TGSI_OPCODE_UIF
:
4153 /* fallthrough to default case to mark the condition as read */
4155 /* Continuing the block, clear any channels from the write array that
4156 * are read by this instruction.
4158 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4159 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4160 /* Any temporary might be read, so no dead code elimination
4161 * across this instruction.
4163 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4164 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4165 /* Clear where it's used as src. */
4166 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4167 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4168 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4169 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4171 for (int c
= 0; c
< 4; c
++) {
4172 if (src_chans
& (1 << c
))
4173 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4177 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4178 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4179 /* Any temporary might be read, so no dead code elimination
4180 * across this instruction.
4182 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4183 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4184 /* Clear where it's used as src. */
4185 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4186 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4187 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4188 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4190 for (int c
= 0; c
< 4; c
++) {
4191 if (src_chans
& (1 << c
))
4192 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4199 /* If this instruction writes to a temporary, add it to the write array.
4200 * If there is already an instruction in the write array for one or more
4201 * of the channels, flag that channel write as dead.
4203 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4204 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4205 !inst
->dst
[i
].reladdr
) {
4206 for (int c
= 0; c
< 4; c
++) {
4207 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4208 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4209 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4212 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4214 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4215 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4222 /* Anything still in the write array at this point is dead code. */
4223 for (int r
= 0; r
< this->next_temp
; r
++) {
4224 for (int c
= 0; c
< 4; c
++) {
4225 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4227 inst
->dead_mask
|= (1 << c
);
4231 /* Now actually remove the instructions that are completely dead and update
4232 * the writemask of other instructions with dead channels.
4234 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4235 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4237 else if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4242 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4243 if (inst
->dead_mask
== WRITEMASK_XY
||
4244 inst
->dead_mask
== WRITEMASK_ZW
)
4245 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4247 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4251 ralloc_free(write_level
);
4252 ralloc_free(writes
);
4257 /* merge DFRACEXP instructions into one. */
4259 glsl_to_tgsi_visitor::merge_two_dsts(void)
4261 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4262 glsl_to_tgsi_instruction
*inst2
;
4264 if (num_inst_dst_regs(inst
) != 2)
4267 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4268 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4271 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4274 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4275 inst
->src
[0].index
== inst2
->src
[0].index
&&
4276 inst
->src
[0].type
== inst2
->src
[0].type
&&
4277 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4279 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4285 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4287 inst
->dst
[0] = inst2
->dst
[0];
4288 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4289 inst
->dst
[1] = inst2
->dst
[1];
4300 /* Merges temporary registers together where possible to reduce the number of
4301 * registers needed to run a program.
4303 * Produces optimal code only after copy propagation and dead code elimination
4306 glsl_to_tgsi_visitor::merge_registers(void)
4308 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4309 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4310 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4312 int num_renames
= 0;
4314 /* Read the indices of the last read and first write to each temp register
4315 * into an array so that we don't have to traverse the instruction list as
4317 for (i
= 0; i
< this->next_temp
; i
++) {
4319 first_writes
[i
] = -1;
4321 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
4323 /* Start looking for registers with non-overlapping usages that can be
4324 * merged together. */
4325 for (i
= 0; i
< this->next_temp
; i
++) {
4326 /* Don't touch unused registers. */
4327 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
4329 for (j
= 0; j
< this->next_temp
; j
++) {
4330 /* Don't touch unused registers. */
4331 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
4333 /* We can merge the two registers if the first write to j is after or
4334 * in the same instruction as the last read from i. Note that the
4335 * register at index i will always be used earlier or at the same time
4336 * as the register at index j. */
4337 if (first_writes
[i
] <= first_writes
[j
] &&
4338 last_reads
[i
] <= first_writes
[j
]) {
4339 renames
[num_renames
].old_reg
= j
;
4340 renames
[num_renames
].new_reg
= i
;
4343 /* Update the first_writes and last_reads arrays with the new
4344 * values for the merged register index, and mark the newly unused
4345 * register index as such. */
4346 last_reads
[i
] = last_reads
[j
];
4347 first_writes
[j
] = -1;
4353 rename_temp_registers(num_renames
, renames
);
4354 ralloc_free(renames
);
4355 ralloc_free(last_reads
);
4356 ralloc_free(first_writes
);
4359 /* Reassign indices to temporary registers by reusing unused indices created
4360 * by optimization passes. */
4362 glsl_to_tgsi_visitor::renumber_registers(void)
4366 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4367 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4368 int num_renames
= 0;
4369 for (i
= 0; i
< this->next_temp
; i
++) {
4370 first_reads
[i
] = -1;
4372 get_first_temp_read(first_reads
);
4374 for (i
= 0; i
< this->next_temp
; i
++) {
4375 if (first_reads
[i
] < 0) continue;
4376 if (i
!= new_index
) {
4377 renames
[num_renames
].old_reg
= i
;
4378 renames
[num_renames
].new_reg
= new_index
;
4384 rename_temp_registers(num_renames
, renames
);
4385 this->next_temp
= new_index
;
4386 ralloc_free(renames
);
4387 ralloc_free(first_reads
);
4390 /* ------------------------- TGSI conversion stuff -------------------------- */
4392 unsigned branch_target
;
4397 * Intermediate state used during shader translation.
4399 struct st_translate
{
4400 struct ureg_program
*ureg
;
4402 unsigned temps_size
;
4403 struct ureg_dst
*temps
;
4405 struct ureg_dst
*arrays
;
4406 unsigned num_temp_arrays
;
4407 struct ureg_src
*constants
;
4409 struct ureg_src
*immediates
;
4411 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
4412 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
4413 struct ureg_dst address
[3];
4414 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
4415 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
4416 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
4417 unsigned *array_sizes
;
4418 struct array_decl
*input_arrays
;
4419 struct array_decl
*output_arrays
;
4421 const GLuint
*inputMapping
;
4422 const GLuint
*outputMapping
;
4424 /* For every instruction that contains a label (eg CALL), keep
4425 * details so that we can go back afterwards and emit the correct
4426 * tgsi instruction number for each label.
4428 struct label
*labels
;
4429 unsigned labels_size
;
4430 unsigned labels_count
;
4432 /* Keep a record of the tgsi instruction number that each mesa
4433 * instruction starts at, will be used to fix up labels after
4438 unsigned insn_count
;
4440 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
4445 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
4446 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
4449 TGSI_SEMANTIC_VERTEXID
,
4450 TGSI_SEMANTIC_INSTANCEID
,
4451 TGSI_SEMANTIC_VERTEXID_NOBASE
,
4452 TGSI_SEMANTIC_BASEVERTEX
,
4453 TGSI_SEMANTIC_BASEINSTANCE
,
4454 TGSI_SEMANTIC_DRAWID
,
4458 TGSI_SEMANTIC_INVOCATIONID
,
4463 TGSI_SEMANTIC_SAMPLEID
,
4464 TGSI_SEMANTIC_SAMPLEPOS
,
4465 TGSI_SEMANTIC_SAMPLEMASK
,
4466 TGSI_SEMANTIC_HELPER_INVOCATION
,
4468 /* Tessellation shaders
4470 TGSI_SEMANTIC_TESSCOORD
,
4471 TGSI_SEMANTIC_VERTICESIN
,
4472 TGSI_SEMANTIC_PRIMID
,
4473 TGSI_SEMANTIC_TESSOUTER
,
4474 TGSI_SEMANTIC_TESSINNER
,
4478 * Make note of a branch to a label in the TGSI code.
4479 * After we've emitted all instructions, we'll go over the list
4480 * of labels built here and patch the TGSI code with the actual
4481 * location of each label.
4483 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
4487 if (t
->labels_count
+ 1 >= t
->labels_size
) {
4488 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
4489 t
->labels
= (struct label
*)realloc(t
->labels
,
4490 t
->labels_size
* sizeof(struct label
));
4491 if (t
->labels
== NULL
) {
4492 static unsigned dummy
;
4498 i
= t
->labels_count
++;
4499 t
->labels
[i
].branch_target
= branch_target
;
4500 return &t
->labels
[i
].token
;
4504 * Called prior to emitting the TGSI code for each instruction.
4505 * Allocate additional space for instructions if needed.
4506 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
4507 * the next TGSI instruction.
4509 static void set_insn_start(struct st_translate
*t
, unsigned start
)
4511 if (t
->insn_count
+ 1 >= t
->insn_size
) {
4512 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
4513 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
4514 if (t
->insn
== NULL
) {
4520 t
->insn
[t
->insn_count
++] = start
;
4524 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
4526 static struct ureg_src
4527 emit_immediate(struct st_translate
*t
,
4528 gl_constant_value values
[4],
4531 struct ureg_program
*ureg
= t
->ureg
;
4536 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
4538 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
4540 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
4541 case GL_UNSIGNED_INT
:
4543 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
4545 assert(!"should not get here - type must be float, int, uint, or bool");
4546 return ureg_src_undef();
4551 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
4553 static struct ureg_dst
4554 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
4560 case PROGRAM_UNDEFINED
:
4561 return ureg_dst_undef();
4563 case PROGRAM_TEMPORARY
:
4564 /* Allocate space for temporaries on demand. */
4565 if (index
>= t
->temps_size
) {
4566 const int inc
= 4096;
4568 t
->temps
= (struct ureg_dst
*)
4570 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
4572 return ureg_dst_undef();
4574 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
4575 t
->temps_size
+= inc
;
4578 if (ureg_dst_is_undef(t
->temps
[index
]))
4579 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
4581 return t
->temps
[index
];
4584 array
= index
>> 16;
4586 assert(array
< t
->num_temp_arrays
);
4588 if (ureg_dst_is_undef(t
->arrays
[array
]))
4589 t
->arrays
[array
] = ureg_DECL_array_temporary(
4590 t
->ureg
, t
->array_sizes
[array
], TRUE
);
4592 return ureg_dst_array_offset(t
->arrays
[array
],
4593 (int)(index
& 0xFFFF) - 0x8000);
4595 case PROGRAM_OUTPUT
:
4597 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
4598 assert(index
< FRAG_RESULT_MAX
);
4599 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
4600 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
4601 assert(index
< VARYING_SLOT_TESS_MAX
);
4603 assert(index
< VARYING_SLOT_MAX
);
4605 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
4606 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4607 return t
->outputs
[t
->outputMapping
[index
]];
4610 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
4611 unsigned mesa_index
= decl
->mesa_index
;
4612 int slot
= t
->outputMapping
[mesa_index
];
4614 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
4615 assert(t
->outputs
[slot
].ArrayID
== array_id
);
4616 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
4619 case PROGRAM_ADDRESS
:
4620 return t
->address
[index
];
4623 assert(!"unknown dst register file");
4624 return ureg_dst_undef();
4629 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
4631 static struct ureg_src
4632 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
4634 int index
= reg
->index
;
4635 int double_reg2
= reg
->double_reg2
? 1 : 0;
4638 case PROGRAM_UNDEFINED
:
4639 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4641 case PROGRAM_TEMPORARY
:
4643 case PROGRAM_OUTPUT
:
4644 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
4646 case PROGRAM_UNIFORM
:
4647 assert(reg
->index
>= 0);
4648 return reg
->index
< t
->num_constants
?
4649 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4650 case PROGRAM_STATE_VAR
:
4651 case PROGRAM_CONSTANT
: /* ie, immediate */
4652 if (reg
->has_index2
)
4653 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
4655 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
4656 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4658 case PROGRAM_IMMEDIATE
:
4659 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
4660 return t
->immediates
[reg
->index
];
4663 /* GLSL inputs are 64-bit containers, so we have to
4664 * map back to the original index and add the offset after
4666 index
-= double_reg2
;
4667 if (!reg
->array_id
) {
4668 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
4669 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4670 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
4673 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
4674 unsigned mesa_index
= decl
->mesa_index
;
4675 int slot
= t
->inputMapping
[mesa_index
];
4677 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
4678 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
4679 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
4682 case PROGRAM_ADDRESS
:
4683 return ureg_src(t
->address
[reg
->index
]);
4685 case PROGRAM_SYSTEM_VALUE
:
4686 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
4687 return t
->systemValues
[reg
->index
];
4690 assert(!"unknown src register file");
4691 return ureg_src_undef();
4696 * Create a TGSI ureg_dst register from an st_dst_reg.
4698 static struct ureg_dst
4699 translate_dst(struct st_translate
*t
,
4700 const st_dst_reg
*dst_reg
,
4703 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
4706 if (dst
.File
== TGSI_FILE_NULL
)
4709 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
4712 dst
= ureg_saturate(dst
);
4714 if (dst_reg
->reladdr
!= NULL
) {
4715 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
4716 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
4719 if (dst_reg
->has_index2
) {
4720 if (dst_reg
->reladdr2
)
4721 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
4724 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
4731 * Create a TGSI ureg_src register from an st_src_reg.
4733 static struct ureg_src
4734 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
4736 struct ureg_src src
= src_register(t
, src_reg
);
4738 if (src_reg
->has_index2
) {
4739 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
4740 * and UBO constant buffers (buffer, position).
4742 if (src_reg
->reladdr2
)
4743 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
4746 src
= ureg_src_dimension(src
, src_reg
->index2D
);
4749 src
= ureg_swizzle(src
,
4750 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
4751 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
4752 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
4753 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
4755 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
4756 src
= ureg_negate(src
);
4758 if (src_reg
->reladdr
!= NULL
) {
4759 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
4760 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
4766 static struct tgsi_texture_offset
4767 translate_tex_offset(struct st_translate
*t
,
4768 const st_src_reg
*in_offset
, int idx
)
4770 struct tgsi_texture_offset offset
;
4771 struct ureg_src imm_src
;
4772 struct ureg_dst dst
;
4775 switch (in_offset
->file
) {
4776 case PROGRAM_IMMEDIATE
:
4777 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
4778 imm_src
= t
->immediates
[in_offset
->index
];
4780 offset
.File
= imm_src
.File
;
4781 offset
.Index
= imm_src
.Index
;
4782 offset
.SwizzleX
= imm_src
.SwizzleX
;
4783 offset
.SwizzleY
= imm_src
.SwizzleY
;
4784 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
4787 case PROGRAM_TEMPORARY
:
4788 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
4789 offset
.File
= imm_src
.File
;
4790 offset
.Index
= imm_src
.Index
;
4791 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4792 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4793 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4797 array
= in_offset
->index
>> 16;
4800 assert(array
< (int)t
->num_temp_arrays
);
4802 dst
= t
->arrays
[array
];
4803 offset
.File
= dst
.File
;
4804 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
4805 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4806 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4807 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4817 compile_tgsi_instruction(struct st_translate
*t
,
4818 const glsl_to_tgsi_instruction
*inst
)
4820 struct ureg_program
*ureg
= t
->ureg
;
4822 struct ureg_dst dst
[2];
4823 struct ureg_src src
[4];
4824 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
4828 unsigned tex_target
;
4830 num_dst
= num_inst_dst_regs(inst
);
4831 num_src
= num_inst_src_regs(inst
);
4833 for (i
= 0; i
< num_dst
; i
++)
4834 dst
[i
] = translate_dst(t
,
4838 for (i
= 0; i
< num_src
; i
++)
4839 src
[i
] = translate_src(t
, &inst
->src
[i
]);
4842 case TGSI_OPCODE_BGNLOOP
:
4843 case TGSI_OPCODE_CAL
:
4844 case TGSI_OPCODE_ELSE
:
4845 case TGSI_OPCODE_ENDLOOP
:
4846 case TGSI_OPCODE_IF
:
4847 case TGSI_OPCODE_UIF
:
4848 assert(num_dst
== 0);
4849 ureg_label_insn(ureg
,
4853 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
4856 case TGSI_OPCODE_TEX
:
4857 case TGSI_OPCODE_TXB
:
4858 case TGSI_OPCODE_TXD
:
4859 case TGSI_OPCODE_TXL
:
4860 case TGSI_OPCODE_TXP
:
4861 case TGSI_OPCODE_TXQ
:
4862 case TGSI_OPCODE_TXQS
:
4863 case TGSI_OPCODE_TXF
:
4864 case TGSI_OPCODE_TEX2
:
4865 case TGSI_OPCODE_TXB2
:
4866 case TGSI_OPCODE_TXL2
:
4867 case TGSI_OPCODE_TG4
:
4868 case TGSI_OPCODE_LODQ
:
4869 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
4870 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
4871 if (inst
->sampler
.reladdr
)
4873 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
4875 for (i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4876 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
4878 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4884 texoffsets
, inst
->tex_offset_num_offset
,
4888 case TGSI_OPCODE_SCS
:
4889 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
4890 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
4903 * Emit the TGSI instructions for inverting and adjusting WPOS.
4904 * This code is unavoidable because it also depends on whether
4905 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
4908 emit_wpos_adjustment( struct st_translate
*t
,
4909 int wpos_transform_const
,
4911 GLfloat adjX
, GLfloat adjY
[2])
4913 struct ureg_program
*ureg
= t
->ureg
;
4915 assert(wpos_transform_const
>= 0);
4917 /* Fragment program uses fragment position input.
4918 * Need to replace instances of INPUT[WPOS] with temp T
4919 * where T = INPUT[WPOS] is inverted by Y.
4921 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
4922 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
4923 struct ureg_src wpos_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
4925 /* First, apply the coordinate shift: */
4926 if (adjX
|| adjY
[0] || adjY
[1]) {
4927 if (adjY
[0] != adjY
[1]) {
4928 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
4929 * depending on whether inversion is actually going to be applied
4930 * or not, which is determined by testing against the inversion
4931 * state variable used below, which will be either +1 or -1.
4933 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
4935 ureg_CMP(ureg
, adj_temp
,
4936 ureg_scalar(wpostrans
, invert
? 2 : 0),
4937 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
4938 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
4939 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
4941 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
4942 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
4944 wpos_input
= ureg_src(wpos_temp
);
4946 /* MOV wpos_temp, input[wpos]
4948 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
4951 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
4952 * inversion/identity, or the other way around if we're drawing to an FBO.
4955 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
4958 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4960 ureg_scalar(wpostrans
, 0),
4961 ureg_scalar(wpostrans
, 1));
4963 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
4966 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4968 ureg_scalar(wpostrans
, 2),
4969 ureg_scalar(wpostrans
, 3));
4972 /* Use wpos_temp as position input from here on:
4974 t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]] = ureg_src(wpos_temp
);
4979 * Emit fragment position/ooordinate code.
4982 emit_wpos(struct st_context
*st
,
4983 struct st_translate
*t
,
4984 const struct gl_program
*program
,
4985 struct ureg_program
*ureg
,
4986 int wpos_transform_const
)
4988 const struct gl_fragment_program
*fp
=
4989 (const struct gl_fragment_program
*) program
;
4990 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
4991 GLfloat adjX
= 0.0f
;
4992 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
4993 boolean invert
= FALSE
;
4995 /* Query the pixel center conventions supported by the pipe driver and set
4996 * adjX, adjY to help out if it cannot handle the requested one internally.
4998 * The bias of the y-coordinate depends on whether y-inversion takes place
4999 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5000 * drawing to an FBO (causes additional inversion), and whether the the pipe
5001 * driver origin and the requested origin differ (the latter condition is
5002 * stored in the 'invert' variable).
5004 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5006 * center shift only:
5011 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5012 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5013 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5014 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5016 * inversion and center shift:
5017 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5018 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5019 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5020 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5022 if (fp
->OriginUpperLeft
) {
5023 /* Fragment shader wants origin in upper-left */
5024 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5025 /* the driver supports upper-left origin */
5027 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5028 /* the driver supports lower-left origin, need to invert Y */
5029 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5030 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5037 /* Fragment shader wants origin in lower-left */
5038 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5039 /* the driver supports lower-left origin */
5040 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5041 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5042 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5043 /* the driver supports upper-left origin, need to invert Y */
5049 if (fp
->PixelCenterInteger
) {
5050 /* Fragment shader wants pixel center integer */
5051 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5052 /* the driver supports pixel center integer */
5054 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5055 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5057 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5058 /* the driver supports pixel center half integer, need to bias X,Y */
5067 /* Fragment shader wants pixel center half integer */
5068 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5069 /* the driver supports pixel center half integer */
5071 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5072 /* the driver supports pixel center integer, need to bias X,Y */
5073 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5074 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5075 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5081 /* we invert after adjustment so that we avoid the MOV to temporary,
5082 * and reuse the adjustment ADD instead */
5083 emit_wpos_adjustment(t
, wpos_transform_const
, invert
, adjX
, adjY
);
5087 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5088 * TGSI uses +1 for front, -1 for back.
5089 * This function converts the TGSI value to the GL value. Simply clamping/
5090 * saturating the value to [0,1] does the job.
5093 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5095 struct ureg_program
*ureg
= t
->ureg
;
5096 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5097 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5099 if (ctx
->Const
.NativeIntegers
) {
5100 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5103 /* MOV_SAT face_temp, input[face] */
5104 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5107 /* Use face_temp as face input from here on: */
5108 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5112 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5113 unsigned *array_id
, unsigned *array_size
)
5117 for (i
= 0; i
< count
; i
++) {
5118 struct array_decl
*decl
= &arrays
[i
];
5120 if (attr
== decl
->mesa_index
) {
5121 *array_id
= decl
->array_id
;
5122 *array_size
= decl
->array_size
;
5123 assert(*array_size
);
5131 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5132 * \param program the program to translate
5133 * \param numInputs number of input registers used
5134 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5136 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5137 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5139 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5140 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5141 * \param numOutputs number of output registers used
5142 * \param outputMapping maps Mesa fragment program outputs to TGSI
5144 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5145 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5148 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5150 extern "C" enum pipe_error
5151 st_translate_program(
5152 struct gl_context
*ctx
,
5154 struct ureg_program
*ureg
,
5155 glsl_to_tgsi_visitor
*program
,
5156 const struct gl_program
*proginfo
,
5158 const GLuint inputMapping
[],
5159 const GLuint inputSlotToAttr
[],
5160 const ubyte inputSemanticName
[],
5161 const ubyte inputSemanticIndex
[],
5162 const GLuint interpMode
[],
5163 const GLuint interpLocation
[],
5165 const GLuint outputMapping
[],
5166 const GLuint outputSlotToAttr
[],
5167 const ubyte outputSemanticName
[],
5168 const ubyte outputSemanticIndex
[])
5170 struct st_translate
*t
;
5172 enum pipe_error ret
= PIPE_OK
;
5174 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5175 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5177 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5178 TGSI_SEMANTIC_FACE
);
5179 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5180 TGSI_SEMANTIC_VERTEXID
);
5181 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5182 TGSI_SEMANTIC_INSTANCEID
);
5183 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5184 TGSI_SEMANTIC_SAMPLEID
);
5185 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5186 TGSI_SEMANTIC_SAMPLEPOS
);
5187 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5188 TGSI_SEMANTIC_SAMPLEMASK
);
5189 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5190 TGSI_SEMANTIC_INVOCATIONID
);
5191 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5192 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5193 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5194 TGSI_SEMANTIC_BASEVERTEX
);
5195 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5196 TGSI_SEMANTIC_TESSCOORD
);
5197 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_HELPER_INVOCATION
] ==
5198 TGSI_SEMANTIC_HELPER_INVOCATION
);
5200 t
= CALLOC_STRUCT(st_translate
);
5202 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5206 t
->procType
= procType
;
5207 t
->inputMapping
= inputMapping
;
5208 t
->outputMapping
= outputMapping
;
5210 t
->num_temp_arrays
= program
->next_array
;
5211 if (t
->num_temp_arrays
)
5212 t
->arrays
= (struct ureg_dst
*)
5213 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5216 * Declare input attributes.
5219 case TGSI_PROCESSOR_FRAGMENT
:
5220 for (i
= 0; i
< numInputs
; i
++) {
5221 unsigned array_id
= 0;
5222 unsigned array_size
;
5224 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5225 program
->num_input_arrays
, &array_id
, &array_size
)) {
5226 /* We've found an array. Declare it so. */
5227 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5228 inputSemanticName
[i
], inputSemanticIndex
[i
],
5229 interpMode
[i
], 0, interpLocation
[i
],
5230 array_id
, array_size
);
5231 i
+= array_size
- 1;
5234 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5235 inputSemanticName
[i
], inputSemanticIndex
[i
],
5236 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
5240 case TGSI_PROCESSOR_GEOMETRY
:
5241 case TGSI_PROCESSOR_TESS_EVAL
:
5242 case TGSI_PROCESSOR_TESS_CTRL
:
5243 for (i
= 0; i
< numInputs
; i
++) {
5244 unsigned array_id
= 0;
5245 unsigned array_size
;
5247 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5248 program
->num_input_arrays
, &array_id
, &array_size
)) {
5249 /* We've found an array. Declare it so. */
5250 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5251 inputSemanticIndex
[i
],
5252 array_id
, array_size
);
5253 i
+= array_size
- 1;
5256 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5257 inputSemanticIndex
[i
], 0, 1);
5261 case TGSI_PROCESSOR_VERTEX
:
5262 for (i
= 0; i
< numInputs
; i
++) {
5263 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
5271 * Declare output attributes.
5274 case TGSI_PROCESSOR_FRAGMENT
:
5276 case TGSI_PROCESSOR_GEOMETRY
:
5277 case TGSI_PROCESSOR_TESS_EVAL
:
5278 case TGSI_PROCESSOR_TESS_CTRL
:
5279 case TGSI_PROCESSOR_VERTEX
:
5280 for (i
= 0; i
< numOutputs
; i
++) {
5281 unsigned array_id
= 0;
5282 unsigned array_size
;
5284 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
5285 program
->num_output_arrays
, &array_id
, &array_size
)) {
5286 /* We've found an array. Declare it so. */
5287 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
5288 outputSemanticName
[i
],
5289 outputSemanticIndex
[i
],
5290 array_id
, array_size
);
5291 i
+= array_size
- 1;
5294 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5295 outputSemanticName
[i
],
5296 outputSemanticIndex
[i
]);
5304 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
5305 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
5306 /* Must do this after setting up t->inputs. */
5307 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
5308 program
->wpos_transform_const
);
5311 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
5312 emit_face_var(ctx
, t
);
5314 for (i
= 0; i
< numOutputs
; i
++) {
5315 switch (outputSemanticName
[i
]) {
5316 case TGSI_SEMANTIC_POSITION
:
5317 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5318 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
5319 outputSemanticIndex
[i
]);
5320 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
5322 case TGSI_SEMANTIC_STENCIL
:
5323 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5324 TGSI_SEMANTIC_STENCIL
, /* Stencil */
5325 outputSemanticIndex
[i
]);
5326 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
5328 case TGSI_SEMANTIC_COLOR
:
5329 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5330 TGSI_SEMANTIC_COLOR
,
5331 outputSemanticIndex
[i
]);
5333 case TGSI_SEMANTIC_SAMPLEMASK
:
5334 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5335 TGSI_SEMANTIC_SAMPLEMASK
,
5336 outputSemanticIndex
[i
]);
5337 /* TODO: If we ever support more than 32 samples, this will have
5338 * to become an array.
5340 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5343 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
5344 ret
= PIPE_ERROR_BAD_INPUT
;
5349 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
5350 for (i
= 0; i
< numOutputs
; i
++) {
5351 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
5352 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
5354 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
5355 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
5356 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5361 /* Declare address register.
5363 if (program
->num_address_regs
> 0) {
5364 assert(program
->num_address_regs
<= 3);
5365 for (int i
= 0; i
< program
->num_address_regs
; i
++)
5366 t
->address
[i
] = ureg_DECL_address(ureg
);
5369 /* Declare misc input registers
5372 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
5374 for (i
= 0; sysInputs
; i
++) {
5375 if (sysInputs
& (1 << i
)) {
5376 unsigned semName
= _mesa_sysval_to_semantic
[i
];
5378 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
5380 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
5381 semName
== TGSI_SEMANTIC_VERTEXID
) {
5382 /* From Gallium perspective, these system values are always
5383 * integer, and require native integer support. However, if
5384 * native integer is supported on the vertex stage but not the
5385 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
5386 * assumes these system values are floats. To resolve the
5387 * inconsistency, we insert a U2F.
5389 struct st_context
*st
= st_context(ctx
);
5390 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5391 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5392 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
5394 if (!ctx
->Const
.NativeIntegers
) {
5395 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
5396 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
5397 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
5401 sysInputs
&= ~(1 << i
);
5406 t
->array_sizes
= program
->array_sizes
;
5407 t
->input_arrays
= program
->input_arrays
;
5408 t
->output_arrays
= program
->output_arrays
;
5410 /* Emit constants and uniforms. TGSI uses a single index space for these,
5411 * so we put all the translated regs in t->constants.
5413 if (proginfo
->Parameters
) {
5414 t
->constants
= (struct ureg_src
*)
5415 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
5416 if (t
->constants
== NULL
) {
5417 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5420 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
5422 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
5423 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
5424 case PROGRAM_STATE_VAR
:
5425 case PROGRAM_UNIFORM
:
5426 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5429 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
5430 * addressing of the const buffer.
5431 * FIXME: Be smarter and recognize param arrays:
5432 * indirect addressing is only valid within the referenced
5435 case PROGRAM_CONSTANT
:
5436 if (program
->indirect_addr_consts
)
5437 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5439 t
->constants
[i
] = emit_immediate(t
,
5440 proginfo
->Parameters
->ParameterValues
[i
],
5441 proginfo
->Parameters
->Parameters
[i
].DataType
,
5450 if (program
->shader
) {
5451 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
5453 for (i
= 0; i
< num_ubos
; i
++) {
5454 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
5455 unsigned num_const_vecs
= (size
+ 15) / 16;
5456 unsigned first
, last
;
5457 assert(num_const_vecs
> 0);
5459 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
5460 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
5464 /* Emit immediate values.
5466 t
->immediates
= (struct ureg_src
*)
5467 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
5468 if (t
->immediates
== NULL
) {
5469 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5472 t
->num_immediates
= program
->num_immediates
;
5475 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
5476 assert(i
< program
->num_immediates
);
5477 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
5479 assert(i
== program
->num_immediates
);
5481 /* texture samplers */
5482 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
5483 if (program
->samplers_used
& (1 << i
)) {
5486 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
5488 switch (program
->sampler_types
[i
]) {
5490 type
= TGSI_RETURN_TYPE_SINT
;
5492 case GLSL_TYPE_UINT
:
5493 type
= TGSI_RETURN_TYPE_UINT
;
5495 case GLSL_TYPE_FLOAT
:
5496 type
= TGSI_RETURN_TYPE_FLOAT
;
5499 unreachable("not reached");
5502 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
5503 type
, type
, type
, type
);
5507 /* Emit each instruction in turn:
5509 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
5510 set_insn_start(t
, ureg_get_instruction_number(ureg
));
5511 compile_tgsi_instruction(t
, inst
);
5514 /* Fix up all emitted labels:
5516 for (i
= 0; i
< t
->labels_count
; i
++) {
5517 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
5518 t
->insn
[t
->labels
[i
].branch_target
]);
5528 t
->num_constants
= 0;
5529 free(t
->immediates
);
5530 t
->num_immediates
= 0;
5533 debug_printf("%s: translate error flag set\n", __func__
);
5541 /* ----------------------------- End TGSI code ------------------------------ */
5545 * Convert a shader's GLSL IR into a Mesa gl_program, although without
5546 * generating Mesa IR.
5548 static struct gl_program
*
5549 get_mesa_program(struct gl_context
*ctx
,
5550 struct gl_shader_program
*shader_program
,
5551 struct gl_shader
*shader
)
5553 glsl_to_tgsi_visitor
* v
;
5554 struct gl_program
*prog
;
5555 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
5557 struct gl_shader_compiler_options
*options
=
5558 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
5559 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5560 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
5562 validate_ir_tree(shader
->ir
);
5564 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
5567 prog
->Parameters
= _mesa_new_parameter_list();
5568 v
= new glsl_to_tgsi_visitor();
5571 v
->shader_program
= shader_program
;
5573 v
->options
= options
;
5574 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
5575 v
->native_integers
= ctx
->Const
.NativeIntegers
;
5577 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
5578 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
5579 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
5580 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
5582 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
5583 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
5586 /* Remove reads from output registers. */
5587 lower_output_reads(shader
->Stage
, shader
->ir
);
5589 /* Emit intermediate IR for main(). */
5590 visit_exec_list(shader
->ir
, v
);
5592 /* Now emit bodies for any functions that were used. */
5594 progress
= GL_FALSE
;
5596 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
5597 if (!entry
->bgn_inst
) {
5598 v
->current_function
= entry
;
5600 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
5601 entry
->bgn_inst
->function
= entry
;
5603 visit_exec_list(&entry
->sig
->body
, v
);
5605 glsl_to_tgsi_instruction
*last
;
5606 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
5607 if (last
->op
!= TGSI_OPCODE_RET
)
5608 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
5610 glsl_to_tgsi_instruction
*end
;
5611 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
5612 end
->function
= entry
;
5620 /* Print out some information (for debugging purposes) used by the
5621 * optimization passes. */
5624 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5625 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5626 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5627 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5629 for (i
= 0; i
< v
->next_temp
; i
++) {
5630 first_writes
[i
] = -1;
5631 first_reads
[i
] = -1;
5632 last_writes
[i
] = -1;
5635 v
->get_first_temp_read(first_reads
);
5636 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5637 v
->get_last_temp_write(last_writes
);
5638 for (i
= 0; i
< v
->next_temp
; i
++)
5639 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
5643 ralloc_free(first_writes
);
5644 ralloc_free(first_reads
);
5645 ralloc_free(last_writes
);
5646 ralloc_free(last_reads
);
5650 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
5653 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
5654 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
5655 v
->copy_propagate();
5657 while (v
->eliminate_dead_code());
5659 v
->merge_two_dsts();
5660 v
->merge_registers();
5661 v
->renumber_registers();
5663 /* Write the END instruction. */
5664 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
5666 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
5668 _mesa_log("GLSL IR for linked %s program %d:\n",
5669 _mesa_shader_stage_to_string(shader
->Stage
),
5670 shader_program
->Name
);
5671 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
5675 prog
->Instructions
= NULL
;
5676 prog
->NumInstructions
= 0;
5678 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
5679 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
5680 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
5681 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
5682 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
5683 count_resources(v
, prog
);
5685 /* This must be done before the uniform storage is associated. */
5686 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
5687 prog
->InputsRead
& VARYING_BIT_POS
){
5688 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
5689 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
5692 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
5693 wposTransformState
);
5696 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
5698 /* Avoid reallocation of the program parameter list, because the uniform
5699 * storage is only associated with the original parameter list.
5700 * This should be enough for Bitmap and DrawPixels constants.
5702 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
5704 /* This has to be done last. Any operation the can cause
5705 * prog->ParameterValues to get reallocated (e.g., anything that adds a
5706 * program constant) has to happen before creating this linkage.
5708 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
5709 if (!shader_program
->LinkStatus
) {
5710 free_glsl_to_tgsi_visitor(v
);
5714 struct st_vertex_program
*stvp
;
5715 struct st_fragment_program
*stfp
;
5716 struct st_geometry_program
*stgp
;
5717 struct st_tessctrl_program
*sttcp
;
5718 struct st_tesseval_program
*sttep
;
5720 switch (shader
->Type
) {
5721 case GL_VERTEX_SHADER
:
5722 stvp
= (struct st_vertex_program
*)prog
;
5723 stvp
->glsl_to_tgsi
= v
;
5725 case GL_FRAGMENT_SHADER
:
5726 stfp
= (struct st_fragment_program
*)prog
;
5727 stfp
->glsl_to_tgsi
= v
;
5729 case GL_GEOMETRY_SHADER
:
5730 stgp
= (struct st_geometry_program
*)prog
;
5731 stgp
->glsl_to_tgsi
= v
;
5733 case GL_TESS_CONTROL_SHADER
:
5734 sttcp
= (struct st_tessctrl_program
*)prog
;
5735 sttcp
->glsl_to_tgsi
= v
;
5737 case GL_TESS_EVALUATION_SHADER
:
5738 sttep
= (struct st_tesseval_program
*)prog
;
5739 sttep
->glsl_to_tgsi
= v
;
5742 assert(!"should not be reached");
5752 st_dump_program_for_shader_db(struct gl_context
*ctx
,
5753 struct gl_shader_program
*prog
)
5755 /* Dump only successfully compiled and linked shaders to the specified
5756 * file. This is for shader-db.
5758 * These options allow some pre-processing of shaders while dumping,
5759 * because some apps have ill-formed shaders.
5761 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
5762 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
5764 if (dump_filename
&& prog
->Name
!= 0) {
5765 FILE *f
= fopen(dump_filename
, "a");
5768 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
5769 const struct gl_shader
*sh
= prog
->Shaders
[i
];
5771 bool skip_version
= false;
5776 source
= sh
->Source
;
5778 /* This string mustn't be changed. shader-db uses it to find
5779 * where the shader begins.
5781 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
5782 _mesa_shader_stage_to_string(sh
->Stage
),
5785 /* Dump the forced version if set. */
5786 if (ctx
->Const
.ForceGLSLVersion
) {
5787 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
5788 skip_version
= true;
5791 /* Insert directives (optional). */
5792 if (insert_directives
) {
5793 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
5794 fprintf(f
, "#version %i\n", prog
->Version
);
5795 fprintf(f
, "%s\n", insert_directives
);
5796 skip_version
= true;
5799 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
5800 const char *next_line
= strstr(source
, "\n");
5803 source
= next_line
+ 1;
5808 fprintf(f
, "%s", source
);
5818 * Called via ctx->Driver.LinkShader()
5819 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
5820 * with code lowering and other optimizations.
5823 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
5825 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5826 assert(prog
->LinkStatus
);
5828 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5829 if (prog
->_LinkedShaders
[i
] == NULL
)
5833 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
5834 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
5835 const struct gl_shader_compiler_options
*options
=
5836 &ctx
->Const
.ShaderCompilerOptions
[stage
];
5837 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
5838 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
5839 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
5840 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
5841 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
5843 /* If there are forms of indirect addressing that the driver
5844 * cannot handle, perform the lowering pass.
5846 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
5847 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
5848 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
5849 options
->EmitNoIndirectInput
,
5850 options
->EmitNoIndirectOutput
,
5851 options
->EmitNoIndirectTemp
,
5852 options
->EmitNoIndirectUniform
);
5855 if (ctx
->Extensions
.ARB_shading_language_packing
) {
5856 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
5857 LOWER_UNPACK_SNORM_2x16
|
5858 LOWER_PACK_UNORM_2x16
|
5859 LOWER_UNPACK_UNORM_2x16
|
5860 LOWER_PACK_SNORM_4x8
|
5861 LOWER_UNPACK_SNORM_4x8
|
5862 LOWER_UNPACK_UNORM_4x8
|
5863 LOWER_PACK_UNORM_4x8
;
5865 if (ctx
->Extensions
.ARB_gpu_shader5
)
5866 lower_inst
|= LOWER_PACK_USE_BFI
|
5868 if (!ctx
->st
->has_half_float_packing
)
5869 lower_inst
|= LOWER_PACK_HALF_2x16
|
5870 LOWER_UNPACK_HALF_2x16
;
5872 lower_packing_builtins(ir
, lower_inst
);
5875 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
5876 lower_offset_arrays(ir
);
5877 do_mat_op_to_vec(ir
);
5878 lower_instructions(ir
,
5884 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
5887 (have_dround
? 0 : DOPS_TO_DFRAC
) |
5888 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
5889 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
5890 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
5892 do_vec_index_to_cond_assign(ir
);
5893 lower_vector_insert(ir
, true);
5894 lower_quadop_vector(ir
, false);
5896 if (options
->MaxIfDepth
== 0) {
5903 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
5905 progress
= do_common_optimization(ir
, true, true, options
,
5906 ctx
->Const
.NativeIntegers
)
5909 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
5913 validate_ir_tree(ir
);
5916 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5917 struct gl_program
*linked_prog
;
5919 if (prog
->_LinkedShaders
[i
] == NULL
)
5922 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
5925 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5927 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
5928 _mesa_shader_stage_to_program(i
),
5930 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5932 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5937 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5940 st_dump_program_for_shader_db(ctx
, prog
);
5945 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
5946 const GLuint outputMapping
[],
5947 struct pipe_stream_output_info
*so
)
5950 struct gl_transform_feedback_info
*info
=
5951 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
5953 for (i
= 0; i
< info
->NumOutputs
; i
++) {
5954 so
->output
[i
].register_index
=
5955 outputMapping
[info
->Outputs
[i
].OutputRegister
];
5956 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
5957 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
5958 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
5959 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
5960 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
5963 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
5964 so
->stride
[i
] = info
->BufferStride
[i
];
5966 so
->num_outputs
= info
->NumOutputs
;