2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "glsl_parser_extras.h"
36 #include "ir_optimization.h"
38 #include "main/errors.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "main/shaderapi.h"
42 #include "program/prog_instruction.h"
43 #include "program/sampler.h"
45 #include "pipe/p_context.h"
46 #include "pipe/p_screen.h"
47 #include "tgsi/tgsi_ureg.h"
48 #include "tgsi/tgsi_info.h"
49 #include "util/u_math.h"
50 #include "util/u_memory.h"
51 #include "st_program.h"
52 #include "st_mesa_to_tgsi.h"
55 #define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
56 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
57 (1 << PROGRAM_CONSTANT) | \
58 (1 << PROGRAM_UNIFORM))
60 #define MAX_GLSL_TEXTURE_OFFSET 4
65 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to TGSI ureg_src.
72 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
84 this->reladdr2
= NULL
;
85 this->has_index2
= false;
86 this->double_reg2
= false;
90 st_src_reg(gl_register_file file
, int index
, int type
)
96 this->swizzle
= SWIZZLE_XYZW
;
99 this->reladdr2
= NULL
;
100 this->has_index2
= false;
101 this->double_reg2
= false;
105 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
110 this->index2D
= index2D
;
111 this->swizzle
= SWIZZLE_XYZW
;
113 this->reladdr
= NULL
;
114 this->reladdr2
= NULL
;
115 this->has_index2
= false;
116 this->double_reg2
= false;
122 this->type
= GLSL_TYPE_ERROR
;
123 this->file
= PROGRAM_UNDEFINED
;
128 this->reladdr
= NULL
;
129 this->reladdr2
= NULL
;
130 this->has_index2
= false;
131 this->double_reg2
= false;
135 explicit st_src_reg(st_dst_reg reg
);
137 gl_register_file file
; /**< PROGRAM_* from Mesa */
138 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
140 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
141 int negate
; /**< NEGATE_XYZW mask from mesa */
142 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
143 /** Register index should be offset by the integer in this reg. */
145 st_src_reg
*reladdr2
;
148 * Is this the second half of a double register pair?
149 * currently used for input mapping only.
157 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
162 this->writemask
= writemask
;
163 this->cond_mask
= COND_TR
;
164 this->reladdr
= NULL
;
165 this->reladdr2
= NULL
;
166 this->has_index2
= false;
171 st_dst_reg(gl_register_file file
, int writemask
, int type
)
176 this->writemask
= writemask
;
177 this->cond_mask
= COND_TR
;
178 this->reladdr
= NULL
;
179 this->reladdr2
= NULL
;
180 this->has_index2
= false;
187 this->type
= GLSL_TYPE_ERROR
;
188 this->file
= PROGRAM_UNDEFINED
;
192 this->cond_mask
= COND_TR
;
193 this->reladdr
= NULL
;
194 this->reladdr2
= NULL
;
195 this->has_index2
= false;
199 explicit st_dst_reg(st_src_reg reg
);
201 gl_register_file file
; /**< PROGRAM_* from Mesa */
202 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
204 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
206 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
207 /** Register index should be offset by the integer in this reg. */
209 st_src_reg
*reladdr2
;
214 st_src_reg::st_src_reg(st_dst_reg reg
)
216 this->type
= reg
.type
;
217 this->file
= reg
.file
;
218 this->index
= reg
.index
;
219 this->swizzle
= SWIZZLE_XYZW
;
221 this->reladdr
= reg
.reladdr
;
222 this->index2D
= reg
.index2D
;
223 this->reladdr2
= reg
.reladdr2
;
224 this->has_index2
= reg
.has_index2
;
225 this->double_reg2
= false;
226 this->array_id
= reg
.array_id
;
229 st_dst_reg::st_dst_reg(st_src_reg reg
)
231 this->type
= reg
.type
;
232 this->file
= reg
.file
;
233 this->index
= reg
.index
;
234 this->writemask
= WRITEMASK_XYZW
;
235 this->cond_mask
= COND_TR
;
236 this->reladdr
= reg
.reladdr
;
237 this->index2D
= reg
.index2D
;
238 this->reladdr2
= reg
.reladdr2
;
239 this->has_index2
= reg
.has_index2
;
240 this->array_id
= reg
.array_id
;
243 class glsl_to_tgsi_instruction
: public exec_node
{
245 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
250 /** Pointer to the ir source this tree came from for debugging */
252 GLboolean cond_update
;
254 st_src_reg sampler
; /**< sampler register */
255 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
256 int tex_target
; /**< One of TEXTURE_*_INDEX */
257 glsl_base_type tex_type
;
258 GLboolean tex_shadow
;
260 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
261 unsigned tex_offset_num_offset
;
262 int dead_mask
; /**< Used in dead code elimination */
264 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
265 const struct tgsi_opcode_info
*info
;
268 class variable_storage
: public exec_node
{
270 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
271 unsigned array_id
= 0)
272 : file(file
), index(index
), var(var
), array_id(array_id
)
277 gl_register_file file
;
279 ir_variable
*var
; /* variable that maps to this, if any */
283 class immediate_storage
: public exec_node
{
285 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
287 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
288 this->size32
= size32
;
292 /* doubles are stored across 2 gl_constant_values */
293 gl_constant_value values
[4];
294 int size32
; /**< Number of 32-bit components (1-4) */
295 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
298 class function_entry
: public exec_node
{
300 ir_function_signature
*sig
;
303 * identifier of this function signature used by the program.
305 * At the point that TGSI instructions for function calls are
306 * generated, we don't know the address of the first instruction of
307 * the function body. So we make the BranchTarget that is called a
308 * small integer and rewrite them during set_branchtargets().
313 * Pointer to first instruction of the function body.
315 * Set during function body emits after main() is processed.
317 glsl_to_tgsi_instruction
*bgn_inst
;
320 * Index of the first instruction of the function body in actual TGSI.
322 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
326 /** Storage for the return value. */
327 st_src_reg return_reg
;
330 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
331 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
339 struct rename_reg_pair
{
344 struct glsl_to_tgsi_visitor
: public ir_visitor
{
346 glsl_to_tgsi_visitor();
347 ~glsl_to_tgsi_visitor();
349 function_entry
*current_function
;
351 struct gl_context
*ctx
;
352 struct gl_program
*prog
;
353 struct gl_shader_program
*shader_program
;
354 struct gl_shader
*shader
;
355 struct gl_shader_compiler_options
*options
;
359 unsigned *array_sizes
;
360 unsigned max_num_arrays
;
363 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
364 unsigned num_input_arrays
;
365 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
366 unsigned num_output_arrays
;
368 int num_address_regs
;
370 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
371 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
372 bool indirect_addr_consts
;
373 int wpos_transform_const
;
376 bool native_integers
;
380 variable_storage
*find_variable_storage(ir_variable
*var
);
382 int add_constant(gl_register_file file
, gl_constant_value values
[8],
383 int size
, int datatype
, GLuint
*swizzle_out
);
385 function_entry
*get_function_signature(ir_function_signature
*sig
);
387 st_src_reg
get_temp(const glsl_type
*type
);
388 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
390 st_src_reg
st_src_reg_for_double(double val
);
391 st_src_reg
st_src_reg_for_float(float val
);
392 st_src_reg
st_src_reg_for_int(int val
);
393 st_src_reg
st_src_reg_for_type(int type
, int val
);
396 * \name Visit methods
398 * As typical for the visitor pattern, there must be one \c visit method for
399 * each concrete subclass of \c ir_instruction. Virtual base classes within
400 * the hierarchy should not have \c visit methods.
403 virtual void visit(ir_variable
*);
404 virtual void visit(ir_loop
*);
405 virtual void visit(ir_loop_jump
*);
406 virtual void visit(ir_function_signature
*);
407 virtual void visit(ir_function
*);
408 virtual void visit(ir_expression
*);
409 virtual void visit(ir_swizzle
*);
410 virtual void visit(ir_dereference_variable
*);
411 virtual void visit(ir_dereference_array
*);
412 virtual void visit(ir_dereference_record
*);
413 virtual void visit(ir_assignment
*);
414 virtual void visit(ir_constant
*);
415 virtual void visit(ir_call
*);
416 virtual void visit(ir_return
*);
417 virtual void visit(ir_discard
*);
418 virtual void visit(ir_texture
*);
419 virtual void visit(ir_if
*);
420 virtual void visit(ir_emit_vertex
*);
421 virtual void visit(ir_end_primitive
*);
422 virtual void visit(ir_barrier
*);
427 /** List of variable_storage */
430 /** List of immediate_storage */
431 exec_list immediates
;
432 unsigned num_immediates
;
434 /** List of function_entry */
435 exec_list function_signatures
;
436 int next_signature_id
;
438 /** List of glsl_to_tgsi_instruction */
439 exec_list instructions
;
441 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
442 st_dst_reg dst
= undef_dst
,
443 st_src_reg src0
= undef_src
,
444 st_src_reg src1
= undef_src
,
445 st_src_reg src2
= undef_src
,
446 st_src_reg src3
= undef_src
);
448 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
449 st_dst_reg dst
, st_dst_reg dst1
,
450 st_src_reg src0
= undef_src
,
451 st_src_reg src1
= undef_src
,
452 st_src_reg src2
= undef_src
,
453 st_src_reg src3
= undef_src
);
455 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
457 st_src_reg src0
, st_src_reg src1
);
460 * Emit the correct dot-product instruction for the type of arguments
462 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
468 void emit_scalar(ir_instruction
*ir
, unsigned op
,
469 st_dst_reg dst
, st_src_reg src0
);
471 void emit_scalar(ir_instruction
*ir
, unsigned op
,
472 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
474 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
476 bool try_emit_mad(ir_expression
*ir
,
478 bool try_emit_mad_for_and_not(ir_expression
*ir
,
481 void emit_swz(ir_expression
*ir
);
483 bool process_move_condition(ir_rvalue
*ir
);
485 void simplify_cmp(void);
487 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
488 void get_first_temp_read(int *first_reads
);
489 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
490 void get_last_temp_write(int *last_writes
);
492 void copy_propagate(void);
493 int eliminate_dead_code(void);
495 void merge_two_dsts(void);
496 void merge_registers(void);
497 void renumber_registers(void);
499 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
500 st_dst_reg
*l
, st_src_reg
*r
,
501 st_src_reg
*cond
, bool cond_swap
);
506 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
507 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
508 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
511 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
514 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
518 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
521 prog
->LinkStatus
= GL_FALSE
;
525 swizzle_for_size(int size
)
527 static const int size_swizzles
[4] = {
528 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
529 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
530 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
531 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
534 assert((size
>= 1) && (size
<= 4));
535 return size_swizzles
[size
- 1];
539 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
541 return op
->info
->num_dst
;
545 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
547 return op
->info
->is_tex
? op
->info
->num_src
- 1 : op
->info
->num_src
;
550 glsl_to_tgsi_instruction
*
551 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
552 st_dst_reg dst
, st_dst_reg dst1
,
553 st_src_reg src0
, st_src_reg src1
,
554 st_src_reg src2
, st_src_reg src3
)
556 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
557 int num_reladdr
= 0, i
, j
;
559 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
561 /* If we have to do relative addressing, we want to load the ARL
562 * reg directly for one of the regs, and preload the other reladdr
563 * sources into temps.
565 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
566 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
567 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
568 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
569 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
570 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
572 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
573 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
574 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
575 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
577 if (dst
.reladdr
|| dst
.reladdr2
) {
579 emit_arl(ir
, address_reg
, *dst
.reladdr
);
581 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
585 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
588 assert(num_reladdr
== 0);
591 inst
->info
= tgsi_get_opcode_info(op
);
600 /* default to float, for paths where this is not initialized
601 * (since 0==UINT which is likely wrong):
603 inst
->tex_type
= GLSL_TYPE_FLOAT
;
605 inst
->function
= NULL
;
607 /* Update indirect addressing status used by TGSI */
608 if (dst
.reladdr
|| dst
.reladdr2
) {
610 case PROGRAM_STATE_VAR
:
611 case PROGRAM_CONSTANT
:
612 case PROGRAM_UNIFORM
:
613 this->indirect_addr_consts
= true;
615 case PROGRAM_IMMEDIATE
:
616 assert(!"immediates should not have indirect addressing");
623 for (i
= 0; i
< 4; i
++) {
624 if(inst
->src
[i
].reladdr
) {
625 switch(inst
->src
[i
].file
) {
626 case PROGRAM_STATE_VAR
:
627 case PROGRAM_CONSTANT
:
628 case PROGRAM_UNIFORM
:
629 this->indirect_addr_consts
= true;
631 case PROGRAM_IMMEDIATE
:
632 assert(!"immediates should not have indirect addressing");
641 this->instructions
.push_tail(inst
);
644 * This section contains the double processing.
645 * GLSL just represents doubles as single channel values,
646 * however most HW and TGSI represent doubles as pairs of register channels.
648 * so we have to fixup destination writemask/index and src swizzle/indexes.
649 * dest writemasks need to translate from single channel write mask
650 * to a dual-channel writemask, but also need to modify the index,
651 * if we are touching the Z,W fields in the pre-translated writemask.
653 * src channels have similiar index modifications along with swizzle
654 * changes to we pick the XY, ZW pairs from the correct index.
656 * GLSL [0].x -> TGSI [0].xy
657 * GLSL [0].y -> TGSI [0].zw
658 * GLSL [0].z -> TGSI [1].xy
659 * GLSL [0].w -> TGSI [1].zw
661 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
|| inst
->dst
[1].type
== GLSL_TYPE_DOUBLE
||
662 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
663 glsl_to_tgsi_instruction
*dinst
= NULL
;
664 int initial_src_swz
[4], initial_src_idx
[4];
665 int initial_dst_idx
[2], initial_dst_writemask
[2];
666 /* select the writemask for dst0 or dst1 */
667 unsigned writemask
= inst
->dst
[0].file
== PROGRAM_UNDEFINED
? inst
->dst
[1].writemask
: inst
->dst
[0].writemask
;
669 /* copy out the writemask, index and swizzles for all src/dsts. */
670 for (j
= 0; j
< 2; j
++) {
671 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
672 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
675 for (j
= 0; j
< 4; j
++) {
676 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
677 initial_src_idx
[j
] = inst
->src
[j
].index
;
681 * scan all the components in the dst writemask
682 * generate an instruction for each of them if required.
686 int i
= u_bit_scan(&writemask
);
688 /* first time use previous instruction */
692 /* create a new instructions for subsequent attempts */
693 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
697 this->instructions
.push_tail(dinst
);
700 /* modify the destination if we are splitting */
701 for (j
= 0; j
< 2; j
++) {
702 if (dinst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
) {
703 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
704 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
706 dinst
->dst
[j
].index
++;
708 /* if we aren't writing to a double, just get the bit of the initial writemask
710 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
714 /* modify the src registers */
715 for (j
= 0; j
< 4; j
++) {
716 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
718 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
719 dinst
->src
[j
].index
= initial_src_idx
[j
];
721 dinst
->src
[j
].double_reg2
= true;
722 dinst
->src
[j
].index
++;
726 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
728 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
731 /* some opcodes are special case in what they use as sources
732 - F2D is a float src0, DLDEXP is integer src1 */
733 if (op
== TGSI_OPCODE_F2D
||
734 op
== TGSI_OPCODE_DLDEXP
||
735 (op
== TGSI_OPCODE_UCMP
&& dinst
->dst
[0].type
== GLSL_TYPE_DOUBLE
)) {
736 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
748 glsl_to_tgsi_instruction
*
749 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
751 st_src_reg src0
, st_src_reg src1
,
752 st_src_reg src2
, st_src_reg src3
)
754 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
758 * Determines whether to use an integer, unsigned integer, or float opcode
759 * based on the operands and input opcode, then emits the result.
762 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
764 st_src_reg src0
, st_src_reg src1
)
766 int type
= GLSL_TYPE_FLOAT
;
768 if (op
== TGSI_OPCODE_MOV
)
771 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
772 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
773 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
774 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
776 if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
777 type
= GLSL_TYPE_DOUBLE
;
778 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
779 type
= GLSL_TYPE_FLOAT
;
780 else if (native_integers
)
781 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
783 #define case5(c, f, i, u, d) \
784 case TGSI_OPCODE_##c: \
785 if (type == GLSL_TYPE_DOUBLE) \
786 op = TGSI_OPCODE_##d; \
787 else if (type == GLSL_TYPE_INT) \
788 op = TGSI_OPCODE_##i; \
789 else if (type == GLSL_TYPE_UINT) \
790 op = TGSI_OPCODE_##u; \
792 op = TGSI_OPCODE_##f; \
795 #define case4(c, f, i, u) \
796 case TGSI_OPCODE_##c: \
797 if (type == GLSL_TYPE_INT) \
798 op = TGSI_OPCODE_##i; \
799 else if (type == GLSL_TYPE_UINT) \
800 op = TGSI_OPCODE_##u; \
802 op = TGSI_OPCODE_##f; \
805 #define case3(f, i, u) case4(f, f, i, u)
806 #define case4d(f, i, u, d) case5(f, f, i, u, d)
807 #define case3fid(f, i, d) case5(f, f, i, i, d)
808 #define case2fi(f, i) case4(f, f, i, i)
809 #define case2iu(i, u) case4(i, LAST, i, u)
811 #define casecomp(c, f, i, u, d) \
812 case TGSI_OPCODE_##c: \
813 if (type == GLSL_TYPE_DOUBLE) \
814 op = TGSI_OPCODE_##d; \
815 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
816 op = TGSI_OPCODE_##i; \
817 else if (type == GLSL_TYPE_UINT) \
818 op = TGSI_OPCODE_##u; \
819 else if (native_integers) \
820 op = TGSI_OPCODE_##f; \
822 op = TGSI_OPCODE_##c; \
826 case3fid(ADD
, UADD
, DADD
);
827 case3fid(MUL
, UMUL
, DMUL
);
828 case3fid(MAD
, UMAD
, DMAD
);
829 case3fid(FMA
, UMAD
, DFMA
);
830 case3(DIV
, IDIV
, UDIV
);
831 case4d(MAX
, IMAX
, UMAX
, DMAX
);
832 case4d(MIN
, IMIN
, UMIN
, DMIN
);
835 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
836 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
837 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
838 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
842 case3fid(SSG
, ISSG
, DSSG
);
843 case3fid(ABS
, IABS
, DABS
);
847 case2iu(IMUL_HI
, UMUL_HI
);
849 case3fid(SQRT
, SQRT
, DSQRT
);
851 case3fid(RCP
, RCP
, DRCP
);
852 case3fid(RSQ
, RSQ
, DRSQ
);
854 case3fid(FRC
, FRC
, DFRAC
);
855 case3fid(TRUNC
, TRUNC
, DTRUNC
);
856 case3fid(CEIL
, CEIL
, DCEIL
);
857 case3fid(FLR
, FLR
, DFLR
);
858 case3fid(ROUND
, ROUND
, DROUND
);
863 assert(op
!= TGSI_OPCODE_LAST
);
867 glsl_to_tgsi_instruction
*
868 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
869 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
872 static const unsigned dot_opcodes
[] = {
873 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
876 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
880 * Emits TGSI scalar opcodes to produce unique answers across channels.
882 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
883 * channel determines the result across all channels. So to do a vec4
884 * of this operation, we want to emit a scalar per source channel used
885 * to produce dest channels.
888 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
890 st_src_reg orig_src0
, st_src_reg orig_src1
)
893 int done_mask
= ~dst
.writemask
;
895 /* TGSI RCP is a scalar operation splatting results to all channels,
896 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
899 for (i
= 0; i
< 4; i
++) {
900 GLuint this_mask
= (1 << i
);
901 st_src_reg src0
= orig_src0
;
902 st_src_reg src1
= orig_src1
;
904 if (done_mask
& this_mask
)
907 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
908 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
909 for (j
= i
+ 1; j
< 4; j
++) {
910 /* If there is another enabled component in the destination that is
911 * derived from the same inputs, generate its value on this pass as
914 if (!(done_mask
& (1 << j
)) &&
915 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
916 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
917 this_mask
|= (1 << j
);
920 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
921 src0_swiz
, src0_swiz
);
922 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
923 src1_swiz
, src1_swiz
);
925 dst
.writemask
= this_mask
;
926 emit_asm(ir
, op
, dst
, src0
, src1
);
927 done_mask
|= this_mask
;
932 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
933 st_dst_reg dst
, st_src_reg src0
)
935 st_src_reg undef
= undef_src
;
937 undef
.swizzle
= SWIZZLE_XXXX
;
939 emit_scalar(ir
, op
, dst
, src0
, undef
);
943 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
944 st_dst_reg dst
, st_src_reg src0
)
946 int op
= TGSI_OPCODE_ARL
;
948 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
949 op
= TGSI_OPCODE_UARL
;
951 assert(dst
.file
== PROGRAM_ADDRESS
);
952 if (dst
.index
>= this->num_address_regs
)
953 this->num_address_regs
= dst
.index
+ 1;
955 emit_asm(NULL
, op
, dst
, src0
);
959 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
960 gl_constant_value values
[8], int size
, int datatype
,
963 if (file
== PROGRAM_CONSTANT
) {
964 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
965 size
, datatype
, swizzle_out
);
968 assert(file
== PROGRAM_IMMEDIATE
);
971 immediate_storage
*entry
;
972 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
975 /* Search immediate storage to see if we already have an identical
976 * immediate that we can use instead of adding a duplicate entry.
978 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
979 immediate_storage
*tmp
= entry
;
981 for (i
= 0; i
* 4 < size32
; i
++) {
982 int slot_size
= MIN2(size32
- (i
* 4), 4);
983 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
985 if (memcmp(tmp
->values
, &values
[i
* 4],
986 slot_size
* sizeof(gl_constant_value
)))
989 /* Everything matches, keep going until the full size is matched */
990 tmp
= (immediate_storage
*)tmp
->next
;
993 /* The full value matched */
1000 for (i
= 0; i
* 4 < size32
; i
++) {
1001 int slot_size
= MIN2(size32
- (i
* 4), 4);
1002 /* Add this immediate to the list. */
1003 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1004 this->immediates
.push_tail(entry
);
1005 this->num_immediates
++;
1011 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1013 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1014 union gl_constant_value uval
;
1017 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1023 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1025 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1026 union gl_constant_value uval
[2];
1028 uval
[0].u
= *(uint32_t *)&val
;
1029 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1030 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1036 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1038 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1039 union gl_constant_value uval
;
1041 assert(native_integers
);
1044 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1050 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1052 if (native_integers
)
1053 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1054 st_src_reg_for_int(val
);
1056 return st_src_reg_for_float(val
);
1060 type_size(const struct glsl_type
*type
)
1065 switch (type
->base_type
) {
1066 case GLSL_TYPE_UINT
:
1068 case GLSL_TYPE_FLOAT
:
1069 case GLSL_TYPE_BOOL
:
1070 if (type
->is_matrix()) {
1071 return type
->matrix_columns
;
1073 /* Regardless of size of vector, it gets a vec4. This is bad
1074 * packing for things like floats, but otherwise arrays become a
1075 * mess. Hopefully a later pass over the code can pack scalars
1076 * down if appropriate.
1081 case GLSL_TYPE_DOUBLE
:
1082 if (type
->is_matrix()) {
1083 if (type
->vector_elements
<= 2)
1084 return type
->matrix_columns
;
1086 return type
->matrix_columns
* 2;
1088 /* For doubles if we have a double or dvec2 they fit in one
1089 * vec4, else they need 2 vec4s.
1091 if (type
->vector_elements
<= 2)
1097 case GLSL_TYPE_ARRAY
:
1098 assert(type
->length
> 0);
1099 return type_size(type
->fields
.array
) * type
->length
;
1100 case GLSL_TYPE_STRUCT
:
1102 for (i
= 0; i
< type
->length
; i
++) {
1103 size
+= type_size(type
->fields
.structure
[i
].type
);
1106 case GLSL_TYPE_SAMPLER
:
1107 case GLSL_TYPE_IMAGE
:
1108 case GLSL_TYPE_SUBROUTINE
:
1109 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1113 case GLSL_TYPE_ATOMIC_UINT
:
1114 case GLSL_TYPE_INTERFACE
:
1115 case GLSL_TYPE_VOID
:
1116 case GLSL_TYPE_ERROR
:
1117 assert(!"Invalid type in type_size");
1125 * If the given GLSL type is an array or matrix or a structure containing
1126 * an array/matrix member, return true. Else return false.
1128 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1129 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1130 * we have an array that might be indexed with a variable, we need to use
1131 * the later storage type.
1134 type_has_array_or_matrix(const glsl_type
*type
)
1136 if (type
->is_array() || type
->is_matrix())
1139 if (type
->is_record()) {
1140 for (unsigned i
= 0; i
< type
->length
; i
++) {
1141 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1152 * In the initial pass of codegen, we assign temporary numbers to
1153 * intermediate results. (not SSA -- variable assignments will reuse
1157 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1161 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1165 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1166 if (next_array
>= max_num_arrays
) {
1167 max_num_arrays
+= 32;
1168 array_sizes
= (unsigned*)
1169 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1172 src
.file
= PROGRAM_ARRAY
;
1173 src
.index
= next_array
<< 16 | 0x8000;
1174 array_sizes
[next_array
] = type_size(type
);
1178 src
.file
= PROGRAM_TEMPORARY
;
1179 src
.index
= next_temp
;
1180 next_temp
+= type_size(type
);
1183 if (type
->is_array() || type
->is_record()) {
1184 src
.swizzle
= SWIZZLE_NOOP
;
1186 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1193 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1196 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1197 if (entry
->var
== var
)
1205 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1207 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1208 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1210 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1211 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1214 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1216 const ir_state_slot
*const slots
= ir
->get_state_slots();
1217 assert(slots
!= NULL
);
1219 /* Check if this statevar's setup in the STATE file exactly
1220 * matches how we'll want to reference it as a
1221 * struct/array/whatever. If not, then we need to move it into
1222 * temporary storage and hope that it'll get copy-propagated
1225 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1226 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1231 variable_storage
*storage
;
1233 if (i
== ir
->get_num_state_slots()) {
1234 /* We'll set the index later. */
1235 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1236 this->variables
.push_tail(storage
);
1240 /* The variable_storage constructor allocates slots based on the size
1241 * of the type. However, this had better match the number of state
1242 * elements that we're going to copy into the new temporary.
1244 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1246 dst
= st_dst_reg(get_temp(ir
->type
));
1248 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1250 this->variables
.push_tail(storage
);
1254 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1255 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1256 (gl_state_index
*)slots
[i
].tokens
);
1258 if (storage
->file
== PROGRAM_STATE_VAR
) {
1259 if (storage
->index
== -1) {
1260 storage
->index
= index
;
1262 assert(index
== storage
->index
+ (int)i
);
1265 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1266 * the data being moved since MOV does not care about the type of
1267 * data it is moving, and we don't want to declare registers with
1268 * array or struct types.
1270 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1271 src
.swizzle
= slots
[i
].swizzle
;
1272 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1273 /* even a float takes up a whole vec4 reg in a struct/array. */
1278 if (storage
->file
== PROGRAM_TEMPORARY
&&
1279 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1280 fail_link(this->shader_program
,
1281 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1282 ir
->name
, dst
.index
- storage
->index
,
1283 type_size(ir
->type
));
1289 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1291 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1293 visit_exec_list(&ir
->body_instructions
, this);
1295 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1299 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1302 case ir_loop_jump::jump_break
:
1303 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1305 case ir_loop_jump::jump_continue
:
1306 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1313 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1320 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1322 /* Ignore function bodies other than main() -- we shouldn't see calls to
1323 * them since they should all be inlined before we get to glsl_to_tgsi.
1325 if (strcmp(ir
->name
, "main") == 0) {
1326 const ir_function_signature
*sig
;
1329 sig
= ir
->matching_signature(NULL
, &empty
, false);
1333 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1340 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1342 int nonmul_operand
= 1 - mul_operand
;
1344 st_dst_reg result_dst
;
1346 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1347 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1350 expr
->operands
[0]->accept(this);
1352 expr
->operands
[1]->accept(this);
1354 ir
->operands
[nonmul_operand
]->accept(this);
1357 this->result
= get_temp(ir
->type
);
1358 result_dst
= st_dst_reg(this->result
);
1359 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1360 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1366 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1368 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1369 * implemented using multiplication, and logical-or is implemented using
1370 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1371 * As result, the logical expression (a & !b) can be rewritten as:
1375 * - (a * 1) - (a * b)
1379 * This final expression can be implemented as a single MAD(a, -b, a)
1383 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1385 const int other_operand
= 1 - try_operand
;
1388 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1389 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1392 ir
->operands
[other_operand
]->accept(this);
1394 expr
->operands
[0]->accept(this);
1397 b
.negate
= ~b
.negate
;
1399 this->result
= get_temp(ir
->type
);
1400 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1406 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1407 st_src_reg
*reg
, int *num_reladdr
)
1409 if (!reg
->reladdr
&& !reg
->reladdr2
)
1412 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1413 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1415 if (*num_reladdr
!= 1) {
1416 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1418 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1426 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1428 unsigned int operand
;
1429 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1430 st_src_reg result_src
;
1431 st_dst_reg result_dst
;
1433 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1435 if (ir
->operation
== ir_binop_add
) {
1436 if (try_emit_mad(ir
, 1))
1438 if (try_emit_mad(ir
, 0))
1442 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1444 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1445 if (try_emit_mad_for_and_not(ir
, 1))
1447 if (try_emit_mad_for_and_not(ir
, 0))
1451 if (ir
->operation
== ir_quadop_vector
)
1452 assert(!"ir_quadop_vector should have been lowered");
1454 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1455 this->result
.file
= PROGRAM_UNDEFINED
;
1456 ir
->operands
[operand
]->accept(this);
1457 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1458 printf("Failed to get tree for expression operand:\n");
1459 ir
->operands
[operand
]->print();
1463 op
[operand
] = this->result
;
1465 /* Matrix expression operands should have been broken down to vector
1466 * operations already.
1468 assert(!ir
->operands
[operand
]->type
->is_matrix());
1471 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1472 if (ir
->operands
[1]) {
1473 vector_elements
= MAX2(vector_elements
,
1474 ir
->operands
[1]->type
->vector_elements
);
1477 this->result
.file
= PROGRAM_UNDEFINED
;
1479 /* Storage for our result. Ideally for an assignment we'd be using
1480 * the actual storage for the result here, instead.
1482 result_src
= get_temp(ir
->type
);
1483 /* convenience for the emit functions below. */
1484 result_dst
= st_dst_reg(result_src
);
1485 /* Limit writes to the channels that will be used by result_src later.
1486 * This does limit this temp's use as a temporary for multi-instruction
1489 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1491 switch (ir
->operation
) {
1492 case ir_unop_logic_not
:
1493 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1494 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1496 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1497 * older GPUs implement SEQ using multiple instructions (i915 uses two
1498 * SGE instructions and a MUL instruction). Since our logic values are
1499 * 0.0 and 1.0, 1-x also implements !x.
1501 op
[0].negate
= ~op
[0].negate
;
1502 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1506 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1507 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1508 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1509 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1511 op
[0].negate
= ~op
[0].negate
;
1515 case ir_unop_subroutine_to_int
:
1516 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1519 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1522 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1525 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1529 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1533 assert(!"not reached: should be handled by ir_explog_to_explog2");
1536 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1539 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1542 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1544 case ir_unop_saturate
: {
1545 glsl_to_tgsi_instruction
*inst
;
1546 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1547 inst
->saturate
= true;
1552 case ir_unop_dFdx_coarse
:
1553 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1555 case ir_unop_dFdx_fine
:
1556 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1559 case ir_unop_dFdy_coarse
:
1560 case ir_unop_dFdy_fine
:
1562 /* The X component contains 1 or -1 depending on whether the framebuffer
1563 * is a FBO or the window system buffer, respectively.
1564 * It is then multiplied with the source operand of DDY.
1566 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1567 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1569 unsigned transform_y_index
=
1570 _mesa_add_state_reference(this->prog
->Parameters
,
1573 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1575 glsl_type::vec4_type
);
1576 transform_y
.swizzle
= SWIZZLE_XXXX
;
1578 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1580 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1581 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1582 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1586 case ir_unop_frexp_sig
:
1587 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1590 case ir_unop_frexp_exp
:
1591 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1594 case ir_unop_noise
: {
1595 /* At some point, a motivated person could add a better
1596 * implementation of noise. Currently not even the nvidia
1597 * binary drivers do anything more than this. In any case, the
1598 * place to do this is in the GL state tracker, not the poor
1601 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1606 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1609 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1613 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1616 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1617 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1619 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1622 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1623 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1625 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1629 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1631 case ir_binop_greater
:
1632 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1634 case ir_binop_lequal
:
1635 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1637 case ir_binop_gequal
:
1638 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1640 case ir_binop_equal
:
1641 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1643 case ir_binop_nequal
:
1644 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1646 case ir_binop_all_equal
:
1647 /* "==" operator producing a scalar boolean. */
1648 if (ir
->operands
[0]->type
->is_vector() ||
1649 ir
->operands
[1]->type
->is_vector()) {
1650 st_src_reg temp
= get_temp(native_integers
?
1651 glsl_type::uvec4_type
:
1652 glsl_type::vec4_type
);
1654 if (native_integers
) {
1655 st_dst_reg temp_dst
= st_dst_reg(temp
);
1656 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1658 if (ir
->operands
[0]->type
->is_boolean() &&
1659 ir
->operands
[1]->as_constant() &&
1660 ir
->operands
[1]->as_constant()->is_one()) {
1661 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1663 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1666 /* Emit 1-3 AND operations to combine the SEQ results. */
1667 switch (ir
->operands
[0]->type
->vector_elements
) {
1671 temp_dst
.writemask
= WRITEMASK_Y
;
1672 temp1
.swizzle
= SWIZZLE_YYYY
;
1673 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1674 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1677 temp_dst
.writemask
= WRITEMASK_X
;
1678 temp1
.swizzle
= SWIZZLE_XXXX
;
1679 temp2
.swizzle
= SWIZZLE_YYYY
;
1680 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1681 temp_dst
.writemask
= WRITEMASK_Y
;
1682 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1683 temp2
.swizzle
= SWIZZLE_WWWW
;
1684 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1687 temp1
.swizzle
= SWIZZLE_XXXX
;
1688 temp2
.swizzle
= SWIZZLE_YYYY
;
1689 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1691 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1693 /* After the dot-product, the value will be an integer on the
1694 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1696 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1698 /* Negating the result of the dot-product gives values on the range
1699 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1700 * This is achieved using SGE.
1702 st_src_reg sge_src
= result_src
;
1703 sge_src
.negate
= ~sge_src
.negate
;
1704 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1707 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1710 case ir_binop_any_nequal
:
1711 /* "!=" operator producing a scalar boolean. */
1712 if (ir
->operands
[0]->type
->is_vector() ||
1713 ir
->operands
[1]->type
->is_vector()) {
1714 st_src_reg temp
= get_temp(native_integers
?
1715 glsl_type::uvec4_type
:
1716 glsl_type::vec4_type
);
1717 if (ir
->operands
[0]->type
->is_boolean() &&
1718 ir
->operands
[1]->as_constant() &&
1719 ir
->operands
[1]->as_constant()->is_zero()) {
1720 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1722 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1725 if (native_integers
) {
1726 st_dst_reg temp_dst
= st_dst_reg(temp
);
1727 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1729 /* Emit 1-3 OR operations to combine the SNE results. */
1730 switch (ir
->operands
[0]->type
->vector_elements
) {
1734 temp_dst
.writemask
= WRITEMASK_Y
;
1735 temp1
.swizzle
= SWIZZLE_YYYY
;
1736 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1737 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1740 temp_dst
.writemask
= WRITEMASK_X
;
1741 temp1
.swizzle
= SWIZZLE_XXXX
;
1742 temp2
.swizzle
= SWIZZLE_YYYY
;
1743 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1744 temp_dst
.writemask
= WRITEMASK_Y
;
1745 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1746 temp2
.swizzle
= SWIZZLE_WWWW
;
1747 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1750 temp1
.swizzle
= SWIZZLE_XXXX
;
1751 temp2
.swizzle
= SWIZZLE_YYYY
;
1752 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1754 /* After the dot-product, the value will be an integer on the
1755 * range [0,4]. Zero stays zero, and positive values become 1.0.
1757 glsl_to_tgsi_instruction
*const dp
=
1758 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1759 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1760 /* The clamping to [0,1] can be done for free in the fragment
1761 * shader with a saturate.
1763 dp
->saturate
= true;
1765 /* Negating the result of the dot-product gives values on the range
1766 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1767 * achieved using SLT.
1769 st_src_reg slt_src
= result_src
;
1770 slt_src
.negate
= ~slt_src
.negate
;
1771 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1775 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1779 case ir_binop_logic_xor
:
1780 if (native_integers
)
1781 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1783 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1786 case ir_binop_logic_or
: {
1787 if (native_integers
) {
1788 /* If integers are used as booleans, we can use an actual "or"
1791 assert(native_integers
);
1792 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1794 /* After the addition, the value will be an integer on the
1795 * range [0,2]. Zero stays zero, and positive values become 1.0.
1797 glsl_to_tgsi_instruction
*add
=
1798 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1799 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1800 /* The clamping to [0,1] can be done for free in the fragment
1801 * shader with a saturate if floats are being used as boolean values.
1803 add
->saturate
= true;
1805 /* Negating the result of the addition gives values on the range
1806 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1807 * is achieved using SLT.
1809 st_src_reg slt_src
= result_src
;
1810 slt_src
.negate
= ~slt_src
.negate
;
1811 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1817 case ir_binop_logic_and
:
1818 /* If native integers are disabled, the bool args are stored as float 0.0
1819 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1820 * actual AND opcode.
1822 if (native_integers
)
1823 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1825 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1829 assert(ir
->operands
[0]->type
->is_vector());
1830 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1831 emit_dp(ir
, result_dst
, op
[0], op
[1],
1832 ir
->operands
[0]->type
->vector_elements
);
1837 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1839 /* sqrt(x) = x * rsq(x). */
1840 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1841 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1842 /* For incoming channels <= 0, set the result to 0. */
1843 op
[0].negate
= ~op
[0].negate
;
1844 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1845 op
[0], result_src
, st_src_reg_for_float(0.0));
1849 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1852 if (native_integers
) {
1853 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1856 /* fallthrough to next case otherwise */
1858 if (native_integers
) {
1859 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1862 /* fallthrough to next case otherwise */
1865 /* Converting between signed and unsigned integers is a no-op. */
1869 if (native_integers
) {
1870 /* Booleans are stored as integers using ~0 for true and 0 for false.
1871 * GLSL requires that int(bool) return 1 for true and 0 for false.
1872 * This conversion is done with AND, but it could be done with NEG.
1874 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1876 /* Booleans and integers are both stored as floats when native
1877 * integers are disabled.
1883 if (native_integers
)
1884 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1886 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1889 if (native_integers
)
1890 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1892 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1894 case ir_unop_bitcast_f2i
:
1896 result_src
.type
= GLSL_TYPE_INT
;
1898 case ir_unop_bitcast_f2u
:
1900 result_src
.type
= GLSL_TYPE_UINT
;
1902 case ir_unop_bitcast_i2f
:
1903 case ir_unop_bitcast_u2f
:
1905 result_src
.type
= GLSL_TYPE_FLOAT
;
1908 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1911 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1914 if (native_integers
)
1915 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1917 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1920 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1923 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1926 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1928 case ir_unop_round_even
:
1929 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1932 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1936 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1939 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1942 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1945 case ir_unop_bit_not
:
1946 if (native_integers
) {
1947 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1951 if (native_integers
) {
1952 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1955 case ir_binop_lshift
:
1956 if (native_integers
) {
1957 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
1960 case ir_binop_rshift
:
1961 if (native_integers
) {
1962 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
1965 case ir_binop_bit_and
:
1966 if (native_integers
) {
1967 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1970 case ir_binop_bit_xor
:
1971 if (native_integers
) {
1972 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1975 case ir_binop_bit_or
:
1976 if (native_integers
) {
1977 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1981 assert(!"GLSL 1.30 features unsupported");
1984 case ir_binop_ubo_load
: {
1985 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1986 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1987 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1988 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
1989 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1992 cbuf
.type
= ir
->type
->base_type
;
1993 cbuf
.file
= PROGRAM_CONSTANT
;
1995 cbuf
.reladdr
= NULL
;
1998 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2000 if (const_offset_ir
) {
2001 /* Constant index into constant buffer */
2002 cbuf
.reladdr
= NULL
;
2003 cbuf
.index
= const_offset
/ 16;
2006 /* Relative/variable index into constant buffer */
2007 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2008 st_src_reg_for_int(4));
2009 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2010 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2013 if (const_uniform_block
) {
2014 /* Constant constant buffer */
2015 cbuf
.reladdr2
= NULL
;
2016 cbuf
.index2D
= const_block
;
2017 cbuf
.has_index2
= true;
2020 /* Relative/variable constant buffer */
2021 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2023 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2024 cbuf
.has_index2
= true;
2027 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2028 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2029 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2030 const_offset
% 16 / 8,
2031 const_offset
% 16 / 8,
2032 const_offset
% 16 / 8);
2034 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2035 const_offset
% 16 / 4,
2036 const_offset
% 16 / 4,
2037 const_offset
% 16 / 4);
2039 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2040 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2042 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2047 /* note: we have to reorder the three args here */
2048 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2051 if (this->ctx
->Const
.NativeIntegers
)
2052 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2054 op
[0].negate
= ~op
[0].negate
;
2055 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2058 case ir_triop_bitfield_extract
:
2059 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2061 case ir_quadop_bitfield_insert
:
2062 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2064 case ir_unop_bitfield_reverse
:
2065 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2067 case ir_unop_bit_count
:
2068 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2070 case ir_unop_find_msb
:
2071 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2073 case ir_unop_find_lsb
:
2074 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2076 case ir_binop_imul_high
:
2077 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2080 /* In theory, MAD is incorrect here. */
2082 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2084 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2086 case ir_unop_interpolate_at_centroid
:
2087 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2089 case ir_binop_interpolate_at_offset
:
2090 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2092 case ir_binop_interpolate_at_sample
:
2093 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2097 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2100 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2103 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2106 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2109 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2112 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2114 case ir_unop_unpack_double_2x32
:
2115 case ir_unop_pack_double_2x32
:
2116 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2119 case ir_binop_ldexp
:
2120 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2121 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2123 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2127 case ir_unop_pack_snorm_2x16
:
2128 case ir_unop_pack_unorm_2x16
:
2129 case ir_unop_pack_half_2x16
:
2130 case ir_unop_pack_snorm_4x8
:
2131 case ir_unop_pack_unorm_4x8
:
2133 case ir_unop_unpack_snorm_2x16
:
2134 case ir_unop_unpack_unorm_2x16
:
2135 case ir_unop_unpack_half_2x16
:
2136 case ir_unop_unpack_half_2x16_split_x
:
2137 case ir_unop_unpack_half_2x16_split_y
:
2138 case ir_unop_unpack_snorm_4x8
:
2139 case ir_unop_unpack_unorm_4x8
:
2141 case ir_binop_pack_half_2x16_split
:
2144 case ir_quadop_vector
:
2145 case ir_binop_vector_extract
:
2146 case ir_triop_vector_insert
:
2147 case ir_binop_carry
:
2148 case ir_binop_borrow
:
2149 case ir_unop_ssbo_unsized_array_length
:
2150 /* This operation is not supported, or should have already been handled.
2152 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2155 case ir_unop_get_buffer_size
:
2156 assert(!"Not implemented yet");
2160 this->result
= result_src
;
2165 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2171 /* Note that this is only swizzles in expressions, not those on the left
2172 * hand side of an assignment, which do write masking. See ir_assignment
2176 ir
->val
->accept(this);
2178 assert(src
.file
!= PROGRAM_UNDEFINED
);
2179 assert(ir
->type
->vector_elements
> 0);
2181 for (i
= 0; i
< 4; i
++) {
2182 if (i
< ir
->type
->vector_elements
) {
2185 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2188 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2191 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2194 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2198 /* If the type is smaller than a vec4, replicate the last
2201 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2205 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2210 /* Test if the variable is an array. Note that geometry and
2211 * tessellation shader inputs are outputs are always arrays (except
2212 * for patch inputs), so only the array element type is considered.
2215 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2217 const glsl_type
*type
= var
->type
;
2219 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2220 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2225 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2226 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2227 stage
== MESA_SHADER_TESS_CTRL
) &&
2229 if (!var
->type
->is_array())
2230 return false; /* a system value probably */
2232 type
= var
->type
->fields
.array
;
2236 return type
->is_array() || type
->is_matrix();
2240 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2242 variable_storage
*entry
= find_variable_storage(ir
->var
);
2243 ir_variable
*var
= ir
->var
;
2247 switch (var
->data
.mode
) {
2248 case ir_var_uniform
:
2249 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2250 var
->data
.location
);
2251 this->variables
.push_tail(entry
);
2253 case ir_var_shader_in
:
2254 /* The linker assigns locations for varyings and attributes,
2255 * including deprecated builtins (like gl_Color), user-assign
2256 * generic attributes (glBindVertexLocation), and
2257 * user-defined varyings.
2259 assert(var
->data
.location
!= -1);
2261 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2262 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2264 decl
->mesa_index
= var
->data
.location
;
2265 decl
->array_id
= num_input_arrays
+ 1;
2267 decl
->array_size
= type_size(var
->type
->fields
.array
);
2269 decl
->array_size
= type_size(var
->type
);
2272 entry
= new(mem_ctx
) variable_storage(var
,
2278 entry
= new(mem_ctx
) variable_storage(var
,
2280 var
->data
.location
);
2282 this->variables
.push_tail(entry
);
2284 case ir_var_shader_out
:
2285 assert(var
->data
.location
!= -1);
2287 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2288 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2290 decl
->mesa_index
= var
->data
.location
;
2291 decl
->array_id
= num_output_arrays
+ 1;
2293 decl
->array_size
= type_size(var
->type
->fields
.array
);
2295 decl
->array_size
= type_size(var
->type
);
2296 num_output_arrays
++;
2298 entry
= new(mem_ctx
) variable_storage(var
,
2304 entry
= new(mem_ctx
) variable_storage(var
,
2309 this->variables
.push_tail(entry
);
2311 case ir_var_system_value
:
2312 entry
= new(mem_ctx
) variable_storage(var
,
2313 PROGRAM_SYSTEM_VALUE
,
2314 var
->data
.location
);
2317 case ir_var_temporary
:
2318 st_src_reg src
= get_temp(var
->type
);
2320 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2321 this->variables
.push_tail(entry
);
2327 printf("Failed to make storage for %s\n", var
->name
);
2332 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2333 this->result
.array_id
= entry
->array_id
;
2334 if (!native_integers
)
2335 this->result
.type
= GLSL_TYPE_FLOAT
;
2339 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2340 GLbitfield64 usage_mask
,
2341 GLbitfield patch_usage_mask
)
2345 /* Fix array declarations by removing unused array elements at both ends
2346 * of the arrays. For example, mat4[3] where only mat[1] is used.
2348 for (i
= 0; i
< count
; i
++) {
2349 struct array_decl
*decl
= &arrays
[i
];
2351 /* Shrink the beginning. */
2352 for (j
= 0; j
< decl
->array_size
; j
++) {
2353 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2354 if (patch_usage_mask
&
2355 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2359 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2368 /* Shrink the end. */
2369 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2370 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2371 if (patch_usage_mask
&
2372 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2376 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2386 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2390 int element_size
= type_size(ir
->type
);
2393 index
= ir
->array_index
->constant_expression_value();
2395 ir
->array
->accept(this);
2398 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2399 switch (this->prog
->Target
) {
2400 case GL_TESS_CONTROL_PROGRAM_NV
:
2401 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2402 !ir
->variable_referenced()->data
.patch
;
2404 case GL_TESS_EVALUATION_PROGRAM_NV
:
2405 is_2D
= src
.file
== PROGRAM_INPUT
&&
2406 !ir
->variable_referenced()->data
.patch
;
2408 case GL_GEOMETRY_PROGRAM_NV
:
2409 is_2D
= src
.file
== PROGRAM_INPUT
;
2419 src
.index2D
= index
->value
.i
[0];
2420 src
.has_index2
= true;
2422 src
.index
+= index
->value
.i
[0] * element_size
;
2424 /* Variable index array dereference. It eats the "vec4" of the
2425 * base of the array and an index that offsets the TGSI register
2428 ir
->array_index
->accept(this);
2430 st_src_reg index_reg
;
2432 if (element_size
== 1) {
2433 index_reg
= this->result
;
2435 index_reg
= get_temp(native_integers
?
2436 glsl_type::int_type
: glsl_type::float_type
);
2438 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2439 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2442 /* If there was already a relative address register involved, add the
2443 * new and the old together to get the new offset.
2445 if (!is_2D
&& src
.reladdr
!= NULL
) {
2446 st_src_reg accum_reg
= get_temp(native_integers
?
2447 glsl_type::int_type
: glsl_type::float_type
);
2449 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2450 index_reg
, *src
.reladdr
);
2452 index_reg
= accum_reg
;
2456 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2457 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2459 src
.has_index2
= true;
2461 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2462 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2466 /* If the type is smaller than a vec4, replicate the last channel out. */
2467 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2468 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2470 src
.swizzle
= SWIZZLE_NOOP
;
2472 /* Change the register type to the element type of the array. */
2473 src
.type
= ir
->type
->base_type
;
2479 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2482 const glsl_type
*struct_type
= ir
->record
->type
;
2485 ir
->record
->accept(this);
2487 for (i
= 0; i
< struct_type
->length
; i
++) {
2488 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2490 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2493 /* If the type is smaller than a vec4, replicate the last channel out. */
2494 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2495 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2497 this->result
.swizzle
= SWIZZLE_NOOP
;
2499 this->result
.index
+= offset
;
2500 this->result
.type
= ir
->type
->base_type
;
2504 * We want to be careful in assignment setup to hit the actual storage
2505 * instead of potentially using a temporary like we might with the
2506 * ir_dereference handler.
2509 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2511 /* The LHS must be a dereference. If the LHS is a variable indexed array
2512 * access of a vector, it must be separated into a series conditional moves
2513 * before reaching this point (see ir_vec_index_to_cond_assign).
2515 assert(ir
->as_dereference());
2516 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2518 assert(!deref_array
->array
->type
->is_vector());
2521 /* Use the rvalue deref handler for the most part. We'll ignore
2522 * swizzles in it and write swizzles using writemask, though.
2525 return st_dst_reg(v
->result
);
2529 * Process the condition of a conditional assignment
2531 * Examines the condition of a conditional assignment to generate the optimal
2532 * first operand of a \c CMP instruction. If the condition is a relational
2533 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2534 * used as the source for the \c CMP instruction. Otherwise the comparison
2535 * is processed to a boolean result, and the boolean result is used as the
2536 * operand to the CMP instruction.
2539 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2541 ir_rvalue
*src_ir
= ir
;
2543 bool switch_order
= false;
2545 ir_expression
*const expr
= ir
->as_expression();
2547 if (native_integers
) {
2548 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2549 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2550 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2551 type
== GLSL_TYPE_BOOL
) {
2552 if (expr
->operation
== ir_binop_equal
) {
2553 if (expr
->operands
[0]->is_zero()) {
2554 src_ir
= expr
->operands
[1];
2555 switch_order
= true;
2557 else if (expr
->operands
[1]->is_zero()) {
2558 src_ir
= expr
->operands
[0];
2559 switch_order
= true;
2562 else if (expr
->operation
== ir_binop_nequal
) {
2563 if (expr
->operands
[0]->is_zero()) {
2564 src_ir
= expr
->operands
[1];
2566 else if (expr
->operands
[1]->is_zero()) {
2567 src_ir
= expr
->operands
[0];
2573 src_ir
->accept(this);
2574 return switch_order
;
2577 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2578 bool zero_on_left
= false;
2580 if (expr
->operands
[0]->is_zero()) {
2581 src_ir
= expr
->operands
[1];
2582 zero_on_left
= true;
2583 } else if (expr
->operands
[1]->is_zero()) {
2584 src_ir
= expr
->operands
[0];
2585 zero_on_left
= false;
2589 * (a < 0) T F F ( a < 0) T F F
2590 * (0 < a) F F T (-a < 0) F F T
2591 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2592 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2593 * (a > 0) F F T (-a < 0) F F T
2594 * (0 > a) T F F ( a < 0) T F F
2595 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2596 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2598 * Note that exchanging the order of 0 and 'a' in the comparison simply
2599 * means that the value of 'a' should be negated.
2602 switch (expr
->operation
) {
2604 switch_order
= false;
2605 negate
= zero_on_left
;
2608 case ir_binop_greater
:
2609 switch_order
= false;
2610 negate
= !zero_on_left
;
2613 case ir_binop_lequal
:
2614 switch_order
= true;
2615 negate
= !zero_on_left
;
2618 case ir_binop_gequal
:
2619 switch_order
= true;
2620 negate
= zero_on_left
;
2624 /* This isn't the right kind of comparison afterall, so make sure
2625 * the whole condition is visited.
2633 src_ir
->accept(this);
2635 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2636 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2637 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2638 * computing the condition.
2641 this->result
.negate
= ~this->result
.negate
;
2643 return switch_order
;
2647 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2648 st_dst_reg
*l
, st_src_reg
*r
,
2649 st_src_reg
*cond
, bool cond_swap
)
2651 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2652 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2653 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2659 if (type
->is_array()) {
2660 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2661 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2666 if (type
->is_matrix()) {
2667 const struct glsl_type
*vec_type
;
2669 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2670 type
->vector_elements
, 1);
2672 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2673 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2678 assert(type
->is_scalar() || type
->is_vector());
2680 r
->type
= type
->base_type
;
2682 st_src_reg l_src
= st_src_reg(*l
);
2683 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2685 if (native_integers
) {
2686 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2687 cond_swap
? l_src
: *r
,
2688 cond_swap
? *r
: l_src
);
2690 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2691 cond_swap
? l_src
: *r
,
2692 cond_swap
? *r
: l_src
);
2695 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2702 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2707 ir
->rhs
->accept(this);
2710 l
= get_assignment_lhs(ir
->lhs
, this);
2712 /* FINISHME: This should really set to the correct maximal writemask for each
2713 * FINISHME: component written (in the loops below). This case can only
2714 * FINISHME: occur for matrices, arrays, and structures.
2716 if (ir
->write_mask
== 0) {
2717 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2718 l
.writemask
= WRITEMASK_XYZW
;
2719 } else if (ir
->lhs
->type
->is_scalar() &&
2720 !ir
->lhs
->type
->is_double() &&
2721 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2722 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2723 * FINISHME: W component of fragment shader output zero, work correctly.
2725 l
.writemask
= WRITEMASK_XYZW
;
2728 int first_enabled_chan
= 0;
2731 l
.writemask
= ir
->write_mask
;
2733 for (int i
= 0; i
< 4; i
++) {
2734 if (l
.writemask
& (1 << i
)) {
2735 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2740 /* Swizzle a small RHS vector into the channels being written.
2742 * glsl ir treats write_mask as dictating how many channels are
2743 * present on the RHS while TGSI treats write_mask as just
2744 * showing which channels of the vec4 RHS get written.
2746 for (int i
= 0; i
< 4; i
++) {
2747 if (l
.writemask
& (1 << i
))
2748 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2750 swizzles
[i
] = first_enabled_chan
;
2752 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2753 swizzles
[2], swizzles
[3]);
2756 assert(l
.file
!= PROGRAM_UNDEFINED
);
2757 assert(r
.file
!= PROGRAM_UNDEFINED
);
2759 if (ir
->condition
) {
2760 const bool switch_order
= this->process_move_condition(ir
->condition
);
2761 st_src_reg condition
= this->result
;
2763 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2764 } else if (ir
->rhs
->as_expression() &&
2765 this->instructions
.get_tail() &&
2766 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2767 type_size(ir
->lhs
->type
) == 1 &&
2768 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2769 /* To avoid emitting an extra MOV when assigning an expression to a
2770 * variable, emit the last instruction of the expression again, but
2771 * replace the destination register with the target of the assignment.
2772 * Dead code elimination will remove the original instruction.
2774 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2775 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2776 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2777 new_inst
->saturate
= inst
->saturate
;
2778 inst
->dead_mask
= inst
->dst
[0].writemask
;
2780 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2786 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2789 GLdouble stack_vals
[4] = { 0 };
2790 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2791 GLenum gl_type
= GL_NONE
;
2793 static int in_array
= 0;
2794 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2796 /* Unfortunately, 4 floats is all we can get into
2797 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2798 * aggregate constant and move each constant value into it. If we
2799 * get lucky, copy propagation will eliminate the extra moves.
2801 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2802 st_src_reg temp_base
= get_temp(ir
->type
);
2803 st_dst_reg temp
= st_dst_reg(temp_base
);
2805 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2806 int size
= type_size(field_value
->type
);
2810 field_value
->accept(this);
2813 for (i
= 0; i
< (unsigned int)size
; i
++) {
2814 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2820 this->result
= temp_base
;
2824 if (ir
->type
->is_array()) {
2825 st_src_reg temp_base
= get_temp(ir
->type
);
2826 st_dst_reg temp
= st_dst_reg(temp_base
);
2827 int size
= type_size(ir
->type
->fields
.array
);
2832 for (i
= 0; i
< ir
->type
->length
; i
++) {
2833 ir
->array_elements
[i
]->accept(this);
2835 for (int j
= 0; j
< size
; j
++) {
2836 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2842 this->result
= temp_base
;
2847 if (ir
->type
->is_matrix()) {
2848 st_src_reg mat
= get_temp(ir
->type
);
2849 st_dst_reg mat_column
= st_dst_reg(mat
);
2851 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2852 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
2853 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2855 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2856 src
.index
= add_constant(file
,
2858 ir
->type
->vector_elements
,
2861 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2870 switch (ir
->type
->base_type
) {
2871 case GLSL_TYPE_FLOAT
:
2873 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2874 values
[i
].f
= ir
->value
.f
[i
];
2877 case GLSL_TYPE_DOUBLE
:
2878 gl_type
= GL_DOUBLE
;
2879 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2880 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
2881 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
2884 case GLSL_TYPE_UINT
:
2885 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
2886 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2887 if (native_integers
)
2888 values
[i
].u
= ir
->value
.u
[i
];
2890 values
[i
].f
= ir
->value
.u
[i
];
2894 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
2895 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2896 if (native_integers
)
2897 values
[i
].i
= ir
->value
.i
[i
];
2899 values
[i
].f
= ir
->value
.i
[i
];
2902 case GLSL_TYPE_BOOL
:
2903 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
2904 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2905 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
2909 assert(!"Non-float/uint/int/bool constant");
2912 this->result
= st_src_reg(file
, -1, ir
->type
);
2913 this->result
.index
= add_constant(file
,
2915 ir
->type
->vector_elements
,
2917 &this->result
.swizzle
);
2921 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
2923 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
2924 if (entry
->sig
== sig
)
2928 entry
= ralloc(mem_ctx
, function_entry
);
2930 entry
->sig_id
= this->next_signature_id
++;
2931 entry
->bgn_inst
= NULL
;
2933 /* Allocate storage for all the parameters. */
2934 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
2935 variable_storage
*storage
;
2937 storage
= find_variable_storage(param
);
2940 st_src_reg src
= get_temp(param
->type
);
2942 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
2943 this->variables
.push_tail(storage
);
2946 if (!sig
->return_type
->is_void()) {
2947 entry
->return_reg
= get_temp(sig
->return_type
);
2949 entry
->return_reg
= undef_src
;
2952 this->function_signatures
.push_tail(entry
);
2957 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
2959 glsl_to_tgsi_instruction
*call_inst
;
2960 ir_function_signature
*sig
= ir
->callee
;
2961 function_entry
*entry
= get_function_signature(sig
);
2964 /* Process in parameters. */
2965 foreach_two_lists(formal_node
, &sig
->parameters
,
2966 actual_node
, &ir
->actual_parameters
) {
2967 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
2968 ir_variable
*param
= (ir_variable
*) formal_node
;
2970 if (param
->data
.mode
== ir_var_function_in
||
2971 param
->data
.mode
== ir_var_function_inout
) {
2972 variable_storage
*storage
= find_variable_storage(param
);
2975 param_rval
->accept(this);
2976 st_src_reg r
= this->result
;
2979 l
.file
= storage
->file
;
2980 l
.index
= storage
->index
;
2982 l
.writemask
= WRITEMASK_XYZW
;
2983 l
.cond_mask
= COND_TR
;
2985 for (i
= 0; i
< type_size(param
->type
); i
++) {
2986 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
2993 /* Emit call instruction */
2994 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
2995 call_inst
->function
= entry
;
2997 /* Process out parameters. */
2998 foreach_two_lists(formal_node
, &sig
->parameters
,
2999 actual_node
, &ir
->actual_parameters
) {
3000 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3001 ir_variable
*param
= (ir_variable
*) formal_node
;
3003 if (param
->data
.mode
== ir_var_function_out
||
3004 param
->data
.mode
== ir_var_function_inout
) {
3005 variable_storage
*storage
= find_variable_storage(param
);
3009 r
.file
= storage
->file
;
3010 r
.index
= storage
->index
;
3012 r
.swizzle
= SWIZZLE_NOOP
;
3015 param_rval
->accept(this);
3016 st_dst_reg l
= st_dst_reg(this->result
);
3018 for (i
= 0; i
< type_size(param
->type
); i
++) {
3019 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3026 /* Process return value. */
3027 this->result
= entry
->return_reg
;
3031 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3033 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3034 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3035 st_src_reg levels_src
;
3036 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3037 glsl_to_tgsi_instruction
*inst
= NULL
;
3038 unsigned opcode
= TGSI_OPCODE_NOP
;
3039 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3040 ir_rvalue
*sampler_index
=
3041 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
3042 bool is_cube_array
= false;
3045 /* if we are a cube array sampler */
3046 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3047 sampler_type
->sampler_array
)) {
3048 is_cube_array
= true;
3051 if (ir
->coordinate
) {
3052 ir
->coordinate
->accept(this);
3054 /* Put our coords in a temp. We'll need to modify them for shadow,
3055 * projection, or LOD, so the only case we'd use it as is is if
3056 * we're doing plain old texturing. The optimization passes on
3057 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3059 coord
= get_temp(glsl_type::vec4_type
);
3060 coord_dst
= st_dst_reg(coord
);
3061 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3062 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3065 if (ir
->projector
) {
3066 ir
->projector
->accept(this);
3067 projector
= this->result
;
3070 /* Storage for our result. Ideally for an assignment we'd be using
3071 * the actual storage for the result here, instead.
3073 result_src
= get_temp(ir
->type
);
3074 result_dst
= st_dst_reg(result_src
);
3078 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3080 ir
->offset
->accept(this);
3081 offset
[0] = this->result
;
3085 if (is_cube_array
||
3086 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3087 opcode
= TGSI_OPCODE_TXB2
;
3090 opcode
= TGSI_OPCODE_TXB
;
3092 ir
->lod_info
.bias
->accept(this);
3093 lod_info
= this->result
;
3095 ir
->offset
->accept(this);
3096 offset
[0] = this->result
;
3100 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3101 ir
->lod_info
.lod
->accept(this);
3102 lod_info
= this->result
;
3104 ir
->offset
->accept(this);
3105 offset
[0] = this->result
;
3109 opcode
= TGSI_OPCODE_TXD
;
3110 ir
->lod_info
.grad
.dPdx
->accept(this);
3112 ir
->lod_info
.grad
.dPdy
->accept(this);
3115 ir
->offset
->accept(this);
3116 offset
[0] = this->result
;
3120 opcode
= TGSI_OPCODE_TXQ
;
3121 ir
->lod_info
.lod
->accept(this);
3122 lod_info
= this->result
;
3124 case ir_query_levels
:
3125 opcode
= TGSI_OPCODE_TXQ
;
3126 lod_info
= undef_src
;
3127 levels_src
= get_temp(ir
->type
);
3130 opcode
= TGSI_OPCODE_TXF
;
3131 ir
->lod_info
.lod
->accept(this);
3132 lod_info
= this->result
;
3134 ir
->offset
->accept(this);
3135 offset
[0] = this->result
;
3139 opcode
= TGSI_OPCODE_TXF
;
3140 ir
->lod_info
.sample_index
->accept(this);
3141 sample_index
= this->result
;
3144 opcode
= TGSI_OPCODE_TG4
;
3145 ir
->lod_info
.component
->accept(this);
3146 component
= this->result
;
3148 ir
->offset
->accept(this);
3149 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3150 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3151 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3152 offset
[i
] = this->result
;
3153 offset
[i
].index
+= i
* type_size(elt_type
);
3154 offset
[i
].type
= elt_type
->base_type
;
3155 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3158 offset
[0] = this->result
;
3163 opcode
= TGSI_OPCODE_LODQ
;
3165 case ir_texture_samples
:
3166 opcode
= TGSI_OPCODE_TXQS
;
3168 case ir_samples_identical
:
3169 unreachable("Unexpected ir_samples_identical opcode");
3172 if (ir
->projector
) {
3173 if (opcode
== TGSI_OPCODE_TEX
) {
3174 /* Slot the projector in as the last component of the coord. */
3175 coord_dst
.writemask
= WRITEMASK_W
;
3176 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3177 coord_dst
.writemask
= WRITEMASK_XYZW
;
3178 opcode
= TGSI_OPCODE_TXP
;
3180 st_src_reg coord_w
= coord
;
3181 coord_w
.swizzle
= SWIZZLE_WWWW
;
3183 /* For the other TEX opcodes there's no projective version
3184 * since the last slot is taken up by LOD info. Do the
3185 * projective divide now.
3187 coord_dst
.writemask
= WRITEMASK_W
;
3188 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3190 /* In the case where we have to project the coordinates "by hand,"
3191 * the shadow comparator value must also be projected.
3193 st_src_reg tmp_src
= coord
;
3194 if (ir
->shadow_comparitor
) {
3195 /* Slot the shadow value in as the second to last component of the
3198 ir
->shadow_comparitor
->accept(this);
3200 tmp_src
= get_temp(glsl_type::vec4_type
);
3201 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3203 /* Projective division not allowed for array samplers. */
3204 assert(!sampler_type
->sampler_array
);
3206 tmp_dst
.writemask
= WRITEMASK_Z
;
3207 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3209 tmp_dst
.writemask
= WRITEMASK_XY
;
3210 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
3213 coord_dst
.writemask
= WRITEMASK_XYZ
;
3214 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
3216 coord_dst
.writemask
= WRITEMASK_XYZW
;
3217 coord
.swizzle
= SWIZZLE_XYZW
;
3221 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
3222 * comparator was put in the correct place (and projected) by the code,
3223 * above, that handles by-hand projection.
3225 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
3226 /* Slot the shadow value in as the second to last component of the
3229 ir
->shadow_comparitor
->accept(this);
3231 if (is_cube_array
) {
3232 cube_sc
= get_temp(glsl_type::float_type
);
3233 cube_sc_dst
= st_dst_reg(cube_sc
);
3234 cube_sc_dst
.writemask
= WRITEMASK_X
;
3235 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
3236 cube_sc_dst
.writemask
= WRITEMASK_X
;
3239 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
3240 sampler_type
->sampler_array
) ||
3241 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3242 coord_dst
.writemask
= WRITEMASK_W
;
3244 coord_dst
.writemask
= WRITEMASK_Z
;
3246 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3247 coord_dst
.writemask
= WRITEMASK_XYZW
;
3251 if (ir
->op
== ir_txf_ms
) {
3252 coord_dst
.writemask
= WRITEMASK_W
;
3253 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
3254 coord_dst
.writemask
= WRITEMASK_XYZW
;
3255 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
3256 opcode
== TGSI_OPCODE_TXF
) {
3257 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
3258 coord_dst
.writemask
= WRITEMASK_W
;
3259 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
3260 coord_dst
.writemask
= WRITEMASK_XYZW
;
3263 if (sampler_index
) {
3264 sampler_index
->accept(this);
3265 emit_arl(ir
, sampler_reladdr
, this->result
);
3268 if (opcode
== TGSI_OPCODE_TXD
)
3269 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
3270 else if (opcode
== TGSI_OPCODE_TXQ
) {
3271 if (ir
->op
== ir_query_levels
) {
3272 /* the level is stored in W */
3273 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
3274 result_dst
.writemask
= WRITEMASK_X
;
3275 levels_src
.swizzle
= SWIZZLE_WWWW
;
3276 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
3278 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
3279 } else if (opcode
== TGSI_OPCODE_TXQS
) {
3280 inst
= emit_asm(ir
, opcode
, result_dst
);
3281 } else if (opcode
== TGSI_OPCODE_TXF
) {
3282 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3283 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
3284 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
3285 } else if (opcode
== TGSI_OPCODE_TEX2
) {
3286 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3287 } else if (opcode
== TGSI_OPCODE_TG4
) {
3288 if (is_cube_array
&& ir
->shadow_comparitor
) {
3289 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3291 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
3294 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3296 if (ir
->shadow_comparitor
)
3297 inst
->tex_shadow
= GL_TRUE
;
3299 inst
->sampler
.index
= _mesa_get_sampler_uniform_value(ir
->sampler
,
3300 this->shader_program
,
3302 if (sampler_index
) {
3303 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3304 memcpy(inst
->sampler
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3305 inst
->sampler_array_size
=
3306 ir
->sampler
->as_dereference_array()->array
->type
->array_size();
3308 inst
->sampler_array_size
= 1;
3312 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
3313 inst
->tex_offsets
[i
] = offset
[i
];
3314 inst
->tex_offset_num_offset
= i
;
3317 switch (sampler_type
->sampler_dimensionality
) {
3318 case GLSL_SAMPLER_DIM_1D
:
3319 inst
->tex_target
= (sampler_type
->sampler_array
)
3320 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3322 case GLSL_SAMPLER_DIM_2D
:
3323 inst
->tex_target
= (sampler_type
->sampler_array
)
3324 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3326 case GLSL_SAMPLER_DIM_3D
:
3327 inst
->tex_target
= TEXTURE_3D_INDEX
;
3329 case GLSL_SAMPLER_DIM_CUBE
:
3330 inst
->tex_target
= (sampler_type
->sampler_array
)
3331 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3333 case GLSL_SAMPLER_DIM_RECT
:
3334 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3336 case GLSL_SAMPLER_DIM_BUF
:
3337 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3339 case GLSL_SAMPLER_DIM_EXTERNAL
:
3340 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3342 case GLSL_SAMPLER_DIM_MS
:
3343 inst
->tex_target
= (sampler_type
->sampler_array
)
3344 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3347 assert(!"Should not get here.");
3350 inst
->tex_type
= ir
->type
->base_type
;
3352 this->result
= result_src
;
3356 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
3358 if (ir
->get_value()) {
3362 assert(current_function
);
3364 ir
->get_value()->accept(this);
3365 st_src_reg r
= this->result
;
3367 l
= st_dst_reg(current_function
->return_reg
);
3369 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
3370 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3376 emit_asm(ir
, TGSI_OPCODE_RET
);
3380 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
3382 if (ir
->condition
) {
3383 ir
->condition
->accept(this);
3384 st_src_reg condition
= this->result
;
3386 /* Convert the bool condition to a float so we can negate. */
3387 if (native_integers
) {
3388 st_src_reg temp
= get_temp(ir
->condition
->type
);
3389 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
3390 condition
, st_src_reg_for_float(1.0));
3394 condition
.negate
= ~condition
.negate
;
3395 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
3397 /* unconditional kil */
3398 emit_asm(ir
, TGSI_OPCODE_KILL
);
3403 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
3406 glsl_to_tgsi_instruction
*if_inst
;
3408 ir
->condition
->accept(this);
3409 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3411 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
3413 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
3415 this->instructions
.push_tail(if_inst
);
3417 visit_exec_list(&ir
->then_instructions
, this);
3419 if (!ir
->else_instructions
.is_empty()) {
3420 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
3421 visit_exec_list(&ir
->else_instructions
, this);
3424 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
3429 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
3431 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3433 ir
->stream
->accept(this);
3434 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
3438 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
3440 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3442 ir
->stream
->accept(this);
3443 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
3447 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
3449 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
3450 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
3452 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
3455 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
3457 result
.file
= PROGRAM_UNDEFINED
;
3462 num_input_arrays
= 0;
3463 num_output_arrays
= 0;
3464 next_signature_id
= 1;
3466 current_function
= NULL
;
3467 num_address_regs
= 0;
3469 indirect_addr_consts
= false;
3470 wpos_transform_const
= -1;
3472 native_integers
= false;
3473 mem_ctx
= ralloc_context(NULL
);
3476 shader_program
= NULL
;
3483 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
3486 ralloc_free(mem_ctx
);
3489 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
3496 * Count resources used by the given gpu program (number of texture
3500 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
3502 v
->samplers_used
= 0;
3504 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
3505 if (inst
->info
->is_tex
) {
3506 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
3507 unsigned idx
= inst
->sampler
.index
+ i
;
3508 v
->samplers_used
|= 1 << idx
;
3510 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
3511 v
->sampler_types
[idx
] = inst
->tex_type
;
3512 v
->sampler_targets
[idx
] =
3513 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
3515 if (inst
->tex_shadow
) {
3516 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
3521 prog
->SamplersUsed
= v
->samplers_used
;
3523 if (v
->shader_program
!= NULL
)
3524 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
3528 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
3529 * are read from the given src in this instruction
3532 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
3534 int read_mask
= 0, comp
;
3536 /* Now, given the src swizzle and the written channels, find which
3537 * components are actually read
3539 for (comp
= 0; comp
< 4; ++comp
) {
3540 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
3542 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
3543 read_mask
|= 1 << coord
;
3550 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
3551 * instruction is the first instruction to write to register T0. There are
3552 * several lowering passes done in GLSL IR (e.g. branches and
3553 * relative addressing) that create a large number of conditional assignments
3554 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
3556 * Here is why this conversion is safe:
3557 * CMP T0, T1 T2 T0 can be expanded to:
3563 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
3564 * as the original program. If (T1 < 0.0) evaluates to false, executing
3565 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
3566 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
3567 * because any instruction that was going to read from T0 after this was going
3568 * to read a garbage value anyway.
3571 glsl_to_tgsi_visitor::simplify_cmp(void)
3573 int tempWritesSize
= 0;
3574 unsigned *tempWrites
= NULL
;
3575 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
3577 memset(outputWrites
, 0, sizeof(outputWrites
));
3579 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3580 unsigned prevWriteMask
= 0;
3582 /* Give up if we encounter relative addressing or flow control. */
3583 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
3584 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
3585 tgsi_get_opcode_info(inst
->op
)->is_branch
||
3586 inst
->op
== TGSI_OPCODE_BGNSUB
||
3587 inst
->op
== TGSI_OPCODE_CONT
||
3588 inst
->op
== TGSI_OPCODE_END
||
3589 inst
->op
== TGSI_OPCODE_ENDSUB
||
3590 inst
->op
== TGSI_OPCODE_RET
) {
3594 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
3595 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
3596 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
3597 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3598 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
3599 if (inst
->dst
[0].index
>= tempWritesSize
) {
3600 const int inc
= 4096;
3602 tempWrites
= (unsigned*)
3604 (tempWritesSize
+ inc
) * sizeof(unsigned));
3608 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
3609 tempWritesSize
+= inc
;
3612 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
3613 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3617 /* For a CMP to be considered a conditional write, the destination
3618 * register and source register two must be the same. */
3619 if (inst
->op
== TGSI_OPCODE_CMP
3620 && !(inst
->dst
[0].writemask
& prevWriteMask
)
3621 && inst
->src
[2].file
== inst
->dst
[0].file
3622 && inst
->src
[2].index
== inst
->dst
[0].index
3623 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
3625 inst
->op
= TGSI_OPCODE_MOV
;
3626 inst
->src
[0] = inst
->src
[1];
3633 /* Replaces all references to a temporary register index with another index. */
3635 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
3637 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3640 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3641 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3642 for (k
= 0; k
< num_renames
; k
++)
3643 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
3644 inst
->src
[j
].index
= renames
[k
].new_reg
;
3647 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3648 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3649 for (k
= 0; k
< num_renames
; k
++)
3650 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
3651 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
3654 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3655 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3656 for (k
= 0; k
< num_renames
; k
++)
3657 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
3658 inst
->dst
[j
].index
= renames
[k
].new_reg
;
3664 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
3666 int depth
= 0; /* loop depth */
3667 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3670 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3671 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3672 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
3673 if (first_reads
[inst
->src
[j
].index
] == -1)
3674 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3677 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3678 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
3679 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
3680 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3683 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3686 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3696 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
3698 int depth
= 0; /* loop depth */
3699 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3702 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3703 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
3704 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
3705 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
3707 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3708 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3709 if (first_writes
[inst
->dst
[j
].index
] == -1)
3710 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
3712 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3713 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
3714 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
3716 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3719 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3722 for (k
= 0; k
< this->next_temp
; k
++) {
3723 if (last_reads
[k
] == -2) {
3735 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
3737 int depth
= 0; /* loop depth */
3741 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3742 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
3743 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
3744 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
3747 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3749 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3751 for (k
= 0; k
< this->next_temp
; k
++) {
3752 if (last_writes
[k
] == -2) {
3763 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
3764 * channels for copy propagation and updates following instructions to
3765 * use the original versions.
3767 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3768 * will occur. As an example, a TXP production before this pass:
3770 * 0: MOV TEMP[1], INPUT[4].xyyy;
3771 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3772 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
3776 * 0: MOV TEMP[1], INPUT[4].xyyy;
3777 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3778 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3780 * which allows for dead code elimination on TEMP[1]'s writes.
3783 glsl_to_tgsi_visitor::copy_propagate(void)
3785 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
3786 glsl_to_tgsi_instruction
*,
3787 this->next_temp
* 4);
3788 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3791 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3792 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3793 || inst
->dst
[0].index
< this->next_temp
);
3795 /* First, do any copy propagation possible into the src regs. */
3796 for (int r
= 0; r
< 3; r
++) {
3797 glsl_to_tgsi_instruction
*first
= NULL
;
3799 int acp_base
= inst
->src
[r
].index
* 4;
3801 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
3802 inst
->src
[r
].reladdr
||
3803 inst
->src
[r
].reladdr2
)
3806 /* See if we can find entries in the ACP consisting of MOVs
3807 * from the same src register for all the swizzled channels
3808 * of this src register reference.
3810 for (int i
= 0; i
< 4; i
++) {
3811 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3812 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
3819 assert(acp_level
[acp_base
+ src_chan
] <= level
);
3824 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
3825 first
->src
[0].index
!= copy_chan
->src
[0].index
||
3826 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
3827 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
3835 /* We've now validated that we can copy-propagate to
3836 * replace this src register reference. Do it.
3838 inst
->src
[r
].file
= first
->src
[0].file
;
3839 inst
->src
[r
].index
= first
->src
[0].index
;
3840 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
3841 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
3842 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
3843 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
3846 for (int i
= 0; i
< 4; i
++) {
3847 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3848 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
3849 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
3851 inst
->src
[r
].swizzle
= swizzle
;
3856 case TGSI_OPCODE_BGNLOOP
:
3857 case TGSI_OPCODE_ENDLOOP
:
3858 /* End of a basic block, clear the ACP entirely. */
3859 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3862 case TGSI_OPCODE_IF
:
3863 case TGSI_OPCODE_UIF
:
3867 case TGSI_OPCODE_ENDIF
:
3868 case TGSI_OPCODE_ELSE
:
3869 /* Clear all channels written inside the block from the ACP, but
3870 * leaving those that were not touched.
3872 for (int r
= 0; r
< this->next_temp
; r
++) {
3873 for (int c
= 0; c
< 4; c
++) {
3874 if (!acp
[4 * r
+ c
])
3877 if (acp_level
[4 * r
+ c
] >= level
)
3878 acp
[4 * r
+ c
] = NULL
;
3881 if (inst
->op
== TGSI_OPCODE_ENDIF
)
3886 /* Continuing the block, clear any written channels from
3889 for (int d
= 0; d
< 2; d
++) {
3890 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
3891 /* Any temporary might be written, so no copy propagation
3892 * across this instruction.
3894 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3895 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
3896 inst
->dst
[d
].reladdr
) {
3897 /* Any output might be written, so no copy propagation
3898 * from outputs across this instruction.
3900 for (int r
= 0; r
< this->next_temp
; r
++) {
3901 for (int c
= 0; c
< 4; c
++) {
3902 if (!acp
[4 * r
+ c
])
3905 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
3906 acp
[4 * r
+ c
] = NULL
;
3909 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
3910 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
3911 /* Clear where it's used as dst. */
3912 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
3913 for (int c
= 0; c
< 4; c
++) {
3914 if (inst
->dst
[d
].writemask
& (1 << c
))
3915 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
3919 /* Clear where it's used as src. */
3920 for (int r
= 0; r
< this->next_temp
; r
++) {
3921 for (int c
= 0; c
< 4; c
++) {
3922 if (!acp
[4 * r
+ c
])
3925 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
3927 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
3928 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
3929 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
3930 acp
[4 * r
+ c
] = NULL
;
3939 /* If this is a copy, add it to the ACP. */
3940 if (inst
->op
== TGSI_OPCODE_MOV
&&
3941 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
3942 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
3943 inst
->dst
[0].index
== inst
->src
[0].index
) &&
3944 !inst
->dst
[0].reladdr
&&
3945 !inst
->dst
[0].reladdr2
&&
3947 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
3948 !inst
->src
[0].reladdr
&&
3949 !inst
->src
[0].reladdr2
&&
3950 !inst
->src
[0].negate
) {
3951 for (int i
= 0; i
< 4; i
++) {
3952 if (inst
->dst
[0].writemask
& (1 << i
)) {
3953 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
3954 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
3960 ralloc_free(acp_level
);
3965 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
3968 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3969 * will occur. As an example, a TXP production after copy propagation but
3972 * 0: MOV TEMP[1], INPUT[4].xyyy;
3973 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3974 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3976 * and after this pass:
3978 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3981 glsl_to_tgsi_visitor::eliminate_dead_code(void)
3983 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
3984 glsl_to_tgsi_instruction
*,
3985 this->next_temp
* 4);
3986 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3990 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3991 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3992 || inst
->dst
[0].index
< this->next_temp
);
3995 case TGSI_OPCODE_BGNLOOP
:
3996 case TGSI_OPCODE_ENDLOOP
:
3997 case TGSI_OPCODE_CONT
:
3998 case TGSI_OPCODE_BRK
:
3999 /* End of a basic block, clear the write array entirely.
4001 * This keeps us from killing dead code when the writes are
4002 * on either side of a loop, even when the register isn't touched
4003 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4004 * dead code of this type, so it shouldn't make a difference as long as
4005 * the dead code elimination pass in the GLSL compiler does its job.
4007 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4010 case TGSI_OPCODE_ENDIF
:
4011 case TGSI_OPCODE_ELSE
:
4012 /* Promote the recorded level of all channels written inside the
4013 * preceding if or else block to the level above the if/else block.
4015 for (int r
= 0; r
< this->next_temp
; r
++) {
4016 for (int c
= 0; c
< 4; c
++) {
4017 if (!writes
[4 * r
+ c
])
4020 if (write_level
[4 * r
+ c
] == level
)
4021 write_level
[4 * r
+ c
] = level
-1;
4024 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4028 case TGSI_OPCODE_IF
:
4029 case TGSI_OPCODE_UIF
:
4031 /* fallthrough to default case to mark the condition as read */
4033 /* Continuing the block, clear any channels from the write array that
4034 * are read by this instruction.
4036 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4037 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4038 /* Any temporary might be read, so no dead code elimination
4039 * across this instruction.
4041 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4042 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4043 /* Clear where it's used as src. */
4044 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4045 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4046 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4047 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4049 for (int c
= 0; c
< 4; c
++) {
4050 if (src_chans
& (1 << c
))
4051 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4055 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4056 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4057 /* Any temporary might be read, so no dead code elimination
4058 * across this instruction.
4060 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4061 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4062 /* Clear where it's used as src. */
4063 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4064 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4065 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4066 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4068 for (int c
= 0; c
< 4; c
++) {
4069 if (src_chans
& (1 << c
))
4070 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4077 /* If this instruction writes to a temporary, add it to the write array.
4078 * If there is already an instruction in the write array for one or more
4079 * of the channels, flag that channel write as dead.
4081 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4082 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4083 !inst
->dst
[i
].reladdr
) {
4084 for (int c
= 0; c
< 4; c
++) {
4085 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4086 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4087 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4090 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4092 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4093 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4100 /* Anything still in the write array at this point is dead code. */
4101 for (int r
= 0; r
< this->next_temp
; r
++) {
4102 for (int c
= 0; c
< 4; c
++) {
4103 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4105 inst
->dead_mask
|= (1 << c
);
4109 /* Now actually remove the instructions that are completely dead and update
4110 * the writemask of other instructions with dead channels.
4112 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4113 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4115 else if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4120 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4121 if (inst
->dead_mask
== WRITEMASK_XY
||
4122 inst
->dead_mask
== WRITEMASK_ZW
)
4123 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4125 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4129 ralloc_free(write_level
);
4130 ralloc_free(writes
);
4135 /* merge DFRACEXP instructions into one. */
4137 glsl_to_tgsi_visitor::merge_two_dsts(void)
4139 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4140 glsl_to_tgsi_instruction
*inst2
;
4142 if (num_inst_dst_regs(inst
) != 2)
4145 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4146 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4149 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4152 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4153 inst
->src
[0].index
== inst2
->src
[0].index
&&
4154 inst
->src
[0].type
== inst2
->src
[0].type
&&
4155 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4157 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4163 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4165 inst
->dst
[0] = inst2
->dst
[0];
4166 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4167 inst
->dst
[1] = inst2
->dst
[1];
4178 /* Merges temporary registers together where possible to reduce the number of
4179 * registers needed to run a program.
4181 * Produces optimal code only after copy propagation and dead code elimination
4184 glsl_to_tgsi_visitor::merge_registers(void)
4186 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4187 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4188 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4190 int num_renames
= 0;
4192 /* Read the indices of the last read and first write to each temp register
4193 * into an array so that we don't have to traverse the instruction list as
4195 for (i
= 0; i
< this->next_temp
; i
++) {
4197 first_writes
[i
] = -1;
4199 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
4201 /* Start looking for registers with non-overlapping usages that can be
4202 * merged together. */
4203 for (i
= 0; i
< this->next_temp
; i
++) {
4204 /* Don't touch unused registers. */
4205 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
4207 for (j
= 0; j
< this->next_temp
; j
++) {
4208 /* Don't touch unused registers. */
4209 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
4211 /* We can merge the two registers if the first write to j is after or
4212 * in the same instruction as the last read from i. Note that the
4213 * register at index i will always be used earlier or at the same time
4214 * as the register at index j. */
4215 if (first_writes
[i
] <= first_writes
[j
] &&
4216 last_reads
[i
] <= first_writes
[j
]) {
4217 renames
[num_renames
].old_reg
= j
;
4218 renames
[num_renames
].new_reg
= i
;
4221 /* Update the first_writes and last_reads arrays with the new
4222 * values for the merged register index, and mark the newly unused
4223 * register index as such. */
4224 last_reads
[i
] = last_reads
[j
];
4225 first_writes
[j
] = -1;
4231 rename_temp_registers(num_renames
, renames
);
4232 ralloc_free(renames
);
4233 ralloc_free(last_reads
);
4234 ralloc_free(first_writes
);
4237 /* Reassign indices to temporary registers by reusing unused indices created
4238 * by optimization passes. */
4240 glsl_to_tgsi_visitor::renumber_registers(void)
4244 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4245 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
4246 int num_renames
= 0;
4247 for (i
= 0; i
< this->next_temp
; i
++) {
4248 first_reads
[i
] = -1;
4250 get_first_temp_read(first_reads
);
4252 for (i
= 0; i
< this->next_temp
; i
++) {
4253 if (first_reads
[i
] < 0) continue;
4254 if (i
!= new_index
) {
4255 renames
[num_renames
].old_reg
= i
;
4256 renames
[num_renames
].new_reg
= new_index
;
4262 rename_temp_registers(num_renames
, renames
);
4263 this->next_temp
= new_index
;
4264 ralloc_free(renames
);
4265 ralloc_free(first_reads
);
4268 /* ------------------------- TGSI conversion stuff -------------------------- */
4270 unsigned branch_target
;
4275 * Intermediate state used during shader translation.
4277 struct st_translate
{
4278 struct ureg_program
*ureg
;
4280 unsigned temps_size
;
4281 struct ureg_dst
*temps
;
4283 struct ureg_dst
*arrays
;
4284 unsigned num_temp_arrays
;
4285 struct ureg_src
*constants
;
4287 struct ureg_src
*immediates
;
4289 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
4290 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
4291 struct ureg_dst address
[3];
4292 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
4293 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
4294 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
4295 unsigned *array_sizes
;
4296 struct array_decl
*input_arrays
;
4297 struct array_decl
*output_arrays
;
4299 const GLuint
*inputMapping
;
4300 const GLuint
*outputMapping
;
4302 /* For every instruction that contains a label (eg CALL), keep
4303 * details so that we can go back afterwards and emit the correct
4304 * tgsi instruction number for each label.
4306 struct label
*labels
;
4307 unsigned labels_size
;
4308 unsigned labels_count
;
4310 /* Keep a record of the tgsi instruction number that each mesa
4311 * instruction starts at, will be used to fix up labels after
4316 unsigned insn_count
;
4318 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
4323 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
4324 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
4327 TGSI_SEMANTIC_VERTEXID
,
4328 TGSI_SEMANTIC_INSTANCEID
,
4329 TGSI_SEMANTIC_VERTEXID_NOBASE
,
4330 TGSI_SEMANTIC_BASEVERTEX
,
4334 TGSI_SEMANTIC_INVOCATIONID
,
4339 TGSI_SEMANTIC_SAMPLEID
,
4340 TGSI_SEMANTIC_SAMPLEPOS
,
4341 TGSI_SEMANTIC_SAMPLEMASK
,
4342 TGSI_SEMANTIC_HELPER_INVOCATION
,
4344 /* Tessellation shaders
4346 TGSI_SEMANTIC_TESSCOORD
,
4347 TGSI_SEMANTIC_VERTICESIN
,
4348 TGSI_SEMANTIC_PRIMID
,
4349 TGSI_SEMANTIC_TESSOUTER
,
4350 TGSI_SEMANTIC_TESSINNER
,
4354 * Make note of a branch to a label in the TGSI code.
4355 * After we've emitted all instructions, we'll go over the list
4356 * of labels built here and patch the TGSI code with the actual
4357 * location of each label.
4359 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
4363 if (t
->labels_count
+ 1 >= t
->labels_size
) {
4364 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
4365 t
->labels
= (struct label
*)realloc(t
->labels
,
4366 t
->labels_size
* sizeof(struct label
));
4367 if (t
->labels
== NULL
) {
4368 static unsigned dummy
;
4374 i
= t
->labels_count
++;
4375 t
->labels
[i
].branch_target
= branch_target
;
4376 return &t
->labels
[i
].token
;
4380 * Called prior to emitting the TGSI code for each instruction.
4381 * Allocate additional space for instructions if needed.
4382 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
4383 * the next TGSI instruction.
4385 static void set_insn_start(struct st_translate
*t
, unsigned start
)
4387 if (t
->insn_count
+ 1 >= t
->insn_size
) {
4388 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
4389 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
4390 if (t
->insn
== NULL
) {
4396 t
->insn
[t
->insn_count
++] = start
;
4400 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
4402 static struct ureg_src
4403 emit_immediate(struct st_translate
*t
,
4404 gl_constant_value values
[4],
4407 struct ureg_program
*ureg
= t
->ureg
;
4412 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
4414 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
4416 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
4417 case GL_UNSIGNED_INT
:
4419 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
4421 assert(!"should not get here - type must be float, int, uint, or bool");
4422 return ureg_src_undef();
4427 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
4429 static struct ureg_dst
4430 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
4436 case PROGRAM_UNDEFINED
:
4437 return ureg_dst_undef();
4439 case PROGRAM_TEMPORARY
:
4440 /* Allocate space for temporaries on demand. */
4441 if (index
>= t
->temps_size
) {
4442 const int inc
= 4096;
4444 t
->temps
= (struct ureg_dst
*)
4446 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
4448 return ureg_dst_undef();
4450 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
4451 t
->temps_size
+= inc
;
4454 if (ureg_dst_is_undef(t
->temps
[index
]))
4455 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
4457 return t
->temps
[index
];
4460 array
= index
>> 16;
4462 assert(array
< t
->num_temp_arrays
);
4464 if (ureg_dst_is_undef(t
->arrays
[array
]))
4465 t
->arrays
[array
] = ureg_DECL_array_temporary(
4466 t
->ureg
, t
->array_sizes
[array
], TRUE
);
4468 return ureg_dst_array_offset(t
->arrays
[array
],
4469 (int)(index
& 0xFFFF) - 0x8000);
4471 case PROGRAM_OUTPUT
:
4473 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
4474 assert(index
< FRAG_RESULT_MAX
);
4475 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
4476 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
4477 assert(index
< VARYING_SLOT_TESS_MAX
);
4479 assert(index
< VARYING_SLOT_MAX
);
4481 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
4482 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4483 return t
->outputs
[t
->outputMapping
[index
]];
4486 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
4487 unsigned mesa_index
= decl
->mesa_index
;
4488 int slot
= t
->outputMapping
[mesa_index
];
4490 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
4491 assert(t
->outputs
[slot
].ArrayID
== array_id
);
4492 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
4495 case PROGRAM_ADDRESS
:
4496 return t
->address
[index
];
4499 assert(!"unknown dst register file");
4500 return ureg_dst_undef();
4505 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
4507 static struct ureg_src
4508 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
4510 int index
= reg
->index
;
4511 int double_reg2
= reg
->double_reg2
? 1 : 0;
4514 case PROGRAM_UNDEFINED
:
4515 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4517 case PROGRAM_TEMPORARY
:
4519 case PROGRAM_OUTPUT
:
4520 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
4522 case PROGRAM_UNIFORM
:
4523 assert(reg
->index
>= 0);
4524 return reg
->index
< t
->num_constants
?
4525 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4526 case PROGRAM_STATE_VAR
:
4527 case PROGRAM_CONSTANT
: /* ie, immediate */
4528 if (reg
->has_index2
)
4529 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
4531 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
4532 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4534 case PROGRAM_IMMEDIATE
:
4535 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
4536 return t
->immediates
[reg
->index
];
4539 /* GLSL inputs are 64-bit containers, so we have to
4540 * map back to the original index and add the offset after
4542 index
-= double_reg2
;
4543 if (!reg
->array_id
) {
4544 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
4545 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4546 return t
->inputs
[t
->inputMapping
[index
]];
4549 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
4550 unsigned mesa_index
= decl
->mesa_index
;
4551 int slot
= t
->inputMapping
[mesa_index
];
4553 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
4554 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
4555 return ureg_src_array_offset(t
->inputs
[slot
], index
- mesa_index
);
4558 case PROGRAM_ADDRESS
:
4559 return ureg_src(t
->address
[reg
->index
]);
4561 case PROGRAM_SYSTEM_VALUE
:
4562 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
4563 return t
->systemValues
[reg
->index
];
4566 assert(!"unknown src register file");
4567 return ureg_src_undef();
4572 * Create a TGSI ureg_dst register from an st_dst_reg.
4574 static struct ureg_dst
4575 translate_dst(struct st_translate
*t
,
4576 const st_dst_reg
*dst_reg
,
4579 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
4582 if (dst
.File
== TGSI_FILE_NULL
)
4585 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
4588 dst
= ureg_saturate(dst
);
4590 if (dst_reg
->reladdr
!= NULL
) {
4591 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
4592 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
4595 if (dst_reg
->has_index2
) {
4596 if (dst_reg
->reladdr2
)
4597 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
4600 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
4607 * Create a TGSI ureg_src register from an st_src_reg.
4609 static struct ureg_src
4610 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
4612 struct ureg_src src
= src_register(t
, src_reg
);
4614 if (src_reg
->has_index2
) {
4615 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
4616 * and UBO constant buffers (buffer, position).
4618 if (src_reg
->reladdr2
)
4619 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
4622 src
= ureg_src_dimension(src
, src_reg
->index2D
);
4625 src
= ureg_swizzle(src
,
4626 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
4627 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
4628 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
4629 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
4631 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
4632 src
= ureg_negate(src
);
4634 if (src_reg
->reladdr
!= NULL
) {
4635 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
4636 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
4642 static struct tgsi_texture_offset
4643 translate_tex_offset(struct st_translate
*t
,
4644 const st_src_reg
*in_offset
, int idx
)
4646 struct tgsi_texture_offset offset
;
4647 struct ureg_src imm_src
;
4648 struct ureg_dst dst
;
4651 switch (in_offset
->file
) {
4652 case PROGRAM_IMMEDIATE
:
4653 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
4654 imm_src
= t
->immediates
[in_offset
->index
];
4656 offset
.File
= imm_src
.File
;
4657 offset
.Index
= imm_src
.Index
;
4658 offset
.SwizzleX
= imm_src
.SwizzleX
;
4659 offset
.SwizzleY
= imm_src
.SwizzleY
;
4660 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
4663 case PROGRAM_TEMPORARY
:
4664 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
4665 offset
.File
= imm_src
.File
;
4666 offset
.Index
= imm_src
.Index
;
4667 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4668 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4669 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4673 array
= in_offset
->index
>> 16;
4676 assert(array
< (int)t
->num_temp_arrays
);
4678 dst
= t
->arrays
[array
];
4679 offset
.File
= dst
.File
;
4680 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
4681 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4682 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4683 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4693 compile_tgsi_instruction(struct st_translate
*t
,
4694 const glsl_to_tgsi_instruction
*inst
)
4696 struct ureg_program
*ureg
= t
->ureg
;
4698 struct ureg_dst dst
[2];
4699 struct ureg_src src
[4];
4700 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
4704 unsigned tex_target
;
4706 num_dst
= num_inst_dst_regs(inst
);
4707 num_src
= num_inst_src_regs(inst
);
4709 for (i
= 0; i
< num_dst
; i
++)
4710 dst
[i
] = translate_dst(t
,
4714 for (i
= 0; i
< num_src
; i
++)
4715 src
[i
] = translate_src(t
, &inst
->src
[i
]);
4718 case TGSI_OPCODE_BGNLOOP
:
4719 case TGSI_OPCODE_CAL
:
4720 case TGSI_OPCODE_ELSE
:
4721 case TGSI_OPCODE_ENDLOOP
:
4722 case TGSI_OPCODE_IF
:
4723 case TGSI_OPCODE_UIF
:
4724 assert(num_dst
== 0);
4725 ureg_label_insn(ureg
,
4729 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
4732 case TGSI_OPCODE_TEX
:
4733 case TGSI_OPCODE_TXB
:
4734 case TGSI_OPCODE_TXD
:
4735 case TGSI_OPCODE_TXL
:
4736 case TGSI_OPCODE_TXP
:
4737 case TGSI_OPCODE_TXQ
:
4738 case TGSI_OPCODE_TXQS
:
4739 case TGSI_OPCODE_TXF
:
4740 case TGSI_OPCODE_TEX2
:
4741 case TGSI_OPCODE_TXB2
:
4742 case TGSI_OPCODE_TXL2
:
4743 case TGSI_OPCODE_TG4
:
4744 case TGSI_OPCODE_LODQ
:
4745 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
4746 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
4747 if (inst
->sampler
.reladdr
)
4749 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
4751 for (i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4752 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
4754 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4760 texoffsets
, inst
->tex_offset_num_offset
,
4764 case TGSI_OPCODE_SCS
:
4765 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
4766 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
4779 * Emit the TGSI instructions for inverting and adjusting WPOS.
4780 * This code is unavoidable because it also depends on whether
4781 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
4784 emit_wpos_adjustment( struct st_translate
*t
,
4785 int wpos_transform_const
,
4787 GLfloat adjX
, GLfloat adjY
[2])
4789 struct ureg_program
*ureg
= t
->ureg
;
4791 assert(wpos_transform_const
>= 0);
4793 /* Fragment program uses fragment position input.
4794 * Need to replace instances of INPUT[WPOS] with temp T
4795 * where T = INPUT[WPOS] is inverted by Y.
4797 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
4798 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
4799 struct ureg_src wpos_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
4801 /* First, apply the coordinate shift: */
4802 if (adjX
|| adjY
[0] || adjY
[1]) {
4803 if (adjY
[0] != adjY
[1]) {
4804 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
4805 * depending on whether inversion is actually going to be applied
4806 * or not, which is determined by testing against the inversion
4807 * state variable used below, which will be either +1 or -1.
4809 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
4811 ureg_CMP(ureg
, adj_temp
,
4812 ureg_scalar(wpostrans
, invert
? 2 : 0),
4813 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
4814 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
4815 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
4817 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
4818 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
4820 wpos_input
= ureg_src(wpos_temp
);
4822 /* MOV wpos_temp, input[wpos]
4824 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
4827 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
4828 * inversion/identity, or the other way around if we're drawing to an FBO.
4831 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
4834 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4836 ureg_scalar(wpostrans
, 0),
4837 ureg_scalar(wpostrans
, 1));
4839 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
4842 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4844 ureg_scalar(wpostrans
, 2),
4845 ureg_scalar(wpostrans
, 3));
4848 /* Use wpos_temp as position input from here on:
4850 t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]] = ureg_src(wpos_temp
);
4855 * Emit fragment position/ooordinate code.
4858 emit_wpos(struct st_context
*st
,
4859 struct st_translate
*t
,
4860 const struct gl_program
*program
,
4861 struct ureg_program
*ureg
,
4862 int wpos_transform_const
)
4864 const struct gl_fragment_program
*fp
=
4865 (const struct gl_fragment_program
*) program
;
4866 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
4867 GLfloat adjX
= 0.0f
;
4868 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
4869 boolean invert
= FALSE
;
4871 /* Query the pixel center conventions supported by the pipe driver and set
4872 * adjX, adjY to help out if it cannot handle the requested one internally.
4874 * The bias of the y-coordinate depends on whether y-inversion takes place
4875 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
4876 * drawing to an FBO (causes additional inversion), and whether the the pipe
4877 * driver origin and the requested origin differ (the latter condition is
4878 * stored in the 'invert' variable).
4880 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
4882 * center shift only:
4887 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
4888 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
4889 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
4890 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
4892 * inversion and center shift:
4893 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
4894 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
4895 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
4896 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
4898 if (fp
->OriginUpperLeft
) {
4899 /* Fragment shader wants origin in upper-left */
4900 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
4901 /* the driver supports upper-left origin */
4903 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
4904 /* the driver supports lower-left origin, need to invert Y */
4905 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
4906 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
4913 /* Fragment shader wants origin in lower-left */
4914 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
4915 /* the driver supports lower-left origin */
4916 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
4917 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
4918 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
4919 /* the driver supports upper-left origin, need to invert Y */
4925 if (fp
->PixelCenterInteger
) {
4926 /* Fragment shader wants pixel center integer */
4927 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
4928 /* the driver supports pixel center integer */
4930 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
4931 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
4933 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
4934 /* the driver supports pixel center half integer, need to bias X,Y */
4943 /* Fragment shader wants pixel center half integer */
4944 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
4945 /* the driver supports pixel center half integer */
4947 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
4948 /* the driver supports pixel center integer, need to bias X,Y */
4949 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
4950 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
4951 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
4957 /* we invert after adjustment so that we avoid the MOV to temporary,
4958 * and reuse the adjustment ADD instead */
4959 emit_wpos_adjustment(t
, wpos_transform_const
, invert
, adjX
, adjY
);
4963 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
4964 * TGSI uses +1 for front, -1 for back.
4965 * This function converts the TGSI value to the GL value. Simply clamping/
4966 * saturating the value to [0,1] does the job.
4969 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
4971 struct ureg_program
*ureg
= t
->ureg
;
4972 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
4973 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
4975 if (ctx
->Const
.NativeIntegers
) {
4976 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
4979 /* MOV_SAT face_temp, input[face] */
4980 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
4983 /* Use face_temp as face input from here on: */
4984 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
4988 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
4989 unsigned *array_id
, unsigned *array_size
)
4993 for (i
= 0; i
< count
; i
++) {
4994 struct array_decl
*decl
= &arrays
[i
];
4996 if (attr
== decl
->mesa_index
) {
4997 *array_id
= decl
->array_id
;
4998 *array_size
= decl
->array_size
;
4999 assert(*array_size
);
5007 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5008 * \param program the program to translate
5009 * \param numInputs number of input registers used
5010 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5012 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5013 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5015 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5016 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5017 * \param numOutputs number of output registers used
5018 * \param outputMapping maps Mesa fragment program outputs to TGSI
5020 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5021 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5024 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5026 extern "C" enum pipe_error
5027 st_translate_program(
5028 struct gl_context
*ctx
,
5030 struct ureg_program
*ureg
,
5031 glsl_to_tgsi_visitor
*program
,
5032 const struct gl_program
*proginfo
,
5034 const GLuint inputMapping
[],
5035 const GLuint inputSlotToAttr
[],
5036 const ubyte inputSemanticName
[],
5037 const ubyte inputSemanticIndex
[],
5038 const GLuint interpMode
[],
5039 const GLuint interpLocation
[],
5041 const GLuint outputMapping
[],
5042 const GLuint outputSlotToAttr
[],
5043 const ubyte outputSemanticName
[],
5044 const ubyte outputSemanticIndex
[])
5046 struct st_translate
*t
;
5048 enum pipe_error ret
= PIPE_OK
;
5050 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5051 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5053 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5054 TGSI_SEMANTIC_FACE
);
5055 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5056 TGSI_SEMANTIC_VERTEXID
);
5057 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5058 TGSI_SEMANTIC_INSTANCEID
);
5059 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5060 TGSI_SEMANTIC_SAMPLEID
);
5061 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5062 TGSI_SEMANTIC_SAMPLEPOS
);
5063 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5064 TGSI_SEMANTIC_SAMPLEMASK
);
5065 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5066 TGSI_SEMANTIC_INVOCATIONID
);
5067 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5068 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5069 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5070 TGSI_SEMANTIC_BASEVERTEX
);
5071 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5072 TGSI_SEMANTIC_TESSCOORD
);
5073 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_HELPER_INVOCATION
] ==
5074 TGSI_SEMANTIC_HELPER_INVOCATION
);
5076 t
= CALLOC_STRUCT(st_translate
);
5078 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5082 t
->procType
= procType
;
5083 t
->inputMapping
= inputMapping
;
5084 t
->outputMapping
= outputMapping
;
5086 t
->num_temp_arrays
= program
->next_array
;
5087 if (t
->num_temp_arrays
)
5088 t
->arrays
= (struct ureg_dst
*)
5089 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5092 * Declare input attributes.
5095 case TGSI_PROCESSOR_FRAGMENT
:
5096 for (i
= 0; i
< numInputs
; i
++) {
5097 unsigned array_id
= 0;
5098 unsigned array_size
;
5100 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5101 program
->num_input_arrays
, &array_id
, &array_size
)) {
5102 /* We've found an array. Declare it so. */
5103 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5104 inputSemanticName
[i
], inputSemanticIndex
[i
],
5105 interpMode
[i
], 0, interpLocation
[i
],
5106 array_id
, array_size
);
5107 i
+= array_size
- 1;
5110 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5111 inputSemanticName
[i
], inputSemanticIndex
[i
],
5112 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
5116 case TGSI_PROCESSOR_GEOMETRY
:
5117 case TGSI_PROCESSOR_TESS_EVAL
:
5118 case TGSI_PROCESSOR_TESS_CTRL
:
5119 for (i
= 0; i
< numInputs
; i
++) {
5120 unsigned array_id
= 0;
5121 unsigned array_size
;
5123 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5124 program
->num_input_arrays
, &array_id
, &array_size
)) {
5125 /* We've found an array. Declare it so. */
5126 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5127 inputSemanticIndex
[i
],
5128 array_id
, array_size
);
5129 i
+= array_size
- 1;
5132 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5133 inputSemanticIndex
[i
], 0, 1);
5137 case TGSI_PROCESSOR_VERTEX
:
5138 for (i
= 0; i
< numInputs
; i
++) {
5139 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
5147 * Declare output attributes.
5150 case TGSI_PROCESSOR_FRAGMENT
:
5152 case TGSI_PROCESSOR_GEOMETRY
:
5153 case TGSI_PROCESSOR_TESS_EVAL
:
5154 case TGSI_PROCESSOR_TESS_CTRL
:
5155 case TGSI_PROCESSOR_VERTEX
:
5156 for (i
= 0; i
< numOutputs
; i
++) {
5157 unsigned array_id
= 0;
5158 unsigned array_size
;
5160 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
5161 program
->num_output_arrays
, &array_id
, &array_size
)) {
5162 /* We've found an array. Declare it so. */
5163 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
5164 outputSemanticName
[i
],
5165 outputSemanticIndex
[i
],
5166 array_id
, array_size
);
5167 i
+= array_size
- 1;
5170 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5171 outputSemanticName
[i
],
5172 outputSemanticIndex
[i
]);
5180 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
5181 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
5182 /* Must do this after setting up t->inputs. */
5183 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
5184 program
->wpos_transform_const
);
5187 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
5188 emit_face_var(ctx
, t
);
5190 for (i
= 0; i
< numOutputs
; i
++) {
5191 switch (outputSemanticName
[i
]) {
5192 case TGSI_SEMANTIC_POSITION
:
5193 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5194 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
5195 outputSemanticIndex
[i
]);
5196 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
5198 case TGSI_SEMANTIC_STENCIL
:
5199 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5200 TGSI_SEMANTIC_STENCIL
, /* Stencil */
5201 outputSemanticIndex
[i
]);
5202 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
5204 case TGSI_SEMANTIC_COLOR
:
5205 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5206 TGSI_SEMANTIC_COLOR
,
5207 outputSemanticIndex
[i
]);
5209 case TGSI_SEMANTIC_SAMPLEMASK
:
5210 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5211 TGSI_SEMANTIC_SAMPLEMASK
,
5212 outputSemanticIndex
[i
]);
5213 /* TODO: If we ever support more than 32 samples, this will have
5214 * to become an array.
5216 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5219 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
5220 ret
= PIPE_ERROR_BAD_INPUT
;
5225 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
5226 for (i
= 0; i
< numOutputs
; i
++) {
5227 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
5228 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
5230 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
5231 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
5232 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5237 /* Declare address register.
5239 if (program
->num_address_regs
> 0) {
5240 assert(program
->num_address_regs
<= 3);
5241 for (int i
= 0; i
< program
->num_address_regs
; i
++)
5242 t
->address
[i
] = ureg_DECL_address(ureg
);
5245 /* Declare misc input registers
5248 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
5249 unsigned numSys
= 0;
5250 for (i
= 0; sysInputs
; i
++) {
5251 if (sysInputs
& (1 << i
)) {
5252 unsigned semName
= _mesa_sysval_to_semantic
[i
];
5253 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, numSys
, semName
, 0);
5254 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
5255 semName
== TGSI_SEMANTIC_VERTEXID
) {
5256 /* From Gallium perspective, these system values are always
5257 * integer, and require native integer support. However, if
5258 * native integer is supported on the vertex stage but not the
5259 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
5260 * assumes these system values are floats. To resolve the
5261 * inconsistency, we insert a U2F.
5263 struct st_context
*st
= st_context(ctx
);
5264 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5265 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5266 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
5268 if (!ctx
->Const
.NativeIntegers
) {
5269 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
5270 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
5271 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
5275 sysInputs
&= ~(1 << i
);
5280 t
->array_sizes
= program
->array_sizes
;
5281 t
->input_arrays
= program
->input_arrays
;
5282 t
->output_arrays
= program
->output_arrays
;
5284 /* Emit constants and uniforms. TGSI uses a single index space for these,
5285 * so we put all the translated regs in t->constants.
5287 if (proginfo
->Parameters
) {
5288 t
->constants
= (struct ureg_src
*)
5289 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
5290 if (t
->constants
== NULL
) {
5291 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5294 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
5296 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
5297 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
5298 case PROGRAM_STATE_VAR
:
5299 case PROGRAM_UNIFORM
:
5300 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5303 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
5304 * addressing of the const buffer.
5305 * FIXME: Be smarter and recognize param arrays:
5306 * indirect addressing is only valid within the referenced
5309 case PROGRAM_CONSTANT
:
5310 if (program
->indirect_addr_consts
)
5311 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5313 t
->constants
[i
] = emit_immediate(t
,
5314 proginfo
->Parameters
->ParameterValues
[i
],
5315 proginfo
->Parameters
->Parameters
[i
].DataType
,
5324 if (program
->shader
) {
5325 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
5327 for (i
= 0; i
< num_ubos
; i
++) {
5328 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
5329 unsigned num_const_vecs
= (size
+ 15) / 16;
5330 unsigned first
, last
;
5331 assert(num_const_vecs
> 0);
5333 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
5334 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
5338 /* Emit immediate values.
5340 t
->immediates
= (struct ureg_src
*)
5341 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
5342 if (t
->immediates
== NULL
) {
5343 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5346 t
->num_immediates
= program
->num_immediates
;
5349 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
5350 assert(i
< program
->num_immediates
);
5351 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
5353 assert(i
== program
->num_immediates
);
5355 /* texture samplers */
5356 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
5357 if (program
->samplers_used
& (1 << i
)) {
5360 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
5362 switch (program
->sampler_types
[i
]) {
5364 type
= TGSI_RETURN_TYPE_SINT
;
5366 case GLSL_TYPE_UINT
:
5367 type
= TGSI_RETURN_TYPE_UINT
;
5369 case GLSL_TYPE_FLOAT
:
5370 type
= TGSI_RETURN_TYPE_FLOAT
;
5373 unreachable("not reached");
5376 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
5377 type
, type
, type
, type
);
5381 /* Emit each instruction in turn:
5383 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
5384 set_insn_start(t
, ureg_get_instruction_number(ureg
));
5385 compile_tgsi_instruction(t
, inst
);
5388 /* Fix up all emitted labels:
5390 for (i
= 0; i
< t
->labels_count
; i
++) {
5391 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
5392 t
->insn
[t
->labels
[i
].branch_target
]);
5402 t
->num_constants
= 0;
5403 free(t
->immediates
);
5404 t
->num_immediates
= 0;
5407 debug_printf("%s: translate error flag set\n", __func__
);
5415 /* ----------------------------- End TGSI code ------------------------------ */
5419 * Convert a shader's GLSL IR into a Mesa gl_program, although without
5420 * generating Mesa IR.
5422 static struct gl_program
*
5423 get_mesa_program(struct gl_context
*ctx
,
5424 struct gl_shader_program
*shader_program
,
5425 struct gl_shader
*shader
)
5427 glsl_to_tgsi_visitor
* v
;
5428 struct gl_program
*prog
;
5429 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
5431 struct gl_shader_compiler_options
*options
=
5432 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
5433 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5434 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
5436 validate_ir_tree(shader
->ir
);
5438 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
5441 prog
->Parameters
= _mesa_new_parameter_list();
5442 v
= new glsl_to_tgsi_visitor();
5445 v
->shader_program
= shader_program
;
5447 v
->options
= options
;
5448 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
5449 v
->native_integers
= ctx
->Const
.NativeIntegers
;
5451 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
5452 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
5453 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
5454 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
5456 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
5457 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
5460 /* Remove reads from output registers. */
5461 lower_output_reads(shader
->Stage
, shader
->ir
);
5463 /* Emit intermediate IR for main(). */
5464 visit_exec_list(shader
->ir
, v
);
5466 /* Now emit bodies for any functions that were used. */
5468 progress
= GL_FALSE
;
5470 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
5471 if (!entry
->bgn_inst
) {
5472 v
->current_function
= entry
;
5474 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
5475 entry
->bgn_inst
->function
= entry
;
5477 visit_exec_list(&entry
->sig
->body
, v
);
5479 glsl_to_tgsi_instruction
*last
;
5480 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
5481 if (last
->op
!= TGSI_OPCODE_RET
)
5482 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
5484 glsl_to_tgsi_instruction
*end
;
5485 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
5486 end
->function
= entry
;
5494 /* Print out some information (for debugging purposes) used by the
5495 * optimization passes. */
5498 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5499 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5500 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5501 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
5503 for (i
= 0; i
< v
->next_temp
; i
++) {
5504 first_writes
[i
] = -1;
5505 first_reads
[i
] = -1;
5506 last_writes
[i
] = -1;
5509 v
->get_first_temp_read(first_reads
);
5510 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5511 v
->get_last_temp_write(last_writes
);
5512 for (i
= 0; i
< v
->next_temp
; i
++)
5513 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
5517 ralloc_free(first_writes
);
5518 ralloc_free(first_reads
);
5519 ralloc_free(last_writes
);
5520 ralloc_free(last_reads
);
5524 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
5527 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
5528 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
5529 v
->copy_propagate();
5531 while (v
->eliminate_dead_code());
5533 v
->merge_two_dsts();
5534 v
->merge_registers();
5535 v
->renumber_registers();
5537 /* Write the END instruction. */
5538 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
5540 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
5542 _mesa_log("GLSL IR for linked %s program %d:\n",
5543 _mesa_shader_stage_to_string(shader
->Stage
),
5544 shader_program
->Name
);
5545 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
5549 prog
->Instructions
= NULL
;
5550 prog
->NumInstructions
= 0;
5552 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
5553 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
5554 prog
->InputsRead
, prog
->PatchInputsRead
);
5555 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
5556 prog
->OutputsWritten
, prog
->PatchOutputsWritten
);
5557 count_resources(v
, prog
);
5559 /* This must be done before the uniform storage is associated. */
5560 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
5561 prog
->InputsRead
& VARYING_BIT_POS
){
5562 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
5563 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
5566 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
5567 wposTransformState
);
5570 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
5572 /* This has to be done last. Any operation the can cause
5573 * prog->ParameterValues to get reallocated (e.g., anything that adds a
5574 * program constant) has to happen before creating this linkage.
5576 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
5577 if (!shader_program
->LinkStatus
) {
5578 free_glsl_to_tgsi_visitor(v
);
5582 struct st_vertex_program
*stvp
;
5583 struct st_fragment_program
*stfp
;
5584 struct st_geometry_program
*stgp
;
5585 struct st_tessctrl_program
*sttcp
;
5586 struct st_tesseval_program
*sttep
;
5588 switch (shader
->Type
) {
5589 case GL_VERTEX_SHADER
:
5590 stvp
= (struct st_vertex_program
*)prog
;
5591 stvp
->glsl_to_tgsi
= v
;
5593 case GL_FRAGMENT_SHADER
:
5594 stfp
= (struct st_fragment_program
*)prog
;
5595 stfp
->glsl_to_tgsi
= v
;
5597 case GL_GEOMETRY_SHADER
:
5598 stgp
= (struct st_geometry_program
*)prog
;
5599 stgp
->glsl_to_tgsi
= v
;
5601 case GL_TESS_CONTROL_SHADER
:
5602 sttcp
= (struct st_tessctrl_program
*)prog
;
5603 sttcp
->glsl_to_tgsi
= v
;
5605 case GL_TESS_EVALUATION_SHADER
:
5606 sttep
= (struct st_tesseval_program
*)prog
;
5607 sttep
->glsl_to_tgsi
= v
;
5610 assert(!"should not be reached");
5620 st_dump_program_for_shader_db(struct gl_context
*ctx
,
5621 struct gl_shader_program
*prog
)
5623 /* Dump only successfully compiled and linked shaders to the specified
5624 * file. This is for shader-db.
5626 * These options allow some pre-processing of shaders while dumping,
5627 * because some apps have ill-formed shaders.
5629 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
5630 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
5632 if (dump_filename
&& prog
->Name
!= 0) {
5633 FILE *f
= fopen(dump_filename
, "a");
5636 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
5637 const struct gl_shader
*sh
= prog
->Shaders
[i
];
5639 bool skip_version
= false;
5644 source
= sh
->Source
;
5646 /* This string mustn't be changed. shader-db uses it to find
5647 * where the shader begins.
5649 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
5650 _mesa_shader_stage_to_string(sh
->Stage
),
5653 /* Dump the forced version if set. */
5654 if (ctx
->Const
.ForceGLSLVersion
) {
5655 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
5656 skip_version
= true;
5659 /* Insert directives (optional). */
5660 if (insert_directives
) {
5661 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
5662 fprintf(f
, "#version %i\n", prog
->Version
);
5663 fprintf(f
, "%s\n", insert_directives
);
5664 skip_version
= true;
5667 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
5668 const char *next_line
= strstr(source
, "\n");
5671 source
= next_line
+ 1;
5676 fprintf(f
, "%s", source
);
5686 * Called via ctx->Driver.LinkShader()
5687 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
5688 * with code lowering and other optimizations.
5691 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
5693 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5694 assert(prog
->LinkStatus
);
5696 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5697 if (prog
->_LinkedShaders
[i
] == NULL
)
5701 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
5702 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
5703 const struct gl_shader_compiler_options
*options
=
5704 &ctx
->Const
.ShaderCompilerOptions
[stage
];
5705 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
5706 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
5707 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
5708 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
5709 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
5711 /* If there are forms of indirect addressing that the driver
5712 * cannot handle, perform the lowering pass.
5714 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
5715 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
5716 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
5717 options
->EmitNoIndirectInput
,
5718 options
->EmitNoIndirectOutput
,
5719 options
->EmitNoIndirectTemp
,
5720 options
->EmitNoIndirectUniform
);
5723 if (ctx
->Extensions
.ARB_shading_language_packing
) {
5724 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
5725 LOWER_UNPACK_SNORM_2x16
|
5726 LOWER_PACK_UNORM_2x16
|
5727 LOWER_UNPACK_UNORM_2x16
|
5728 LOWER_PACK_SNORM_4x8
|
5729 LOWER_UNPACK_SNORM_4x8
|
5730 LOWER_UNPACK_UNORM_4x8
|
5731 LOWER_PACK_UNORM_4x8
|
5732 LOWER_PACK_HALF_2x16
|
5733 LOWER_UNPACK_HALF_2x16
;
5735 if (ctx
->Extensions
.ARB_gpu_shader5
)
5736 lower_inst
|= LOWER_PACK_USE_BFI
|
5739 lower_packing_builtins(ir
, lower_inst
);
5742 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
5743 lower_offset_arrays(ir
);
5744 do_mat_op_to_vec(ir
);
5745 lower_instructions(ir
,
5751 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
5754 (have_dround
? 0 : DOPS_TO_DFRAC
) |
5755 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
5756 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
5757 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
5759 do_vec_index_to_cond_assign(ir
);
5760 lower_vector_insert(ir
, true);
5761 lower_quadop_vector(ir
, false);
5763 if (options
->MaxIfDepth
== 0) {
5770 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
5772 progress
= do_common_optimization(ir
, true, true, options
,
5773 ctx
->Const
.NativeIntegers
)
5776 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
5780 validate_ir_tree(ir
);
5783 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5784 struct gl_program
*linked_prog
;
5786 if (prog
->_LinkedShaders
[i
] == NULL
)
5789 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
5792 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5794 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
5795 _mesa_shader_stage_to_program(i
),
5797 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5799 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5804 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5807 st_dump_program_for_shader_db(ctx
, prog
);
5812 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
5813 const GLuint outputMapping
[],
5814 struct pipe_stream_output_info
*so
)
5817 struct gl_transform_feedback_info
*info
=
5818 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
5820 for (i
= 0; i
< info
->NumOutputs
; i
++) {
5821 so
->output
[i
].register_index
=
5822 outputMapping
[info
->Outputs
[i
].OutputRegister
];
5823 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
5824 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
5825 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
5826 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
5827 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
5830 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
5831 so
->stride
[i
] = info
->BufferStride
[i
];
5833 so
->num_outputs
= info
->NumOutputs
;