2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
59 #include "util/hash_table.h"
62 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
63 (1 << PROGRAM_CONSTANT) | \
64 (1 << PROGRAM_UNIFORM))
66 #define MAX_GLSL_TEXTURE_OFFSET 4
71 static int swizzle_for_size(int size
);
73 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
75 unsigned num_elements
= 4;
78 type
= type
->without_array();
79 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
80 num_elements
= type
->vector_elements
;
83 int swizzle
= swizzle_for_size(num_elements
);
84 assert(num_elements
+ component
<= 4);
86 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
90 static unsigned is_precise(const ir_variable
*ir
)
94 return ir
->data
.precise
|| ir
->data
.invariant
;
98 * This struct is a corresponding struct to TGSI ureg_src.
102 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
103 int component
= 0, unsigned array_id
= 0)
105 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
108 this->swizzle
= swizzle_for_type(type
, component
);
112 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
113 this->reladdr
= NULL
;
114 this->reladdr2
= NULL
;
115 this->has_index2
= false;
116 this->double_reg2
= false;
117 this->array_id
= array_id
;
118 this->is_double_vertex_input
= false;
121 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
123 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
128 this->swizzle
= SWIZZLE_XYZW
;
131 this->reladdr
= NULL
;
132 this->reladdr2
= NULL
;
133 this->has_index2
= false;
134 this->double_reg2
= false;
136 this->is_double_vertex_input
= false;
139 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
141 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
145 this->index2D
= index2D
;
146 this->swizzle
= SWIZZLE_XYZW
;
149 this->reladdr
= NULL
;
150 this->reladdr2
= NULL
;
151 this->has_index2
= false;
152 this->double_reg2
= false;
154 this->is_double_vertex_input
= false;
159 this->type
= GLSL_TYPE_ERROR
;
160 this->file
= PROGRAM_UNDEFINED
;
166 this->reladdr
= NULL
;
167 this->reladdr2
= NULL
;
168 this->has_index2
= false;
169 this->double_reg2
= false;
171 this->is_double_vertex_input
= false;
174 explicit st_src_reg(st_dst_reg reg
);
176 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
178 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
179 int negate
:4; /**< NEGATE_XYZW mask from mesa */
181 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
182 unsigned has_index2
:1;
183 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
185 * Is this the second half of a double register pair?
186 * currently used for input mapping only.
188 unsigned double_reg2
:1;
189 unsigned is_double_vertex_input
:1;
190 unsigned array_id
:10;
192 /** Register index should be offset by the integer in this reg. */
194 st_src_reg
*reladdr2
;
198 st_src_reg reg
= *this;
207 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
209 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
213 this->writemask
= writemask
;
214 this->reladdr
= NULL
;
215 this->reladdr2
= NULL
;
216 this->has_index2
= false;
221 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
223 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
227 this->writemask
= writemask
;
228 this->reladdr
= NULL
;
229 this->reladdr2
= NULL
;
230 this->has_index2
= false;
237 this->type
= GLSL_TYPE_ERROR
;
238 this->file
= PROGRAM_UNDEFINED
;
242 this->reladdr
= NULL
;
243 this->reladdr2
= NULL
;
244 this->has_index2
= false;
248 explicit st_dst_reg(st_src_reg reg
);
250 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
252 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
253 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
254 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
255 unsigned has_index2
:1;
256 unsigned array_id
:10;
258 /** Register index should be offset by the integer in this reg. */
260 st_src_reg
*reladdr2
;
263 st_src_reg::st_src_reg(st_dst_reg reg
)
265 this->type
= reg
.type
;
266 this->file
= reg
.file
;
267 this->index
= reg
.index
;
268 this->swizzle
= SWIZZLE_XYZW
;
271 this->reladdr
= reg
.reladdr
;
272 this->index2D
= reg
.index2D
;
273 this->reladdr2
= reg
.reladdr2
;
274 this->has_index2
= reg
.has_index2
;
275 this->double_reg2
= false;
276 this->array_id
= reg
.array_id
;
277 this->is_double_vertex_input
= false;
280 st_dst_reg::st_dst_reg(st_src_reg reg
)
282 this->type
= reg
.type
;
283 this->file
= reg
.file
;
284 this->index
= reg
.index
;
285 this->writemask
= WRITEMASK_XYZW
;
286 this->reladdr
= reg
.reladdr
;
287 this->index2D
= reg
.index2D
;
288 this->reladdr2
= reg
.reladdr2
;
289 this->has_index2
= reg
.has_index2
;
290 this->array_id
= reg
.array_id
;
293 class glsl_to_tgsi_instruction
: public exec_node
{
295 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
299 st_src_reg resource
; /**< sampler, image or buffer register */
300 st_src_reg
*tex_offsets
;
302 /** Pointer to the ir source this tree came from for debugging */
305 unsigned op
:8; /**< TGSI opcode */
308 unsigned is_64bit_expanded
:1;
309 unsigned sampler_base
:5;
310 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
311 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
312 glsl_base_type tex_type
:5;
313 unsigned tex_shadow
:1;
314 unsigned image_format
:9;
315 unsigned tex_offset_num_offset
:3;
316 unsigned dead_mask
:4; /**< Used in dead code elimination */
317 unsigned buffer_access
:3; /**< buffer access type */
319 const struct tgsi_opcode_info
*info
;
322 class variable_storage
{
323 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
326 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
327 unsigned array_id
= 0)
328 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
330 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
333 gl_register_file file
;
336 /* Explicit component location. This is given in terms of the GLSL-style
337 * swizzles where each double is a single component, i.e. for 64-bit types
338 * it can only be 0 or 1.
341 ir_variable
*var
; /* variable that maps to this, if any */
345 class immediate_storage
: public exec_node
{
347 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
349 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
350 this->size32
= size32
;
354 /* doubles are stored across 2 gl_constant_values */
355 gl_constant_value values
[4];
356 int size32
; /**< Number of 32-bit components (1-4) */
357 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
360 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
361 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
365 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
368 unsigned gs_out_streams
;
369 enum glsl_interp_mode interp
;
370 enum glsl_base_type base_type
;
371 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
374 static struct inout_decl
*
375 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
377 assert(array_id
!= 0);
379 for (unsigned i
= 0; i
< count
; i
++) {
380 struct inout_decl
*decl
= &decls
[i
];
382 if (array_id
== decl
->array_id
) {
390 static enum glsl_base_type
391 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
394 return GLSL_TYPE_ERROR
;
395 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
397 return decl
->base_type
;
398 return GLSL_TYPE_ERROR
;
401 struct rename_reg_pair
{
406 struct glsl_to_tgsi_visitor
: public ir_visitor
{
408 glsl_to_tgsi_visitor();
409 ~glsl_to_tgsi_visitor();
411 struct gl_context
*ctx
;
412 struct gl_program
*prog
;
413 struct gl_shader_program
*shader_program
;
414 struct gl_linked_shader
*shader
;
415 struct gl_shader_compiler_options
*options
;
419 unsigned *array_sizes
;
420 unsigned max_num_arrays
;
423 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
425 unsigned num_input_arrays
;
426 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
427 unsigned num_outputs
;
428 unsigned num_output_arrays
;
430 int num_address_regs
;
431 uint32_t samplers_used
;
432 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
433 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
435 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
436 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
437 bool indirect_addr_consts
;
438 int wpos_transform_const
;
441 bool native_integers
;
444 bool use_shared_memory
;
448 variable_storage
*find_variable_storage(ir_variable
*var
);
450 int add_constant(gl_register_file file
, gl_constant_value values
[8],
451 int size
, int datatype
, uint16_t *swizzle_out
);
453 st_src_reg
get_temp(const glsl_type
*type
);
454 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
456 st_src_reg
st_src_reg_for_double(double val
);
457 st_src_reg
st_src_reg_for_float(float val
);
458 st_src_reg
st_src_reg_for_int(int val
);
459 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
462 * \name Visit methods
464 * As typical for the visitor pattern, there must be one \c visit method for
465 * each concrete subclass of \c ir_instruction. Virtual base classes within
466 * the hierarchy should not have \c visit methods.
469 virtual void visit(ir_variable
*);
470 virtual void visit(ir_loop
*);
471 virtual void visit(ir_loop_jump
*);
472 virtual void visit(ir_function_signature
*);
473 virtual void visit(ir_function
*);
474 virtual void visit(ir_expression
*);
475 virtual void visit(ir_swizzle
*);
476 virtual void visit(ir_dereference_variable
*);
477 virtual void visit(ir_dereference_array
*);
478 virtual void visit(ir_dereference_record
*);
479 virtual void visit(ir_assignment
*);
480 virtual void visit(ir_constant
*);
481 virtual void visit(ir_call
*);
482 virtual void visit(ir_return
*);
483 virtual void visit(ir_discard
*);
484 virtual void visit(ir_texture
*);
485 virtual void visit(ir_if
*);
486 virtual void visit(ir_emit_vertex
*);
487 virtual void visit(ir_end_primitive
*);
488 virtual void visit(ir_barrier
*);
491 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
493 void visit_atomic_counter_intrinsic(ir_call
*);
494 void visit_ssbo_intrinsic(ir_call
*);
495 void visit_membar_intrinsic(ir_call
*);
496 void visit_shared_intrinsic(ir_call
*);
497 void visit_image_intrinsic(ir_call
*);
498 void visit_generic_intrinsic(ir_call
*, unsigned op
);
502 /** List of variable_storage */
503 struct hash_table
*variables
;
505 /** List of immediate_storage */
506 exec_list immediates
;
507 unsigned num_immediates
;
509 /** List of glsl_to_tgsi_instruction */
510 exec_list instructions
;
512 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
513 st_dst_reg dst
= undef_dst
,
514 st_src_reg src0
= undef_src
,
515 st_src_reg src1
= undef_src
,
516 st_src_reg src2
= undef_src
,
517 st_src_reg src3
= undef_src
);
519 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
520 st_dst_reg dst
, st_dst_reg dst1
,
521 st_src_reg src0
= undef_src
,
522 st_src_reg src1
= undef_src
,
523 st_src_reg src2
= undef_src
,
524 st_src_reg src3
= undef_src
);
526 unsigned get_opcode(unsigned op
,
528 st_src_reg src0
, st_src_reg src1
);
531 * Emit the correct dot-product instruction for the type of arguments
533 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
539 void emit_scalar(ir_instruction
*ir
, unsigned op
,
540 st_dst_reg dst
, st_src_reg src0
);
542 void emit_scalar(ir_instruction
*ir
, unsigned op
,
543 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
545 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
547 void get_deref_offsets(ir_dereference
*ir
,
548 unsigned *array_size
,
553 void calc_deref_offsets(ir_dereference
*tail
,
554 unsigned *array_elements
,
556 st_src_reg
*indirect
,
558 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
560 bool try_emit_mad(ir_expression
*ir
,
562 bool try_emit_mad_for_and_not(ir_expression
*ir
,
565 void emit_swz(ir_expression
*ir
);
567 bool process_move_condition(ir_rvalue
*ir
);
569 void simplify_cmp(void);
571 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
572 void get_first_temp_read(int *first_reads
);
573 void get_first_temp_write(int *first_writes
);
574 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
575 void get_last_temp_write(int *last_writes
);
577 void copy_propagate(void);
578 int eliminate_dead_code(void);
580 void merge_two_dsts(void);
581 void merge_registers(void);
582 void renumber_registers(void);
584 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
585 st_dst_reg
*l
, st_src_reg
*r
,
586 st_src_reg
*cond
, bool cond_swap
);
591 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
592 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
593 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
596 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
599 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
603 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
606 prog
->data
->LinkStatus
= linking_failure
;
610 swizzle_for_size(int size
)
612 static const int size_swizzles
[4] = {
613 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
614 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
615 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
616 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
619 assert((size
>= 1) && (size
<= 4));
620 return size_swizzles
[size
- 1];
624 is_resource_instruction(unsigned opcode
)
627 case TGSI_OPCODE_RESQ
:
628 case TGSI_OPCODE_LOAD
:
629 case TGSI_OPCODE_ATOMUADD
:
630 case TGSI_OPCODE_ATOMXCHG
:
631 case TGSI_OPCODE_ATOMCAS
:
632 case TGSI_OPCODE_ATOMAND
:
633 case TGSI_OPCODE_ATOMOR
:
634 case TGSI_OPCODE_ATOMXOR
:
635 case TGSI_OPCODE_ATOMUMIN
:
636 case TGSI_OPCODE_ATOMUMAX
:
637 case TGSI_OPCODE_ATOMIMIN
:
638 case TGSI_OPCODE_ATOMIMAX
:
646 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
648 return op
->info
->num_dst
;
652 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
654 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
655 op
->info
->num_src
- 1 : op
->info
->num_src
;
658 glsl_to_tgsi_instruction
*
659 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
660 st_dst_reg dst
, st_dst_reg dst1
,
661 st_src_reg src0
, st_src_reg src1
,
662 st_src_reg src2
, st_src_reg src3
)
664 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
665 int num_reladdr
= 0, i
, j
;
666 bool dst_is_64bit
[2];
668 op
= get_opcode(op
, dst
, src0
, src1
);
670 /* If we have to do relative addressing, we want to load the ARL
671 * reg directly for one of the regs, and preload the other reladdr
672 * sources into temps.
674 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
675 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
676 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
677 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
678 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
679 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
681 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
682 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
683 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
684 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
686 if (dst
.reladdr
|| dst
.reladdr2
) {
688 emit_arl(ir
, address_reg
, *dst
.reladdr
);
690 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
694 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
697 assert(num_reladdr
== 0);
699 /* inst->op has only 8 bits. */
700 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
703 inst
->precise
= this->precise
;
704 inst
->info
= tgsi_get_opcode_info(op
);
711 inst
->is_64bit_expanded
= false;
714 inst
->tex_offsets
= NULL
;
715 inst
->tex_offset_num_offset
= 0;
717 inst
->tex_shadow
= 0;
718 /* default to float, for paths where this is not initialized
719 * (since 0==UINT which is likely wrong):
721 inst
->tex_type
= GLSL_TYPE_FLOAT
;
723 /* Update indirect addressing status used by TGSI */
724 if (dst
.reladdr
|| dst
.reladdr2
) {
726 case PROGRAM_STATE_VAR
:
727 case PROGRAM_CONSTANT
:
728 case PROGRAM_UNIFORM
:
729 this->indirect_addr_consts
= true;
731 case PROGRAM_IMMEDIATE
:
732 assert(!"immediates should not have indirect addressing");
739 for (i
= 0; i
< 4; i
++) {
740 if(inst
->src
[i
].reladdr
) {
741 switch(inst
->src
[i
].file
) {
742 case PROGRAM_STATE_VAR
:
743 case PROGRAM_CONSTANT
:
744 case PROGRAM_UNIFORM
:
745 this->indirect_addr_consts
= true;
747 case PROGRAM_IMMEDIATE
:
748 assert(!"immediates should not have indirect addressing");
758 * This section contains the double processing.
759 * GLSL just represents doubles as single channel values,
760 * however most HW and TGSI represent doubles as pairs of register channels.
762 * so we have to fixup destination writemask/index and src swizzle/indexes.
763 * dest writemasks need to translate from single channel write mask
764 * to a dual-channel writemask, but also need to modify the index,
765 * if we are touching the Z,W fields in the pre-translated writemask.
767 * src channels have similiar index modifications along with swizzle
768 * changes to we pick the XY, ZW pairs from the correct index.
770 * GLSL [0].x -> TGSI [0].xy
771 * GLSL [0].y -> TGSI [0].zw
772 * GLSL [0].z -> TGSI [1].xy
773 * GLSL [0].w -> TGSI [1].zw
775 for (j
= 0; j
< 2; j
++) {
776 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
777 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
778 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
779 if (glsl_base_type_is_64bit(type
))
780 dst_is_64bit
[j
] = true;
784 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
785 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
786 glsl_to_tgsi_instruction
*dinst
= NULL
;
787 int initial_src_swz
[4], initial_src_idx
[4];
788 int initial_dst_idx
[2], initial_dst_writemask
[2];
789 /* select the writemask for dst0 or dst1 */
790 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
792 /* copy out the writemask, index and swizzles for all src/dsts. */
793 for (j
= 0; j
< 2; j
++) {
794 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
795 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
798 for (j
= 0; j
< 4; j
++) {
799 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
800 initial_src_idx
[j
] = inst
->src
[j
].index
;
804 * scan all the components in the dst writemask
805 * generate an instruction for each of them if required.
810 int i
= u_bit_scan(&writemask
);
812 /* before emitting the instruction, see if we have to adjust load / store
814 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
815 addr
.file
== PROGRAM_UNDEFINED
) {
816 /* We have to advance the buffer address by 16 */
817 addr
= get_temp(glsl_type::uint_type
);
818 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
819 inst
->src
[0], st_src_reg_for_int(16));
822 /* first time use previous instruction */
826 /* create a new instructions for subsequent attempts */
827 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
832 this->instructions
.push_tail(dinst
);
833 dinst
->is_64bit_expanded
= true;
835 /* modify the destination if we are splitting */
836 for (j
= 0; j
< 2; j
++) {
837 if (dst_is_64bit
[j
]) {
838 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
839 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
841 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
842 dinst
->src
[0] = addr
;
843 if (dinst
->op
!= TGSI_OPCODE_STORE
)
844 dinst
->dst
[j
].index
++;
847 /* if we aren't writing to a double, just get the bit of the initial writemask
849 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
853 /* modify the src registers */
854 for (j
= 0; j
< 4; j
++) {
855 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
857 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
858 dinst
->src
[j
].index
= initial_src_idx
[j
];
860 dinst
->src
[j
].double_reg2
= true;
861 dinst
->src
[j
].index
++;
865 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
867 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
870 /* some opcodes are special case in what they use as sources
871 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
872 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
873 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
874 op
== TGSI_OPCODE_DLDEXP
||
875 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
876 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
883 this->instructions
.push_tail(inst
);
890 glsl_to_tgsi_instruction
*
891 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
893 st_src_reg src0
, st_src_reg src1
,
894 st_src_reg src2
, st_src_reg src3
)
896 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
900 * Determines whether to use an integer, unsigned integer, or float opcode
901 * based on the operands and input opcode, then emits the result.
904 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
906 st_src_reg src0
, st_src_reg src1
)
908 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
910 if (op
== TGSI_OPCODE_MOV
)
913 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
914 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
915 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
916 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
918 if (is_resource_instruction(op
))
920 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
921 type
= GLSL_TYPE_INT64
;
922 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
923 type
= GLSL_TYPE_UINT64
;
924 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
925 type
= GLSL_TYPE_DOUBLE
;
926 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
927 type
= GLSL_TYPE_FLOAT
;
928 else if (native_integers
)
929 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
931 #define case7(c, f, i, u, d, i64, ui64) \
932 case TGSI_OPCODE_##c: \
933 if (type == GLSL_TYPE_UINT64) \
934 op = TGSI_OPCODE_##ui64; \
935 else if (type == GLSL_TYPE_INT64) \
936 op = TGSI_OPCODE_##i64; \
937 else if (type == GLSL_TYPE_DOUBLE) \
938 op = TGSI_OPCODE_##d; \
939 else if (type == GLSL_TYPE_INT) \
940 op = TGSI_OPCODE_##i; \
941 else if (type == GLSL_TYPE_UINT) \
942 op = TGSI_OPCODE_##u; \
944 op = TGSI_OPCODE_##f; \
947 #define casecomp(c, f, i, u, d, i64, ui64) \
948 case TGSI_OPCODE_##c: \
949 if (type == GLSL_TYPE_INT64) \
950 op = TGSI_OPCODE_##i64; \
951 else if (type == GLSL_TYPE_UINT64) \
952 op = TGSI_OPCODE_##ui64; \
953 else if (type == GLSL_TYPE_DOUBLE) \
954 op = TGSI_OPCODE_##d; \
955 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
956 op = TGSI_OPCODE_##i; \
957 else if (type == GLSL_TYPE_UINT) \
958 op = TGSI_OPCODE_##u; \
959 else if (native_integers) \
960 op = TGSI_OPCODE_##f; \
962 op = TGSI_OPCODE_##c; \
966 /* Some instructions are initially selected without considering the type.
967 * This fixes the type:
969 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
971 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
972 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
973 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
974 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
975 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
976 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
977 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
978 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
979 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
980 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
981 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
982 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
983 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
984 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
985 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
986 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
988 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
989 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
990 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
991 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
992 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
993 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
994 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
995 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
997 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
998 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
999 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
1000 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
1005 assert(op
!= TGSI_OPCODE_LAST
);
1009 glsl_to_tgsi_instruction
*
1010 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1011 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1014 static const unsigned dot_opcodes
[] = {
1015 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1018 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1022 * Emits TGSI scalar opcodes to produce unique answers across channels.
1024 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1025 * channel determines the result across all channels. So to do a vec4
1026 * of this operation, we want to emit a scalar per source channel used
1027 * to produce dest channels.
1030 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1032 st_src_reg orig_src0
, st_src_reg orig_src1
)
1035 int done_mask
= ~dst
.writemask
;
1037 /* TGSI RCP is a scalar operation splatting results to all channels,
1038 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1041 for (i
= 0; i
< 4; i
++) {
1042 GLuint this_mask
= (1 << i
);
1043 st_src_reg src0
= orig_src0
;
1044 st_src_reg src1
= orig_src1
;
1046 if (done_mask
& this_mask
)
1049 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1050 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1051 for (j
= i
+ 1; j
< 4; j
++) {
1052 /* If there is another enabled component in the destination that is
1053 * derived from the same inputs, generate its value on this pass as
1056 if (!(done_mask
& (1 << j
)) &&
1057 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1058 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1059 this_mask
|= (1 << j
);
1062 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1063 src0_swiz
, src0_swiz
);
1064 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1065 src1_swiz
, src1_swiz
);
1067 dst
.writemask
= this_mask
;
1068 emit_asm(ir
, op
, dst
, src0
, src1
);
1069 done_mask
|= this_mask
;
1074 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1075 st_dst_reg dst
, st_src_reg src0
)
1077 st_src_reg undef
= undef_src
;
1079 undef
.swizzle
= SWIZZLE_XXXX
;
1081 emit_scalar(ir
, op
, dst
, src0
, undef
);
1085 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1086 st_dst_reg dst
, st_src_reg src0
)
1088 int op
= TGSI_OPCODE_ARL
;
1090 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1091 op
= TGSI_OPCODE_UARL
;
1093 assert(dst
.file
== PROGRAM_ADDRESS
);
1094 if (dst
.index
>= this->num_address_regs
)
1095 this->num_address_regs
= dst
.index
+ 1;
1097 emit_asm(NULL
, op
, dst
, src0
);
1101 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1102 gl_constant_value values
[8], int size
, int datatype
,
1103 uint16_t *swizzle_out
)
1105 if (file
== PROGRAM_CONSTANT
) {
1106 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1107 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1108 size
, datatype
, &swizzle
);
1110 *swizzle_out
= swizzle
;
1114 assert(file
== PROGRAM_IMMEDIATE
);
1117 immediate_storage
*entry
;
1118 int size32
= size
* ((datatype
== GL_DOUBLE
||
1119 datatype
== GL_INT64_ARB
||
1120 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1123 /* Search immediate storage to see if we already have an identical
1124 * immediate that we can use instead of adding a duplicate entry.
1126 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1127 immediate_storage
*tmp
= entry
;
1129 for (i
= 0; i
* 4 < size32
; i
++) {
1130 int slot_size
= MIN2(size32
- (i
* 4), 4);
1131 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1133 if (memcmp(tmp
->values
, &values
[i
* 4],
1134 slot_size
* sizeof(gl_constant_value
)))
1137 /* Everything matches, keep going until the full size is matched */
1138 tmp
= (immediate_storage
*)tmp
->next
;
1141 /* The full value matched */
1142 if (i
* 4 >= size32
)
1148 for (i
= 0; i
* 4 < size32
; i
++) {
1149 int slot_size
= MIN2(size32
- (i
* 4), 4);
1150 /* Add this immediate to the list. */
1151 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1152 this->immediates
.push_tail(entry
);
1153 this->num_immediates
++;
1159 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1161 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1162 union gl_constant_value uval
;
1165 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1171 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1173 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1174 union gl_constant_value uval
[2];
1176 memcpy(uval
, &val
, sizeof(uval
));
1177 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1178 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1183 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1185 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1186 union gl_constant_value uval
;
1188 assert(native_integers
);
1191 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1197 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1199 if (native_integers
)
1200 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1201 st_src_reg_for_int(val
);
1203 return st_src_reg_for_float(val
);
1207 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1209 return type
->count_attribute_slots(is_vs_input
);
1213 type_size(const struct glsl_type
*type
)
1215 return type
->count_attribute_slots(false);
1219 * If the given GLSL type is an array or matrix or a structure containing
1220 * an array/matrix member, return true. Else return false.
1222 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1223 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1224 * we have an array that might be indexed with a variable, we need to use
1225 * the later storage type.
1228 type_has_array_or_matrix(const glsl_type
*type
)
1230 if (type
->is_array() || type
->is_matrix())
1233 if (type
->is_record()) {
1234 for (unsigned i
= 0; i
< type
->length
; i
++) {
1235 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1246 * In the initial pass of codegen, we assign temporary numbers to
1247 * intermediate results. (not SSA -- variable assignments will reuse
1251 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1255 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1260 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1261 if (next_array
>= max_num_arrays
) {
1262 max_num_arrays
+= 32;
1263 array_sizes
= (unsigned*)
1264 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1267 src
.file
= PROGRAM_ARRAY
;
1269 src
.array_id
= next_array
+ 1;
1270 array_sizes
[next_array
] = type_size(type
);
1274 src
.file
= PROGRAM_TEMPORARY
;
1275 src
.index
= next_temp
;
1276 next_temp
+= type_size(type
);
1279 if (type
->is_array() || type
->is_record()) {
1280 src
.swizzle
= SWIZZLE_NOOP
;
1282 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1289 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1291 struct hash_entry
*entry
;
1293 entry
= _mesa_hash_table_search(this->variables
, var
);
1297 return (variable_storage
*)entry
->data
;
1301 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1303 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1304 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1305 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1308 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1310 const ir_state_slot
*const slots
= ir
->get_state_slots();
1311 assert(slots
!= NULL
);
1313 /* Check if this statevar's setup in the STATE file exactly
1314 * matches how we'll want to reference it as a
1315 * struct/array/whatever. If not, then we need to move it into
1316 * temporary storage and hope that it'll get copy-propagated
1319 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1320 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1325 variable_storage
*storage
;
1327 if (i
== ir
->get_num_state_slots()) {
1328 /* We'll set the index later. */
1329 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1331 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1335 /* The variable_storage constructor allocates slots based on the size
1336 * of the type. However, this had better match the number of state
1337 * elements that we're going to copy into the new temporary.
1339 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1341 dst
= st_dst_reg(get_temp(ir
->type
));
1343 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1346 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1350 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1351 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1352 (gl_state_index
*)slots
[i
].tokens
);
1354 if (storage
->file
== PROGRAM_STATE_VAR
) {
1355 if (storage
->index
== -1) {
1356 storage
->index
= index
;
1358 assert(index
== storage
->index
+ (int)i
);
1361 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1362 * the data being moved since MOV does not care about the type of
1363 * data it is moving, and we don't want to declare registers with
1364 * array or struct types.
1366 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1367 src
.swizzle
= slots
[i
].swizzle
;
1368 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1369 /* even a float takes up a whole vec4 reg in a struct/array. */
1374 if (storage
->file
== PROGRAM_TEMPORARY
&&
1375 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1376 fail_link(this->shader_program
,
1377 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1378 ir
->name
, dst
.index
- storage
->index
,
1379 type_size(ir
->type
));
1385 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1387 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1389 visit_exec_list(&ir
->body_instructions
, this);
1391 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1395 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1398 case ir_loop_jump::jump_break
:
1399 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1401 case ir_loop_jump::jump_continue
:
1402 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1409 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1416 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1418 /* Ignore function bodies other than main() -- we shouldn't see calls to
1419 * them since they should all be inlined before we get to glsl_to_tgsi.
1421 if (strcmp(ir
->name
, "main") == 0) {
1422 const ir_function_signature
*sig
;
1425 sig
= ir
->matching_signature(NULL
, &empty
, false);
1429 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1436 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1438 int nonmul_operand
= 1 - mul_operand
;
1440 st_dst_reg result_dst
;
1442 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1443 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1446 expr
->operands
[0]->accept(this);
1448 expr
->operands
[1]->accept(this);
1450 ir
->operands
[nonmul_operand
]->accept(this);
1453 this->result
= get_temp(ir
->type
);
1454 result_dst
= st_dst_reg(this->result
);
1455 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1456 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1462 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1464 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1465 * implemented using multiplication, and logical-or is implemented using
1466 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1467 * As result, the logical expression (a & !b) can be rewritten as:
1471 * - (a * 1) - (a * b)
1475 * This final expression can be implemented as a single MAD(a, -b, a)
1479 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1481 const int other_operand
= 1 - try_operand
;
1484 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1485 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1488 ir
->operands
[other_operand
]->accept(this);
1490 expr
->operands
[0]->accept(this);
1493 b
.negate
= ~b
.negate
;
1495 this->result
= get_temp(ir
->type
);
1496 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1502 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1503 st_src_reg
*reg
, int *num_reladdr
)
1505 if (!reg
->reladdr
&& !reg
->reladdr2
)
1508 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1509 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1511 if (*num_reladdr
!= 1) {
1512 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1514 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1522 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1524 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1526 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1528 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1529 if (try_emit_mad(ir
, 1))
1531 if (try_emit_mad(ir
, 0))
1535 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1537 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1538 if (try_emit_mad_for_and_not(ir
, 1))
1540 if (try_emit_mad_for_and_not(ir
, 0))
1544 if (ir
->operation
== ir_quadop_vector
)
1545 assert(!"ir_quadop_vector should have been lowered");
1547 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1548 this->result
.file
= PROGRAM_UNDEFINED
;
1549 ir
->operands
[operand
]->accept(this);
1550 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1551 printf("Failed to get tree for expression operand:\n");
1552 ir
->operands
[operand
]->print();
1556 op
[operand
] = this->result
;
1558 /* Matrix expression operands should have been broken down to vector
1559 * operations already.
1561 assert(!ir
->operands
[operand
]->type
->is_matrix());
1564 visit_expression(ir
, op
);
1567 /* The non-recursive part of the expression visitor lives in a separate
1568 * function and should be prevented from being inlined, to avoid a stack
1569 * explosion when deeply nested expressions are visited.
1572 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1574 st_src_reg result_src
;
1575 st_dst_reg result_dst
;
1577 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1578 if (ir
->operands
[1]) {
1579 vector_elements
= MAX2(vector_elements
,
1580 ir
->operands
[1]->type
->vector_elements
);
1583 this->result
.file
= PROGRAM_UNDEFINED
;
1585 /* Storage for our result. Ideally for an assignment we'd be using
1586 * the actual storage for the result here, instead.
1588 result_src
= get_temp(ir
->type
);
1589 /* convenience for the emit functions below. */
1590 result_dst
= st_dst_reg(result_src
);
1591 /* Limit writes to the channels that will be used by result_src later.
1592 * This does limit this temp's use as a temporary for multi-instruction
1595 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1597 switch (ir
->operation
) {
1598 case ir_unop_logic_not
:
1599 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1600 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1602 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1603 * older GPUs implement SEQ using multiple instructions (i915 uses two
1604 * SGE instructions and a MUL instruction). Since our logic values are
1605 * 0.0 and 1.0, 1-x also implements !x.
1607 op
[0].negate
= ~op
[0].negate
;
1608 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1612 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1613 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1614 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1615 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1616 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1617 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1619 op
[0].negate
= ~op
[0].negate
;
1623 case ir_unop_subroutine_to_int
:
1624 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1627 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1628 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1629 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1630 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1631 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1632 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1634 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1637 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1640 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1644 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1647 assert(!"not reached: should be handled by exp_to_exp2");
1650 assert(!"not reached: should be handled by log_to_log2");
1653 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1656 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1659 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1661 case ir_unop_saturate
: {
1662 glsl_to_tgsi_instruction
*inst
;
1663 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1664 inst
->saturate
= true;
1669 case ir_unop_dFdx_coarse
:
1670 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1672 case ir_unop_dFdx_fine
:
1673 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1676 case ir_unop_dFdy_coarse
:
1677 case ir_unop_dFdy_fine
:
1679 /* The X component contains 1 or -1 depending on whether the framebuffer
1680 * is a FBO or the window system buffer, respectively.
1681 * It is then multiplied with the source operand of DDY.
1683 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1684 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1686 unsigned transform_y_index
=
1687 _mesa_add_state_reference(this->prog
->Parameters
,
1690 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1692 glsl_type::vec4_type
);
1693 transform_y
.swizzle
= SWIZZLE_XXXX
;
1695 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1697 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1698 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1699 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1703 case ir_unop_frexp_sig
:
1704 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1707 case ir_unop_frexp_exp
:
1708 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1711 case ir_unop_noise
: {
1712 /* At some point, a motivated person could add a better
1713 * implementation of noise. Currently not even the nvidia
1714 * binary drivers do anything more than this. In any case, the
1715 * place to do this is in the GL state tracker, not the poor
1718 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1723 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1726 op
[1].negate
= ~op
[1].negate
;
1727 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1731 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1734 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1737 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1738 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1740 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1744 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1746 case ir_binop_greater
:
1747 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1749 case ir_binop_lequal
:
1750 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1752 case ir_binop_gequal
:
1753 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1755 case ir_binop_equal
:
1756 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1758 case ir_binop_nequal
:
1759 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_all_equal
:
1762 /* "==" operator producing a scalar boolean. */
1763 if (ir
->operands
[0]->type
->is_vector() ||
1764 ir
->operands
[1]->type
->is_vector()) {
1765 st_src_reg temp
= get_temp(native_integers
?
1766 glsl_type::uvec4_type
:
1767 glsl_type::vec4_type
);
1769 if (native_integers
) {
1770 st_dst_reg temp_dst
= st_dst_reg(temp
);
1771 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1773 if (ir
->operands
[0]->type
->is_boolean() &&
1774 ir
->operands
[1]->as_constant() &&
1775 ir
->operands
[1]->as_constant()->is_one()) {
1776 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1778 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1781 /* Emit 1-3 AND operations to combine the SEQ results. */
1782 switch (ir
->operands
[0]->type
->vector_elements
) {
1786 temp_dst
.writemask
= WRITEMASK_Y
;
1787 temp1
.swizzle
= SWIZZLE_YYYY
;
1788 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1789 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1792 temp_dst
.writemask
= WRITEMASK_X
;
1793 temp1
.swizzle
= SWIZZLE_XXXX
;
1794 temp2
.swizzle
= SWIZZLE_YYYY
;
1795 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1796 temp_dst
.writemask
= WRITEMASK_Y
;
1797 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1798 temp2
.swizzle
= SWIZZLE_WWWW
;
1799 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1802 temp1
.swizzle
= SWIZZLE_XXXX
;
1803 temp2
.swizzle
= SWIZZLE_YYYY
;
1804 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1806 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1808 /* After the dot-product, the value will be an integer on the
1809 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1811 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1813 /* Negating the result of the dot-product gives values on the range
1814 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1815 * This is achieved using SGE.
1817 st_src_reg sge_src
= result_src
;
1818 sge_src
.negate
= ~sge_src
.negate
;
1819 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1822 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1825 case ir_binop_any_nequal
:
1826 /* "!=" operator producing a scalar boolean. */
1827 if (ir
->operands
[0]->type
->is_vector() ||
1828 ir
->operands
[1]->type
->is_vector()) {
1829 st_src_reg temp
= get_temp(native_integers
?
1830 glsl_type::uvec4_type
:
1831 glsl_type::vec4_type
);
1832 if (ir
->operands
[0]->type
->is_boolean() &&
1833 ir
->operands
[1]->as_constant() &&
1834 ir
->operands
[1]->as_constant()->is_zero()) {
1835 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1837 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1840 if (native_integers
) {
1841 st_dst_reg temp_dst
= st_dst_reg(temp
);
1842 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1844 /* Emit 1-3 OR operations to combine the SNE results. */
1845 switch (ir
->operands
[0]->type
->vector_elements
) {
1849 temp_dst
.writemask
= WRITEMASK_Y
;
1850 temp1
.swizzle
= SWIZZLE_YYYY
;
1851 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1852 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1855 temp_dst
.writemask
= WRITEMASK_X
;
1856 temp1
.swizzle
= SWIZZLE_XXXX
;
1857 temp2
.swizzle
= SWIZZLE_YYYY
;
1858 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1859 temp_dst
.writemask
= WRITEMASK_Y
;
1860 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1861 temp2
.swizzle
= SWIZZLE_WWWW
;
1862 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1865 temp1
.swizzle
= SWIZZLE_XXXX
;
1866 temp2
.swizzle
= SWIZZLE_YYYY
;
1867 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1869 /* After the dot-product, the value will be an integer on the
1870 * range [0,4]. Zero stays zero, and positive values become 1.0.
1872 glsl_to_tgsi_instruction
*const dp
=
1873 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1874 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1875 /* The clamping to [0,1] can be done for free in the fragment
1876 * shader with a saturate.
1878 dp
->saturate
= true;
1880 /* Negating the result of the dot-product gives values on the range
1881 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1882 * achieved using SLT.
1884 st_src_reg slt_src
= result_src
;
1885 slt_src
.negate
= ~slt_src
.negate
;
1886 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1890 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1894 case ir_binop_logic_xor
:
1895 if (native_integers
)
1896 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1898 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1901 case ir_binop_logic_or
: {
1902 if (native_integers
) {
1903 /* If integers are used as booleans, we can use an actual "or"
1906 assert(native_integers
);
1907 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1909 /* After the addition, the value will be an integer on the
1910 * range [0,2]. Zero stays zero, and positive values become 1.0.
1912 glsl_to_tgsi_instruction
*add
=
1913 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1914 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1915 /* The clamping to [0,1] can be done for free in the fragment
1916 * shader with a saturate if floats are being used as boolean values.
1918 add
->saturate
= true;
1920 /* Negating the result of the addition gives values on the range
1921 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1922 * is achieved using SLT.
1924 st_src_reg slt_src
= result_src
;
1925 slt_src
.negate
= ~slt_src
.negate
;
1926 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1932 case ir_binop_logic_and
:
1933 /* If native integers are disabled, the bool args are stored as float 0.0
1934 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1935 * actual AND opcode.
1937 if (native_integers
)
1938 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1940 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1944 assert(ir
->operands
[0]->type
->is_vector());
1945 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1946 emit_dp(ir
, result_dst
, op
[0], op
[1],
1947 ir
->operands
[0]->type
->vector_elements
);
1952 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1954 /* This is the only instruction sequence that makes the game "Risen"
1955 * render correctly. ABS is not required for the game, but since GLSL
1956 * declares negative values as "undefined", allowing us to do whatever
1957 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1960 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1961 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1965 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1968 if (native_integers
) {
1969 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1972 /* fallthrough to next case otherwise */
1974 if (native_integers
) {
1975 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1978 /* fallthrough to next case otherwise */
1981 case ir_unop_i642u64
:
1982 case ir_unop_u642i64
:
1983 /* Converting between signed and unsigned integers is a no-op. */
1985 result_src
.type
= result_dst
.type
;
1988 if (native_integers
) {
1989 /* Booleans are stored as integers using ~0 for true and 0 for false.
1990 * GLSL requires that int(bool) return 1 for true and 0 for false.
1991 * This conversion is done with AND, but it could be done with NEG.
1993 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1995 /* Booleans and integers are both stored as floats when native
1996 * integers are disabled.
2002 if (native_integers
)
2003 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2005 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2008 if (native_integers
)
2009 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2011 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2013 case ir_unop_bitcast_f2i
:
2014 case ir_unop_bitcast_f2u
:
2015 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2016 if (op
[0].negate
|| op
[0].abs
)
2017 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2020 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2023 case ir_unop_bitcast_i2f
:
2024 case ir_unop_bitcast_u2f
:
2026 result_src
.type
= GLSL_TYPE_FLOAT
;
2029 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2032 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2035 if (native_integers
)
2036 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2038 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2040 case ir_unop_bitcast_u642d
:
2041 case ir_unop_bitcast_i642d
:
2043 result_src
.type
= GLSL_TYPE_DOUBLE
;
2045 case ir_unop_bitcast_d2i64
:
2047 result_src
.type
= GLSL_TYPE_INT64
;
2049 case ir_unop_bitcast_d2u64
:
2051 result_src
.type
= GLSL_TYPE_UINT64
;
2054 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2057 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2060 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2062 case ir_unop_round_even
:
2063 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2066 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2070 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2073 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2076 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2079 case ir_unop_bit_not
:
2080 if (native_integers
) {
2081 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2085 if (native_integers
) {
2086 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2089 case ir_binop_lshift
:
2090 case ir_binop_rshift
:
2091 if (native_integers
) {
2092 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
2096 if (glsl_base_type_is_64bit(op
[0].type
)) {
2097 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
2100 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
2101 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
2106 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
2109 case ir_binop_bit_and
:
2110 if (native_integers
) {
2111 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2114 case ir_binop_bit_xor
:
2115 if (native_integers
) {
2116 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2119 case ir_binop_bit_or
:
2120 if (native_integers
) {
2121 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2125 assert(!"GLSL 1.30 features unsupported");
2128 case ir_binop_ubo_load
: {
2129 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2130 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2131 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2132 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 1;
2133 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2136 cbuf
.type
= ir
->type
->base_type
;
2137 cbuf
.file
= PROGRAM_CONSTANT
;
2139 cbuf
.reladdr
= NULL
;
2142 cbuf
.index2D
= const_block
;
2144 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2146 if (const_offset_ir
) {
2147 /* Constant index into constant buffer */
2148 cbuf
.reladdr
= NULL
;
2149 cbuf
.index
= const_offset
/ 16;
2152 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2153 st_src_reg offset
= op
[1];
2155 /* The OpenGL spec is written in such a way that accesses with
2156 * non-constant offset are almost always vec4-aligned. The only
2157 * exception to this are members of structs in arrays of structs:
2158 * each struct in an array of structs is at least vec4-aligned,
2159 * but single-element and [ui]vec2 members of the struct may be at
2160 * an offset that is not a multiple of 16 bytes.
2162 * Here, we extract that offset, relying on previous passes to always
2163 * generate offset expressions of the form (+ expr constant_offset).
2165 * Note that the std430 layout, which allows more cases of alignment
2166 * less than vec4 in arrays, is not supported for uniform blocks, so
2167 * we do not have to deal with it here.
2169 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2170 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2171 if (const_offset_ir
) {
2172 const_offset
= const_offset_ir
->value
.u
[0];
2173 cbuf
.index
= const_offset
/ 16;
2174 offset_expr
->operands
[0]->accept(this);
2175 offset
= this->result
;
2179 /* Relative/variable index into constant buffer */
2180 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2181 st_src_reg_for_int(4));
2182 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2183 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2186 if (const_uniform_block
) {
2187 /* Constant constant buffer */
2188 cbuf
.reladdr2
= NULL
;
2189 cbuf
.has_index2
= true;
2192 /* Relative/variable constant buffer */
2193 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2194 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2195 cbuf
.has_index2
= true;
2198 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2199 if (glsl_base_type_is_64bit(cbuf
.type
))
2200 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2201 const_offset
% 16 / 8,
2202 const_offset
% 16 / 8,
2203 const_offset
% 16 / 8);
2205 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2206 const_offset
% 16 / 4,
2207 const_offset
% 16 / 4,
2208 const_offset
% 16 / 4);
2210 if (ir
->type
->is_boolean()) {
2211 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2213 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2218 /* note: we have to reorder the three args here */
2219 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2222 if (this->ctx
->Const
.NativeIntegers
)
2223 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2225 op
[0].negate
= ~op
[0].negate
;
2226 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2229 case ir_triop_bitfield_extract
:
2230 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2232 case ir_quadop_bitfield_insert
:
2233 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2235 case ir_unop_bitfield_reverse
:
2236 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2238 case ir_unop_bit_count
:
2239 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2241 case ir_unop_find_msb
:
2242 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2244 case ir_unop_find_lsb
:
2245 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2247 case ir_binop_imul_high
:
2248 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2251 /* In theory, MAD is incorrect here. */
2253 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2255 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2257 case ir_unop_interpolate_at_centroid
:
2258 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2260 case ir_binop_interpolate_at_offset
: {
2261 /* The y coordinate needs to be flipped for the default fb */
2262 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2263 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2265 unsigned transform_y_index
=
2266 _mesa_add_state_reference(this->prog
->Parameters
,
2269 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2271 glsl_type::vec4_type
);
2272 transform_y
.swizzle
= SWIZZLE_XXXX
;
2274 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2275 st_dst_reg temp_dst
= st_dst_reg(temp
);
2277 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2278 temp_dst
.writemask
= WRITEMASK_Y
;
2279 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2280 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2283 case ir_binop_interpolate_at_sample
:
2284 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2288 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2291 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2294 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2297 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2300 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2303 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2305 case ir_unop_unpack_double_2x32
:
2306 case ir_unop_pack_double_2x32
:
2307 case ir_unop_unpack_int_2x32
:
2308 case ir_unop_pack_int_2x32
:
2309 case ir_unop_unpack_uint_2x32
:
2310 case ir_unop_pack_uint_2x32
:
2311 case ir_unop_unpack_sampler_2x32
:
2312 case ir_unop_pack_sampler_2x32
:
2313 case ir_unop_unpack_image_2x32
:
2314 case ir_unop_pack_image_2x32
:
2315 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2318 case ir_binop_ldexp
:
2319 if (ir
->operands
[0]->type
->is_double()) {
2320 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2322 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2326 case ir_unop_pack_half_2x16
:
2327 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2329 case ir_unop_unpack_half_2x16
:
2330 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2333 case ir_unop_get_buffer_size
: {
2334 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2337 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2338 (const_offset
? const_offset
->value
.u
[0] : 0),
2340 if (!const_offset
) {
2341 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2342 *buffer
.reladdr
= op
[0];
2343 emit_arl(ir
, sampler_reladdr
, op
[0]);
2345 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2351 case ir_unop_b2i64
: {
2352 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2353 st_dst_reg temp_dst
= st_dst_reg(temp
);
2354 unsigned orig_swz
= op
[0].swizzle
;
2356 * To convert unsigned to 64-bit:
2357 * zero Y channel, copy X channel.
2359 temp_dst
.writemask
= WRITEMASK_Y
;
2360 if (vector_elements
> 1)
2361 temp_dst
.writemask
|= WRITEMASK_W
;
2362 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2363 temp_dst
.writemask
= WRITEMASK_X
;
2364 if (vector_elements
> 1)
2365 temp_dst
.writemask
|= WRITEMASK_Z
;
2366 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2367 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2368 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2369 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2371 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2373 result_src
.type
= GLSL_TYPE_UINT64
;
2374 if (vector_elements
> 2) {
2375 /* Subtle: We rely on the fact that get_temp here returns the next
2376 * TGSI temporary register directly after the temp register used for
2377 * the first two components, so that the result gets picked up
2380 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2381 st_dst_reg temp_dst
= st_dst_reg(temp
);
2382 temp_dst
.writemask
= WRITEMASK_Y
;
2383 if (vector_elements
> 3)
2384 temp_dst
.writemask
|= WRITEMASK_W
;
2385 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2387 temp_dst
.writemask
= WRITEMASK_X
;
2388 if (vector_elements
> 3)
2389 temp_dst
.writemask
|= WRITEMASK_Z
;
2390 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2391 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2392 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2393 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2395 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2402 case ir_unop_i642u
: {
2403 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2404 st_dst_reg temp_dst
= st_dst_reg(temp
);
2405 unsigned orig_swz
= op
[0].swizzle
;
2406 unsigned orig_idx
= op
[0].index
;
2408 temp_dst
.writemask
= WRITEMASK_X
;
2410 for (el
= 0; el
< vector_elements
; el
++) {
2411 unsigned swz
= GET_SWZ(orig_swz
, el
);
2413 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2415 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2417 op
[0].index
= orig_idx
+ 1;
2418 op
[0].type
= GLSL_TYPE_UINT
;
2419 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2420 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2423 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2424 result_src
.type
= GLSL_TYPE_UINT
;
2426 result_src
.type
= GLSL_TYPE_INT
;
2430 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2433 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2436 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2439 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2442 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2445 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2448 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2451 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2454 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2457 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2460 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2462 /* these might be needed */
2463 case ir_unop_pack_snorm_2x16
:
2464 case ir_unop_pack_unorm_2x16
:
2465 case ir_unop_pack_snorm_4x8
:
2466 case ir_unop_pack_unorm_4x8
:
2468 case ir_unop_unpack_snorm_2x16
:
2469 case ir_unop_unpack_unorm_2x16
:
2470 case ir_unop_unpack_snorm_4x8
:
2471 case ir_unop_unpack_unorm_4x8
:
2473 case ir_quadop_vector
:
2474 case ir_binop_vector_extract
:
2475 case ir_triop_vector_insert
:
2476 case ir_binop_carry
:
2477 case ir_binop_borrow
:
2478 case ir_unop_ssbo_unsized_array_length
:
2479 /* This operation is not supported, or should have already been handled.
2481 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2485 this->result
= result_src
;
2490 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2496 /* Note that this is only swizzles in expressions, not those on the left
2497 * hand side of an assignment, which do write masking. See ir_assignment
2501 ir
->val
->accept(this);
2503 assert(src
.file
!= PROGRAM_UNDEFINED
);
2504 assert(ir
->type
->vector_elements
> 0);
2506 for (i
= 0; i
< 4; i
++) {
2507 if (i
< ir
->type
->vector_elements
) {
2510 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2513 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2516 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2519 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2523 /* If the type is smaller than a vec4, replicate the last
2526 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2530 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2535 /* Test if the variable is an array. Note that geometry and
2536 * tessellation shader inputs are outputs are always arrays (except
2537 * for patch inputs), so only the array element type is considered.
2540 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2542 const glsl_type
*type
= var
->type
;
2544 *remove_array
= false;
2546 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2547 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2550 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2551 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2552 stage
== MESA_SHADER_TESS_CTRL
) &&
2554 if (!var
->type
->is_array())
2555 return false; /* a system value probably */
2557 type
= var
->type
->fields
.array
;
2558 *remove_array
= true;
2561 return type
->is_array() || type
->is_matrix();
2565 st_translate_interp_loc(ir_variable
*var
)
2567 if (var
->data
.centroid
)
2568 return TGSI_INTERPOLATE_LOC_CENTROID
;
2569 else if (var
->data
.sample
)
2570 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2572 return TGSI_INTERPOLATE_LOC_CENTER
;
2576 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2578 variable_storage
*entry
= find_variable_storage(ir
->var
);
2579 ir_variable
*var
= ir
->var
;
2583 switch (var
->data
.mode
) {
2584 case ir_var_uniform
:
2585 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2586 var
->data
.param_index
);
2587 _mesa_hash_table_insert(this->variables
, var
, entry
);
2589 case ir_var_shader_in
: {
2590 /* The linker assigns locations for varyings and attributes,
2591 * including deprecated builtins (like gl_Color), user-assign
2592 * generic attributes (glBindVertexLocation), and
2593 * user-defined varyings.
2595 assert(var
->data
.location
!= -1);
2597 const glsl_type
*type_without_array
= var
->type
->without_array();
2598 struct inout_decl
*decl
= &inputs
[num_inputs
];
2599 unsigned component
= var
->data
.location_frac
;
2600 unsigned num_components
;
2603 if (type_without_array
->is_64bit())
2604 component
= component
/ 2;
2605 if (type_without_array
->vector_elements
)
2606 num_components
= type_without_array
->vector_elements
;
2610 decl
->mesa_index
= var
->data
.location
;
2611 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2612 decl
->interp_loc
= st_translate_interp_loc(var
);
2613 decl
->base_type
= type_without_array
->base_type
;
2614 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2616 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2617 decl
->array_id
= num_input_arrays
+ 1;
2624 decl
->size
= type_size(var
->type
->fields
.array
);
2626 decl
->size
= type_size(var
->type
);
2628 entry
= new(mem_ctx
) variable_storage(var
,
2632 entry
->component
= component
;
2634 _mesa_hash_table_insert(this->variables
, var
, entry
);
2638 case ir_var_shader_out
: {
2639 assert(var
->data
.location
!= -1);
2641 const glsl_type
*type_without_array
= var
->type
->without_array();
2642 struct inout_decl
*decl
= &outputs
[num_outputs
];
2643 unsigned component
= var
->data
.location_frac
;
2644 unsigned num_components
;
2647 if (type_without_array
->is_64bit())
2648 component
= component
/ 2;
2649 if (type_without_array
->vector_elements
)
2650 num_components
= type_without_array
->vector_elements
;
2654 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2655 decl
->base_type
= type_without_array
->base_type
;
2656 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2657 if (var
->data
.stream
& (1u << 31)) {
2658 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2660 assert(var
->data
.stream
< 4);
2661 decl
->gs_out_streams
= 0;
2662 for (unsigned i
= 0; i
< num_components
; ++i
)
2663 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2666 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2667 decl
->array_id
= num_output_arrays
+ 1;
2668 num_output_arrays
++;
2674 decl
->size
= type_size(var
->type
->fields
.array
);
2676 decl
->size
= type_size(var
->type
);
2678 if (var
->data
.fb_fetch_output
) {
2679 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2680 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2681 var
->type
, component
, decl
->array_id
);
2682 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2683 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2686 entry
= new(mem_ctx
) variable_storage(var
,
2691 entry
->component
= component
;
2693 _mesa_hash_table_insert(this->variables
, var
, entry
);
2697 case ir_var_system_value
:
2698 entry
= new(mem_ctx
) variable_storage(var
,
2699 PROGRAM_SYSTEM_VALUE
,
2700 var
->data
.location
);
2703 case ir_var_temporary
:
2704 st_src_reg src
= get_temp(var
->type
);
2706 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2708 _mesa_hash_table_insert(this->variables
, var
, entry
);
2714 printf("Failed to make storage for %s\n", var
->name
);
2719 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2720 entry
->component
, entry
->array_id
);
2721 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2722 this->result
.is_double_vertex_input
= true;
2723 if (!native_integers
)
2724 this->result
.type
= GLSL_TYPE_FLOAT
;
2728 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2729 GLbitfield64
* usage_mask
,
2730 GLbitfield64 double_usage_mask
,
2731 GLbitfield
* patch_usage_mask
)
2736 /* Fix array declarations by removing unused array elements at both ends
2737 * of the arrays. For example, mat4[3] where only mat[1] is used.
2739 for (i
= 0; i
< count
; i
++) {
2740 struct inout_decl
*decl
= &decls
[i
];
2741 if (!decl
->array_id
)
2744 /* Shrink the beginning. */
2745 for (j
= 0; j
< (int)decl
->size
; j
++) {
2746 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2747 if (*patch_usage_mask
&
2748 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2752 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2754 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2763 /* Shrink the end. */
2764 for (j
= decl
->size
-1; j
>= 0; j
--) {
2765 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2766 if (*patch_usage_mask
&
2767 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2771 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2773 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2780 /* When not all entries of an array are accessed, we mark them as used
2781 * here anyway, to ensure that the input/output mapping logic doesn't get
2784 * TODO This happens when an array isn't used via indirect access, which
2785 * some game ports do (at least eON-based). There is an optimization
2786 * opportunity here by replacing the array declaration with non-array
2787 * declarations of those slots that are actually used.
2789 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2790 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2791 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2793 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2799 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2804 ir_variable
*var
= ir
->variable_referenced();
2806 /* We only need the logic provided by st_glsl_storage_type_size()
2807 * for arrays of structs. Indirect sampler and image indexing is handled
2810 int element_size
= ir
->type
->without_array()->is_record() ?
2811 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2812 type_size(ir
->type
);
2814 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2816 ir
->array
->accept(this);
2819 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2820 switch (this->prog
->Target
) {
2821 case GL_TESS_CONTROL_PROGRAM_NV
:
2822 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2823 !ir
->variable_referenced()->data
.patch
;
2825 case GL_TESS_EVALUATION_PROGRAM_NV
:
2826 is_2D
= src
.file
== PROGRAM_INPUT
&&
2827 !ir
->variable_referenced()->data
.patch
;
2829 case GL_GEOMETRY_PROGRAM_NV
:
2830 is_2D
= src
.file
== PROGRAM_INPUT
;
2840 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2841 src
.file
== PROGRAM_INPUT
)
2842 element_size
= attrib_type_size(ir
->type
, true);
2844 src
.index2D
= index
->value
.i
[0];
2845 src
.has_index2
= true;
2847 src
.index
+= index
->value
.i
[0] * element_size
;
2849 /* Variable index array dereference. It eats the "vec4" of the
2850 * base of the array and an index that offsets the TGSI register
2853 ir
->array_index
->accept(this);
2855 st_src_reg index_reg
;
2857 if (element_size
== 1) {
2858 index_reg
= this->result
;
2860 index_reg
= get_temp(native_integers
?
2861 glsl_type::int_type
: glsl_type::float_type
);
2863 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2864 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2867 /* If there was already a relative address register involved, add the
2868 * new and the old together to get the new offset.
2870 if (!is_2D
&& src
.reladdr
!= NULL
) {
2871 st_src_reg accum_reg
= get_temp(native_integers
?
2872 glsl_type::int_type
: glsl_type::float_type
);
2874 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2875 index_reg
, *src
.reladdr
);
2877 index_reg
= accum_reg
;
2881 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2882 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2884 src
.has_index2
= true;
2886 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2887 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2891 /* Change the register type to the element type of the array. */
2892 src
.type
= ir
->type
->base_type
;
2898 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2901 const glsl_type
*struct_type
= ir
->record
->type
;
2902 ir_variable
*var
= ir
->record
->variable_referenced();
2905 ir
->record
->accept(this);
2907 assert(ir
->field_idx
>= 0);
2909 for (i
= 0; i
< struct_type
->length
; i
++) {
2910 if (i
== (unsigned) ir
->field_idx
)
2912 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2913 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2916 /* If the type is smaller than a vec4, replicate the last channel out. */
2917 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2918 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2920 this->result
.swizzle
= SWIZZLE_NOOP
;
2922 this->result
.index
+= offset
;
2923 this->result
.type
= ir
->type
->base_type
;
2927 * We want to be careful in assignment setup to hit the actual storage
2928 * instead of potentially using a temporary like we might with the
2929 * ir_dereference handler.
2932 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2934 /* The LHS must be a dereference. If the LHS is a variable indexed array
2935 * access of a vector, it must be separated into a series conditional moves
2936 * before reaching this point (see ir_vec_index_to_cond_assign).
2938 assert(ir
->as_dereference());
2939 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2941 assert(!deref_array
->array
->type
->is_vector());
2944 /* Use the rvalue deref handler for the most part. We write swizzles using
2945 * the writemask, but we do extract the base component for enhanced layouts
2946 * from the source swizzle.
2949 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2950 return st_dst_reg(v
->result
);
2954 * Process the condition of a conditional assignment
2956 * Examines the condition of a conditional assignment to generate the optimal
2957 * first operand of a \c CMP instruction. If the condition is a relational
2958 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2959 * used as the source for the \c CMP instruction. Otherwise the comparison
2960 * is processed to a boolean result, and the boolean result is used as the
2961 * operand to the CMP instruction.
2964 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2966 ir_rvalue
*src_ir
= ir
;
2968 bool switch_order
= false;
2970 ir_expression
*const expr
= ir
->as_expression();
2972 if (native_integers
) {
2973 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2974 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2975 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2976 type
== GLSL_TYPE_BOOL
) {
2977 if (expr
->operation
== ir_binop_equal
) {
2978 if (expr
->operands
[0]->is_zero()) {
2979 src_ir
= expr
->operands
[1];
2980 switch_order
= true;
2982 else if (expr
->operands
[1]->is_zero()) {
2983 src_ir
= expr
->operands
[0];
2984 switch_order
= true;
2987 else if (expr
->operation
== ir_binop_nequal
) {
2988 if (expr
->operands
[0]->is_zero()) {
2989 src_ir
= expr
->operands
[1];
2991 else if (expr
->operands
[1]->is_zero()) {
2992 src_ir
= expr
->operands
[0];
2998 src_ir
->accept(this);
2999 return switch_order
;
3002 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
3003 bool zero_on_left
= false;
3005 if (expr
->operands
[0]->is_zero()) {
3006 src_ir
= expr
->operands
[1];
3007 zero_on_left
= true;
3008 } else if (expr
->operands
[1]->is_zero()) {
3009 src_ir
= expr
->operands
[0];
3010 zero_on_left
= false;
3014 * (a < 0) T F F ( a < 0) T F F
3015 * (0 < a) F F T (-a < 0) F F T
3016 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3017 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3018 * (a > 0) F F T (-a < 0) F F T
3019 * (0 > a) T F F ( a < 0) T F F
3020 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3021 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3023 * Note that exchanging the order of 0 and 'a' in the comparison simply
3024 * means that the value of 'a' should be negated.
3027 switch (expr
->operation
) {
3029 switch_order
= false;
3030 negate
= zero_on_left
;
3033 case ir_binop_greater
:
3034 switch_order
= false;
3035 negate
= !zero_on_left
;
3038 case ir_binop_lequal
:
3039 switch_order
= true;
3040 negate
= !zero_on_left
;
3043 case ir_binop_gequal
:
3044 switch_order
= true;
3045 negate
= zero_on_left
;
3049 /* This isn't the right kind of comparison afterall, so make sure
3050 * the whole condition is visited.
3058 src_ir
->accept(this);
3060 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3061 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3062 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3063 * computing the condition.
3066 this->result
.negate
= ~this->result
.negate
;
3068 return switch_order
;
3072 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3073 st_dst_reg
*l
, st_src_reg
*r
,
3074 st_src_reg
*cond
, bool cond_swap
)
3076 if (type
->is_record()) {
3077 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3078 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3084 if (type
->is_array()) {
3085 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3086 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3091 if (type
->is_matrix()) {
3092 const struct glsl_type
*vec_type
;
3094 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3095 type
->vector_elements
, 1);
3097 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3098 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3103 assert(type
->is_scalar() || type
->is_vector());
3105 l
->type
= type
->base_type
;
3106 r
->type
= type
->base_type
;
3108 st_src_reg l_src
= st_src_reg(*l
);
3109 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3111 if (native_integers
) {
3112 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3113 cond_swap
? l_src
: *r
,
3114 cond_swap
? *r
: l_src
);
3116 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3117 cond_swap
? l_src
: *r
,
3118 cond_swap
? *r
: l_src
);
3121 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3125 if (type
->is_dual_slot()) {
3127 if (r
->is_double_vertex_input
== false)
3133 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3139 /* all generated instructions need to be flaged as precise */
3140 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3141 ir
->rhs
->accept(this);
3144 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3148 int first_enabled_chan
= 0;
3150 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3152 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3153 variable
->data
.mode
== ir_var_shader_out
&&
3154 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3155 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3156 assert(ir
->lhs
->type
->is_scalar());
3157 assert(ir
->write_mask
== WRITEMASK_X
);
3159 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3160 l
.writemask
= WRITEMASK_Z
;
3162 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3163 l
.writemask
= WRITEMASK_Y
;
3165 } else if (ir
->write_mask
== 0) {
3166 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3168 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3171 l
.writemask
= u_bit_consecutive(0, num_elements
);
3173 /* The type is a struct or an array of (array of) structs. */
3174 l
.writemask
= WRITEMASK_XYZW
;
3177 l
.writemask
= ir
->write_mask
;
3180 for (int i
= 0; i
< 4; i
++) {
3181 if (l
.writemask
& (1 << i
)) {
3182 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3187 l
.writemask
= l
.writemask
<< dst_component
;
3189 /* Swizzle a small RHS vector into the channels being written.
3191 * glsl ir treats write_mask as dictating how many channels are
3192 * present on the RHS while TGSI treats write_mask as just
3193 * showing which channels of the vec4 RHS get written.
3195 for (int i
= 0; i
< 4; i
++) {
3196 if (l
.writemask
& (1 << i
))
3197 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3199 swizzles
[i
] = first_enabled_chan
;
3201 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3202 swizzles
[2], swizzles
[3]);
3205 assert(l
.file
!= PROGRAM_UNDEFINED
);
3206 assert(r
.file
!= PROGRAM_UNDEFINED
);
3208 if (ir
->condition
) {
3209 const bool switch_order
= this->process_move_condition(ir
->condition
);
3210 st_src_reg condition
= this->result
;
3212 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3213 } else if (ir
->rhs
->as_expression() &&
3214 this->instructions
.get_tail() &&
3215 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3216 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3217 type_size(ir
->lhs
->type
) == 1 &&
3218 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3219 /* To avoid emitting an extra MOV when assigning an expression to a
3220 * variable, emit the last instruction of the expression again, but
3221 * replace the destination register with the target of the assignment.
3222 * Dead code elimination will remove the original instruction.
3224 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3225 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3226 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3227 new_inst
->saturate
= inst
->saturate
;
3228 inst
->dead_mask
= inst
->dst
[0].writemask
;
3230 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3237 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3240 GLdouble stack_vals
[4] = { 0 };
3241 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3242 GLenum gl_type
= GL_NONE
;
3244 static int in_array
= 0;
3245 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3247 /* Unfortunately, 4 floats is all we can get into
3248 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3249 * aggregate constant and move each constant value into it. If we
3250 * get lucky, copy propagation will eliminate the extra moves.
3252 if (ir
->type
->is_record()) {
3253 st_src_reg temp_base
= get_temp(ir
->type
);
3254 st_dst_reg temp
= st_dst_reg(temp_base
);
3256 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3257 int size
= type_size(field_value
->type
);
3261 field_value
->accept(this);
3264 for (i
= 0; i
< (unsigned int)size
; i
++) {
3265 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3271 this->result
= temp_base
;
3275 if (ir
->type
->is_array()) {
3276 st_src_reg temp_base
= get_temp(ir
->type
);
3277 st_dst_reg temp
= st_dst_reg(temp_base
);
3278 int size
= type_size(ir
->type
->fields
.array
);
3283 for (i
= 0; i
< ir
->type
->length
; i
++) {
3284 ir
->array_elements
[i
]->accept(this);
3286 for (int j
= 0; j
< size
; j
++) {
3287 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3293 this->result
= temp_base
;
3298 if (ir
->type
->is_matrix()) {
3299 st_src_reg mat
= get_temp(ir
->type
);
3300 st_dst_reg mat_column
= st_dst_reg(mat
);
3302 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3303 switch (ir
->type
->base_type
) {
3304 case GLSL_TYPE_FLOAT
:
3305 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3307 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3308 src
.index
= add_constant(file
,
3310 ir
->type
->vector_elements
,
3313 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3315 case GLSL_TYPE_DOUBLE
:
3316 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3317 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3318 src
.index
= add_constant(file
,
3320 ir
->type
->vector_elements
,
3323 if (ir
->type
->vector_elements
>= 2) {
3324 mat_column
.writemask
= WRITEMASK_XY
;
3325 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3326 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3328 mat_column
.writemask
= WRITEMASK_X
;
3329 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3330 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3333 if (ir
->type
->vector_elements
> 2) {
3334 if (ir
->type
->vector_elements
== 4) {
3335 mat_column
.writemask
= WRITEMASK_ZW
;
3336 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3337 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3339 mat_column
.writemask
= WRITEMASK_Z
;
3340 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3341 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3342 mat_column
.writemask
= WRITEMASK_XYZW
;
3343 src
.swizzle
= SWIZZLE_XYZW
;
3349 unreachable("Illegal matrix constant type.\n");
3358 switch (ir
->type
->base_type
) {
3359 case GLSL_TYPE_FLOAT
:
3361 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3362 values
[i
].f
= ir
->value
.f
[i
];
3365 case GLSL_TYPE_DOUBLE
:
3366 gl_type
= GL_DOUBLE
;
3367 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3368 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3371 case GLSL_TYPE_INT64
:
3372 gl_type
= GL_INT64_ARB
;
3373 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3374 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3377 case GLSL_TYPE_UINT64
:
3378 gl_type
= GL_UNSIGNED_INT64_ARB
;
3379 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3380 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3383 case GLSL_TYPE_UINT
:
3384 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3385 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3386 if (native_integers
)
3387 values
[i
].u
= ir
->value
.u
[i
];
3389 values
[i
].f
= ir
->value
.u
[i
];
3393 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3394 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3395 if (native_integers
)
3396 values
[i
].i
= ir
->value
.i
[i
];
3398 values
[i
].f
= ir
->value
.i
[i
];
3401 case GLSL_TYPE_BOOL
:
3402 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3403 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3404 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3408 assert(!"Non-float/uint/int/bool constant");
3411 this->result
= st_src_reg(file
, -1, ir
->type
);
3412 this->result
.index
= add_constant(file
,
3414 ir
->type
->vector_elements
,
3416 &this->result
.swizzle
);
3420 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3422 exec_node
*param
= ir
->actual_parameters
.get_head();
3423 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3424 ir_variable
*location
= deref
->variable_referenced();
3427 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3429 /* Calculate the surface offset */
3431 unsigned array_size
= 0, base
= 0;
3434 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3436 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3437 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3438 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3439 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3440 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3442 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3445 ir
->return_deref
->accept(this);
3446 st_dst_reg
dst(this->result
);
3447 dst
.writemask
= WRITEMASK_X
;
3449 glsl_to_tgsi_instruction
*inst
;
3451 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3452 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3453 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3454 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3455 st_src_reg_for_int(1));
3456 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3457 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3458 st_src_reg_for_int(-1));
3459 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3461 param
= param
->get_next();
3462 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3465 st_src_reg data
= this->result
, data2
= undef_src
;
3467 switch (ir
->callee
->intrinsic_id
) {
3468 case ir_intrinsic_atomic_counter_add
:
3469 opcode
= TGSI_OPCODE_ATOMUADD
;
3471 case ir_intrinsic_atomic_counter_min
:
3472 opcode
= TGSI_OPCODE_ATOMIMIN
;
3474 case ir_intrinsic_atomic_counter_max
:
3475 opcode
= TGSI_OPCODE_ATOMIMAX
;
3477 case ir_intrinsic_atomic_counter_and
:
3478 opcode
= TGSI_OPCODE_ATOMAND
;
3480 case ir_intrinsic_atomic_counter_or
:
3481 opcode
= TGSI_OPCODE_ATOMOR
;
3483 case ir_intrinsic_atomic_counter_xor
:
3484 opcode
= TGSI_OPCODE_ATOMXOR
;
3486 case ir_intrinsic_atomic_counter_exchange
:
3487 opcode
= TGSI_OPCODE_ATOMXCHG
;
3489 case ir_intrinsic_atomic_counter_comp_swap
: {
3490 opcode
= TGSI_OPCODE_ATOMCAS
;
3491 param
= param
->get_next();
3492 val
= ((ir_instruction
*)param
)->as_rvalue();
3494 data2
= this->result
;
3498 assert(!"Unexpected intrinsic");
3502 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3505 inst
->resource
= buffer
;
3509 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3511 exec_node
*param
= ir
->actual_parameters
.get_head();
3513 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3515 param
= param
->get_next();
3516 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3518 ir_constant
*const_block
= block
->as_constant();
3522 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3523 (const_block
? const_block
->value
.u
[0] : 0),
3527 block
->accept(this);
3528 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3529 *buffer
.reladdr
= this->result
;
3530 emit_arl(ir
, sampler_reladdr
, this->result
);
3533 /* Calculate the surface offset */
3534 offset
->accept(this);
3535 st_src_reg off
= this->result
;
3537 st_dst_reg dst
= undef_dst
;
3538 if (ir
->return_deref
) {
3539 ir
->return_deref
->accept(this);
3540 dst
= st_dst_reg(this->result
);
3541 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3544 glsl_to_tgsi_instruction
*inst
;
3546 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3547 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3548 if (dst
.type
== GLSL_TYPE_BOOL
)
3549 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3550 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3551 param
= param
->get_next();
3552 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3555 param
= param
->get_next();
3556 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3558 dst
.writemask
= write_mask
->value
.u
[0];
3560 dst
.type
= this->result
.type
;
3561 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3563 param
= param
->get_next();
3564 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3567 st_src_reg data
= this->result
, data2
= undef_src
;
3569 switch (ir
->callee
->intrinsic_id
) {
3570 case ir_intrinsic_ssbo_atomic_add
:
3571 opcode
= TGSI_OPCODE_ATOMUADD
;
3573 case ir_intrinsic_ssbo_atomic_min
:
3574 opcode
= TGSI_OPCODE_ATOMIMIN
;
3576 case ir_intrinsic_ssbo_atomic_max
:
3577 opcode
= TGSI_OPCODE_ATOMIMAX
;
3579 case ir_intrinsic_ssbo_atomic_and
:
3580 opcode
= TGSI_OPCODE_ATOMAND
;
3582 case ir_intrinsic_ssbo_atomic_or
:
3583 opcode
= TGSI_OPCODE_ATOMOR
;
3585 case ir_intrinsic_ssbo_atomic_xor
:
3586 opcode
= TGSI_OPCODE_ATOMXOR
;
3588 case ir_intrinsic_ssbo_atomic_exchange
:
3589 opcode
= TGSI_OPCODE_ATOMXCHG
;
3591 case ir_intrinsic_ssbo_atomic_comp_swap
:
3592 opcode
= TGSI_OPCODE_ATOMCAS
;
3593 param
= param
->get_next();
3594 val
= ((ir_instruction
*)param
)->as_rvalue();
3596 data2
= this->result
;
3599 assert(!"Unexpected intrinsic");
3603 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3606 param
= param
->get_next();
3607 ir_constant
*access
= NULL
;
3608 if (!param
->is_tail_sentinel()) {
3609 access
= ((ir_instruction
*)param
)->as_constant();
3613 /* The emit_asm() might have actually split the op into pieces, e.g. for
3614 * double stores. We have to go back and fix up all the generated ops.
3616 unsigned op
= inst
->op
;
3618 inst
->resource
= buffer
;
3620 inst
->buffer_access
= access
->value
.u
[0];
3622 if (inst
== this->instructions
.get_head_raw())
3624 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3626 if (inst
->op
== TGSI_OPCODE_UADD
) {
3627 if (inst
== this->instructions
.get_head_raw())
3629 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3631 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3635 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3637 switch (ir
->callee
->intrinsic_id
) {
3638 case ir_intrinsic_memory_barrier
:
3639 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3640 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3641 TGSI_MEMBAR_ATOMIC_BUFFER
|
3642 TGSI_MEMBAR_SHADER_IMAGE
|
3643 TGSI_MEMBAR_SHARED
));
3645 case ir_intrinsic_memory_barrier_atomic_counter
:
3646 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3647 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3649 case ir_intrinsic_memory_barrier_buffer
:
3650 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3651 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3653 case ir_intrinsic_memory_barrier_image
:
3654 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3655 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3657 case ir_intrinsic_memory_barrier_shared
:
3658 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3659 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3661 case ir_intrinsic_group_memory_barrier
:
3662 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3663 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3664 TGSI_MEMBAR_ATOMIC_BUFFER
|
3665 TGSI_MEMBAR_SHADER_IMAGE
|
3666 TGSI_MEMBAR_SHARED
|
3667 TGSI_MEMBAR_THREAD_GROUP
));
3670 assert(!"Unexpected memory barrier intrinsic");
3675 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3677 exec_node
*param
= ir
->actual_parameters
.get_head();
3679 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3681 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3683 /* Calculate the surface offset */
3684 offset
->accept(this);
3685 st_src_reg off
= this->result
;
3687 st_dst_reg dst
= undef_dst
;
3688 if (ir
->return_deref
) {
3689 ir
->return_deref
->accept(this);
3690 dst
= st_dst_reg(this->result
);
3691 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3694 glsl_to_tgsi_instruction
*inst
;
3696 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3697 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3698 inst
->resource
= buffer
;
3699 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3700 param
= param
->get_next();
3701 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3704 param
= param
->get_next();
3705 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3707 dst
.writemask
= write_mask
->value
.u
[0];
3709 dst
.type
= this->result
.type
;
3710 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3711 inst
->resource
= buffer
;
3713 param
= param
->get_next();
3714 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3717 st_src_reg data
= this->result
, data2
= undef_src
;
3719 switch (ir
->callee
->intrinsic_id
) {
3720 case ir_intrinsic_shared_atomic_add
:
3721 opcode
= TGSI_OPCODE_ATOMUADD
;
3723 case ir_intrinsic_shared_atomic_min
:
3724 opcode
= TGSI_OPCODE_ATOMIMIN
;
3726 case ir_intrinsic_shared_atomic_max
:
3727 opcode
= TGSI_OPCODE_ATOMIMAX
;
3729 case ir_intrinsic_shared_atomic_and
:
3730 opcode
= TGSI_OPCODE_ATOMAND
;
3732 case ir_intrinsic_shared_atomic_or
:
3733 opcode
= TGSI_OPCODE_ATOMOR
;
3735 case ir_intrinsic_shared_atomic_xor
:
3736 opcode
= TGSI_OPCODE_ATOMXOR
;
3738 case ir_intrinsic_shared_atomic_exchange
:
3739 opcode
= TGSI_OPCODE_ATOMXCHG
;
3741 case ir_intrinsic_shared_atomic_comp_swap
:
3742 opcode
= TGSI_OPCODE_ATOMCAS
;
3743 param
= param
->get_next();
3744 val
= ((ir_instruction
*)param
)->as_rvalue();
3746 data2
= this->result
;
3749 assert(!"Unexpected intrinsic");
3753 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3754 inst
->resource
= buffer
;
3759 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3760 bool *memory_coherent
, bool *memory_volatile
,
3761 bool *memory_restrict
, unsigned *image_format
)
3764 switch (ir
->ir_type
) {
3765 case ir_type_dereference_record
: {
3766 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3767 const glsl_type
*struct_type
= deref_record
->record
->type
;
3768 int fild_idx
= deref_record
->field_idx
;
3770 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3772 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3774 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3776 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3778 struct_type
->fields
.structure
[fild_idx
].image_format
;
3782 case ir_type_dereference_array
: {
3783 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3784 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3785 memory_coherent
, memory_volatile
, memory_restrict
,
3790 case ir_type_dereference_variable
: {
3791 ir_variable
*var
= ir
->variable_referenced();
3793 *type
= var
->type
->without_array();
3794 *memory_coherent
= var
->data
.memory_coherent
;
3795 *memory_volatile
= var
->data
.memory_volatile
;
3796 *memory_restrict
= var
->data
.memory_restrict
;
3797 *image_format
= var
->data
.image_format
;
3807 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3809 exec_node
*param
= ir
->actual_parameters
.get_head();
3811 ir_dereference
*img
= (ir_dereference
*)param
;
3812 const ir_variable
*imgvar
= img
->variable_referenced();
3813 unsigned sampler_array_size
= 1, sampler_base
= 0;
3814 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3815 unsigned image_format
= 0;
3816 const glsl_type
*type
= NULL
;
3818 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3819 &memory_restrict
, &image_format
);
3822 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3824 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3825 &index
, &reladdr
, !imgvar
->contains_bindless());
3827 image
.index
= index
;
3828 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3829 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3830 *image
.reladdr
= reladdr
;
3831 emit_arl(ir
, sampler_reladdr
, reladdr
);
3834 st_dst_reg dst
= undef_dst
;
3835 if (ir
->return_deref
) {
3836 ir
->return_deref
->accept(this);
3837 dst
= st_dst_reg(this->result
);
3838 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3841 glsl_to_tgsi_instruction
*inst
;
3843 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3844 dst
.writemask
= WRITEMASK_XYZ
;
3845 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3846 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3847 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3848 st_dst_reg dstres
= st_dst_reg(res
);
3849 dstres
.writemask
= WRITEMASK_W
;
3850 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3851 res
.swizzle
= SWIZZLE_WWWW
;
3852 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3854 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3856 st_dst_reg coord_dst
;
3857 coord
= get_temp(glsl_type::ivec4_type
);
3858 coord_dst
= st_dst_reg(coord
);
3859 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3860 param
= param
->get_next();
3861 ((ir_dereference
*)param
)->accept(this);
3862 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3863 coord
.swizzle
= SWIZZLE_XXXX
;
3864 switch (type
->coordinate_components()) {
3865 case 4: assert(!"unexpected coord count");
3867 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3869 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3872 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3873 param
= param
->get_next();
3874 ((ir_dereference
*)param
)->accept(this);
3875 st_src_reg sample
= this->result
;
3876 sample
.swizzle
= SWIZZLE_XXXX
;
3877 coord_dst
.writemask
= WRITEMASK_W
;
3878 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3879 coord
.swizzle
|= SWIZZLE_W
<< 9;
3882 param
= param
->get_next();
3883 if (!param
->is_tail_sentinel()) {
3884 ((ir_dereference
*)param
)->accept(this);
3885 arg1
= this->result
;
3886 param
= param
->get_next();
3889 if (!param
->is_tail_sentinel()) {
3890 ((ir_dereference
*)param
)->accept(this);
3891 arg2
= this->result
;
3892 param
= param
->get_next();
3895 assert(param
->is_tail_sentinel());
3898 switch (ir
->callee
->intrinsic_id
) {
3899 case ir_intrinsic_image_load
:
3900 opcode
= TGSI_OPCODE_LOAD
;
3902 case ir_intrinsic_image_store
:
3903 opcode
= TGSI_OPCODE_STORE
;
3905 case ir_intrinsic_image_atomic_add
:
3906 opcode
= TGSI_OPCODE_ATOMUADD
;
3908 case ir_intrinsic_image_atomic_min
:
3909 opcode
= TGSI_OPCODE_ATOMIMIN
;
3911 case ir_intrinsic_image_atomic_max
:
3912 opcode
= TGSI_OPCODE_ATOMIMAX
;
3914 case ir_intrinsic_image_atomic_and
:
3915 opcode
= TGSI_OPCODE_ATOMAND
;
3917 case ir_intrinsic_image_atomic_or
:
3918 opcode
= TGSI_OPCODE_ATOMOR
;
3920 case ir_intrinsic_image_atomic_xor
:
3921 opcode
= TGSI_OPCODE_ATOMXOR
;
3923 case ir_intrinsic_image_atomic_exchange
:
3924 opcode
= TGSI_OPCODE_ATOMXCHG
;
3926 case ir_intrinsic_image_atomic_comp_swap
:
3927 opcode
= TGSI_OPCODE_ATOMCAS
;
3930 assert(!"Unexpected intrinsic");
3934 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3935 if (opcode
== TGSI_OPCODE_STORE
)
3936 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3939 if (imgvar
->contains_bindless()) {
3941 inst
->resource
= this->result
;
3942 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3943 SWIZZLE_X
, SWIZZLE_Y
);
3945 inst
->resource
= image
;
3946 inst
->sampler_array_size
= sampler_array_size
;
3947 inst
->sampler_base
= sampler_base
;
3950 inst
->tex_target
= type
->sampler_index();
3951 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3952 _mesa_get_shader_image_format(image_format
));
3954 if (memory_coherent
)
3955 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3956 if (memory_restrict
)
3957 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3958 if (memory_volatile
)
3959 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3963 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3965 ir
->return_deref
->accept(this);
3966 st_dst_reg dst
= st_dst_reg(this->result
);
3968 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3970 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3971 unsigned num_src
= 0;
3972 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3973 assert(num_src
< ARRAY_SIZE(src
));
3975 this->result
.file
= PROGRAM_UNDEFINED
;
3976 param
->accept(this);
3977 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3979 src
[num_src
] = this->result
;
3983 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3987 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3989 ir_function_signature
*sig
= ir
->callee
;
3991 /* Filter out intrinsics */
3992 switch (sig
->intrinsic_id
) {
3993 case ir_intrinsic_atomic_counter_read
:
3994 case ir_intrinsic_atomic_counter_increment
:
3995 case ir_intrinsic_atomic_counter_predecrement
:
3996 case ir_intrinsic_atomic_counter_add
:
3997 case ir_intrinsic_atomic_counter_min
:
3998 case ir_intrinsic_atomic_counter_max
:
3999 case ir_intrinsic_atomic_counter_and
:
4000 case ir_intrinsic_atomic_counter_or
:
4001 case ir_intrinsic_atomic_counter_xor
:
4002 case ir_intrinsic_atomic_counter_exchange
:
4003 case ir_intrinsic_atomic_counter_comp_swap
:
4004 visit_atomic_counter_intrinsic(ir
);
4007 case ir_intrinsic_ssbo_load
:
4008 case ir_intrinsic_ssbo_store
:
4009 case ir_intrinsic_ssbo_atomic_add
:
4010 case ir_intrinsic_ssbo_atomic_min
:
4011 case ir_intrinsic_ssbo_atomic_max
:
4012 case ir_intrinsic_ssbo_atomic_and
:
4013 case ir_intrinsic_ssbo_atomic_or
:
4014 case ir_intrinsic_ssbo_atomic_xor
:
4015 case ir_intrinsic_ssbo_atomic_exchange
:
4016 case ir_intrinsic_ssbo_atomic_comp_swap
:
4017 visit_ssbo_intrinsic(ir
);
4020 case ir_intrinsic_memory_barrier
:
4021 case ir_intrinsic_memory_barrier_atomic_counter
:
4022 case ir_intrinsic_memory_barrier_buffer
:
4023 case ir_intrinsic_memory_barrier_image
:
4024 case ir_intrinsic_memory_barrier_shared
:
4025 case ir_intrinsic_group_memory_barrier
:
4026 visit_membar_intrinsic(ir
);
4029 case ir_intrinsic_shared_load
:
4030 case ir_intrinsic_shared_store
:
4031 case ir_intrinsic_shared_atomic_add
:
4032 case ir_intrinsic_shared_atomic_min
:
4033 case ir_intrinsic_shared_atomic_max
:
4034 case ir_intrinsic_shared_atomic_and
:
4035 case ir_intrinsic_shared_atomic_or
:
4036 case ir_intrinsic_shared_atomic_xor
:
4037 case ir_intrinsic_shared_atomic_exchange
:
4038 case ir_intrinsic_shared_atomic_comp_swap
:
4039 visit_shared_intrinsic(ir
);
4042 case ir_intrinsic_image_load
:
4043 case ir_intrinsic_image_store
:
4044 case ir_intrinsic_image_atomic_add
:
4045 case ir_intrinsic_image_atomic_min
:
4046 case ir_intrinsic_image_atomic_max
:
4047 case ir_intrinsic_image_atomic_and
:
4048 case ir_intrinsic_image_atomic_or
:
4049 case ir_intrinsic_image_atomic_xor
:
4050 case ir_intrinsic_image_atomic_exchange
:
4051 case ir_intrinsic_image_atomic_comp_swap
:
4052 case ir_intrinsic_image_size
:
4053 case ir_intrinsic_image_samples
:
4054 visit_image_intrinsic(ir
);
4057 case ir_intrinsic_shader_clock
:
4058 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4061 case ir_intrinsic_vote_all
:
4062 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4064 case ir_intrinsic_vote_any
:
4065 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4067 case ir_intrinsic_vote_eq
:
4068 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4070 case ir_intrinsic_ballot
:
4071 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4073 case ir_intrinsic_read_first_invocation
:
4074 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4076 case ir_intrinsic_read_invocation
:
4077 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4080 case ir_intrinsic_invalid
:
4081 case ir_intrinsic_generic_load
:
4082 case ir_intrinsic_generic_store
:
4083 case ir_intrinsic_generic_atomic_add
:
4084 case ir_intrinsic_generic_atomic_and
:
4085 case ir_intrinsic_generic_atomic_or
:
4086 case ir_intrinsic_generic_atomic_xor
:
4087 case ir_intrinsic_generic_atomic_min
:
4088 case ir_intrinsic_generic_atomic_max
:
4089 case ir_intrinsic_generic_atomic_exchange
:
4090 case ir_intrinsic_generic_atomic_comp_swap
:
4091 unreachable("Invalid intrinsic");
4096 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4097 unsigned *array_elements
,
4099 st_src_reg
*indirect
,
4102 switch (tail
->ir_type
) {
4103 case ir_type_dereference_record
: {
4104 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4105 const glsl_type
*struct_type
= deref_record
->record
->type
;
4106 int field_index
= deref_record
->field_idx
;
4108 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4110 assert(field_index
>= 0);
4111 *location
+= struct_type
->record_location_offset(field_index
);
4115 case ir_type_dereference_array
: {
4116 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4118 void *mem_ctx
= ralloc_parent(deref_arr
);
4119 ir_constant
*array_index
=
4120 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4123 st_src_reg temp_reg
;
4124 st_dst_reg temp_dst
;
4126 temp_reg
= get_temp(glsl_type::uint_type
);
4127 temp_dst
= st_dst_reg(temp_reg
);
4128 temp_dst
.writemask
= 1;
4130 deref_arr
->array_index
->accept(this);
4131 if (*array_elements
!= 1)
4132 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4134 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4136 if (indirect
->file
== PROGRAM_UNDEFINED
)
4137 *indirect
= temp_reg
;
4139 temp_dst
= st_dst_reg(*indirect
);
4140 temp_dst
.writemask
= 1;
4141 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4144 *index
+= array_index
->value
.u
[0] * *array_elements
;
4146 *array_elements
*= deref_arr
->array
->type
->length
;
4148 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4157 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4158 unsigned *array_size
,
4161 st_src_reg
*reladdr
,
4164 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4165 unsigned location
= 0;
4166 ir_variable
*var
= ir
->variable_referenced();
4168 memset(reladdr
, 0, sizeof(*reladdr
));
4169 reladdr
->file
= PROGRAM_UNDEFINED
;
4175 location
= var
->data
.location
;
4176 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4179 * If we end up with no indirect then adjust the base to the index,
4180 * and set the array size to 1.
4182 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4188 assert(location
!= 0xffffffff);
4189 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4190 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4195 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4197 if (offset
.reladdr
|| offset
.reladdr2
) {
4198 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4199 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4200 tmp_dst
.writemask
= WRITEMASK_XY
;
4201 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4209 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4211 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4212 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4213 st_src_reg levels_src
, reladdr
;
4214 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4215 glsl_to_tgsi_instruction
*inst
= NULL
;
4216 unsigned opcode
= TGSI_OPCODE_NOP
;
4217 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4218 unsigned sampler_array_size
= 1, sampler_base
= 0;
4219 bool is_cube_array
= false, is_cube_shadow
= false;
4220 ir_variable
*var
= ir
->sampler
->variable_referenced();
4223 /* if we are a cube array sampler or a cube shadow */
4224 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4225 is_cube_array
= sampler_type
->sampler_array
;
4226 is_cube_shadow
= sampler_type
->sampler_shadow
;
4229 if (ir
->coordinate
) {
4230 ir
->coordinate
->accept(this);
4232 /* Put our coords in a temp. We'll need to modify them for shadow,
4233 * projection, or LOD, so the only case we'd use it as-is is if
4234 * we're doing plain old texturing. The optimization passes on
4235 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4237 coord
= get_temp(glsl_type::vec4_type
);
4238 coord_dst
= st_dst_reg(coord
);
4239 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4240 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4243 if (ir
->projector
) {
4244 ir
->projector
->accept(this);
4245 projector
= this->result
;
4248 /* Storage for our result. Ideally for an assignment we'd be using
4249 * the actual storage for the result here, instead.
4251 result_src
= get_temp(ir
->type
);
4252 result_dst
= st_dst_reg(result_src
);
4253 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4257 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4259 ir
->offset
->accept(this);
4260 offset
[0] = this->result
;
4264 if (is_cube_array
|| is_cube_shadow
) {
4265 opcode
= TGSI_OPCODE_TXB2
;
4268 opcode
= TGSI_OPCODE_TXB
;
4270 ir
->lod_info
.bias
->accept(this);
4271 lod_info
= this->result
;
4273 ir
->offset
->accept(this);
4274 offset
[0] = this->result
;
4278 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4279 opcode
= TGSI_OPCODE_TEX_LZ
;
4281 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4282 ir
->lod_info
.lod
->accept(this);
4283 lod_info
= this->result
;
4286 ir
->offset
->accept(this);
4287 offset
[0] = this->result
;
4291 opcode
= TGSI_OPCODE_TXD
;
4292 ir
->lod_info
.grad
.dPdx
->accept(this);
4294 ir
->lod_info
.grad
.dPdy
->accept(this);
4297 ir
->offset
->accept(this);
4298 offset
[0] = this->result
;
4302 opcode
= TGSI_OPCODE_TXQ
;
4303 ir
->lod_info
.lod
->accept(this);
4304 lod_info
= this->result
;
4306 case ir_query_levels
:
4307 opcode
= TGSI_OPCODE_TXQ
;
4308 lod_info
= undef_src
;
4309 levels_src
= get_temp(ir
->type
);
4312 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4313 opcode
= TGSI_OPCODE_TXF_LZ
;
4315 opcode
= TGSI_OPCODE_TXF
;
4316 ir
->lod_info
.lod
->accept(this);
4317 lod_info
= this->result
;
4320 ir
->offset
->accept(this);
4321 offset
[0] = this->result
;
4325 opcode
= TGSI_OPCODE_TXF
;
4326 ir
->lod_info
.sample_index
->accept(this);
4327 sample_index
= this->result
;
4330 opcode
= TGSI_OPCODE_TG4
;
4331 ir
->lod_info
.component
->accept(this);
4332 component
= this->result
;
4334 ir
->offset
->accept(this);
4335 if (ir
->offset
->type
->is_array()) {
4336 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4337 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4338 offset
[i
] = this->result
;
4339 offset
[i
].index
+= i
* type_size(elt_type
);
4340 offset
[i
].type
= elt_type
->base_type
;
4341 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4342 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4345 offset
[0] = canonicalize_gather_offset(this->result
);
4350 opcode
= TGSI_OPCODE_LODQ
;
4352 case ir_texture_samples
:
4353 opcode
= TGSI_OPCODE_TXQS
;
4355 case ir_samples_identical
:
4356 unreachable("Unexpected ir_samples_identical opcode");
4359 if (ir
->projector
) {
4360 if (opcode
== TGSI_OPCODE_TEX
) {
4361 /* Slot the projector in as the last component of the coord. */
4362 coord_dst
.writemask
= WRITEMASK_W
;
4363 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4364 coord_dst
.writemask
= WRITEMASK_XYZW
;
4365 opcode
= TGSI_OPCODE_TXP
;
4367 st_src_reg coord_w
= coord
;
4368 coord_w
.swizzle
= SWIZZLE_WWWW
;
4370 /* For the other TEX opcodes there's no projective version
4371 * since the last slot is taken up by LOD info. Do the
4372 * projective divide now.
4374 coord_dst
.writemask
= WRITEMASK_W
;
4375 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4377 /* In the case where we have to project the coordinates "by hand,"
4378 * the shadow comparator value must also be projected.
4380 st_src_reg tmp_src
= coord
;
4381 if (ir
->shadow_comparator
) {
4382 /* Slot the shadow value in as the second to last component of the
4385 ir
->shadow_comparator
->accept(this);
4387 tmp_src
= get_temp(glsl_type::vec4_type
);
4388 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4390 /* Projective division not allowed for array samplers. */
4391 assert(!sampler_type
->sampler_array
);
4393 tmp_dst
.writemask
= WRITEMASK_Z
;
4394 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4396 tmp_dst
.writemask
= WRITEMASK_XY
;
4397 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4400 coord_dst
.writemask
= WRITEMASK_XYZ
;
4401 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4403 coord_dst
.writemask
= WRITEMASK_XYZW
;
4404 coord
.swizzle
= SWIZZLE_XYZW
;
4408 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4409 * comparator was put in the correct place (and projected) by the code,
4410 * above, that handles by-hand projection.
4412 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4413 /* Slot the shadow value in as the second to last component of the
4416 ir
->shadow_comparator
->accept(this);
4418 if (is_cube_array
) {
4419 cube_sc
= get_temp(glsl_type::float_type
);
4420 cube_sc_dst
= st_dst_reg(cube_sc
);
4421 cube_sc_dst
.writemask
= WRITEMASK_X
;
4422 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4423 cube_sc_dst
.writemask
= WRITEMASK_X
;
4426 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4427 sampler_type
->sampler_array
) ||
4428 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4429 coord_dst
.writemask
= WRITEMASK_W
;
4431 coord_dst
.writemask
= WRITEMASK_Z
;
4433 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4434 coord_dst
.writemask
= WRITEMASK_XYZW
;
4438 if (ir
->op
== ir_txf_ms
) {
4439 coord_dst
.writemask
= WRITEMASK_W
;
4440 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4441 coord_dst
.writemask
= WRITEMASK_XYZW
;
4442 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4443 opcode
== TGSI_OPCODE_TXF
) {
4444 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4445 coord_dst
.writemask
= WRITEMASK_W
;
4446 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4447 coord_dst
.writemask
= WRITEMASK_XYZW
;
4450 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4453 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4454 &index
, &reladdr
, !var
->contains_bindless());
4456 sampler
.index
= index
;
4457 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4458 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4459 *sampler
.reladdr
= reladdr
;
4460 emit_arl(ir
, sampler_reladdr
, reladdr
);
4463 if (opcode
== TGSI_OPCODE_TXD
)
4464 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4465 else if (opcode
== TGSI_OPCODE_TXQ
) {
4466 if (ir
->op
== ir_query_levels
) {
4467 /* the level is stored in W */
4468 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4469 result_dst
.writemask
= WRITEMASK_X
;
4470 levels_src
.swizzle
= SWIZZLE_WWWW
;
4471 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4473 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4474 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4475 inst
= emit_asm(ir
, opcode
, result_dst
);
4476 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4477 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4478 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4479 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4480 } else if (opcode
== TGSI_OPCODE_TG4
) {
4481 if (is_cube_array
&& ir
->shadow_comparator
) {
4482 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4484 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4487 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4489 if (ir
->shadow_comparator
)
4490 inst
->tex_shadow
= GL_TRUE
;
4492 if (var
->contains_bindless()) {
4493 ir
->sampler
->accept(this);
4494 inst
->resource
= this->result
;
4495 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4496 SWIZZLE_X
, SWIZZLE_Y
);
4498 inst
->resource
= sampler
;
4499 inst
->sampler_array_size
= sampler_array_size
;
4500 inst
->sampler_base
= sampler_base
;
4504 if (!inst
->tex_offsets
)
4505 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4507 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4508 inst
->tex_offsets
[i
] = offset
[i
];
4509 inst
->tex_offset_num_offset
= i
;
4512 inst
->tex_target
= sampler_type
->sampler_index();
4513 inst
->tex_type
= ir
->type
->base_type
;
4515 this->result
= result_src
;
4519 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4521 assert(!ir
->get_value());
4523 emit_asm(ir
, TGSI_OPCODE_RET
);
4527 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4529 if (ir
->condition
) {
4530 ir
->condition
->accept(this);
4531 st_src_reg condition
= this->result
;
4533 /* Convert the bool condition to a float so we can negate. */
4534 if (native_integers
) {
4535 st_src_reg temp
= get_temp(ir
->condition
->type
);
4536 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4537 condition
, st_src_reg_for_float(1.0));
4541 condition
.negate
= ~condition
.negate
;
4542 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4544 /* unconditional kil */
4545 emit_asm(ir
, TGSI_OPCODE_KILL
);
4550 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4553 glsl_to_tgsi_instruction
*if_inst
;
4555 ir
->condition
->accept(this);
4556 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4558 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4560 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4562 this->instructions
.push_tail(if_inst
);
4564 visit_exec_list(&ir
->then_instructions
, this);
4566 if (!ir
->else_instructions
.is_empty()) {
4567 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4568 visit_exec_list(&ir
->else_instructions
, this);
4571 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4576 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4578 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4580 ir
->stream
->accept(this);
4581 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4585 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4587 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4589 ir
->stream
->accept(this);
4590 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4594 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4596 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4597 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4599 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4602 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4604 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4606 result
.file
= PROGRAM_UNDEFINED
;
4613 num_input_arrays
= 0;
4614 num_output_arrays
= 0;
4616 num_address_regs
= 0;
4619 indirect_addr_consts
= false;
4620 wpos_transform_const
= -1;
4622 native_integers
= false;
4623 mem_ctx
= ralloc_context(NULL
);
4627 shader_program
= NULL
;
4632 use_shared_memory
= false;
4633 has_tex_txf_lz
= false;
4637 static void var_destroy(struct hash_entry
*entry
)
4639 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4644 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4646 _mesa_hash_table_destroy(variables
, var_destroy
);
4648 ralloc_free(mem_ctx
);
4651 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4658 * Count resources used by the given gpu program (number of texture
4662 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4664 v
->samplers_used
= 0;
4667 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4668 if (inst
->info
->is_tex
) {
4669 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4670 unsigned idx
= inst
->sampler_base
+ i
;
4671 v
->samplers_used
|= 1u << idx
;
4673 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4674 v
->sampler_types
[idx
] = inst
->tex_type
;
4675 v
->sampler_targets
[idx
] =
4676 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4678 if (inst
->tex_shadow
) {
4679 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4684 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4685 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4687 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4688 is_resource_instruction(inst
->op
) ||
4689 inst
->op
== TGSI_OPCODE_STORE
)) {
4690 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4691 v
->use_shared_memory
= true;
4692 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4693 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4694 unsigned idx
= inst
->sampler_base
+ i
;
4695 v
->images_used
|= 1 << idx
;
4696 v
->image_targets
[idx
] =
4697 st_translate_texture_target(inst
->tex_target
, false);
4698 v
->image_formats
[idx
] = inst
->image_format
;
4703 prog
->SamplersUsed
= v
->samplers_used
;
4705 if (v
->shader_program
!= NULL
)
4706 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4710 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4711 * are read from the given src in this instruction
4714 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4716 int read_mask
= 0, comp
;
4718 /* Now, given the src swizzle and the written channels, find which
4719 * components are actually read
4721 for (comp
= 0; comp
< 4; ++comp
) {
4722 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4724 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4725 read_mask
|= 1 << coord
;
4732 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4733 * instruction is the first instruction to write to register T0. There are
4734 * several lowering passes done in GLSL IR (e.g. branches and
4735 * relative addressing) that create a large number of conditional assignments
4736 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4738 * Here is why this conversion is safe:
4739 * CMP T0, T1 T2 T0 can be expanded to:
4745 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4746 * as the original program. If (T1 < 0.0) evaluates to false, executing
4747 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4748 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4749 * because any instruction that was going to read from T0 after this was going
4750 * to read a garbage value anyway.
4753 glsl_to_tgsi_visitor::simplify_cmp(void)
4755 int tempWritesSize
= 0;
4756 unsigned *tempWrites
= NULL
;
4757 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4759 memset(outputWrites
, 0, sizeof(outputWrites
));
4761 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4762 unsigned prevWriteMask
= 0;
4764 /* Give up if we encounter relative addressing or flow control. */
4765 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4766 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4767 inst
->info
->is_branch
||
4768 inst
->op
== TGSI_OPCODE_CONT
||
4769 inst
->op
== TGSI_OPCODE_END
||
4770 inst
->op
== TGSI_OPCODE_RET
) {
4774 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4775 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4776 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4777 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4778 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4779 if (inst
->dst
[0].index
>= tempWritesSize
) {
4780 const int inc
= 4096;
4782 tempWrites
= (unsigned*)
4784 (tempWritesSize
+ inc
) * sizeof(unsigned));
4788 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4789 tempWritesSize
+= inc
;
4792 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4793 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4797 /* For a CMP to be considered a conditional write, the destination
4798 * register and source register two must be the same. */
4799 if (inst
->op
== TGSI_OPCODE_CMP
4800 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4801 && inst
->src
[2].file
== inst
->dst
[0].file
4802 && inst
->src
[2].index
== inst
->dst
[0].index
4803 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4805 inst
->op
= TGSI_OPCODE_MOV
;
4806 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4807 inst
->src
[0] = inst
->src
[1];
4814 /* Replaces all references to a temporary register index with another index. */
4816 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4818 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4821 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4822 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4823 for (k
= 0; k
< num_renames
; k
++)
4824 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4825 inst
->src
[j
].index
= renames
[k
].new_reg
;
4828 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4829 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4830 for (k
= 0; k
< num_renames
; k
++)
4831 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4832 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4835 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
4836 for (k
= 0; k
< num_renames
; k
++)
4837 if (inst
->resource
.index
== renames
[k
].old_reg
)
4838 inst
->resource
.index
= renames
[k
].new_reg
;
4841 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4842 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4843 for (k
= 0; k
< num_renames
; k
++)
4844 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4845 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4851 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4853 int depth
= 0; /* loop depth */
4854 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4857 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4858 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4859 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4860 if (first_writes
[inst
->dst
[j
].index
] == -1)
4861 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4865 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4868 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4878 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4880 int depth
= 0; /* loop depth */
4881 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4884 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4885 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4886 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4887 if (first_reads
[inst
->src
[j
].index
] == -1)
4888 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4891 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4892 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4893 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4894 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4897 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4900 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4910 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4912 int depth
= 0; /* loop depth */
4913 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4916 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4917 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4918 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4919 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4921 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4922 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4923 if (first_writes
[inst
->dst
[j
].index
] == -1)
4924 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4925 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4928 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4929 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4930 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4932 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4935 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4938 for (k
= 0; k
< this->next_temp
; k
++) {
4939 if (last_reads
[k
] == -2) {
4951 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4953 int depth
= 0; /* loop depth */
4957 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4958 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4959 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4960 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4963 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4965 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4967 for (k
= 0; k
< this->next_temp
; k
++) {
4968 if (last_writes
[k
] == -2) {
4979 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4980 * channels for copy propagation and updates following instructions to
4981 * use the original versions.
4983 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4984 * will occur. As an example, a TXP production before this pass:
4986 * 0: MOV TEMP[1], INPUT[4].xyyy;
4987 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4988 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4992 * 0: MOV TEMP[1], INPUT[4].xyyy;
4993 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4994 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4996 * which allows for dead code elimination on TEMP[1]'s writes.
4999 glsl_to_tgsi_visitor::copy_propagate(void)
5001 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5002 glsl_to_tgsi_instruction
*,
5003 this->next_temp
* 4);
5004 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5007 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5008 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5009 || inst
->dst
[0].index
< this->next_temp
);
5011 /* First, do any copy propagation possible into the src regs. */
5012 for (int r
= 0; r
< 3; r
++) {
5013 glsl_to_tgsi_instruction
*first
= NULL
;
5015 int acp_base
= inst
->src
[r
].index
* 4;
5017 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5018 inst
->src
[r
].reladdr
||
5019 inst
->src
[r
].reladdr2
)
5022 /* See if we can find entries in the ACP consisting of MOVs
5023 * from the same src register for all the swizzled channels
5024 * of this src register reference.
5026 for (int i
= 0; i
< 4; i
++) {
5027 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5028 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5035 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5040 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5041 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5042 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5043 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5051 /* We've now validated that we can copy-propagate to
5052 * replace this src register reference. Do it.
5054 inst
->src
[r
].file
= first
->src
[0].file
;
5055 inst
->src
[r
].index
= first
->src
[0].index
;
5056 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5057 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5058 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5059 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5062 for (int i
= 0; i
< 4; i
++) {
5063 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5064 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5065 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5067 inst
->src
[r
].swizzle
= swizzle
;
5072 case TGSI_OPCODE_BGNLOOP
:
5073 case TGSI_OPCODE_ENDLOOP
:
5074 /* End of a basic block, clear the ACP entirely. */
5075 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5078 case TGSI_OPCODE_IF
:
5079 case TGSI_OPCODE_UIF
:
5083 case TGSI_OPCODE_ENDIF
:
5084 case TGSI_OPCODE_ELSE
:
5085 /* Clear all channels written inside the block from the ACP, but
5086 * leaving those that were not touched.
5088 for (int r
= 0; r
< this->next_temp
; r
++) {
5089 for (int c
= 0; c
< 4; c
++) {
5090 if (!acp
[4 * r
+ c
])
5093 if (acp_level
[4 * r
+ c
] >= level
)
5094 acp
[4 * r
+ c
] = NULL
;
5097 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5102 /* Continuing the block, clear any written channels from
5105 for (int d
= 0; d
< 2; d
++) {
5106 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5107 /* Any temporary might be written, so no copy propagation
5108 * across this instruction.
5110 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5111 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5112 inst
->dst
[d
].reladdr
) {
5113 /* Any output might be written, so no copy propagation
5114 * from outputs across this instruction.
5116 for (int r
= 0; r
< this->next_temp
; r
++) {
5117 for (int c
= 0; c
< 4; c
++) {
5118 if (!acp
[4 * r
+ c
])
5121 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5122 acp
[4 * r
+ c
] = NULL
;
5125 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5126 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5127 /* Clear where it's used as dst. */
5128 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5129 for (int c
= 0; c
< 4; c
++) {
5130 if (inst
->dst
[d
].writemask
& (1 << c
))
5131 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5135 /* Clear where it's used as src. */
5136 for (int r
= 0; r
< this->next_temp
; r
++) {
5137 for (int c
= 0; c
< 4; c
++) {
5138 if (!acp
[4 * r
+ c
])
5141 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5143 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5144 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5145 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5146 acp
[4 * r
+ c
] = NULL
;
5155 /* If this is a copy, add it to the ACP. */
5156 if (inst
->op
== TGSI_OPCODE_MOV
&&
5157 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5158 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5159 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5160 !inst
->dst
[0].reladdr
&&
5161 !inst
->dst
[0].reladdr2
&&
5163 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5164 !inst
->src
[0].reladdr
&&
5165 !inst
->src
[0].reladdr2
&&
5166 !inst
->src
[0].negate
&&
5167 !inst
->src
[0].abs
) {
5168 for (int i
= 0; i
< 4; i
++) {
5169 if (inst
->dst
[0].writemask
& (1 << i
)) {
5170 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5171 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5177 ralloc_free(acp_level
);
5182 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5185 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5186 * will occur. As an example, a TXP production after copy propagation but
5189 * 0: MOV TEMP[1], INPUT[4].xyyy;
5190 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5191 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5193 * and after this pass:
5195 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5198 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5200 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5201 glsl_to_tgsi_instruction
*,
5202 this->next_temp
* 4);
5203 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5207 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5208 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5209 || inst
->dst
[0].index
< this->next_temp
);
5212 case TGSI_OPCODE_BGNLOOP
:
5213 case TGSI_OPCODE_ENDLOOP
:
5214 case TGSI_OPCODE_CONT
:
5215 case TGSI_OPCODE_BRK
:
5216 /* End of a basic block, clear the write array entirely.
5218 * This keeps us from killing dead code when the writes are
5219 * on either side of a loop, even when the register isn't touched
5220 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5221 * dead code of this type, so it shouldn't make a difference as long as
5222 * the dead code elimination pass in the GLSL compiler does its job.
5224 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5227 case TGSI_OPCODE_ENDIF
:
5228 case TGSI_OPCODE_ELSE
:
5229 /* Promote the recorded level of all channels written inside the
5230 * preceding if or else block to the level above the if/else block.
5232 for (int r
= 0; r
< this->next_temp
; r
++) {
5233 for (int c
= 0; c
< 4; c
++) {
5234 if (!writes
[4 * r
+ c
])
5237 if (write_level
[4 * r
+ c
] == level
)
5238 write_level
[4 * r
+ c
] = level
-1;
5241 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5245 case TGSI_OPCODE_IF
:
5246 case TGSI_OPCODE_UIF
:
5248 /* fallthrough to default case to mark the condition as read */
5250 /* Continuing the block, clear any channels from the write array that
5251 * are read by this instruction.
5253 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5254 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5255 /* Any temporary might be read, so no dead code elimination
5256 * across this instruction.
5258 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5259 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5260 /* Clear where it's used as src. */
5261 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5262 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5263 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5264 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5266 for (int c
= 0; c
< 4; c
++) {
5267 if (src_chans
& (1 << c
))
5268 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5272 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5273 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5274 /* Any temporary might be read, so no dead code elimination
5275 * across this instruction.
5277 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5278 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5279 /* Clear where it's used as src. */
5280 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5281 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5282 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5283 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5285 for (int c
= 0; c
< 4; c
++) {
5286 if (src_chans
& (1 << c
))
5287 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5292 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5295 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5296 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5297 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5298 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5300 for (int c
= 0; c
< 4; c
++) {
5301 if (src_chans
& (1 << c
))
5302 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5309 /* If this instruction writes to a temporary, add it to the write array.
5310 * If there is already an instruction in the write array for one or more
5311 * of the channels, flag that channel write as dead.
5313 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5314 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5315 !inst
->dst
[i
].reladdr
) {
5316 for (int c
= 0; c
< 4; c
++) {
5317 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5318 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5319 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5322 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5324 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5325 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5332 /* Anything still in the write array at this point is dead code. */
5333 for (int r
= 0; r
< this->next_temp
; r
++) {
5334 for (int c
= 0; c
< 4; c
++) {
5335 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5337 inst
->dead_mask
|= (1 << c
);
5341 /* Now actually remove the instructions that are completely dead and update
5342 * the writemask of other instructions with dead channels.
5344 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5345 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5347 /* No amount of dead masks should remove memory stores */
5348 if (inst
->info
->is_store
)
5351 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5356 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5357 if (inst
->dead_mask
== WRITEMASK_XY
||
5358 inst
->dead_mask
== WRITEMASK_ZW
)
5359 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5361 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5365 ralloc_free(write_level
);
5366 ralloc_free(writes
);
5371 /* merge DFRACEXP instructions into one. */
5373 glsl_to_tgsi_visitor::merge_two_dsts(void)
5375 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5376 glsl_to_tgsi_instruction
*inst2
;
5378 if (num_inst_dst_regs(inst
) != 2)
5381 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5382 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5385 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5388 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5389 inst
->src
[0].index
== inst2
->src
[0].index
&&
5390 inst
->src
[0].type
== inst2
->src
[0].type
&&
5391 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5393 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5399 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5401 inst
->dst
[0] = inst2
->dst
[0];
5402 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5403 inst
->dst
[1] = inst2
->dst
[1];
5414 /* Merges temporary registers together where possible to reduce the number of
5415 * registers needed to run a program.
5417 * Produces optimal code only after copy propagation and dead code elimination
5420 glsl_to_tgsi_visitor::merge_registers(void)
5422 int *last_reads
= ralloc_array(mem_ctx
, int, this->next_temp
);
5423 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5424 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5426 int num_renames
= 0;
5428 /* Read the indices of the last read and first write to each temp register
5429 * into an array so that we don't have to traverse the instruction list as
5431 for (i
= 0; i
< this->next_temp
; i
++) {
5433 first_writes
[i
] = -1;
5435 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5437 /* Start looking for registers with non-overlapping usages that can be
5438 * merged together. */
5439 for (i
= 0; i
< this->next_temp
; i
++) {
5440 /* Don't touch unused registers. */
5441 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5443 for (j
= 0; j
< this->next_temp
; j
++) {
5444 /* Don't touch unused registers. */
5445 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5447 /* We can merge the two registers if the first write to j is after or
5448 * in the same instruction as the last read from i. Note that the
5449 * register at index i will always be used earlier or at the same time
5450 * as the register at index j. */
5451 if (first_writes
[i
] <= first_writes
[j
] &&
5452 last_reads
[i
] <= first_writes
[j
]) {
5453 renames
[num_renames
].old_reg
= j
;
5454 renames
[num_renames
].new_reg
= i
;
5457 /* Update the first_writes and last_reads arrays with the new
5458 * values for the merged register index, and mark the newly unused
5459 * register index as such. */
5460 assert(last_reads
[j
] >= last_reads
[i
]);
5461 last_reads
[i
] = last_reads
[j
];
5462 first_writes
[j
] = -1;
5468 rename_temp_registers(num_renames
, renames
);
5469 ralloc_free(renames
);
5470 ralloc_free(last_reads
);
5471 ralloc_free(first_writes
);
5474 /* Reassign indices to temporary registers by reusing unused indices created
5475 * by optimization passes. */
5477 glsl_to_tgsi_visitor::renumber_registers(void)
5481 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5482 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5483 int num_renames
= 0;
5485 for (i
= 0; i
< this->next_temp
; i
++) {
5486 first_writes
[i
] = -1;
5488 get_first_temp_write(first_writes
);
5490 for (i
= 0; i
< this->next_temp
; i
++) {
5491 if (first_writes
[i
] < 0) continue;
5492 if (i
!= new_index
) {
5493 renames
[num_renames
].old_reg
= i
;
5494 renames
[num_renames
].new_reg
= new_index
;
5500 rename_temp_registers(num_renames
, renames
);
5501 this->next_temp
= new_index
;
5502 ralloc_free(renames
);
5503 ralloc_free(first_writes
);
5506 /* ------------------------- TGSI conversion stuff -------------------------- */
5509 * Intermediate state used during shader translation.
5511 struct st_translate
{
5512 struct ureg_program
*ureg
;
5514 unsigned temps_size
;
5515 struct ureg_dst
*temps
;
5517 struct ureg_dst
*arrays
;
5518 unsigned num_temp_arrays
;
5519 struct ureg_src
*constants
;
5521 struct ureg_src
*immediates
;
5523 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5524 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5525 struct ureg_dst address
[3];
5526 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5527 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5528 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5529 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5530 struct ureg_src shared_memory
;
5531 unsigned *array_sizes
;
5532 struct inout_decl
*input_decls
;
5533 unsigned num_input_decls
;
5534 struct inout_decl
*output_decls
;
5535 unsigned num_output_decls
;
5537 const ubyte
*inputMapping
;
5538 const ubyte
*outputMapping
;
5540 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5543 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5545 _mesa_sysval_to_semantic(unsigned sysval
)
5549 case SYSTEM_VALUE_VERTEX_ID
:
5550 return TGSI_SEMANTIC_VERTEXID
;
5551 case SYSTEM_VALUE_INSTANCE_ID
:
5552 return TGSI_SEMANTIC_INSTANCEID
;
5553 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5554 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5555 case SYSTEM_VALUE_BASE_VERTEX
:
5556 return TGSI_SEMANTIC_BASEVERTEX
;
5557 case SYSTEM_VALUE_BASE_INSTANCE
:
5558 return TGSI_SEMANTIC_BASEINSTANCE
;
5559 case SYSTEM_VALUE_DRAW_ID
:
5560 return TGSI_SEMANTIC_DRAWID
;
5562 /* Geometry shader */
5563 case SYSTEM_VALUE_INVOCATION_ID
:
5564 return TGSI_SEMANTIC_INVOCATIONID
;
5566 /* Fragment shader */
5567 case SYSTEM_VALUE_FRAG_COORD
:
5568 return TGSI_SEMANTIC_POSITION
;
5569 case SYSTEM_VALUE_FRONT_FACE
:
5570 return TGSI_SEMANTIC_FACE
;
5571 case SYSTEM_VALUE_SAMPLE_ID
:
5572 return TGSI_SEMANTIC_SAMPLEID
;
5573 case SYSTEM_VALUE_SAMPLE_POS
:
5574 return TGSI_SEMANTIC_SAMPLEPOS
;
5575 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5576 return TGSI_SEMANTIC_SAMPLEMASK
;
5577 case SYSTEM_VALUE_HELPER_INVOCATION
:
5578 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5580 /* Tessellation shader */
5581 case SYSTEM_VALUE_TESS_COORD
:
5582 return TGSI_SEMANTIC_TESSCOORD
;
5583 case SYSTEM_VALUE_VERTICES_IN
:
5584 return TGSI_SEMANTIC_VERTICESIN
;
5585 case SYSTEM_VALUE_PRIMITIVE_ID
:
5586 return TGSI_SEMANTIC_PRIMID
;
5587 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5588 return TGSI_SEMANTIC_TESSOUTER
;
5589 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5590 return TGSI_SEMANTIC_TESSINNER
;
5592 /* Compute shader */
5593 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5594 return TGSI_SEMANTIC_THREAD_ID
;
5595 case SYSTEM_VALUE_WORK_GROUP_ID
:
5596 return TGSI_SEMANTIC_BLOCK_ID
;
5597 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5598 return TGSI_SEMANTIC_GRID_SIZE
;
5599 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5600 return TGSI_SEMANTIC_BLOCK_SIZE
;
5602 /* ARB_shader_ballot */
5603 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5604 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5605 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5606 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5607 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5608 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5609 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5610 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5611 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5612 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5613 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5614 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5615 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5616 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5619 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5620 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5621 case SYSTEM_VALUE_VERTEX_CNT
:
5623 assert(!"Unexpected SYSTEM_VALUE_ enum");
5624 return TGSI_SEMANTIC_COUNT
;
5629 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5631 static struct ureg_src
5632 emit_immediate(struct st_translate
*t
,
5633 gl_constant_value values
[4],
5636 struct ureg_program
*ureg
= t
->ureg
;
5641 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5643 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5645 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5646 case GL_UNSIGNED_INT64_ARB
:
5647 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5649 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5650 case GL_UNSIGNED_INT
:
5652 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5654 assert(!"should not get here - type must be float, int, uint, or bool");
5655 return ureg_src_undef();
5660 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5662 static struct ureg_dst
5663 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5669 case PROGRAM_UNDEFINED
:
5670 return ureg_dst_undef();
5672 case PROGRAM_TEMPORARY
:
5673 /* Allocate space for temporaries on demand. */
5674 if (index
>= t
->temps_size
) {
5675 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5677 t
->temps
= (struct ureg_dst
*)
5679 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5681 return ureg_dst_undef();
5683 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5684 t
->temps_size
+= inc
;
5687 if (ureg_dst_is_undef(t
->temps
[index
]))
5688 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5690 return t
->temps
[index
];
5693 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5694 array
= array_id
- 1;
5696 if (ureg_dst_is_undef(t
->arrays
[array
]))
5697 t
->arrays
[array
] = ureg_DECL_array_temporary(
5698 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5700 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5702 case PROGRAM_OUTPUT
:
5704 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5705 assert(index
< 2 * FRAG_RESULT_MAX
);
5706 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5707 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5708 assert(index
< VARYING_SLOT_TESS_MAX
);
5710 assert(index
< VARYING_SLOT_MAX
);
5712 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5713 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5714 return t
->outputs
[t
->outputMapping
[index
]];
5717 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5718 unsigned mesa_index
= decl
->mesa_index
;
5719 int slot
= t
->outputMapping
[mesa_index
];
5721 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5723 struct ureg_dst dst
= t
->outputs
[slot
];
5724 dst
.ArrayID
= array_id
;
5725 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5728 case PROGRAM_ADDRESS
:
5729 return t
->address
[index
];
5732 assert(!"unknown dst register file");
5733 return ureg_dst_undef();
5738 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5740 static struct ureg_src
5741 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5743 int index
= reg
->index
;
5744 int double_reg2
= reg
->double_reg2
? 1 : 0;
5747 case PROGRAM_UNDEFINED
:
5748 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5750 case PROGRAM_TEMPORARY
:
5752 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5754 case PROGRAM_OUTPUT
: {
5755 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5756 assert(dst
.WriteMask
!= 0);
5757 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5758 return ureg_swizzle(ureg_src(dst
),
5762 MIN2(shift
+ 3, 3));
5765 case PROGRAM_UNIFORM
:
5766 assert(reg
->index
>= 0);
5767 return reg
->index
< t
->num_constants
?
5768 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5769 case PROGRAM_STATE_VAR
:
5770 case PROGRAM_CONSTANT
: /* ie, immediate */
5771 if (reg
->has_index2
)
5772 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5774 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5775 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5777 case PROGRAM_IMMEDIATE
:
5778 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5779 return t
->immediates
[reg
->index
];
5782 /* GLSL inputs are 64-bit containers, so we have to
5783 * map back to the original index and add the offset after
5785 index
-= double_reg2
;
5786 if (!reg
->array_id
) {
5787 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5788 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5789 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5792 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5793 unsigned mesa_index
= decl
->mesa_index
;
5794 int slot
= t
->inputMapping
[mesa_index
];
5796 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5798 struct ureg_src src
= t
->inputs
[slot
];
5799 src
.ArrayID
= reg
->array_id
;
5800 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5803 case PROGRAM_ADDRESS
:
5804 return ureg_src(t
->address
[reg
->index
]);
5806 case PROGRAM_SYSTEM_VALUE
:
5807 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5808 return t
->systemValues
[reg
->index
];
5811 assert(!"unknown src register file");
5812 return ureg_src_undef();
5817 * Create a TGSI ureg_dst register from an st_dst_reg.
5819 static struct ureg_dst
5820 translate_dst(struct st_translate
*t
,
5821 const st_dst_reg
*dst_reg
,
5824 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5827 if (dst
.File
== TGSI_FILE_NULL
)
5830 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5833 dst
= ureg_saturate(dst
);
5835 if (dst_reg
->reladdr
!= NULL
) {
5836 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5837 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5840 if (dst_reg
->has_index2
) {
5841 if (dst_reg
->reladdr2
)
5842 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5845 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5852 * Create a TGSI ureg_src register from an st_src_reg.
5854 static struct ureg_src
5855 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5857 struct ureg_src src
= src_register(t
, src_reg
);
5859 if (src_reg
->has_index2
) {
5860 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5861 * and UBO constant buffers (buffer, position).
5863 if (src_reg
->reladdr2
)
5864 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5867 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5870 src
= ureg_swizzle(src
,
5871 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5872 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5873 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5874 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5877 src
= ureg_abs(src
);
5879 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5880 src
= ureg_negate(src
);
5882 if (src_reg
->reladdr
!= NULL
) {
5883 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5884 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5890 static struct tgsi_texture_offset
5891 translate_tex_offset(struct st_translate
*t
,
5892 const st_src_reg
*in_offset
)
5894 struct tgsi_texture_offset offset
;
5895 struct ureg_src src
= translate_src(t
, in_offset
);
5897 offset
.File
= src
.File
;
5898 offset
.Index
= src
.Index
;
5899 offset
.SwizzleX
= src
.SwizzleX
;
5900 offset
.SwizzleY
= src
.SwizzleY
;
5901 offset
.SwizzleZ
= src
.SwizzleZ
;
5904 assert(!src
.Indirect
);
5905 assert(!src
.DimIndirect
);
5906 assert(!src
.Dimension
);
5907 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5908 assert(!src
.Negate
);
5914 compile_tgsi_instruction(struct st_translate
*t
,
5915 const glsl_to_tgsi_instruction
*inst
)
5917 struct ureg_program
*ureg
= t
->ureg
;
5919 struct ureg_dst dst
[2];
5920 struct ureg_src src
[4];
5921 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5925 unsigned tex_target
= 0;
5927 num_dst
= num_inst_dst_regs(inst
);
5928 num_src
= num_inst_src_regs(inst
);
5930 for (i
= 0; i
< num_dst
; i
++)
5931 dst
[i
] = translate_dst(t
,
5935 for (i
= 0; i
< num_src
; i
++)
5936 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5939 case TGSI_OPCODE_BGNLOOP
:
5940 case TGSI_OPCODE_ELSE
:
5941 case TGSI_OPCODE_ENDLOOP
:
5942 case TGSI_OPCODE_IF
:
5943 case TGSI_OPCODE_UIF
:
5944 assert(num_dst
== 0);
5945 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5948 case TGSI_OPCODE_TEX
:
5949 case TGSI_OPCODE_TEX_LZ
:
5950 case TGSI_OPCODE_TXB
:
5951 case TGSI_OPCODE_TXD
:
5952 case TGSI_OPCODE_TXL
:
5953 case TGSI_OPCODE_TXP
:
5954 case TGSI_OPCODE_TXQ
:
5955 case TGSI_OPCODE_TXQS
:
5956 case TGSI_OPCODE_TXF
:
5957 case TGSI_OPCODE_TXF_LZ
:
5958 case TGSI_OPCODE_TEX2
:
5959 case TGSI_OPCODE_TXB2
:
5960 case TGSI_OPCODE_TXL2
:
5961 case TGSI_OPCODE_TG4
:
5962 case TGSI_OPCODE_LODQ
:
5963 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5964 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5966 /* Bindless samplers. */
5967 src
[num_src
] = translate_src(t
, &inst
->resource
);
5969 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5970 if (inst
->resource
.reladdr
)
5972 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5974 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5975 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5977 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5983 st_translate_texture_type(inst
->tex_type
),
5984 texoffsets
, inst
->tex_offset_num_offset
,
5988 case TGSI_OPCODE_RESQ
:
5989 case TGSI_OPCODE_LOAD
:
5990 case TGSI_OPCODE_ATOMUADD
:
5991 case TGSI_OPCODE_ATOMXCHG
:
5992 case TGSI_OPCODE_ATOMCAS
:
5993 case TGSI_OPCODE_ATOMAND
:
5994 case TGSI_OPCODE_ATOMOR
:
5995 case TGSI_OPCODE_ATOMXOR
:
5996 case TGSI_OPCODE_ATOMUMIN
:
5997 case TGSI_OPCODE_ATOMUMAX
:
5998 case TGSI_OPCODE_ATOMIMIN
:
5999 case TGSI_OPCODE_ATOMIMAX
:
6000 for (i
= num_src
- 1; i
>= 0; i
--)
6001 src
[i
+ 1] = src
[i
];
6003 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6004 src
[0] = t
->shared_memory
;
6005 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6006 src
[0] = t
->buffers
[inst
->resource
.index
];
6008 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6009 src
[0] = t
->images
[inst
->resource
.index
];
6011 /* Bindless images. */
6012 src
[0] = translate_src(t
, &inst
->resource
);
6014 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6016 if (inst
->resource
.reladdr
)
6017 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
6018 assert(src
[0].File
!= TGSI_FILE_NULL
);
6019 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6020 inst
->buffer_access
,
6021 tex_target
, inst
->image_format
);
6024 case TGSI_OPCODE_STORE
:
6025 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6026 dst
[0] = ureg_dst(t
->shared_memory
);
6027 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6028 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6030 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6031 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6033 /* Bindless images. */
6034 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6036 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6038 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6039 if (inst
->resource
.reladdr
)
6040 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
6041 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6042 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6043 inst
->buffer_access
,
6044 tex_target
, inst
->image_format
);
6051 src
, num_src
, inst
->precise
);
6057 * Emit the TGSI instructions for inverting and adjusting WPOS.
6058 * This code is unavoidable because it also depends on whether
6059 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6062 emit_wpos_adjustment(struct gl_context
*ctx
,
6063 struct st_translate
*t
,
6064 int wpos_transform_const
,
6066 GLfloat adjX
, GLfloat adjY
[2])
6068 struct ureg_program
*ureg
= t
->ureg
;
6070 assert(wpos_transform_const
>= 0);
6072 /* Fragment program uses fragment position input.
6073 * Need to replace instances of INPUT[WPOS] with temp T
6074 * where T = INPUT[WPOS] is inverted by Y.
6076 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6077 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
6078 struct ureg_src
*wpos
=
6079 ctx
->Const
.GLSLFragCoordIsSysVal
?
6080 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6081 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6082 struct ureg_src wpos_input
= *wpos
;
6084 /* First, apply the coordinate shift: */
6085 if (adjX
|| adjY
[0] || adjY
[1]) {
6086 if (adjY
[0] != adjY
[1]) {
6087 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6088 * depending on whether inversion is actually going to be applied
6089 * or not, which is determined by testing against the inversion
6090 * state variable used below, which will be either +1 or -1.
6092 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6094 ureg_CMP(ureg
, adj_temp
,
6095 ureg_scalar(wpostrans
, invert
? 2 : 0),
6096 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6097 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6098 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6100 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6101 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6103 wpos_input
= ureg_src(wpos_temp
);
6105 /* MOV wpos_temp, input[wpos]
6107 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
6110 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6111 * inversion/identity, or the other way around if we're drawing to an FBO.
6114 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6117 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6119 ureg_scalar(wpostrans
, 0),
6120 ureg_scalar(wpostrans
, 1));
6122 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6125 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6127 ureg_scalar(wpostrans
, 2),
6128 ureg_scalar(wpostrans
, 3));
6131 /* Use wpos_temp as position input from here on:
6133 *wpos
= ureg_src(wpos_temp
);
6138 * Emit fragment position/ooordinate code.
6141 emit_wpos(struct st_context
*st
,
6142 struct st_translate
*t
,
6143 const struct gl_program
*program
,
6144 struct ureg_program
*ureg
,
6145 int wpos_transform_const
)
6147 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6148 GLfloat adjX
= 0.0f
;
6149 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6150 boolean invert
= FALSE
;
6152 /* Query the pixel center conventions supported by the pipe driver and set
6153 * adjX, adjY to help out if it cannot handle the requested one internally.
6155 * The bias of the y-coordinate depends on whether y-inversion takes place
6156 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6157 * drawing to an FBO (causes additional inversion), and whether the pipe
6158 * driver origin and the requested origin differ (the latter condition is
6159 * stored in the 'invert' variable).
6161 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6163 * center shift only:
6168 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6169 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6170 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6171 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6173 * inversion and center shift:
6174 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6175 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6176 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6177 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6179 if (program
->OriginUpperLeft
) {
6180 /* Fragment shader wants origin in upper-left */
6181 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6182 /* the driver supports upper-left origin */
6184 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6185 /* the driver supports lower-left origin, need to invert Y */
6186 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6187 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6194 /* Fragment shader wants origin in lower-left */
6195 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6196 /* the driver supports lower-left origin */
6197 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6198 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6199 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6200 /* the driver supports upper-left origin, need to invert Y */
6206 if (program
->PixelCenterInteger
) {
6207 /* Fragment shader wants pixel center integer */
6208 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6209 /* the driver supports pixel center integer */
6211 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6212 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6214 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6215 /* the driver supports pixel center half integer, need to bias X,Y */
6224 /* Fragment shader wants pixel center half integer */
6225 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6226 /* the driver supports pixel center half integer */
6228 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6229 /* the driver supports pixel center integer, need to bias X,Y */
6230 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6231 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6232 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6238 /* we invert after adjustment so that we avoid the MOV to temporary,
6239 * and reuse the adjustment ADD instead */
6240 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6244 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6245 * TGSI uses +1 for front, -1 for back.
6246 * This function converts the TGSI value to the GL value. Simply clamping/
6247 * saturating the value to [0,1] does the job.
6250 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6252 struct ureg_program
*ureg
= t
->ureg
;
6253 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6254 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6256 if (ctx
->Const
.NativeIntegers
) {
6257 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6260 /* MOV_SAT face_temp, input[face] */
6261 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6264 /* Use face_temp as face input from here on: */
6265 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6269 emit_compute_block_size(const struct gl_program
*prog
,
6270 struct ureg_program
*ureg
) {
6271 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6272 prog
->info
.cs
.local_size
[0]);
6273 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6274 prog
->info
.cs
.local_size
[1]);
6275 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6276 prog
->info
.cs
.local_size
[2]);
6279 struct sort_inout_decls
{
6280 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6281 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6284 const ubyte
*mapping
;
6287 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6289 * This is for the benefit of older drivers which are broken when the
6290 * declarations aren't sorted in this way.
6293 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6295 const ubyte mapping
[])
6297 sort_inout_decls sorter
;
6298 sorter
.mapping
= mapping
;
6299 std::sort(decls
, decls
+ count
, sorter
);
6303 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6305 switch (glsl_qual
) {
6306 case INTERP_MODE_NONE
:
6307 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6308 return TGSI_INTERPOLATE_COLOR
;
6309 return TGSI_INTERPOLATE_PERSPECTIVE
;
6310 case INTERP_MODE_SMOOTH
:
6311 return TGSI_INTERPOLATE_PERSPECTIVE
;
6312 case INTERP_MODE_FLAT
:
6313 return TGSI_INTERPOLATE_CONSTANT
;
6314 case INTERP_MODE_NOPERSPECTIVE
:
6315 return TGSI_INTERPOLATE_LINEAR
;
6317 assert(0 && "unexpected interp mode in st_translate_interp()");
6318 return TGSI_INTERPOLATE_PERSPECTIVE
;
6323 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6324 * \param program the program to translate
6325 * \param numInputs number of input registers used
6326 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6328 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6329 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6331 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6332 * \param numOutputs number of output registers used
6333 * \param outputMapping maps Mesa fragment program outputs to TGSI
6335 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6336 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6339 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6341 extern "C" enum pipe_error
6342 st_translate_program(
6343 struct gl_context
*ctx
,
6345 struct ureg_program
*ureg
,
6346 glsl_to_tgsi_visitor
*program
,
6347 const struct gl_program
*proginfo
,
6349 const ubyte inputMapping
[],
6350 const ubyte inputSlotToAttr
[],
6351 const ubyte inputSemanticName
[],
6352 const ubyte inputSemanticIndex
[],
6353 const ubyte interpMode
[],
6355 const ubyte outputMapping
[],
6356 const ubyte outputSemanticName
[],
6357 const ubyte outputSemanticIndex
[])
6359 struct st_translate
*t
;
6361 struct gl_program_constants
*frag_const
=
6362 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6363 enum pipe_error ret
= PIPE_OK
;
6365 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6366 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6368 t
= CALLOC_STRUCT(st_translate
);
6370 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6374 t
->procType
= procType
;
6375 t
->inputMapping
= inputMapping
;
6376 t
->outputMapping
= outputMapping
;
6378 t
->num_temp_arrays
= program
->next_array
;
6379 if (t
->num_temp_arrays
)
6380 t
->arrays
= (struct ureg_dst
*)
6381 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6384 * Declare input attributes.
6387 case PIPE_SHADER_FRAGMENT
:
6388 case PIPE_SHADER_GEOMETRY
:
6389 case PIPE_SHADER_TESS_EVAL
:
6390 case PIPE_SHADER_TESS_CTRL
:
6391 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6393 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6394 struct inout_decl
*decl
= &program
->inputs
[i
];
6395 unsigned slot
= inputMapping
[decl
->mesa_index
];
6396 struct ureg_src src
;
6397 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6399 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6400 if (tgsi_usage_mask
== 1)
6401 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6402 else if (tgsi_usage_mask
== 2)
6403 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6405 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6408 unsigned interp_mode
= 0;
6409 unsigned interp_location
= 0;
6410 if (procType
== PIPE_SHADER_FRAGMENT
) {
6412 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6414 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6416 interp_location
= decl
->interp_loc
;
6419 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6420 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6421 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6422 decl
->array_id
, decl
->size
);
6424 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6425 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6426 /* The ArrayID is set up in dst_register */
6427 t
->inputs
[slot
+ j
] = src
;
6428 t
->inputs
[slot
+ j
].ArrayID
= 0;
6429 t
->inputs
[slot
+ j
].Index
+= j
;
6434 case PIPE_SHADER_VERTEX
:
6435 for (i
= 0; i
< numInputs
; i
++) {
6436 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6439 case PIPE_SHADER_COMPUTE
:
6446 * Declare output attributes.
6449 case PIPE_SHADER_FRAGMENT
:
6450 case PIPE_SHADER_COMPUTE
:
6452 case PIPE_SHADER_GEOMETRY
:
6453 case PIPE_SHADER_TESS_EVAL
:
6454 case PIPE_SHADER_TESS_CTRL
:
6455 case PIPE_SHADER_VERTEX
:
6456 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6458 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6459 struct inout_decl
*decl
= &program
->outputs
[i
];
6460 unsigned slot
= outputMapping
[decl
->mesa_index
];
6461 struct ureg_dst dst
;
6462 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6464 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6465 if (tgsi_usage_mask
== 1)
6466 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6467 else if (tgsi_usage_mask
== 2)
6468 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6470 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6473 dst
= ureg_DECL_output_layout(ureg
,
6474 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6475 decl
->gs_out_streams
,
6476 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6478 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6479 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6480 /* The ArrayID is set up in dst_register */
6481 t
->outputs
[slot
+ j
] = dst
;
6482 t
->outputs
[slot
+ j
].ArrayID
= 0;
6483 t
->outputs
[slot
+ j
].Index
+= j
;
6492 if (procType
== PIPE_SHADER_FRAGMENT
) {
6493 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6494 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6495 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6497 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6498 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6501 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6502 /* Must do this after setting up t->inputs. */
6503 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6504 program
->wpos_transform_const
);
6507 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6508 emit_face_var(ctx
, t
);
6510 for (i
= 0; i
< numOutputs
; i
++) {
6511 switch (outputSemanticName
[i
]) {
6512 case TGSI_SEMANTIC_POSITION
:
6513 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6514 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6515 outputSemanticIndex
[i
]);
6516 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6518 case TGSI_SEMANTIC_STENCIL
:
6519 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6520 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6521 outputSemanticIndex
[i
]);
6522 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6524 case TGSI_SEMANTIC_COLOR
:
6525 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6526 TGSI_SEMANTIC_COLOR
,
6527 outputSemanticIndex
[i
]);
6529 case TGSI_SEMANTIC_SAMPLEMASK
:
6530 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6531 TGSI_SEMANTIC_SAMPLEMASK
,
6532 outputSemanticIndex
[i
]);
6533 /* TODO: If we ever support more than 32 samples, this will have
6534 * to become an array.
6536 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6539 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6540 ret
= PIPE_ERROR_BAD_INPUT
;
6545 else if (procType
== PIPE_SHADER_VERTEX
) {
6546 for (i
= 0; i
< numOutputs
; i
++) {
6547 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6548 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6550 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6551 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6552 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6557 if (procType
== PIPE_SHADER_COMPUTE
) {
6558 emit_compute_block_size(proginfo
, ureg
);
6561 /* Declare address register.
6563 if (program
->num_address_regs
> 0) {
6564 assert(program
->num_address_regs
<= 3);
6565 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6566 t
->address
[i
] = ureg_DECL_address(ureg
);
6569 /* Declare misc input registers
6572 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6574 for (i
= 0; sysInputs
; i
++) {
6575 if (sysInputs
& (1 << i
)) {
6576 unsigned semName
= _mesa_sysval_to_semantic(i
);
6578 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6580 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6581 semName
== TGSI_SEMANTIC_VERTEXID
) {
6582 /* From Gallium perspective, these system values are always
6583 * integer, and require native integer support. However, if
6584 * native integer is supported on the vertex stage but not the
6585 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6586 * assumes these system values are floats. To resolve the
6587 * inconsistency, we insert a U2F.
6589 struct st_context
*st
= st_context(ctx
);
6590 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6591 assert(procType
== PIPE_SHADER_VERTEX
);
6592 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6594 if (!ctx
->Const
.NativeIntegers
) {
6595 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6596 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6597 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6601 if (procType
== PIPE_SHADER_FRAGMENT
&&
6602 semName
== TGSI_SEMANTIC_POSITION
)
6603 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6604 program
->wpos_transform_const
);
6606 sysInputs
&= ~(1 << i
);
6611 t
->array_sizes
= program
->array_sizes
;
6612 t
->input_decls
= program
->inputs
;
6613 t
->num_input_decls
= program
->num_inputs
;
6614 t
->output_decls
= program
->outputs
;
6615 t
->num_output_decls
= program
->num_outputs
;
6617 /* Emit constants and uniforms. TGSI uses a single index space for these,
6618 * so we put all the translated regs in t->constants.
6620 if (proginfo
->Parameters
) {
6621 t
->constants
= (struct ureg_src
*)
6622 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6623 if (t
->constants
== NULL
) {
6624 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6627 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6629 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6630 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6631 case PROGRAM_STATE_VAR
:
6632 case PROGRAM_UNIFORM
:
6633 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6636 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6637 * addressing of the const buffer.
6638 * FIXME: Be smarter and recognize param arrays:
6639 * indirect addressing is only valid within the referenced
6642 case PROGRAM_CONSTANT
:
6643 if (program
->indirect_addr_consts
)
6644 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6646 t
->constants
[i
] = emit_immediate(t
,
6647 proginfo
->Parameters
->ParameterValues
[i
],
6648 proginfo
->Parameters
->Parameters
[i
].DataType
,
6657 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6658 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6659 unsigned num_const_vecs
= (size
+ 15) / 16;
6660 unsigned first
, last
;
6661 assert(num_const_vecs
> 0);
6663 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6664 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6667 /* Emit immediate values.
6669 t
->immediates
= (struct ureg_src
*)
6670 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6671 if (t
->immediates
== NULL
) {
6672 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6675 t
->num_immediates
= program
->num_immediates
;
6678 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6679 assert(i
< program
->num_immediates
);
6680 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6682 assert(i
== program
->num_immediates
);
6684 /* texture samplers */
6685 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6686 if (program
->samplers_used
& (1u << i
)) {
6687 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6689 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6691 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6692 type
, type
, type
, type
);
6696 /* Declare atomic and shader storage buffers. */
6698 struct gl_program
*prog
= program
->prog
;
6700 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6701 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6702 assert(index
< frag_const
->MaxAtomicBuffers
);
6703 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6706 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6707 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6708 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6709 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6713 if (program
->use_shared_memory
)
6714 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6716 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6717 if (program
->images_used
& (1 << i
)) {
6718 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6719 program
->image_targets
[i
],
6720 program
->image_formats
[i
],
6725 /* Emit each instruction in turn:
6727 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6728 compile_tgsi_instruction(t
, inst
);
6730 /* Set the next shader stage hint for VS and TES. */
6732 case PIPE_SHADER_VERTEX
:
6733 case PIPE_SHADER_TESS_EVAL
:
6734 if (program
->shader_program
->SeparateShader
)
6737 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6738 if (program
->shader_program
->_LinkedShaders
[i
]) {
6739 ureg_set_next_shader_processor(
6740 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6752 t
->num_constants
= 0;
6753 free(t
->immediates
);
6754 t
->num_immediates
= 0;
6760 /* ----------------------------- End TGSI code ------------------------------ */
6764 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6765 * generating Mesa IR.
6767 static struct gl_program
*
6768 get_mesa_program_tgsi(struct gl_context
*ctx
,
6769 struct gl_shader_program
*shader_program
,
6770 struct gl_linked_shader
*shader
)
6772 glsl_to_tgsi_visitor
* v
;
6773 struct gl_program
*prog
;
6774 struct gl_shader_compiler_options
*options
=
6775 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6776 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6777 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6778 unsigned skip_merge_registers
;
6780 validate_ir_tree(shader
->ir
);
6782 prog
= shader
->Program
;
6784 prog
->Parameters
= _mesa_new_parameter_list();
6785 v
= new glsl_to_tgsi_visitor();
6788 v
->shader_program
= shader_program
;
6790 v
->options
= options
;
6791 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6792 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6794 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6795 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6796 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6797 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6798 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6799 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6801 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6802 _mesa_key_pointer_equal
);
6803 skip_merge_registers
=
6804 pscreen
->get_shader_param(pscreen
, ptarget
,
6805 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6807 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6810 /* Remove reads from output registers. */
6811 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6812 lower_output_reads(shader
->Stage
, shader
->ir
);
6814 /* Emit intermediate IR for main(). */
6815 visit_exec_list(shader
->ir
, v
);
6818 /* Print out some information (for debugging purposes) used by the
6819 * optimization passes. */
6822 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6823 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6824 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6825 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6827 for (i
= 0; i
< v
->next_temp
; i
++) {
6828 first_writes
[i
] = -1;
6829 first_reads
[i
] = -1;
6830 last_writes
[i
] = -1;
6833 v
->get_first_temp_read(first_reads
);
6834 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6835 v
->get_last_temp_write(last_writes
);
6836 for (i
= 0; i
< v
->next_temp
; i
++)
6837 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6841 ralloc_free(first_writes
);
6842 ralloc_free(first_reads
);
6843 ralloc_free(last_writes
);
6844 ralloc_free(last_reads
);
6848 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6851 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6852 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6853 v
->copy_propagate();
6855 while (v
->eliminate_dead_code());
6857 v
->merge_two_dsts();
6858 if (!skip_merge_registers
)
6859 v
->merge_registers();
6860 v
->renumber_registers();
6862 /* Write the END instruction. */
6863 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6865 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6867 _mesa_log("GLSL IR for linked %s program %d:\n",
6868 _mesa_shader_stage_to_string(shader
->Stage
),
6869 shader_program
->Name
);
6870 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6874 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6875 _mesa_copy_linked_program_data(shader_program
, shader
);
6876 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6877 &prog
->info
.inputs_read
,
6878 prog
->info
.double_inputs_read
,
6879 &prog
->info
.patch_inputs_read
);
6880 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6881 &prog
->info
.outputs_written
, 0ULL,
6882 &prog
->info
.patch_outputs_written
);
6883 count_resources(v
, prog
);
6885 /* The GLSL IR won't be needed anymore. */
6886 ralloc_free(shader
->ir
);
6889 /* This must be done before the uniform storage is associated. */
6890 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6891 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6892 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6893 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6894 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6897 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6898 wposTransformState
);
6901 /* Avoid reallocation of the program parameter list, because the uniform
6902 * storage is only associated with the original parameter list.
6903 * This should be enough for Bitmap and DrawPixels constants.
6905 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6907 /* This has to be done last. Any operation the can cause
6908 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6909 * program constant) has to happen before creating this linkage.
6911 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6912 if (!shader_program
->data
->LinkStatus
) {
6913 free_glsl_to_tgsi_visitor(v
);
6914 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6918 struct st_vertex_program
*stvp
;
6919 struct st_fragment_program
*stfp
;
6920 struct st_common_program
*stp
;
6921 struct st_compute_program
*stcp
;
6923 switch (shader
->Stage
) {
6924 case MESA_SHADER_VERTEX
:
6925 stvp
= (struct st_vertex_program
*)prog
;
6926 stvp
->glsl_to_tgsi
= v
;
6928 case MESA_SHADER_FRAGMENT
:
6929 stfp
= (struct st_fragment_program
*)prog
;
6930 stfp
->glsl_to_tgsi
= v
;
6932 case MESA_SHADER_TESS_CTRL
:
6933 case MESA_SHADER_TESS_EVAL
:
6934 case MESA_SHADER_GEOMETRY
:
6935 stp
= st_common_program(prog
);
6936 stp
->glsl_to_tgsi
= v
;
6938 case MESA_SHADER_COMPUTE
:
6939 stcp
= (struct st_compute_program
*)prog
;
6940 stcp
->glsl_to_tgsi
= v
;
6943 assert(!"should not be reached");
6950 /* See if there are unsupported control flow statements. */
6951 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6953 const struct gl_shader_compiler_options
*options
;
6955 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6961 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6963 /* Other functions are skipped (same as glsl_to_tgsi). */
6964 if (strcmp(ir
->name
, "main") == 0)
6965 return visit_continue
;
6967 return visit_continue_with_parent
;
6970 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6972 if (!ir
->callee
->is_intrinsic()) {
6973 unsupported
= true; /* it's a function call */
6976 return visit_continue
;
6979 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6981 if (options
->EmitNoMainReturn
) {
6985 return visit_continue
;
6992 has_unsupported_control_flow(exec_list
*ir
,
6993 const struct gl_shader_compiler_options
*options
)
6995 ir_control_flow_info_visitor
visitor(options
);
6996 visit_list_elements(&visitor
, ir
);
6997 return visitor
.unsupported
;
7004 * Called via ctx->Driver.LinkShader()
7005 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7006 * with code lowering and other optimizations.
7009 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7011 /* Return early if we are loading the shader from on-disk cache */
7012 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
7016 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7017 assert(prog
->data
->LinkStatus
);
7019 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7020 if (prog
->_LinkedShaders
[i
] == NULL
)
7023 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7024 exec_list
*ir
= shader
->ir
;
7025 gl_shader_stage stage
= shader
->Stage
;
7026 const struct gl_shader_compiler_options
*options
=
7027 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7028 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7029 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7030 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7031 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7032 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7033 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7034 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7036 /* If there are forms of indirect addressing that the driver
7037 * cannot handle, perform the lowering pass.
7039 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7040 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7041 lower_variable_index_to_cond_assign(stage
, ir
,
7042 options
->EmitNoIndirectInput
,
7043 options
->EmitNoIndirectOutput
,
7044 options
->EmitNoIndirectTemp
,
7045 options
->EmitNoIndirectUniform
);
7048 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7049 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7051 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7052 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7053 LOWER_UNPACK_SNORM_2x16
|
7054 LOWER_PACK_UNORM_2x16
|
7055 LOWER_UNPACK_UNORM_2x16
|
7056 LOWER_PACK_SNORM_4x8
|
7057 LOWER_UNPACK_SNORM_4x8
|
7058 LOWER_UNPACK_UNORM_4x8
|
7059 LOWER_PACK_UNORM_4x8
;
7061 if (ctx
->Extensions
.ARB_gpu_shader5
)
7062 lower_inst
|= LOWER_PACK_USE_BFI
|
7064 if (!ctx
->st
->has_half_float_packing
)
7065 lower_inst
|= LOWER_PACK_HALF_2x16
|
7066 LOWER_UNPACK_HALF_2x16
;
7068 lower_packing_builtins(ir
, lower_inst
);
7071 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7072 lower_offset_arrays(ir
);
7073 do_mat_op_to_vec(ir
);
7075 if (stage
== MESA_SHADER_FRAGMENT
)
7076 lower_blend_equation_advanced(shader
);
7078 lower_instructions(ir
,
7084 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7087 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7088 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7089 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7090 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7091 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7092 /* Assume that if ARB_gpu_shader5 is not supported
7093 * then all of the extended integer functions need
7094 * lowering. It may be necessary to add some caps
7095 * for individual instructions.
7097 (!ctx
->Extensions
.ARB_gpu_shader5
7098 ? BIT_COUNT_TO_MATH
|
7102 FIND_LSB_TO_FLOAT_CAST
|
7103 FIND_MSB_TO_FLOAT_CAST
|
7107 do_vec_index_to_cond_assign(ir
);
7108 lower_vector_insert(ir
, true);
7109 lower_quadop_vector(ir
, false);
7111 if (options
->MaxIfDepth
== 0) {
7115 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7116 /* Do it once and repeat only if there's unsupported control flow. */
7118 do_common_optimization(ir
, true, true, options
,
7119 ctx
->Const
.NativeIntegers
);
7120 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7121 options
->MaxIfDepth
, if_threshold
);
7122 } while (has_unsupported_control_flow(ir
, options
));
7124 /* Repeat it until it stops making changes. */
7127 progress
= do_common_optimization(ir
, true, true, options
,
7128 ctx
->Const
.NativeIntegers
);
7129 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7130 options
->MaxIfDepth
, if_threshold
);
7134 validate_ir_tree(ir
);
7137 build_program_resource_list(ctx
, prog
);
7139 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7140 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7144 enum pipe_shader_type ptarget
=
7145 pipe_shader_type_from_mesa(shader
->Stage
);
7146 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7147 pscreen
->get_shader_param(pscreen
, ptarget
,
7148 PIPE_SHADER_CAP_PREFERRED_IR
);
7150 struct gl_program
*linked_prog
= NULL
;
7151 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
7152 /* TODO only for GLSL VS/FS/CS for now: */
7153 switch (shader
->Stage
) {
7154 case MESA_SHADER_VERTEX
:
7155 case MESA_SHADER_FRAGMENT
:
7156 case MESA_SHADER_COMPUTE
:
7157 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
7162 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
7166 st_set_prog_affected_state_flags(linked_prog
);
7167 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7168 _mesa_shader_stage_to_program(i
),
7170 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7180 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7181 const ubyte outputMapping
[],
7182 struct pipe_stream_output_info
*so
)
7184 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7187 struct gl_transform_feedback_info
*info
=
7188 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7189 st_translate_stream_output_info2(info
, outputMapping
, so
);
7193 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7194 const ubyte outputMapping
[],
7195 struct pipe_stream_output_info
*so
)
7199 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7200 so
->output
[i
].register_index
=
7201 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7202 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7203 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7204 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7205 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7206 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7209 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7210 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7212 so
->num_outputs
= info
->NumOutputs
;