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st/mesa: s/int/GLenum/ in st_glsl_to_tgsi.cpp
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_nir.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
59
60 #include "util/hash_table.h"
61 #include <algorithm>
62
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
66
67 #define MAX_GLSL_TEXTURE_OFFSET 4
68
69 static unsigned is_precise(const ir_variable *ir)
70 {
71 if (!ir)
72 return 0;
73 return ir->data.precise || ir->data.invariant;
74 }
75
76 class variable_storage {
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
78
79 public:
80 variable_storage(ir_variable *var, gl_register_file file, int index,
81 unsigned array_id = 0)
82 : file(file), index(index), component(0), var(var), array_id(array_id)
83 {
84 assert(file != PROGRAM_ARRAY || array_id != 0);
85 }
86
87 gl_register_file file;
88 int index;
89
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
93 */
94 int component;
95 ir_variable *var; /* variable that maps to this, if any */
96 unsigned array_id;
97 };
98
99 class immediate_storage : public exec_node {
100 public:
101 immediate_storage(gl_constant_value *values, int size32, GLenum type)
102 {
103 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
104 this->size32 = size32;
105 this->type = type;
106 }
107
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values[4];
110 int size32; /**< Number of 32-bit components (1-4) */
111 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
112 };
113
114 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
115 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
116
117 struct inout_decl {
118 unsigned mesa_index;
119 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
120 unsigned size;
121 unsigned interp_loc;
122 unsigned gs_out_streams;
123 enum glsl_interp_mode interp;
124 enum glsl_base_type base_type;
125 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
126 };
127
128 static struct inout_decl *
129 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
130 {
131 assert(array_id != 0);
132
133 for (unsigned i = 0; i < count; i++) {
134 struct inout_decl *decl = &decls[i];
135
136 if (array_id == decl->array_id) {
137 return decl;
138 }
139 }
140
141 return NULL;
142 }
143
144 static enum glsl_base_type
145 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
146 {
147 if (!array_id)
148 return GLSL_TYPE_ERROR;
149 struct inout_decl *decl = find_inout_array(decls, count, array_id);
150 if (decl)
151 return decl->base_type;
152 return GLSL_TYPE_ERROR;
153 }
154
155 struct hwatomic_decl {
156 unsigned location;
157 unsigned binding;
158 unsigned size;
159 unsigned array_id;
160 };
161
162 struct glsl_to_tgsi_visitor : public ir_visitor {
163 public:
164 glsl_to_tgsi_visitor();
165 ~glsl_to_tgsi_visitor();
166
167 struct gl_context *ctx;
168 struct gl_program *prog;
169 struct gl_shader_program *shader_program;
170 struct gl_linked_shader *shader;
171 struct gl_shader_compiler_options *options;
172
173 int next_temp;
174
175 unsigned *array_sizes;
176 unsigned max_num_arrays;
177 unsigned next_array;
178
179 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
180 unsigned num_inputs;
181 unsigned num_input_arrays;
182 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
183 unsigned num_outputs;
184 unsigned num_output_arrays;
185
186 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
187 unsigned num_atomics;
188 unsigned num_atomic_arrays;
189 int num_address_regs;
190 uint32_t samplers_used;
191 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
192 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
193 int images_used;
194 int image_targets[PIPE_MAX_SHADER_IMAGES];
195 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
196 bool indirect_addr_consts;
197 int wpos_transform_const;
198
199 bool native_integers;
200 bool have_sqrt;
201 bool have_fma;
202 bool use_shared_memory;
203 bool has_tex_txf_lz;
204 bool precise;
205 bool need_uarl;
206
207 variable_storage *find_variable_storage(ir_variable *var);
208
209 int add_constant(gl_register_file file, gl_constant_value values[8],
210 int size, GLenum datatype, uint16_t *swizzle_out);
211
212 st_src_reg get_temp(const glsl_type *type);
213 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
214
215 st_src_reg st_src_reg_for_double(double val);
216 st_src_reg st_src_reg_for_float(float val);
217 st_src_reg st_src_reg_for_int(int val);
218 st_src_reg st_src_reg_for_int64(int64_t val);
219 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
220
221 /**
222 * \name Visit methods
223 *
224 * As typical for the visitor pattern, there must be one \c visit method for
225 * each concrete subclass of \c ir_instruction. Virtual base classes within
226 * the hierarchy should not have \c visit methods.
227 */
228 /*@{*/
229 virtual void visit(ir_variable *);
230 virtual void visit(ir_loop *);
231 virtual void visit(ir_loop_jump *);
232 virtual void visit(ir_function_signature *);
233 virtual void visit(ir_function *);
234 virtual void visit(ir_expression *);
235 virtual void visit(ir_swizzle *);
236 virtual void visit(ir_dereference_variable *);
237 virtual void visit(ir_dereference_array *);
238 virtual void visit(ir_dereference_record *);
239 virtual void visit(ir_assignment *);
240 virtual void visit(ir_constant *);
241 virtual void visit(ir_call *);
242 virtual void visit(ir_return *);
243 virtual void visit(ir_discard *);
244 virtual void visit(ir_texture *);
245 virtual void visit(ir_if *);
246 virtual void visit(ir_emit_vertex *);
247 virtual void visit(ir_end_primitive *);
248 virtual void visit(ir_barrier *);
249 /*@}*/
250
251 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
252
253 void visit_atomic_counter_intrinsic(ir_call *);
254 void visit_ssbo_intrinsic(ir_call *);
255 void visit_membar_intrinsic(ir_call *);
256 void visit_shared_intrinsic(ir_call *);
257 void visit_image_intrinsic(ir_call *);
258 void visit_generic_intrinsic(ir_call *, unsigned op);
259
260 st_src_reg result;
261
262 /** List of variable_storage */
263 struct hash_table *variables;
264
265 /** List of immediate_storage */
266 exec_list immediates;
267 unsigned num_immediates;
268
269 /** List of glsl_to_tgsi_instruction */
270 exec_list instructions;
271
272 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
273 st_dst_reg dst = undef_dst,
274 st_src_reg src0 = undef_src,
275 st_src_reg src1 = undef_src,
276 st_src_reg src2 = undef_src,
277 st_src_reg src3 = undef_src);
278
279 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
280 st_dst_reg dst, st_dst_reg dst1,
281 st_src_reg src0 = undef_src,
282 st_src_reg src1 = undef_src,
283 st_src_reg src2 = undef_src,
284 st_src_reg src3 = undef_src);
285
286 unsigned get_opcode(unsigned op,
287 st_dst_reg dst,
288 st_src_reg src0, st_src_reg src1);
289
290 /**
291 * Emit the correct dot-product instruction for the type of arguments
292 */
293 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
294 st_dst_reg dst,
295 st_src_reg src0,
296 st_src_reg src1,
297 unsigned elements);
298
299 void emit_scalar(ir_instruction *ir, unsigned op,
300 st_dst_reg dst, st_src_reg src0);
301
302 void emit_scalar(ir_instruction *ir, unsigned op,
303 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
304
305 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
306
307 void get_deref_offsets(ir_dereference *ir,
308 unsigned *array_size,
309 unsigned *base,
310 uint16_t *index,
311 st_src_reg *reladdr,
312 bool opaque);
313 void calc_deref_offsets(ir_dereference *tail,
314 unsigned *array_elements,
315 uint16_t *index,
316 st_src_reg *indirect,
317 unsigned *location);
318 st_src_reg canonicalize_gather_offset(st_src_reg offset);
319
320 bool try_emit_mad(ir_expression *ir,
321 int mul_operand);
322 bool try_emit_mad_for_and_not(ir_expression *ir,
323 int mul_operand);
324
325 void emit_swz(ir_expression *ir);
326
327 bool process_move_condition(ir_rvalue *ir);
328
329 void simplify_cmp(void);
330
331 void rename_temp_registers(struct rename_reg_pair *renames);
332 void get_first_temp_read(int *first_reads);
333 void get_first_temp_write(int *first_writes);
334 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
335 void get_last_temp_write(int *last_writes);
336
337 void copy_propagate(void);
338 int eliminate_dead_code(void);
339
340 void merge_two_dsts(void);
341 void merge_registers(void);
342 void renumber_registers(void);
343
344 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
345 st_dst_reg *l, st_src_reg *r,
346 st_src_reg *cond, bool cond_swap);
347
348 void *mem_ctx;
349 };
350
351 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X, GLSL_TYPE_FLOAT, 0);
352 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X, GLSL_TYPE_FLOAT, 1);
353 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X, GLSL_TYPE_FLOAT, 2);
354
355 static void
356 fail_link(struct gl_shader_program *prog, const char *fmt, ...) PRINTFLIKE(2, 3);
357
358 static void
359 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
360 {
361 va_list args;
362 va_start(args, fmt);
363 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
364 va_end(args);
365
366 prog->data->LinkStatus = LINKING_FAILURE;
367 }
368
369 int
370 swizzle_for_size(int size)
371 {
372 static const int size_swizzles[4] = {
373 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
374 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
375 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
376 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
377 };
378
379 assert((size >= 1) && (size <= 4));
380 return size_swizzles[size - 1];
381 }
382
383
384 glsl_to_tgsi_instruction *
385 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
386 st_dst_reg dst, st_dst_reg dst1,
387 st_src_reg src0, st_src_reg src1,
388 st_src_reg src2, st_src_reg src3)
389 {
390 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
391 int num_reladdr = 0, i, j;
392 bool dst_is_64bit[2];
393
394 op = get_opcode(op, dst, src0, src1);
395
396 /* If we have to do relative addressing, we want to load the ARL
397 * reg directly for one of the regs, and preload the other reladdr
398 * sources into temps.
399 */
400 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
401 assert(!dst1.reladdr); /* should be lowered in earlier passes */
402 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
403 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
404 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
405 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
406
407 reladdr_to_temp(ir, &src3, &num_reladdr);
408 reladdr_to_temp(ir, &src2, &num_reladdr);
409 reladdr_to_temp(ir, &src1, &num_reladdr);
410 reladdr_to_temp(ir, &src0, &num_reladdr);
411
412 if (dst.reladdr || dst.reladdr2) {
413 if (dst.reladdr)
414 emit_arl(ir, address_reg, *dst.reladdr);
415 if (dst.reladdr2)
416 emit_arl(ir, address_reg2, *dst.reladdr2);
417 num_reladdr--;
418 }
419
420 assert(num_reladdr == 0);
421
422 /* inst->op has only 8 bits. */
423 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
424
425 inst->op = op;
426 inst->precise = this->precise;
427 inst->info = tgsi_get_opcode_info(op);
428 inst->dst[0] = dst;
429 inst->dst[1] = dst1;
430 inst->src[0] = src0;
431 inst->src[1] = src1;
432 inst->src[2] = src2;
433 inst->src[3] = src3;
434 inst->is_64bit_expanded = false;
435 inst->ir = ir;
436 inst->dead_mask = 0;
437 inst->tex_offsets = NULL;
438 inst->tex_offset_num_offset = 0;
439 inst->saturate = 0;
440 inst->tex_shadow = 0;
441 /* default to float, for paths where this is not initialized
442 * (since 0==UINT which is likely wrong):
443 */
444 inst->tex_type = GLSL_TYPE_FLOAT;
445
446 /* Update indirect addressing status used by TGSI */
447 if (dst.reladdr || dst.reladdr2) {
448 switch(dst.file) {
449 case PROGRAM_STATE_VAR:
450 case PROGRAM_CONSTANT:
451 case PROGRAM_UNIFORM:
452 this->indirect_addr_consts = true;
453 break;
454 case PROGRAM_IMMEDIATE:
455 assert(!"immediates should not have indirect addressing");
456 break;
457 default:
458 break;
459 }
460 }
461 else {
462 for (i = 0; i < 4; i++) {
463 if(inst->src[i].reladdr) {
464 switch(inst->src[i].file) {
465 case PROGRAM_STATE_VAR:
466 case PROGRAM_CONSTANT:
467 case PROGRAM_UNIFORM:
468 this->indirect_addr_consts = true;
469 break;
470 case PROGRAM_IMMEDIATE:
471 assert(!"immediates should not have indirect addressing");
472 break;
473 default:
474 break;
475 }
476 }
477 }
478 }
479
480 /*
481 * This section contains the double processing.
482 * GLSL just represents doubles as single channel values,
483 * however most HW and TGSI represent doubles as pairs of register channels.
484 *
485 * so we have to fixup destination writemask/index and src swizzle/indexes.
486 * dest writemasks need to translate from single channel write mask
487 * to a dual-channel writemask, but also need to modify the index,
488 * if we are touching the Z,W fields in the pre-translated writemask.
489 *
490 * src channels have similiar index modifications along with swizzle
491 * changes to we pick the XY, ZW pairs from the correct index.
492 *
493 * GLSL [0].x -> TGSI [0].xy
494 * GLSL [0].y -> TGSI [0].zw
495 * GLSL [0].z -> TGSI [1].xy
496 * GLSL [0].w -> TGSI [1].zw
497 */
498 for (j = 0; j < 2; j++) {
499 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
500 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT && inst->dst[j].type == GLSL_TYPE_ARRAY) {
501 enum glsl_base_type type = find_array_type(this->outputs, this->num_outputs, inst->dst[j].array_id);
502 if (glsl_base_type_is_64bit(type))
503 dst_is_64bit[j] = true;
504 }
505 }
506
507 if (dst_is_64bit[0] || dst_is_64bit[1] ||
508 glsl_base_type_is_64bit(inst->src[0].type)) {
509 glsl_to_tgsi_instruction *dinst = NULL;
510 int initial_src_swz[4], initial_src_idx[4];
511 int initial_dst_idx[2], initial_dst_writemask[2];
512 /* select the writemask for dst0 or dst1 */
513 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED ? inst->dst[0].writemask : inst->dst[1].writemask;
514
515 /* copy out the writemask, index and swizzles for all src/dsts. */
516 for (j = 0; j < 2; j++) {
517 initial_dst_writemask[j] = inst->dst[j].writemask;
518 initial_dst_idx[j] = inst->dst[j].index;
519 }
520
521 for (j = 0; j < 4; j++) {
522 initial_src_swz[j] = inst->src[j].swizzle;
523 initial_src_idx[j] = inst->src[j].index;
524 }
525
526 /*
527 * scan all the components in the dst writemask
528 * generate an instruction for each of them if required.
529 */
530 st_src_reg addr;
531 while (writemask) {
532
533 int i = u_bit_scan(&writemask);
534
535 /* before emitting the instruction, see if we have to adjust load / store
536 * address */
537 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD || inst->op == TGSI_OPCODE_STORE) &&
538 addr.file == PROGRAM_UNDEFINED) {
539 /* We have to advance the buffer address by 16 */
540 addr = get_temp(glsl_type::uint_type);
541 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
542 inst->src[0], st_src_reg_for_int(16));
543 }
544
545 /* first time use previous instruction */
546 if (dinst == NULL) {
547 dinst = inst;
548 } else {
549 /* create a new instructions for subsequent attempts */
550 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
551 *dinst = *inst;
552 dinst->next = NULL;
553 dinst->prev = NULL;
554 }
555 this->instructions.push_tail(dinst);
556 dinst->is_64bit_expanded = true;
557
558 /* modify the destination if we are splitting */
559 for (j = 0; j < 2; j++) {
560 if (dst_is_64bit[j]) {
561 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
562 dinst->dst[j].index = initial_dst_idx[j];
563 if (i > 1) {
564 if (dinst->op == TGSI_OPCODE_LOAD || dinst->op == TGSI_OPCODE_STORE)
565 dinst->src[0] = addr;
566 if (dinst->op != TGSI_OPCODE_STORE)
567 dinst->dst[j].index++;
568 }
569 } else {
570 /* if we aren't writing to a double, just get the bit of the initial writemask
571 for this channel */
572 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
573 }
574 }
575
576 /* modify the src registers */
577 for (j = 0; j < 4; j++) {
578 int swz = GET_SWZ(initial_src_swz[j], i);
579
580 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
581 dinst->src[j].index = initial_src_idx[j];
582 if (swz > 1) {
583 dinst->src[j].double_reg2 = true;
584 dinst->src[j].index++;
585 }
586
587 if (swz & 1)
588 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_Z, SWIZZLE_W);
589 else
590 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
591
592 } else {
593 /* some opcodes are special case in what they use as sources
594 - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
595 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D || op == TGSI_OPCODE_I2D ||
596 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
597 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
598 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
599 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
600 }
601 }
602 }
603 }
604 inst = dinst;
605 } else {
606 this->instructions.push_tail(inst);
607 }
608
609
610 return inst;
611 }
612
613 glsl_to_tgsi_instruction *
614 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
615 st_dst_reg dst,
616 st_src_reg src0, st_src_reg src1,
617 st_src_reg src2, st_src_reg src3)
618 {
619 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
620 }
621
622 /**
623 * Determines whether to use an integer, unsigned integer, or float opcode
624 * based on the operands and input opcode, then emits the result.
625 */
626 unsigned
627 glsl_to_tgsi_visitor::get_opcode(unsigned op,
628 st_dst_reg dst,
629 st_src_reg src0, st_src_reg src1)
630 {
631 enum glsl_base_type type = GLSL_TYPE_FLOAT;
632
633 if (op == TGSI_OPCODE_MOV)
634 return op;
635
636 assert(src0.type != GLSL_TYPE_ARRAY);
637 assert(src0.type != GLSL_TYPE_STRUCT);
638 assert(src1.type != GLSL_TYPE_ARRAY);
639 assert(src1.type != GLSL_TYPE_STRUCT);
640
641 if (is_resource_instruction(op))
642 type = src1.type;
643 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
644 type = GLSL_TYPE_INT64;
645 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
646 type = GLSL_TYPE_UINT64;
647 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
648 type = GLSL_TYPE_DOUBLE;
649 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
650 type = GLSL_TYPE_FLOAT;
651 else if (native_integers)
652 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
653
654 #define case7(c, f, i, u, d, i64, ui64) \
655 case TGSI_OPCODE_##c: \
656 if (type == GLSL_TYPE_UINT64) \
657 op = TGSI_OPCODE_##ui64; \
658 else if (type == GLSL_TYPE_INT64) \
659 op = TGSI_OPCODE_##i64; \
660 else if (type == GLSL_TYPE_DOUBLE) \
661 op = TGSI_OPCODE_##d; \
662 else if (type == GLSL_TYPE_INT) \
663 op = TGSI_OPCODE_##i; \
664 else if (type == GLSL_TYPE_UINT) \
665 op = TGSI_OPCODE_##u; \
666 else \
667 op = TGSI_OPCODE_##f; \
668 break;
669
670 #define casecomp(c, f, i, u, d, i64, ui64) \
671 case TGSI_OPCODE_##c: \
672 if (type == GLSL_TYPE_INT64) \
673 op = TGSI_OPCODE_##i64; \
674 else if (type == GLSL_TYPE_UINT64) \
675 op = TGSI_OPCODE_##ui64; \
676 else if (type == GLSL_TYPE_DOUBLE) \
677 op = TGSI_OPCODE_##d; \
678 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
679 op = TGSI_OPCODE_##i; \
680 else if (type == GLSL_TYPE_UINT) \
681 op = TGSI_OPCODE_##u; \
682 else if (native_integers) \
683 op = TGSI_OPCODE_##f; \
684 else \
685 op = TGSI_OPCODE_##c; \
686 break;
687
688 switch(op) {
689 /* Some instructions are initially selected without considering the type.
690 * This fixes the type:
691 *
692 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
693 */
694 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
695 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
696 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
697 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
698 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
699 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
700 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
701 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
702 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
703 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
704 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
705 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
706 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
707 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
708 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
709 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
710
711 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
712 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
713 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
714 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
715 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
716 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
717 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
718 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
719
720 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
721 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
722 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
723 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
724
725 default: break;
726 }
727
728 assert(op != TGSI_OPCODE_LAST);
729 return op;
730 }
731
732 glsl_to_tgsi_instruction *
733 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
734 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
735 unsigned elements)
736 {
737 static const unsigned dot_opcodes[] = {
738 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
739 };
740
741 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
742 }
743
744 /**
745 * Emits TGSI scalar opcodes to produce unique answers across channels.
746 *
747 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
748 * channel determines the result across all channels. So to do a vec4
749 * of this operation, we want to emit a scalar per source channel used
750 * to produce dest channels.
751 */
752 void
753 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
754 st_dst_reg dst,
755 st_src_reg orig_src0, st_src_reg orig_src1)
756 {
757 int i, j;
758 int done_mask = ~dst.writemask;
759
760 /* TGSI RCP is a scalar operation splatting results to all channels,
761 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
762 * dst channels.
763 */
764 for (i = 0; i < 4; i++) {
765 GLuint this_mask = (1 << i);
766 st_src_reg src0 = orig_src0;
767 st_src_reg src1 = orig_src1;
768
769 if (done_mask & this_mask)
770 continue;
771
772 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
773 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
774 for (j = i + 1; j < 4; j++) {
775 /* If there is another enabled component in the destination that is
776 * derived from the same inputs, generate its value on this pass as
777 * well.
778 */
779 if (!(done_mask & (1 << j)) &&
780 GET_SWZ(src0.swizzle, j) == src0_swiz &&
781 GET_SWZ(src1.swizzle, j) == src1_swiz) {
782 this_mask |= (1 << j);
783 }
784 }
785 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
786 src0_swiz, src0_swiz);
787 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
788 src1_swiz, src1_swiz);
789
790 dst.writemask = this_mask;
791 emit_asm(ir, op, dst, src0, src1);
792 done_mask |= this_mask;
793 }
794 }
795
796 void
797 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
798 st_dst_reg dst, st_src_reg src0)
799 {
800 st_src_reg undef = undef_src;
801
802 undef.swizzle = SWIZZLE_XXXX;
803
804 emit_scalar(ir, op, dst, src0, undef);
805 }
806
807 void
808 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
809 st_dst_reg dst, st_src_reg src0)
810 {
811 int op = TGSI_OPCODE_ARL;
812
813 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
814 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
815 return;
816
817 op = TGSI_OPCODE_UARL;
818 }
819
820 assert(dst.file == PROGRAM_ADDRESS);
821 if (dst.index >= this->num_address_regs)
822 this->num_address_regs = dst.index + 1;
823
824 emit_asm(NULL, op, dst, src0);
825 }
826
827 int
828 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
829 gl_constant_value values[8], int size,
830 GLenum datatype,
831 uint16_t *swizzle_out)
832 {
833 if (file == PROGRAM_CONSTANT) {
834 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
835 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters, values,
836 size, datatype, &swizzle);
837 if (swizzle_out)
838 *swizzle_out = swizzle;
839 return result;
840 }
841
842 assert(file == PROGRAM_IMMEDIATE);
843
844 int index = 0;
845 immediate_storage *entry;
846 int size32 = size * ((datatype == GL_DOUBLE ||
847 datatype == GL_INT64_ARB ||
848 datatype == GL_UNSIGNED_INT64_ARB)? 2 : 1);
849 int i;
850
851 /* Search immediate storage to see if we already have an identical
852 * immediate that we can use instead of adding a duplicate entry.
853 */
854 foreach_in_list(immediate_storage, entry, &this->immediates) {
855 immediate_storage *tmp = entry;
856
857 for (i = 0; i * 4 < size32; i++) {
858 int slot_size = MIN2(size32 - (i * 4), 4);
859 if (tmp->type != datatype || tmp->size32 != slot_size)
860 break;
861 if (memcmp(tmp->values, &values[i * 4],
862 slot_size * sizeof(gl_constant_value)))
863 break;
864
865 /* Everything matches, keep going until the full size is matched */
866 tmp = (immediate_storage *)tmp->next;
867 }
868
869 /* The full value matched */
870 if (i * 4 >= size32)
871 return index;
872
873 index++;
874 }
875
876 for (i = 0; i * 4 < size32; i++) {
877 int slot_size = MIN2(size32 - (i * 4), 4);
878 /* Add this immediate to the list. */
879 entry = new(mem_ctx) immediate_storage(&values[i * 4], slot_size, datatype);
880 this->immediates.push_tail(entry);
881 this->num_immediates++;
882 }
883 return index;
884 }
885
886 st_src_reg
887 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
888 {
889 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
890 union gl_constant_value uval;
891
892 uval.f = val;
893 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
894
895 return src;
896 }
897
898 st_src_reg
899 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
900 {
901 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
902 union gl_constant_value uval[2];
903
904 memcpy(uval, &val, sizeof(uval));
905 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
906 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
907 return src;
908 }
909
910 st_src_reg
911 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
912 {
913 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
914 union gl_constant_value uval;
915
916 assert(native_integers);
917
918 uval.i = val;
919 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
920
921 return src;
922 }
923
924 st_src_reg
925 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
926 {
927 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
928 union gl_constant_value uval[2];
929
930 memcpy(uval, &val, sizeof(uval));
931 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
932 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
933
934 return src;
935 }
936
937 st_src_reg
938 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
939 {
940 if (native_integers)
941 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
942 st_src_reg_for_int(val);
943 else
944 return st_src_reg_for_float(val);
945 }
946
947 static int
948 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
949 {
950 return type->count_attribute_slots(is_vs_input);
951 }
952
953 static int
954 type_size(const struct glsl_type *type)
955 {
956 return type->count_attribute_slots(false);
957 }
958
959 static void
960 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
961 exec_list *instructions, ir_constant *access)
962 {
963 /**
964 * emit_asm() might have actually split the op into pieces, e.g. for
965 * double stores. We have to go back and fix up all the generated ops.
966 */
967 unsigned op = inst->op;
968 do {
969 inst->resource = *buf;
970 if (access)
971 inst->buffer_access = access->value.u[0];
972
973 if (inst == instructions->get_head_raw())
974 break;
975 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
976
977 if (inst->op == TGSI_OPCODE_UADD) {
978 if (inst == instructions->get_head_raw())
979 break;
980 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
981 }
982 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
983 }
984
985 /**
986 * If the given GLSL type is an array or matrix or a structure containing
987 * an array/matrix member, return true. Else return false.
988 *
989 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
990 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
991 * we have an array that might be indexed with a variable, we need to use
992 * the later storage type.
993 */
994 static bool
995 type_has_array_or_matrix(const glsl_type *type)
996 {
997 if (type->is_array() || type->is_matrix())
998 return true;
999
1000 if (type->is_record()) {
1001 for (unsigned i = 0; i < type->length; i++) {
1002 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1003 return true;
1004 }
1005 }
1006 }
1007
1008 return false;
1009 }
1010
1011
1012 /**
1013 * In the initial pass of codegen, we assign temporary numbers to
1014 * intermediate results. (not SSA -- variable assignments will reuse
1015 * storage).
1016 */
1017 st_src_reg
1018 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1019 {
1020 st_src_reg src;
1021
1022 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1023 src.reladdr = NULL;
1024 src.negate = 0;
1025 src.abs = 0;
1026
1027 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1028 if (next_array >= max_num_arrays) {
1029 max_num_arrays += 32;
1030 array_sizes = (unsigned*)
1031 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1032 }
1033
1034 src.file = PROGRAM_ARRAY;
1035 src.index = 0;
1036 src.array_id = next_array + 1;
1037 array_sizes[next_array] = type_size(type);
1038 ++next_array;
1039
1040 } else {
1041 src.file = PROGRAM_TEMPORARY;
1042 src.index = next_temp;
1043 next_temp += type_size(type);
1044 }
1045
1046 if (type->is_array() || type->is_record()) {
1047 src.swizzle = SWIZZLE_NOOP;
1048 } else {
1049 src.swizzle = swizzle_for_size(type->vector_elements);
1050 }
1051
1052 return src;
1053 }
1054
1055 variable_storage *
1056 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1057 {
1058 struct hash_entry *entry;
1059
1060 entry = _mesa_hash_table_search(this->variables, var);
1061 if (!entry)
1062 return NULL;
1063
1064 return (variable_storage *)entry->data;
1065 }
1066
1067 void
1068 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1069 {
1070 if (strcmp(ir->name, "gl_FragCoord") == 0) {
1071 this->prog->OriginUpperLeft = ir->data.origin_upper_left;
1072 this->prog->PixelCenterInteger = ir->data.pixel_center_integer;
1073 }
1074
1075 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1076 unsigned int i;
1077 const ir_state_slot *const slots = ir->get_state_slots();
1078 assert(slots != NULL);
1079
1080 /* Check if this statevar's setup in the STATE file exactly
1081 * matches how we'll want to reference it as a
1082 * struct/array/whatever. If not, then we need to move it into
1083 * temporary storage and hope that it'll get copy-propagated
1084 * out.
1085 */
1086 for (i = 0; i < ir->get_num_state_slots(); i++) {
1087 if (slots[i].swizzle != SWIZZLE_XYZW) {
1088 break;
1089 }
1090 }
1091
1092 variable_storage *storage;
1093 st_dst_reg dst;
1094 if (i == ir->get_num_state_slots()) {
1095 /* We'll set the index later. */
1096 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1097
1098 _mesa_hash_table_insert(this->variables, ir, storage);
1099
1100 dst = undef_dst;
1101 } else {
1102 /* The variable_storage constructor allocates slots based on the size
1103 * of the type. However, this had better match the number of state
1104 * elements that we're going to copy into the new temporary.
1105 */
1106 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1107
1108 dst = st_dst_reg(get_temp(ir->type));
1109
1110 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1111 dst.array_id);
1112
1113 _mesa_hash_table_insert(this->variables, ir, storage);
1114 }
1115
1116
1117 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1118 int index = _mesa_add_state_reference(this->prog->Parameters,
1119 (gl_state_index *)slots[i].tokens);
1120
1121 if (storage->file == PROGRAM_STATE_VAR) {
1122 if (storage->index == -1) {
1123 storage->index = index;
1124 } else {
1125 assert(index == storage->index + (int)i);
1126 }
1127 } else {
1128 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1129 * the data being moved since MOV does not care about the type of
1130 * data it is moving, and we don't want to declare registers with
1131 * array or struct types.
1132 */
1133 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1134 src.swizzle = slots[i].swizzle;
1135 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1136 /* even a float takes up a whole vec4 reg in a struct/array. */
1137 dst.index++;
1138 }
1139 }
1140
1141 if (storage->file == PROGRAM_TEMPORARY &&
1142 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1143 fail_link(this->shader_program,
1144 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1145 ir->name, dst.index - storage->index,
1146 type_size(ir->type));
1147 }
1148 }
1149 }
1150
1151 void
1152 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1153 {
1154 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1155
1156 visit_exec_list(&ir->body_instructions, this);
1157
1158 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1159 }
1160
1161 void
1162 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1163 {
1164 switch (ir->mode) {
1165 case ir_loop_jump::jump_break:
1166 emit_asm(NULL, TGSI_OPCODE_BRK);
1167 break;
1168 case ir_loop_jump::jump_continue:
1169 emit_asm(NULL, TGSI_OPCODE_CONT);
1170 break;
1171 }
1172 }
1173
1174
1175 void
1176 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1177 {
1178 assert(0);
1179 (void)ir;
1180 }
1181
1182 void
1183 glsl_to_tgsi_visitor::visit(ir_function *ir)
1184 {
1185 /* Ignore function bodies other than main() -- we shouldn't see calls to
1186 * them since they should all be inlined before we get to glsl_to_tgsi.
1187 */
1188 if (strcmp(ir->name, "main") == 0) {
1189 const ir_function_signature *sig;
1190 exec_list empty;
1191
1192 sig = ir->matching_signature(NULL, &empty, false);
1193
1194 assert(sig);
1195
1196 foreach_in_list(ir_instruction, ir, &sig->body) {
1197 ir->accept(this);
1198 }
1199 }
1200 }
1201
1202 bool
1203 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1204 {
1205 int nonmul_operand = 1 - mul_operand;
1206 st_src_reg a, b, c;
1207 st_dst_reg result_dst;
1208
1209 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1210 if (!expr || expr->operation != ir_binop_mul)
1211 return false;
1212
1213 expr->operands[0]->accept(this);
1214 a = this->result;
1215 expr->operands[1]->accept(this);
1216 b = this->result;
1217 ir->operands[nonmul_operand]->accept(this);
1218 c = this->result;
1219
1220 this->result = get_temp(ir->type);
1221 result_dst = st_dst_reg(this->result);
1222 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1223 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1224
1225 return true;
1226 }
1227
1228 /**
1229 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1230 *
1231 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1232 * implemented using multiplication, and logical-or is implemented using
1233 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1234 * As result, the logical expression (a & !b) can be rewritten as:
1235 *
1236 * - a * !b
1237 * - a * (1 - b)
1238 * - (a * 1) - (a * b)
1239 * - a + -(a * b)
1240 * - a + (a * -b)
1241 *
1242 * This final expression can be implemented as a single MAD(a, -b, a)
1243 * instruction.
1244 */
1245 bool
1246 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir, int try_operand)
1247 {
1248 const int other_operand = 1 - try_operand;
1249 st_src_reg a, b;
1250
1251 ir_expression *expr = ir->operands[try_operand]->as_expression();
1252 if (!expr || expr->operation != ir_unop_logic_not)
1253 return false;
1254
1255 ir->operands[other_operand]->accept(this);
1256 a = this->result;
1257 expr->operands[0]->accept(this);
1258 b = this->result;
1259
1260 b.negate = ~b.negate;
1261
1262 this->result = get_temp(ir->type);
1263 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1264
1265 return true;
1266 }
1267
1268 void
1269 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1270 st_src_reg *reg, int *num_reladdr)
1271 {
1272 if (!reg->reladdr && !reg->reladdr2)
1273 return;
1274
1275 if (reg->reladdr) emit_arl(ir, address_reg, *reg->reladdr);
1276 if (reg->reladdr2) emit_arl(ir, address_reg2, *reg->reladdr2);
1277
1278 if (*num_reladdr != 1) {
1279 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1280
1281 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1282 *reg = temp;
1283 }
1284
1285 (*num_reladdr)--;
1286 }
1287
1288 void
1289 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1290 {
1291 st_src_reg op[ARRAY_SIZE(ir->operands)];
1292
1293 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1294 */
1295 if (!this->precise && ir->operation == ir_binop_add) {
1296 if (try_emit_mad(ir, 1))
1297 return;
1298 if (try_emit_mad(ir, 0))
1299 return;
1300 }
1301
1302 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1303 */
1304 if (!native_integers && ir->operation == ir_binop_logic_and) {
1305 if (try_emit_mad_for_and_not(ir, 1))
1306 return;
1307 if (try_emit_mad_for_and_not(ir, 0))
1308 return;
1309 }
1310
1311 if (ir->operation == ir_quadop_vector)
1312 assert(!"ir_quadop_vector should have been lowered");
1313
1314 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1315 this->result.file = PROGRAM_UNDEFINED;
1316 ir->operands[operand]->accept(this);
1317 if (this->result.file == PROGRAM_UNDEFINED) {
1318 printf("Failed to get tree for expression operand:\n");
1319 ir->operands[operand]->print();
1320 printf("\n");
1321 exit(1);
1322 }
1323 op[operand] = this->result;
1324
1325 /* Matrix expression operands should have been broken down to vector
1326 * operations already.
1327 */
1328 assert(!ir->operands[operand]->type->is_matrix());
1329 }
1330
1331 visit_expression(ir, op);
1332 }
1333
1334 /* The non-recursive part of the expression visitor lives in a separate
1335 * function and should be prevented from being inlined, to avoid a stack
1336 * explosion when deeply nested expressions are visited.
1337 */
1338 void
1339 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1340 {
1341 st_src_reg result_src;
1342 st_dst_reg result_dst;
1343
1344 int vector_elements = ir->operands[0]->type->vector_elements;
1345 if (ir->operands[1] &&
1346 ir->operation != ir_binop_interpolate_at_offset &&
1347 ir->operation != ir_binop_interpolate_at_sample) {
1348 st_src_reg *swz_op = NULL;
1349 if (vector_elements > ir->operands[1]->type->vector_elements) {
1350 assert(ir->operands[1]->type->vector_elements == 1);
1351 swz_op = &op[1];
1352 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1353 assert(ir->operands[0]->type->vector_elements == 1);
1354 swz_op = &op[0];
1355 }
1356 if (swz_op) {
1357 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1358 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1359 swizzle_x, swizzle_x);
1360 }
1361 vector_elements = MAX2(vector_elements,
1362 ir->operands[1]->type->vector_elements);
1363 }
1364 if (ir->operands[2] &&
1365 ir->operands[2]->type->vector_elements != vector_elements) {
1366 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1367 assert(ir->operands[2]->type->vector_elements == 1);
1368 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1369 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1370 swizzle_x, swizzle_x);
1371 }
1372
1373 this->result.file = PROGRAM_UNDEFINED;
1374
1375 /* Storage for our result. Ideally for an assignment we'd be using
1376 * the actual storage for the result here, instead.
1377 */
1378 result_src = get_temp(ir->type);
1379 /* convenience for the emit functions below. */
1380 result_dst = st_dst_reg(result_src);
1381 /* Limit writes to the channels that will be used by result_src later.
1382 * This does limit this temp's use as a temporary for multi-instruction
1383 * sequences.
1384 */
1385 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1386
1387 switch (ir->operation) {
1388 case ir_unop_logic_not:
1389 if (result_dst.type != GLSL_TYPE_FLOAT)
1390 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1391 else {
1392 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1393 * older GPUs implement SEQ using multiple instructions (i915 uses two
1394 * SGE instructions and a MUL instruction). Since our logic values are
1395 * 0.0 and 1.0, 1-x also implements !x.
1396 */
1397 op[0].negate = ~op[0].negate;
1398 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], st_src_reg_for_float(1.0));
1399 }
1400 break;
1401 case ir_unop_neg:
1402 if (result_dst.type == GLSL_TYPE_INT64 || result_dst.type == GLSL_TYPE_UINT64)
1403 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1404 else if (result_dst.type == GLSL_TYPE_INT || result_dst.type == GLSL_TYPE_UINT)
1405 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1406 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1407 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1408 else {
1409 op[0].negate = ~op[0].negate;
1410 result_src = op[0];
1411 }
1412 break;
1413 case ir_unop_subroutine_to_int:
1414 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1415 break;
1416 case ir_unop_abs:
1417 if (result_dst.type == GLSL_TYPE_FLOAT)
1418 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1419 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1420 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1421 else if (result_dst.type == GLSL_TYPE_INT64 || result_dst.type == GLSL_TYPE_UINT64)
1422 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1423 else
1424 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1425 break;
1426 case ir_unop_sign:
1427 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1428 break;
1429 case ir_unop_rcp:
1430 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1431 break;
1432
1433 case ir_unop_exp2:
1434 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1435 break;
1436 case ir_unop_exp:
1437 assert(!"not reached: should be handled by exp_to_exp2");
1438 break;
1439 case ir_unop_log:
1440 assert(!"not reached: should be handled by log_to_log2");
1441 break;
1442 case ir_unop_log2:
1443 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1444 break;
1445 case ir_unop_sin:
1446 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1447 break;
1448 case ir_unop_cos:
1449 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1450 break;
1451 case ir_unop_saturate: {
1452 glsl_to_tgsi_instruction *inst;
1453 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1454 inst->saturate = true;
1455 break;
1456 }
1457
1458 case ir_unop_dFdx:
1459 case ir_unop_dFdx_coarse:
1460 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1461 break;
1462 case ir_unop_dFdx_fine:
1463 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1464 break;
1465 case ir_unop_dFdy:
1466 case ir_unop_dFdy_coarse:
1467 case ir_unop_dFdy_fine:
1468 {
1469 /* The X component contains 1 or -1 depending on whether the framebuffer
1470 * is a FBO or the window system buffer, respectively.
1471 * It is then multiplied with the source operand of DDY.
1472 */
1473 static const gl_state_index transform_y_state[STATE_LENGTH]
1474 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1475
1476 unsigned transform_y_index =
1477 _mesa_add_state_reference(this->prog->Parameters,
1478 transform_y_state);
1479
1480 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1481 transform_y_index,
1482 glsl_type::vec4_type);
1483 transform_y.swizzle = SWIZZLE_XXXX;
1484
1485 st_src_reg temp = get_temp(glsl_type::vec4_type);
1486
1487 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1488 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1489 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1490 break;
1491 }
1492
1493 case ir_unop_frexp_sig:
1494 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1495 break;
1496
1497 case ir_unop_frexp_exp:
1498 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1499 break;
1500
1501 case ir_unop_noise: {
1502 /* At some point, a motivated person could add a better
1503 * implementation of noise. Currently not even the nvidia
1504 * binary drivers do anything more than this. In any case, the
1505 * place to do this is in the GL state tracker, not the poor
1506 * driver.
1507 */
1508 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1509 break;
1510 }
1511
1512 case ir_binop_add:
1513 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1514 break;
1515 case ir_binop_sub:
1516 op[1].negate = ~op[1].negate;
1517 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1518 break;
1519
1520 case ir_binop_mul:
1521 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1522 break;
1523 case ir_binop_div:
1524 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1525 break;
1526 case ir_binop_mod:
1527 if (result_dst.type == GLSL_TYPE_FLOAT)
1528 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1529 else
1530 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1531 break;
1532
1533 case ir_binop_less:
1534 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1535 break;
1536 case ir_binop_gequal:
1537 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1538 break;
1539 case ir_binop_equal:
1540 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1541 break;
1542 case ir_binop_nequal:
1543 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1544 break;
1545 case ir_binop_all_equal:
1546 /* "==" operator producing a scalar boolean. */
1547 if (ir->operands[0]->type->is_vector() ||
1548 ir->operands[1]->type->is_vector()) {
1549 st_src_reg temp = get_temp(native_integers ?
1550 glsl_type::uvec4_type :
1551 glsl_type::vec4_type);
1552
1553 if (native_integers) {
1554 st_dst_reg temp_dst = st_dst_reg(temp);
1555 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1556
1557 if (ir->operands[0]->type->is_boolean() &&
1558 ir->operands[1]->as_constant() &&
1559 ir->operands[1]->as_constant()->is_one()) {
1560 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1561 } else {
1562 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1563 }
1564
1565 /* Emit 1-3 AND operations to combine the SEQ results. */
1566 switch (ir->operands[0]->type->vector_elements) {
1567 case 2:
1568 break;
1569 case 3:
1570 temp_dst.writemask = WRITEMASK_Y;
1571 temp1.swizzle = SWIZZLE_YYYY;
1572 temp2.swizzle = SWIZZLE_ZZZZ;
1573 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1574 break;
1575 case 4:
1576 temp_dst.writemask = WRITEMASK_X;
1577 temp1.swizzle = SWIZZLE_XXXX;
1578 temp2.swizzle = SWIZZLE_YYYY;
1579 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1580 temp_dst.writemask = WRITEMASK_Y;
1581 temp1.swizzle = SWIZZLE_ZZZZ;
1582 temp2.swizzle = SWIZZLE_WWWW;
1583 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1584 }
1585
1586 temp1.swizzle = SWIZZLE_XXXX;
1587 temp2.swizzle = SWIZZLE_YYYY;
1588 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1589 } else {
1590 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1591
1592 /* After the dot-product, the value will be an integer on the
1593 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1594 */
1595 emit_dp(ir, result_dst, temp, temp, vector_elements);
1596
1597 /* Negating the result of the dot-product gives values on the range
1598 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1599 * This is achieved using SGE.
1600 */
1601 st_src_reg sge_src = result_src;
1602 sge_src.negate = ~sge_src.negate;
1603 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src, st_src_reg_for_float(0.0));
1604 }
1605 } else {
1606 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1607 }
1608 break;
1609 case ir_binop_any_nequal:
1610 /* "!=" operator producing a scalar boolean. */
1611 if (ir->operands[0]->type->is_vector() ||
1612 ir->operands[1]->type->is_vector()) {
1613 st_src_reg temp = get_temp(native_integers ?
1614 glsl_type::uvec4_type :
1615 glsl_type::vec4_type);
1616 if (ir->operands[0]->type->is_boolean() &&
1617 ir->operands[1]->as_constant() &&
1618 ir->operands[1]->as_constant()->is_zero()) {
1619 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1620 } else {
1621 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1622 }
1623
1624 if (native_integers) {
1625 st_dst_reg temp_dst = st_dst_reg(temp);
1626 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1627
1628 /* Emit 1-3 OR operations to combine the SNE results. */
1629 switch (ir->operands[0]->type->vector_elements) {
1630 case 2:
1631 break;
1632 case 3:
1633 temp_dst.writemask = WRITEMASK_Y;
1634 temp1.swizzle = SWIZZLE_YYYY;
1635 temp2.swizzle = SWIZZLE_ZZZZ;
1636 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1637 break;
1638 case 4:
1639 temp_dst.writemask = WRITEMASK_X;
1640 temp1.swizzle = SWIZZLE_XXXX;
1641 temp2.swizzle = SWIZZLE_YYYY;
1642 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_ZZZZ;
1645 temp2.swizzle = SWIZZLE_WWWW;
1646 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1647 }
1648
1649 temp1.swizzle = SWIZZLE_XXXX;
1650 temp2.swizzle = SWIZZLE_YYYY;
1651 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1652 } else {
1653 /* After the dot-product, the value will be an integer on the
1654 * range [0,4]. Zero stays zero, and positive values become 1.0.
1655 */
1656 glsl_to_tgsi_instruction *const dp =
1657 emit_dp(ir, result_dst, temp, temp, vector_elements);
1658 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1659 /* The clamping to [0,1] can be done for free in the fragment
1660 * shader with a saturate.
1661 */
1662 dp->saturate = true;
1663 } else {
1664 /* Negating the result of the dot-product gives values on the range
1665 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1666 * achieved using SLT.
1667 */
1668 st_src_reg slt_src = result_src;
1669 slt_src.negate = ~slt_src.negate;
1670 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
1671 }
1672 }
1673 } else {
1674 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1675 }
1676 break;
1677
1678 case ir_binop_logic_xor:
1679 if (native_integers)
1680 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1681 else
1682 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1683 break;
1684
1685 case ir_binop_logic_or: {
1686 if (native_integers) {
1687 /* If integers are used as booleans, we can use an actual "or"
1688 * instruction.
1689 */
1690 assert(native_integers);
1691 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1692 } else {
1693 /* After the addition, the value will be an integer on the
1694 * range [0,2]. Zero stays zero, and positive values become 1.0.
1695 */
1696 glsl_to_tgsi_instruction *add =
1697 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1698 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1699 /* The clamping to [0,1] can be done for free in the fragment
1700 * shader with a saturate if floats are being used as boolean values.
1701 */
1702 add->saturate = true;
1703 } else {
1704 /* Negating the result of the addition gives values on the range
1705 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1706 * is achieved using SLT.
1707 */
1708 st_src_reg slt_src = result_src;
1709 slt_src.negate = ~slt_src.negate;
1710 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
1711 }
1712 }
1713 break;
1714 }
1715
1716 case ir_binop_logic_and:
1717 /* If native integers are disabled, the bool args are stored as float 0.0
1718 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1719 * actual AND opcode.
1720 */
1721 if (native_integers)
1722 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1723 else
1724 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1725 break;
1726
1727 case ir_binop_dot:
1728 assert(ir->operands[0]->type->is_vector());
1729 assert(ir->operands[0]->type == ir->operands[1]->type);
1730 emit_dp(ir, result_dst, op[0], op[1],
1731 ir->operands[0]->type->vector_elements);
1732 break;
1733
1734 case ir_unop_sqrt:
1735 if (have_sqrt) {
1736 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1737 } else {
1738 /* This is the only instruction sequence that makes the game "Risen"
1739 * render correctly. ABS is not required for the game, but since GLSL
1740 * declares negative values as "undefined", allowing us to do whatever
1741 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1742 * behavior.
1743 */
1744 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1745 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1746 }
1747 break;
1748 case ir_unop_rsq:
1749 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1750 break;
1751 case ir_unop_i2f:
1752 if (native_integers) {
1753 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1754 break;
1755 }
1756 /* fallthrough to next case otherwise */
1757 case ir_unop_b2f:
1758 if (native_integers) {
1759 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_float(1.0));
1760 break;
1761 }
1762 /* fallthrough to next case otherwise */
1763 case ir_unop_i2u:
1764 case ir_unop_u2i:
1765 case ir_unop_i642u64:
1766 case ir_unop_u642i64:
1767 /* Converting between signed and unsigned integers is a no-op. */
1768 result_src = op[0];
1769 result_src.type = result_dst.type;
1770 break;
1771 case ir_unop_b2i:
1772 if (native_integers) {
1773 /* Booleans are stored as integers using ~0 for true and 0 for false.
1774 * GLSL requires that int(bool) return 1 for true and 0 for false.
1775 * This conversion is done with AND, but it could be done with NEG.
1776 */
1777 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_int(1));
1778 } else {
1779 /* Booleans and integers are both stored as floats when native
1780 * integers are disabled.
1781 */
1782 result_src = op[0];
1783 }
1784 break;
1785 case ir_unop_f2i:
1786 if (native_integers)
1787 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1788 else
1789 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1790 break;
1791 case ir_unop_f2u:
1792 if (native_integers)
1793 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1794 else
1795 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1796 break;
1797 case ir_unop_bitcast_f2i:
1798 case ir_unop_bitcast_f2u:
1799 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1800 if (op[0].negate || op[0].abs)
1801 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1802 else
1803 result_src = op[0];
1804 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1805 GLSL_TYPE_UINT;
1806 break;
1807 case ir_unop_bitcast_i2f:
1808 case ir_unop_bitcast_u2f:
1809 result_src = op[0];
1810 result_src.type = GLSL_TYPE_FLOAT;
1811 break;
1812 case ir_unop_f2b:
1813 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
1814 break;
1815 case ir_unop_d2b:
1816 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_double(0.0));
1817 break;
1818 case ir_unop_i2b:
1819 if (native_integers)
1820 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0], st_src_reg_for_int(0));
1821 else
1822 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
1823 break;
1824 case ir_unop_bitcast_u642d:
1825 case ir_unop_bitcast_i642d:
1826 result_src = op[0];
1827 result_src.type = GLSL_TYPE_DOUBLE;
1828 break;
1829 case ir_unop_bitcast_d2i64:
1830 result_src = op[0];
1831 result_src.type = GLSL_TYPE_INT64;
1832 break;
1833 case ir_unop_bitcast_d2u64:
1834 result_src = op[0];
1835 result_src.type = GLSL_TYPE_UINT64;
1836 break;
1837 case ir_unop_trunc:
1838 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1839 break;
1840 case ir_unop_ceil:
1841 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1842 break;
1843 case ir_unop_floor:
1844 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1845 break;
1846 case ir_unop_round_even:
1847 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1848 break;
1849 case ir_unop_fract:
1850 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1851 break;
1852
1853 case ir_binop_min:
1854 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1855 break;
1856 case ir_binop_max:
1857 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1858 break;
1859 case ir_binop_pow:
1860 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1861 break;
1862
1863 case ir_unop_bit_not:
1864 if (native_integers) {
1865 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1866 break;
1867 }
1868 case ir_unop_u2f:
1869 if (native_integers) {
1870 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1871 break;
1872 }
1873 case ir_binop_lshift:
1874 case ir_binop_rshift:
1875 if (native_integers) {
1876 unsigned opcode = ir->operation == ir_binop_lshift ? TGSI_OPCODE_SHL
1877 : TGSI_OPCODE_ISHR;
1878 st_src_reg count;
1879
1880 if (glsl_base_type_is_64bit(op[0].type)) {
1881 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1882 * 64 bits.
1883 */
1884 count = get_temp(glsl_type::u64vec(ir->operands[1]->type->components()));
1885 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1886 } else {
1887 count = op[1];
1888 }
1889
1890 emit_asm(ir, opcode, result_dst, op[0], count);
1891 break;
1892 }
1893 case ir_binop_bit_and:
1894 if (native_integers) {
1895 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1896 break;
1897 }
1898 case ir_binop_bit_xor:
1899 if (native_integers) {
1900 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1901 break;
1902 }
1903 case ir_binop_bit_or:
1904 if (native_integers) {
1905 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1906 break;
1907 }
1908
1909 assert(!"GLSL 1.30 features unsupported");
1910 break;
1911
1912 case ir_binop_ubo_load: {
1913 if (ctx->Const.UseSTD430AsDefaultPacking) {
1914 ir_rvalue *block = ir->operands[0];
1915 ir_rvalue *offset = ir->operands[1];
1916 ir_constant *const_block = block->as_constant();
1917
1918 st_src_reg cbuf(PROGRAM_CONSTANT,
1919 (const_block ? const_block->value.u[0] + 1 : 1),
1920 ir->type->base_type);
1921
1922 cbuf.has_index2 = true;
1923
1924 if (!const_block) {
1925 block->accept(this);
1926 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
1927 *cbuf.reladdr = this->result;
1928 emit_arl(ir, sampler_reladdr, this->result);
1929 }
1930
1931 /* Calculate the surface offset */
1932 offset->accept(this);
1933 st_src_reg off = this->result;
1934
1935 glsl_to_tgsi_instruction *inst =
1936 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
1937
1938 if (result_dst.type == GLSL_TYPE_BOOL)
1939 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
1940 st_src_reg_for_int(0));
1941
1942 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
1943 NULL);
1944 } else {
1945 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
1946 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
1947 unsigned const_offset = const_offset_ir ?
1948 const_offset_ir->value.u[0] : 0;
1949 unsigned const_block = const_uniform_block ?
1950 const_uniform_block->value.u[0] + 1 : 1;
1951 st_src_reg index_reg = get_temp(glsl_type::uint_type);
1952 st_src_reg cbuf;
1953
1954 cbuf.type = ir->type->base_type;
1955 cbuf.file = PROGRAM_CONSTANT;
1956 cbuf.index = 0;
1957 cbuf.reladdr = NULL;
1958 cbuf.negate = 0;
1959 cbuf.abs = 0;
1960 cbuf.index2D = const_block;
1961
1962 assert(ir->type->is_vector() || ir->type->is_scalar());
1963
1964 if (const_offset_ir) {
1965 /* Constant index into constant buffer */
1966 cbuf.reladdr = NULL;
1967 cbuf.index = const_offset / 16;
1968 } else {
1969 ir_expression *offset_expr = ir->operands[1]->as_expression();
1970 st_src_reg offset = op[1];
1971
1972 /* The OpenGL spec is written in such a way that accesses with
1973 * non-constant offset are almost always vec4-aligned. The only
1974 * exception to this are members of structs in arrays of structs:
1975 * each struct in an array of structs is at least vec4-aligned,
1976 * but single-element and [ui]vec2 members of the struct may be at
1977 * an offset that is not a multiple of 16 bytes.
1978 *
1979 * Here, we extract that offset, relying on previous passes to
1980 * always generate offset expressions of the form
1981 * (+ expr constant_offset).
1982 *
1983 * Note that the std430 layout, which allows more cases of
1984 * alignment less than vec4 in arrays, is not supported for
1985 * uniform blocks, so we do not have to deal with it here.
1986 */
1987 if (offset_expr && offset_expr->operation == ir_binop_add) {
1988 const_offset_ir = offset_expr->operands[1]->as_constant();
1989 if (const_offset_ir) {
1990 const_offset = const_offset_ir->value.u[0];
1991 cbuf.index = const_offset / 16;
1992 offset_expr->operands[0]->accept(this);
1993 offset = this->result;
1994 }
1995 }
1996
1997 /* Relative/variable index into constant buffer */
1998 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
1999 st_src_reg_for_int(4));
2000 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2001 memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
2002 }
2003
2004 if (const_uniform_block) {
2005 /* Constant constant buffer */
2006 cbuf.reladdr2 = NULL;
2007 } else {
2008 /* Relative/variable constant buffer */
2009 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2010 memcpy(cbuf.reladdr2, &op[0], sizeof(st_src_reg));
2011 }
2012 cbuf.has_index2 = true;
2013
2014 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2015 if (glsl_base_type_is_64bit(cbuf.type))
2016 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2017 const_offset % 16 / 8,
2018 const_offset % 16 / 8,
2019 const_offset % 16 / 8);
2020 else
2021 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2022 const_offset % 16 / 4,
2023 const_offset % 16 / 4,
2024 const_offset % 16 / 4);
2025
2026 if (ir->type->is_boolean()) {
2027 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2028 st_src_reg_for_int(0));
2029 } else {
2030 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2031 }
2032 }
2033 break;
2034 }
2035 case ir_triop_lrp:
2036 /* note: we have to reorder the three args here */
2037 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2038 break;
2039 case ir_triop_csel:
2040 if (this->ctx->Const.NativeIntegers)
2041 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2042 else {
2043 op[0].negate = ~op[0].negate;
2044 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2045 }
2046 break;
2047 case ir_triop_bitfield_extract:
2048 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2049 break;
2050 case ir_quadop_bitfield_insert:
2051 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2052 break;
2053 case ir_unop_bitfield_reverse:
2054 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2055 break;
2056 case ir_unop_bit_count:
2057 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2058 break;
2059 case ir_unop_find_msb:
2060 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2061 break;
2062 case ir_unop_find_lsb:
2063 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2064 break;
2065 case ir_binop_imul_high:
2066 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2067 break;
2068 case ir_triop_fma:
2069 /* In theory, MAD is incorrect here. */
2070 if (have_fma)
2071 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2072 else
2073 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2074 break;
2075 case ir_unop_interpolate_at_centroid:
2076 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2077 break;
2078 case ir_binop_interpolate_at_offset: {
2079 /* The y coordinate needs to be flipped for the default fb */
2080 static const gl_state_index transform_y_state[STATE_LENGTH]
2081 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2082
2083 unsigned transform_y_index =
2084 _mesa_add_state_reference(this->prog->Parameters,
2085 transform_y_state);
2086
2087 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2088 transform_y_index,
2089 glsl_type::vec4_type);
2090 transform_y.swizzle = SWIZZLE_XXXX;
2091
2092 st_src_reg temp = get_temp(glsl_type::vec2_type);
2093 st_dst_reg temp_dst = st_dst_reg(temp);
2094
2095 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2096 temp_dst.writemask = WRITEMASK_Y;
2097 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2098 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2099 break;
2100 }
2101 case ir_binop_interpolate_at_sample:
2102 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2103 break;
2104
2105 case ir_unop_d2f:
2106 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2107 break;
2108 case ir_unop_f2d:
2109 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2110 break;
2111 case ir_unop_d2i:
2112 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2113 break;
2114 case ir_unop_i2d:
2115 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2116 break;
2117 case ir_unop_d2u:
2118 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2119 break;
2120 case ir_unop_u2d:
2121 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2122 break;
2123 case ir_unop_unpack_double_2x32:
2124 case ir_unop_pack_double_2x32:
2125 case ir_unop_unpack_int_2x32:
2126 case ir_unop_pack_int_2x32:
2127 case ir_unop_unpack_uint_2x32:
2128 case ir_unop_pack_uint_2x32:
2129 case ir_unop_unpack_sampler_2x32:
2130 case ir_unop_pack_sampler_2x32:
2131 case ir_unop_unpack_image_2x32:
2132 case ir_unop_pack_image_2x32:
2133 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2134 break;
2135
2136 case ir_binop_ldexp:
2137 if (ir->operands[0]->type->is_double()) {
2138 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2139 } else if (ir->operands[0]->type->is_float()) {
2140 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2141 } else {
2142 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2143 }
2144 break;
2145
2146 case ir_unop_pack_half_2x16:
2147 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2148 break;
2149 case ir_unop_unpack_half_2x16:
2150 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2151 break;
2152
2153 case ir_unop_get_buffer_size: {
2154 ir_constant *const_offset = ir->operands[0]->as_constant();
2155 int buf_base = ctx->st->has_hw_atomics ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2156 st_src_reg buffer(
2157 PROGRAM_BUFFER,
2158 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2159 GLSL_TYPE_UINT);
2160 if (!const_offset) {
2161 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2162 *buffer.reladdr = op[0];
2163 emit_arl(ir, sampler_reladdr, op[0]);
2164 }
2165 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2166 break;
2167 }
2168
2169 case ir_unop_u2i64:
2170 case ir_unop_u2u64:
2171 case ir_unop_b2i64: {
2172 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2173 st_dst_reg temp_dst = st_dst_reg(temp);
2174 unsigned orig_swz = op[0].swizzle;
2175 /*
2176 * To convert unsigned to 64-bit:
2177 * zero Y channel, copy X channel.
2178 */
2179 temp_dst.writemask = WRITEMASK_Y;
2180 if (vector_elements > 1)
2181 temp_dst.writemask |= WRITEMASK_W;
2182 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2183 temp_dst.writemask = WRITEMASK_X;
2184 if (vector_elements > 1)
2185 temp_dst.writemask |= WRITEMASK_Z;
2186 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2187 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2188 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2189 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2190 else
2191 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2192 result_src = temp;
2193 result_src.type = GLSL_TYPE_UINT64;
2194 if (vector_elements > 2) {
2195 /* Subtle: We rely on the fact that get_temp here returns the next
2196 * TGSI temporary register directly after the temp register used for
2197 * the first two components, so that the result gets picked up
2198 * automatically.
2199 */
2200 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2201 st_dst_reg temp_dst = st_dst_reg(temp);
2202 temp_dst.writemask = WRITEMASK_Y;
2203 if (vector_elements > 3)
2204 temp_dst.writemask |= WRITEMASK_W;
2205 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2206
2207 temp_dst.writemask = WRITEMASK_X;
2208 if (vector_elements > 3)
2209 temp_dst.writemask |= WRITEMASK_Z;
2210 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2), GET_SWZ(orig_swz, 2),
2211 GET_SWZ(orig_swz, 3), GET_SWZ(orig_swz, 3));
2212 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2213 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2214 else
2215 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2216 }
2217 break;
2218 }
2219 case ir_unop_i642i:
2220 case ir_unop_u642i:
2221 case ir_unop_u642u:
2222 case ir_unop_i642u: {
2223 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2224 st_dst_reg temp_dst = st_dst_reg(temp);
2225 unsigned orig_swz = op[0].swizzle;
2226 unsigned orig_idx = op[0].index;
2227 int el;
2228 temp_dst.writemask = WRITEMASK_X;
2229
2230 for (el = 0; el < vector_elements; el++) {
2231 unsigned swz = GET_SWZ(orig_swz, el);
2232 if (swz & 1)
2233 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z);
2234 else
2235 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X);
2236 if (swz > 2)
2237 op[0].index = orig_idx + 1;
2238 op[0].type = GLSL_TYPE_UINT;
2239 temp_dst.writemask = WRITEMASK_X << el;
2240 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2241 }
2242 result_src = temp;
2243 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2244 result_src.type = GLSL_TYPE_UINT;
2245 else
2246 result_src.type = GLSL_TYPE_INT;
2247 break;
2248 }
2249 case ir_unop_i642b:
2250 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int64(0));
2251 break;
2252 case ir_unop_i642f:
2253 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2254 break;
2255 case ir_unop_u642f:
2256 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2257 break;
2258 case ir_unop_i642d:
2259 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2260 break;
2261 case ir_unop_u642d:
2262 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2263 break;
2264 case ir_unop_i2i64:
2265 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2266 break;
2267 case ir_unop_f2i64:
2268 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2269 break;
2270 case ir_unop_d2i64:
2271 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2272 break;
2273 case ir_unop_i2u64:
2274 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2275 break;
2276 case ir_unop_f2u64:
2277 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2278 break;
2279 case ir_unop_d2u64:
2280 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2281 break;
2282 /* these might be needed */
2283 case ir_unop_pack_snorm_2x16:
2284 case ir_unop_pack_unorm_2x16:
2285 case ir_unop_pack_snorm_4x8:
2286 case ir_unop_pack_unorm_4x8:
2287
2288 case ir_unop_unpack_snorm_2x16:
2289 case ir_unop_unpack_unorm_2x16:
2290 case ir_unop_unpack_snorm_4x8:
2291 case ir_unop_unpack_unorm_4x8:
2292
2293 case ir_quadop_vector:
2294 case ir_binop_vector_extract:
2295 case ir_triop_vector_insert:
2296 case ir_binop_carry:
2297 case ir_binop_borrow:
2298 case ir_unop_ssbo_unsized_array_length:
2299 /* This operation is not supported, or should have already been handled.
2300 */
2301 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2302 break;
2303 }
2304
2305 this->result = result_src;
2306 }
2307
2308
2309 void
2310 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2311 {
2312 st_src_reg src;
2313 int i;
2314 int swizzle[4];
2315
2316 /* Note that this is only swizzles in expressions, not those on the left
2317 * hand side of an assignment, which do write masking. See ir_assignment
2318 * for that.
2319 */
2320
2321 ir->val->accept(this);
2322 src = this->result;
2323 assert(src.file != PROGRAM_UNDEFINED);
2324 assert(ir->type->vector_elements > 0);
2325
2326 for (i = 0; i < 4; i++) {
2327 if (i < ir->type->vector_elements) {
2328 switch (i) {
2329 case 0:
2330 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2331 break;
2332 case 1:
2333 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2334 break;
2335 case 2:
2336 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2337 break;
2338 case 3:
2339 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2340 break;
2341 }
2342 } else {
2343 /* If the type is smaller than a vec4, replicate the last
2344 * channel out.
2345 */
2346 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2347 }
2348 }
2349
2350 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2351
2352 this->result = src;
2353 }
2354
2355 /* Test if the variable is an array. Note that geometry and
2356 * tessellation shader inputs are outputs are always arrays (except
2357 * for patch inputs), so only the array element type is considered.
2358 */
2359 static bool
2360 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2361 {
2362 const glsl_type *type = var->type;
2363
2364 *remove_array = false;
2365
2366 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2367 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2368 return false;
2369
2370 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2371 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2372 stage == MESA_SHADER_TESS_CTRL) &&
2373 !var->data.patch) {
2374 if (!var->type->is_array())
2375 return false; /* a system value probably */
2376
2377 type = var->type->fields.array;
2378 *remove_array = true;
2379 }
2380
2381 return type->is_array() || type->is_matrix();
2382 }
2383
2384 static unsigned
2385 st_translate_interp_loc(ir_variable *var)
2386 {
2387 if (var->data.centroid)
2388 return TGSI_INTERPOLATE_LOC_CENTROID;
2389 else if (var->data.sample)
2390 return TGSI_INTERPOLATE_LOC_SAMPLE;
2391 else
2392 return TGSI_INTERPOLATE_LOC_CENTER;
2393 }
2394
2395 void
2396 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2397 {
2398 variable_storage *entry = find_variable_storage(ir->var);
2399 ir_variable *var = ir->var;
2400 bool remove_array;
2401
2402 if (!entry) {
2403 switch (var->data.mode) {
2404 case ir_var_uniform:
2405 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2406 var->data.param_index);
2407 _mesa_hash_table_insert(this->variables, var, entry);
2408 break;
2409 case ir_var_shader_in: {
2410 /* The linker assigns locations for varyings and attributes,
2411 * including deprecated builtins (like gl_Color), user-assign
2412 * generic attributes (glBindVertexLocation), and
2413 * user-defined varyings.
2414 */
2415 assert(var->data.location != -1);
2416
2417 const glsl_type *type_without_array = var->type->without_array();
2418 struct inout_decl *decl = &inputs[num_inputs];
2419 unsigned component = var->data.location_frac;
2420 unsigned num_components;
2421 num_inputs++;
2422
2423 if (type_without_array->is_64bit())
2424 component = component / 2;
2425 if (type_without_array->vector_elements)
2426 num_components = type_without_array->vector_elements;
2427 else
2428 num_components = 4;
2429
2430 decl->mesa_index = var->data.location;
2431 decl->interp = (glsl_interp_mode) var->data.interpolation;
2432 decl->interp_loc = st_translate_interp_loc(var);
2433 decl->base_type = type_without_array->base_type;
2434 decl->usage_mask = u_bit_consecutive(component, num_components);
2435
2436 if (is_inout_array(shader->Stage, var, &remove_array)) {
2437 decl->array_id = num_input_arrays + 1;
2438 num_input_arrays++;
2439 } else {
2440 decl->array_id = 0;
2441 }
2442
2443 if (remove_array)
2444 decl->size = type_size(var->type->fields.array);
2445 else
2446 decl->size = type_size(var->type);
2447
2448 entry = new(mem_ctx) variable_storage(var,
2449 PROGRAM_INPUT,
2450 decl->mesa_index,
2451 decl->array_id);
2452 entry->component = component;
2453
2454 _mesa_hash_table_insert(this->variables, var, entry);
2455
2456 break;
2457 }
2458 case ir_var_shader_out: {
2459 assert(var->data.location != -1);
2460
2461 const glsl_type *type_without_array = var->type->without_array();
2462 struct inout_decl *decl = &outputs[num_outputs];
2463 unsigned component = var->data.location_frac;
2464 unsigned num_components;
2465 num_outputs++;
2466
2467 if (type_without_array->is_64bit())
2468 component = component / 2;
2469 if (type_without_array->vector_elements)
2470 num_components = type_without_array->vector_elements;
2471 else
2472 num_components = 4;
2473
2474 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2475 decl->base_type = type_without_array->base_type;
2476 decl->usage_mask = u_bit_consecutive(component, num_components);
2477 if (var->data.stream & (1u << 31)) {
2478 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2479 } else {
2480 assert(var->data.stream < 4);
2481 decl->gs_out_streams = 0;
2482 for (unsigned i = 0; i < num_components; ++i)
2483 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2484 }
2485
2486 if (is_inout_array(shader->Stage, var, &remove_array)) {
2487 decl->array_id = num_output_arrays + 1;
2488 num_output_arrays++;
2489 } else {
2490 decl->array_id = 0;
2491 }
2492
2493 if (remove_array)
2494 decl->size = type_size(var->type->fields.array);
2495 else
2496 decl->size = type_size(var->type);
2497
2498 if (var->data.fb_fetch_output) {
2499 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2500 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2501 var->type, component, decl->array_id);
2502 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2503 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2504 dst.array_id);
2505 } else {
2506 entry = new(mem_ctx) variable_storage(var,
2507 PROGRAM_OUTPUT,
2508 decl->mesa_index,
2509 decl->array_id);
2510 }
2511 entry->component = component;
2512
2513 _mesa_hash_table_insert(this->variables, var, entry);
2514
2515 break;
2516 }
2517 case ir_var_system_value:
2518 entry = new(mem_ctx) variable_storage(var,
2519 PROGRAM_SYSTEM_VALUE,
2520 var->data.location);
2521 break;
2522 case ir_var_auto:
2523 case ir_var_temporary:
2524 st_src_reg src = get_temp(var->type);
2525
2526 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2527 src.array_id);
2528 _mesa_hash_table_insert(this->variables, var, entry);
2529
2530 break;
2531 }
2532
2533 if (!entry) {
2534 printf("Failed to make storage for %s\n", var->name);
2535 exit(1);
2536 }
2537 }
2538
2539 this->result = st_src_reg(entry->file, entry->index, var->type,
2540 entry->component, entry->array_id);
2541 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2542 var->data.mode == ir_var_shader_in &&
2543 var->type->without_array()->is_double())
2544 this->result.is_double_vertex_input = true;
2545 if (!native_integers)
2546 this->result.type = GLSL_TYPE_FLOAT;
2547 }
2548
2549 static void
2550 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2551 GLbitfield64* usage_mask,
2552 GLbitfield64 double_usage_mask,
2553 GLbitfield* patch_usage_mask)
2554 {
2555 unsigned i;
2556 int j;
2557
2558 /* Fix array declarations by removing unused array elements at both ends
2559 * of the arrays. For example, mat4[3] where only mat[1] is used.
2560 */
2561 for (i = 0; i < count; i++) {
2562 struct inout_decl *decl = &decls[i];
2563 if (!decl->array_id)
2564 continue;
2565
2566 /* Shrink the beginning. */
2567 for (j = 0; j < (int)decl->size; j++) {
2568 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2569 if (*patch_usage_mask &
2570 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2571 break;
2572 }
2573 else {
2574 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2575 break;
2576 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2577 break;
2578 }
2579
2580 decl->mesa_index++;
2581 decl->size--;
2582 j--;
2583 }
2584
2585 /* Shrink the end. */
2586 for (j = decl->size-1; j >= 0; j--) {
2587 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2588 if (*patch_usage_mask &
2589 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2590 break;
2591 }
2592 else {
2593 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2594 break;
2595 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2596 break;
2597 }
2598
2599 decl->size--;
2600 }
2601
2602 /* When not all entries of an array are accessed, we mark them as used
2603 * here anyway, to ensure that the input/output mapping logic doesn't get
2604 * confused.
2605 *
2606 * TODO This happens when an array isn't used via indirect access, which
2607 * some game ports do (at least eON-based). There is an optimization
2608 * opportunity here by replacing the array declaration with non-array
2609 * declarations of those slots that are actually used.
2610 */
2611 for (j = 1; j < (int)decl->size; ++j) {
2612 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2613 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2614 else
2615 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2616 }
2617 }
2618 }
2619
2620 void
2621 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2622 {
2623 ir_constant *index;
2624 st_src_reg src;
2625 bool is_2D = false;
2626 ir_variable *var = ir->variable_referenced();
2627
2628 /* We only need the logic provided by st_glsl_storage_type_size()
2629 * for arrays of structs. Indirect sampler and image indexing is handled
2630 * elsewhere.
2631 */
2632 int element_size = ir->type->without_array()->is_record() ?
2633 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2634 type_size(ir->type);
2635
2636 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2637
2638 ir->array->accept(this);
2639 src = this->result;
2640
2641 if (!src.has_index2) {
2642 switch (this->prog->Target) {
2643 case GL_TESS_CONTROL_PROGRAM_NV:
2644 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2645 !ir->variable_referenced()->data.patch;
2646 break;
2647 case GL_TESS_EVALUATION_PROGRAM_NV:
2648 is_2D = src.file == PROGRAM_INPUT &&
2649 !ir->variable_referenced()->data.patch;
2650 break;
2651 case GL_GEOMETRY_PROGRAM_NV:
2652 is_2D = src.file == PROGRAM_INPUT;
2653 break;
2654 }
2655 }
2656
2657 if (is_2D)
2658 element_size = 1;
2659
2660 if (index) {
2661
2662 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2663 src.file == PROGRAM_INPUT)
2664 element_size = attrib_type_size(ir->type, true);
2665 if (is_2D) {
2666 src.index2D = index->value.i[0];
2667 src.has_index2 = true;
2668 } else
2669 src.index += index->value.i[0] * element_size;
2670 } else {
2671 /* Variable index array dereference. It eats the "vec4" of the
2672 * base of the array and an index that offsets the TGSI register
2673 * index.
2674 */
2675 ir->array_index->accept(this);
2676
2677 st_src_reg index_reg;
2678
2679 if (element_size == 1) {
2680 index_reg = this->result;
2681 } else {
2682 index_reg = get_temp(native_integers ?
2683 glsl_type::int_type : glsl_type::float_type);
2684
2685 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2686 this->result, st_src_reg_for_type(index_reg.type, element_size));
2687 }
2688
2689 /* If there was already a relative address register involved, add the
2690 * new and the old together to get the new offset.
2691 */
2692 if (!is_2D && src.reladdr != NULL) {
2693 st_src_reg accum_reg = get_temp(native_integers ?
2694 glsl_type::int_type : glsl_type::float_type);
2695
2696 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2697 index_reg, *src.reladdr);
2698
2699 index_reg = accum_reg;
2700 }
2701
2702 if (is_2D) {
2703 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2704 memcpy(src.reladdr2, &index_reg, sizeof(index_reg));
2705 src.index2D = 0;
2706 src.has_index2 = true;
2707 } else {
2708 src.reladdr = ralloc(mem_ctx, st_src_reg);
2709 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
2710 }
2711 }
2712
2713 /* Change the register type to the element type of the array. */
2714 src.type = ir->type->base_type;
2715
2716 this->result = src;
2717 }
2718
2719 void
2720 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2721 {
2722 unsigned int i;
2723 const glsl_type *struct_type = ir->record->type;
2724 ir_variable *var = ir->record->variable_referenced();
2725 int offset = 0;
2726
2727 ir->record->accept(this);
2728
2729 assert(ir->field_idx >= 0);
2730 assert(var);
2731 for (i = 0; i < struct_type->length; i++) {
2732 if (i == (unsigned) ir->field_idx)
2733 break;
2734 const glsl_type *member_type = struct_type->fields.structure[i].type;
2735 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2736 }
2737
2738 /* If the type is smaller than a vec4, replicate the last channel out. */
2739 if (ir->type->is_scalar() || ir->type->is_vector())
2740 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2741 else
2742 this->result.swizzle = SWIZZLE_NOOP;
2743
2744 this->result.index += offset;
2745 this->result.type = ir->type->base_type;
2746 }
2747
2748 /**
2749 * We want to be careful in assignment setup to hit the actual storage
2750 * instead of potentially using a temporary like we might with the
2751 * ir_dereference handler.
2752 */
2753 static st_dst_reg
2754 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2755 {
2756 /* The LHS must be a dereference. If the LHS is a variable indexed array
2757 * access of a vector, it must be separated into a series conditional moves
2758 * before reaching this point (see ir_vec_index_to_cond_assign).
2759 */
2760 assert(ir->as_dereference());
2761 ir_dereference_array *deref_array = ir->as_dereference_array();
2762 if (deref_array) {
2763 assert(!deref_array->array->type->is_vector());
2764 }
2765
2766 /* Use the rvalue deref handler for the most part. We write swizzles using
2767 * the writemask, but we do extract the base component for enhanced layouts
2768 * from the source swizzle.
2769 */
2770 ir->accept(v);
2771 *component = GET_SWZ(v->result.swizzle, 0);
2772 return st_dst_reg(v->result);
2773 }
2774
2775 /**
2776 * Process the condition of a conditional assignment
2777 *
2778 * Examines the condition of a conditional assignment to generate the optimal
2779 * first operand of a \c CMP instruction. If the condition is a relational
2780 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2781 * used as the source for the \c CMP instruction. Otherwise the comparison
2782 * is processed to a boolean result, and the boolean result is used as the
2783 * operand to the CMP instruction.
2784 */
2785 bool
2786 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2787 {
2788 ir_rvalue *src_ir = ir;
2789 bool negate = true;
2790 bool switch_order = false;
2791
2792 ir_expression *const expr = ir->as_expression();
2793
2794 if (native_integers) {
2795 if ((expr != NULL) && (expr->num_operands == 2)) {
2796 enum glsl_base_type type = expr->operands[0]->type->base_type;
2797 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2798 type == GLSL_TYPE_BOOL) {
2799 if (expr->operation == ir_binop_equal) {
2800 if (expr->operands[0]->is_zero()) {
2801 src_ir = expr->operands[1];
2802 switch_order = true;
2803 }
2804 else if (expr->operands[1]->is_zero()) {
2805 src_ir = expr->operands[0];
2806 switch_order = true;
2807 }
2808 }
2809 else if (expr->operation == ir_binop_nequal) {
2810 if (expr->operands[0]->is_zero()) {
2811 src_ir = expr->operands[1];
2812 }
2813 else if (expr->operands[1]->is_zero()) {
2814 src_ir = expr->operands[0];
2815 }
2816 }
2817 }
2818 }
2819
2820 src_ir->accept(this);
2821 return switch_order;
2822 }
2823
2824 if ((expr != NULL) && (expr->num_operands == 2)) {
2825 bool zero_on_left = false;
2826
2827 if (expr->operands[0]->is_zero()) {
2828 src_ir = expr->operands[1];
2829 zero_on_left = true;
2830 } else if (expr->operands[1]->is_zero()) {
2831 src_ir = expr->operands[0];
2832 zero_on_left = false;
2833 }
2834
2835 /* a is - 0 + - 0 +
2836 * (a < 0) T F F ( a < 0) T F F
2837 * (0 < a) F F T (-a < 0) F F T
2838 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2839 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2840 *
2841 * Note that exchanging the order of 0 and 'a' in the comparison simply
2842 * means that the value of 'a' should be negated.
2843 */
2844 if (src_ir != ir) {
2845 switch (expr->operation) {
2846 case ir_binop_less:
2847 switch_order = false;
2848 negate = zero_on_left;
2849 break;
2850
2851 case ir_binop_gequal:
2852 switch_order = true;
2853 negate = zero_on_left;
2854 break;
2855
2856 default:
2857 /* This isn't the right kind of comparison afterall, so make sure
2858 * the whole condition is visited.
2859 */
2860 src_ir = ir;
2861 break;
2862 }
2863 }
2864 }
2865
2866 src_ir->accept(this);
2867
2868 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2869 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2870 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2871 * computing the condition.
2872 */
2873 if (negate)
2874 this->result.negate = ~this->result.negate;
2875
2876 return switch_order;
2877 }
2878
2879 void
2880 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
2881 st_dst_reg *l, st_src_reg *r,
2882 st_src_reg *cond, bool cond_swap)
2883 {
2884 if (type->is_record()) {
2885 for (unsigned int i = 0; i < type->length; i++) {
2886 emit_block_mov(ir, type->fields.structure[i].type, l, r,
2887 cond, cond_swap);
2888 }
2889 return;
2890 }
2891
2892 if (type->is_array()) {
2893 for (unsigned int i = 0; i < type->length; i++) {
2894 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
2895 }
2896 return;
2897 }
2898
2899 if (type->is_matrix()) {
2900 const struct glsl_type *vec_type;
2901
2902 vec_type = glsl_type::get_instance(type->is_double() ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
2903 type->vector_elements, 1);
2904
2905 for (int i = 0; i < type->matrix_columns; i++) {
2906 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
2907 }
2908 return;
2909 }
2910
2911 assert(type->is_scalar() || type->is_vector());
2912
2913 l->type = type->base_type;
2914 r->type = type->base_type;
2915 if (cond) {
2916 st_src_reg l_src = st_src_reg(*l);
2917
2918 if (l_src.file == PROGRAM_OUTPUT &&
2919 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
2920 (l_src.index == FRAG_RESULT_DEPTH || l_src.index == FRAG_RESULT_STENCIL)) {
2921 /* This is a special case because the source swizzles will be shifted
2922 * later to account for the difference between GLSL (where they're
2923 * plain floats) and TGSI (where they're Z and Y components). */
2924 l_src.swizzle = SWIZZLE_XXXX;
2925 }
2926
2927 if (native_integers) {
2928 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
2929 cond_swap ? l_src : *r,
2930 cond_swap ? *r : l_src);
2931 } else {
2932 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
2933 cond_swap ? l_src : *r,
2934 cond_swap ? *r : l_src);
2935 }
2936 } else {
2937 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
2938 }
2939 l->index++;
2940 r->index++;
2941 if (type->is_dual_slot()) {
2942 l->index++;
2943 if (r->is_double_vertex_input == false)
2944 r->index++;
2945 }
2946 }
2947
2948 void
2949 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
2950 {
2951 int dst_component;
2952 st_dst_reg l;
2953 st_src_reg r;
2954
2955 /* all generated instructions need to be flaged as precise */
2956 this->precise = is_precise(ir->lhs->variable_referenced());
2957 ir->rhs->accept(this);
2958 r = this->result;
2959
2960 l = get_assignment_lhs(ir->lhs, this, &dst_component);
2961
2962 {
2963 int swizzles[4];
2964 int first_enabled_chan = 0;
2965 int rhs_chan = 0;
2966 ir_variable *variable = ir->lhs->variable_referenced();
2967
2968 if (shader->Stage == MESA_SHADER_FRAGMENT &&
2969 variable->data.mode == ir_var_shader_out &&
2970 (variable->data.location == FRAG_RESULT_DEPTH ||
2971 variable->data.location == FRAG_RESULT_STENCIL)) {
2972 assert(ir->lhs->type->is_scalar());
2973 assert(ir->write_mask == WRITEMASK_X);
2974
2975 if (variable->data.location == FRAG_RESULT_DEPTH)
2976 l.writemask = WRITEMASK_Z;
2977 else {
2978 assert(variable->data.location == FRAG_RESULT_STENCIL);
2979 l.writemask = WRITEMASK_Y;
2980 }
2981 } else if (ir->write_mask == 0) {
2982 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
2983
2984 unsigned num_elements = ir->lhs->type->without_array()->vector_elements;
2985
2986 if (num_elements) {
2987 l.writemask = u_bit_consecutive(0, num_elements);
2988 } else {
2989 /* The type is a struct or an array of (array of) structs. */
2990 l.writemask = WRITEMASK_XYZW;
2991 }
2992 } else {
2993 l.writemask = ir->write_mask;
2994 }
2995
2996 for (int i = 0; i < 4; i++) {
2997 if (l.writemask & (1 << i)) {
2998 first_enabled_chan = GET_SWZ(r.swizzle, i);
2999 break;
3000 }
3001 }
3002
3003 l.writemask = l.writemask << dst_component;
3004
3005 /* Swizzle a small RHS vector into the channels being written.
3006 *
3007 * glsl ir treats write_mask as dictating how many channels are
3008 * present on the RHS while TGSI treats write_mask as just
3009 * showing which channels of the vec4 RHS get written.
3010 */
3011 for (int i = 0; i < 4; i++) {
3012 if (l.writemask & (1 << i))
3013 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3014 else
3015 swizzles[i] = first_enabled_chan;
3016 }
3017 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3018 swizzles[2], swizzles[3]);
3019 }
3020
3021 assert(l.file != PROGRAM_UNDEFINED);
3022 assert(r.file != PROGRAM_UNDEFINED);
3023
3024 if (ir->condition) {
3025 const bool switch_order = this->process_move_condition(ir->condition);
3026 st_src_reg condition = this->result;
3027
3028 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3029 } else if (ir->rhs->as_expression() &&
3030 this->instructions.get_tail() &&
3031 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3032 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3033 type_size(ir->lhs->type) == 1 &&
3034 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3035 /* To avoid emitting an extra MOV when assigning an expression to a
3036 * variable, emit the last instruction of the expression again, but
3037 * replace the destination register with the target of the assignment.
3038 * Dead code elimination will remove the original instruction.
3039 */
3040 glsl_to_tgsi_instruction *inst, *new_inst;
3041 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3042 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3043 new_inst->saturate = inst->saturate;
3044 new_inst->resource = inst->resource;
3045 inst->dead_mask = inst->dst[0].writemask;
3046 } else {
3047 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3048 }
3049 this->precise = 0;
3050 }
3051
3052
3053 void
3054 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3055 {
3056 st_src_reg src;
3057 GLdouble stack_vals[4] = { 0 };
3058 gl_constant_value *values = (gl_constant_value *) stack_vals;
3059 GLenum gl_type = GL_NONE;
3060 unsigned int i;
3061 static int in_array = 0;
3062 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3063
3064 /* Unfortunately, 4 floats is all we can get into
3065 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3066 * aggregate constant and move each constant value into it. If we
3067 * get lucky, copy propagation will eliminate the extra moves.
3068 */
3069 if (ir->type->is_record()) {
3070 st_src_reg temp_base = get_temp(ir->type);
3071 st_dst_reg temp = st_dst_reg(temp_base);
3072
3073 for (i = 0; i < ir->type->length; i++) {
3074 ir_constant *const field_value = ir->get_record_field(i);
3075 int size = type_size(field_value->type);
3076
3077 assert(size > 0);
3078
3079 field_value->accept(this);
3080 src = this->result;
3081
3082 for (unsigned j = 0; j < (unsigned int)size; j++) {
3083 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3084
3085 src.index++;
3086 temp.index++;
3087 }
3088 }
3089 this->result = temp_base;
3090 return;
3091 }
3092
3093 if (ir->type->is_array()) {
3094 st_src_reg temp_base = get_temp(ir->type);
3095 st_dst_reg temp = st_dst_reg(temp_base);
3096 int size = type_size(ir->type->fields.array);
3097
3098 assert(size > 0);
3099 in_array++;
3100
3101 for (i = 0; i < ir->type->length; i++) {
3102 ir->const_elements[i]->accept(this);
3103 src = this->result;
3104 for (int j = 0; j < size; j++) {
3105 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3106
3107 src.index++;
3108 temp.index++;
3109 }
3110 }
3111 this->result = temp_base;
3112 in_array--;
3113 return;
3114 }
3115
3116 if (ir->type->is_matrix()) {
3117 st_src_reg mat = get_temp(ir->type);
3118 st_dst_reg mat_column = st_dst_reg(mat);
3119
3120 for (i = 0; i < ir->type->matrix_columns; i++) {
3121 switch (ir->type->base_type) {
3122 case GLSL_TYPE_FLOAT:
3123 values = (gl_constant_value *) &ir->value.f[i * ir->type->vector_elements];
3124
3125 src = st_src_reg(file, -1, ir->type->base_type);
3126 src.index = add_constant(file,
3127 values,
3128 ir->type->vector_elements,
3129 GL_FLOAT,
3130 &src.swizzle);
3131 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3132 break;
3133 case GLSL_TYPE_DOUBLE:
3134 values = (gl_constant_value *) &ir->value.d[i * ir->type->vector_elements];
3135 src = st_src_reg(file, -1, ir->type->base_type);
3136 src.index = add_constant(file,
3137 values,
3138 ir->type->vector_elements,
3139 GL_DOUBLE,
3140 &src.swizzle);
3141 if (ir->type->vector_elements >= 2) {
3142 mat_column.writemask = WRITEMASK_XY;
3143 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
3144 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3145 } else {
3146 mat_column.writemask = WRITEMASK_X;
3147 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X);
3148 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3149 }
3150 src.index++;
3151 if (ir->type->vector_elements > 2) {
3152 if (ir->type->vector_elements == 4) {
3153 mat_column.writemask = WRITEMASK_ZW;
3154 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
3155 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3156 } else {
3157 mat_column.writemask = WRITEMASK_Z;
3158 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y);
3159 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3160 mat_column.writemask = WRITEMASK_XYZW;
3161 src.swizzle = SWIZZLE_XYZW;
3162 }
3163 mat_column.index++;
3164 }
3165 break;
3166 default:
3167 unreachable("Illegal matrix constant type.\n");
3168 break;
3169 }
3170 mat_column.index++;
3171 }
3172 this->result = mat;
3173 return;
3174 }
3175
3176 switch (ir->type->base_type) {
3177 case GLSL_TYPE_FLOAT:
3178 gl_type = GL_FLOAT;
3179 for (i = 0; i < ir->type->vector_elements; i++) {
3180 values[i].f = ir->value.f[i];
3181 }
3182 break;
3183 case GLSL_TYPE_DOUBLE:
3184 gl_type = GL_DOUBLE;
3185 for (i = 0; i < ir->type->vector_elements; i++) {
3186 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3187 }
3188 break;
3189 case GLSL_TYPE_INT64:
3190 gl_type = GL_INT64_ARB;
3191 for (i = 0; i < ir->type->vector_elements; i++) {
3192 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3193 }
3194 break;
3195 case GLSL_TYPE_UINT64:
3196 gl_type = GL_UNSIGNED_INT64_ARB;
3197 for (i = 0; i < ir->type->vector_elements; i++) {
3198 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3199 }
3200 break;
3201 case GLSL_TYPE_UINT:
3202 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3203 for (i = 0; i < ir->type->vector_elements; i++) {
3204 if (native_integers)
3205 values[i].u = ir->value.u[i];
3206 else
3207 values[i].f = ir->value.u[i];
3208 }
3209 break;
3210 case GLSL_TYPE_INT:
3211 gl_type = native_integers ? GL_INT : GL_FLOAT;
3212 for (i = 0; i < ir->type->vector_elements; i++) {
3213 if (native_integers)
3214 values[i].i = ir->value.i[i];
3215 else
3216 values[i].f = ir->value.i[i];
3217 }
3218 break;
3219 case GLSL_TYPE_BOOL:
3220 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3221 for (i = 0; i < ir->type->vector_elements; i++) {
3222 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3223 }
3224 break;
3225 default:
3226 assert(!"Non-float/uint/int/bool constant");
3227 }
3228
3229 this->result = st_src_reg(file, -1, ir->type);
3230 this->result.index = add_constant(file,
3231 values,
3232 ir->type->vector_elements,
3233 gl_type,
3234 &this->result.swizzle);
3235 }
3236
3237 void
3238 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3239 {
3240 exec_node *param = ir->actual_parameters.get_head();
3241 ir_dereference *deref = static_cast<ir_dereference *>(param);
3242 ir_variable *location = deref->variable_referenced();
3243 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3244 /* Calculate the surface offset */
3245 st_src_reg offset;
3246 unsigned array_size = 0, base = 0;
3247 uint16_t index = 0;
3248 st_src_reg resource;
3249
3250 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3251
3252 if (has_hw_atomics) {
3253 variable_storage *entry = find_variable_storage(location);
3254 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT, location->data.binding);
3255
3256 if (!entry) {
3257 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3258 num_atomics);
3259 _mesa_hash_table_insert(this->variables, location, entry);
3260
3261 atomic_info[num_atomics].location = location->data.location;
3262 atomic_info[num_atomics].binding = location->data.binding;
3263 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3264 if (atomic_info[num_atomics].size == 0)
3265 atomic_info[num_atomics].size = 1;
3266 atomic_info[num_atomics].array_id = 0;
3267 num_atomics++;
3268 }
3269
3270 if (offset.file != PROGRAM_UNDEFINED) {
3271 if (atomic_info[entry->index].array_id == 0) {
3272 num_atomic_arrays++;
3273 atomic_info[entry->index].array_id = num_atomic_arrays;
3274 }
3275 buffer.array_id = atomic_info[entry->index].array_id;
3276 }
3277
3278 buffer.index = index;
3279 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3280 buffer.has_index2 = true;
3281
3282 if (offset.file != PROGRAM_UNDEFINED) {
3283 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3284 *buffer.reladdr = offset;
3285 emit_arl(ir, sampler_reladdr, offset);
3286 }
3287 offset = st_src_reg_for_int(0);
3288
3289 resource = buffer;
3290 } else {
3291 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3292 GLSL_TYPE_ATOMIC_UINT);
3293
3294 if (offset.file != PROGRAM_UNDEFINED) {
3295 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3296 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3297 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3298 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3299 } else {
3300 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3301 }
3302 resource = buffer;
3303 }
3304
3305 ir->return_deref->accept(this);
3306 st_dst_reg dst(this->result);
3307 dst.writemask = WRITEMASK_X;
3308
3309 glsl_to_tgsi_instruction *inst;
3310
3311 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3312 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3313 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3314 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3315 st_src_reg_for_int(1));
3316 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3317 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3318 st_src_reg_for_int(-1));
3319 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3320 } else {
3321 param = param->get_next();
3322 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3323 val->accept(this);
3324
3325 st_src_reg data = this->result, data2 = undef_src;
3326 unsigned opcode;
3327 switch (ir->callee->intrinsic_id) {
3328 case ir_intrinsic_atomic_counter_add:
3329 opcode = TGSI_OPCODE_ATOMUADD;
3330 break;
3331 case ir_intrinsic_atomic_counter_min:
3332 opcode = TGSI_OPCODE_ATOMIMIN;
3333 break;
3334 case ir_intrinsic_atomic_counter_max:
3335 opcode = TGSI_OPCODE_ATOMIMAX;
3336 break;
3337 case ir_intrinsic_atomic_counter_and:
3338 opcode = TGSI_OPCODE_ATOMAND;
3339 break;
3340 case ir_intrinsic_atomic_counter_or:
3341 opcode = TGSI_OPCODE_ATOMOR;
3342 break;
3343 case ir_intrinsic_atomic_counter_xor:
3344 opcode = TGSI_OPCODE_ATOMXOR;
3345 break;
3346 case ir_intrinsic_atomic_counter_exchange:
3347 opcode = TGSI_OPCODE_ATOMXCHG;
3348 break;
3349 case ir_intrinsic_atomic_counter_comp_swap: {
3350 opcode = TGSI_OPCODE_ATOMCAS;
3351 param = param->get_next();
3352 val = ((ir_instruction *)param)->as_rvalue();
3353 val->accept(this);
3354 data2 = this->result;
3355 break;
3356 }
3357 default:
3358 assert(!"Unexpected intrinsic");
3359 return;
3360 }
3361
3362 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3363 }
3364
3365 inst->resource = resource;
3366 }
3367
3368 void
3369 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3370 {
3371 exec_node *param = ir->actual_parameters.get_head();
3372
3373 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3374
3375 param = param->get_next();
3376 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3377
3378 ir_constant *const_block = block->as_constant();
3379 int buf_base = st_context(ctx)->has_hw_atomics ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3380 st_src_reg buffer(
3381 PROGRAM_BUFFER,
3382 buf_base + (const_block ? const_block->value.u[0] : 0),
3383 GLSL_TYPE_UINT);
3384
3385 if (!const_block) {
3386 block->accept(this);
3387 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3388 *buffer.reladdr = this->result;
3389 emit_arl(ir, sampler_reladdr, this->result);
3390 }
3391
3392 /* Calculate the surface offset */
3393 offset->accept(this);
3394 st_src_reg off = this->result;
3395
3396 st_dst_reg dst = undef_dst;
3397 if (ir->return_deref) {
3398 ir->return_deref->accept(this);
3399 dst = st_dst_reg(this->result);
3400 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3401 }
3402
3403 glsl_to_tgsi_instruction *inst;
3404
3405 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3406 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3407 if (dst.type == GLSL_TYPE_BOOL)
3408 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst), st_src_reg_for_int(0));
3409 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3410 param = param->get_next();
3411 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3412 val->accept(this);
3413
3414 param = param->get_next();
3415 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3416 assert(write_mask);
3417 dst.writemask = write_mask->value.u[0];
3418
3419 dst.type = this->result.type;
3420 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3421 } else {
3422 param = param->get_next();
3423 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3424 val->accept(this);
3425
3426 st_src_reg data = this->result, data2 = undef_src;
3427 unsigned opcode;
3428 switch (ir->callee->intrinsic_id) {
3429 case ir_intrinsic_ssbo_atomic_add:
3430 opcode = TGSI_OPCODE_ATOMUADD;
3431 break;
3432 case ir_intrinsic_ssbo_atomic_min:
3433 opcode = TGSI_OPCODE_ATOMIMIN;
3434 break;
3435 case ir_intrinsic_ssbo_atomic_max:
3436 opcode = TGSI_OPCODE_ATOMIMAX;
3437 break;
3438 case ir_intrinsic_ssbo_atomic_and:
3439 opcode = TGSI_OPCODE_ATOMAND;
3440 break;
3441 case ir_intrinsic_ssbo_atomic_or:
3442 opcode = TGSI_OPCODE_ATOMOR;
3443 break;
3444 case ir_intrinsic_ssbo_atomic_xor:
3445 opcode = TGSI_OPCODE_ATOMXOR;
3446 break;
3447 case ir_intrinsic_ssbo_atomic_exchange:
3448 opcode = TGSI_OPCODE_ATOMXCHG;
3449 break;
3450 case ir_intrinsic_ssbo_atomic_comp_swap:
3451 opcode = TGSI_OPCODE_ATOMCAS;
3452 param = param->get_next();
3453 val = ((ir_instruction *)param)->as_rvalue();
3454 val->accept(this);
3455 data2 = this->result;
3456 break;
3457 default:
3458 assert(!"Unexpected intrinsic");
3459 return;
3460 }
3461
3462 inst = emit_asm(ir, opcode, dst, off, data, data2);
3463 }
3464
3465 param = param->get_next();
3466 ir_constant *access = NULL;
3467 if (!param->is_tail_sentinel()) {
3468 access = ((ir_instruction *)param)->as_constant();
3469 assert(access);
3470 }
3471
3472 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3473 }
3474
3475 void
3476 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3477 {
3478 switch (ir->callee->intrinsic_id) {
3479 case ir_intrinsic_memory_barrier:
3480 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3481 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3482 TGSI_MEMBAR_ATOMIC_BUFFER |
3483 TGSI_MEMBAR_SHADER_IMAGE |
3484 TGSI_MEMBAR_SHARED));
3485 break;
3486 case ir_intrinsic_memory_barrier_atomic_counter:
3487 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3488 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3489 break;
3490 case ir_intrinsic_memory_barrier_buffer:
3491 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3492 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3493 break;
3494 case ir_intrinsic_memory_barrier_image:
3495 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3496 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3497 break;
3498 case ir_intrinsic_memory_barrier_shared:
3499 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3500 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3501 break;
3502 case ir_intrinsic_group_memory_barrier:
3503 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3504 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3505 TGSI_MEMBAR_ATOMIC_BUFFER |
3506 TGSI_MEMBAR_SHADER_IMAGE |
3507 TGSI_MEMBAR_SHARED |
3508 TGSI_MEMBAR_THREAD_GROUP));
3509 break;
3510 default:
3511 assert(!"Unexpected memory barrier intrinsic");
3512 }
3513 }
3514
3515 void
3516 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3517 {
3518 exec_node *param = ir->actual_parameters.get_head();
3519
3520 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3521
3522 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3523
3524 /* Calculate the surface offset */
3525 offset->accept(this);
3526 st_src_reg off = this->result;
3527
3528 st_dst_reg dst = undef_dst;
3529 if (ir->return_deref) {
3530 ir->return_deref->accept(this);
3531 dst = st_dst_reg(this->result);
3532 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3533 }
3534
3535 glsl_to_tgsi_instruction *inst;
3536
3537 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3538 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3539 inst->resource = buffer;
3540 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3541 param = param->get_next();
3542 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3543 val->accept(this);
3544
3545 param = param->get_next();
3546 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3547 assert(write_mask);
3548 dst.writemask = write_mask->value.u[0];
3549
3550 dst.type = this->result.type;
3551 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3552 inst->resource = buffer;
3553 } else {
3554 param = param->get_next();
3555 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3556 val->accept(this);
3557
3558 st_src_reg data = this->result, data2 = undef_src;
3559 unsigned opcode;
3560 switch (ir->callee->intrinsic_id) {
3561 case ir_intrinsic_shared_atomic_add:
3562 opcode = TGSI_OPCODE_ATOMUADD;
3563 break;
3564 case ir_intrinsic_shared_atomic_min:
3565 opcode = TGSI_OPCODE_ATOMIMIN;
3566 break;
3567 case ir_intrinsic_shared_atomic_max:
3568 opcode = TGSI_OPCODE_ATOMIMAX;
3569 break;
3570 case ir_intrinsic_shared_atomic_and:
3571 opcode = TGSI_OPCODE_ATOMAND;
3572 break;
3573 case ir_intrinsic_shared_atomic_or:
3574 opcode = TGSI_OPCODE_ATOMOR;
3575 break;
3576 case ir_intrinsic_shared_atomic_xor:
3577 opcode = TGSI_OPCODE_ATOMXOR;
3578 break;
3579 case ir_intrinsic_shared_atomic_exchange:
3580 opcode = TGSI_OPCODE_ATOMXCHG;
3581 break;
3582 case ir_intrinsic_shared_atomic_comp_swap:
3583 opcode = TGSI_OPCODE_ATOMCAS;
3584 param = param->get_next();
3585 val = ((ir_instruction *)param)->as_rvalue();
3586 val->accept(this);
3587 data2 = this->result;
3588 break;
3589 default:
3590 assert(!"Unexpected intrinsic");
3591 return;
3592 }
3593
3594 inst = emit_asm(ir, opcode, dst, off, data, data2);
3595 inst->resource = buffer;
3596 }
3597 }
3598
3599 static void
3600 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3601 bool *memory_coherent, bool *memory_volatile,
3602 bool *memory_restrict, unsigned *image_format)
3603 {
3604
3605 switch (ir->ir_type) {
3606 case ir_type_dereference_record: {
3607 ir_dereference_record *deref_record = ir->as_dereference_record();
3608 const glsl_type *struct_type = deref_record->record->type;
3609 int fild_idx = deref_record->field_idx;
3610
3611 *type = struct_type->fields.structure[fild_idx].type->without_array();
3612 *memory_coherent =
3613 struct_type->fields.structure[fild_idx].memory_coherent;
3614 *memory_volatile =
3615 struct_type->fields.structure[fild_idx].memory_volatile;
3616 *memory_restrict =
3617 struct_type->fields.structure[fild_idx].memory_restrict;
3618 *image_format =
3619 struct_type->fields.structure[fild_idx].image_format;
3620 break;
3621 }
3622
3623 case ir_type_dereference_array: {
3624 ir_dereference_array *deref_arr = ir->as_dereference_array();
3625 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3626 memory_coherent, memory_volatile, memory_restrict,
3627 image_format);
3628 break;
3629 }
3630
3631 case ir_type_dereference_variable: {
3632 ir_variable *var = ir->variable_referenced();
3633
3634 *type = var->type->without_array();
3635 *memory_coherent = var->data.memory_coherent;
3636 *memory_volatile = var->data.memory_volatile;
3637 *memory_restrict = var->data.memory_restrict;
3638 *image_format = var->data.image_format;
3639 break;
3640 }
3641
3642 default:
3643 break;
3644 }
3645 }
3646
3647 void
3648 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3649 {
3650 exec_node *param = ir->actual_parameters.get_head();
3651
3652 ir_dereference *img = (ir_dereference *)param;
3653 const ir_variable *imgvar = img->variable_referenced();
3654 unsigned sampler_array_size = 1, sampler_base = 0;
3655 bool memory_coherent = false, memory_volatile = false, memory_restrict = false;
3656 unsigned image_format = 0;
3657 const glsl_type *type = NULL;
3658
3659 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3660 &memory_restrict, &image_format);
3661
3662 st_src_reg reladdr;
3663 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3664 uint16_t index = 0;
3665 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3666 &index, &reladdr, !imgvar->contains_bindless());
3667
3668 image.index = index;
3669 if (reladdr.file != PROGRAM_UNDEFINED) {
3670 image.reladdr = ralloc(mem_ctx, st_src_reg);
3671 *image.reladdr = reladdr;
3672 emit_arl(ir, sampler_reladdr, reladdr);
3673 }
3674
3675 st_dst_reg dst = undef_dst;
3676 if (ir->return_deref) {
3677 ir->return_deref->accept(this);
3678 dst = st_dst_reg(this->result);
3679 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3680 }
3681
3682 glsl_to_tgsi_instruction *inst;
3683
3684 st_src_reg bindless;
3685 if (imgvar->contains_bindless()) {
3686 img->accept(this);
3687 bindless = this->result;
3688 }
3689
3690 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3691 dst.writemask = WRITEMASK_XYZ;
3692 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3693 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3694 st_src_reg res = get_temp(glsl_type::ivec4_type);
3695 st_dst_reg dstres = st_dst_reg(res);
3696 dstres.writemask = WRITEMASK_W;
3697 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3698 res.swizzle = SWIZZLE_WWWW;
3699 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3700 } else {
3701 st_src_reg arg1 = undef_src, arg2 = undef_src;
3702 st_src_reg coord;
3703 st_dst_reg coord_dst;
3704 coord = get_temp(glsl_type::ivec4_type);
3705 coord_dst = st_dst_reg(coord);
3706 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3707 param = param->get_next();
3708 ((ir_dereference *)param)->accept(this);
3709 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3710 coord.swizzle = SWIZZLE_XXXX;
3711 switch (type->coordinate_components()) {
3712 case 4: assert(!"unexpected coord count");
3713 /* fallthrough */
3714 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3715 /* fallthrough */
3716 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3717 }
3718
3719 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3720 param = param->get_next();
3721 ((ir_dereference *)param)->accept(this);
3722 st_src_reg sample = this->result;
3723 sample.swizzle = SWIZZLE_XXXX;
3724 coord_dst.writemask = WRITEMASK_W;
3725 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3726 coord.swizzle |= SWIZZLE_W << 9;
3727 }
3728
3729 param = param->get_next();
3730 if (!param->is_tail_sentinel()) {
3731 ((ir_dereference *)param)->accept(this);
3732 arg1 = this->result;
3733 param = param->get_next();
3734 }
3735
3736 if (!param->is_tail_sentinel()) {
3737 ((ir_dereference *)param)->accept(this);
3738 arg2 = this->result;
3739 param = param->get_next();
3740 }
3741
3742 assert(param->is_tail_sentinel());
3743
3744 unsigned opcode;
3745 switch (ir->callee->intrinsic_id) {
3746 case ir_intrinsic_image_load:
3747 opcode = TGSI_OPCODE_LOAD;
3748 break;
3749 case ir_intrinsic_image_store:
3750 opcode = TGSI_OPCODE_STORE;
3751 break;
3752 case ir_intrinsic_image_atomic_add:
3753 opcode = TGSI_OPCODE_ATOMUADD;
3754 break;
3755 case ir_intrinsic_image_atomic_min:
3756 opcode = TGSI_OPCODE_ATOMIMIN;
3757 break;
3758 case ir_intrinsic_image_atomic_max:
3759 opcode = TGSI_OPCODE_ATOMIMAX;
3760 break;
3761 case ir_intrinsic_image_atomic_and:
3762 opcode = TGSI_OPCODE_ATOMAND;
3763 break;
3764 case ir_intrinsic_image_atomic_or:
3765 opcode = TGSI_OPCODE_ATOMOR;
3766 break;
3767 case ir_intrinsic_image_atomic_xor:
3768 opcode = TGSI_OPCODE_ATOMXOR;
3769 break;
3770 case ir_intrinsic_image_atomic_exchange:
3771 opcode = TGSI_OPCODE_ATOMXCHG;
3772 break;
3773 case ir_intrinsic_image_atomic_comp_swap:
3774 opcode = TGSI_OPCODE_ATOMCAS;
3775 break;
3776 default:
3777 assert(!"Unexpected intrinsic");
3778 return;
3779 }
3780
3781 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3782 if (opcode == TGSI_OPCODE_STORE)
3783 inst->dst[0].writemask = WRITEMASK_XYZW;
3784 }
3785
3786 if (imgvar->contains_bindless()) {
3787 inst->resource = bindless;
3788 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3789 SWIZZLE_X, SWIZZLE_Y);
3790 } else {
3791 inst->resource = image;
3792 inst->sampler_array_size = sampler_array_size;
3793 inst->sampler_base = sampler_base;
3794 }
3795
3796 inst->tex_target = type->sampler_index();
3797 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3798 _mesa_get_shader_image_format(image_format));
3799
3800 if (memory_coherent)
3801 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3802 if (memory_restrict)
3803 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3804 if (memory_volatile)
3805 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3806 }
3807
3808 void
3809 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, unsigned op)
3810 {
3811 ir->return_deref->accept(this);
3812 st_dst_reg dst = st_dst_reg(this->result);
3813
3814 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3815
3816 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3817 unsigned num_src = 0;
3818 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
3819 assert(num_src < ARRAY_SIZE(src));
3820
3821 this->result.file = PROGRAM_UNDEFINED;
3822 param->accept(this);
3823 assert(this->result.file != PROGRAM_UNDEFINED);
3824
3825 src[num_src] = this->result;
3826 num_src++;
3827 }
3828
3829 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
3830 }
3831
3832 void
3833 glsl_to_tgsi_visitor::visit(ir_call *ir)
3834 {
3835 ir_function_signature *sig = ir->callee;
3836
3837 /* Filter out intrinsics */
3838 switch (sig->intrinsic_id) {
3839 case ir_intrinsic_atomic_counter_read:
3840 case ir_intrinsic_atomic_counter_increment:
3841 case ir_intrinsic_atomic_counter_predecrement:
3842 case ir_intrinsic_atomic_counter_add:
3843 case ir_intrinsic_atomic_counter_min:
3844 case ir_intrinsic_atomic_counter_max:
3845 case ir_intrinsic_atomic_counter_and:
3846 case ir_intrinsic_atomic_counter_or:
3847 case ir_intrinsic_atomic_counter_xor:
3848 case ir_intrinsic_atomic_counter_exchange:
3849 case ir_intrinsic_atomic_counter_comp_swap:
3850 visit_atomic_counter_intrinsic(ir);
3851 return;
3852
3853 case ir_intrinsic_ssbo_load:
3854 case ir_intrinsic_ssbo_store:
3855 case ir_intrinsic_ssbo_atomic_add:
3856 case ir_intrinsic_ssbo_atomic_min:
3857 case ir_intrinsic_ssbo_atomic_max:
3858 case ir_intrinsic_ssbo_atomic_and:
3859 case ir_intrinsic_ssbo_atomic_or:
3860 case ir_intrinsic_ssbo_atomic_xor:
3861 case ir_intrinsic_ssbo_atomic_exchange:
3862 case ir_intrinsic_ssbo_atomic_comp_swap:
3863 visit_ssbo_intrinsic(ir);
3864 return;
3865
3866 case ir_intrinsic_memory_barrier:
3867 case ir_intrinsic_memory_barrier_atomic_counter:
3868 case ir_intrinsic_memory_barrier_buffer:
3869 case ir_intrinsic_memory_barrier_image:
3870 case ir_intrinsic_memory_barrier_shared:
3871 case ir_intrinsic_group_memory_barrier:
3872 visit_membar_intrinsic(ir);
3873 return;
3874
3875 case ir_intrinsic_shared_load:
3876 case ir_intrinsic_shared_store:
3877 case ir_intrinsic_shared_atomic_add:
3878 case ir_intrinsic_shared_atomic_min:
3879 case ir_intrinsic_shared_atomic_max:
3880 case ir_intrinsic_shared_atomic_and:
3881 case ir_intrinsic_shared_atomic_or:
3882 case ir_intrinsic_shared_atomic_xor:
3883 case ir_intrinsic_shared_atomic_exchange:
3884 case ir_intrinsic_shared_atomic_comp_swap:
3885 visit_shared_intrinsic(ir);
3886 return;
3887
3888 case ir_intrinsic_image_load:
3889 case ir_intrinsic_image_store:
3890 case ir_intrinsic_image_atomic_add:
3891 case ir_intrinsic_image_atomic_min:
3892 case ir_intrinsic_image_atomic_max:
3893 case ir_intrinsic_image_atomic_and:
3894 case ir_intrinsic_image_atomic_or:
3895 case ir_intrinsic_image_atomic_xor:
3896 case ir_intrinsic_image_atomic_exchange:
3897 case ir_intrinsic_image_atomic_comp_swap:
3898 case ir_intrinsic_image_size:
3899 case ir_intrinsic_image_samples:
3900 visit_image_intrinsic(ir);
3901 return;
3902
3903 case ir_intrinsic_shader_clock:
3904 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
3905 return;
3906
3907 case ir_intrinsic_vote_all:
3908 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
3909 return;
3910 case ir_intrinsic_vote_any:
3911 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
3912 return;
3913 case ir_intrinsic_vote_eq:
3914 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
3915 return;
3916 case ir_intrinsic_ballot:
3917 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
3918 return;
3919 case ir_intrinsic_read_first_invocation:
3920 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
3921 return;
3922 case ir_intrinsic_read_invocation:
3923 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
3924 return;
3925
3926 case ir_intrinsic_invalid:
3927 case ir_intrinsic_generic_load:
3928 case ir_intrinsic_generic_store:
3929 case ir_intrinsic_generic_atomic_add:
3930 case ir_intrinsic_generic_atomic_and:
3931 case ir_intrinsic_generic_atomic_or:
3932 case ir_intrinsic_generic_atomic_xor:
3933 case ir_intrinsic_generic_atomic_min:
3934 case ir_intrinsic_generic_atomic_max:
3935 case ir_intrinsic_generic_atomic_exchange:
3936 case ir_intrinsic_generic_atomic_comp_swap:
3937 unreachable("Invalid intrinsic");
3938 }
3939 }
3940
3941 void
3942 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
3943 unsigned *array_elements,
3944 uint16_t *index,
3945 st_src_reg *indirect,
3946 unsigned *location)
3947 {
3948 switch (tail->ir_type) {
3949 case ir_type_dereference_record: {
3950 ir_dereference_record *deref_record = tail->as_dereference_record();
3951 const glsl_type *struct_type = deref_record->record->type;
3952 int field_index = deref_record->field_idx;
3953
3954 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
3955
3956 assert(field_index >= 0);
3957 *location += struct_type->record_location_offset(field_index);
3958 break;
3959 }
3960
3961 case ir_type_dereference_array: {
3962 ir_dereference_array *deref_arr = tail->as_dereference_array();
3963
3964 void *mem_ctx = ralloc_parent(deref_arr);
3965 ir_constant *array_index =
3966 deref_arr->array_index->constant_expression_value(mem_ctx);
3967
3968 if (!array_index) {
3969 st_src_reg temp_reg;
3970 st_dst_reg temp_dst;
3971
3972 temp_reg = get_temp(glsl_type::uint_type);
3973 temp_dst = st_dst_reg(temp_reg);
3974 temp_dst.writemask = 1;
3975
3976 deref_arr->array_index->accept(this);
3977 if (*array_elements != 1)
3978 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
3979 else
3980 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
3981
3982 if (indirect->file == PROGRAM_UNDEFINED)
3983 *indirect = temp_reg;
3984 else {
3985 temp_dst = st_dst_reg(*indirect);
3986 temp_dst.writemask = 1;
3987 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
3988 }
3989 } else
3990 *index += array_index->value.u[0] * *array_elements;
3991
3992 *array_elements *= deref_arr->array->type->length;
3993
3994 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
3995 break;
3996 }
3997 default:
3998 break;
3999 }
4000 }
4001
4002 void
4003 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4004 unsigned *array_size,
4005 unsigned *base,
4006 uint16_t *index,
4007 st_src_reg *reladdr,
4008 bool opaque)
4009 {
4010 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4011 unsigned location = 0;
4012 ir_variable *var = ir->variable_referenced();
4013
4014 memset(reladdr, 0, sizeof(*reladdr));
4015 reladdr->file = PROGRAM_UNDEFINED;
4016
4017 *base = 0;
4018 *array_size = 1;
4019
4020 assert(var);
4021 location = var->data.location;
4022 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4023
4024 /*
4025 * If we end up with no indirect then adjust the base to the index,
4026 * and set the array size to 1.
4027 */
4028 if (reladdr->file == PROGRAM_UNDEFINED) {
4029 *base = *index;
4030 *array_size = 1;
4031 }
4032
4033 if (opaque) {
4034 assert(location != 0xffffffff);
4035 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4036 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4037 }
4038 }
4039
4040 st_src_reg
4041 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4042 {
4043 if (offset.reladdr || offset.reladdr2) {
4044 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4045 st_dst_reg tmp_dst = st_dst_reg(tmp);
4046 tmp_dst.writemask = WRITEMASK_XY;
4047 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4048 return tmp;
4049 }
4050
4051 return offset;
4052 }
4053
4054 void
4055 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4056 {
4057 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4058 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4059 st_src_reg levels_src, reladdr;
4060 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4061 glsl_to_tgsi_instruction *inst = NULL;
4062 unsigned opcode = TGSI_OPCODE_NOP;
4063 const glsl_type *sampler_type = ir->sampler->type;
4064 unsigned sampler_array_size = 1, sampler_base = 0;
4065 bool is_cube_array = false, is_cube_shadow = false;
4066 ir_variable *var = ir->sampler->variable_referenced();
4067 unsigned i;
4068
4069 /* if we are a cube array sampler or a cube shadow */
4070 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4071 is_cube_array = sampler_type->sampler_array;
4072 is_cube_shadow = sampler_type->sampler_shadow;
4073 }
4074
4075 if (ir->coordinate) {
4076 ir->coordinate->accept(this);
4077
4078 /* Put our coords in a temp. We'll need to modify them for shadow,
4079 * projection, or LOD, so the only case we'd use it as-is is if
4080 * we're doing plain old texturing. The optimization passes on
4081 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4082 */
4083 coord = get_temp(glsl_type::vec4_type);
4084 coord_dst = st_dst_reg(coord);
4085 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4086 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4087 }
4088
4089 if (ir->projector) {
4090 ir->projector->accept(this);
4091 projector = this->result;
4092 }
4093
4094 /* Storage for our result. Ideally for an assignment we'd be using
4095 * the actual storage for the result here, instead.
4096 */
4097 result_src = get_temp(ir->type);
4098 result_dst = st_dst_reg(result_src);
4099 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4100
4101 switch (ir->op) {
4102 case ir_tex:
4103 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4104 if (ir->offset) {
4105 ir->offset->accept(this);
4106 offset[0] = this->result;
4107 }
4108 break;
4109 case ir_txb:
4110 if (is_cube_array || is_cube_shadow) {
4111 opcode = TGSI_OPCODE_TXB2;
4112 }
4113 else {
4114 opcode = TGSI_OPCODE_TXB;
4115 }
4116 ir->lod_info.bias->accept(this);
4117 lod_info = this->result;
4118 if (ir->offset) {
4119 ir->offset->accept(this);
4120 offset[0] = this->result;
4121 }
4122 break;
4123 case ir_txl:
4124 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4125 opcode = TGSI_OPCODE_TEX_LZ;
4126 } else {
4127 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4128 ir->lod_info.lod->accept(this);
4129 lod_info = this->result;
4130 }
4131 if (ir->offset) {
4132 ir->offset->accept(this);
4133 offset[0] = this->result;
4134 }
4135 break;
4136 case ir_txd:
4137 opcode = TGSI_OPCODE_TXD;
4138 ir->lod_info.grad.dPdx->accept(this);
4139 dx = this->result;
4140 ir->lod_info.grad.dPdy->accept(this);
4141 dy = this->result;
4142 if (ir->offset) {
4143 ir->offset->accept(this);
4144 offset[0] = this->result;
4145 }
4146 break;
4147 case ir_txs:
4148 opcode = TGSI_OPCODE_TXQ;
4149 ir->lod_info.lod->accept(this);
4150 lod_info = this->result;
4151 break;
4152 case ir_query_levels:
4153 opcode = TGSI_OPCODE_TXQ;
4154 lod_info = undef_src;
4155 levels_src = get_temp(ir->type);
4156 break;
4157 case ir_txf:
4158 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4159 opcode = TGSI_OPCODE_TXF_LZ;
4160 } else {
4161 opcode = TGSI_OPCODE_TXF;
4162 ir->lod_info.lod->accept(this);
4163 lod_info = this->result;
4164 }
4165 if (ir->offset) {
4166 ir->offset->accept(this);
4167 offset[0] = this->result;
4168 }
4169 break;
4170 case ir_txf_ms:
4171 opcode = TGSI_OPCODE_TXF;
4172 ir->lod_info.sample_index->accept(this);
4173 sample_index = this->result;
4174 break;
4175 case ir_tg4:
4176 opcode = TGSI_OPCODE_TG4;
4177 ir->lod_info.component->accept(this);
4178 component = this->result;
4179 if (ir->offset) {
4180 ir->offset->accept(this);
4181 if (ir->offset->type->is_array()) {
4182 const glsl_type *elt_type = ir->offset->type->fields.array;
4183 for (i = 0; i < ir->offset->type->length; i++) {
4184 offset[i] = this->result;
4185 offset[i].index += i * type_size(elt_type);
4186 offset[i].type = elt_type->base_type;
4187 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4188 offset[i] = canonicalize_gather_offset(offset[i]);
4189 }
4190 } else {
4191 offset[0] = canonicalize_gather_offset(this->result);
4192 }
4193 }
4194 break;
4195 case ir_lod:
4196 opcode = TGSI_OPCODE_LODQ;
4197 break;
4198 case ir_texture_samples:
4199 opcode = TGSI_OPCODE_TXQS;
4200 break;
4201 case ir_samples_identical:
4202 unreachable("Unexpected ir_samples_identical opcode");
4203 }
4204
4205 if (ir->projector) {
4206 if (opcode == TGSI_OPCODE_TEX) {
4207 /* Slot the projector in as the last component of the coord. */
4208 coord_dst.writemask = WRITEMASK_W;
4209 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4210 coord_dst.writemask = WRITEMASK_XYZW;
4211 opcode = TGSI_OPCODE_TXP;
4212 } else {
4213 st_src_reg coord_w = coord;
4214 coord_w.swizzle = SWIZZLE_WWWW;
4215
4216 /* For the other TEX opcodes there's no projective version
4217 * since the last slot is taken up by LOD info. Do the
4218 * projective divide now.
4219 */
4220 coord_dst.writemask = WRITEMASK_W;
4221 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4222
4223 /* In the case where we have to project the coordinates "by hand,"
4224 * the shadow comparator value must also be projected.
4225 */
4226 st_src_reg tmp_src = coord;
4227 if (ir->shadow_comparator) {
4228 /* Slot the shadow value in as the second to last component of the
4229 * coord.
4230 */
4231 ir->shadow_comparator->accept(this);
4232
4233 tmp_src = get_temp(glsl_type::vec4_type);
4234 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4235
4236 /* Projective division not allowed for array samplers. */
4237 assert(!sampler_type->sampler_array);
4238
4239 tmp_dst.writemask = WRITEMASK_Z;
4240 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4241
4242 tmp_dst.writemask = WRITEMASK_XY;
4243 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4244 }
4245
4246 coord_dst.writemask = WRITEMASK_XYZ;
4247 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4248
4249 coord_dst.writemask = WRITEMASK_XYZW;
4250 coord.swizzle = SWIZZLE_XYZW;
4251 }
4252 }
4253
4254 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4255 * comparator was put in the correct place (and projected) by the code,
4256 * above, that handles by-hand projection.
4257 */
4258 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4259 /* Slot the shadow value in as the second to last component of the
4260 * coord.
4261 */
4262 ir->shadow_comparator->accept(this);
4263
4264 if (is_cube_array) {
4265 cube_sc = get_temp(glsl_type::float_type);
4266 cube_sc_dst = st_dst_reg(cube_sc);
4267 cube_sc_dst.writemask = WRITEMASK_X;
4268 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4269 cube_sc_dst.writemask = WRITEMASK_X;
4270 }
4271 else {
4272 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4273 sampler_type->sampler_array) ||
4274 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4275 coord_dst.writemask = WRITEMASK_W;
4276 } else {
4277 coord_dst.writemask = WRITEMASK_Z;
4278 }
4279 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4280 coord_dst.writemask = WRITEMASK_XYZW;
4281 }
4282 }
4283
4284 if (ir->op == ir_txf_ms) {
4285 coord_dst.writemask = WRITEMASK_W;
4286 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4287 coord_dst.writemask = WRITEMASK_XYZW;
4288 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4289 opcode == TGSI_OPCODE_TXF) {
4290 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4291 coord_dst.writemask = WRITEMASK_W;
4292 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4293 coord_dst.writemask = WRITEMASK_XYZW;
4294 }
4295
4296 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4297
4298 uint16_t index = 0;
4299 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4300 &index, &reladdr, !var->contains_bindless());
4301
4302 sampler.index = index;
4303 if (reladdr.file != PROGRAM_UNDEFINED) {
4304 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4305 *sampler.reladdr = reladdr;
4306 emit_arl(ir, sampler_reladdr, reladdr);
4307 }
4308
4309 st_src_reg bindless;
4310 if (var->contains_bindless()) {
4311 ir->sampler->accept(this);
4312 bindless = this->result;
4313 }
4314
4315 if (opcode == TGSI_OPCODE_TXD)
4316 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4317 else if (opcode == TGSI_OPCODE_TXQ) {
4318 if (ir->op == ir_query_levels) {
4319 /* the level is stored in W */
4320 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4321 result_dst.writemask = WRITEMASK_X;
4322 levels_src.swizzle = SWIZZLE_WWWW;
4323 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4324 } else
4325 inst = emit_asm(ir, opcode, result_dst, lod_info);
4326 } else if (opcode == TGSI_OPCODE_TXQS) {
4327 inst = emit_asm(ir, opcode, result_dst);
4328 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4329 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4330 } else if (opcode == TGSI_OPCODE_TEX2) {
4331 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4332 } else if (opcode == TGSI_OPCODE_TG4) {
4333 if (is_cube_array && ir->shadow_comparator) {
4334 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4335 } else {
4336 inst = emit_asm(ir, opcode, result_dst, coord, component);
4337 }
4338 } else
4339 inst = emit_asm(ir, opcode, result_dst, coord);
4340
4341 if (ir->shadow_comparator)
4342 inst->tex_shadow = GL_TRUE;
4343
4344 if (var->contains_bindless()) {
4345 inst->resource = bindless;
4346 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4347 SWIZZLE_X, SWIZZLE_Y);
4348 } else {
4349 inst->resource = sampler;
4350 inst->sampler_array_size = sampler_array_size;
4351 inst->sampler_base = sampler_base;
4352 }
4353
4354 if (ir->offset) {
4355 if (!inst->tex_offsets)
4356 inst->tex_offsets = rzalloc_array(inst, st_src_reg, MAX_GLSL_TEXTURE_OFFSET);
4357
4358 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET && offset[i].file != PROGRAM_UNDEFINED; i++)
4359 inst->tex_offsets[i] = offset[i];
4360 inst->tex_offset_num_offset = i;
4361 }
4362
4363 inst->tex_target = sampler_type->sampler_index();
4364 inst->tex_type = ir->type->base_type;
4365
4366 this->result = result_src;
4367 }
4368
4369 void
4370 glsl_to_tgsi_visitor::visit(ir_return *ir)
4371 {
4372 assert(!ir->get_value());
4373
4374 emit_asm(ir, TGSI_OPCODE_RET);
4375 }
4376
4377 void
4378 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4379 {
4380 if (ir->condition) {
4381 ir->condition->accept(this);
4382 st_src_reg condition = this->result;
4383
4384 /* Convert the bool condition to a float so we can negate. */
4385 if (native_integers) {
4386 st_src_reg temp = get_temp(ir->condition->type);
4387 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4388 condition, st_src_reg_for_float(1.0));
4389 condition = temp;
4390 }
4391
4392 condition.negate = ~condition.negate;
4393 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4394 } else {
4395 /* unconditional kil */
4396 emit_asm(ir, TGSI_OPCODE_KILL);
4397 }
4398 }
4399
4400 void
4401 glsl_to_tgsi_visitor::visit(ir_if *ir)
4402 {
4403 unsigned if_opcode;
4404 glsl_to_tgsi_instruction *if_inst;
4405
4406 ir->condition->accept(this);
4407 assert(this->result.file != PROGRAM_UNDEFINED);
4408
4409 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4410
4411 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4412
4413 this->instructions.push_tail(if_inst);
4414
4415 visit_exec_list(&ir->then_instructions, this);
4416
4417 if (!ir->else_instructions.is_empty()) {
4418 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4419 visit_exec_list(&ir->else_instructions, this);
4420 }
4421
4422 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4423 }
4424
4425
4426 void
4427 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4428 {
4429 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4430
4431 ir->stream->accept(this);
4432 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4433 }
4434
4435 void
4436 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4437 {
4438 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4439
4440 ir->stream->accept(this);
4441 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4442 }
4443
4444 void
4445 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4446 {
4447 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4448 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4449
4450 emit_asm(ir, TGSI_OPCODE_BARRIER);
4451 }
4452
4453 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4454 {
4455 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4456
4457 result.file = PROGRAM_UNDEFINED;
4458 next_temp = 1;
4459 array_sizes = NULL;
4460 max_num_arrays = 0;
4461 next_array = 0;
4462 num_inputs = 0;
4463 num_outputs = 0;
4464 num_input_arrays = 0;
4465 num_output_arrays = 0;
4466 num_atomics = 0;
4467 num_atomic_arrays = 0;
4468 num_immediates = 0;
4469 num_address_regs = 0;
4470 samplers_used = 0;
4471 images_used = 0;
4472 indirect_addr_consts = false;
4473 wpos_transform_const = -1;
4474 native_integers = false;
4475 mem_ctx = ralloc_context(NULL);
4476 ctx = NULL;
4477 prog = NULL;
4478 precise = 0;
4479 shader_program = NULL;
4480 shader = NULL;
4481 options = NULL;
4482 have_sqrt = false;
4483 have_fma = false;
4484 use_shared_memory = false;
4485 has_tex_txf_lz = false;
4486 variables = NULL;
4487 }
4488
4489 static void var_destroy(struct hash_entry *entry)
4490 {
4491 variable_storage *storage = (variable_storage *)entry->data;
4492
4493 delete storage;
4494 }
4495
4496 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4497 {
4498 _mesa_hash_table_destroy(variables, var_destroy);
4499 free(array_sizes);
4500 ralloc_free(mem_ctx);
4501 }
4502
4503 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4504 {
4505 delete v;
4506 }
4507
4508
4509 /**
4510 * Count resources used by the given gpu program (number of texture
4511 * samplers, etc).
4512 */
4513 static void
4514 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4515 {
4516 v->samplers_used = 0;
4517 v->images_used = 0;
4518 prog->info.textures_used_by_txf = 0;
4519
4520 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4521 if (inst->info->is_tex) {
4522 for (int i = 0; i < inst->sampler_array_size; i++) {
4523 unsigned idx = inst->sampler_base + i;
4524 v->samplers_used |= 1u << idx;
4525
4526 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4527 v->sampler_types[idx] = inst->tex_type;
4528 v->sampler_targets[idx] =
4529 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4530
4531 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4532 prog->info.textures_used_by_txf |= 1u << idx;
4533 }
4534 }
4535 }
4536
4537 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4538 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4539
4540 if (inst->resource.file != PROGRAM_UNDEFINED && (
4541 is_resource_instruction(inst->op) ||
4542 inst->op == TGSI_OPCODE_STORE)) {
4543 if (inst->resource.file == PROGRAM_MEMORY) {
4544 v->use_shared_memory = true;
4545 } else if (inst->resource.file == PROGRAM_IMAGE) {
4546 for (int i = 0; i < inst->sampler_array_size; i++) {
4547 unsigned idx = inst->sampler_base + i;
4548 v->images_used |= 1 << idx;
4549 v->image_targets[idx] =
4550 st_translate_texture_target(inst->tex_target, false);
4551 v->image_formats[idx] = inst->image_format;
4552 }
4553 }
4554 }
4555 }
4556 prog->SamplersUsed = v->samplers_used;
4557
4558 if (v->shader_program != NULL)
4559 _mesa_update_shader_textures_used(v->shader_program, prog);
4560 }
4561
4562 /**
4563 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4564 * are read from the given src in this instruction
4565 */
4566 static int
4567 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4568 {
4569 int read_mask = 0, comp;
4570
4571 /* Now, given the src swizzle and the written channels, find which
4572 * components are actually read
4573 */
4574 for (comp = 0; comp < 4; ++comp) {
4575 const unsigned coord = GET_SWZ(src.swizzle, comp);
4576 assert(coord < 4);
4577 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4578 read_mask |= 1 << coord;
4579 }
4580
4581 return read_mask;
4582 }
4583
4584 /**
4585 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4586 * instruction is the first instruction to write to register T0. There are
4587 * several lowering passes done in GLSL IR (e.g. branches and
4588 * relative addressing) that create a large number of conditional assignments
4589 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4590 *
4591 * Here is why this conversion is safe:
4592 * CMP T0, T1 T2 T0 can be expanded to:
4593 * if (T1 < 0.0)
4594 * MOV T0, T2;
4595 * else
4596 * MOV T0, T0;
4597 *
4598 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4599 * as the original program. If (T1 < 0.0) evaluates to false, executing
4600 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4601 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4602 * because any instruction that was going to read from T0 after this was going
4603 * to read a garbage value anyway.
4604 */
4605 void
4606 glsl_to_tgsi_visitor::simplify_cmp(void)
4607 {
4608 int tempWritesSize = 0;
4609 unsigned *tempWrites = NULL;
4610 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4611
4612 memset(outputWrites, 0, sizeof(outputWrites));
4613
4614 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4615 unsigned prevWriteMask = 0;
4616
4617 /* Give up if we encounter relative addressing or flow control. */
4618 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4619 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4620 inst->info->is_branch ||
4621 inst->op == TGSI_OPCODE_CONT ||
4622 inst->op == TGSI_OPCODE_END ||
4623 inst->op == TGSI_OPCODE_RET) {
4624 break;
4625 }
4626
4627 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4628 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4629 prevWriteMask = outputWrites[inst->dst[0].index];
4630 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4631 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4632 if (inst->dst[0].index >= tempWritesSize) {
4633 const int inc = 4096;
4634
4635 tempWrites = (unsigned*)
4636 realloc(tempWrites,
4637 (tempWritesSize + inc) * sizeof(unsigned));
4638 if (!tempWrites)
4639 return;
4640
4641 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4642 tempWritesSize += inc;
4643 }
4644
4645 prevWriteMask = tempWrites[inst->dst[0].index];
4646 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4647 } else
4648 continue;
4649
4650 /* For a CMP to be considered a conditional write, the destination
4651 * register and source register two must be the same. */
4652 if (inst->op == TGSI_OPCODE_CMP
4653 && !(inst->dst[0].writemask & prevWriteMask)
4654 && inst->src[2].file == inst->dst[0].file
4655 && inst->src[2].index == inst->dst[0].index
4656 && inst->dst[0].writemask == get_src_arg_mask(inst->dst[0], inst->src[2])) {
4657
4658 inst->op = TGSI_OPCODE_MOV;
4659 inst->info = tgsi_get_opcode_info(inst->op);
4660 inst->src[0] = inst->src[1];
4661 }
4662 }
4663
4664 free(tempWrites);
4665 }
4666
4667 static void
4668 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4669 {
4670 if (src && src->file == PROGRAM_TEMPORARY) {
4671 int old_idx = src->index;
4672 if (renames[old_idx].valid)
4673 src->index = renames[old_idx].new_reg;
4674 }
4675 }
4676
4677 /* Replaces all references to a temporary register index with another index. */
4678 void
4679 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4680 {
4681 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4682 unsigned j;
4683 for (j = 0; j < num_inst_src_regs(inst); j++) {
4684 rename_temp_handle_src(renames, &inst->src[j]);
4685 rename_temp_handle_src(renames, inst->src[j].reladdr);
4686 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4687 }
4688
4689 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4690 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4691 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4692 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4693 }
4694
4695 rename_temp_handle_src(renames, &inst->resource);
4696 rename_temp_handle_src(renames, inst->resource.reladdr);
4697 rename_temp_handle_src(renames, inst->resource.reladdr2);
4698
4699 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4700 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4701 int old_idx = inst->dst[j].index;
4702 if (renames[old_idx].valid)
4703 inst->dst[j].index = renames[old_idx].new_reg;
4704 }
4705 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4706 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4707 }
4708 }
4709 }
4710
4711 void
4712 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4713 {
4714 int depth = 0; /* loop depth */
4715 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4716 unsigned i = 0, j;
4717
4718 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4719 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4720 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4721 if (first_writes[inst->dst[j].index] == -1)
4722 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4723 }
4724 }
4725
4726 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4727 if(depth++ == 0)
4728 loop_start = i;
4729 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4730 if (--depth == 0)
4731 loop_start = -1;
4732 }
4733 assert(depth >= 0);
4734 i++;
4735 }
4736 }
4737
4738 void
4739 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4740 {
4741 int depth = 0; /* loop depth */
4742 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4743 unsigned i = 0, j;
4744
4745 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4746 for (j = 0; j < num_inst_src_regs(inst); j++) {
4747 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4748 if (first_reads[inst->src[j].index] == -1)
4749 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4750 }
4751 }
4752 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4753 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4754 if (first_reads[inst->tex_offsets[j].index] == -1)
4755 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4756 }
4757 }
4758 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4759 if(depth++ == 0)
4760 loop_start = i;
4761 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4762 if (--depth == 0)
4763 loop_start = -1;
4764 }
4765 assert(depth >= 0);
4766 i++;
4767 }
4768 }
4769
4770 void
4771 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
4772 {
4773 int depth = 0; /* loop depth */
4774 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4775 unsigned i = 0, j;
4776 int k;
4777 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4778 for (j = 0; j < num_inst_src_regs(inst); j++) {
4779 if (inst->src[j].file == PROGRAM_TEMPORARY)
4780 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
4781 }
4782 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4783 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4784 if (first_writes[inst->dst[j].index] == -1)
4785 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4786 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
4787 }
4788 }
4789 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4790 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
4791 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
4792 }
4793 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4794 if(depth++ == 0)
4795 loop_start = i;
4796 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4797 if (--depth == 0) {
4798 loop_start = -1;
4799 for (k = 0; k < this->next_temp; k++) {
4800 if (last_reads[k] == -2) {
4801 last_reads[k] = i;
4802 }
4803 }
4804 }
4805 }
4806 assert(depth >= 0);
4807 i++;
4808 }
4809 }
4810
4811 void
4812 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
4813 {
4814 int depth = 0; /* loop depth */
4815 int i = 0, k;
4816 unsigned j;
4817
4818 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4819 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4820 if (inst->dst[j].file == PROGRAM_TEMPORARY)
4821 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
4822 }
4823
4824 if (inst->op == TGSI_OPCODE_BGNLOOP)
4825 depth++;
4826 else if (inst->op == TGSI_OPCODE_ENDLOOP)
4827 if (--depth == 0) {
4828 for (k = 0; k < this->next_temp; k++) {
4829 if (last_writes[k] == -2) {
4830 last_writes[k] = i;
4831 }
4832 }
4833 }
4834 assert(depth >= 0);
4835 i++;
4836 }
4837 }
4838
4839 /*
4840 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4841 * channels for copy propagation and updates following instructions to
4842 * use the original versions.
4843 *
4844 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4845 * will occur. As an example, a TXP production before this pass:
4846 *
4847 * 0: MOV TEMP[1], INPUT[4].xyyy;
4848 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4849 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4850 *
4851 * and after:
4852 *
4853 * 0: MOV TEMP[1], INPUT[4].xyyy;
4854 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4855 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4856 *
4857 * which allows for dead code elimination on TEMP[1]'s writes.
4858 */
4859 void
4860 glsl_to_tgsi_visitor::copy_propagate(void)
4861 {
4862 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
4863 glsl_to_tgsi_instruction *,
4864 this->next_temp * 4);
4865 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
4866 int level = 0;
4867
4868 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4869 assert(inst->dst[0].file != PROGRAM_TEMPORARY
4870 || inst->dst[0].index < this->next_temp);
4871
4872 /* First, do any copy propagation possible into the src regs. */
4873 for (int r = 0; r < 3; r++) {
4874 glsl_to_tgsi_instruction *first = NULL;
4875 bool good = true;
4876 int acp_base = inst->src[r].index * 4;
4877
4878 if (inst->src[r].file != PROGRAM_TEMPORARY ||
4879 inst->src[r].reladdr ||
4880 inst->src[r].reladdr2)
4881 continue;
4882
4883 /* See if we can find entries in the ACP consisting of MOVs
4884 * from the same src register for all the swizzled channels
4885 * of this src register reference.
4886 */
4887 for (int i = 0; i < 4; i++) {
4888 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4889 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
4890
4891 if (!copy_chan) {
4892 good = false;
4893 break;
4894 }
4895
4896 assert(acp_level[acp_base + src_chan] <= level);
4897
4898 if (!first) {
4899 first = copy_chan;
4900 } else {
4901 if (first->src[0].file != copy_chan->src[0].file ||
4902 first->src[0].index != copy_chan->src[0].index ||
4903 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
4904 first->src[0].index2D != copy_chan->src[0].index2D) {
4905 good = false;
4906 break;
4907 }
4908 }
4909 }
4910
4911 if (good) {
4912 /* We've now validated that we can copy-propagate to
4913 * replace this src register reference. Do it.
4914 */
4915 inst->src[r].file = first->src[0].file;
4916 inst->src[r].index = first->src[0].index;
4917 inst->src[r].index2D = first->src[0].index2D;
4918 inst->src[r].has_index2 = first->src[0].has_index2;
4919 inst->src[r].double_reg2 = first->src[0].double_reg2;
4920 inst->src[r].array_id = first->src[0].array_id;
4921
4922 int swizzle = 0;
4923 for (int i = 0; i < 4; i++) {
4924 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4925 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
4926 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
4927 }
4928 inst->src[r].swizzle = swizzle;
4929 }
4930 }
4931
4932 switch (inst->op) {
4933 case TGSI_OPCODE_BGNLOOP:
4934 case TGSI_OPCODE_ENDLOOP:
4935 /* End of a basic block, clear the ACP entirely. */
4936 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
4937 break;
4938
4939 case TGSI_OPCODE_IF:
4940 case TGSI_OPCODE_UIF:
4941 ++level;
4942 break;
4943
4944 case TGSI_OPCODE_ENDIF:
4945 case TGSI_OPCODE_ELSE:
4946 /* Clear all channels written inside the block from the ACP, but
4947 * leaving those that were not touched.
4948 */
4949 for (int r = 0; r < this->next_temp; r++) {
4950 for (int c = 0; c < 4; c++) {
4951 if (!acp[4 * r + c])
4952 continue;
4953
4954 if (acp_level[4 * r + c] >= level)
4955 acp[4 * r + c] = NULL;
4956 }
4957 }
4958 if (inst->op == TGSI_OPCODE_ENDIF)
4959 --level;
4960 break;
4961
4962 default:
4963 /* Continuing the block, clear any written channels from
4964 * the ACP.
4965 */
4966 for (int d = 0; d < 2; d++) {
4967 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
4968 /* Any temporary might be written, so no copy propagation
4969 * across this instruction.
4970 */
4971 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
4972 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
4973 inst->dst[d].reladdr) {
4974 /* Any output might be written, so no copy propagation
4975 * from outputs across this instruction.
4976 */
4977 for (int r = 0; r < this->next_temp; r++) {
4978 for (int c = 0; c < 4; c++) {
4979 if (!acp[4 * r + c])
4980 continue;
4981
4982 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
4983 acp[4 * r + c] = NULL;
4984 }
4985 }
4986 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
4987 inst->dst[d].file == PROGRAM_OUTPUT) {
4988 /* Clear where it's used as dst. */
4989 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
4990 for (int c = 0; c < 4; c++) {
4991 if (inst->dst[d].writemask & (1 << c))
4992 acp[4 * inst->dst[d].index + c] = NULL;
4993 }
4994 }
4995
4996 /* Clear where it's used as src. */
4997 for (int r = 0; r < this->next_temp; r++) {
4998 for (int c = 0; c < 4; c++) {
4999 if (!acp[4 * r + c])
5000 continue;
5001
5002 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5003
5004 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5005 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5006 inst->dst[d].writemask & (1 << src_chan)) {
5007 acp[4 * r + c] = NULL;
5008 }
5009 }
5010 }
5011 }
5012 }
5013 break;
5014 }
5015
5016 /* If this is a copy, add it to the ACP. */
5017 if (inst->op == TGSI_OPCODE_MOV &&
5018 inst->dst[0].file == PROGRAM_TEMPORARY &&
5019 !(inst->dst[0].file == inst->src[0].file &&
5020 inst->dst[0].index == inst->src[0].index) &&
5021 !inst->dst[0].reladdr &&
5022 !inst->dst[0].reladdr2 &&
5023 !inst->saturate &&
5024 inst->src[0].file != PROGRAM_ARRAY &&
5025 (inst->src[0].file != PROGRAM_OUTPUT ||
5026 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5027 !inst->src[0].reladdr &&
5028 !inst->src[0].reladdr2 &&
5029 !inst->src[0].negate &&
5030 !inst->src[0].abs) {
5031 for (int i = 0; i < 4; i++) {
5032 if (inst->dst[0].writemask & (1 << i)) {
5033 acp[4 * inst->dst[0].index + i] = inst;
5034 acp_level[4 * inst->dst[0].index + i] = level;
5035 }
5036 }
5037 }
5038 }
5039
5040 ralloc_free(acp_level);
5041 ralloc_free(acp);
5042 }
5043
5044 static void
5045 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5046 {
5047 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5048 /* Clear where it's used as src. */
5049 int swz = GET_SWZ(reladdr->swizzle, 0);
5050 writes[4 * reladdr->index + swz] = NULL;
5051 }
5052 }
5053
5054 /*
5055 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5056 * code elimination.
5057 *
5058 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5059 * will occur. As an example, a TXP production after copy propagation but
5060 * before this pass:
5061 *
5062 * 0: MOV TEMP[1], INPUT[4].xyyy;
5063 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5064 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5065 *
5066 * and after this pass:
5067 *
5068 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5069 */
5070 int
5071 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5072 {
5073 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5074 glsl_to_tgsi_instruction *,
5075 this->next_temp * 4);
5076 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5077 int level = 0;
5078 int removed = 0;
5079
5080 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5081 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5082 || inst->dst[0].index < this->next_temp);
5083
5084 switch (inst->op) {
5085 case TGSI_OPCODE_BGNLOOP:
5086 case TGSI_OPCODE_ENDLOOP:
5087 case TGSI_OPCODE_CONT:
5088 case TGSI_OPCODE_BRK:
5089 /* End of a basic block, clear the write array entirely.
5090 *
5091 * This keeps us from killing dead code when the writes are
5092 * on either side of a loop, even when the register isn't touched
5093 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5094 * dead code of this type, so it shouldn't make a difference as long as
5095 * the dead code elimination pass in the GLSL compiler does its job.
5096 */
5097 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5098 break;
5099
5100 case TGSI_OPCODE_ENDIF:
5101 case TGSI_OPCODE_ELSE:
5102 /* Promote the recorded level of all channels written inside the
5103 * preceding if or else block to the level above the if/else block.
5104 */
5105 for (int r = 0; r < this->next_temp; r++) {
5106 for (int c = 0; c < 4; c++) {
5107 if (!writes[4 * r + c])
5108 continue;
5109
5110 if (write_level[4 * r + c] == level)
5111 write_level[4 * r + c] = level-1;
5112 }
5113 }
5114 if(inst->op == TGSI_OPCODE_ENDIF)
5115 --level;
5116 break;
5117
5118 case TGSI_OPCODE_IF:
5119 case TGSI_OPCODE_UIF:
5120 ++level;
5121 /* fallthrough to default case to mark the condition as read */
5122 default:
5123 /* Continuing the block, clear any channels from the write array that
5124 * are read by this instruction.
5125 */
5126 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5127 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5128 /* Any temporary might be read, so no dead code elimination
5129 * across this instruction.
5130 */
5131 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5132 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5133 /* Clear where it's used as src. */
5134 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5135 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5136 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5137 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5138
5139 for (int c = 0; c < 4; c++) {
5140 if (src_chans & (1 << c))
5141 writes[4 * inst->src[i].index + c] = NULL;
5142 }
5143 }
5144 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5145 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5146 }
5147 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5148 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5149 /* Any temporary might be read, so no dead code elimination
5150 * across this instruction.
5151 */
5152 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5153 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5154 /* Clear where it's used as src. */
5155 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5156 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5157 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5158 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5159
5160 for (int c = 0; c < 4; c++) {
5161 if (src_chans & (1 << c))
5162 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5163 }
5164 }
5165 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5166 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5167 }
5168
5169 if (inst->resource.file == PROGRAM_TEMPORARY) {
5170 int src_chans;
5171
5172 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5173 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5174 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5175 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5176
5177 for (int c = 0; c < 4; c++) {
5178 if (src_chans & (1 << c))
5179 writes[4 * inst->resource.index + c] = NULL;
5180 }
5181 }
5182 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5183 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5184
5185 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5186 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5187 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5188 }
5189 break;
5190 }
5191
5192 /* If this instruction writes to a temporary, add it to the write array.
5193 * If there is already an instruction in the write array for one or more
5194 * of the channels, flag that channel write as dead.
5195 */
5196 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5197 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5198 !inst->dst[i].reladdr) {
5199 for (int c = 0; c < 4; c++) {
5200 if (inst->dst[i].writemask & (1 << c)) {
5201 if (writes[4 * inst->dst[i].index + c]) {
5202 if (write_level[4 * inst->dst[i].index + c] < level)
5203 continue;
5204 else
5205 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5206 }
5207 writes[4 * inst->dst[i].index + c] = inst;
5208 write_level[4 * inst->dst[i].index + c] = level;
5209 }
5210 }
5211 }
5212 }
5213 }
5214
5215 /* Anything still in the write array at this point is dead code. */
5216 for (int r = 0; r < this->next_temp; r++) {
5217 for (int c = 0; c < 4; c++) {
5218 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5219 if (inst)
5220 inst->dead_mask |= (1 << c);
5221 }
5222 }
5223
5224 /* Now actually remove the instructions that are completely dead and update
5225 * the writemask of other instructions with dead channels.
5226 */
5227 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5228 if (!inst->dead_mask || !inst->dst[0].writemask)
5229 continue;
5230 /* No amount of dead masks should remove memory stores */
5231 if (inst->info->is_store)
5232 continue;
5233
5234 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5235 inst->remove();
5236 delete inst;
5237 removed++;
5238 } else {
5239 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5240 if (inst->dead_mask == WRITEMASK_XY ||
5241 inst->dead_mask == WRITEMASK_ZW)
5242 inst->dst[0].writemask &= ~(inst->dead_mask);
5243 } else
5244 inst->dst[0].writemask &= ~(inst->dead_mask);
5245 }
5246 }
5247
5248 ralloc_free(write_level);
5249 ralloc_free(writes);
5250
5251 return removed;
5252 }
5253
5254 /* merge DFRACEXP instructions into one. */
5255 void
5256 glsl_to_tgsi_visitor::merge_two_dsts(void)
5257 {
5258 /* We never delete inst, but we may delete its successor. */
5259 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5260 glsl_to_tgsi_instruction *inst2;
5261 unsigned defined;
5262
5263 if (num_inst_dst_regs(inst) != 2)
5264 continue;
5265
5266 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5267 inst->dst[1].file != PROGRAM_UNDEFINED)
5268 continue;
5269
5270 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5271 inst->dst[1].file != PROGRAM_UNDEFINED);
5272
5273 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5274 defined = 1;
5275 else
5276 defined = 0;
5277
5278 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5279 while (!inst2->is_tail_sentinel()) {
5280 if (inst->op == inst2->op &&
5281 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5282 inst->src[0].file == inst2->src[0].file &&
5283 inst->src[0].index == inst2->src[0].index &&
5284 inst->src[0].type == inst2->src[0].type &&
5285 inst->src[0].swizzle == inst2->src[0].swizzle)
5286 break;
5287 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5288 }
5289
5290 if (inst2->is_tail_sentinel()) {
5291 /* Undefined destinations are not allowed, substitute with an unused
5292 * temporary register.
5293 */
5294 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5295 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5296 inst->dst[defined ^ 1].writemask = 0;
5297 continue;
5298 }
5299
5300 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5301 inst2->remove();
5302 delete inst2;
5303 }
5304 }
5305
5306 /* Merges temporary registers together where possible to reduce the number of
5307 * registers needed to run a program.
5308 *
5309 * Produces optimal code only after copy propagation and dead code elimination
5310 * have been run. */
5311 void
5312 glsl_to_tgsi_visitor::merge_registers(void)
5313 {
5314 struct lifetime *lifetimes =
5315 rzalloc_array(mem_ctx, struct lifetime, this->next_temp);
5316
5317 if (get_temp_registers_required_lifetimes(mem_ctx, &this->instructions,
5318 this->next_temp, lifetimes)) {
5319 struct rename_reg_pair *renames =
5320 rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5321 get_temp_registers_remapping(mem_ctx, this->next_temp, lifetimes, renames);
5322 rename_temp_registers(renames);
5323 ralloc_free(renames);
5324 }
5325
5326 ralloc_free(lifetimes);
5327 }
5328
5329 /* Reassign indices to temporary registers by reusing unused indices created
5330 * by optimization passes. */
5331 void
5332 glsl_to_tgsi_visitor::renumber_registers(void)
5333 {
5334 int i = 0;
5335 int new_index = 0;
5336 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5337 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5338
5339 for (i = 0; i < this->next_temp; i++) {
5340 first_writes[i] = -1;
5341 }
5342 get_first_temp_write(first_writes);
5343
5344 for (i = 0; i < this->next_temp; i++) {
5345 if (first_writes[i] < 0) continue;
5346 if (i != new_index) {
5347 renames[i].new_reg = new_index;
5348 renames[i].valid = true;
5349 }
5350 new_index++;
5351 }
5352
5353 rename_temp_registers(renames);
5354 this->next_temp = new_index;
5355 ralloc_free(renames);
5356 ralloc_free(first_writes);
5357 }
5358
5359 /* ------------------------- TGSI conversion stuff -------------------------- */
5360
5361 /**
5362 * Intermediate state used during shader translation.
5363 */
5364 struct st_translate {
5365 struct ureg_program *ureg;
5366
5367 unsigned temps_size;
5368 struct ureg_dst *temps;
5369
5370 struct ureg_dst *arrays;
5371 unsigned num_temp_arrays;
5372 struct ureg_src *constants;
5373 int num_constants;
5374 struct ureg_src *immediates;
5375 int num_immediates;
5376 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5377 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5378 struct ureg_dst address[3];
5379 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5380 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5381 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5382 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5383 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5384 struct ureg_src shared_memory;
5385 unsigned *array_sizes;
5386 struct inout_decl *input_decls;
5387 unsigned num_input_decls;
5388 struct inout_decl *output_decls;
5389 unsigned num_output_decls;
5390
5391 const ubyte *inputMapping;
5392 const ubyte *outputMapping;
5393
5394 unsigned procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5395 bool need_uarl;
5396 };
5397
5398 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5399 unsigned
5400 _mesa_sysval_to_semantic(unsigned sysval)
5401 {
5402 switch (sysval) {
5403 /* Vertex shader */
5404 case SYSTEM_VALUE_VERTEX_ID:
5405 return TGSI_SEMANTIC_VERTEXID;
5406 case SYSTEM_VALUE_INSTANCE_ID:
5407 return TGSI_SEMANTIC_INSTANCEID;
5408 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5409 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5410 case SYSTEM_VALUE_BASE_VERTEX:
5411 return TGSI_SEMANTIC_BASEVERTEX;
5412 case SYSTEM_VALUE_BASE_INSTANCE:
5413 return TGSI_SEMANTIC_BASEINSTANCE;
5414 case SYSTEM_VALUE_DRAW_ID:
5415 return TGSI_SEMANTIC_DRAWID;
5416
5417 /* Geometry shader */
5418 case SYSTEM_VALUE_INVOCATION_ID:
5419 return TGSI_SEMANTIC_INVOCATIONID;
5420
5421 /* Fragment shader */
5422 case SYSTEM_VALUE_FRAG_COORD:
5423 return TGSI_SEMANTIC_POSITION;
5424 case SYSTEM_VALUE_FRONT_FACE:
5425 return TGSI_SEMANTIC_FACE;
5426 case SYSTEM_VALUE_SAMPLE_ID:
5427 return TGSI_SEMANTIC_SAMPLEID;
5428 case SYSTEM_VALUE_SAMPLE_POS:
5429 return TGSI_SEMANTIC_SAMPLEPOS;
5430 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5431 return TGSI_SEMANTIC_SAMPLEMASK;
5432 case SYSTEM_VALUE_HELPER_INVOCATION:
5433 return TGSI_SEMANTIC_HELPER_INVOCATION;
5434
5435 /* Tessellation shader */
5436 case SYSTEM_VALUE_TESS_COORD:
5437 return TGSI_SEMANTIC_TESSCOORD;
5438 case SYSTEM_VALUE_VERTICES_IN:
5439 return TGSI_SEMANTIC_VERTICESIN;
5440 case SYSTEM_VALUE_PRIMITIVE_ID:
5441 return TGSI_SEMANTIC_PRIMID;
5442 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5443 return TGSI_SEMANTIC_TESSOUTER;
5444 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5445 return TGSI_SEMANTIC_TESSINNER;
5446
5447 /* Compute shader */
5448 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5449 return TGSI_SEMANTIC_THREAD_ID;
5450 case SYSTEM_VALUE_WORK_GROUP_ID:
5451 return TGSI_SEMANTIC_BLOCK_ID;
5452 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5453 return TGSI_SEMANTIC_GRID_SIZE;
5454 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5455 return TGSI_SEMANTIC_BLOCK_SIZE;
5456
5457 /* ARB_shader_ballot */
5458 case SYSTEM_VALUE_SUBGROUP_SIZE:
5459 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5460 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5461 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5462 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5463 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5464 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5465 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5466 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5467 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5468 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5469 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5470 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5471 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5472
5473 /* Unhandled */
5474 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5475 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5476 case SYSTEM_VALUE_VERTEX_CNT:
5477 default:
5478 assert(!"Unexpected SYSTEM_VALUE_ enum");
5479 return TGSI_SEMANTIC_COUNT;
5480 }
5481 }
5482
5483 /**
5484 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5485 */
5486 static struct ureg_src
5487 emit_immediate(struct st_translate *t,
5488 gl_constant_value values[4],
5489 GLenum type, int size)
5490 {
5491 struct ureg_program *ureg = t->ureg;
5492
5493 switch(type)
5494 {
5495 case GL_FLOAT:
5496 return ureg_DECL_immediate(ureg, &values[0].f, size);
5497 case GL_DOUBLE:
5498 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5499 case GL_INT64_ARB:
5500 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5501 case GL_UNSIGNED_INT64_ARB:
5502 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5503 case GL_INT:
5504 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5505 case GL_UNSIGNED_INT:
5506 case GL_BOOL:
5507 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5508 default:
5509 assert(!"should not get here - type must be float, int, uint, or bool");
5510 return ureg_src_undef();
5511 }
5512 }
5513
5514 /**
5515 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5516 */
5517 static struct ureg_dst
5518 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5519 unsigned array_id)
5520 {
5521 unsigned array;
5522
5523 switch(file) {
5524 case PROGRAM_UNDEFINED:
5525 return ureg_dst_undef();
5526
5527 case PROGRAM_TEMPORARY:
5528 /* Allocate space for temporaries on demand. */
5529 if (index >= t->temps_size) {
5530 const int inc = align(index - t->temps_size + 1, 4096);
5531
5532 t->temps = (struct ureg_dst*)
5533 realloc(t->temps,
5534 (t->temps_size + inc) * sizeof(struct ureg_dst));
5535 if (!t->temps)
5536 return ureg_dst_undef();
5537
5538 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5539 t->temps_size += inc;
5540 }
5541
5542 if (ureg_dst_is_undef(t->temps[index]))
5543 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5544
5545 return t->temps[index];
5546
5547 case PROGRAM_ARRAY:
5548 assert(array_id && array_id <= t->num_temp_arrays);
5549 array = array_id - 1;
5550
5551 if (ureg_dst_is_undef(t->arrays[array]))
5552 t->arrays[array] = ureg_DECL_array_temporary(
5553 t->ureg, t->array_sizes[array], TRUE);
5554
5555 return ureg_dst_array_offset(t->arrays[array], index);
5556
5557 case PROGRAM_OUTPUT:
5558 if (!array_id) {
5559 if (t->procType == PIPE_SHADER_FRAGMENT)
5560 assert(index < 2 * FRAG_RESULT_MAX);
5561 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5562 t->procType == PIPE_SHADER_TESS_EVAL)
5563 assert(index < VARYING_SLOT_TESS_MAX);
5564 else
5565 assert(index < VARYING_SLOT_MAX);
5566
5567 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5568 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5569 return t->outputs[t->outputMapping[index]];
5570 }
5571 else {
5572 struct inout_decl *decl = find_inout_array(t->output_decls, t->num_output_decls, array_id);
5573 unsigned mesa_index = decl->mesa_index;
5574 int slot = t->outputMapping[mesa_index];
5575
5576 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5577
5578 struct ureg_dst dst = t->outputs[slot];
5579 dst.ArrayID = array_id;
5580 return ureg_dst_array_offset(dst, index - mesa_index);
5581 }
5582
5583 case PROGRAM_ADDRESS:
5584 return t->address[index];
5585
5586 default:
5587 assert(!"unknown dst register file");
5588 return ureg_dst_undef();
5589 }
5590 }
5591
5592 static struct ureg_src
5593 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5594
5595 static struct ureg_src
5596 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5597 unsigned addr_index)
5598 {
5599 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5600 return ureg_src(t->address[addr_index]);
5601
5602 return translate_src(t, reladdr);
5603 }
5604
5605 /**
5606 * Create a TGSI ureg_dst register from an st_dst_reg.
5607 */
5608 static struct ureg_dst
5609 translate_dst(struct st_translate *t,
5610 const st_dst_reg *dst_reg,
5611 bool saturate)
5612 {
5613 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5614 dst_reg->array_id);
5615
5616 if (dst.File == TGSI_FILE_NULL)
5617 return dst;
5618
5619 dst = ureg_writemask(dst, dst_reg->writemask);
5620
5621 if (saturate)
5622 dst = ureg_saturate(dst);
5623
5624 if (dst_reg->reladdr != NULL) {
5625 assert(dst_reg->file != PROGRAM_TEMPORARY);
5626 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5627 }
5628
5629 if (dst_reg->has_index2) {
5630 if (dst_reg->reladdr2)
5631 dst = ureg_dst_dimension_indirect(dst,
5632 translate_addr(t, dst_reg->reladdr2, 1),
5633 dst_reg->index2D);
5634 else
5635 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5636 }
5637
5638 return dst;
5639 }
5640
5641 /**
5642 * Create a TGSI ureg_src register from an st_src_reg.
5643 */
5644 static struct ureg_src
5645 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5646 {
5647 struct ureg_src src;
5648 int index = src_reg->index;
5649 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5650
5651 switch(src_reg->file) {
5652 case PROGRAM_UNDEFINED:
5653 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5654 break;
5655
5656 case PROGRAM_TEMPORARY:
5657 case PROGRAM_ARRAY:
5658 src = ureg_src(dst_register(t, src_reg->file, src_reg->index, src_reg->array_id));
5659 break;
5660
5661 case PROGRAM_OUTPUT: {
5662 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index, src_reg->array_id);
5663 assert(dst.WriteMask != 0);
5664 unsigned shift = ffs(dst.WriteMask) - 1;
5665 src = ureg_swizzle(ureg_src(dst),
5666 shift,
5667 MIN2(shift + 1, 3),
5668 MIN2(shift + 2, 3),
5669 MIN2(shift + 3, 3));
5670 break;
5671 }
5672
5673 case PROGRAM_UNIFORM:
5674 assert(src_reg->index >= 0);
5675 src = src_reg->index < t->num_constants ?
5676 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5677 break;
5678 case PROGRAM_STATE_VAR:
5679 case PROGRAM_CONSTANT: /* ie, immediate */
5680 if (src_reg->has_index2)
5681 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
5682 else
5683 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
5684 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5685 break;
5686
5687 case PROGRAM_IMMEDIATE:
5688 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
5689 src = t->immediates[src_reg->index];
5690 break;
5691
5692 case PROGRAM_INPUT:
5693 /* GLSL inputs are 64-bit containers, so we have to
5694 * map back to the original index and add the offset after
5695 * mapping. */
5696 index -= double_reg2;
5697 if (!src_reg->array_id) {
5698 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
5699 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
5700 src = t->inputs[t->inputMapping[index] + double_reg2];
5701 }
5702 else {
5703 struct inout_decl *decl = find_inout_array(t->input_decls, t->num_input_decls,
5704 src_reg->array_id);
5705 unsigned mesa_index = decl->mesa_index;
5706 int slot = t->inputMapping[mesa_index];
5707
5708 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
5709
5710 src = t->inputs[slot];
5711 src.ArrayID = src_reg->array_id;
5712 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
5713 }
5714 break;
5715
5716 case PROGRAM_ADDRESS:
5717 src = ureg_src(t->address[src_reg->index]);
5718 break;
5719
5720 case PROGRAM_SYSTEM_VALUE:
5721 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
5722 src = t->systemValues[src_reg->index];
5723 break;
5724
5725 case PROGRAM_HW_ATOMIC:
5726 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
5727 src_reg->array_id);
5728 break;
5729
5730 default:
5731 assert(!"unknown src register file");
5732 return ureg_src_undef();
5733 }
5734
5735 if (src_reg->has_index2) {
5736 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5737 * and UBO constant buffers (buffer, position).
5738 */
5739 if (src_reg->reladdr2)
5740 src = ureg_src_dimension_indirect(src,
5741 translate_addr(t, src_reg->reladdr2, 1),
5742 src_reg->index2D);
5743 else
5744 src = ureg_src_dimension(src, src_reg->index2D);
5745 }
5746
5747 src = ureg_swizzle(src,
5748 GET_SWZ(src_reg->swizzle, 0) & 0x3,
5749 GET_SWZ(src_reg->swizzle, 1) & 0x3,
5750 GET_SWZ(src_reg->swizzle, 2) & 0x3,
5751 GET_SWZ(src_reg->swizzle, 3) & 0x3);
5752
5753 if (src_reg->abs)
5754 src = ureg_abs(src);
5755
5756 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
5757 src = ureg_negate(src);
5758
5759 if (src_reg->reladdr != NULL) {
5760 assert(src_reg->file != PROGRAM_TEMPORARY);
5761 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
5762 }
5763
5764 return src;
5765 }
5766
5767 static struct tgsi_texture_offset
5768 translate_tex_offset(struct st_translate *t,
5769 const st_src_reg *in_offset)
5770 {
5771 struct tgsi_texture_offset offset;
5772 struct ureg_src src = translate_src(t, in_offset);
5773
5774 offset.File = src.File;
5775 offset.Index = src.Index;
5776 offset.SwizzleX = src.SwizzleX;
5777 offset.SwizzleY = src.SwizzleY;
5778 offset.SwizzleZ = src.SwizzleZ;
5779 offset.Padding = 0;
5780
5781 assert(!src.Indirect);
5782 assert(!src.DimIndirect);
5783 assert(!src.Dimension);
5784 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
5785 assert(!src.Negate);
5786
5787 return offset;
5788 }
5789
5790 static void
5791 compile_tgsi_instruction(struct st_translate *t,
5792 const glsl_to_tgsi_instruction *inst)
5793 {
5794 struct ureg_program *ureg = t->ureg;
5795 int i;
5796 struct ureg_dst dst[2];
5797 struct ureg_src src[4];
5798 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
5799
5800 int num_dst;
5801 int num_src;
5802 unsigned tex_target = 0;
5803
5804 num_dst = num_inst_dst_regs(inst);
5805 num_src = num_inst_src_regs(inst);
5806
5807 for (i = 0; i < num_dst; i++)
5808 dst[i] = translate_dst(t,
5809 &inst->dst[i],
5810 inst->saturate);
5811
5812 for (i = 0; i < num_src; i++)
5813 src[i] = translate_src(t, &inst->src[i]);
5814
5815 switch(inst->op) {
5816 case TGSI_OPCODE_BGNLOOP:
5817 case TGSI_OPCODE_ELSE:
5818 case TGSI_OPCODE_ENDLOOP:
5819 case TGSI_OPCODE_IF:
5820 case TGSI_OPCODE_UIF:
5821 assert(num_dst == 0);
5822 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
5823 return;
5824
5825 case TGSI_OPCODE_TEX:
5826 case TGSI_OPCODE_TEX_LZ:
5827 case TGSI_OPCODE_TXB:
5828 case TGSI_OPCODE_TXD:
5829 case TGSI_OPCODE_TXL:
5830 case TGSI_OPCODE_TXP:
5831 case TGSI_OPCODE_TXQ:
5832 case TGSI_OPCODE_TXQS:
5833 case TGSI_OPCODE_TXF:
5834 case TGSI_OPCODE_TXF_LZ:
5835 case TGSI_OPCODE_TEX2:
5836 case TGSI_OPCODE_TXB2:
5837 case TGSI_OPCODE_TXL2:
5838 case TGSI_OPCODE_TG4:
5839 case TGSI_OPCODE_LODQ:
5840 if (inst->resource.file == PROGRAM_SAMPLER) {
5841 src[num_src] = t->samplers[inst->resource.index];
5842 } else {
5843 /* Bindless samplers. */
5844 src[num_src] = translate_src(t, &inst->resource);
5845 }
5846 assert(src[num_src].File != TGSI_FILE_NULL);
5847 if (inst->resource.reladdr)
5848 src[num_src] =
5849 ureg_src_indirect(src[num_src],
5850 translate_addr(t, inst->resource.reladdr, 2));
5851 num_src++;
5852 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
5853 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
5854 }
5855 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5856
5857 ureg_tex_insn(ureg,
5858 inst->op,
5859 dst, num_dst,
5860 tex_target,
5861 st_translate_texture_type(inst->tex_type),
5862 texoffsets, inst->tex_offset_num_offset,
5863 src, num_src);
5864 return;
5865
5866 case TGSI_OPCODE_RESQ:
5867 case TGSI_OPCODE_LOAD:
5868 case TGSI_OPCODE_ATOMUADD:
5869 case TGSI_OPCODE_ATOMXCHG:
5870 case TGSI_OPCODE_ATOMCAS:
5871 case TGSI_OPCODE_ATOMAND:
5872 case TGSI_OPCODE_ATOMOR:
5873 case TGSI_OPCODE_ATOMXOR:
5874 case TGSI_OPCODE_ATOMUMIN:
5875 case TGSI_OPCODE_ATOMUMAX:
5876 case TGSI_OPCODE_ATOMIMIN:
5877 case TGSI_OPCODE_ATOMIMAX:
5878 for (i = num_src - 1; i >= 0; i--)
5879 src[i + 1] = src[i];
5880 num_src++;
5881 if (inst->resource.file == PROGRAM_MEMORY) {
5882 src[0] = t->shared_memory;
5883 } else if (inst->resource.file == PROGRAM_BUFFER) {
5884 src[0] = t->buffers[inst->resource.index];
5885 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
5886 src[0] = translate_src(t, &inst->resource);
5887 } else if (inst->resource.file == PROGRAM_CONSTANT) {
5888 assert(inst->resource.has_index2);
5889 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
5890 } else {
5891 assert(inst->resource.file != PROGRAM_UNDEFINED);
5892 if (inst->resource.file == PROGRAM_IMAGE) {
5893 src[0] = t->images[inst->resource.index];
5894 } else {
5895 /* Bindless images. */
5896 src[0] = translate_src(t, &inst->resource);
5897 }
5898 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5899 }
5900 if (inst->resource.reladdr)
5901 src[0] = ureg_src_indirect(src[0],
5902 translate_addr(t, inst->resource.reladdr, 2));
5903 assert(src[0].File != TGSI_FILE_NULL);
5904 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5905 inst->buffer_access,
5906 tex_target, inst->image_format);
5907 break;
5908
5909 case TGSI_OPCODE_STORE:
5910 if (inst->resource.file == PROGRAM_MEMORY) {
5911 dst[0] = ureg_dst(t->shared_memory);
5912 } else if (inst->resource.file == PROGRAM_BUFFER) {
5913 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
5914 } else {
5915 if (inst->resource.file == PROGRAM_IMAGE) {
5916 dst[0] = ureg_dst(t->images[inst->resource.index]);
5917 } else {
5918 /* Bindless images. */
5919 dst[0] = ureg_dst(translate_src(t, &inst->resource));
5920 }
5921 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5922 }
5923 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
5924 if (inst->resource.reladdr)
5925 dst[0] = ureg_dst_indirect(dst[0],
5926 translate_addr(t, inst->resource.reladdr, 2));
5927 assert(dst[0].File != TGSI_FILE_NULL);
5928 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5929 inst->buffer_access,
5930 tex_target, inst->image_format);
5931 break;
5932
5933 default:
5934 ureg_insn(ureg,
5935 inst->op,
5936 dst, num_dst,
5937 src, num_src, inst->precise);
5938 break;
5939 }
5940 }
5941
5942 /**
5943 * Emit the TGSI instructions for inverting and adjusting WPOS.
5944 * This code is unavoidable because it also depends on whether
5945 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5946 */
5947 static void
5948 emit_wpos_adjustment(struct gl_context *ctx,
5949 struct st_translate *t,
5950 int wpos_transform_const,
5951 boolean invert,
5952 GLfloat adjX, GLfloat adjY[2])
5953 {
5954 struct ureg_program *ureg = t->ureg;
5955
5956 assert(wpos_transform_const >= 0);
5957
5958 /* Fragment program uses fragment position input.
5959 * Need to replace instances of INPUT[WPOS] with temp T
5960 * where T = INPUT[WPOS] is inverted by Y.
5961 */
5962 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
5963 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
5964 struct ureg_src *wpos =
5965 ctx->Const.GLSLFragCoordIsSysVal ?
5966 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
5967 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
5968 struct ureg_src wpos_input = *wpos;
5969
5970 /* First, apply the coordinate shift: */
5971 if (adjX || adjY[0] || adjY[1]) {
5972 if (adjY[0] != adjY[1]) {
5973 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5974 * depending on whether inversion is actually going to be applied
5975 * or not, which is determined by testing against the inversion
5976 * state variable used below, which will be either +1 or -1.
5977 */
5978 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
5979
5980 ureg_CMP(ureg, adj_temp,
5981 ureg_scalar(wpostrans, invert ? 2 : 0),
5982 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
5983 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
5984 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
5985 } else {
5986 ureg_ADD(ureg, wpos_temp, wpos_input,
5987 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
5988 }
5989 wpos_input = ureg_src(wpos_temp);
5990 } else {
5991 /* MOV wpos_temp, input[wpos]
5992 */
5993 ureg_MOV( ureg, wpos_temp, wpos_input );
5994 }
5995
5996 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5997 * inversion/identity, or the other way around if we're drawing to an FBO.
5998 */
5999 if (invert) {
6000 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6001 */
6002 ureg_MAD( ureg,
6003 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
6004 wpos_input,
6005 ureg_scalar(wpostrans, 0),
6006 ureg_scalar(wpostrans, 1));
6007 } else {
6008 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6009 */
6010 ureg_MAD( ureg,
6011 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
6012 wpos_input,
6013 ureg_scalar(wpostrans, 2),
6014 ureg_scalar(wpostrans, 3));
6015 }
6016
6017 /* Use wpos_temp as position input from here on:
6018 */
6019 *wpos = ureg_src(wpos_temp);
6020 }
6021
6022
6023 /**
6024 * Emit fragment position/ooordinate code.
6025 */
6026 static void
6027 emit_wpos(struct st_context *st,
6028 struct st_translate *t,
6029 const struct gl_program *program,
6030 struct ureg_program *ureg,
6031 int wpos_transform_const)
6032 {
6033 struct pipe_screen *pscreen = st->pipe->screen;
6034 GLfloat adjX = 0.0f;
6035 GLfloat adjY[2] = { 0.0f, 0.0f };
6036 boolean invert = FALSE;
6037
6038 /* Query the pixel center conventions supported by the pipe driver and set
6039 * adjX, adjY to help out if it cannot handle the requested one internally.
6040 *
6041 * The bias of the y-coordinate depends on whether y-inversion takes place
6042 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6043 * drawing to an FBO (causes additional inversion), and whether the pipe
6044 * driver origin and the requested origin differ (the latter condition is
6045 * stored in the 'invert' variable).
6046 *
6047 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6048 *
6049 * center shift only:
6050 * i -> h: +0.5
6051 * h -> i: -0.5
6052 *
6053 * inversion only:
6054 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6055 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6056 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6057 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6058 *
6059 * inversion and center shift:
6060 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6061 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6062 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6063 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6064 */
6065 if (program->OriginUpperLeft) {
6066 /* Fragment shader wants origin in upper-left */
6067 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6068 /* the driver supports upper-left origin */
6069 }
6070 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6071 /* the driver supports lower-left origin, need to invert Y */
6072 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6073 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6074 invert = TRUE;
6075 }
6076 else
6077 assert(0);
6078 }
6079 else {
6080 /* Fragment shader wants origin in lower-left */
6081 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6082 /* the driver supports lower-left origin */
6083 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6084 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6085 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6086 /* the driver supports upper-left origin, need to invert Y */
6087 invert = TRUE;
6088 else
6089 assert(0);
6090 }
6091
6092 if (program->PixelCenterInteger) {
6093 /* Fragment shader wants pixel center integer */
6094 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6095 /* the driver supports pixel center integer */
6096 adjY[1] = 1.0f;
6097 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6098 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6099 }
6100 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6101 /* the driver supports pixel center half integer, need to bias X,Y */
6102 adjX = -0.5f;
6103 adjY[0] = -0.5f;
6104 adjY[1] = 0.5f;
6105 }
6106 else
6107 assert(0);
6108 }
6109 else {
6110 /* Fragment shader wants pixel center half integer */
6111 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6112 /* the driver supports pixel center half integer */
6113 }
6114 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6115 /* the driver supports pixel center integer, need to bias X,Y */
6116 adjX = adjY[0] = adjY[1] = 0.5f;
6117 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6118 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6119 }
6120 else
6121 assert(0);
6122 }
6123
6124 /* we invert after adjustment so that we avoid the MOV to temporary,
6125 * and reuse the adjustment ADD instead */
6126 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6127 }
6128
6129 /**
6130 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6131 * TGSI uses +1 for front, -1 for back.
6132 * This function converts the TGSI value to the GL value. Simply clamping/
6133 * saturating the value to [0,1] does the job.
6134 */
6135 static void
6136 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6137 {
6138 struct ureg_program *ureg = t->ureg;
6139 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6140 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6141
6142 if (ctx->Const.NativeIntegers) {
6143 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6144 }
6145 else {
6146 /* MOV_SAT face_temp, input[face] */
6147 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6148 }
6149
6150 /* Use face_temp as face input from here on: */
6151 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6152 }
6153
6154 static void
6155 emit_compute_block_size(const struct gl_program *prog,
6156 struct ureg_program *ureg) {
6157 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6158 prog->info.cs.local_size[0]);
6159 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6160 prog->info.cs.local_size[1]);
6161 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6162 prog->info.cs.local_size[2]);
6163 }
6164
6165 struct sort_inout_decls {
6166 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6167 return mapping[a.mesa_index] < mapping[b.mesa_index];
6168 }
6169
6170 const ubyte *mapping;
6171 };
6172
6173 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6174 *
6175 * This is for the benefit of older drivers which are broken when the
6176 * declarations aren't sorted in this way.
6177 */
6178 static void
6179 sort_inout_decls_by_slot(struct inout_decl *decls,
6180 unsigned count,
6181 const ubyte mapping[])
6182 {
6183 sort_inout_decls sorter;
6184 sorter.mapping = mapping;
6185 std::sort(decls, decls + count, sorter);
6186 }
6187
6188 static unsigned
6189 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6190 {
6191 switch (glsl_qual) {
6192 case INTERP_MODE_NONE:
6193 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6194 return TGSI_INTERPOLATE_COLOR;
6195 return TGSI_INTERPOLATE_PERSPECTIVE;
6196 case INTERP_MODE_SMOOTH:
6197 return TGSI_INTERPOLATE_PERSPECTIVE;
6198 case INTERP_MODE_FLAT:
6199 return TGSI_INTERPOLATE_CONSTANT;
6200 case INTERP_MODE_NOPERSPECTIVE:
6201 return TGSI_INTERPOLATE_LINEAR;
6202 default:
6203 assert(0 && "unexpected interp mode in st_translate_interp()");
6204 return TGSI_INTERPOLATE_PERSPECTIVE;
6205 }
6206 }
6207
6208 /**
6209 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6210 * \param program the program to translate
6211 * \param numInputs number of input registers used
6212 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6213 * input indexes
6214 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6215 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6216 * each input
6217 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6218 * \param numOutputs number of output registers used
6219 * \param outputMapping maps Mesa fragment program outputs to TGSI
6220 * generic outputs
6221 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6222 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6223 * each output
6224 *
6225 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6226 */
6227 extern "C" enum pipe_error
6228 st_translate_program(
6229 struct gl_context *ctx,
6230 uint procType,
6231 struct ureg_program *ureg,
6232 glsl_to_tgsi_visitor *program,
6233 const struct gl_program *proginfo,
6234 GLuint numInputs,
6235 const ubyte inputMapping[],
6236 const ubyte inputSlotToAttr[],
6237 const ubyte inputSemanticName[],
6238 const ubyte inputSemanticIndex[],
6239 const ubyte interpMode[],
6240 GLuint numOutputs,
6241 const ubyte outputMapping[],
6242 const ubyte outputSemanticName[],
6243 const ubyte outputSemanticIndex[])
6244 {
6245 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6246 struct st_translate *t;
6247 unsigned i;
6248 struct gl_program_constants *frag_const =
6249 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6250 enum pipe_error ret = PIPE_OK;
6251
6252 assert(numInputs <= ARRAY_SIZE(t->inputs));
6253 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6254
6255 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6256 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6257 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6258 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6259 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6260 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6261 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6262 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6263 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op, TGSI_OPCODE_LAST - 1);
6264
6265 t = CALLOC_STRUCT(st_translate);
6266 if (!t) {
6267 ret = PIPE_ERROR_OUT_OF_MEMORY;
6268 goto out;
6269 }
6270
6271 t->procType = procType;
6272 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6273 t->inputMapping = inputMapping;
6274 t->outputMapping = outputMapping;
6275 t->ureg = ureg;
6276 t->num_temp_arrays = program->next_array;
6277 if (t->num_temp_arrays)
6278 t->arrays = (struct ureg_dst*)
6279 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6280
6281 /*
6282 * Declare input attributes.
6283 */
6284 switch (procType) {
6285 case PIPE_SHADER_FRAGMENT:
6286 case PIPE_SHADER_GEOMETRY:
6287 case PIPE_SHADER_TESS_EVAL:
6288 case PIPE_SHADER_TESS_CTRL:
6289 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6290
6291 for (i = 0; i < program->num_inputs; ++i) {
6292 struct inout_decl *decl = &program->inputs[i];
6293 unsigned slot = inputMapping[decl->mesa_index];
6294 struct ureg_src src;
6295 ubyte tgsi_usage_mask = decl->usage_mask;
6296
6297 if (glsl_base_type_is_64bit(decl->base_type)) {
6298 if (tgsi_usage_mask == 1)
6299 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6300 else if (tgsi_usage_mask == 2)
6301 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6302 else
6303 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6304 }
6305
6306 unsigned interp_mode = 0;
6307 unsigned interp_location = 0;
6308 if (procType == PIPE_SHADER_FRAGMENT) {
6309 assert(interpMode);
6310 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6311 interpMode[slot] :
6312 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6313
6314 interp_location = decl->interp_loc;
6315 }
6316
6317 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6318 inputSemanticName[slot], inputSemanticIndex[slot],
6319 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6320 decl->array_id, decl->size);
6321
6322 for (unsigned j = 0; j < decl->size; ++j) {
6323 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6324 /* The ArrayID is set up in dst_register */
6325 t->inputs[slot + j] = src;
6326 t->inputs[slot + j].ArrayID = 0;
6327 t->inputs[slot + j].Index += j;
6328 }
6329 }
6330 }
6331 break;
6332 case PIPE_SHADER_VERTEX:
6333 for (i = 0; i < numInputs; i++) {
6334 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6335 }
6336 break;
6337 case PIPE_SHADER_COMPUTE:
6338 break;
6339 default:
6340 assert(0);
6341 }
6342
6343 /*
6344 * Declare output attributes.
6345 */
6346 switch (procType) {
6347 case PIPE_SHADER_FRAGMENT:
6348 case PIPE_SHADER_COMPUTE:
6349 break;
6350 case PIPE_SHADER_GEOMETRY:
6351 case PIPE_SHADER_TESS_EVAL:
6352 case PIPE_SHADER_TESS_CTRL:
6353 case PIPE_SHADER_VERTEX:
6354 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6355
6356 for (i = 0; i < program->num_outputs; ++i) {
6357 struct inout_decl *decl = &program->outputs[i];
6358 unsigned slot = outputMapping[decl->mesa_index];
6359 struct ureg_dst dst;
6360 ubyte tgsi_usage_mask = decl->usage_mask;
6361
6362 if (glsl_base_type_is_64bit(decl->base_type)) {
6363 if (tgsi_usage_mask == 1)
6364 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6365 else if (tgsi_usage_mask == 2)
6366 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6367 else
6368 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6369 }
6370
6371 dst = ureg_DECL_output_layout(ureg,
6372 outputSemanticName[slot], outputSemanticIndex[slot],
6373 decl->gs_out_streams,
6374 slot, tgsi_usage_mask, decl->array_id, decl->size);
6375
6376 for (unsigned j = 0; j < decl->size; ++j) {
6377 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6378 /* The ArrayID is set up in dst_register */
6379 t->outputs[slot + j] = dst;
6380 t->outputs[slot + j].ArrayID = 0;
6381 t->outputs[slot + j].Index += j;
6382 }
6383 }
6384 }
6385 break;
6386 default:
6387 assert(0);
6388 }
6389
6390 if (procType == PIPE_SHADER_FRAGMENT) {
6391 if (program->shader->Program->info.fs.early_fragment_tests ||
6392 program->shader->Program->info.fs.post_depth_coverage) {
6393 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6394
6395 if (program->shader->Program->info.fs.post_depth_coverage)
6396 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6397 }
6398
6399 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6400 /* Must do this after setting up t->inputs. */
6401 emit_wpos(st_context(ctx), t, proginfo, ureg,
6402 program->wpos_transform_const);
6403 }
6404
6405 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6406 emit_face_var(ctx, t);
6407
6408 for (i = 0; i < numOutputs; i++) {
6409 switch (outputSemanticName[i]) {
6410 case TGSI_SEMANTIC_POSITION:
6411 t->outputs[i] = ureg_DECL_output(ureg,
6412 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6413 outputSemanticIndex[i]);
6414 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6415 break;
6416 case TGSI_SEMANTIC_STENCIL:
6417 t->outputs[i] = ureg_DECL_output(ureg,
6418 TGSI_SEMANTIC_STENCIL, /* Stencil */
6419 outputSemanticIndex[i]);
6420 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6421 break;
6422 case TGSI_SEMANTIC_COLOR:
6423 t->outputs[i] = ureg_DECL_output(ureg,
6424 TGSI_SEMANTIC_COLOR,
6425 outputSemanticIndex[i]);
6426 break;
6427 case TGSI_SEMANTIC_SAMPLEMASK:
6428 t->outputs[i] = ureg_DECL_output(ureg,
6429 TGSI_SEMANTIC_SAMPLEMASK,
6430 outputSemanticIndex[i]);
6431 /* TODO: If we ever support more than 32 samples, this will have
6432 * to become an array.
6433 */
6434 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6435 break;
6436 default:
6437 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6438 ret = PIPE_ERROR_BAD_INPUT;
6439 goto out;
6440 }
6441 }
6442 }
6443 else if (procType == PIPE_SHADER_VERTEX) {
6444 for (i = 0; i < numOutputs; i++) {
6445 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6446 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6447 ureg_MOV(ureg,
6448 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6449 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6450 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6451 }
6452 }
6453 }
6454
6455 if (procType == PIPE_SHADER_COMPUTE) {
6456 emit_compute_block_size(proginfo, ureg);
6457 }
6458
6459 /* Declare address register.
6460 */
6461 if (program->num_address_regs > 0) {
6462 assert(program->num_address_regs <= 3);
6463 for (int i = 0; i < program->num_address_regs; i++)
6464 t->address[i] = ureg_DECL_address(ureg);
6465 }
6466
6467 /* Declare misc input registers
6468 */
6469 {
6470 GLbitfield sysInputs = proginfo->info.system_values_read;
6471
6472 for (i = 0; sysInputs; i++) {
6473 if (sysInputs & (1 << i)) {
6474 unsigned semName = _mesa_sysval_to_semantic(i);
6475
6476 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6477
6478 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6479 semName == TGSI_SEMANTIC_VERTEXID) {
6480 /* From Gallium perspective, these system values are always
6481 * integer, and require native integer support. However, if
6482 * native integer is supported on the vertex stage but not the
6483 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6484 * assumes these system values are floats. To resolve the
6485 * inconsistency, we insert a U2F.
6486 */
6487 struct st_context *st = st_context(ctx);
6488 struct pipe_screen *pscreen = st->pipe->screen;
6489 assert(procType == PIPE_SHADER_VERTEX);
6490 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6491 (void) pscreen;
6492 if (!ctx->Const.NativeIntegers) {
6493 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6494 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
6495 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6496 }
6497 }
6498
6499 if (procType == PIPE_SHADER_FRAGMENT &&
6500 semName == TGSI_SEMANTIC_POSITION)
6501 emit_wpos(st_context(ctx), t, proginfo, ureg,
6502 program->wpos_transform_const);
6503
6504 sysInputs &= ~(1 << i);
6505 }
6506 }
6507 }
6508
6509 t->array_sizes = program->array_sizes;
6510 t->input_decls = program->inputs;
6511 t->num_input_decls = program->num_inputs;
6512 t->output_decls = program->outputs;
6513 t->num_output_decls = program->num_outputs;
6514
6515 /* Emit constants and uniforms. TGSI uses a single index space for these,
6516 * so we put all the translated regs in t->constants.
6517 */
6518 if (proginfo->Parameters) {
6519 t->constants = (struct ureg_src *)
6520 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6521 if (t->constants == NULL) {
6522 ret = PIPE_ERROR_OUT_OF_MEMORY;
6523 goto out;
6524 }
6525 t->num_constants = proginfo->Parameters->NumParameters;
6526
6527 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6528 switch (proginfo->Parameters->Parameters[i].Type) {
6529 case PROGRAM_STATE_VAR:
6530 case PROGRAM_UNIFORM:
6531 t->constants[i] = ureg_DECL_constant(ureg, i);
6532 break;
6533
6534 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6535 * addressing of the const buffer.
6536 * FIXME: Be smarter and recognize param arrays:
6537 * indirect addressing is only valid within the referenced
6538 * array.
6539 */
6540 case PROGRAM_CONSTANT:
6541 if (program->indirect_addr_consts)
6542 t->constants[i] = ureg_DECL_constant(ureg, i);
6543 else
6544 t->constants[i] = emit_immediate(t,
6545 proginfo->Parameters->ParameterValues[i],
6546 proginfo->Parameters->Parameters[i].DataType,
6547 4);
6548 break;
6549 default:
6550 break;
6551 }
6552 }
6553 }
6554
6555 for (i = 0; i < proginfo->info.num_ubos; i++) {
6556 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6557 unsigned num_const_vecs = (size + 15) / 16;
6558 unsigned first, last;
6559 assert(num_const_vecs > 0);
6560 first = 0;
6561 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6562 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6563 }
6564
6565 /* Emit immediate values.
6566 */
6567 t->immediates = (struct ureg_src *)
6568 calloc(program->num_immediates, sizeof(struct ureg_src));
6569 if (t->immediates == NULL) {
6570 ret = PIPE_ERROR_OUT_OF_MEMORY;
6571 goto out;
6572 }
6573 t->num_immediates = program->num_immediates;
6574
6575 i = 0;
6576 foreach_in_list(immediate_storage, imm, &program->immediates) {
6577 assert(i < program->num_immediates);
6578 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6579 }
6580 assert(i == program->num_immediates);
6581
6582 /* texture samplers */
6583 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6584 if (program->samplers_used & (1u << i)) {
6585 enum tgsi_return_type type =
6586 st_translate_texture_type(program->sampler_types[i]);
6587
6588 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6589
6590 ureg_DECL_sampler_view( ureg, i, program->sampler_targets[i],
6591 type, type, type, type );
6592 }
6593 }
6594
6595 /* Declare atomic and shader storage buffers. */
6596 {
6597 struct gl_program *prog = program->prog;
6598
6599 if (!st_context(ctx)->has_hw_atomics) {
6600 for (i = 0; i < prog->info.num_abos; i++) {
6601 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
6602 assert(index < frag_const->MaxAtomicBuffers);
6603 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6604 }
6605 } else {
6606 for (i = 0; i < program->num_atomics; i++) {
6607 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6608 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6609 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6610 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6611 ainfo->array_id);
6612 }
6613 }
6614
6615 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6616 for (i = 0; i < prog->info.num_ssbos; i++) {
6617 unsigned index = i;
6618 if (!st_context(ctx)->has_hw_atomics)
6619 index += frag_const->MaxAtomicBuffers;
6620
6621 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
6622 }
6623 }
6624
6625 if (program->use_shared_memory)
6626 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
6627
6628 for (i = 0; i < program->shader->Program->info.num_images; i++) {
6629 if (program->images_used & (1 << i)) {
6630 t->images[i] = ureg_DECL_image(ureg, i,
6631 program->image_targets[i],
6632 program->image_formats[i],
6633 true, false);
6634 }
6635 }
6636
6637 /* Emit each instruction in turn:
6638 */
6639 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
6640 compile_tgsi_instruction(t, inst);
6641
6642 /* Set the next shader stage hint for VS and TES. */
6643 switch (procType) {
6644 case PIPE_SHADER_VERTEX:
6645 case PIPE_SHADER_TESS_EVAL:
6646 if (program->shader_program->SeparateShader)
6647 break;
6648
6649 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
6650 if (program->shader_program->_LinkedShaders[i]) {
6651 ureg_set_next_shader_processor(
6652 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
6653 break;
6654 }
6655 }
6656 break;
6657 }
6658
6659 out:
6660 if (t) {
6661 free(t->arrays);
6662 free(t->temps);
6663 free(t->constants);
6664 t->num_constants = 0;
6665 free(t->immediates);
6666 t->num_immediates = 0;
6667 FREE(t);
6668 }
6669
6670 return ret;
6671 }
6672 /* ----------------------------- End TGSI code ------------------------------ */
6673
6674
6675 /**
6676 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6677 * generating Mesa IR.
6678 */
6679 static struct gl_program *
6680 get_mesa_program_tgsi(struct gl_context *ctx,
6681 struct gl_shader_program *shader_program,
6682 struct gl_linked_shader *shader)
6683 {
6684 glsl_to_tgsi_visitor* v;
6685 struct gl_program *prog;
6686 struct gl_shader_compiler_options *options =
6687 &ctx->Const.ShaderCompilerOptions[shader->Stage];
6688 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6689 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
6690 unsigned skip_merge_registers;
6691
6692 validate_ir_tree(shader->ir);
6693
6694 prog = shader->Program;
6695
6696 prog->Parameters = _mesa_new_parameter_list();
6697 v = new glsl_to_tgsi_visitor();
6698 v->ctx = ctx;
6699 v->prog = prog;
6700 v->shader_program = shader_program;
6701 v->shader = shader;
6702 v->options = options;
6703 v->native_integers = ctx->Const.NativeIntegers;
6704
6705 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
6706 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
6707 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
6708 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
6709 v->has_tex_txf_lz = pscreen->get_param(pscreen,
6710 PIPE_CAP_TGSI_TEX_TXF_LZ);
6711 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6712
6713 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
6714 _mesa_key_pointer_equal);
6715 skip_merge_registers =
6716 pscreen->get_shader_param(pscreen, ptarget,
6717 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
6718
6719 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
6720 prog->Parameters);
6721
6722 /* Remove reads from output registers. */
6723 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
6724 lower_output_reads(shader->Stage, shader->ir);
6725
6726 /* Emit intermediate IR for main(). */
6727 visit_exec_list(shader->ir, v);
6728
6729 #if 0
6730 /* Print out some information (for debugging purposes) used by the
6731 * optimization passes. */
6732 {
6733 int i;
6734 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6735 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6736 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6737 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6738
6739 for (i = 0; i < v->next_temp; i++) {
6740 first_writes[i] = -1;
6741 first_reads[i] = -1;
6742 last_writes[i] = -1;
6743 last_reads[i] = -1;
6744 }
6745 v->get_first_temp_read(first_reads);
6746 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
6747 v->get_last_temp_write(last_writes);
6748 for (i = 0; i < v->next_temp; i++)
6749 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
6750 first_writes[i],
6751 last_reads[i],
6752 last_writes[i]);
6753 ralloc_free(first_writes);
6754 ralloc_free(first_reads);
6755 ralloc_free(last_writes);
6756 ralloc_free(last_reads);
6757 }
6758 #endif
6759
6760 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6761 v->simplify_cmp();
6762 v->copy_propagate();
6763
6764 while (v->eliminate_dead_code());
6765
6766 v->merge_two_dsts();
6767 if (!skip_merge_registers)
6768 v->merge_registers();
6769 v->renumber_registers();
6770
6771 /* Write the END instruction. */
6772 v->emit_asm(NULL, TGSI_OPCODE_END);
6773
6774 if (ctx->_Shader->Flags & GLSL_DUMP) {
6775 _mesa_log("\n");
6776 _mesa_log("GLSL IR for linked %s program %d:\n",
6777 _mesa_shader_stage_to_string(shader->Stage),
6778 shader_program->Name);
6779 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
6780 _mesa_log("\n\n");
6781 }
6782
6783 do_set_program_inouts(shader->ir, prog, shader->Stage);
6784 _mesa_copy_linked_program_data(shader_program, shader);
6785 shrink_array_declarations(v->inputs, v->num_inputs,
6786 &prog->info.inputs_read,
6787 prog->info.vs.double_inputs_read,
6788 &prog->info.patch_inputs_read);
6789 shrink_array_declarations(v->outputs, v->num_outputs,
6790 &prog->info.outputs_written, 0ULL,
6791 &prog->info.patch_outputs_written);
6792 count_resources(v, prog);
6793
6794 /* The GLSL IR won't be needed anymore. */
6795 ralloc_free(shader->ir);
6796 shader->ir = NULL;
6797
6798 /* This must be done before the uniform storage is associated. */
6799 if (shader->Stage == MESA_SHADER_FRAGMENT &&
6800 (prog->info.inputs_read & VARYING_BIT_POS ||
6801 prog->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD))) {
6802 static const gl_state_index wposTransformState[STATE_LENGTH] = {
6803 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
6804 };
6805
6806 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
6807 wposTransformState);
6808 }
6809
6810 /* Avoid reallocation of the program parameter list, because the uniform
6811 * storage is only associated with the original parameter list.
6812 * This should be enough for Bitmap and DrawPixels constants.
6813 */
6814 _mesa_reserve_parameter_storage(prog->Parameters, 8);
6815
6816 /* This has to be done last. Any operation the can cause
6817 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6818 * program constant) has to happen before creating this linkage.
6819 */
6820 _mesa_associate_uniform_storage(ctx, shader_program, prog, true);
6821 if (!shader_program->data->LinkStatus) {
6822 free_glsl_to_tgsi_visitor(v);
6823 _mesa_reference_program(ctx, &shader->Program, NULL);
6824 return NULL;
6825 }
6826
6827 struct st_vertex_program *stvp;
6828 struct st_fragment_program *stfp;
6829 struct st_common_program *stp;
6830 struct st_compute_program *stcp;
6831
6832 switch (shader->Stage) {
6833 case MESA_SHADER_VERTEX:
6834 stvp = (struct st_vertex_program *)prog;
6835 stvp->glsl_to_tgsi = v;
6836 break;
6837 case MESA_SHADER_FRAGMENT:
6838 stfp = (struct st_fragment_program *)prog;
6839 stfp->glsl_to_tgsi = v;
6840 break;
6841 case MESA_SHADER_TESS_CTRL:
6842 case MESA_SHADER_TESS_EVAL:
6843 case MESA_SHADER_GEOMETRY:
6844 stp = st_common_program(prog);
6845 stp->glsl_to_tgsi = v;
6846 break;
6847 case MESA_SHADER_COMPUTE:
6848 stcp = (struct st_compute_program *)prog;
6849 stcp->glsl_to_tgsi = v;
6850 break;
6851 default:
6852 assert(!"should not be reached");
6853 return NULL;
6854 }
6855
6856 return prog;
6857 }
6858
6859 /* See if there are unsupported control flow statements. */
6860 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
6861 private:
6862 const struct gl_shader_compiler_options *options;
6863 public:
6864 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
6865 : options(options),
6866 unsupported(false)
6867 {
6868 }
6869
6870 virtual ir_visitor_status visit_enter(ir_function *ir)
6871 {
6872 /* Other functions are skipped (same as glsl_to_tgsi). */
6873 if (strcmp(ir->name, "main") == 0)
6874 return visit_continue;
6875
6876 return visit_continue_with_parent;
6877 }
6878
6879 virtual ir_visitor_status visit_enter(ir_call *ir)
6880 {
6881 if (!ir->callee->is_intrinsic()) {
6882 unsupported = true; /* it's a function call */
6883 return visit_stop;
6884 }
6885 return visit_continue;
6886 }
6887
6888 virtual ir_visitor_status visit_enter(ir_return *ir)
6889 {
6890 if (options->EmitNoMainReturn) {
6891 unsupported = true;
6892 return visit_stop;
6893 }
6894 return visit_continue;
6895 }
6896
6897 bool unsupported;
6898 };
6899
6900 static bool
6901 has_unsupported_control_flow(exec_list *ir,
6902 const struct gl_shader_compiler_options *options)
6903 {
6904 ir_control_flow_info_visitor visitor(options);
6905 visit_list_elements(&visitor, ir);
6906 return visitor.unsupported;
6907 }
6908
6909 extern "C" {
6910
6911 /**
6912 * Link a shader.
6913 * Called via ctx->Driver.LinkShader()
6914 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6915 * with code lowering and other optimizations.
6916 */
6917 GLboolean
6918 st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
6919 {
6920 /* Return early if we are loading the shader from on-disk cache */
6921 if (st_load_tgsi_from_disk_cache(ctx, prog)) {
6922 return GL_TRUE;
6923 }
6924
6925 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6926 assert(prog->data->LinkStatus);
6927
6928 bool use_nir = false;
6929 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
6930 if (prog->_LinkedShaders[i] == NULL)
6931 continue;
6932
6933 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
6934 exec_list *ir = shader->ir;
6935 gl_shader_stage stage = shader->Stage;
6936 const struct gl_shader_compiler_options *options =
6937 &ctx->Const.ShaderCompilerOptions[stage];
6938 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
6939 bool have_dround = pscreen->get_shader_param(pscreen, ptarget,
6940 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED);
6941 bool have_dfrexp = pscreen->get_shader_param(pscreen, ptarget,
6942 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED);
6943 bool have_ldexp = pscreen->get_shader_param(pscreen, ptarget,
6944 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED);
6945 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
6946 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
6947
6948 enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
6949 pscreen->get_shader_param(pscreen, ptarget,
6950 PIPE_SHADER_CAP_PREFERRED_IR);
6951 if (preferred_ir == PIPE_SHADER_IR_NIR)
6952 use_nir = true;
6953
6954 /* If there are forms of indirect addressing that the driver
6955 * cannot handle, perform the lowering pass.
6956 */
6957 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput ||
6958 options->EmitNoIndirectTemp || options->EmitNoIndirectUniform) {
6959 lower_variable_index_to_cond_assign(stage, ir,
6960 options->EmitNoIndirectInput,
6961 options->EmitNoIndirectOutput,
6962 options->EmitNoIndirectTemp,
6963 options->EmitNoIndirectUniform);
6964 }
6965
6966 if (!pscreen->get_param(pscreen, PIPE_CAP_INT64_DIVMOD))
6967 lower_64bit_integer_instructions(ir, DIV64 | MOD64);
6968
6969 if (ctx->Extensions.ARB_shading_language_packing) {
6970 unsigned lower_inst = LOWER_PACK_SNORM_2x16 |
6971 LOWER_UNPACK_SNORM_2x16 |
6972 LOWER_PACK_UNORM_2x16 |
6973 LOWER_UNPACK_UNORM_2x16 |
6974 LOWER_PACK_SNORM_4x8 |
6975 LOWER_UNPACK_SNORM_4x8 |
6976 LOWER_UNPACK_UNORM_4x8 |
6977 LOWER_PACK_UNORM_4x8;
6978
6979 if (ctx->Extensions.ARB_gpu_shader5)
6980 lower_inst |= LOWER_PACK_USE_BFI |
6981 LOWER_PACK_USE_BFE;
6982 if (!ctx->st->has_half_float_packing)
6983 lower_inst |= LOWER_PACK_HALF_2x16 |
6984 LOWER_UNPACK_HALF_2x16;
6985
6986 lower_packing_builtins(ir, lower_inst);
6987 }
6988
6989 if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS))
6990 lower_offset_arrays(ir);
6991 do_mat_op_to_vec(ir);
6992
6993 if (stage == MESA_SHADER_FRAGMENT)
6994 lower_blend_equation_advanced(shader);
6995
6996 lower_instructions(ir,
6997 MOD_TO_FLOOR |
6998 FDIV_TO_MUL_RCP |
6999 EXP_TO_EXP2 |
7000 LOG_TO_LOG2 |
7001 (have_ldexp ? 0 : LDEXP_TO_ARITH) |
7002 (have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
7003 CARRY_TO_ARITH |
7004 BORROW_TO_ARITH |
7005 (have_dround ? 0 : DOPS_TO_DFRAC) |
7006 (options->EmitNoPow ? POW_TO_EXP2 : 0) |
7007 (!ctx->Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) |
7008 (options->EmitNoSat ? SAT_TO_CLAMP : 0) |
7009 (ctx->Const.ForceGLSLAbsSqrt ? SQRT_TO_ABS_SQRT : 0) |
7010 /* Assume that if ARB_gpu_shader5 is not supported
7011 * then all of the extended integer functions need
7012 * lowering. It may be necessary to add some caps
7013 * for individual instructions.
7014 */
7015 (!ctx->Extensions.ARB_gpu_shader5
7016 ? BIT_COUNT_TO_MATH |
7017 EXTRACT_TO_SHIFTS |
7018 INSERT_TO_SHIFTS |
7019 REVERSE_TO_SHIFTS |
7020 FIND_LSB_TO_FLOAT_CAST |
7021 FIND_MSB_TO_FLOAT_CAST |
7022 IMUL_HIGH_TO_MUL
7023 : 0));
7024
7025 do_vec_index_to_cond_assign(ir);
7026 lower_vector_insert(ir, true);
7027 lower_quadop_vector(ir, false);
7028 lower_noise(ir);
7029 if (options->MaxIfDepth == 0) {
7030 lower_discard(ir);
7031 }
7032
7033 if (ctx->Const.GLSLOptimizeConservatively) {
7034 /* Do it once and repeat only if there's unsupported control flow. */
7035 do {
7036 do_common_optimization(ir, true, true, options,
7037 ctx->Const.NativeIntegers);
7038 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7039 options->MaxIfDepth, if_threshold);
7040 } while (has_unsupported_control_flow(ir, options));
7041 } else {
7042 /* Repeat it until it stops making changes. */
7043 bool progress;
7044 do {
7045 progress = do_common_optimization(ir, true, true, options,
7046 ctx->Const.NativeIntegers);
7047 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7048 options->MaxIfDepth, if_threshold);
7049 } while (progress);
7050 }
7051
7052 validate_ir_tree(ir);
7053 }
7054
7055 build_program_resource_list(ctx, prog);
7056
7057 if (use_nir)
7058 return st_link_nir(ctx, prog);
7059
7060 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7061 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7062 if (shader == NULL)
7063 continue;
7064
7065 struct gl_program *linked_prog =
7066 get_mesa_program_tgsi(ctx, prog, shader);
7067 st_set_prog_affected_state_flags(linked_prog);
7068
7069 if (linked_prog) {
7070 if (!ctx->Driver.ProgramStringNotify(ctx,
7071 _mesa_shader_stage_to_program(i),
7072 linked_prog)) {
7073 _mesa_reference_program(ctx, &shader->Program, NULL);
7074 return GL_FALSE;
7075 }
7076 }
7077 }
7078
7079 return GL_TRUE;
7080 }
7081
7082 void
7083 st_translate_stream_output_info(glsl_to_tgsi_visitor *glsl_to_tgsi,
7084 const ubyte outputMapping[],
7085 struct pipe_stream_output_info *so)
7086 {
7087 if (!glsl_to_tgsi->shader_program->last_vert_prog)
7088 return;
7089
7090 struct gl_transform_feedback_info *info =
7091 glsl_to_tgsi->shader_program->last_vert_prog->sh.LinkedTransformFeedback;
7092 st_translate_stream_output_info2(info, outputMapping, so);
7093 }
7094
7095 void
7096 st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
7097 const ubyte outputMapping[],
7098 struct pipe_stream_output_info *so)
7099 {
7100 unsigned i;
7101
7102 for (i = 0; i < info->NumOutputs; i++) {
7103 so->output[i].register_index =
7104 outputMapping[info->Outputs[i].OutputRegister];
7105 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7106 so->output[i].num_components = info->Outputs[i].NumComponents;
7107 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7108 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7109 so->output[i].stream = info->Outputs[i].StreamId;
7110 }
7111
7112 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7113 so->stride[i] = info->Buffers[i].Stride;
7114 }
7115 so->num_outputs = info->NumOutputs;
7116 }
7117
7118 } /* extern "C" */