2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
128 static struct inout_decl
*
129 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
131 assert(array_id
!= 0);
133 for (unsigned i
= 0; i
< count
; i
++) {
134 struct inout_decl
*decl
= &decls
[i
];
136 if (array_id
== decl
->array_id
) {
144 static enum glsl_base_type
145 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
148 return GLSL_TYPE_ERROR
;
149 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
151 return decl
->base_type
;
152 return GLSL_TYPE_ERROR
;
155 struct glsl_to_tgsi_visitor
: public ir_visitor
{
157 glsl_to_tgsi_visitor();
158 ~glsl_to_tgsi_visitor();
160 struct gl_context
*ctx
;
161 struct gl_program
*prog
;
162 struct gl_shader_program
*shader_program
;
163 struct gl_linked_shader
*shader
;
164 struct gl_shader_compiler_options
*options
;
168 unsigned *array_sizes
;
169 unsigned max_num_arrays
;
172 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
174 unsigned num_input_arrays
;
175 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
176 unsigned num_outputs
;
177 unsigned num_output_arrays
;
179 int num_address_regs
;
180 uint32_t samplers_used
;
181 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
182 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
184 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
185 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
186 bool indirect_addr_consts
;
187 int wpos_transform_const
;
190 bool native_integers
;
193 bool use_shared_memory
;
198 variable_storage
*find_variable_storage(ir_variable
*var
);
200 int add_constant(gl_register_file file
, gl_constant_value values
[8],
201 int size
, int datatype
, uint16_t *swizzle_out
);
203 st_src_reg
get_temp(const glsl_type
*type
);
204 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
206 st_src_reg
st_src_reg_for_double(double val
);
207 st_src_reg
st_src_reg_for_float(float val
);
208 st_src_reg
st_src_reg_for_int(int val
);
209 st_src_reg
st_src_reg_for_int64(int64_t val
);
210 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
213 * \name Visit methods
215 * As typical for the visitor pattern, there must be one \c visit method for
216 * each concrete subclass of \c ir_instruction. Virtual base classes within
217 * the hierarchy should not have \c visit methods.
220 virtual void visit(ir_variable
*);
221 virtual void visit(ir_loop
*);
222 virtual void visit(ir_loop_jump
*);
223 virtual void visit(ir_function_signature
*);
224 virtual void visit(ir_function
*);
225 virtual void visit(ir_expression
*);
226 virtual void visit(ir_swizzle
*);
227 virtual void visit(ir_dereference_variable
*);
228 virtual void visit(ir_dereference_array
*);
229 virtual void visit(ir_dereference_record
*);
230 virtual void visit(ir_assignment
*);
231 virtual void visit(ir_constant
*);
232 virtual void visit(ir_call
*);
233 virtual void visit(ir_return
*);
234 virtual void visit(ir_discard
*);
235 virtual void visit(ir_texture
*);
236 virtual void visit(ir_if
*);
237 virtual void visit(ir_emit_vertex
*);
238 virtual void visit(ir_end_primitive
*);
239 virtual void visit(ir_barrier
*);
242 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
244 void visit_atomic_counter_intrinsic(ir_call
*);
245 void visit_ssbo_intrinsic(ir_call
*);
246 void visit_membar_intrinsic(ir_call
*);
247 void visit_shared_intrinsic(ir_call
*);
248 void visit_image_intrinsic(ir_call
*);
249 void visit_generic_intrinsic(ir_call
*, unsigned op
);
253 /** List of variable_storage */
254 struct hash_table
*variables
;
256 /** List of immediate_storage */
257 exec_list immediates
;
258 unsigned num_immediates
;
260 /** List of glsl_to_tgsi_instruction */
261 exec_list instructions
;
263 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
264 st_dst_reg dst
= undef_dst
,
265 st_src_reg src0
= undef_src
,
266 st_src_reg src1
= undef_src
,
267 st_src_reg src2
= undef_src
,
268 st_src_reg src3
= undef_src
);
270 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
271 st_dst_reg dst
, st_dst_reg dst1
,
272 st_src_reg src0
= undef_src
,
273 st_src_reg src1
= undef_src
,
274 st_src_reg src2
= undef_src
,
275 st_src_reg src3
= undef_src
);
277 unsigned get_opcode(unsigned op
,
279 st_src_reg src0
, st_src_reg src1
);
282 * Emit the correct dot-product instruction for the type of arguments
284 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
290 void emit_scalar(ir_instruction
*ir
, unsigned op
,
291 st_dst_reg dst
, st_src_reg src0
);
293 void emit_scalar(ir_instruction
*ir
, unsigned op
,
294 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
296 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
298 void get_deref_offsets(ir_dereference
*ir
,
299 unsigned *array_size
,
304 void calc_deref_offsets(ir_dereference
*tail
,
305 unsigned *array_elements
,
307 st_src_reg
*indirect
,
309 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
311 bool try_emit_mad(ir_expression
*ir
,
313 bool try_emit_mad_for_and_not(ir_expression
*ir
,
316 void emit_swz(ir_expression
*ir
);
318 bool process_move_condition(ir_rvalue
*ir
);
320 void simplify_cmp(void);
322 void rename_temp_registers(struct rename_reg_pair
*renames
);
323 void get_first_temp_read(int *first_reads
);
324 void get_first_temp_write(int *first_writes
);
325 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
326 void get_last_temp_write(int *last_writes
);
328 void copy_propagate(void);
329 int eliminate_dead_code(void);
331 void merge_two_dsts(void);
332 void merge_registers(void);
333 void renumber_registers(void);
335 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
336 st_dst_reg
*l
, st_src_reg
*r
,
337 st_src_reg
*cond
, bool cond_swap
);
342 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
343 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
344 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
347 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
350 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
354 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
357 prog
->data
->LinkStatus
= linking_failure
;
361 swizzle_for_size(int size
)
363 static const int size_swizzles
[4] = {
364 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
365 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
366 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
367 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
370 assert((size
>= 1) && (size
<= 4));
371 return size_swizzles
[size
- 1];
375 glsl_to_tgsi_instruction
*
376 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
377 st_dst_reg dst
, st_dst_reg dst1
,
378 st_src_reg src0
, st_src_reg src1
,
379 st_src_reg src2
, st_src_reg src3
)
381 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
382 int num_reladdr
= 0, i
, j
;
383 bool dst_is_64bit
[2];
385 op
= get_opcode(op
, dst
, src0
, src1
);
387 /* If we have to do relative addressing, we want to load the ARL
388 * reg directly for one of the regs, and preload the other reladdr
389 * sources into temps.
391 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
392 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
393 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
394 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
395 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
396 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
398 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
399 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
400 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
401 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
403 if (dst
.reladdr
|| dst
.reladdr2
) {
405 emit_arl(ir
, address_reg
, *dst
.reladdr
);
407 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
411 assert(num_reladdr
== 0);
413 /* inst->op has only 8 bits. */
414 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
417 inst
->precise
= this->precise
;
418 inst
->info
= tgsi_get_opcode_info(op
);
425 inst
->is_64bit_expanded
= false;
428 inst
->tex_offsets
= NULL
;
429 inst
->tex_offset_num_offset
= 0;
431 inst
->tex_shadow
= 0;
432 /* default to float, for paths where this is not initialized
433 * (since 0==UINT which is likely wrong):
435 inst
->tex_type
= GLSL_TYPE_FLOAT
;
437 /* Update indirect addressing status used by TGSI */
438 if (dst
.reladdr
|| dst
.reladdr2
) {
440 case PROGRAM_STATE_VAR
:
441 case PROGRAM_CONSTANT
:
442 case PROGRAM_UNIFORM
:
443 this->indirect_addr_consts
= true;
445 case PROGRAM_IMMEDIATE
:
446 assert(!"immediates should not have indirect addressing");
453 for (i
= 0; i
< 4; i
++) {
454 if(inst
->src
[i
].reladdr
) {
455 switch(inst
->src
[i
].file
) {
456 case PROGRAM_STATE_VAR
:
457 case PROGRAM_CONSTANT
:
458 case PROGRAM_UNIFORM
:
459 this->indirect_addr_consts
= true;
461 case PROGRAM_IMMEDIATE
:
462 assert(!"immediates should not have indirect addressing");
472 * This section contains the double processing.
473 * GLSL just represents doubles as single channel values,
474 * however most HW and TGSI represent doubles as pairs of register channels.
476 * so we have to fixup destination writemask/index and src swizzle/indexes.
477 * dest writemasks need to translate from single channel write mask
478 * to a dual-channel writemask, but also need to modify the index,
479 * if we are touching the Z,W fields in the pre-translated writemask.
481 * src channels have similiar index modifications along with swizzle
482 * changes to we pick the XY, ZW pairs from the correct index.
484 * GLSL [0].x -> TGSI [0].xy
485 * GLSL [0].y -> TGSI [0].zw
486 * GLSL [0].z -> TGSI [1].xy
487 * GLSL [0].w -> TGSI [1].zw
489 for (j
= 0; j
< 2; j
++) {
490 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
491 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
492 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
493 if (glsl_base_type_is_64bit(type
))
494 dst_is_64bit
[j
] = true;
498 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
499 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
500 glsl_to_tgsi_instruction
*dinst
= NULL
;
501 int initial_src_swz
[4], initial_src_idx
[4];
502 int initial_dst_idx
[2], initial_dst_writemask
[2];
503 /* select the writemask for dst0 or dst1 */
504 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
506 /* copy out the writemask, index and swizzles for all src/dsts. */
507 for (j
= 0; j
< 2; j
++) {
508 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
509 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
512 for (j
= 0; j
< 4; j
++) {
513 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
514 initial_src_idx
[j
] = inst
->src
[j
].index
;
518 * scan all the components in the dst writemask
519 * generate an instruction for each of them if required.
524 int i
= u_bit_scan(&writemask
);
526 /* before emitting the instruction, see if we have to adjust load / store
528 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
529 addr
.file
== PROGRAM_UNDEFINED
) {
530 /* We have to advance the buffer address by 16 */
531 addr
= get_temp(glsl_type::uint_type
);
532 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
533 inst
->src
[0], st_src_reg_for_int(16));
536 /* first time use previous instruction */
540 /* create a new instructions for subsequent attempts */
541 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
546 this->instructions
.push_tail(dinst
);
547 dinst
->is_64bit_expanded
= true;
549 /* modify the destination if we are splitting */
550 for (j
= 0; j
< 2; j
++) {
551 if (dst_is_64bit
[j
]) {
552 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
553 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
555 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
556 dinst
->src
[0] = addr
;
557 if (dinst
->op
!= TGSI_OPCODE_STORE
)
558 dinst
->dst
[j
].index
++;
561 /* if we aren't writing to a double, just get the bit of the initial writemask
563 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
567 /* modify the src registers */
568 for (j
= 0; j
< 4; j
++) {
569 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
571 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
572 dinst
->src
[j
].index
= initial_src_idx
[j
];
574 dinst
->src
[j
].double_reg2
= true;
575 dinst
->src
[j
].index
++;
579 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
581 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
584 /* some opcodes are special case in what they use as sources
585 - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
586 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
587 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
588 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
589 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
590 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
597 this->instructions
.push_tail(inst
);
604 glsl_to_tgsi_instruction
*
605 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
607 st_src_reg src0
, st_src_reg src1
,
608 st_src_reg src2
, st_src_reg src3
)
610 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
614 * Determines whether to use an integer, unsigned integer, or float opcode
615 * based on the operands and input opcode, then emits the result.
618 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
620 st_src_reg src0
, st_src_reg src1
)
622 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
624 if (op
== TGSI_OPCODE_MOV
)
627 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
628 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
629 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
630 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
632 if (is_resource_instruction(op
))
634 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
635 type
= GLSL_TYPE_INT64
;
636 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
637 type
= GLSL_TYPE_UINT64
;
638 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
639 type
= GLSL_TYPE_DOUBLE
;
640 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
641 type
= GLSL_TYPE_FLOAT
;
642 else if (native_integers
)
643 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
645 #define case7(c, f, i, u, d, i64, ui64) \
646 case TGSI_OPCODE_##c: \
647 if (type == GLSL_TYPE_UINT64) \
648 op = TGSI_OPCODE_##ui64; \
649 else if (type == GLSL_TYPE_INT64) \
650 op = TGSI_OPCODE_##i64; \
651 else if (type == GLSL_TYPE_DOUBLE) \
652 op = TGSI_OPCODE_##d; \
653 else if (type == GLSL_TYPE_INT) \
654 op = TGSI_OPCODE_##i; \
655 else if (type == GLSL_TYPE_UINT) \
656 op = TGSI_OPCODE_##u; \
658 op = TGSI_OPCODE_##f; \
661 #define casecomp(c, f, i, u, d, i64, ui64) \
662 case TGSI_OPCODE_##c: \
663 if (type == GLSL_TYPE_INT64) \
664 op = TGSI_OPCODE_##i64; \
665 else if (type == GLSL_TYPE_UINT64) \
666 op = TGSI_OPCODE_##ui64; \
667 else if (type == GLSL_TYPE_DOUBLE) \
668 op = TGSI_OPCODE_##d; \
669 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
670 op = TGSI_OPCODE_##i; \
671 else if (type == GLSL_TYPE_UINT) \
672 op = TGSI_OPCODE_##u; \
673 else if (native_integers) \
674 op = TGSI_OPCODE_##f; \
676 op = TGSI_OPCODE_##c; \
680 /* Some instructions are initially selected without considering the type.
681 * This fixes the type:
683 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
685 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
686 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
687 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
688 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
689 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
690 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
691 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
692 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
693 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
694 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
695 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
696 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
697 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
698 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
699 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
700 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
702 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
703 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
704 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
705 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
706 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
707 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
708 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
709 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
711 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
712 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
713 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
714 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
719 assert(op
!= TGSI_OPCODE_LAST
);
723 glsl_to_tgsi_instruction
*
724 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
725 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
728 static const unsigned dot_opcodes
[] = {
729 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
732 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
736 * Emits TGSI scalar opcodes to produce unique answers across channels.
738 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
739 * channel determines the result across all channels. So to do a vec4
740 * of this operation, we want to emit a scalar per source channel used
741 * to produce dest channels.
744 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
746 st_src_reg orig_src0
, st_src_reg orig_src1
)
749 int done_mask
= ~dst
.writemask
;
751 /* TGSI RCP is a scalar operation splatting results to all channels,
752 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
755 for (i
= 0; i
< 4; i
++) {
756 GLuint this_mask
= (1 << i
);
757 st_src_reg src0
= orig_src0
;
758 st_src_reg src1
= orig_src1
;
760 if (done_mask
& this_mask
)
763 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
764 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
765 for (j
= i
+ 1; j
< 4; j
++) {
766 /* If there is another enabled component in the destination that is
767 * derived from the same inputs, generate its value on this pass as
770 if (!(done_mask
& (1 << j
)) &&
771 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
772 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
773 this_mask
|= (1 << j
);
776 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
777 src0_swiz
, src0_swiz
);
778 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
779 src1_swiz
, src1_swiz
);
781 dst
.writemask
= this_mask
;
782 emit_asm(ir
, op
, dst
, src0
, src1
);
783 done_mask
|= this_mask
;
788 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
789 st_dst_reg dst
, st_src_reg src0
)
791 st_src_reg undef
= undef_src
;
793 undef
.swizzle
= SWIZZLE_XXXX
;
795 emit_scalar(ir
, op
, dst
, src0
, undef
);
799 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
800 st_dst_reg dst
, st_src_reg src0
)
802 int op
= TGSI_OPCODE_ARL
;
804 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
805 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
808 op
= TGSI_OPCODE_UARL
;
811 assert(dst
.file
== PROGRAM_ADDRESS
);
812 if (dst
.index
>= this->num_address_regs
)
813 this->num_address_regs
= dst
.index
+ 1;
815 emit_asm(NULL
, op
, dst
, src0
);
819 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
820 gl_constant_value values
[8], int size
, int datatype
,
821 uint16_t *swizzle_out
)
823 if (file
== PROGRAM_CONSTANT
) {
824 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
825 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
826 size
, datatype
, &swizzle
);
828 *swizzle_out
= swizzle
;
832 assert(file
== PROGRAM_IMMEDIATE
);
835 immediate_storage
*entry
;
836 int size32
= size
* ((datatype
== GL_DOUBLE
||
837 datatype
== GL_INT64_ARB
||
838 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
841 /* Search immediate storage to see if we already have an identical
842 * immediate that we can use instead of adding a duplicate entry.
844 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
845 immediate_storage
*tmp
= entry
;
847 for (i
= 0; i
* 4 < size32
; i
++) {
848 int slot_size
= MIN2(size32
- (i
* 4), 4);
849 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
851 if (memcmp(tmp
->values
, &values
[i
* 4],
852 slot_size
* sizeof(gl_constant_value
)))
855 /* Everything matches, keep going until the full size is matched */
856 tmp
= (immediate_storage
*)tmp
->next
;
859 /* The full value matched */
866 for (i
= 0; i
* 4 < size32
; i
++) {
867 int slot_size
= MIN2(size32
- (i
* 4), 4);
868 /* Add this immediate to the list. */
869 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
870 this->immediates
.push_tail(entry
);
871 this->num_immediates
++;
877 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
879 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
880 union gl_constant_value uval
;
883 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
889 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
891 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
892 union gl_constant_value uval
[2];
894 memcpy(uval
, &val
, sizeof(uval
));
895 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
896 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
901 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
903 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
904 union gl_constant_value uval
;
906 assert(native_integers
);
909 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
915 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
917 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
918 union gl_constant_value uval
[2];
920 memcpy(uval
, &val
, sizeof(uval
));
921 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
922 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
928 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
931 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
932 st_src_reg_for_int(val
);
934 return st_src_reg_for_float(val
);
938 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
940 return type
->count_attribute_slots(is_vs_input
);
944 type_size(const struct glsl_type
*type
)
946 return type
->count_attribute_slots(false);
950 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
951 exec_list
*instructions
, ir_constant
*access
)
954 * emit_asm() might have actually split the op into pieces, e.g. for
955 * double stores. We have to go back and fix up all the generated ops.
957 unsigned op
= inst
->op
;
959 inst
->resource
= *buf
;
961 inst
->buffer_access
= access
->value
.u
[0];
963 if (inst
== instructions
->get_head_raw())
965 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
967 if (inst
->op
== TGSI_OPCODE_UADD
) {
968 if (inst
== instructions
->get_head_raw())
970 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
972 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
976 * If the given GLSL type is an array or matrix or a structure containing
977 * an array/matrix member, return true. Else return false.
979 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
980 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
981 * we have an array that might be indexed with a variable, we need to use
982 * the later storage type.
985 type_has_array_or_matrix(const glsl_type
*type
)
987 if (type
->is_array() || type
->is_matrix())
990 if (type
->is_record()) {
991 for (unsigned i
= 0; i
< type
->length
; i
++) {
992 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1003 * In the initial pass of codegen, we assign temporary numbers to
1004 * intermediate results. (not SSA -- variable assignments will reuse
1008 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1012 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1017 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1018 if (next_array
>= max_num_arrays
) {
1019 max_num_arrays
+= 32;
1020 array_sizes
= (unsigned*)
1021 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1024 src
.file
= PROGRAM_ARRAY
;
1026 src
.array_id
= next_array
+ 1;
1027 array_sizes
[next_array
] = type_size(type
);
1031 src
.file
= PROGRAM_TEMPORARY
;
1032 src
.index
= next_temp
;
1033 next_temp
+= type_size(type
);
1036 if (type
->is_array() || type
->is_record()) {
1037 src
.swizzle
= SWIZZLE_NOOP
;
1039 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1046 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1048 struct hash_entry
*entry
;
1050 entry
= _mesa_hash_table_search(this->variables
, var
);
1054 return (variable_storage
*)entry
->data
;
1058 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1060 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1061 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1062 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1065 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1067 const ir_state_slot
*const slots
= ir
->get_state_slots();
1068 assert(slots
!= NULL
);
1070 /* Check if this statevar's setup in the STATE file exactly
1071 * matches how we'll want to reference it as a
1072 * struct/array/whatever. If not, then we need to move it into
1073 * temporary storage and hope that it'll get copy-propagated
1076 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1077 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1082 variable_storage
*storage
;
1084 if (i
== ir
->get_num_state_slots()) {
1085 /* We'll set the index later. */
1086 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1088 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1092 /* The variable_storage constructor allocates slots based on the size
1093 * of the type. However, this had better match the number of state
1094 * elements that we're going to copy into the new temporary.
1096 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1098 dst
= st_dst_reg(get_temp(ir
->type
));
1100 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1103 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1107 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1108 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1109 (gl_state_index
*)slots
[i
].tokens
);
1111 if (storage
->file
== PROGRAM_STATE_VAR
) {
1112 if (storage
->index
== -1) {
1113 storage
->index
= index
;
1115 assert(index
== storage
->index
+ (int)i
);
1118 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1119 * the data being moved since MOV does not care about the type of
1120 * data it is moving, and we don't want to declare registers with
1121 * array or struct types.
1123 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1124 src
.swizzle
= slots
[i
].swizzle
;
1125 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1126 /* even a float takes up a whole vec4 reg in a struct/array. */
1131 if (storage
->file
== PROGRAM_TEMPORARY
&&
1132 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1133 fail_link(this->shader_program
,
1134 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1135 ir
->name
, dst
.index
- storage
->index
,
1136 type_size(ir
->type
));
1142 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1144 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1146 visit_exec_list(&ir
->body_instructions
, this);
1148 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1152 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1155 case ir_loop_jump::jump_break
:
1156 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1158 case ir_loop_jump::jump_continue
:
1159 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1166 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1173 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1175 /* Ignore function bodies other than main() -- we shouldn't see calls to
1176 * them since they should all be inlined before we get to glsl_to_tgsi.
1178 if (strcmp(ir
->name
, "main") == 0) {
1179 const ir_function_signature
*sig
;
1182 sig
= ir
->matching_signature(NULL
, &empty
, false);
1186 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1193 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1195 int nonmul_operand
= 1 - mul_operand
;
1197 st_dst_reg result_dst
;
1199 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1200 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1203 expr
->operands
[0]->accept(this);
1205 expr
->operands
[1]->accept(this);
1207 ir
->operands
[nonmul_operand
]->accept(this);
1210 this->result
= get_temp(ir
->type
);
1211 result_dst
= st_dst_reg(this->result
);
1212 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1213 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1219 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1221 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1222 * implemented using multiplication, and logical-or is implemented using
1223 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1224 * As result, the logical expression (a & !b) can be rewritten as:
1228 * - (a * 1) - (a * b)
1232 * This final expression can be implemented as a single MAD(a, -b, a)
1236 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1238 const int other_operand
= 1 - try_operand
;
1241 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1242 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1245 ir
->operands
[other_operand
]->accept(this);
1247 expr
->operands
[0]->accept(this);
1250 b
.negate
= ~b
.negate
;
1252 this->result
= get_temp(ir
->type
);
1253 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1259 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1260 st_src_reg
*reg
, int *num_reladdr
)
1262 if (!reg
->reladdr
&& !reg
->reladdr2
)
1265 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1266 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1268 if (*num_reladdr
!= 1) {
1269 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1271 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1279 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1281 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1283 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1285 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1286 if (try_emit_mad(ir
, 1))
1288 if (try_emit_mad(ir
, 0))
1292 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1294 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1295 if (try_emit_mad_for_and_not(ir
, 1))
1297 if (try_emit_mad_for_and_not(ir
, 0))
1301 if (ir
->operation
== ir_quadop_vector
)
1302 assert(!"ir_quadop_vector should have been lowered");
1304 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1305 this->result
.file
= PROGRAM_UNDEFINED
;
1306 ir
->operands
[operand
]->accept(this);
1307 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1308 printf("Failed to get tree for expression operand:\n");
1309 ir
->operands
[operand
]->print();
1313 op
[operand
] = this->result
;
1315 /* Matrix expression operands should have been broken down to vector
1316 * operations already.
1318 assert(!ir
->operands
[operand
]->type
->is_matrix());
1321 visit_expression(ir
, op
);
1324 /* The non-recursive part of the expression visitor lives in a separate
1325 * function and should be prevented from being inlined, to avoid a stack
1326 * explosion when deeply nested expressions are visited.
1329 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1331 st_src_reg result_src
;
1332 st_dst_reg result_dst
;
1334 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1335 if (ir
->operands
[1]) {
1336 vector_elements
= MAX2(vector_elements
,
1337 ir
->operands
[1]->type
->vector_elements
);
1340 this->result
.file
= PROGRAM_UNDEFINED
;
1342 /* Storage for our result. Ideally for an assignment we'd be using
1343 * the actual storage for the result here, instead.
1345 result_src
= get_temp(ir
->type
);
1346 /* convenience for the emit functions below. */
1347 result_dst
= st_dst_reg(result_src
);
1348 /* Limit writes to the channels that will be used by result_src later.
1349 * This does limit this temp's use as a temporary for multi-instruction
1352 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1354 switch (ir
->operation
) {
1355 case ir_unop_logic_not
:
1356 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1357 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1359 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1360 * older GPUs implement SEQ using multiple instructions (i915 uses two
1361 * SGE instructions and a MUL instruction). Since our logic values are
1362 * 0.0 and 1.0, 1-x also implements !x.
1364 op
[0].negate
= ~op
[0].negate
;
1365 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1369 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1370 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1371 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1372 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1373 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1374 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1376 op
[0].negate
= ~op
[0].negate
;
1380 case ir_unop_subroutine_to_int
:
1381 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1384 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1385 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1386 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1387 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1388 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1389 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1391 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1394 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1397 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1401 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1404 assert(!"not reached: should be handled by exp_to_exp2");
1407 assert(!"not reached: should be handled by log_to_log2");
1410 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1413 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1416 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1418 case ir_unop_saturate
: {
1419 glsl_to_tgsi_instruction
*inst
;
1420 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1421 inst
->saturate
= true;
1426 case ir_unop_dFdx_coarse
:
1427 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1429 case ir_unop_dFdx_fine
:
1430 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1433 case ir_unop_dFdy_coarse
:
1434 case ir_unop_dFdy_fine
:
1436 /* The X component contains 1 or -1 depending on whether the framebuffer
1437 * is a FBO or the window system buffer, respectively.
1438 * It is then multiplied with the source operand of DDY.
1440 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1441 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1443 unsigned transform_y_index
=
1444 _mesa_add_state_reference(this->prog
->Parameters
,
1447 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1449 glsl_type::vec4_type
);
1450 transform_y
.swizzle
= SWIZZLE_XXXX
;
1452 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1454 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1455 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1456 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1460 case ir_unop_frexp_sig
:
1461 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1464 case ir_unop_frexp_exp
:
1465 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1468 case ir_unop_noise
: {
1469 /* At some point, a motivated person could add a better
1470 * implementation of noise. Currently not even the nvidia
1471 * binary drivers do anything more than this. In any case, the
1472 * place to do this is in the GL state tracker, not the poor
1475 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1480 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1483 op
[1].negate
= ~op
[1].negate
;
1484 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1488 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1491 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1494 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1495 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1497 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1501 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1503 case ir_binop_greater
:
1504 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1506 case ir_binop_lequal
:
1507 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1509 case ir_binop_gequal
:
1510 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1512 case ir_binop_equal
:
1513 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1515 case ir_binop_nequal
:
1516 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1518 case ir_binop_all_equal
:
1519 /* "==" operator producing a scalar boolean. */
1520 if (ir
->operands
[0]->type
->is_vector() ||
1521 ir
->operands
[1]->type
->is_vector()) {
1522 st_src_reg temp
= get_temp(native_integers
?
1523 glsl_type::uvec4_type
:
1524 glsl_type::vec4_type
);
1526 if (native_integers
) {
1527 st_dst_reg temp_dst
= st_dst_reg(temp
);
1528 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1530 if (ir
->operands
[0]->type
->is_boolean() &&
1531 ir
->operands
[1]->as_constant() &&
1532 ir
->operands
[1]->as_constant()->is_one()) {
1533 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1535 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1538 /* Emit 1-3 AND operations to combine the SEQ results. */
1539 switch (ir
->operands
[0]->type
->vector_elements
) {
1543 temp_dst
.writemask
= WRITEMASK_Y
;
1544 temp1
.swizzle
= SWIZZLE_YYYY
;
1545 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1546 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1549 temp_dst
.writemask
= WRITEMASK_X
;
1550 temp1
.swizzle
= SWIZZLE_XXXX
;
1551 temp2
.swizzle
= SWIZZLE_YYYY
;
1552 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1553 temp_dst
.writemask
= WRITEMASK_Y
;
1554 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1555 temp2
.swizzle
= SWIZZLE_WWWW
;
1556 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1559 temp1
.swizzle
= SWIZZLE_XXXX
;
1560 temp2
.swizzle
= SWIZZLE_YYYY
;
1561 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1563 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1565 /* After the dot-product, the value will be an integer on the
1566 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1568 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1570 /* Negating the result of the dot-product gives values on the range
1571 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1572 * This is achieved using SGE.
1574 st_src_reg sge_src
= result_src
;
1575 sge_src
.negate
= ~sge_src
.negate
;
1576 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1579 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1582 case ir_binop_any_nequal
:
1583 /* "!=" operator producing a scalar boolean. */
1584 if (ir
->operands
[0]->type
->is_vector() ||
1585 ir
->operands
[1]->type
->is_vector()) {
1586 st_src_reg temp
= get_temp(native_integers
?
1587 glsl_type::uvec4_type
:
1588 glsl_type::vec4_type
);
1589 if (ir
->operands
[0]->type
->is_boolean() &&
1590 ir
->operands
[1]->as_constant() &&
1591 ir
->operands
[1]->as_constant()->is_zero()) {
1592 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1594 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1597 if (native_integers
) {
1598 st_dst_reg temp_dst
= st_dst_reg(temp
);
1599 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1601 /* Emit 1-3 OR operations to combine the SNE results. */
1602 switch (ir
->operands
[0]->type
->vector_elements
) {
1606 temp_dst
.writemask
= WRITEMASK_Y
;
1607 temp1
.swizzle
= SWIZZLE_YYYY
;
1608 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1609 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1612 temp_dst
.writemask
= WRITEMASK_X
;
1613 temp1
.swizzle
= SWIZZLE_XXXX
;
1614 temp2
.swizzle
= SWIZZLE_YYYY
;
1615 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1616 temp_dst
.writemask
= WRITEMASK_Y
;
1617 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1618 temp2
.swizzle
= SWIZZLE_WWWW
;
1619 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1622 temp1
.swizzle
= SWIZZLE_XXXX
;
1623 temp2
.swizzle
= SWIZZLE_YYYY
;
1624 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1626 /* After the dot-product, the value will be an integer on the
1627 * range [0,4]. Zero stays zero, and positive values become 1.0.
1629 glsl_to_tgsi_instruction
*const dp
=
1630 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1631 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1632 /* The clamping to [0,1] can be done for free in the fragment
1633 * shader with a saturate.
1635 dp
->saturate
= true;
1637 /* Negating the result of the dot-product gives values on the range
1638 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1639 * achieved using SLT.
1641 st_src_reg slt_src
= result_src
;
1642 slt_src
.negate
= ~slt_src
.negate
;
1643 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1647 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1651 case ir_binop_logic_xor
:
1652 if (native_integers
)
1653 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1655 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1658 case ir_binop_logic_or
: {
1659 if (native_integers
) {
1660 /* If integers are used as booleans, we can use an actual "or"
1663 assert(native_integers
);
1664 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1666 /* After the addition, the value will be an integer on the
1667 * range [0,2]. Zero stays zero, and positive values become 1.0.
1669 glsl_to_tgsi_instruction
*add
=
1670 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1671 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1672 /* The clamping to [0,1] can be done for free in the fragment
1673 * shader with a saturate if floats are being used as boolean values.
1675 add
->saturate
= true;
1677 /* Negating the result of the addition gives values on the range
1678 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1679 * is achieved using SLT.
1681 st_src_reg slt_src
= result_src
;
1682 slt_src
.negate
= ~slt_src
.negate
;
1683 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1689 case ir_binop_logic_and
:
1690 /* If native integers are disabled, the bool args are stored as float 0.0
1691 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1692 * actual AND opcode.
1694 if (native_integers
)
1695 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1697 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1701 assert(ir
->operands
[0]->type
->is_vector());
1702 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1703 emit_dp(ir
, result_dst
, op
[0], op
[1],
1704 ir
->operands
[0]->type
->vector_elements
);
1709 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1711 /* This is the only instruction sequence that makes the game "Risen"
1712 * render correctly. ABS is not required for the game, but since GLSL
1713 * declares negative values as "undefined", allowing us to do whatever
1714 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1717 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1718 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1722 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1725 if (native_integers
) {
1726 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1729 /* fallthrough to next case otherwise */
1731 if (native_integers
) {
1732 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1735 /* fallthrough to next case otherwise */
1738 case ir_unop_i642u64
:
1739 case ir_unop_u642i64
:
1740 /* Converting between signed and unsigned integers is a no-op. */
1742 result_src
.type
= result_dst
.type
;
1745 if (native_integers
) {
1746 /* Booleans are stored as integers using ~0 for true and 0 for false.
1747 * GLSL requires that int(bool) return 1 for true and 0 for false.
1748 * This conversion is done with AND, but it could be done with NEG.
1750 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1752 /* Booleans and integers are both stored as floats when native
1753 * integers are disabled.
1759 if (native_integers
)
1760 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1762 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1765 if (native_integers
)
1766 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1768 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1770 case ir_unop_bitcast_f2i
:
1771 case ir_unop_bitcast_f2u
:
1772 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1773 if (op
[0].negate
|| op
[0].abs
)
1774 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1777 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1780 case ir_unop_bitcast_i2f
:
1781 case ir_unop_bitcast_u2f
:
1783 result_src
.type
= GLSL_TYPE_FLOAT
;
1786 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1789 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1792 if (native_integers
)
1793 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1795 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1797 case ir_unop_bitcast_u642d
:
1798 case ir_unop_bitcast_i642d
:
1800 result_src
.type
= GLSL_TYPE_DOUBLE
;
1802 case ir_unop_bitcast_d2i64
:
1804 result_src
.type
= GLSL_TYPE_INT64
;
1806 case ir_unop_bitcast_d2u64
:
1808 result_src
.type
= GLSL_TYPE_UINT64
;
1811 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1814 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1817 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1819 case ir_unop_round_even
:
1820 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1823 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1827 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1830 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1833 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1836 case ir_unop_bit_not
:
1837 if (native_integers
) {
1838 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1842 if (native_integers
) {
1843 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1846 case ir_binop_lshift
:
1847 case ir_binop_rshift
:
1848 if (native_integers
) {
1849 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
1853 if (glsl_base_type_is_64bit(op
[0].type
)) {
1854 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1857 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
1858 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1863 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1866 case ir_binop_bit_and
:
1867 if (native_integers
) {
1868 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1871 case ir_binop_bit_xor
:
1872 if (native_integers
) {
1873 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1876 case ir_binop_bit_or
:
1877 if (native_integers
) {
1878 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1882 assert(!"GLSL 1.30 features unsupported");
1885 case ir_binop_ubo_load
: {
1886 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1887 ir_rvalue
*block
= ir
->operands
[0];
1888 ir_rvalue
*offset
= ir
->operands
[1];
1889 ir_constant
*const_block
= block
->as_constant();
1891 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1892 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1893 ir
->type
->base_type
);
1895 cbuf
.has_index2
= true;
1898 block
->accept(this);
1899 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1900 *cbuf
.reladdr
= this->result
;
1901 emit_arl(ir
, sampler_reladdr
, this->result
);
1904 /* Calculate the surface offset */
1905 offset
->accept(this);
1906 st_src_reg off
= this->result
;
1908 glsl_to_tgsi_instruction
*inst
=
1909 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1911 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1912 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1913 st_src_reg_for_int(0));
1915 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1918 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1919 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1920 unsigned const_offset
= const_offset_ir
?
1921 const_offset_ir
->value
.u
[0] : 0;
1922 unsigned const_block
= const_uniform_block
?
1923 const_uniform_block
->value
.u
[0] + 1 : 1;
1924 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1927 cbuf
.type
= ir
->type
->base_type
;
1928 cbuf
.file
= PROGRAM_CONSTANT
;
1930 cbuf
.reladdr
= NULL
;
1933 cbuf
.index2D
= const_block
;
1935 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1937 if (const_offset_ir
) {
1938 /* Constant index into constant buffer */
1939 cbuf
.reladdr
= NULL
;
1940 cbuf
.index
= const_offset
/ 16;
1942 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
1943 st_src_reg offset
= op
[1];
1945 /* The OpenGL spec is written in such a way that accesses with
1946 * non-constant offset are almost always vec4-aligned. The only
1947 * exception to this are members of structs in arrays of structs:
1948 * each struct in an array of structs is at least vec4-aligned,
1949 * but single-element and [ui]vec2 members of the struct may be at
1950 * an offset that is not a multiple of 16 bytes.
1952 * Here, we extract that offset, relying on previous passes to
1953 * always generate offset expressions of the form
1954 * (+ expr constant_offset).
1956 * Note that the std430 layout, which allows more cases of
1957 * alignment less than vec4 in arrays, is not supported for
1958 * uniform blocks, so we do not have to deal with it here.
1960 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
1961 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
1962 if (const_offset_ir
) {
1963 const_offset
= const_offset_ir
->value
.u
[0];
1964 cbuf
.index
= const_offset
/ 16;
1965 offset_expr
->operands
[0]->accept(this);
1966 offset
= this->result
;
1970 /* Relative/variable index into constant buffer */
1971 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
1972 st_src_reg_for_int(4));
1973 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1974 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
1977 if (const_uniform_block
) {
1978 /* Constant constant buffer */
1979 cbuf
.reladdr2
= NULL
;
1981 /* Relative/variable constant buffer */
1982 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
1983 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
1985 cbuf
.has_index2
= true;
1987 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1988 if (glsl_base_type_is_64bit(cbuf
.type
))
1989 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
1990 const_offset
% 16 / 8,
1991 const_offset
% 16 / 8,
1992 const_offset
% 16 / 8);
1994 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
1995 const_offset
% 16 / 4,
1996 const_offset
% 16 / 4,
1997 const_offset
% 16 / 4);
1999 if (ir
->type
->is_boolean()) {
2000 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2001 st_src_reg_for_int(0));
2003 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2009 /* note: we have to reorder the three args here */
2010 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2013 if (this->ctx
->Const
.NativeIntegers
)
2014 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2016 op
[0].negate
= ~op
[0].negate
;
2017 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2020 case ir_triop_bitfield_extract
:
2021 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2023 case ir_quadop_bitfield_insert
:
2024 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2026 case ir_unop_bitfield_reverse
:
2027 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2029 case ir_unop_bit_count
:
2030 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2032 case ir_unop_find_msb
:
2033 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2035 case ir_unop_find_lsb
:
2036 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2038 case ir_binop_imul_high
:
2039 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2042 /* In theory, MAD is incorrect here. */
2044 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2046 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2048 case ir_unop_interpolate_at_centroid
:
2049 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2051 case ir_binop_interpolate_at_offset
: {
2052 /* The y coordinate needs to be flipped for the default fb */
2053 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2054 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2056 unsigned transform_y_index
=
2057 _mesa_add_state_reference(this->prog
->Parameters
,
2060 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2062 glsl_type::vec4_type
);
2063 transform_y
.swizzle
= SWIZZLE_XXXX
;
2065 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2066 st_dst_reg temp_dst
= st_dst_reg(temp
);
2068 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2069 temp_dst
.writemask
= WRITEMASK_Y
;
2070 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2071 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2074 case ir_binop_interpolate_at_sample
:
2075 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2079 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2082 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2085 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2088 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2091 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2094 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2096 case ir_unop_unpack_double_2x32
:
2097 case ir_unop_pack_double_2x32
:
2098 case ir_unop_unpack_int_2x32
:
2099 case ir_unop_pack_int_2x32
:
2100 case ir_unop_unpack_uint_2x32
:
2101 case ir_unop_pack_uint_2x32
:
2102 case ir_unop_unpack_sampler_2x32
:
2103 case ir_unop_pack_sampler_2x32
:
2104 case ir_unop_unpack_image_2x32
:
2105 case ir_unop_pack_image_2x32
:
2106 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2109 case ir_binop_ldexp
:
2110 if (ir
->operands
[0]->type
->is_double()) {
2111 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2112 } else if (ir
->operands
[0]->type
->is_float()) {
2113 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2115 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2119 case ir_unop_pack_half_2x16
:
2120 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2122 case ir_unop_unpack_half_2x16
:
2123 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2126 case ir_unop_get_buffer_size
: {
2127 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2130 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2131 (const_offset
? const_offset
->value
.u
[0] : 0),
2133 if (!const_offset
) {
2134 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2135 *buffer
.reladdr
= op
[0];
2136 emit_arl(ir
, sampler_reladdr
, op
[0]);
2138 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2144 case ir_unop_b2i64
: {
2145 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2146 st_dst_reg temp_dst
= st_dst_reg(temp
);
2147 unsigned orig_swz
= op
[0].swizzle
;
2149 * To convert unsigned to 64-bit:
2150 * zero Y channel, copy X channel.
2152 temp_dst
.writemask
= WRITEMASK_Y
;
2153 if (vector_elements
> 1)
2154 temp_dst
.writemask
|= WRITEMASK_W
;
2155 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2156 temp_dst
.writemask
= WRITEMASK_X
;
2157 if (vector_elements
> 1)
2158 temp_dst
.writemask
|= WRITEMASK_Z
;
2159 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2160 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2161 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2162 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2164 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2166 result_src
.type
= GLSL_TYPE_UINT64
;
2167 if (vector_elements
> 2) {
2168 /* Subtle: We rely on the fact that get_temp here returns the next
2169 * TGSI temporary register directly after the temp register used for
2170 * the first two components, so that the result gets picked up
2173 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2174 st_dst_reg temp_dst
= st_dst_reg(temp
);
2175 temp_dst
.writemask
= WRITEMASK_Y
;
2176 if (vector_elements
> 3)
2177 temp_dst
.writemask
|= WRITEMASK_W
;
2178 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2180 temp_dst
.writemask
= WRITEMASK_X
;
2181 if (vector_elements
> 3)
2182 temp_dst
.writemask
|= WRITEMASK_Z
;
2183 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2184 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2185 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2186 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2188 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2195 case ir_unop_i642u
: {
2196 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2197 st_dst_reg temp_dst
= st_dst_reg(temp
);
2198 unsigned orig_swz
= op
[0].swizzle
;
2199 unsigned orig_idx
= op
[0].index
;
2201 temp_dst
.writemask
= WRITEMASK_X
;
2203 for (el
= 0; el
< vector_elements
; el
++) {
2204 unsigned swz
= GET_SWZ(orig_swz
, el
);
2206 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2208 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2210 op
[0].index
= orig_idx
+ 1;
2211 op
[0].type
= GLSL_TYPE_UINT
;
2212 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2213 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2216 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2217 result_src
.type
= GLSL_TYPE_UINT
;
2219 result_src
.type
= GLSL_TYPE_INT
;
2223 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int64(0));
2226 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2229 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2232 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2235 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2238 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2241 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2244 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2247 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2250 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2253 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2255 /* these might be needed */
2256 case ir_unop_pack_snorm_2x16
:
2257 case ir_unop_pack_unorm_2x16
:
2258 case ir_unop_pack_snorm_4x8
:
2259 case ir_unop_pack_unorm_4x8
:
2261 case ir_unop_unpack_snorm_2x16
:
2262 case ir_unop_unpack_unorm_2x16
:
2263 case ir_unop_unpack_snorm_4x8
:
2264 case ir_unop_unpack_unorm_4x8
:
2266 case ir_quadop_vector
:
2267 case ir_binop_vector_extract
:
2268 case ir_triop_vector_insert
:
2269 case ir_binop_carry
:
2270 case ir_binop_borrow
:
2271 case ir_unop_ssbo_unsized_array_length
:
2272 /* This operation is not supported, or should have already been handled.
2274 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2278 this->result
= result_src
;
2283 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2289 /* Note that this is only swizzles in expressions, not those on the left
2290 * hand side of an assignment, which do write masking. See ir_assignment
2294 ir
->val
->accept(this);
2296 assert(src
.file
!= PROGRAM_UNDEFINED
);
2297 assert(ir
->type
->vector_elements
> 0);
2299 for (i
= 0; i
< 4; i
++) {
2300 if (i
< ir
->type
->vector_elements
) {
2303 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2306 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2309 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2312 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2316 /* If the type is smaller than a vec4, replicate the last
2319 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2323 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2328 /* Test if the variable is an array. Note that geometry and
2329 * tessellation shader inputs are outputs are always arrays (except
2330 * for patch inputs), so only the array element type is considered.
2333 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2335 const glsl_type
*type
= var
->type
;
2337 *remove_array
= false;
2339 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2340 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2343 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2344 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2345 stage
== MESA_SHADER_TESS_CTRL
) &&
2347 if (!var
->type
->is_array())
2348 return false; /* a system value probably */
2350 type
= var
->type
->fields
.array
;
2351 *remove_array
= true;
2354 return type
->is_array() || type
->is_matrix();
2358 st_translate_interp_loc(ir_variable
*var
)
2360 if (var
->data
.centroid
)
2361 return TGSI_INTERPOLATE_LOC_CENTROID
;
2362 else if (var
->data
.sample
)
2363 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2365 return TGSI_INTERPOLATE_LOC_CENTER
;
2369 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2371 variable_storage
*entry
= find_variable_storage(ir
->var
);
2372 ir_variable
*var
= ir
->var
;
2376 switch (var
->data
.mode
) {
2377 case ir_var_uniform
:
2378 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2379 var
->data
.param_index
);
2380 _mesa_hash_table_insert(this->variables
, var
, entry
);
2382 case ir_var_shader_in
: {
2383 /* The linker assigns locations for varyings and attributes,
2384 * including deprecated builtins (like gl_Color), user-assign
2385 * generic attributes (glBindVertexLocation), and
2386 * user-defined varyings.
2388 assert(var
->data
.location
!= -1);
2390 const glsl_type
*type_without_array
= var
->type
->without_array();
2391 struct inout_decl
*decl
= &inputs
[num_inputs
];
2392 unsigned component
= var
->data
.location_frac
;
2393 unsigned num_components
;
2396 if (type_without_array
->is_64bit())
2397 component
= component
/ 2;
2398 if (type_without_array
->vector_elements
)
2399 num_components
= type_without_array
->vector_elements
;
2403 decl
->mesa_index
= var
->data
.location
;
2404 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2405 decl
->interp_loc
= st_translate_interp_loc(var
);
2406 decl
->base_type
= type_without_array
->base_type
;
2407 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2409 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2410 decl
->array_id
= num_input_arrays
+ 1;
2417 decl
->size
= type_size(var
->type
->fields
.array
);
2419 decl
->size
= type_size(var
->type
);
2421 entry
= new(mem_ctx
) variable_storage(var
,
2425 entry
->component
= component
;
2427 _mesa_hash_table_insert(this->variables
, var
, entry
);
2431 case ir_var_shader_out
: {
2432 assert(var
->data
.location
!= -1);
2434 const glsl_type
*type_without_array
= var
->type
->without_array();
2435 struct inout_decl
*decl
= &outputs
[num_outputs
];
2436 unsigned component
= var
->data
.location_frac
;
2437 unsigned num_components
;
2440 if (type_without_array
->is_64bit())
2441 component
= component
/ 2;
2442 if (type_without_array
->vector_elements
)
2443 num_components
= type_without_array
->vector_elements
;
2447 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2448 decl
->base_type
= type_without_array
->base_type
;
2449 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2450 if (var
->data
.stream
& (1u << 31)) {
2451 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2453 assert(var
->data
.stream
< 4);
2454 decl
->gs_out_streams
= 0;
2455 for (unsigned i
= 0; i
< num_components
; ++i
)
2456 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2459 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2460 decl
->array_id
= num_output_arrays
+ 1;
2461 num_output_arrays
++;
2467 decl
->size
= type_size(var
->type
->fields
.array
);
2469 decl
->size
= type_size(var
->type
);
2471 if (var
->data
.fb_fetch_output
) {
2472 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2473 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2474 var
->type
, component
, decl
->array_id
);
2475 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2476 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2479 entry
= new(mem_ctx
) variable_storage(var
,
2484 entry
->component
= component
;
2486 _mesa_hash_table_insert(this->variables
, var
, entry
);
2490 case ir_var_system_value
:
2491 entry
= new(mem_ctx
) variable_storage(var
,
2492 PROGRAM_SYSTEM_VALUE
,
2493 var
->data
.location
);
2496 case ir_var_temporary
:
2497 st_src_reg src
= get_temp(var
->type
);
2499 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2501 _mesa_hash_table_insert(this->variables
, var
, entry
);
2507 printf("Failed to make storage for %s\n", var
->name
);
2512 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2513 entry
->component
, entry
->array_id
);
2514 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2515 var
->data
.mode
== ir_var_shader_in
&&
2516 var
->type
->without_array()->is_double())
2517 this->result
.is_double_vertex_input
= true;
2518 if (!native_integers
)
2519 this->result
.type
= GLSL_TYPE_FLOAT
;
2523 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2524 GLbitfield64
* usage_mask
,
2525 GLbitfield64 double_usage_mask
,
2526 GLbitfield
* patch_usage_mask
)
2531 /* Fix array declarations by removing unused array elements at both ends
2532 * of the arrays. For example, mat4[3] where only mat[1] is used.
2534 for (i
= 0; i
< count
; i
++) {
2535 struct inout_decl
*decl
= &decls
[i
];
2536 if (!decl
->array_id
)
2539 /* Shrink the beginning. */
2540 for (j
= 0; j
< (int)decl
->size
; j
++) {
2541 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2542 if (*patch_usage_mask
&
2543 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2547 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2549 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2558 /* Shrink the end. */
2559 for (j
= decl
->size
-1; j
>= 0; j
--) {
2560 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2561 if (*patch_usage_mask
&
2562 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2566 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2568 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2575 /* When not all entries of an array are accessed, we mark them as used
2576 * here anyway, to ensure that the input/output mapping logic doesn't get
2579 * TODO This happens when an array isn't used via indirect access, which
2580 * some game ports do (at least eON-based). There is an optimization
2581 * opportunity here by replacing the array declaration with non-array
2582 * declarations of those slots that are actually used.
2584 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2585 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2586 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2588 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2594 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2599 ir_variable
*var
= ir
->variable_referenced();
2601 /* We only need the logic provided by st_glsl_storage_type_size()
2602 * for arrays of structs. Indirect sampler and image indexing is handled
2605 int element_size
= ir
->type
->without_array()->is_record() ?
2606 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2607 type_size(ir
->type
);
2609 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2611 ir
->array
->accept(this);
2614 if (!src
.has_index2
) {
2615 switch (this->prog
->Target
) {
2616 case GL_TESS_CONTROL_PROGRAM_NV
:
2617 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2618 !ir
->variable_referenced()->data
.patch
;
2620 case GL_TESS_EVALUATION_PROGRAM_NV
:
2621 is_2D
= src
.file
== PROGRAM_INPUT
&&
2622 !ir
->variable_referenced()->data
.patch
;
2624 case GL_GEOMETRY_PROGRAM_NV
:
2625 is_2D
= src
.file
== PROGRAM_INPUT
;
2635 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2636 src
.file
== PROGRAM_INPUT
)
2637 element_size
= attrib_type_size(ir
->type
, true);
2639 src
.index2D
= index
->value
.i
[0];
2640 src
.has_index2
= true;
2642 src
.index
+= index
->value
.i
[0] * element_size
;
2644 /* Variable index array dereference. It eats the "vec4" of the
2645 * base of the array and an index that offsets the TGSI register
2648 ir
->array_index
->accept(this);
2650 st_src_reg index_reg
;
2652 if (element_size
== 1) {
2653 index_reg
= this->result
;
2655 index_reg
= get_temp(native_integers
?
2656 glsl_type::int_type
: glsl_type::float_type
);
2658 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2659 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2662 /* If there was already a relative address register involved, add the
2663 * new and the old together to get the new offset.
2665 if (!is_2D
&& src
.reladdr
!= NULL
) {
2666 st_src_reg accum_reg
= get_temp(native_integers
?
2667 glsl_type::int_type
: glsl_type::float_type
);
2669 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2670 index_reg
, *src
.reladdr
);
2672 index_reg
= accum_reg
;
2676 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2677 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2679 src
.has_index2
= true;
2681 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2682 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2686 /* Change the register type to the element type of the array. */
2687 src
.type
= ir
->type
->base_type
;
2693 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2696 const glsl_type
*struct_type
= ir
->record
->type
;
2697 ir_variable
*var
= ir
->record
->variable_referenced();
2700 ir
->record
->accept(this);
2702 assert(ir
->field_idx
>= 0);
2704 for (i
= 0; i
< struct_type
->length
; i
++) {
2705 if (i
== (unsigned) ir
->field_idx
)
2707 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2708 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2711 /* If the type is smaller than a vec4, replicate the last channel out. */
2712 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2713 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2715 this->result
.swizzle
= SWIZZLE_NOOP
;
2717 this->result
.index
+= offset
;
2718 this->result
.type
= ir
->type
->base_type
;
2722 * We want to be careful in assignment setup to hit the actual storage
2723 * instead of potentially using a temporary like we might with the
2724 * ir_dereference handler.
2727 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2729 /* The LHS must be a dereference. If the LHS is a variable indexed array
2730 * access of a vector, it must be separated into a series conditional moves
2731 * before reaching this point (see ir_vec_index_to_cond_assign).
2733 assert(ir
->as_dereference());
2734 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2736 assert(!deref_array
->array
->type
->is_vector());
2739 /* Use the rvalue deref handler for the most part. We write swizzles using
2740 * the writemask, but we do extract the base component for enhanced layouts
2741 * from the source swizzle.
2744 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2745 return st_dst_reg(v
->result
);
2749 * Process the condition of a conditional assignment
2751 * Examines the condition of a conditional assignment to generate the optimal
2752 * first operand of a \c CMP instruction. If the condition is a relational
2753 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2754 * used as the source for the \c CMP instruction. Otherwise the comparison
2755 * is processed to a boolean result, and the boolean result is used as the
2756 * operand to the CMP instruction.
2759 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2761 ir_rvalue
*src_ir
= ir
;
2763 bool switch_order
= false;
2765 ir_expression
*const expr
= ir
->as_expression();
2767 if (native_integers
) {
2768 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2769 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2770 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2771 type
== GLSL_TYPE_BOOL
) {
2772 if (expr
->operation
== ir_binop_equal
) {
2773 if (expr
->operands
[0]->is_zero()) {
2774 src_ir
= expr
->operands
[1];
2775 switch_order
= true;
2777 else if (expr
->operands
[1]->is_zero()) {
2778 src_ir
= expr
->operands
[0];
2779 switch_order
= true;
2782 else if (expr
->operation
== ir_binop_nequal
) {
2783 if (expr
->operands
[0]->is_zero()) {
2784 src_ir
= expr
->operands
[1];
2786 else if (expr
->operands
[1]->is_zero()) {
2787 src_ir
= expr
->operands
[0];
2793 src_ir
->accept(this);
2794 return switch_order
;
2797 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2798 bool zero_on_left
= false;
2800 if (expr
->operands
[0]->is_zero()) {
2801 src_ir
= expr
->operands
[1];
2802 zero_on_left
= true;
2803 } else if (expr
->operands
[1]->is_zero()) {
2804 src_ir
= expr
->operands
[0];
2805 zero_on_left
= false;
2809 * (a < 0) T F F ( a < 0) T F F
2810 * (0 < a) F F T (-a < 0) F F T
2811 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2812 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2813 * (a > 0) F F T (-a < 0) F F T
2814 * (0 > a) T F F ( a < 0) T F F
2815 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2816 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2818 * Note that exchanging the order of 0 and 'a' in the comparison simply
2819 * means that the value of 'a' should be negated.
2822 switch (expr
->operation
) {
2824 switch_order
= false;
2825 negate
= zero_on_left
;
2828 case ir_binop_greater
:
2829 switch_order
= false;
2830 negate
= !zero_on_left
;
2833 case ir_binop_lequal
:
2834 switch_order
= true;
2835 negate
= !zero_on_left
;
2838 case ir_binop_gequal
:
2839 switch_order
= true;
2840 negate
= zero_on_left
;
2844 /* This isn't the right kind of comparison afterall, so make sure
2845 * the whole condition is visited.
2853 src_ir
->accept(this);
2855 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2856 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2857 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2858 * computing the condition.
2861 this->result
.negate
= ~this->result
.negate
;
2863 return switch_order
;
2867 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2868 st_dst_reg
*l
, st_src_reg
*r
,
2869 st_src_reg
*cond
, bool cond_swap
)
2871 if (type
->is_record()) {
2872 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2873 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2879 if (type
->is_array()) {
2880 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2881 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2886 if (type
->is_matrix()) {
2887 const struct glsl_type
*vec_type
;
2889 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2890 type
->vector_elements
, 1);
2892 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2893 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2898 assert(type
->is_scalar() || type
->is_vector());
2900 l
->type
= type
->base_type
;
2901 r
->type
= type
->base_type
;
2903 st_src_reg l_src
= st_src_reg(*l
);
2905 if (l_src
.file
== PROGRAM_OUTPUT
&&
2906 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
2907 (l_src
.index
== FRAG_RESULT_DEPTH
|| l_src
.index
== FRAG_RESULT_STENCIL
)) {
2908 /* This is a special case because the source swizzles will be shifted
2909 * later to account for the difference between GLSL (where they're
2910 * plain floats) and TGSI (where they're Z and Y components). */
2911 l_src
.swizzle
= SWIZZLE_XXXX
;
2914 if (native_integers
) {
2915 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2916 cond_swap
? l_src
: *r
,
2917 cond_swap
? *r
: l_src
);
2919 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2920 cond_swap
? l_src
: *r
,
2921 cond_swap
? *r
: l_src
);
2924 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2928 if (type
->is_dual_slot()) {
2930 if (r
->is_double_vertex_input
== false)
2936 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2942 /* all generated instructions need to be flaged as precise */
2943 this->precise
= is_precise(ir
->lhs
->variable_referenced());
2944 ir
->rhs
->accept(this);
2947 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2951 int first_enabled_chan
= 0;
2953 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2955 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2956 variable
->data
.mode
== ir_var_shader_out
&&
2957 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2958 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2959 assert(ir
->lhs
->type
->is_scalar());
2960 assert(ir
->write_mask
== WRITEMASK_X
);
2962 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2963 l
.writemask
= WRITEMASK_Z
;
2965 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2966 l
.writemask
= WRITEMASK_Y
;
2968 } else if (ir
->write_mask
== 0) {
2969 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2971 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2974 l
.writemask
= u_bit_consecutive(0, num_elements
);
2976 /* The type is a struct or an array of (array of) structs. */
2977 l
.writemask
= WRITEMASK_XYZW
;
2980 l
.writemask
= ir
->write_mask
;
2983 for (int i
= 0; i
< 4; i
++) {
2984 if (l
.writemask
& (1 << i
)) {
2985 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2990 l
.writemask
= l
.writemask
<< dst_component
;
2992 /* Swizzle a small RHS vector into the channels being written.
2994 * glsl ir treats write_mask as dictating how many channels are
2995 * present on the RHS while TGSI treats write_mask as just
2996 * showing which channels of the vec4 RHS get written.
2998 for (int i
= 0; i
< 4; i
++) {
2999 if (l
.writemask
& (1 << i
))
3000 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3002 swizzles
[i
] = first_enabled_chan
;
3004 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3005 swizzles
[2], swizzles
[3]);
3008 assert(l
.file
!= PROGRAM_UNDEFINED
);
3009 assert(r
.file
!= PROGRAM_UNDEFINED
);
3011 if (ir
->condition
) {
3012 const bool switch_order
= this->process_move_condition(ir
->condition
);
3013 st_src_reg condition
= this->result
;
3015 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3016 } else if (ir
->rhs
->as_expression() &&
3017 this->instructions
.get_tail() &&
3018 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3019 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3020 type_size(ir
->lhs
->type
) == 1 &&
3021 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3022 /* To avoid emitting an extra MOV when assigning an expression to a
3023 * variable, emit the last instruction of the expression again, but
3024 * replace the destination register with the target of the assignment.
3025 * Dead code elimination will remove the original instruction.
3027 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3028 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3029 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3030 new_inst
->saturate
= inst
->saturate
;
3031 new_inst
->resource
= inst
->resource
;
3032 inst
->dead_mask
= inst
->dst
[0].writemask
;
3034 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3041 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3044 GLdouble stack_vals
[4] = { 0 };
3045 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3046 GLenum gl_type
= GL_NONE
;
3048 static int in_array
= 0;
3049 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3051 /* Unfortunately, 4 floats is all we can get into
3052 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3053 * aggregate constant and move each constant value into it. If we
3054 * get lucky, copy propagation will eliminate the extra moves.
3056 if (ir
->type
->is_record()) {
3057 st_src_reg temp_base
= get_temp(ir
->type
);
3058 st_dst_reg temp
= st_dst_reg(temp_base
);
3060 for (i
= 0; i
< ir
->type
->length
; i
++) {
3061 ir_constant
*const field_value
= ir
->get_record_field(i
);
3062 int size
= type_size(field_value
->type
);
3066 field_value
->accept(this);
3069 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3070 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3076 this->result
= temp_base
;
3080 if (ir
->type
->is_array()) {
3081 st_src_reg temp_base
= get_temp(ir
->type
);
3082 st_dst_reg temp
= st_dst_reg(temp_base
);
3083 int size
= type_size(ir
->type
->fields
.array
);
3088 for (i
= 0; i
< ir
->type
->length
; i
++) {
3089 ir
->const_elements
[i
]->accept(this);
3091 for (int j
= 0; j
< size
; j
++) {
3092 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3098 this->result
= temp_base
;
3103 if (ir
->type
->is_matrix()) {
3104 st_src_reg mat
= get_temp(ir
->type
);
3105 st_dst_reg mat_column
= st_dst_reg(mat
);
3107 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3108 switch (ir
->type
->base_type
) {
3109 case GLSL_TYPE_FLOAT
:
3110 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3112 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3113 src
.index
= add_constant(file
,
3115 ir
->type
->vector_elements
,
3118 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3120 case GLSL_TYPE_DOUBLE
:
3121 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3122 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3123 src
.index
= add_constant(file
,
3125 ir
->type
->vector_elements
,
3128 if (ir
->type
->vector_elements
>= 2) {
3129 mat_column
.writemask
= WRITEMASK_XY
;
3130 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3131 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3133 mat_column
.writemask
= WRITEMASK_X
;
3134 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3135 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3138 if (ir
->type
->vector_elements
> 2) {
3139 if (ir
->type
->vector_elements
== 4) {
3140 mat_column
.writemask
= WRITEMASK_ZW
;
3141 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3142 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3144 mat_column
.writemask
= WRITEMASK_Z
;
3145 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3146 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3147 mat_column
.writemask
= WRITEMASK_XYZW
;
3148 src
.swizzle
= SWIZZLE_XYZW
;
3154 unreachable("Illegal matrix constant type.\n");
3163 switch (ir
->type
->base_type
) {
3164 case GLSL_TYPE_FLOAT
:
3166 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3167 values
[i
].f
= ir
->value
.f
[i
];
3170 case GLSL_TYPE_DOUBLE
:
3171 gl_type
= GL_DOUBLE
;
3172 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3173 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3176 case GLSL_TYPE_INT64
:
3177 gl_type
= GL_INT64_ARB
;
3178 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3179 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3182 case GLSL_TYPE_UINT64
:
3183 gl_type
= GL_UNSIGNED_INT64_ARB
;
3184 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3185 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3188 case GLSL_TYPE_UINT
:
3189 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3190 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3191 if (native_integers
)
3192 values
[i
].u
= ir
->value
.u
[i
];
3194 values
[i
].f
= ir
->value
.u
[i
];
3198 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3199 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3200 if (native_integers
)
3201 values
[i
].i
= ir
->value
.i
[i
];
3203 values
[i
].f
= ir
->value
.i
[i
];
3206 case GLSL_TYPE_BOOL
:
3207 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3208 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3209 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3213 assert(!"Non-float/uint/int/bool constant");
3216 this->result
= st_src_reg(file
, -1, ir
->type
);
3217 this->result
.index
= add_constant(file
,
3219 ir
->type
->vector_elements
,
3221 &this->result
.swizzle
);
3225 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3227 exec_node
*param
= ir
->actual_parameters
.get_head();
3228 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3229 ir_variable
*location
= deref
->variable_referenced();
3232 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3234 /* Calculate the surface offset */
3236 unsigned array_size
= 0, base
= 0;
3239 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3241 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3242 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3243 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3244 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3245 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3247 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3250 ir
->return_deref
->accept(this);
3251 st_dst_reg
dst(this->result
);
3252 dst
.writemask
= WRITEMASK_X
;
3254 glsl_to_tgsi_instruction
*inst
;
3256 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3257 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3258 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3259 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3260 st_src_reg_for_int(1));
3261 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3262 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3263 st_src_reg_for_int(-1));
3264 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3266 param
= param
->get_next();
3267 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3270 st_src_reg data
= this->result
, data2
= undef_src
;
3272 switch (ir
->callee
->intrinsic_id
) {
3273 case ir_intrinsic_atomic_counter_add
:
3274 opcode
= TGSI_OPCODE_ATOMUADD
;
3276 case ir_intrinsic_atomic_counter_min
:
3277 opcode
= TGSI_OPCODE_ATOMIMIN
;
3279 case ir_intrinsic_atomic_counter_max
:
3280 opcode
= TGSI_OPCODE_ATOMIMAX
;
3282 case ir_intrinsic_atomic_counter_and
:
3283 opcode
= TGSI_OPCODE_ATOMAND
;
3285 case ir_intrinsic_atomic_counter_or
:
3286 opcode
= TGSI_OPCODE_ATOMOR
;
3288 case ir_intrinsic_atomic_counter_xor
:
3289 opcode
= TGSI_OPCODE_ATOMXOR
;
3291 case ir_intrinsic_atomic_counter_exchange
:
3292 opcode
= TGSI_OPCODE_ATOMXCHG
;
3294 case ir_intrinsic_atomic_counter_comp_swap
: {
3295 opcode
= TGSI_OPCODE_ATOMCAS
;
3296 param
= param
->get_next();
3297 val
= ((ir_instruction
*)param
)->as_rvalue();
3299 data2
= this->result
;
3303 assert(!"Unexpected intrinsic");
3307 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3310 inst
->resource
= buffer
;
3314 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3316 exec_node
*param
= ir
->actual_parameters
.get_head();
3318 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3320 param
= param
->get_next();
3321 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3323 ir_constant
*const_block
= block
->as_constant();
3327 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3328 (const_block
? const_block
->value
.u
[0] : 0),
3332 block
->accept(this);
3333 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3334 *buffer
.reladdr
= this->result
;
3335 emit_arl(ir
, sampler_reladdr
, this->result
);
3338 /* Calculate the surface offset */
3339 offset
->accept(this);
3340 st_src_reg off
= this->result
;
3342 st_dst_reg dst
= undef_dst
;
3343 if (ir
->return_deref
) {
3344 ir
->return_deref
->accept(this);
3345 dst
= st_dst_reg(this->result
);
3346 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3349 glsl_to_tgsi_instruction
*inst
;
3351 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3352 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3353 if (dst
.type
== GLSL_TYPE_BOOL
)
3354 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3355 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3356 param
= param
->get_next();
3357 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3360 param
= param
->get_next();
3361 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3363 dst
.writemask
= write_mask
->value
.u
[0];
3365 dst
.type
= this->result
.type
;
3366 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3368 param
= param
->get_next();
3369 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3372 st_src_reg data
= this->result
, data2
= undef_src
;
3374 switch (ir
->callee
->intrinsic_id
) {
3375 case ir_intrinsic_ssbo_atomic_add
:
3376 opcode
= TGSI_OPCODE_ATOMUADD
;
3378 case ir_intrinsic_ssbo_atomic_min
:
3379 opcode
= TGSI_OPCODE_ATOMIMIN
;
3381 case ir_intrinsic_ssbo_atomic_max
:
3382 opcode
= TGSI_OPCODE_ATOMIMAX
;
3384 case ir_intrinsic_ssbo_atomic_and
:
3385 opcode
= TGSI_OPCODE_ATOMAND
;
3387 case ir_intrinsic_ssbo_atomic_or
:
3388 opcode
= TGSI_OPCODE_ATOMOR
;
3390 case ir_intrinsic_ssbo_atomic_xor
:
3391 opcode
= TGSI_OPCODE_ATOMXOR
;
3393 case ir_intrinsic_ssbo_atomic_exchange
:
3394 opcode
= TGSI_OPCODE_ATOMXCHG
;
3396 case ir_intrinsic_ssbo_atomic_comp_swap
:
3397 opcode
= TGSI_OPCODE_ATOMCAS
;
3398 param
= param
->get_next();
3399 val
= ((ir_instruction
*)param
)->as_rvalue();
3401 data2
= this->result
;
3404 assert(!"Unexpected intrinsic");
3408 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3411 param
= param
->get_next();
3412 ir_constant
*access
= NULL
;
3413 if (!param
->is_tail_sentinel()) {
3414 access
= ((ir_instruction
*)param
)->as_constant();
3418 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3422 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3424 switch (ir
->callee
->intrinsic_id
) {
3425 case ir_intrinsic_memory_barrier
:
3426 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3427 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3428 TGSI_MEMBAR_ATOMIC_BUFFER
|
3429 TGSI_MEMBAR_SHADER_IMAGE
|
3430 TGSI_MEMBAR_SHARED
));
3432 case ir_intrinsic_memory_barrier_atomic_counter
:
3433 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3434 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3436 case ir_intrinsic_memory_barrier_buffer
:
3437 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3438 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3440 case ir_intrinsic_memory_barrier_image
:
3441 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3442 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3444 case ir_intrinsic_memory_barrier_shared
:
3445 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3446 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3448 case ir_intrinsic_group_memory_barrier
:
3449 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3450 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3451 TGSI_MEMBAR_ATOMIC_BUFFER
|
3452 TGSI_MEMBAR_SHADER_IMAGE
|
3453 TGSI_MEMBAR_SHARED
|
3454 TGSI_MEMBAR_THREAD_GROUP
));
3457 assert(!"Unexpected memory barrier intrinsic");
3462 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3464 exec_node
*param
= ir
->actual_parameters
.get_head();
3466 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3468 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3470 /* Calculate the surface offset */
3471 offset
->accept(this);
3472 st_src_reg off
= this->result
;
3474 st_dst_reg dst
= undef_dst
;
3475 if (ir
->return_deref
) {
3476 ir
->return_deref
->accept(this);
3477 dst
= st_dst_reg(this->result
);
3478 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3481 glsl_to_tgsi_instruction
*inst
;
3483 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3484 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3485 inst
->resource
= buffer
;
3486 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3487 param
= param
->get_next();
3488 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3491 param
= param
->get_next();
3492 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3494 dst
.writemask
= write_mask
->value
.u
[0];
3496 dst
.type
= this->result
.type
;
3497 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3498 inst
->resource
= buffer
;
3500 param
= param
->get_next();
3501 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3504 st_src_reg data
= this->result
, data2
= undef_src
;
3506 switch (ir
->callee
->intrinsic_id
) {
3507 case ir_intrinsic_shared_atomic_add
:
3508 opcode
= TGSI_OPCODE_ATOMUADD
;
3510 case ir_intrinsic_shared_atomic_min
:
3511 opcode
= TGSI_OPCODE_ATOMIMIN
;
3513 case ir_intrinsic_shared_atomic_max
:
3514 opcode
= TGSI_OPCODE_ATOMIMAX
;
3516 case ir_intrinsic_shared_atomic_and
:
3517 opcode
= TGSI_OPCODE_ATOMAND
;
3519 case ir_intrinsic_shared_atomic_or
:
3520 opcode
= TGSI_OPCODE_ATOMOR
;
3522 case ir_intrinsic_shared_atomic_xor
:
3523 opcode
= TGSI_OPCODE_ATOMXOR
;
3525 case ir_intrinsic_shared_atomic_exchange
:
3526 opcode
= TGSI_OPCODE_ATOMXCHG
;
3528 case ir_intrinsic_shared_atomic_comp_swap
:
3529 opcode
= TGSI_OPCODE_ATOMCAS
;
3530 param
= param
->get_next();
3531 val
= ((ir_instruction
*)param
)->as_rvalue();
3533 data2
= this->result
;
3536 assert(!"Unexpected intrinsic");
3540 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3541 inst
->resource
= buffer
;
3546 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3547 bool *memory_coherent
, bool *memory_volatile
,
3548 bool *memory_restrict
, unsigned *image_format
)
3551 switch (ir
->ir_type
) {
3552 case ir_type_dereference_record
: {
3553 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3554 const glsl_type
*struct_type
= deref_record
->record
->type
;
3555 int fild_idx
= deref_record
->field_idx
;
3557 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3559 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3561 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3563 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3565 struct_type
->fields
.structure
[fild_idx
].image_format
;
3569 case ir_type_dereference_array
: {
3570 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3571 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3572 memory_coherent
, memory_volatile
, memory_restrict
,
3577 case ir_type_dereference_variable
: {
3578 ir_variable
*var
= ir
->variable_referenced();
3580 *type
= var
->type
->without_array();
3581 *memory_coherent
= var
->data
.memory_coherent
;
3582 *memory_volatile
= var
->data
.memory_volatile
;
3583 *memory_restrict
= var
->data
.memory_restrict
;
3584 *image_format
= var
->data
.image_format
;
3594 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3596 exec_node
*param
= ir
->actual_parameters
.get_head();
3598 ir_dereference
*img
= (ir_dereference
*)param
;
3599 const ir_variable
*imgvar
= img
->variable_referenced();
3600 unsigned sampler_array_size
= 1, sampler_base
= 0;
3601 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3602 unsigned image_format
= 0;
3603 const glsl_type
*type
= NULL
;
3605 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3606 &memory_restrict
, &image_format
);
3609 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3611 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3612 &index
, &reladdr
, !imgvar
->contains_bindless());
3614 image
.index
= index
;
3615 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3616 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3617 *image
.reladdr
= reladdr
;
3618 emit_arl(ir
, sampler_reladdr
, reladdr
);
3621 st_dst_reg dst
= undef_dst
;
3622 if (ir
->return_deref
) {
3623 ir
->return_deref
->accept(this);
3624 dst
= st_dst_reg(this->result
);
3625 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3628 glsl_to_tgsi_instruction
*inst
;
3630 st_src_reg bindless
;
3631 if (imgvar
->contains_bindless()) {
3633 bindless
= this->result
;
3636 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3637 dst
.writemask
= WRITEMASK_XYZ
;
3638 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3639 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3640 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3641 st_dst_reg dstres
= st_dst_reg(res
);
3642 dstres
.writemask
= WRITEMASK_W
;
3643 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3644 res
.swizzle
= SWIZZLE_WWWW
;
3645 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3647 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3649 st_dst_reg coord_dst
;
3650 coord
= get_temp(glsl_type::ivec4_type
);
3651 coord_dst
= st_dst_reg(coord
);
3652 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3653 param
= param
->get_next();
3654 ((ir_dereference
*)param
)->accept(this);
3655 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3656 coord
.swizzle
= SWIZZLE_XXXX
;
3657 switch (type
->coordinate_components()) {
3658 case 4: assert(!"unexpected coord count");
3660 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3662 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3665 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3666 param
= param
->get_next();
3667 ((ir_dereference
*)param
)->accept(this);
3668 st_src_reg sample
= this->result
;
3669 sample
.swizzle
= SWIZZLE_XXXX
;
3670 coord_dst
.writemask
= WRITEMASK_W
;
3671 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3672 coord
.swizzle
|= SWIZZLE_W
<< 9;
3675 param
= param
->get_next();
3676 if (!param
->is_tail_sentinel()) {
3677 ((ir_dereference
*)param
)->accept(this);
3678 arg1
= this->result
;
3679 param
= param
->get_next();
3682 if (!param
->is_tail_sentinel()) {
3683 ((ir_dereference
*)param
)->accept(this);
3684 arg2
= this->result
;
3685 param
= param
->get_next();
3688 assert(param
->is_tail_sentinel());
3691 switch (ir
->callee
->intrinsic_id
) {
3692 case ir_intrinsic_image_load
:
3693 opcode
= TGSI_OPCODE_LOAD
;
3695 case ir_intrinsic_image_store
:
3696 opcode
= TGSI_OPCODE_STORE
;
3698 case ir_intrinsic_image_atomic_add
:
3699 opcode
= TGSI_OPCODE_ATOMUADD
;
3701 case ir_intrinsic_image_atomic_min
:
3702 opcode
= TGSI_OPCODE_ATOMIMIN
;
3704 case ir_intrinsic_image_atomic_max
:
3705 opcode
= TGSI_OPCODE_ATOMIMAX
;
3707 case ir_intrinsic_image_atomic_and
:
3708 opcode
= TGSI_OPCODE_ATOMAND
;
3710 case ir_intrinsic_image_atomic_or
:
3711 opcode
= TGSI_OPCODE_ATOMOR
;
3713 case ir_intrinsic_image_atomic_xor
:
3714 opcode
= TGSI_OPCODE_ATOMXOR
;
3716 case ir_intrinsic_image_atomic_exchange
:
3717 opcode
= TGSI_OPCODE_ATOMXCHG
;
3719 case ir_intrinsic_image_atomic_comp_swap
:
3720 opcode
= TGSI_OPCODE_ATOMCAS
;
3723 assert(!"Unexpected intrinsic");
3727 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3728 if (opcode
== TGSI_OPCODE_STORE
)
3729 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3732 if (imgvar
->contains_bindless()) {
3733 inst
->resource
= bindless
;
3734 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3735 SWIZZLE_X
, SWIZZLE_Y
);
3737 inst
->resource
= image
;
3738 inst
->sampler_array_size
= sampler_array_size
;
3739 inst
->sampler_base
= sampler_base
;
3742 inst
->tex_target
= type
->sampler_index();
3743 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3744 _mesa_get_shader_image_format(image_format
));
3746 if (memory_coherent
)
3747 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3748 if (memory_restrict
)
3749 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3750 if (memory_volatile
)
3751 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3755 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3757 ir
->return_deref
->accept(this);
3758 st_dst_reg dst
= st_dst_reg(this->result
);
3760 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3762 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3763 unsigned num_src
= 0;
3764 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3765 assert(num_src
< ARRAY_SIZE(src
));
3767 this->result
.file
= PROGRAM_UNDEFINED
;
3768 param
->accept(this);
3769 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3771 src
[num_src
] = this->result
;
3775 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3779 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3781 ir_function_signature
*sig
= ir
->callee
;
3783 /* Filter out intrinsics */
3784 switch (sig
->intrinsic_id
) {
3785 case ir_intrinsic_atomic_counter_read
:
3786 case ir_intrinsic_atomic_counter_increment
:
3787 case ir_intrinsic_atomic_counter_predecrement
:
3788 case ir_intrinsic_atomic_counter_add
:
3789 case ir_intrinsic_atomic_counter_min
:
3790 case ir_intrinsic_atomic_counter_max
:
3791 case ir_intrinsic_atomic_counter_and
:
3792 case ir_intrinsic_atomic_counter_or
:
3793 case ir_intrinsic_atomic_counter_xor
:
3794 case ir_intrinsic_atomic_counter_exchange
:
3795 case ir_intrinsic_atomic_counter_comp_swap
:
3796 visit_atomic_counter_intrinsic(ir
);
3799 case ir_intrinsic_ssbo_load
:
3800 case ir_intrinsic_ssbo_store
:
3801 case ir_intrinsic_ssbo_atomic_add
:
3802 case ir_intrinsic_ssbo_atomic_min
:
3803 case ir_intrinsic_ssbo_atomic_max
:
3804 case ir_intrinsic_ssbo_atomic_and
:
3805 case ir_intrinsic_ssbo_atomic_or
:
3806 case ir_intrinsic_ssbo_atomic_xor
:
3807 case ir_intrinsic_ssbo_atomic_exchange
:
3808 case ir_intrinsic_ssbo_atomic_comp_swap
:
3809 visit_ssbo_intrinsic(ir
);
3812 case ir_intrinsic_memory_barrier
:
3813 case ir_intrinsic_memory_barrier_atomic_counter
:
3814 case ir_intrinsic_memory_barrier_buffer
:
3815 case ir_intrinsic_memory_barrier_image
:
3816 case ir_intrinsic_memory_barrier_shared
:
3817 case ir_intrinsic_group_memory_barrier
:
3818 visit_membar_intrinsic(ir
);
3821 case ir_intrinsic_shared_load
:
3822 case ir_intrinsic_shared_store
:
3823 case ir_intrinsic_shared_atomic_add
:
3824 case ir_intrinsic_shared_atomic_min
:
3825 case ir_intrinsic_shared_atomic_max
:
3826 case ir_intrinsic_shared_atomic_and
:
3827 case ir_intrinsic_shared_atomic_or
:
3828 case ir_intrinsic_shared_atomic_xor
:
3829 case ir_intrinsic_shared_atomic_exchange
:
3830 case ir_intrinsic_shared_atomic_comp_swap
:
3831 visit_shared_intrinsic(ir
);
3834 case ir_intrinsic_image_load
:
3835 case ir_intrinsic_image_store
:
3836 case ir_intrinsic_image_atomic_add
:
3837 case ir_intrinsic_image_atomic_min
:
3838 case ir_intrinsic_image_atomic_max
:
3839 case ir_intrinsic_image_atomic_and
:
3840 case ir_intrinsic_image_atomic_or
:
3841 case ir_intrinsic_image_atomic_xor
:
3842 case ir_intrinsic_image_atomic_exchange
:
3843 case ir_intrinsic_image_atomic_comp_swap
:
3844 case ir_intrinsic_image_size
:
3845 case ir_intrinsic_image_samples
:
3846 visit_image_intrinsic(ir
);
3849 case ir_intrinsic_shader_clock
:
3850 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3853 case ir_intrinsic_vote_all
:
3854 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3856 case ir_intrinsic_vote_any
:
3857 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3859 case ir_intrinsic_vote_eq
:
3860 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3862 case ir_intrinsic_ballot
:
3863 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3865 case ir_intrinsic_read_first_invocation
:
3866 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
3868 case ir_intrinsic_read_invocation
:
3869 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
3872 case ir_intrinsic_invalid
:
3873 case ir_intrinsic_generic_load
:
3874 case ir_intrinsic_generic_store
:
3875 case ir_intrinsic_generic_atomic_add
:
3876 case ir_intrinsic_generic_atomic_and
:
3877 case ir_intrinsic_generic_atomic_or
:
3878 case ir_intrinsic_generic_atomic_xor
:
3879 case ir_intrinsic_generic_atomic_min
:
3880 case ir_intrinsic_generic_atomic_max
:
3881 case ir_intrinsic_generic_atomic_exchange
:
3882 case ir_intrinsic_generic_atomic_comp_swap
:
3883 unreachable("Invalid intrinsic");
3888 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3889 unsigned *array_elements
,
3891 st_src_reg
*indirect
,
3894 switch (tail
->ir_type
) {
3895 case ir_type_dereference_record
: {
3896 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3897 const glsl_type
*struct_type
= deref_record
->record
->type
;
3898 int field_index
= deref_record
->field_idx
;
3900 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3902 assert(field_index
>= 0);
3903 *location
+= struct_type
->record_location_offset(field_index
);
3907 case ir_type_dereference_array
: {
3908 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3910 void *mem_ctx
= ralloc_parent(deref_arr
);
3911 ir_constant
*array_index
=
3912 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
3915 st_src_reg temp_reg
;
3916 st_dst_reg temp_dst
;
3918 temp_reg
= get_temp(glsl_type::uint_type
);
3919 temp_dst
= st_dst_reg(temp_reg
);
3920 temp_dst
.writemask
= 1;
3922 deref_arr
->array_index
->accept(this);
3923 if (*array_elements
!= 1)
3924 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3926 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3928 if (indirect
->file
== PROGRAM_UNDEFINED
)
3929 *indirect
= temp_reg
;
3931 temp_dst
= st_dst_reg(*indirect
);
3932 temp_dst
.writemask
= 1;
3933 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3936 *index
+= array_index
->value
.u
[0] * *array_elements
;
3938 *array_elements
*= deref_arr
->array
->type
->length
;
3940 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3949 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3950 unsigned *array_size
,
3953 st_src_reg
*reladdr
,
3956 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3957 unsigned location
= 0;
3958 ir_variable
*var
= ir
->variable_referenced();
3960 memset(reladdr
, 0, sizeof(*reladdr
));
3961 reladdr
->file
= PROGRAM_UNDEFINED
;
3967 location
= var
->data
.location
;
3968 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3971 * If we end up with no indirect then adjust the base to the index,
3972 * and set the array size to 1.
3974 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3980 assert(location
!= 0xffffffff);
3981 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3982 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3987 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3989 if (offset
.reladdr
|| offset
.reladdr2
) {
3990 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3991 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3992 tmp_dst
.writemask
= WRITEMASK_XY
;
3993 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4001 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4003 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4004 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4005 st_src_reg levels_src
, reladdr
;
4006 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4007 glsl_to_tgsi_instruction
*inst
= NULL
;
4008 unsigned opcode
= TGSI_OPCODE_NOP
;
4009 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4010 unsigned sampler_array_size
= 1, sampler_base
= 0;
4011 bool is_cube_array
= false, is_cube_shadow
= false;
4012 ir_variable
*var
= ir
->sampler
->variable_referenced();
4015 /* if we are a cube array sampler or a cube shadow */
4016 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4017 is_cube_array
= sampler_type
->sampler_array
;
4018 is_cube_shadow
= sampler_type
->sampler_shadow
;
4021 if (ir
->coordinate
) {
4022 ir
->coordinate
->accept(this);
4024 /* Put our coords in a temp. We'll need to modify them for shadow,
4025 * projection, or LOD, so the only case we'd use it as-is is if
4026 * we're doing plain old texturing. The optimization passes on
4027 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4029 coord
= get_temp(glsl_type::vec4_type
);
4030 coord_dst
= st_dst_reg(coord
);
4031 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4032 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4035 if (ir
->projector
) {
4036 ir
->projector
->accept(this);
4037 projector
= this->result
;
4040 /* Storage for our result. Ideally for an assignment we'd be using
4041 * the actual storage for the result here, instead.
4043 result_src
= get_temp(ir
->type
);
4044 result_dst
= st_dst_reg(result_src
);
4045 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4049 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4051 ir
->offset
->accept(this);
4052 offset
[0] = this->result
;
4056 if (is_cube_array
|| is_cube_shadow
) {
4057 opcode
= TGSI_OPCODE_TXB2
;
4060 opcode
= TGSI_OPCODE_TXB
;
4062 ir
->lod_info
.bias
->accept(this);
4063 lod_info
= this->result
;
4065 ir
->offset
->accept(this);
4066 offset
[0] = this->result
;
4070 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4071 opcode
= TGSI_OPCODE_TEX_LZ
;
4073 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4074 ir
->lod_info
.lod
->accept(this);
4075 lod_info
= this->result
;
4078 ir
->offset
->accept(this);
4079 offset
[0] = this->result
;
4083 opcode
= TGSI_OPCODE_TXD
;
4084 ir
->lod_info
.grad
.dPdx
->accept(this);
4086 ir
->lod_info
.grad
.dPdy
->accept(this);
4089 ir
->offset
->accept(this);
4090 offset
[0] = this->result
;
4094 opcode
= TGSI_OPCODE_TXQ
;
4095 ir
->lod_info
.lod
->accept(this);
4096 lod_info
= this->result
;
4098 case ir_query_levels
:
4099 opcode
= TGSI_OPCODE_TXQ
;
4100 lod_info
= undef_src
;
4101 levels_src
= get_temp(ir
->type
);
4104 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4105 opcode
= TGSI_OPCODE_TXF_LZ
;
4107 opcode
= TGSI_OPCODE_TXF
;
4108 ir
->lod_info
.lod
->accept(this);
4109 lod_info
= this->result
;
4112 ir
->offset
->accept(this);
4113 offset
[0] = this->result
;
4117 opcode
= TGSI_OPCODE_TXF
;
4118 ir
->lod_info
.sample_index
->accept(this);
4119 sample_index
= this->result
;
4122 opcode
= TGSI_OPCODE_TG4
;
4123 ir
->lod_info
.component
->accept(this);
4124 component
= this->result
;
4126 ir
->offset
->accept(this);
4127 if (ir
->offset
->type
->is_array()) {
4128 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4129 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4130 offset
[i
] = this->result
;
4131 offset
[i
].index
+= i
* type_size(elt_type
);
4132 offset
[i
].type
= elt_type
->base_type
;
4133 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4134 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4137 offset
[0] = canonicalize_gather_offset(this->result
);
4142 opcode
= TGSI_OPCODE_LODQ
;
4144 case ir_texture_samples
:
4145 opcode
= TGSI_OPCODE_TXQS
;
4147 case ir_samples_identical
:
4148 unreachable("Unexpected ir_samples_identical opcode");
4151 if (ir
->projector
) {
4152 if (opcode
== TGSI_OPCODE_TEX
) {
4153 /* Slot the projector in as the last component of the coord. */
4154 coord_dst
.writemask
= WRITEMASK_W
;
4155 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4156 coord_dst
.writemask
= WRITEMASK_XYZW
;
4157 opcode
= TGSI_OPCODE_TXP
;
4159 st_src_reg coord_w
= coord
;
4160 coord_w
.swizzle
= SWIZZLE_WWWW
;
4162 /* For the other TEX opcodes there's no projective version
4163 * since the last slot is taken up by LOD info. Do the
4164 * projective divide now.
4166 coord_dst
.writemask
= WRITEMASK_W
;
4167 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4169 /* In the case where we have to project the coordinates "by hand,"
4170 * the shadow comparator value must also be projected.
4172 st_src_reg tmp_src
= coord
;
4173 if (ir
->shadow_comparator
) {
4174 /* Slot the shadow value in as the second to last component of the
4177 ir
->shadow_comparator
->accept(this);
4179 tmp_src
= get_temp(glsl_type::vec4_type
);
4180 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4182 /* Projective division not allowed for array samplers. */
4183 assert(!sampler_type
->sampler_array
);
4185 tmp_dst
.writemask
= WRITEMASK_Z
;
4186 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4188 tmp_dst
.writemask
= WRITEMASK_XY
;
4189 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4192 coord_dst
.writemask
= WRITEMASK_XYZ
;
4193 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4195 coord_dst
.writemask
= WRITEMASK_XYZW
;
4196 coord
.swizzle
= SWIZZLE_XYZW
;
4200 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4201 * comparator was put in the correct place (and projected) by the code,
4202 * above, that handles by-hand projection.
4204 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4205 /* Slot the shadow value in as the second to last component of the
4208 ir
->shadow_comparator
->accept(this);
4210 if (is_cube_array
) {
4211 cube_sc
= get_temp(glsl_type::float_type
);
4212 cube_sc_dst
= st_dst_reg(cube_sc
);
4213 cube_sc_dst
.writemask
= WRITEMASK_X
;
4214 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4215 cube_sc_dst
.writemask
= WRITEMASK_X
;
4218 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4219 sampler_type
->sampler_array
) ||
4220 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4221 coord_dst
.writemask
= WRITEMASK_W
;
4223 coord_dst
.writemask
= WRITEMASK_Z
;
4225 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4226 coord_dst
.writemask
= WRITEMASK_XYZW
;
4230 if (ir
->op
== ir_txf_ms
) {
4231 coord_dst
.writemask
= WRITEMASK_W
;
4232 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4233 coord_dst
.writemask
= WRITEMASK_XYZW
;
4234 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4235 opcode
== TGSI_OPCODE_TXF
) {
4236 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4237 coord_dst
.writemask
= WRITEMASK_W
;
4238 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4239 coord_dst
.writemask
= WRITEMASK_XYZW
;
4242 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4245 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4246 &index
, &reladdr
, !var
->contains_bindless());
4248 sampler
.index
= index
;
4249 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4250 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4251 *sampler
.reladdr
= reladdr
;
4252 emit_arl(ir
, sampler_reladdr
, reladdr
);
4255 st_src_reg bindless
;
4256 if (var
->contains_bindless()) {
4257 ir
->sampler
->accept(this);
4258 bindless
= this->result
;
4261 if (opcode
== TGSI_OPCODE_TXD
)
4262 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4263 else if (opcode
== TGSI_OPCODE_TXQ
) {
4264 if (ir
->op
== ir_query_levels
) {
4265 /* the level is stored in W */
4266 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4267 result_dst
.writemask
= WRITEMASK_X
;
4268 levels_src
.swizzle
= SWIZZLE_WWWW
;
4269 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4271 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4272 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4273 inst
= emit_asm(ir
, opcode
, result_dst
);
4274 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4275 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4276 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4277 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4278 } else if (opcode
== TGSI_OPCODE_TG4
) {
4279 if (is_cube_array
&& ir
->shadow_comparator
) {
4280 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4282 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4285 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4287 if (ir
->shadow_comparator
)
4288 inst
->tex_shadow
= GL_TRUE
;
4290 if (var
->contains_bindless()) {
4291 inst
->resource
= bindless
;
4292 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4293 SWIZZLE_X
, SWIZZLE_Y
);
4295 inst
->resource
= sampler
;
4296 inst
->sampler_array_size
= sampler_array_size
;
4297 inst
->sampler_base
= sampler_base
;
4301 if (!inst
->tex_offsets
)
4302 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4304 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4305 inst
->tex_offsets
[i
] = offset
[i
];
4306 inst
->tex_offset_num_offset
= i
;
4309 inst
->tex_target
= sampler_type
->sampler_index();
4310 inst
->tex_type
= ir
->type
->base_type
;
4312 this->result
= result_src
;
4316 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4318 assert(!ir
->get_value());
4320 emit_asm(ir
, TGSI_OPCODE_RET
);
4324 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4326 if (ir
->condition
) {
4327 ir
->condition
->accept(this);
4328 st_src_reg condition
= this->result
;
4330 /* Convert the bool condition to a float so we can negate. */
4331 if (native_integers
) {
4332 st_src_reg temp
= get_temp(ir
->condition
->type
);
4333 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4334 condition
, st_src_reg_for_float(1.0));
4338 condition
.negate
= ~condition
.negate
;
4339 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4341 /* unconditional kil */
4342 emit_asm(ir
, TGSI_OPCODE_KILL
);
4347 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4350 glsl_to_tgsi_instruction
*if_inst
;
4352 ir
->condition
->accept(this);
4353 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4355 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4357 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4359 this->instructions
.push_tail(if_inst
);
4361 visit_exec_list(&ir
->then_instructions
, this);
4363 if (!ir
->else_instructions
.is_empty()) {
4364 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4365 visit_exec_list(&ir
->else_instructions
, this);
4368 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4373 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4375 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4377 ir
->stream
->accept(this);
4378 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4382 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4384 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4386 ir
->stream
->accept(this);
4387 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4391 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4393 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4394 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4396 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4399 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4401 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4403 result
.file
= PROGRAM_UNDEFINED
;
4410 num_input_arrays
= 0;
4411 num_output_arrays
= 0;
4413 num_address_regs
= 0;
4416 indirect_addr_consts
= false;
4417 wpos_transform_const
= -1;
4419 native_integers
= false;
4420 mem_ctx
= ralloc_context(NULL
);
4424 shader_program
= NULL
;
4429 use_shared_memory
= false;
4430 has_tex_txf_lz
= false;
4434 static void var_destroy(struct hash_entry
*entry
)
4436 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4441 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4443 _mesa_hash_table_destroy(variables
, var_destroy
);
4445 ralloc_free(mem_ctx
);
4448 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4455 * Count resources used by the given gpu program (number of texture
4459 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4461 v
->samplers_used
= 0;
4463 prog
->info
.textures_used_by_txf
= 0;
4465 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4466 if (inst
->info
->is_tex
) {
4467 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4468 unsigned idx
= inst
->sampler_base
+ i
;
4469 v
->samplers_used
|= 1u << idx
;
4471 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4472 v
->sampler_types
[idx
] = inst
->tex_type
;
4473 v
->sampler_targets
[idx
] =
4474 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4476 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4477 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4482 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4483 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4485 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4486 is_resource_instruction(inst
->op
) ||
4487 inst
->op
== TGSI_OPCODE_STORE
)) {
4488 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4489 v
->use_shared_memory
= true;
4490 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4491 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4492 unsigned idx
= inst
->sampler_base
+ i
;
4493 v
->images_used
|= 1 << idx
;
4494 v
->image_targets
[idx
] =
4495 st_translate_texture_target(inst
->tex_target
, false);
4496 v
->image_formats
[idx
] = inst
->image_format
;
4501 prog
->SamplersUsed
= v
->samplers_used
;
4503 if (v
->shader_program
!= NULL
)
4504 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4508 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4509 * are read from the given src in this instruction
4512 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4514 int read_mask
= 0, comp
;
4516 /* Now, given the src swizzle and the written channels, find which
4517 * components are actually read
4519 for (comp
= 0; comp
< 4; ++comp
) {
4520 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4522 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4523 read_mask
|= 1 << coord
;
4530 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4531 * instruction is the first instruction to write to register T0. There are
4532 * several lowering passes done in GLSL IR (e.g. branches and
4533 * relative addressing) that create a large number of conditional assignments
4534 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4536 * Here is why this conversion is safe:
4537 * CMP T0, T1 T2 T0 can be expanded to:
4543 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4544 * as the original program. If (T1 < 0.0) evaluates to false, executing
4545 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4546 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4547 * because any instruction that was going to read from T0 after this was going
4548 * to read a garbage value anyway.
4551 glsl_to_tgsi_visitor::simplify_cmp(void)
4553 int tempWritesSize
= 0;
4554 unsigned *tempWrites
= NULL
;
4555 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4557 memset(outputWrites
, 0, sizeof(outputWrites
));
4559 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4560 unsigned prevWriteMask
= 0;
4562 /* Give up if we encounter relative addressing or flow control. */
4563 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4564 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4565 inst
->info
->is_branch
||
4566 inst
->op
== TGSI_OPCODE_CONT
||
4567 inst
->op
== TGSI_OPCODE_END
||
4568 inst
->op
== TGSI_OPCODE_RET
) {
4572 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4573 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4574 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4575 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4576 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4577 if (inst
->dst
[0].index
>= tempWritesSize
) {
4578 const int inc
= 4096;
4580 tempWrites
= (unsigned*)
4582 (tempWritesSize
+ inc
) * sizeof(unsigned));
4586 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4587 tempWritesSize
+= inc
;
4590 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4591 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4595 /* For a CMP to be considered a conditional write, the destination
4596 * register and source register two must be the same. */
4597 if (inst
->op
== TGSI_OPCODE_CMP
4598 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4599 && inst
->src
[2].file
== inst
->dst
[0].file
4600 && inst
->src
[2].index
== inst
->dst
[0].index
4601 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4603 inst
->op
= TGSI_OPCODE_MOV
;
4604 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4605 inst
->src
[0] = inst
->src
[1];
4613 rename_temp_handle_src(struct rename_reg_pair
*renames
,
4614 struct st_src_reg
*src
)
4616 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4617 int old_idx
= src
->index
;
4618 if (renames
[old_idx
].valid
)
4619 src
->index
= renames
[old_idx
].new_reg
;
4623 /* Replaces all references to a temporary register index with another index. */
4625 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4627 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4629 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4630 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4631 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4632 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4635 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4636 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4637 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4638 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4641 rename_temp_handle_src(renames
, &inst
->resource
);
4642 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4643 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4645 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4646 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4647 int old_idx
= inst
->dst
[j
].index
;
4648 if (renames
[old_idx
].valid
)
4649 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4651 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4652 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4658 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4660 int depth
= 0; /* loop depth */
4661 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4664 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4665 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4666 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4667 if (first_writes
[inst
->dst
[j
].index
] == -1)
4668 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4672 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4675 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4685 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4687 int depth
= 0; /* loop depth */
4688 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4691 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4692 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4693 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4694 if (first_reads
[inst
->src
[j
].index
] == -1)
4695 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4698 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4699 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4700 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4701 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4704 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4707 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4717 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4719 int depth
= 0; /* loop depth */
4720 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4723 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4724 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4725 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4726 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4728 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4729 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4730 if (first_writes
[inst
->dst
[j
].index
] == -1)
4731 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4732 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4735 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4736 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4737 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4739 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4742 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4745 for (k
= 0; k
< this->next_temp
; k
++) {
4746 if (last_reads
[k
] == -2) {
4758 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4760 int depth
= 0; /* loop depth */
4764 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4765 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4766 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4767 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4770 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4772 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4774 for (k
= 0; k
< this->next_temp
; k
++) {
4775 if (last_writes
[k
] == -2) {
4786 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4787 * channels for copy propagation and updates following instructions to
4788 * use the original versions.
4790 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4791 * will occur. As an example, a TXP production before this pass:
4793 * 0: MOV TEMP[1], INPUT[4].xyyy;
4794 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4795 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4799 * 0: MOV TEMP[1], INPUT[4].xyyy;
4800 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4801 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4803 * which allows for dead code elimination on TEMP[1]'s writes.
4806 glsl_to_tgsi_visitor::copy_propagate(void)
4808 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4809 glsl_to_tgsi_instruction
*,
4810 this->next_temp
* 4);
4811 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4814 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4815 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4816 || inst
->dst
[0].index
< this->next_temp
);
4818 /* First, do any copy propagation possible into the src regs. */
4819 for (int r
= 0; r
< 3; r
++) {
4820 glsl_to_tgsi_instruction
*first
= NULL
;
4822 int acp_base
= inst
->src
[r
].index
* 4;
4824 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4825 inst
->src
[r
].reladdr
||
4826 inst
->src
[r
].reladdr2
)
4829 /* See if we can find entries in the ACP consisting of MOVs
4830 * from the same src register for all the swizzled channels
4831 * of this src register reference.
4833 for (int i
= 0; i
< 4; i
++) {
4834 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4835 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4842 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4847 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4848 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4849 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4850 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4858 /* We've now validated that we can copy-propagate to
4859 * replace this src register reference. Do it.
4861 inst
->src
[r
].file
= first
->src
[0].file
;
4862 inst
->src
[r
].index
= first
->src
[0].index
;
4863 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4864 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4865 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4866 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4869 for (int i
= 0; i
< 4; i
++) {
4870 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4871 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4872 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4874 inst
->src
[r
].swizzle
= swizzle
;
4879 case TGSI_OPCODE_BGNLOOP
:
4880 case TGSI_OPCODE_ENDLOOP
:
4881 /* End of a basic block, clear the ACP entirely. */
4882 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4885 case TGSI_OPCODE_IF
:
4886 case TGSI_OPCODE_UIF
:
4890 case TGSI_OPCODE_ENDIF
:
4891 case TGSI_OPCODE_ELSE
:
4892 /* Clear all channels written inside the block from the ACP, but
4893 * leaving those that were not touched.
4895 for (int r
= 0; r
< this->next_temp
; r
++) {
4896 for (int c
= 0; c
< 4; c
++) {
4897 if (!acp
[4 * r
+ c
])
4900 if (acp_level
[4 * r
+ c
] >= level
)
4901 acp
[4 * r
+ c
] = NULL
;
4904 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4909 /* Continuing the block, clear any written channels from
4912 for (int d
= 0; d
< 2; d
++) {
4913 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4914 /* Any temporary might be written, so no copy propagation
4915 * across this instruction.
4917 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4918 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4919 inst
->dst
[d
].reladdr
) {
4920 /* Any output might be written, so no copy propagation
4921 * from outputs across this instruction.
4923 for (int r
= 0; r
< this->next_temp
; r
++) {
4924 for (int c
= 0; c
< 4; c
++) {
4925 if (!acp
[4 * r
+ c
])
4928 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4929 acp
[4 * r
+ c
] = NULL
;
4932 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4933 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4934 /* Clear where it's used as dst. */
4935 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4936 for (int c
= 0; c
< 4; c
++) {
4937 if (inst
->dst
[d
].writemask
& (1 << c
))
4938 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4942 /* Clear where it's used as src. */
4943 for (int r
= 0; r
< this->next_temp
; r
++) {
4944 for (int c
= 0; c
< 4; c
++) {
4945 if (!acp
[4 * r
+ c
])
4948 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4950 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4951 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4952 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4953 acp
[4 * r
+ c
] = NULL
;
4962 /* If this is a copy, add it to the ACP. */
4963 if (inst
->op
== TGSI_OPCODE_MOV
&&
4964 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4965 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4966 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4967 !inst
->dst
[0].reladdr
&&
4968 !inst
->dst
[0].reladdr2
&&
4970 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4971 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
4972 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
4973 !inst
->src
[0].reladdr
&&
4974 !inst
->src
[0].reladdr2
&&
4975 !inst
->src
[0].negate
&&
4976 !inst
->src
[0].abs
) {
4977 for (int i
= 0; i
< 4; i
++) {
4978 if (inst
->dst
[0].writemask
& (1 << i
)) {
4979 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4980 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4986 ralloc_free(acp_level
);
4991 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
4993 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
4994 /* Clear where it's used as src. */
4995 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
4996 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5001 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5004 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5005 * will occur. As an example, a TXP production after copy propagation but
5008 * 0: MOV TEMP[1], INPUT[4].xyyy;
5009 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5010 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5012 * and after this pass:
5014 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5017 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5019 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5020 glsl_to_tgsi_instruction
*,
5021 this->next_temp
* 4);
5022 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5026 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5027 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5028 || inst
->dst
[0].index
< this->next_temp
);
5031 case TGSI_OPCODE_BGNLOOP
:
5032 case TGSI_OPCODE_ENDLOOP
:
5033 case TGSI_OPCODE_CONT
:
5034 case TGSI_OPCODE_BRK
:
5035 /* End of a basic block, clear the write array entirely.
5037 * This keeps us from killing dead code when the writes are
5038 * on either side of a loop, even when the register isn't touched
5039 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5040 * dead code of this type, so it shouldn't make a difference as long as
5041 * the dead code elimination pass in the GLSL compiler does its job.
5043 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5046 case TGSI_OPCODE_ENDIF
:
5047 case TGSI_OPCODE_ELSE
:
5048 /* Promote the recorded level of all channels written inside the
5049 * preceding if or else block to the level above the if/else block.
5051 for (int r
= 0; r
< this->next_temp
; r
++) {
5052 for (int c
= 0; c
< 4; c
++) {
5053 if (!writes
[4 * r
+ c
])
5056 if (write_level
[4 * r
+ c
] == level
)
5057 write_level
[4 * r
+ c
] = level
-1;
5060 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5064 case TGSI_OPCODE_IF
:
5065 case TGSI_OPCODE_UIF
:
5067 /* fallthrough to default case to mark the condition as read */
5069 /* Continuing the block, clear any channels from the write array that
5070 * are read by this instruction.
5072 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5073 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5074 /* Any temporary might be read, so no dead code elimination
5075 * across this instruction.
5077 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5078 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5079 /* Clear where it's used as src. */
5080 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5081 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5082 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5083 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5085 for (int c
= 0; c
< 4; c
++) {
5086 if (src_chans
& (1 << c
))
5087 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5090 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5091 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5093 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5094 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5095 /* Any temporary might be read, so no dead code elimination
5096 * across this instruction.
5098 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5099 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5100 /* Clear where it's used as src. */
5101 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5102 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5103 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5104 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5106 for (int c
= 0; c
< 4; c
++) {
5107 if (src_chans
& (1 << c
))
5108 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5111 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5112 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5115 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5118 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5119 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5120 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5121 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5123 for (int c
= 0; c
< 4; c
++) {
5124 if (src_chans
& (1 << c
))
5125 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5128 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5129 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5131 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5132 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5133 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5138 /* If this instruction writes to a temporary, add it to the write array.
5139 * If there is already an instruction in the write array for one or more
5140 * of the channels, flag that channel write as dead.
5142 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5143 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5144 !inst
->dst
[i
].reladdr
) {
5145 for (int c
= 0; c
< 4; c
++) {
5146 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5147 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5148 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5151 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5153 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5154 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5161 /* Anything still in the write array at this point is dead code. */
5162 for (int r
= 0; r
< this->next_temp
; r
++) {
5163 for (int c
= 0; c
< 4; c
++) {
5164 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5166 inst
->dead_mask
|= (1 << c
);
5170 /* Now actually remove the instructions that are completely dead and update
5171 * the writemask of other instructions with dead channels.
5173 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5174 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5176 /* No amount of dead masks should remove memory stores */
5177 if (inst
->info
->is_store
)
5180 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5185 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5186 if (inst
->dead_mask
== WRITEMASK_XY
||
5187 inst
->dead_mask
== WRITEMASK_ZW
)
5188 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5190 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5194 ralloc_free(write_level
);
5195 ralloc_free(writes
);
5200 /* merge DFRACEXP instructions into one. */
5202 glsl_to_tgsi_visitor::merge_two_dsts(void)
5204 /* We never delete inst, but we may delete its successor. */
5205 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5206 glsl_to_tgsi_instruction
*inst2
;
5209 if (num_inst_dst_regs(inst
) != 2)
5212 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5213 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5216 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5217 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5219 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5224 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5226 if (inst
->op
== inst2
->op
&&
5227 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5228 inst
->src
[0].file
== inst2
->src
[0].file
&&
5229 inst
->src
[0].index
== inst2
->src
[0].index
&&
5230 inst
->src
[0].type
== inst2
->src
[0].type
&&
5231 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5233 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5237 /* Undefined destinations are not allowed, substitute with an unused
5238 * temporary register.
5240 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5241 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5242 inst
->dst
[defined
^ 1].writemask
= 0;
5246 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5252 /* Merges temporary registers together where possible to reduce the number of
5253 * registers needed to run a program.
5255 * Produces optimal code only after copy propagation and dead code elimination
5258 glsl_to_tgsi_visitor::merge_registers(void)
5261 struct lifetime
*lifetimes
=
5262 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5264 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5265 this->next_temp
, lifetimes
)) {
5266 struct rename_reg_pair
*renames
=
5267 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5268 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5269 rename_temp_registers(renames
);
5270 ralloc_free(renames
);
5273 ralloc_free(lifetimes
);
5276 /* Reassign indices to temporary registers by reusing unused indices created
5277 * by optimization passes. */
5279 glsl_to_tgsi_visitor::renumber_registers(void)
5283 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5284 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5286 for (i
= 0; i
< this->next_temp
; i
++) {
5287 first_writes
[i
] = -1;
5289 get_first_temp_write(first_writes
);
5291 for (i
= 0; i
< this->next_temp
; i
++) {
5292 if (first_writes
[i
] < 0) continue;
5293 if (i
!= new_index
) {
5294 renames
[i
].new_reg
= new_index
;
5295 renames
[i
].valid
= true;
5300 rename_temp_registers(renames
);
5301 this->next_temp
= new_index
;
5302 ralloc_free(renames
);
5303 ralloc_free(first_writes
);
5306 /* ------------------------- TGSI conversion stuff -------------------------- */
5309 * Intermediate state used during shader translation.
5311 struct st_translate
{
5312 struct ureg_program
*ureg
;
5314 unsigned temps_size
;
5315 struct ureg_dst
*temps
;
5317 struct ureg_dst
*arrays
;
5318 unsigned num_temp_arrays
;
5319 struct ureg_src
*constants
;
5321 struct ureg_src
*immediates
;
5323 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5324 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5325 struct ureg_dst address
[3];
5326 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5327 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5328 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5329 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5330 struct ureg_src shared_memory
;
5331 unsigned *array_sizes
;
5332 struct inout_decl
*input_decls
;
5333 unsigned num_input_decls
;
5334 struct inout_decl
*output_decls
;
5335 unsigned num_output_decls
;
5337 const ubyte
*inputMapping
;
5338 const ubyte
*outputMapping
;
5340 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5344 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5346 _mesa_sysval_to_semantic(unsigned sysval
)
5350 case SYSTEM_VALUE_VERTEX_ID
:
5351 return TGSI_SEMANTIC_VERTEXID
;
5352 case SYSTEM_VALUE_INSTANCE_ID
:
5353 return TGSI_SEMANTIC_INSTANCEID
;
5354 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5355 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5356 case SYSTEM_VALUE_BASE_VERTEX
:
5357 return TGSI_SEMANTIC_BASEVERTEX
;
5358 case SYSTEM_VALUE_BASE_INSTANCE
:
5359 return TGSI_SEMANTIC_BASEINSTANCE
;
5360 case SYSTEM_VALUE_DRAW_ID
:
5361 return TGSI_SEMANTIC_DRAWID
;
5363 /* Geometry shader */
5364 case SYSTEM_VALUE_INVOCATION_ID
:
5365 return TGSI_SEMANTIC_INVOCATIONID
;
5367 /* Fragment shader */
5368 case SYSTEM_VALUE_FRAG_COORD
:
5369 return TGSI_SEMANTIC_POSITION
;
5370 case SYSTEM_VALUE_FRONT_FACE
:
5371 return TGSI_SEMANTIC_FACE
;
5372 case SYSTEM_VALUE_SAMPLE_ID
:
5373 return TGSI_SEMANTIC_SAMPLEID
;
5374 case SYSTEM_VALUE_SAMPLE_POS
:
5375 return TGSI_SEMANTIC_SAMPLEPOS
;
5376 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5377 return TGSI_SEMANTIC_SAMPLEMASK
;
5378 case SYSTEM_VALUE_HELPER_INVOCATION
:
5379 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5381 /* Tessellation shader */
5382 case SYSTEM_VALUE_TESS_COORD
:
5383 return TGSI_SEMANTIC_TESSCOORD
;
5384 case SYSTEM_VALUE_VERTICES_IN
:
5385 return TGSI_SEMANTIC_VERTICESIN
;
5386 case SYSTEM_VALUE_PRIMITIVE_ID
:
5387 return TGSI_SEMANTIC_PRIMID
;
5388 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5389 return TGSI_SEMANTIC_TESSOUTER
;
5390 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5391 return TGSI_SEMANTIC_TESSINNER
;
5393 /* Compute shader */
5394 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5395 return TGSI_SEMANTIC_THREAD_ID
;
5396 case SYSTEM_VALUE_WORK_GROUP_ID
:
5397 return TGSI_SEMANTIC_BLOCK_ID
;
5398 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5399 return TGSI_SEMANTIC_GRID_SIZE
;
5400 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5401 return TGSI_SEMANTIC_BLOCK_SIZE
;
5403 /* ARB_shader_ballot */
5404 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5405 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5406 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5407 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5408 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5409 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5410 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5411 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5412 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5413 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5414 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5415 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5416 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5417 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5420 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5421 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5422 case SYSTEM_VALUE_VERTEX_CNT
:
5424 assert(!"Unexpected SYSTEM_VALUE_ enum");
5425 return TGSI_SEMANTIC_COUNT
;
5430 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5432 static struct ureg_src
5433 emit_immediate(struct st_translate
*t
,
5434 gl_constant_value values
[4],
5437 struct ureg_program
*ureg
= t
->ureg
;
5442 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5444 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5446 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5447 case GL_UNSIGNED_INT64_ARB
:
5448 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5450 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5451 case GL_UNSIGNED_INT
:
5453 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5455 assert(!"should not get here - type must be float, int, uint, or bool");
5456 return ureg_src_undef();
5461 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5463 static struct ureg_dst
5464 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5470 case PROGRAM_UNDEFINED
:
5471 return ureg_dst_undef();
5473 case PROGRAM_TEMPORARY
:
5474 /* Allocate space for temporaries on demand. */
5475 if (index
>= t
->temps_size
) {
5476 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5478 t
->temps
= (struct ureg_dst
*)
5480 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5482 return ureg_dst_undef();
5484 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5485 t
->temps_size
+= inc
;
5488 if (ureg_dst_is_undef(t
->temps
[index
]))
5489 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5491 return t
->temps
[index
];
5494 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5495 array
= array_id
- 1;
5497 if (ureg_dst_is_undef(t
->arrays
[array
]))
5498 t
->arrays
[array
] = ureg_DECL_array_temporary(
5499 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5501 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5503 case PROGRAM_OUTPUT
:
5505 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5506 assert(index
< 2 * FRAG_RESULT_MAX
);
5507 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5508 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5509 assert(index
< VARYING_SLOT_TESS_MAX
);
5511 assert(index
< VARYING_SLOT_MAX
);
5513 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5514 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5515 return t
->outputs
[t
->outputMapping
[index
]];
5518 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5519 unsigned mesa_index
= decl
->mesa_index
;
5520 int slot
= t
->outputMapping
[mesa_index
];
5522 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5524 struct ureg_dst dst
= t
->outputs
[slot
];
5525 dst
.ArrayID
= array_id
;
5526 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5529 case PROGRAM_ADDRESS
:
5530 return t
->address
[index
];
5533 assert(!"unknown dst register file");
5534 return ureg_dst_undef();
5538 static struct ureg_src
5539 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5541 static struct ureg_src
5542 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5543 unsigned addr_index
)
5545 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5546 return ureg_src(t
->address
[addr_index
]);
5548 return translate_src(t
, reladdr
);
5552 * Create a TGSI ureg_dst register from an st_dst_reg.
5554 static struct ureg_dst
5555 translate_dst(struct st_translate
*t
,
5556 const st_dst_reg
*dst_reg
,
5559 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5562 if (dst
.File
== TGSI_FILE_NULL
)
5565 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5568 dst
= ureg_saturate(dst
);
5570 if (dst_reg
->reladdr
!= NULL
) {
5571 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5572 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5575 if (dst_reg
->has_index2
) {
5576 if (dst_reg
->reladdr2
)
5577 dst
= ureg_dst_dimension_indirect(dst
,
5578 translate_addr(t
, dst_reg
->reladdr2
, 1),
5581 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5588 * Create a TGSI ureg_src register from an st_src_reg.
5590 static struct ureg_src
5591 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5593 struct ureg_src src
;
5594 int index
= src_reg
->index
;
5595 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5597 switch(src_reg
->file
) {
5598 case PROGRAM_UNDEFINED
:
5599 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5602 case PROGRAM_TEMPORARY
:
5604 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
));
5607 case PROGRAM_OUTPUT
: {
5608 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
);
5609 assert(dst
.WriteMask
!= 0);
5610 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5611 src
= ureg_swizzle(ureg_src(dst
),
5615 MIN2(shift
+ 3, 3));
5619 case PROGRAM_UNIFORM
:
5620 assert(src_reg
->index
>= 0);
5621 src
= src_reg
->index
< t
->num_constants
?
5622 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5624 case PROGRAM_STATE_VAR
:
5625 case PROGRAM_CONSTANT
: /* ie, immediate */
5626 if (src_reg
->has_index2
)
5627 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5629 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5630 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5633 case PROGRAM_IMMEDIATE
:
5634 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5635 src
= t
->immediates
[src_reg
->index
];
5639 /* GLSL inputs are 64-bit containers, so we have to
5640 * map back to the original index and add the offset after
5642 index
-= double_reg2
;
5643 if (!src_reg
->array_id
) {
5644 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5645 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5646 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5649 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
,
5651 unsigned mesa_index
= decl
->mesa_index
;
5652 int slot
= t
->inputMapping
[mesa_index
];
5654 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5656 src
= t
->inputs
[slot
];
5657 src
.ArrayID
= src_reg
->array_id
;
5658 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5662 case PROGRAM_ADDRESS
:
5663 src
= ureg_src(t
->address
[src_reg
->index
]);
5666 case PROGRAM_SYSTEM_VALUE
:
5667 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5668 src
= t
->systemValues
[src_reg
->index
];
5672 assert(!"unknown src register file");
5673 return ureg_src_undef();
5676 if (src_reg
->has_index2
) {
5677 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5678 * and UBO constant buffers (buffer, position).
5680 if (src_reg
->reladdr2
)
5681 src
= ureg_src_dimension_indirect(src
,
5682 translate_addr(t
, src_reg
->reladdr2
, 1),
5685 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5688 src
= ureg_swizzle(src
,
5689 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5690 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5691 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5692 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5695 src
= ureg_abs(src
);
5697 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5698 src
= ureg_negate(src
);
5700 if (src_reg
->reladdr
!= NULL
) {
5701 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5702 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5708 static struct tgsi_texture_offset
5709 translate_tex_offset(struct st_translate
*t
,
5710 const st_src_reg
*in_offset
)
5712 struct tgsi_texture_offset offset
;
5713 struct ureg_src src
= translate_src(t
, in_offset
);
5715 offset
.File
= src
.File
;
5716 offset
.Index
= src
.Index
;
5717 offset
.SwizzleX
= src
.SwizzleX
;
5718 offset
.SwizzleY
= src
.SwizzleY
;
5719 offset
.SwizzleZ
= src
.SwizzleZ
;
5722 assert(!src
.Indirect
);
5723 assert(!src
.DimIndirect
);
5724 assert(!src
.Dimension
);
5725 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5726 assert(!src
.Negate
);
5732 compile_tgsi_instruction(struct st_translate
*t
,
5733 const glsl_to_tgsi_instruction
*inst
)
5735 struct ureg_program
*ureg
= t
->ureg
;
5737 struct ureg_dst dst
[2];
5738 struct ureg_src src
[4];
5739 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5743 unsigned tex_target
= 0;
5745 num_dst
= num_inst_dst_regs(inst
);
5746 num_src
= num_inst_src_regs(inst
);
5748 for (i
= 0; i
< num_dst
; i
++)
5749 dst
[i
] = translate_dst(t
,
5753 for (i
= 0; i
< num_src
; i
++)
5754 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5757 case TGSI_OPCODE_BGNLOOP
:
5758 case TGSI_OPCODE_ELSE
:
5759 case TGSI_OPCODE_ENDLOOP
:
5760 case TGSI_OPCODE_IF
:
5761 case TGSI_OPCODE_UIF
:
5762 assert(num_dst
== 0);
5763 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5766 case TGSI_OPCODE_TEX
:
5767 case TGSI_OPCODE_TEX_LZ
:
5768 case TGSI_OPCODE_TXB
:
5769 case TGSI_OPCODE_TXD
:
5770 case TGSI_OPCODE_TXL
:
5771 case TGSI_OPCODE_TXP
:
5772 case TGSI_OPCODE_TXQ
:
5773 case TGSI_OPCODE_TXQS
:
5774 case TGSI_OPCODE_TXF
:
5775 case TGSI_OPCODE_TXF_LZ
:
5776 case TGSI_OPCODE_TEX2
:
5777 case TGSI_OPCODE_TXB2
:
5778 case TGSI_OPCODE_TXL2
:
5779 case TGSI_OPCODE_TG4
:
5780 case TGSI_OPCODE_LODQ
:
5781 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5782 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5784 /* Bindless samplers. */
5785 src
[num_src
] = translate_src(t
, &inst
->resource
);
5787 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5788 if (inst
->resource
.reladdr
)
5790 ureg_src_indirect(src
[num_src
],
5791 translate_addr(t
, inst
->resource
.reladdr
, 2));
5793 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5794 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5796 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5802 st_translate_texture_type(inst
->tex_type
),
5803 texoffsets
, inst
->tex_offset_num_offset
,
5807 case TGSI_OPCODE_RESQ
:
5808 case TGSI_OPCODE_LOAD
:
5809 case TGSI_OPCODE_ATOMUADD
:
5810 case TGSI_OPCODE_ATOMXCHG
:
5811 case TGSI_OPCODE_ATOMCAS
:
5812 case TGSI_OPCODE_ATOMAND
:
5813 case TGSI_OPCODE_ATOMOR
:
5814 case TGSI_OPCODE_ATOMXOR
:
5815 case TGSI_OPCODE_ATOMUMIN
:
5816 case TGSI_OPCODE_ATOMUMAX
:
5817 case TGSI_OPCODE_ATOMIMIN
:
5818 case TGSI_OPCODE_ATOMIMAX
:
5819 for (i
= num_src
- 1; i
>= 0; i
--)
5820 src
[i
+ 1] = src
[i
];
5822 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5823 src
[0] = t
->shared_memory
;
5824 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5825 src
[0] = t
->buffers
[inst
->resource
.index
];
5826 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
5827 assert(inst
->resource
.has_index2
);
5828 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
5830 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
5831 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5832 src
[0] = t
->images
[inst
->resource
.index
];
5834 /* Bindless images. */
5835 src
[0] = translate_src(t
, &inst
->resource
);
5837 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5839 if (inst
->resource
.reladdr
)
5840 src
[0] = ureg_src_indirect(src
[0],
5841 translate_addr(t
, inst
->resource
.reladdr
, 2));
5842 assert(src
[0].File
!= TGSI_FILE_NULL
);
5843 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5844 inst
->buffer_access
,
5845 tex_target
, inst
->image_format
);
5848 case TGSI_OPCODE_STORE
:
5849 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5850 dst
[0] = ureg_dst(t
->shared_memory
);
5851 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5852 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5854 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5855 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5857 /* Bindless images. */
5858 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
5860 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5862 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5863 if (inst
->resource
.reladdr
)
5864 dst
[0] = ureg_dst_indirect(dst
[0],
5865 translate_addr(t
, inst
->resource
.reladdr
, 2));
5866 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5867 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5868 inst
->buffer_access
,
5869 tex_target
, inst
->image_format
);
5876 src
, num_src
, inst
->precise
);
5882 * Emit the TGSI instructions for inverting and adjusting WPOS.
5883 * This code is unavoidable because it also depends on whether
5884 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5887 emit_wpos_adjustment(struct gl_context
*ctx
,
5888 struct st_translate
*t
,
5889 int wpos_transform_const
,
5891 GLfloat adjX
, GLfloat adjY
[2])
5893 struct ureg_program
*ureg
= t
->ureg
;
5895 assert(wpos_transform_const
>= 0);
5897 /* Fragment program uses fragment position input.
5898 * Need to replace instances of INPUT[WPOS] with temp T
5899 * where T = INPUT[WPOS] is inverted by Y.
5901 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5902 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5903 struct ureg_src
*wpos
=
5904 ctx
->Const
.GLSLFragCoordIsSysVal
?
5905 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5906 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5907 struct ureg_src wpos_input
= *wpos
;
5909 /* First, apply the coordinate shift: */
5910 if (adjX
|| adjY
[0] || adjY
[1]) {
5911 if (adjY
[0] != adjY
[1]) {
5912 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5913 * depending on whether inversion is actually going to be applied
5914 * or not, which is determined by testing against the inversion
5915 * state variable used below, which will be either +1 or -1.
5917 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5919 ureg_CMP(ureg
, adj_temp
,
5920 ureg_scalar(wpostrans
, invert
? 2 : 0),
5921 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5922 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5923 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5925 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5926 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5928 wpos_input
= ureg_src(wpos_temp
);
5930 /* MOV wpos_temp, input[wpos]
5932 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5935 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5936 * inversion/identity, or the other way around if we're drawing to an FBO.
5939 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5942 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5944 ureg_scalar(wpostrans
, 0),
5945 ureg_scalar(wpostrans
, 1));
5947 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5950 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5952 ureg_scalar(wpostrans
, 2),
5953 ureg_scalar(wpostrans
, 3));
5956 /* Use wpos_temp as position input from here on:
5958 *wpos
= ureg_src(wpos_temp
);
5963 * Emit fragment position/ooordinate code.
5966 emit_wpos(struct st_context
*st
,
5967 struct st_translate
*t
,
5968 const struct gl_program
*program
,
5969 struct ureg_program
*ureg
,
5970 int wpos_transform_const
)
5972 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5973 GLfloat adjX
= 0.0f
;
5974 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5975 boolean invert
= FALSE
;
5977 /* Query the pixel center conventions supported by the pipe driver and set
5978 * adjX, adjY to help out if it cannot handle the requested one internally.
5980 * The bias of the y-coordinate depends on whether y-inversion takes place
5981 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5982 * drawing to an FBO (causes additional inversion), and whether the pipe
5983 * driver origin and the requested origin differ (the latter condition is
5984 * stored in the 'invert' variable).
5986 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5988 * center shift only:
5993 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5994 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5995 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5996 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5998 * inversion and center shift:
5999 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6000 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6001 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6002 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6004 if (program
->OriginUpperLeft
) {
6005 /* Fragment shader wants origin in upper-left */
6006 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6007 /* the driver supports upper-left origin */
6009 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6010 /* the driver supports lower-left origin, need to invert Y */
6011 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6012 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6019 /* Fragment shader wants origin in lower-left */
6020 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6021 /* the driver supports lower-left origin */
6022 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6023 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6024 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6025 /* the driver supports upper-left origin, need to invert Y */
6031 if (program
->PixelCenterInteger
) {
6032 /* Fragment shader wants pixel center integer */
6033 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6034 /* the driver supports pixel center integer */
6036 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6037 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6039 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6040 /* the driver supports pixel center half integer, need to bias X,Y */
6049 /* Fragment shader wants pixel center half integer */
6050 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6051 /* the driver supports pixel center half integer */
6053 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6054 /* the driver supports pixel center integer, need to bias X,Y */
6055 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6056 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6057 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6063 /* we invert after adjustment so that we avoid the MOV to temporary,
6064 * and reuse the adjustment ADD instead */
6065 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6069 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6070 * TGSI uses +1 for front, -1 for back.
6071 * This function converts the TGSI value to the GL value. Simply clamping/
6072 * saturating the value to [0,1] does the job.
6075 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6077 struct ureg_program
*ureg
= t
->ureg
;
6078 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6079 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6081 if (ctx
->Const
.NativeIntegers
) {
6082 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6085 /* MOV_SAT face_temp, input[face] */
6086 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6089 /* Use face_temp as face input from here on: */
6090 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6094 emit_compute_block_size(const struct gl_program
*prog
,
6095 struct ureg_program
*ureg
) {
6096 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6097 prog
->info
.cs
.local_size
[0]);
6098 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6099 prog
->info
.cs
.local_size
[1]);
6100 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6101 prog
->info
.cs
.local_size
[2]);
6104 struct sort_inout_decls
{
6105 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6106 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6109 const ubyte
*mapping
;
6112 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6114 * This is for the benefit of older drivers which are broken when the
6115 * declarations aren't sorted in this way.
6118 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6120 const ubyte mapping
[])
6122 sort_inout_decls sorter
;
6123 sorter
.mapping
= mapping
;
6124 std::sort(decls
, decls
+ count
, sorter
);
6128 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6130 switch (glsl_qual
) {
6131 case INTERP_MODE_NONE
:
6132 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6133 return TGSI_INTERPOLATE_COLOR
;
6134 return TGSI_INTERPOLATE_PERSPECTIVE
;
6135 case INTERP_MODE_SMOOTH
:
6136 return TGSI_INTERPOLATE_PERSPECTIVE
;
6137 case INTERP_MODE_FLAT
:
6138 return TGSI_INTERPOLATE_CONSTANT
;
6139 case INTERP_MODE_NOPERSPECTIVE
:
6140 return TGSI_INTERPOLATE_LINEAR
;
6142 assert(0 && "unexpected interp mode in st_translate_interp()");
6143 return TGSI_INTERPOLATE_PERSPECTIVE
;
6148 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6149 * \param program the program to translate
6150 * \param numInputs number of input registers used
6151 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6153 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6154 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6156 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6157 * \param numOutputs number of output registers used
6158 * \param outputMapping maps Mesa fragment program outputs to TGSI
6160 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6161 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6164 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6166 extern "C" enum pipe_error
6167 st_translate_program(
6168 struct gl_context
*ctx
,
6170 struct ureg_program
*ureg
,
6171 glsl_to_tgsi_visitor
*program
,
6172 const struct gl_program
*proginfo
,
6174 const ubyte inputMapping
[],
6175 const ubyte inputSlotToAttr
[],
6176 const ubyte inputSemanticName
[],
6177 const ubyte inputSemanticIndex
[],
6178 const ubyte interpMode
[],
6180 const ubyte outputMapping
[],
6181 const ubyte outputSemanticName
[],
6182 const ubyte outputSemanticIndex
[])
6184 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6185 struct st_translate
*t
;
6187 struct gl_program_constants
*frag_const
=
6188 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6189 enum pipe_error ret
= PIPE_OK
;
6191 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6192 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6194 t
= CALLOC_STRUCT(st_translate
);
6196 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6200 t
->procType
= procType
;
6201 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6202 t
->inputMapping
= inputMapping
;
6203 t
->outputMapping
= outputMapping
;
6205 t
->num_temp_arrays
= program
->next_array
;
6206 if (t
->num_temp_arrays
)
6207 t
->arrays
= (struct ureg_dst
*)
6208 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6211 * Declare input attributes.
6214 case PIPE_SHADER_FRAGMENT
:
6215 case PIPE_SHADER_GEOMETRY
:
6216 case PIPE_SHADER_TESS_EVAL
:
6217 case PIPE_SHADER_TESS_CTRL
:
6218 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6220 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6221 struct inout_decl
*decl
= &program
->inputs
[i
];
6222 unsigned slot
= inputMapping
[decl
->mesa_index
];
6223 struct ureg_src src
;
6224 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6226 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6227 if (tgsi_usage_mask
== 1)
6228 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6229 else if (tgsi_usage_mask
== 2)
6230 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6232 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6235 unsigned interp_mode
= 0;
6236 unsigned interp_location
= 0;
6237 if (procType
== PIPE_SHADER_FRAGMENT
) {
6239 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6241 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6243 interp_location
= decl
->interp_loc
;
6246 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6247 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6248 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6249 decl
->array_id
, decl
->size
);
6251 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6252 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6253 /* The ArrayID is set up in dst_register */
6254 t
->inputs
[slot
+ j
] = src
;
6255 t
->inputs
[slot
+ j
].ArrayID
= 0;
6256 t
->inputs
[slot
+ j
].Index
+= j
;
6261 case PIPE_SHADER_VERTEX
:
6262 for (i
= 0; i
< numInputs
; i
++) {
6263 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6266 case PIPE_SHADER_COMPUTE
:
6273 * Declare output attributes.
6276 case PIPE_SHADER_FRAGMENT
:
6277 case PIPE_SHADER_COMPUTE
:
6279 case PIPE_SHADER_GEOMETRY
:
6280 case PIPE_SHADER_TESS_EVAL
:
6281 case PIPE_SHADER_TESS_CTRL
:
6282 case PIPE_SHADER_VERTEX
:
6283 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6285 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6286 struct inout_decl
*decl
= &program
->outputs
[i
];
6287 unsigned slot
= outputMapping
[decl
->mesa_index
];
6288 struct ureg_dst dst
;
6289 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6291 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6292 if (tgsi_usage_mask
== 1)
6293 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6294 else if (tgsi_usage_mask
== 2)
6295 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6297 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6300 dst
= ureg_DECL_output_layout(ureg
,
6301 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6302 decl
->gs_out_streams
,
6303 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6305 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6306 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6307 /* The ArrayID is set up in dst_register */
6308 t
->outputs
[slot
+ j
] = dst
;
6309 t
->outputs
[slot
+ j
].ArrayID
= 0;
6310 t
->outputs
[slot
+ j
].Index
+= j
;
6319 if (procType
== PIPE_SHADER_FRAGMENT
) {
6320 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6321 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6322 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6324 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6325 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6328 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6329 /* Must do this after setting up t->inputs. */
6330 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6331 program
->wpos_transform_const
);
6334 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6335 emit_face_var(ctx
, t
);
6337 for (i
= 0; i
< numOutputs
; i
++) {
6338 switch (outputSemanticName
[i
]) {
6339 case TGSI_SEMANTIC_POSITION
:
6340 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6341 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6342 outputSemanticIndex
[i
]);
6343 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6345 case TGSI_SEMANTIC_STENCIL
:
6346 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6347 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6348 outputSemanticIndex
[i
]);
6349 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6351 case TGSI_SEMANTIC_COLOR
:
6352 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6353 TGSI_SEMANTIC_COLOR
,
6354 outputSemanticIndex
[i
]);
6356 case TGSI_SEMANTIC_SAMPLEMASK
:
6357 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6358 TGSI_SEMANTIC_SAMPLEMASK
,
6359 outputSemanticIndex
[i
]);
6360 /* TODO: If we ever support more than 32 samples, this will have
6361 * to become an array.
6363 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6366 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6367 ret
= PIPE_ERROR_BAD_INPUT
;
6372 else if (procType
== PIPE_SHADER_VERTEX
) {
6373 for (i
= 0; i
< numOutputs
; i
++) {
6374 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6375 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6377 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6378 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6379 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6384 if (procType
== PIPE_SHADER_COMPUTE
) {
6385 emit_compute_block_size(proginfo
, ureg
);
6388 /* Declare address register.
6390 if (program
->num_address_regs
> 0) {
6391 assert(program
->num_address_regs
<= 3);
6392 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6393 t
->address
[i
] = ureg_DECL_address(ureg
);
6396 /* Declare misc input registers
6399 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6401 for (i
= 0; sysInputs
; i
++) {
6402 if (sysInputs
& (1 << i
)) {
6403 unsigned semName
= _mesa_sysval_to_semantic(i
);
6405 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6407 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6408 semName
== TGSI_SEMANTIC_VERTEXID
) {
6409 /* From Gallium perspective, these system values are always
6410 * integer, and require native integer support. However, if
6411 * native integer is supported on the vertex stage but not the
6412 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6413 * assumes these system values are floats. To resolve the
6414 * inconsistency, we insert a U2F.
6416 struct st_context
*st
= st_context(ctx
);
6417 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6418 assert(procType
== PIPE_SHADER_VERTEX
);
6419 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6421 if (!ctx
->Const
.NativeIntegers
) {
6422 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6423 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6424 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6428 if (procType
== PIPE_SHADER_FRAGMENT
&&
6429 semName
== TGSI_SEMANTIC_POSITION
)
6430 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6431 program
->wpos_transform_const
);
6433 sysInputs
&= ~(1 << i
);
6438 t
->array_sizes
= program
->array_sizes
;
6439 t
->input_decls
= program
->inputs
;
6440 t
->num_input_decls
= program
->num_inputs
;
6441 t
->output_decls
= program
->outputs
;
6442 t
->num_output_decls
= program
->num_outputs
;
6444 /* Emit constants and uniforms. TGSI uses a single index space for these,
6445 * so we put all the translated regs in t->constants.
6447 if (proginfo
->Parameters
) {
6448 t
->constants
= (struct ureg_src
*)
6449 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6450 if (t
->constants
== NULL
) {
6451 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6454 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6456 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6457 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6458 case PROGRAM_STATE_VAR
:
6459 case PROGRAM_UNIFORM
:
6460 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6463 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6464 * addressing of the const buffer.
6465 * FIXME: Be smarter and recognize param arrays:
6466 * indirect addressing is only valid within the referenced
6469 case PROGRAM_CONSTANT
:
6470 if (program
->indirect_addr_consts
)
6471 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6473 t
->constants
[i
] = emit_immediate(t
,
6474 proginfo
->Parameters
->ParameterValues
[i
],
6475 proginfo
->Parameters
->Parameters
[i
].DataType
,
6484 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6485 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6486 unsigned num_const_vecs
= (size
+ 15) / 16;
6487 unsigned first
, last
;
6488 assert(num_const_vecs
> 0);
6490 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6491 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6494 /* Emit immediate values.
6496 t
->immediates
= (struct ureg_src
*)
6497 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6498 if (t
->immediates
== NULL
) {
6499 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6502 t
->num_immediates
= program
->num_immediates
;
6505 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6506 assert(i
< program
->num_immediates
);
6507 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6509 assert(i
== program
->num_immediates
);
6511 /* texture samplers */
6512 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6513 if (program
->samplers_used
& (1u << i
)) {
6514 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6516 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6518 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6519 type
, type
, type
, type
);
6523 /* Declare atomic and shader storage buffers. */
6525 struct gl_program
*prog
= program
->prog
;
6527 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6528 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6529 assert(index
< frag_const
->MaxAtomicBuffers
);
6530 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6533 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6534 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6535 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6536 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6540 if (program
->use_shared_memory
)
6541 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6543 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6544 if (program
->images_used
& (1 << i
)) {
6545 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6546 program
->image_targets
[i
],
6547 program
->image_formats
[i
],
6552 /* Emit each instruction in turn:
6554 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6555 compile_tgsi_instruction(t
, inst
);
6557 /* Set the next shader stage hint for VS and TES. */
6559 case PIPE_SHADER_VERTEX
:
6560 case PIPE_SHADER_TESS_EVAL
:
6561 if (program
->shader_program
->SeparateShader
)
6564 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6565 if (program
->shader_program
->_LinkedShaders
[i
]) {
6566 ureg_set_next_shader_processor(
6567 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6579 t
->num_constants
= 0;
6580 free(t
->immediates
);
6581 t
->num_immediates
= 0;
6587 /* ----------------------------- End TGSI code ------------------------------ */
6591 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6592 * generating Mesa IR.
6594 static struct gl_program
*
6595 get_mesa_program_tgsi(struct gl_context
*ctx
,
6596 struct gl_shader_program
*shader_program
,
6597 struct gl_linked_shader
*shader
)
6599 glsl_to_tgsi_visitor
* v
;
6600 struct gl_program
*prog
;
6601 struct gl_shader_compiler_options
*options
=
6602 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6603 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6604 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6605 unsigned skip_merge_registers
;
6607 validate_ir_tree(shader
->ir
);
6609 prog
= shader
->Program
;
6611 prog
->Parameters
= _mesa_new_parameter_list();
6612 v
= new glsl_to_tgsi_visitor();
6615 v
->shader_program
= shader_program
;
6617 v
->options
= options
;
6618 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6619 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6621 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6622 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6623 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6624 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6625 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6626 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6627 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6629 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6630 _mesa_key_pointer_equal
);
6631 skip_merge_registers
=
6632 pscreen
->get_shader_param(pscreen
, ptarget
,
6633 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6635 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6638 /* Remove reads from output registers. */
6639 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6640 lower_output_reads(shader
->Stage
, shader
->ir
);
6642 /* Emit intermediate IR for main(). */
6643 visit_exec_list(shader
->ir
, v
);
6646 /* Print out some information (for debugging purposes) used by the
6647 * optimization passes. */
6650 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6651 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6652 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6653 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6655 for (i
= 0; i
< v
->next_temp
; i
++) {
6656 first_writes
[i
] = -1;
6657 first_reads
[i
] = -1;
6658 last_writes
[i
] = -1;
6661 v
->get_first_temp_read(first_reads
);
6662 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6663 v
->get_last_temp_write(last_writes
);
6664 for (i
= 0; i
< v
->next_temp
; i
++)
6665 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6669 ralloc_free(first_writes
);
6670 ralloc_free(first_reads
);
6671 ralloc_free(last_writes
);
6672 ralloc_free(last_reads
);
6676 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6678 v
->copy_propagate();
6680 while (v
->eliminate_dead_code());
6682 v
->merge_two_dsts();
6683 if (!skip_merge_registers
)
6684 v
->merge_registers();
6685 v
->renumber_registers();
6687 /* Write the END instruction. */
6688 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6690 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6692 _mesa_log("GLSL IR for linked %s program %d:\n",
6693 _mesa_shader_stage_to_string(shader
->Stage
),
6694 shader_program
->Name
);
6695 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6699 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6700 _mesa_copy_linked_program_data(shader_program
, shader
);
6701 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6702 &prog
->info
.inputs_read
,
6703 prog
->info
.double_inputs_read
,
6704 &prog
->info
.patch_inputs_read
);
6705 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6706 &prog
->info
.outputs_written
, 0ULL,
6707 &prog
->info
.patch_outputs_written
);
6708 count_resources(v
, prog
);
6710 /* The GLSL IR won't be needed anymore. */
6711 ralloc_free(shader
->ir
);
6714 /* This must be done before the uniform storage is associated. */
6715 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6716 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6717 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6718 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6719 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6722 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6723 wposTransformState
);
6726 /* Avoid reallocation of the program parameter list, because the uniform
6727 * storage is only associated with the original parameter list.
6728 * This should be enough for Bitmap and DrawPixels constants.
6730 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6732 /* This has to be done last. Any operation the can cause
6733 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6734 * program constant) has to happen before creating this linkage.
6736 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6737 if (!shader_program
->data
->LinkStatus
) {
6738 free_glsl_to_tgsi_visitor(v
);
6739 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6743 struct st_vertex_program
*stvp
;
6744 struct st_fragment_program
*stfp
;
6745 struct st_common_program
*stp
;
6746 struct st_compute_program
*stcp
;
6748 switch (shader
->Stage
) {
6749 case MESA_SHADER_VERTEX
:
6750 stvp
= (struct st_vertex_program
*)prog
;
6751 stvp
->glsl_to_tgsi
= v
;
6753 case MESA_SHADER_FRAGMENT
:
6754 stfp
= (struct st_fragment_program
*)prog
;
6755 stfp
->glsl_to_tgsi
= v
;
6757 case MESA_SHADER_TESS_CTRL
:
6758 case MESA_SHADER_TESS_EVAL
:
6759 case MESA_SHADER_GEOMETRY
:
6760 stp
= st_common_program(prog
);
6761 stp
->glsl_to_tgsi
= v
;
6763 case MESA_SHADER_COMPUTE
:
6764 stcp
= (struct st_compute_program
*)prog
;
6765 stcp
->glsl_to_tgsi
= v
;
6768 assert(!"should not be reached");
6775 /* See if there are unsupported control flow statements. */
6776 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6778 const struct gl_shader_compiler_options
*options
;
6780 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6786 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6788 /* Other functions are skipped (same as glsl_to_tgsi). */
6789 if (strcmp(ir
->name
, "main") == 0)
6790 return visit_continue
;
6792 return visit_continue_with_parent
;
6795 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6797 if (!ir
->callee
->is_intrinsic()) {
6798 unsupported
= true; /* it's a function call */
6801 return visit_continue
;
6804 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6806 if (options
->EmitNoMainReturn
) {
6810 return visit_continue
;
6817 has_unsupported_control_flow(exec_list
*ir
,
6818 const struct gl_shader_compiler_options
*options
)
6820 ir_control_flow_info_visitor
visitor(options
);
6821 visit_list_elements(&visitor
, ir
);
6822 return visitor
.unsupported
;
6829 * Called via ctx->Driver.LinkShader()
6830 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6831 * with code lowering and other optimizations.
6834 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6836 /* Return early if we are loading the shader from on-disk cache */
6837 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6841 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6842 assert(prog
->data
->LinkStatus
);
6844 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6845 if (prog
->_LinkedShaders
[i
] == NULL
)
6848 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6849 exec_list
*ir
= shader
->ir
;
6850 gl_shader_stage stage
= shader
->Stage
;
6851 const struct gl_shader_compiler_options
*options
=
6852 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6853 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
6854 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6855 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6856 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6857 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6858 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6859 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
6860 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6861 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6863 /* If there are forms of indirect addressing that the driver
6864 * cannot handle, perform the lowering pass.
6866 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6867 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6868 lower_variable_index_to_cond_assign(stage
, ir
,
6869 options
->EmitNoIndirectInput
,
6870 options
->EmitNoIndirectOutput
,
6871 options
->EmitNoIndirectTemp
,
6872 options
->EmitNoIndirectUniform
);
6875 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6876 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6878 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6879 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6880 LOWER_UNPACK_SNORM_2x16
|
6881 LOWER_PACK_UNORM_2x16
|
6882 LOWER_UNPACK_UNORM_2x16
|
6883 LOWER_PACK_SNORM_4x8
|
6884 LOWER_UNPACK_SNORM_4x8
|
6885 LOWER_UNPACK_UNORM_4x8
|
6886 LOWER_PACK_UNORM_4x8
;
6888 if (ctx
->Extensions
.ARB_gpu_shader5
)
6889 lower_inst
|= LOWER_PACK_USE_BFI
|
6891 if (!ctx
->st
->has_half_float_packing
)
6892 lower_inst
|= LOWER_PACK_HALF_2x16
|
6893 LOWER_UNPACK_HALF_2x16
;
6895 lower_packing_builtins(ir
, lower_inst
);
6898 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6899 lower_offset_arrays(ir
);
6900 do_mat_op_to_vec(ir
);
6902 if (stage
== MESA_SHADER_FRAGMENT
)
6903 lower_blend_equation_advanced(shader
);
6905 lower_instructions(ir
,
6910 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
6911 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6914 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6915 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6916 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6917 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6918 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6919 /* Assume that if ARB_gpu_shader5 is not supported
6920 * then all of the extended integer functions need
6921 * lowering. It may be necessary to add some caps
6922 * for individual instructions.
6924 (!ctx
->Extensions
.ARB_gpu_shader5
6925 ? BIT_COUNT_TO_MATH
|
6929 FIND_LSB_TO_FLOAT_CAST
|
6930 FIND_MSB_TO_FLOAT_CAST
|
6934 do_vec_index_to_cond_assign(ir
);
6935 lower_vector_insert(ir
, true);
6936 lower_quadop_vector(ir
, false);
6938 if (options
->MaxIfDepth
== 0) {
6942 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6943 /* Do it once and repeat only if there's unsupported control flow. */
6945 do_common_optimization(ir
, true, true, options
,
6946 ctx
->Const
.NativeIntegers
);
6947 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6948 options
->MaxIfDepth
, if_threshold
);
6949 } while (has_unsupported_control_flow(ir
, options
));
6951 /* Repeat it until it stops making changes. */
6954 progress
= do_common_optimization(ir
, true, true, options
,
6955 ctx
->Const
.NativeIntegers
);
6956 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6957 options
->MaxIfDepth
, if_threshold
);
6961 validate_ir_tree(ir
);
6964 build_program_resource_list(ctx
, prog
);
6966 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6967 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6971 enum pipe_shader_type ptarget
=
6972 pipe_shader_type_from_mesa(shader
->Stage
);
6973 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6974 pscreen
->get_shader_param(pscreen
, ptarget
,
6975 PIPE_SHADER_CAP_PREFERRED_IR
);
6977 struct gl_program
*linked_prog
= NULL
;
6978 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6979 /* TODO only for GLSL VS/FS/CS for now: */
6980 switch (shader
->Stage
) {
6981 case MESA_SHADER_VERTEX
:
6982 case MESA_SHADER_FRAGMENT
:
6983 case MESA_SHADER_COMPUTE
:
6984 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6989 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6993 st_set_prog_affected_state_flags(linked_prog
);
6994 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6995 _mesa_shader_stage_to_program(i
),
6997 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7007 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7008 const ubyte outputMapping
[],
7009 struct pipe_stream_output_info
*so
)
7011 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7014 struct gl_transform_feedback_info
*info
=
7015 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7016 st_translate_stream_output_info2(info
, outputMapping
, so
);
7020 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7021 const ubyte outputMapping
[],
7022 struct pipe_stream_output_info
*so
)
7026 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7027 so
->output
[i
].register_index
=
7028 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7029 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7030 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7031 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7032 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7033 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7036 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7037 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7039 so
->num_outputs
= info
->NumOutputs
;