2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
70 #include "util/u_atomic.h"
71 #include "util/simple_mtx.h"
75 /* Prepare to make it possible to specify log file */
76 static std::ofstream stats_log
;
78 /* Helper function to check whether we want to write some statistics
79 * of the shader conversion.
82 static simple_mtx_t print_stats_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
84 static inline bool print_stats_enabled ()
86 static int stats_enabled
= 0;
89 simple_mtx_lock(&print_stats_mutex
);
91 const char *stats_filename
= getenv("GLSL_TO_TGSI_PRINT_STATS");
93 bool write_header
= std::ifstream(stats_filename
).fail();
94 stats_log
.open(stats_filename
, std::ios_base::out
| std::ios_base::app
);
95 stats_enabled
= stats_log
.good() ? 1 : -1;
97 stats_log
<< "arrays,temps,temps in arrays,total,instructions\n";
102 simple_mtx_unlock(&print_stats_mutex
);
104 return stats_enabled
> 0;
106 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
108 #define PRINT_STATS(X)
112 static unsigned is_precise(const ir_variable
*ir
)
116 return ir
->data
.precise
|| ir
->data
.invariant
;
119 class variable_storage
{
120 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
123 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
124 unsigned array_id
= 0)
125 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
127 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
130 gl_register_file file
;
133 /* Explicit component location. This is given in terms of the GLSL-style
134 * swizzles where each double is a single component, i.e. for 64-bit types
135 * it can only be 0 or 1.
138 ir_variable
*var
; /* variable that maps to this, if any */
142 class immediate_storage
: public exec_node
{
144 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
146 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
147 this->size32
= size32
;
151 /* doubles are stored across 2 gl_constant_values */
152 gl_constant_value values
[4];
153 int size32
; /**< Number of 32-bit components (1-4) */
154 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
157 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
158 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
162 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
165 unsigned gs_out_streams
;
166 enum glsl_interp_mode interp
;
167 enum glsl_base_type base_type
;
168 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
172 static struct inout_decl
*
173 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
175 assert(array_id
!= 0);
177 for (unsigned i
= 0; i
< count
; i
++) {
178 struct inout_decl
*decl
= &decls
[i
];
180 if (array_id
== decl
->array_id
) {
188 static enum glsl_base_type
189 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
192 return GLSL_TYPE_ERROR
;
193 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
195 return decl
->base_type
;
196 return GLSL_TYPE_ERROR
;
199 struct hwatomic_decl
{
206 struct glsl_to_tgsi_visitor
: public ir_visitor
{
208 glsl_to_tgsi_visitor();
209 ~glsl_to_tgsi_visitor();
211 struct gl_context
*ctx
;
212 struct gl_program
*prog
;
213 struct gl_shader_program
*shader_program
;
214 struct gl_linked_shader
*shader
;
215 struct gl_shader_compiler_options
*options
;
219 unsigned *array_sizes
;
220 unsigned max_num_arrays
;
223 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
225 unsigned num_input_arrays
;
226 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
227 unsigned num_outputs
;
228 unsigned num_output_arrays
;
230 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
231 unsigned num_atomics
;
232 unsigned num_atomic_arrays
;
233 int num_address_regs
;
234 uint32_t samplers_used
;
235 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
236 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
238 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
239 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
240 bool image_wr
[PIPE_MAX_SHADER_IMAGES
];
241 bool indirect_addr_consts
;
242 int wpos_transform_const
;
244 bool native_integers
;
247 bool use_shared_memory
;
252 variable_storage
*find_variable_storage(ir_variable
*var
);
254 int add_constant(gl_register_file file
, gl_constant_value values
[8],
255 int size
, GLenum datatype
, uint16_t *swizzle_out
);
257 st_src_reg
get_temp(const glsl_type
*type
);
258 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
260 st_src_reg
st_src_reg_for_double(double val
);
261 st_src_reg
st_src_reg_for_float(float val
);
262 st_src_reg
st_src_reg_for_int(int val
);
263 st_src_reg
st_src_reg_for_int64(int64_t val
);
264 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
267 * \name Visit methods
269 * As typical for the visitor pattern, there must be one \c visit method for
270 * each concrete subclass of \c ir_instruction. Virtual base classes within
271 * the hierarchy should not have \c visit methods.
274 virtual void visit(ir_variable
*);
275 virtual void visit(ir_loop
*);
276 virtual void visit(ir_loop_jump
*);
277 virtual void visit(ir_function_signature
*);
278 virtual void visit(ir_function
*);
279 virtual void visit(ir_expression
*);
280 virtual void visit(ir_swizzle
*);
281 virtual void visit(ir_dereference_variable
*);
282 virtual void visit(ir_dereference_array
*);
283 virtual void visit(ir_dereference_record
*);
284 virtual void visit(ir_assignment
*);
285 virtual void visit(ir_constant
*);
286 virtual void visit(ir_call
*);
287 virtual void visit(ir_return
*);
288 virtual void visit(ir_discard
*);
289 virtual void visit(ir_texture
*);
290 virtual void visit(ir_if
*);
291 virtual void visit(ir_emit_vertex
*);
292 virtual void visit(ir_end_primitive
*);
293 virtual void visit(ir_barrier
*);
296 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
298 void visit_atomic_counter_intrinsic(ir_call
*);
299 void visit_ssbo_intrinsic(ir_call
*);
300 void visit_membar_intrinsic(ir_call
*);
301 void visit_shared_intrinsic(ir_call
*);
302 void visit_image_intrinsic(ir_call
*);
303 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
307 /** List of variable_storage */
308 struct hash_table
*variables
;
310 /** List of immediate_storage */
311 exec_list immediates
;
312 unsigned num_immediates
;
314 /** List of glsl_to_tgsi_instruction */
315 exec_list instructions
;
317 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
318 st_dst_reg dst
= undef_dst
,
319 st_src_reg src0
= undef_src
,
320 st_src_reg src1
= undef_src
,
321 st_src_reg src2
= undef_src
,
322 st_src_reg src3
= undef_src
);
324 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
325 st_dst_reg dst
, st_dst_reg dst1
,
326 st_src_reg src0
= undef_src
,
327 st_src_reg src1
= undef_src
,
328 st_src_reg src2
= undef_src
,
329 st_src_reg src3
= undef_src
);
331 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
333 st_src_reg src0
, st_src_reg src1
);
336 * Emit the correct dot-product instruction for the type of arguments
338 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
344 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
345 st_dst_reg dst
, st_src_reg src0
);
347 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
348 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
350 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
352 void get_deref_offsets(ir_dereference
*ir
,
353 unsigned *array_size
,
358 void calc_deref_offsets(ir_dereference
*tail
,
359 unsigned *array_elements
,
361 st_src_reg
*indirect
,
363 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
364 bool handle_bound_deref(ir_dereference
*ir
);
366 bool try_emit_mad(ir_expression
*ir
,
368 bool try_emit_mad_for_and_not(ir_expression
*ir
,
371 void emit_swz(ir_expression
*ir
);
373 bool process_move_condition(ir_rvalue
*ir
);
375 void simplify_cmp(void);
377 void rename_temp_registers(struct rename_reg_pair
*renames
);
378 void get_first_temp_read(int *first_reads
);
379 void get_first_temp_write(int *first_writes
);
380 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
381 void get_last_temp_write(int *last_writes
);
383 void copy_propagate(void);
384 int eliminate_dead_code(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
390 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
391 st_dst_reg
*l
, st_src_reg
*r
,
392 st_src_reg
*cond
, bool cond_swap
);
399 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
401 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
403 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
407 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
411 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
415 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
418 prog
->data
->LinkStatus
= LINKING_FAILURE
;
422 swizzle_for_size(int size
)
424 static const int size_swizzles
[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
426 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
427 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
428 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
431 assert((size
>= 1) && (size
<= 4));
432 return size_swizzles
[size
- 1];
436 glsl_to_tgsi_instruction
*
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
438 st_dst_reg dst
, st_dst_reg dst1
,
439 st_src_reg src0
, st_src_reg src1
,
440 st_src_reg src2
, st_src_reg src3
)
442 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
443 int num_reladdr
= 0, i
, j
;
444 bool dst_is_64bit
[2];
446 op
= get_opcode(op
, dst
, src0
, src1
);
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
452 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
453 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
454 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
455 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
456 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
457 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
459 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
460 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
461 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
462 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
464 if (dst
.reladdr
|| dst
.reladdr2
) {
466 emit_arl(ir
, address_reg
, *dst
.reladdr
);
468 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
472 assert(num_reladdr
== 0);
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
478 inst
->precise
= this->precise
;
479 inst
->info
= tgsi_get_opcode_info(op
);
486 inst
->is_64bit_expanded
= false;
489 inst
->tex_offsets
= NULL
;
490 inst
->tex_offset_num_offset
= 0;
492 inst
->tex_shadow
= 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
496 inst
->tex_type
= GLSL_TYPE_FLOAT
;
498 /* Update indirect addressing status used by TGSI */
499 if (dst
.reladdr
|| dst
.reladdr2
) {
501 case PROGRAM_STATE_VAR
:
502 case PROGRAM_CONSTANT
:
503 case PROGRAM_UNIFORM
:
504 this->indirect_addr_consts
= true;
506 case PROGRAM_IMMEDIATE
:
507 assert(!"immediates should not have indirect addressing");
514 for (i
= 0; i
< 4; i
++) {
515 if (inst
->src
[i
].reladdr
) {
516 switch (inst
->src
[i
].file
) {
517 case PROGRAM_STATE_VAR
:
518 case PROGRAM_CONSTANT
:
519 case PROGRAM_UNIFORM
:
520 this->indirect_addr_consts
= true;
522 case PROGRAM_IMMEDIATE
:
523 assert(!"immediates should not have indirect addressing");
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
550 for (j
= 0; j
< 2; j
++) {
551 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
552 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
553 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
554 enum glsl_base_type type
= find_array_type(this->outputs
,
556 inst
->dst
[j
].array_id
);
557 if (glsl_base_type_is_64bit(type
))
558 dst_is_64bit
[j
] = true;
562 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
563 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
564 glsl_to_tgsi_instruction
*dinst
= NULL
;
565 int initial_src_swz
[4], initial_src_idx
[4];
566 int initial_dst_idx
[2], initial_dst_writemask
[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
569 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j
= 0; j
< 2; j
++) {
573 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
574 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
577 for (j
= 0; j
< 4; j
++) {
578 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
579 initial_src_idx
[j
] = inst
->src
[j
].index
;
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
589 int i
= u_bit_scan(&writemask
);
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
594 inst
->op
== TGSI_OPCODE_STORE
) &&
595 addr
.file
== PROGRAM_UNDEFINED
) {
596 /* We have to advance the buffer address by 16 */
597 addr
= get_temp(glsl_type::uint_type
);
598 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
599 inst
->src
[0], st_src_reg_for_int(16));
602 /* first time use previous instruction */
606 /* create a new instructions for subsequent attempts */
607 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
612 this->instructions
.push_tail(dinst
);
613 dinst
->is_64bit_expanded
= true;
615 /* modify the destination if we are splitting */
616 for (j
= 0; j
< 2; j
++) {
617 if (dst_is_64bit
[j
]) {
618 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
619 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
621 if (dinst
->op
== TGSI_OPCODE_LOAD
||
622 dinst
->op
== TGSI_OPCODE_STORE
)
623 dinst
->src
[0] = addr
;
624 if (dinst
->op
!= TGSI_OPCODE_STORE
)
625 dinst
->dst
[j
].index
++;
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
631 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
635 /* modify the src registers */
636 for (j
= 0; j
< 4; j
++) {
637 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
639 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
640 dinst
->src
[j
].index
= initial_src_idx
[j
];
642 dinst
->src
[j
].double_reg2
= true;
643 dinst
->src
[j
].index
++;
647 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
648 SWIZZLE_Z
, SWIZZLE_W
);
650 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
651 SWIZZLE_X
, SWIZZLE_Y
);
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
658 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
659 op
== TGSI_OPCODE_I2D
||
660 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
661 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
662 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
663 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
670 this->instructions
.push_tail(inst
);
677 glsl_to_tgsi_instruction
*
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
680 st_src_reg src0
, st_src_reg src1
,
681 st_src_reg src2
, st_src_reg src3
)
683 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
693 st_src_reg src0
, st_src_reg src1
)
695 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
697 if (op
== TGSI_OPCODE_MOV
)
700 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
701 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
702 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
703 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
705 if (is_resource_instruction(op
))
707 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
708 type
= GLSL_TYPE_INT64
;
709 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
710 type
= GLSL_TYPE_UINT64
;
711 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
712 type
= GLSL_TYPE_DOUBLE
;
713 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
714 type
= GLSL_TYPE_FLOAT
;
715 else if (native_integers
)
716 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
731 op = TGSI_OPCODE_##f; \
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
749 op = TGSI_OPCODE_##c; \
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
758 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
759 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
760 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
761 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
762 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
763 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
764 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
765 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
766 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
767 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
768 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
769 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
770 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
771 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
772 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
773 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
775 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
776 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
777 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
778 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
779 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
780 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
781 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
782 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
784 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
785 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
786 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
787 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
793 assert(op
!= TGSI_OPCODE_LAST
);
797 glsl_to_tgsi_instruction
*
798 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
799 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
802 static const enum tgsi_opcode dot_opcodes
[] = {
803 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
806 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
810 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
813 * channel determines the result across all channels. So to do a vec4
814 * of this operation, we want to emit a scalar per source channel used
815 * to produce dest channels.
818 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
820 st_src_reg orig_src0
, st_src_reg orig_src1
)
823 int done_mask
= ~dst
.writemask
;
825 /* TGSI RCP is a scalar operation splatting results to all channels,
826 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
829 for (i
= 0; i
< 4; i
++) {
830 GLuint this_mask
= (1 << i
);
831 st_src_reg src0
= orig_src0
;
832 st_src_reg src1
= orig_src1
;
834 if (done_mask
& this_mask
)
837 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
838 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
839 for (j
= i
+ 1; j
< 4; j
++) {
840 /* If there is another enabled component in the destination that is
841 * derived from the same inputs, generate its value on this pass as
844 if (!(done_mask
& (1 << j
)) &&
845 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
846 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
847 this_mask
|= (1 << j
);
850 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
851 src0_swiz
, src0_swiz
);
852 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
853 src1_swiz
, src1_swiz
);
855 dst
.writemask
= this_mask
;
856 emit_asm(ir
, op
, dst
, src0
, src1
);
857 done_mask
|= this_mask
;
862 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
863 st_dst_reg dst
, st_src_reg src0
)
865 st_src_reg undef
= undef_src
;
867 undef
.swizzle
= SWIZZLE_XXXX
;
869 emit_scalar(ir
, op
, dst
, src0
, undef
);
873 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
874 st_dst_reg dst
, st_src_reg src0
)
876 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
878 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
879 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
882 op
= TGSI_OPCODE_UARL
;
885 assert(dst
.file
== PROGRAM_ADDRESS
);
886 if (dst
.index
>= this->num_address_regs
)
887 this->num_address_regs
= dst
.index
+ 1;
889 emit_asm(NULL
, op
, dst
, src0
);
893 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
894 gl_constant_value values
[8], int size
,
896 uint16_t *swizzle_out
)
898 if (file
== PROGRAM_CONSTANT
) {
899 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
900 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
901 values
, size
, datatype
,
904 *swizzle_out
= swizzle
;
908 assert(file
== PROGRAM_IMMEDIATE
);
911 immediate_storage
*entry
;
912 int size32
= size
* ((datatype
== GL_DOUBLE
||
913 datatype
== GL_INT64_ARB
||
914 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
917 /* Search immediate storage to see if we already have an identical
918 * immediate that we can use instead of adding a duplicate entry.
920 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
921 immediate_storage
*tmp
= entry
;
923 for (i
= 0; i
* 4 < size32
; i
++) {
924 int slot_size
= MIN2(size32
- (i
* 4), 4);
925 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
927 if (memcmp(tmp
->values
, &values
[i
* 4],
928 slot_size
* sizeof(gl_constant_value
)))
931 /* Everything matches, keep going until the full size is matched */
932 tmp
= (immediate_storage
*)tmp
->next
;
935 /* The full value matched */
942 for (i
= 0; i
* 4 < size32
; i
++) {
943 int slot_size
= MIN2(size32
- (i
* 4), 4);
944 /* Add this immediate to the list. */
945 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
946 slot_size
, datatype
);
947 this->immediates
.push_tail(entry
);
948 this->num_immediates
++;
954 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
956 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
957 union gl_constant_value uval
;
960 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
966 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
968 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
969 union gl_constant_value uval
[2];
971 memcpy(uval
, &val
, sizeof(uval
));
972 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
973 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
978 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
980 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
981 union gl_constant_value uval
;
983 assert(native_integers
);
986 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
992 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
994 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
995 union gl_constant_value uval
[2];
997 memcpy(uval
, &val
, sizeof(uval
));
998 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
999 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1005 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1007 if (native_integers
)
1008 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1009 st_src_reg_for_int(val
);
1011 return st_src_reg_for_float(val
);
1015 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1017 return type
->count_attribute_slots(is_vs_input
);
1021 type_size(const struct glsl_type
*type
)
1023 return type
->count_attribute_slots(false);
1027 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
1028 exec_list
*instructions
, ir_constant
*access
)
1031 * emit_asm() might have actually split the op into pieces, e.g. for
1032 * double stores. We have to go back and fix up all the generated ops.
1034 enum tgsi_opcode op
= inst
->op
;
1036 inst
->resource
= *buf
;
1038 inst
->buffer_access
= access
->value
.u
[0];
1040 if (inst
== instructions
->get_head_raw())
1042 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1044 if (inst
->op
== TGSI_OPCODE_UADD
) {
1045 if (inst
== instructions
->get_head_raw())
1047 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1049 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1053 * If the given GLSL type is an array or matrix or a structure containing
1054 * an array/matrix member, return true. Else return false.
1056 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1057 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1058 * we have an array that might be indexed with a variable, we need to use
1059 * the later storage type.
1062 type_has_array_or_matrix(const glsl_type
*type
)
1064 if (type
->is_array() || type
->is_matrix())
1067 if (type
->is_record()) {
1068 for (unsigned i
= 0; i
< type
->length
; i
++) {
1069 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1080 * In the initial pass of codegen, we assign temporary numbers to
1081 * intermediate results. (not SSA -- variable assignments will reuse
1085 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1089 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1094 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1095 if (next_array
>= max_num_arrays
) {
1096 max_num_arrays
+= 32;
1097 array_sizes
= (unsigned*)
1098 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1101 src
.file
= PROGRAM_ARRAY
;
1103 src
.array_id
= next_array
+ 1;
1104 array_sizes
[next_array
] = type_size(type
);
1108 src
.file
= PROGRAM_TEMPORARY
;
1109 src
.index
= next_temp
;
1110 next_temp
+= type_size(type
);
1113 if (type
->is_array() || type
->is_record()) {
1114 src
.swizzle
= SWIZZLE_NOOP
;
1116 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1123 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1125 struct hash_entry
*entry
;
1127 entry
= _mesa_hash_table_search(this->variables
, var
);
1131 return (variable_storage
*)entry
->data
;
1135 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1137 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1138 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1139 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1142 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1144 const ir_state_slot
*const slots
= ir
->get_state_slots();
1145 assert(slots
!= NULL
);
1147 /* Check if this statevar's setup in the STATE file exactly
1148 * matches how we'll want to reference it as a
1149 * struct/array/whatever. If not, then we need to move it into
1150 * temporary storage and hope that it'll get copy-propagated
1153 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1154 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1159 variable_storage
*storage
;
1161 if (i
== ir
->get_num_state_slots()) {
1162 /* We'll set the index later. */
1163 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1165 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1169 /* The variable_storage constructor allocates slots based on the size
1170 * of the type. However, this had better match the number of state
1171 * elements that we're going to copy into the new temporary.
1173 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1175 dst
= st_dst_reg(get_temp(ir
->type
));
1177 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1180 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1184 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1185 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1188 if (storage
->file
== PROGRAM_STATE_VAR
) {
1189 if (storage
->index
== -1) {
1190 storage
->index
= index
;
1192 assert(index
== storage
->index
+ (int)i
);
1195 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1196 * the data being moved since MOV does not care about the type of
1197 * data it is moving, and we don't want to declare registers with
1198 * array or struct types.
1200 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1201 src
.swizzle
= slots
[i
].swizzle
;
1202 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1203 /* even a float takes up a whole vec4 reg in a struct/array. */
1208 if (storage
->file
== PROGRAM_TEMPORARY
&&
1209 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1210 fail_link(this->shader_program
,
1211 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1212 ir
->name
, dst
.index
- storage
->index
,
1213 type_size(ir
->type
));
1219 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1221 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1223 visit_exec_list(&ir
->body_instructions
, this);
1225 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1229 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1232 case ir_loop_jump::jump_break
:
1233 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1235 case ir_loop_jump::jump_continue
:
1236 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1243 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1250 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1252 /* Ignore function bodies other than main() -- we shouldn't see calls to
1253 * them since they should all be inlined before we get to glsl_to_tgsi.
1255 if (strcmp(ir
->name
, "main") == 0) {
1256 const ir_function_signature
*sig
;
1259 sig
= ir
->matching_signature(NULL
, &empty
, false);
1263 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1270 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1272 int nonmul_operand
= 1 - mul_operand
;
1274 st_dst_reg result_dst
;
1276 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1277 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1280 expr
->operands
[0]->accept(this);
1282 expr
->operands
[1]->accept(this);
1284 ir
->operands
[nonmul_operand
]->accept(this);
1287 this->result
= get_temp(ir
->type
);
1288 result_dst
= st_dst_reg(this->result
);
1289 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1290 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1305 * - (a * 1) - (a * b)
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1316 const int other_operand
= 1 - try_operand
;
1319 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1320 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1323 ir
->operands
[other_operand
]->accept(this);
1325 expr
->operands
[0]->accept(this);
1328 b
.negate
= ~b
.negate
;
1330 this->result
= get_temp(ir
->type
);
1331 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1338 st_src_reg
*reg
, int *num_reladdr
)
1340 if (!reg
->reladdr
&& !reg
->reladdr2
)
1344 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1346 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1348 if (*num_reladdr
!= 1) {
1349 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1351 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1359 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1361 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1365 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1366 if (try_emit_mad(ir
, 1))
1368 if (try_emit_mad(ir
, 0))
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1374 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1375 if (try_emit_mad_for_and_not(ir
, 1))
1377 if (try_emit_mad_for_and_not(ir
, 0))
1381 if (ir
->operation
== ir_quadop_vector
)
1382 assert(!"ir_quadop_vector should have been lowered");
1384 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1385 this->result
.file
= PROGRAM_UNDEFINED
;
1386 ir
->operands
[operand
]->accept(this);
1387 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir
->operands
[operand
]->print();
1393 op
[operand
] = this->result
;
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1398 assert(!ir
->operands
[operand
]->type
->is_matrix());
1401 visit_expression(ir
, op
);
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1411 st_src_reg result_src
;
1412 st_dst_reg result_dst
;
1414 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1415 if (ir
->operands
[1] &&
1416 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1417 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1418 st_src_reg
*swz_op
= NULL
;
1419 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1420 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1422 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1423 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1427 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1428 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1429 swizzle_x
, swizzle_x
);
1431 vector_elements
= MAX2(vector_elements
,
1432 ir
->operands
[1]->type
->vector_elements
);
1434 if (ir
->operands
[2] &&
1435 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1438 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1439 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1440 swizzle_x
, swizzle_x
);
1443 this->result
.file
= PROGRAM_UNDEFINED
;
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1448 result_src
= get_temp(ir
->type
);
1449 /* convenience for the emit functions below. */
1450 result_dst
= st_dst_reg(result_src
);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1455 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1457 switch (ir
->operation
) {
1458 case ir_unop_logic_not
:
1459 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1460 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1467 op
[0].negate
= ~op
[0].negate
;
1468 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1469 st_src_reg_for_float(1.0));
1473 if (result_dst
.type
== GLSL_TYPE_INT64
||
1474 result_dst
.type
== GLSL_TYPE_UINT64
)
1475 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1476 else if (result_dst
.type
== GLSL_TYPE_INT
||
1477 result_dst
.type
== GLSL_TYPE_UINT
)
1478 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1479 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1480 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1482 op
[0].negate
= ~op
[0].negate
;
1486 case ir_unop_subroutine_to_int
:
1487 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1490 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1491 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1492 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1493 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1494 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1495 result_dst
.type
== GLSL_TYPE_UINT64
)
1496 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1498 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1501 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1504 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1508 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1511 assert(!"not reached: should be handled by exp_to_exp2");
1514 assert(!"not reached: should be handled by log_to_log2");
1517 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1520 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1523 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1525 case ir_unop_saturate
: {
1526 glsl_to_tgsi_instruction
*inst
;
1527 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1528 inst
->saturate
= true;
1533 case ir_unop_dFdx_coarse
:
1534 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1536 case ir_unop_dFdx_fine
:
1537 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1540 case ir_unop_dFdy_coarse
:
1541 case ir_unop_dFdy_fine
:
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1547 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1548 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1550 unsigned transform_y_index
=
1551 _mesa_add_state_reference(this->prog
->Parameters
,
1554 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1556 glsl_type::vec4_type
);
1557 transform_y
.swizzle
= SWIZZLE_XXXX
;
1559 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1561 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1562 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1563 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1567 case ir_unop_frexp_sig
:
1568 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1571 case ir_unop_frexp_exp
:
1572 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1575 case ir_unop_noise
: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1582 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1587 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1590 op
[1].negate
= ~op
[1].negate
;
1591 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1595 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1598 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1601 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1604 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1608 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1610 case ir_binop_gequal
:
1611 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1613 case ir_binop_equal
:
1614 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1616 case ir_binop_nequal
:
1617 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1619 case ir_binop_all_equal
:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir
->operands
[0]->type
->is_vector() ||
1622 ir
->operands
[1]->type
->is_vector()) {
1623 st_src_reg temp
= get_temp(native_integers
?
1624 glsl_type::uvec4_type
:
1625 glsl_type::vec4_type
);
1627 if (native_integers
) {
1628 st_dst_reg temp_dst
= st_dst_reg(temp
);
1629 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1631 if (ir
->operands
[0]->type
->is_boolean() &&
1632 ir
->operands
[1]->as_constant() &&
1633 ir
->operands
[1]->as_constant()->is_one()) {
1634 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1636 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir
->operands
[0]->type
->vector_elements
) {
1644 temp_dst
.writemask
= WRITEMASK_Y
;
1645 temp1
.swizzle
= SWIZZLE_YYYY
;
1646 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1647 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1650 temp_dst
.writemask
= WRITEMASK_X
;
1651 temp1
.swizzle
= SWIZZLE_XXXX
;
1652 temp2
.swizzle
= SWIZZLE_YYYY
;
1653 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1654 temp_dst
.writemask
= WRITEMASK_Y
;
1655 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1656 temp2
.swizzle
= SWIZZLE_WWWW
;
1657 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1660 temp1
.swizzle
= SWIZZLE_XXXX
;
1661 temp2
.swizzle
= SWIZZLE_YYYY
;
1662 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1664 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1669 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1675 st_src_reg sge_src
= result_src
;
1676 sge_src
.negate
= ~sge_src
.negate
;
1677 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1678 st_src_reg_for_float(0.0));
1681 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1684 case ir_binop_any_nequal
:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir
->operands
[0]->type
->is_vector() ||
1687 ir
->operands
[1]->type
->is_vector()) {
1688 st_src_reg temp
= get_temp(native_integers
?
1689 glsl_type::uvec4_type
:
1690 glsl_type::vec4_type
);
1691 if (ir
->operands
[0]->type
->is_boolean() &&
1692 ir
->operands
[1]->as_constant() &&
1693 ir
->operands
[1]->as_constant()->is_zero()) {
1694 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1696 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1699 if (native_integers
) {
1700 st_dst_reg temp_dst
= st_dst_reg(temp
);
1701 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir
->operands
[0]->type
->vector_elements
) {
1708 temp_dst
.writemask
= WRITEMASK_Y
;
1709 temp1
.swizzle
= SWIZZLE_YYYY
;
1710 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1711 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1714 temp_dst
.writemask
= WRITEMASK_X
;
1715 temp1
.swizzle
= SWIZZLE_XXXX
;
1716 temp2
.swizzle
= SWIZZLE_YYYY
;
1717 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1718 temp_dst
.writemask
= WRITEMASK_Y
;
1719 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1720 temp2
.swizzle
= SWIZZLE_WWWW
;
1721 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1724 temp1
.swizzle
= SWIZZLE_XXXX
;
1725 temp2
.swizzle
= SWIZZLE_YYYY
;
1726 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1731 glsl_to_tgsi_instruction
*const dp
=
1732 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1733 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1737 dp
->saturate
= true;
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1743 st_src_reg slt_src
= result_src
;
1744 slt_src
.negate
= ~slt_src
.negate
;
1745 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1746 st_src_reg_for_float(0.0));
1750 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1754 case ir_binop_logic_xor
:
1755 if (native_integers
)
1756 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1758 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_logic_or
: {
1762 if (native_integers
) {
1763 /* If integers are used as booleans, we can use an actual "or"
1766 assert(native_integers
);
1767 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1772 glsl_to_tgsi_instruction
*add
=
1773 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1774 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1779 add
->saturate
= true;
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1785 st_src_reg slt_src
= result_src
;
1786 slt_src
.negate
= ~slt_src
.negate
;
1787 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1788 st_src_reg_for_float(0.0));
1794 case ir_binop_logic_and
:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1799 if (native_integers
)
1800 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1802 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1806 assert(ir
->operands
[0]->type
->is_vector());
1807 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1808 emit_dp(ir
, result_dst
, op
[0], op
[1],
1809 ir
->operands
[0]->type
->vector_elements
);
1814 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1822 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1823 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1827 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1830 if (native_integers
) {
1831 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1834 /* fallthrough to next case otherwise */
1836 if (native_integers
) {
1837 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1838 st_src_reg_for_float(1.0));
1841 /* fallthrough to next case otherwise */
1844 case ir_unop_i642u64
:
1845 case ir_unop_u642i64
:
1846 /* Converting between signed and unsigned integers is a no-op. */
1848 result_src
.type
= result_dst
.type
;
1851 if (native_integers
) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1856 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1857 st_src_reg_for_int(1));
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1866 if (native_integers
)
1867 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1869 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1872 if (native_integers
)
1873 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1875 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1877 case ir_unop_bitcast_f2i
:
1878 case ir_unop_bitcast_f2u
:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op
[0].negate
|| op
[0].abs
)
1881 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1884 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1887 case ir_unop_bitcast_i2f
:
1888 case ir_unop_bitcast_u2f
:
1890 result_src
.type
= GLSL_TYPE_FLOAT
;
1893 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1894 st_src_reg_for_float(0.0));
1897 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1898 st_src_reg_for_double(0.0));
1901 if (native_integers
)
1902 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1903 st_src_reg_for_int(0));
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1906 st_src_reg_for_float(0.0));
1908 case ir_unop_bitcast_u642d
:
1909 case ir_unop_bitcast_i642d
:
1911 result_src
.type
= GLSL_TYPE_DOUBLE
;
1913 case ir_unop_bitcast_d2i64
:
1915 result_src
.type
= GLSL_TYPE_INT64
;
1917 case ir_unop_bitcast_d2u64
:
1919 result_src
.type
= GLSL_TYPE_UINT64
;
1922 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1925 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1928 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1930 case ir_unop_round_even
:
1931 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1934 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1938 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1941 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1944 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1947 case ir_unop_bit_not
:
1948 if (native_integers
) {
1949 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1953 if (native_integers
) {
1954 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1957 case ir_binop_lshift
:
1958 case ir_binop_rshift
:
1959 if (native_integers
) {
1960 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1961 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1964 if (glsl_base_type_is_64bit(op
[0].type
)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1968 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1969 ->type
->components()));
1970 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1975 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1978 case ir_binop_bit_and
:
1979 if (native_integers
) {
1980 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1983 case ir_binop_bit_xor
:
1984 if (native_integers
) {
1985 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1988 case ir_binop_bit_or
:
1989 if (native_integers
) {
1990 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1994 assert(!"GLSL 1.30 features unsupported");
1997 case ir_binop_ubo_load
: {
1998 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1999 ir_rvalue
*block
= ir
->operands
[0];
2000 ir_rvalue
*offset
= ir
->operands
[1];
2001 ir_constant
*const_block
= block
->as_constant();
2003 st_src_reg
cbuf(PROGRAM_CONSTANT
,
2004 (const_block
? const_block
->value
.u
[0] + 1 : 1),
2005 ir
->type
->base_type
);
2007 cbuf
.has_index2
= true;
2010 block
->accept(this);
2011 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2012 *cbuf
.reladdr
= this->result
;
2013 emit_arl(ir
, sampler_reladdr
, this->result
);
2016 /* Calculate the surface offset */
2017 offset
->accept(this);
2018 st_src_reg off
= this->result
;
2020 glsl_to_tgsi_instruction
*inst
=
2021 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
2023 if (result_dst
.type
== GLSL_TYPE_BOOL
)
2024 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
2025 st_src_reg_for_int(0));
2027 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
2030 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2031 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2032 unsigned const_offset
= const_offset_ir
?
2033 const_offset_ir
->value
.u
[0] : 0;
2034 unsigned const_block
= const_uniform_block
?
2035 const_uniform_block
->value
.u
[0] + 1 : 1;
2036 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2039 cbuf
.type
= ir
->type
->base_type
;
2040 cbuf
.file
= PROGRAM_CONSTANT
;
2042 cbuf
.reladdr
= NULL
;
2045 cbuf
.index2D
= const_block
;
2047 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2049 if (const_offset_ir
) {
2050 /* Constant index into constant buffer */
2051 cbuf
.reladdr
= NULL
;
2052 cbuf
.index
= const_offset
/ 16;
2054 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2055 st_src_reg offset
= op
[1];
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2072 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2073 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2074 if (const_offset_ir
) {
2075 const_offset
= const_offset_ir
->value
.u
[0];
2076 cbuf
.index
= const_offset
/ 16;
2077 offset_expr
->operands
[0]->accept(this);
2078 offset
= this->result
;
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2084 st_src_reg_for_int(4));
2085 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2086 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2089 if (const_uniform_block
) {
2090 /* Constant constant buffer */
2091 cbuf
.reladdr2
= NULL
;
2093 /* Relative/variable constant buffer */
2094 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2095 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2097 cbuf
.has_index2
= true;
2099 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2100 if (glsl_base_type_is_64bit(cbuf
.type
))
2101 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2102 const_offset
% 16 / 8,
2103 const_offset
% 16 / 8,
2104 const_offset
% 16 / 8);
2106 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2107 const_offset
% 16 / 4,
2108 const_offset
% 16 / 4,
2109 const_offset
% 16 / 4);
2111 if (ir
->type
->is_boolean()) {
2112 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2113 st_src_reg_for_int(0));
2115 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2125 if (this->ctx
->Const
.NativeIntegers
)
2126 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2128 op
[0].negate
= ~op
[0].negate
;
2129 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2132 case ir_triop_bitfield_extract
:
2133 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2135 case ir_quadop_bitfield_insert
:
2136 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2138 case ir_unop_bitfield_reverse
:
2139 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2141 case ir_unop_bit_count
:
2142 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2144 case ir_unop_find_msb
:
2145 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2147 case ir_unop_find_lsb
:
2148 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2150 case ir_binop_imul_high
:
2151 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2154 /* In theory, MAD is incorrect here. */
2156 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2158 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2160 case ir_unop_interpolate_at_centroid
:
2161 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2163 case ir_binop_interpolate_at_offset
: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2166 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2168 unsigned transform_y_index
=
2169 _mesa_add_state_reference(this->prog
->Parameters
,
2172 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2174 glsl_type::vec4_type
);
2175 transform_y
.swizzle
= SWIZZLE_XXXX
;
2177 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2178 st_dst_reg temp_dst
= st_dst_reg(temp
);
2180 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2181 temp_dst
.writemask
= WRITEMASK_Y
;
2182 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2183 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2186 case ir_binop_interpolate_at_sample
:
2187 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2191 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2194 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2197 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2200 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2203 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2206 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2208 case ir_unop_unpack_double_2x32
:
2209 case ir_unop_pack_double_2x32
:
2210 case ir_unop_unpack_int_2x32
:
2211 case ir_unop_pack_int_2x32
:
2212 case ir_unop_unpack_uint_2x32
:
2213 case ir_unop_pack_uint_2x32
:
2214 case ir_unop_unpack_sampler_2x32
:
2215 case ir_unop_pack_sampler_2x32
:
2216 case ir_unop_unpack_image_2x32
:
2217 case ir_unop_pack_image_2x32
:
2218 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2221 case ir_binop_ldexp
:
2222 if (ir
->operands
[0]->type
->is_double()) {
2223 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2224 } else if (ir
->operands
[0]->type
->is_float()) {
2225 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2231 case ir_unop_pack_half_2x16
:
2232 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2234 case ir_unop_unpack_half_2x16
:
2235 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2238 case ir_unop_get_buffer_size
: {
2239 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2240 int buf_base
= ctx
->st
->has_hw_atomics
2241 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
2244 buf_base
+ (const_offset
? const_offset
->value
.u
[0] : 0),
2246 if (!const_offset
) {
2247 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2248 *buffer
.reladdr
= op
[0];
2249 emit_arl(ir
, sampler_reladdr
, op
[0]);
2251 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2257 case ir_unop_b2i64
: {
2258 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2259 st_dst_reg temp_dst
= st_dst_reg(temp
);
2260 unsigned orig_swz
= op
[0].swizzle
;
2262 * To convert unsigned to 64-bit:
2263 * zero Y channel, copy X channel.
2265 temp_dst
.writemask
= WRITEMASK_Y
;
2266 if (vector_elements
> 1)
2267 temp_dst
.writemask
|= WRITEMASK_W
;
2268 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2269 temp_dst
.writemask
= WRITEMASK_X
;
2270 if (vector_elements
> 1)
2271 temp_dst
.writemask
|= WRITEMASK_Z
;
2272 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2273 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2274 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2275 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2277 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2279 result_src
.type
= GLSL_TYPE_UINT64
;
2280 if (vector_elements
> 2) {
2281 /* Subtle: We rely on the fact that get_temp here returns the next
2282 * TGSI temporary register directly after the temp register used for
2283 * the first two components, so that the result gets picked up
2286 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2287 st_dst_reg temp_dst
= st_dst_reg(temp
);
2288 temp_dst
.writemask
= WRITEMASK_Y
;
2289 if (vector_elements
> 3)
2290 temp_dst
.writemask
|= WRITEMASK_W
;
2291 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2293 temp_dst
.writemask
= WRITEMASK_X
;
2294 if (vector_elements
> 3)
2295 temp_dst
.writemask
|= WRITEMASK_Z
;
2296 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2297 GET_SWZ(orig_swz
, 2),
2298 GET_SWZ(orig_swz
, 3),
2299 GET_SWZ(orig_swz
, 3));
2300 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2301 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2303 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2304 st_src_reg_for_int(1));
2311 case ir_unop_i642u
: {
2312 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2313 st_dst_reg temp_dst
= st_dst_reg(temp
);
2314 unsigned orig_swz
= op
[0].swizzle
;
2315 unsigned orig_idx
= op
[0].index
;
2317 temp_dst
.writemask
= WRITEMASK_X
;
2319 for (el
= 0; el
< vector_elements
; el
++) {
2320 unsigned swz
= GET_SWZ(orig_swz
, el
);
2322 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2323 SWIZZLE_Z
, SWIZZLE_Z
);
2325 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2326 SWIZZLE_X
, SWIZZLE_X
);
2328 op
[0].index
= orig_idx
+ 1;
2329 op
[0].type
= GLSL_TYPE_UINT
;
2330 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2331 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2334 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2335 result_src
.type
= GLSL_TYPE_UINT
;
2337 result_src
.type
= GLSL_TYPE_INT
;
2341 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2342 st_src_reg_for_int64(0));
2345 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2348 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2351 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2354 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2357 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2360 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2363 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2366 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2369 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2372 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2374 /* these might be needed */
2375 case ir_unop_pack_snorm_2x16
:
2376 case ir_unop_pack_unorm_2x16
:
2377 case ir_unop_pack_snorm_4x8
:
2378 case ir_unop_pack_unorm_4x8
:
2380 case ir_unop_unpack_snorm_2x16
:
2381 case ir_unop_unpack_unorm_2x16
:
2382 case ir_unop_unpack_snorm_4x8
:
2383 case ir_unop_unpack_unorm_4x8
:
2385 case ir_quadop_vector
:
2386 case ir_binop_vector_extract
:
2387 case ir_triop_vector_insert
:
2388 case ir_binop_carry
:
2389 case ir_binop_borrow
:
2390 case ir_unop_ssbo_unsized_array_length
:
2391 /* This operation is not supported, or should have already been handled.
2393 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2397 this->result
= result_src
;
2402 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2408 /* Note that this is only swizzles in expressions, not those on the left
2409 * hand side of an assignment, which do write masking. See ir_assignment
2413 ir
->val
->accept(this);
2415 assert(src
.file
!= PROGRAM_UNDEFINED
);
2416 assert(ir
->type
->vector_elements
> 0);
2418 for (i
= 0; i
< 4; i
++) {
2419 if (i
< ir
->type
->vector_elements
) {
2422 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2425 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2428 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2431 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2435 /* If the type is smaller than a vec4, replicate the last
2438 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2442 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2447 /* Test if the variable is an array. Note that geometry and
2448 * tessellation shader inputs are outputs are always arrays (except
2449 * for patch inputs), so only the array element type is considered.
2452 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2454 const glsl_type
*type
= var
->type
;
2456 *remove_array
= false;
2458 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2459 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2462 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2463 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2464 stage
== MESA_SHADER_TESS_CTRL
) &&
2466 if (!var
->type
->is_array())
2467 return false; /* a system value probably */
2469 type
= var
->type
->fields
.array
;
2470 *remove_array
= true;
2473 return type
->is_array() || type
->is_matrix();
2477 st_translate_interp_loc(ir_variable
*var
)
2479 if (var
->data
.centroid
)
2480 return TGSI_INTERPOLATE_LOC_CENTROID
;
2481 else if (var
->data
.sample
)
2482 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2484 return TGSI_INTERPOLATE_LOC_CENTER
;
2488 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2490 variable_storage
*entry
;
2491 ir_variable
*var
= ir
->var
;
2494 if (handle_bound_deref(ir
->as_dereference()))
2497 entry
= find_variable_storage(ir
->var
);
2500 switch (var
->data
.mode
) {
2501 case ir_var_uniform
:
2502 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2503 var
->data
.param_index
);
2504 _mesa_hash_table_insert(this->variables
, var
, entry
);
2506 case ir_var_shader_in
: {
2507 /* The linker assigns locations for varyings and attributes,
2508 * including deprecated builtins (like gl_Color), user-assign
2509 * generic attributes (glBindVertexLocation), and
2510 * user-defined varyings.
2512 assert(var
->data
.location
!= -1);
2514 const glsl_type
*type_without_array
= var
->type
->without_array();
2515 struct inout_decl
*decl
= &inputs
[num_inputs
];
2516 unsigned component
= var
->data
.location_frac
;
2517 unsigned num_components
;
2520 if (type_without_array
->is_64bit())
2521 component
= component
/ 2;
2522 if (type_without_array
->vector_elements
)
2523 num_components
= type_without_array
->vector_elements
;
2527 decl
->mesa_index
= var
->data
.location
;
2528 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2529 decl
->interp_loc
= st_translate_interp_loc(var
);
2530 decl
->base_type
= type_without_array
->base_type
;
2531 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2533 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2534 decl
->array_id
= num_input_arrays
+ 1;
2541 decl
->size
= type_size(var
->type
->fields
.array
);
2543 decl
->size
= type_size(var
->type
);
2545 entry
= new(mem_ctx
) variable_storage(var
,
2549 entry
->component
= component
;
2551 _mesa_hash_table_insert(this->variables
, var
, entry
);
2555 case ir_var_shader_out
: {
2556 assert(var
->data
.location
!= -1);
2558 const glsl_type
*type_without_array
= var
->type
->without_array();
2559 struct inout_decl
*decl
= &outputs
[num_outputs
];
2560 unsigned component
= var
->data
.location_frac
;
2561 unsigned num_components
;
2564 decl
->invariant
= var
->data
.invariant
;
2566 if (type_without_array
->is_64bit())
2567 component
= component
/ 2;
2568 if (type_without_array
->vector_elements
)
2569 num_components
= type_without_array
->vector_elements
;
2573 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2574 decl
->base_type
= type_without_array
->base_type
;
2575 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2576 if (var
->data
.stream
& (1u << 31)) {
2577 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2579 assert(var
->data
.stream
< 4);
2580 decl
->gs_out_streams
= 0;
2581 for (unsigned i
= 0; i
< num_components
; ++i
)
2582 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2585 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2586 decl
->array_id
= num_output_arrays
+ 1;
2587 num_output_arrays
++;
2593 decl
->size
= type_size(var
->type
->fields
.array
);
2595 decl
->size
= type_size(var
->type
);
2597 if (var
->data
.fb_fetch_output
) {
2598 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2599 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2600 var
->type
, component
, decl
->array_id
);
2601 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2602 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2605 entry
= new(mem_ctx
) variable_storage(var
,
2610 entry
->component
= component
;
2612 _mesa_hash_table_insert(this->variables
, var
, entry
);
2616 case ir_var_system_value
:
2617 entry
= new(mem_ctx
) variable_storage(var
,
2618 PROGRAM_SYSTEM_VALUE
,
2619 var
->data
.location
);
2622 case ir_var_temporary
:
2623 st_src_reg src
= get_temp(var
->type
);
2625 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2627 _mesa_hash_table_insert(this->variables
, var
, entry
);
2633 printf("Failed to make storage for %s\n", var
->name
);
2638 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2639 entry
->component
, entry
->array_id
);
2640 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2641 var
->data
.mode
== ir_var_shader_in
&&
2642 var
->type
->without_array()->is_double())
2643 this->result
.is_double_vertex_input
= true;
2644 if (!native_integers
)
2645 this->result
.type
= GLSL_TYPE_FLOAT
;
2649 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2650 GLbitfield64
* usage_mask
,
2651 GLbitfield64 double_usage_mask
,
2652 GLbitfield
* patch_usage_mask
)
2657 /* Fix array declarations by removing unused array elements at both ends
2658 * of the arrays. For example, mat4[3] where only mat[1] is used.
2660 for (i
= 0; i
< count
; i
++) {
2661 struct inout_decl
*decl
= &decls
[i
];
2662 if (!decl
->array_id
)
2665 /* Shrink the beginning. */
2666 for (j
= 0; j
< (int)decl
->size
; j
++) {
2667 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2668 if (*patch_usage_mask
&
2669 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2673 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2675 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2684 /* Shrink the end. */
2685 for (j
= decl
->size
-1; j
>= 0; j
--) {
2686 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2687 if (*patch_usage_mask
&
2688 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2692 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2694 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2701 /* When not all entries of an array are accessed, we mark them as used
2702 * here anyway, to ensure that the input/output mapping logic doesn't get
2705 * TODO This happens when an array isn't used via indirect access, which
2706 * some game ports do (at least eON-based). There is an optimization
2707 * opportunity here by replacing the array declaration with non-array
2708 * declarations of those slots that are actually used.
2710 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2711 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2712 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2714 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2720 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2725 ir_variable
*var
= ir
->variable_referenced();
2727 if (handle_bound_deref(ir
->as_dereference()))
2730 /* We only need the logic provided by st_glsl_storage_type_size()
2731 * for arrays of structs. Indirect sampler and image indexing is handled
2734 int element_size
= ir
->type
->without_array()->is_record() ?
2735 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2736 type_size(ir
->type
);
2738 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2740 ir
->array
->accept(this);
2743 if (!src
.has_index2
) {
2744 switch (this->prog
->Target
) {
2745 case GL_TESS_CONTROL_PROGRAM_NV
:
2746 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2747 !ir
->variable_referenced()->data
.patch
;
2749 case GL_TESS_EVALUATION_PROGRAM_NV
:
2750 is_2D
= src
.file
== PROGRAM_INPUT
&&
2751 !ir
->variable_referenced()->data
.patch
;
2753 case GL_GEOMETRY_PROGRAM_NV
:
2754 is_2D
= src
.file
== PROGRAM_INPUT
;
2764 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2765 src
.file
== PROGRAM_INPUT
)
2766 element_size
= attrib_type_size(ir
->type
, true);
2768 src
.index2D
= index
->value
.i
[0];
2769 src
.has_index2
= true;
2771 src
.index
+= index
->value
.i
[0] * element_size
;
2773 /* Variable index array dereference. It eats the "vec4" of the
2774 * base of the array and an index that offsets the TGSI register
2777 ir
->array_index
->accept(this);
2779 st_src_reg index_reg
;
2781 if (element_size
== 1) {
2782 index_reg
= this->result
;
2784 index_reg
= get_temp(native_integers
?
2785 glsl_type::int_type
: glsl_type::float_type
);
2787 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2788 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2791 /* If there was already a relative address register involved, add the
2792 * new and the old together to get the new offset.
2794 if (!is_2D
&& src
.reladdr
!= NULL
) {
2795 st_src_reg accum_reg
= get_temp(native_integers
?
2796 glsl_type::int_type
: glsl_type::float_type
);
2798 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2799 index_reg
, *src
.reladdr
);
2801 index_reg
= accum_reg
;
2805 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2806 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2808 src
.has_index2
= true;
2810 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2811 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2815 /* Change the register type to the element type of the array. */
2816 src
.type
= ir
->type
->base_type
;
2822 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2825 const glsl_type
*struct_type
= ir
->record
->type
;
2826 ir_variable
*var
= ir
->record
->variable_referenced();
2829 if (handle_bound_deref(ir
->as_dereference()))
2832 ir
->record
->accept(this);
2834 assert(ir
->field_idx
>= 0);
2836 for (i
= 0; i
< struct_type
->length
; i
++) {
2837 if (i
== (unsigned) ir
->field_idx
)
2839 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2840 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2843 /* If the type is smaller than a vec4, replicate the last channel out. */
2844 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2845 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2847 this->result
.swizzle
= SWIZZLE_NOOP
;
2849 this->result
.index
+= offset
;
2850 this->result
.type
= ir
->type
->base_type
;
2854 * We want to be careful in assignment setup to hit the actual storage
2855 * instead of potentially using a temporary like we might with the
2856 * ir_dereference handler.
2859 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2861 /* The LHS must be a dereference. If the LHS is a variable indexed array
2862 * access of a vector, it must be separated into a series conditional moves
2863 * before reaching this point (see ir_vec_index_to_cond_assign).
2865 assert(ir
->as_dereference());
2866 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2868 assert(!deref_array
->array
->type
->is_vector());
2871 /* Use the rvalue deref handler for the most part. We write swizzles using
2872 * the writemask, but we do extract the base component for enhanced layouts
2873 * from the source swizzle.
2876 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2877 return st_dst_reg(v
->result
);
2881 * Process the condition of a conditional assignment
2883 * Examines the condition of a conditional assignment to generate the optimal
2884 * first operand of a \c CMP instruction. If the condition is a relational
2885 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2886 * used as the source for the \c CMP instruction. Otherwise the comparison
2887 * is processed to a boolean result, and the boolean result is used as the
2888 * operand to the CMP instruction.
2891 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2893 ir_rvalue
*src_ir
= ir
;
2895 bool switch_order
= false;
2897 ir_expression
*const expr
= ir
->as_expression();
2899 if (native_integers
) {
2900 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2901 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2902 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2903 type
== GLSL_TYPE_BOOL
) {
2904 if (expr
->operation
== ir_binop_equal
) {
2905 if (expr
->operands
[0]->is_zero()) {
2906 src_ir
= expr
->operands
[1];
2907 switch_order
= true;
2909 else if (expr
->operands
[1]->is_zero()) {
2910 src_ir
= expr
->operands
[0];
2911 switch_order
= true;
2914 else if (expr
->operation
== ir_binop_nequal
) {
2915 if (expr
->operands
[0]->is_zero()) {
2916 src_ir
= expr
->operands
[1];
2918 else if (expr
->operands
[1]->is_zero()) {
2919 src_ir
= expr
->operands
[0];
2925 src_ir
->accept(this);
2926 return switch_order
;
2929 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2930 bool zero_on_left
= false;
2932 if (expr
->operands
[0]->is_zero()) {
2933 src_ir
= expr
->operands
[1];
2934 zero_on_left
= true;
2935 } else if (expr
->operands
[1]->is_zero()) {
2936 src_ir
= expr
->operands
[0];
2937 zero_on_left
= false;
2941 * (a < 0) T F F ( a < 0) T F F
2942 * (0 < a) F F T (-a < 0) F F T
2943 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2944 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2946 * Note that exchanging the order of 0 and 'a' in the comparison simply
2947 * means that the value of 'a' should be negated.
2950 switch (expr
->operation
) {
2952 switch_order
= false;
2953 negate
= zero_on_left
;
2956 case ir_binop_gequal
:
2957 switch_order
= true;
2958 negate
= zero_on_left
;
2962 /* This isn't the right kind of comparison afterall, so make sure
2963 * the whole condition is visited.
2971 src_ir
->accept(this);
2973 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2974 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2975 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2976 * computing the condition.
2979 this->result
.negate
= ~this->result
.negate
;
2981 return switch_order
;
2985 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2986 st_dst_reg
*l
, st_src_reg
*r
,
2987 st_src_reg
*cond
, bool cond_swap
)
2989 if (type
->is_record()) {
2990 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2991 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2997 if (type
->is_array()) {
2998 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2999 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3004 if (type
->is_matrix()) {
3005 const struct glsl_type
*vec_type
;
3007 vec_type
= glsl_type::get_instance(type
->is_double()
3008 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3009 type
->vector_elements
, 1);
3011 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3012 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3017 assert(type
->is_scalar() || type
->is_vector());
3019 l
->type
= type
->base_type
;
3020 r
->type
= type
->base_type
;
3022 st_src_reg l_src
= st_src_reg(*l
);
3024 if (l_src
.file
== PROGRAM_OUTPUT
&&
3025 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
3026 (l_src
.index
== FRAG_RESULT_DEPTH
||
3027 l_src
.index
== FRAG_RESULT_STENCIL
)) {
3028 /* This is a special case because the source swizzles will be shifted
3029 * later to account for the difference between GLSL (where they're
3030 * plain floats) and TGSI (where they're Z and Y components). */
3031 l_src
.swizzle
= SWIZZLE_XXXX
;
3034 if (native_integers
) {
3035 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3036 cond_swap
? l_src
: *r
,
3037 cond_swap
? *r
: l_src
);
3039 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3040 cond_swap
? l_src
: *r
,
3041 cond_swap
? *r
: l_src
);
3044 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3048 if (type
->is_dual_slot()) {
3050 if (r
->is_double_vertex_input
== false)
3056 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3062 /* all generated instructions need to be flaged as precise */
3063 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3064 ir
->rhs
->accept(this);
3067 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3071 int first_enabled_chan
= 0;
3073 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3075 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3076 variable
->data
.mode
== ir_var_shader_out
&&
3077 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3078 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3079 assert(ir
->lhs
->type
->is_scalar());
3080 assert(ir
->write_mask
== WRITEMASK_X
);
3082 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3083 l
.writemask
= WRITEMASK_Z
;
3085 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3086 l
.writemask
= WRITEMASK_Y
;
3088 } else if (ir
->write_mask
== 0) {
3089 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3091 unsigned num_elements
=
3092 ir
->lhs
->type
->without_array()->vector_elements
;
3095 l
.writemask
= u_bit_consecutive(0, num_elements
);
3097 /* The type is a struct or an array of (array of) structs. */
3098 l
.writemask
= WRITEMASK_XYZW
;
3101 l
.writemask
= ir
->write_mask
;
3104 for (int i
= 0; i
< 4; i
++) {
3105 if (l
.writemask
& (1 << i
)) {
3106 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3111 l
.writemask
= l
.writemask
<< dst_component
;
3113 /* Swizzle a small RHS vector into the channels being written.
3115 * glsl ir treats write_mask as dictating how many channels are
3116 * present on the RHS while TGSI treats write_mask as just
3117 * showing which channels of the vec4 RHS get written.
3119 for (int i
= 0; i
< 4; i
++) {
3120 if (l
.writemask
& (1 << i
))
3121 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3123 swizzles
[i
] = first_enabled_chan
;
3125 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3126 swizzles
[2], swizzles
[3]);
3129 assert(l
.file
!= PROGRAM_UNDEFINED
);
3130 assert(r
.file
!= PROGRAM_UNDEFINED
);
3132 if (ir
->condition
) {
3133 const bool switch_order
= this->process_move_condition(ir
->condition
);
3134 st_src_reg condition
= this->result
;
3136 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3137 } else if (ir
->rhs
->as_expression() &&
3138 this->instructions
.get_tail() &&
3139 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3140 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3141 type_size(ir
->lhs
->type
) == 1 &&
3142 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3143 /* To avoid emitting an extra MOV when assigning an expression to a
3144 * variable, emit the last instruction of the expression again, but
3145 * replace the destination register with the target of the assignment.
3146 * Dead code elimination will remove the original instruction.
3148 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3149 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3150 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3151 new_inst
->saturate
= inst
->saturate
;
3152 new_inst
->resource
= inst
->resource
;
3153 inst
->dead_mask
= inst
->dst
[0].writemask
;
3155 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3162 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3165 GLdouble stack_vals
[4] = { 0 };
3166 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3167 GLenum gl_type
= GL_NONE
;
3168 unsigned int i
, elements
;
3169 static int in_array
= 0;
3170 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3172 /* Unfortunately, 4 floats is all we can get into
3173 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3174 * aggregate constant and move each constant value into it. If we
3175 * get lucky, copy propagation will eliminate the extra moves.
3177 if (ir
->type
->is_record()) {
3178 st_src_reg temp_base
= get_temp(ir
->type
);
3179 st_dst_reg temp
= st_dst_reg(temp_base
);
3181 for (i
= 0; i
< ir
->type
->length
; i
++) {
3182 ir_constant
*const field_value
= ir
->get_record_field(i
);
3183 int size
= type_size(field_value
->type
);
3187 field_value
->accept(this);
3190 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3191 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3197 this->result
= temp_base
;
3201 if (ir
->type
->is_array()) {
3202 st_src_reg temp_base
= get_temp(ir
->type
);
3203 st_dst_reg temp
= st_dst_reg(temp_base
);
3204 int size
= type_size(ir
->type
->fields
.array
);
3209 for (i
= 0; i
< ir
->type
->length
; i
++) {
3210 ir
->const_elements
[i
]->accept(this);
3212 for (int j
= 0; j
< size
; j
++) {
3213 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3219 this->result
= temp_base
;
3224 if (ir
->type
->is_matrix()) {
3225 st_src_reg mat
= get_temp(ir
->type
);
3226 st_dst_reg mat_column
= st_dst_reg(mat
);
3228 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3229 switch (ir
->type
->base_type
) {
3230 case GLSL_TYPE_FLOAT
:
3231 values
= (gl_constant_value
*)
3232 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3234 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3235 src
.index
= add_constant(file
,
3237 ir
->type
->vector_elements
,
3240 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3242 case GLSL_TYPE_DOUBLE
:
3243 values
= (gl_constant_value
*)
3244 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3245 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3246 src
.index
= add_constant(file
,
3248 ir
->type
->vector_elements
,
3251 if (ir
->type
->vector_elements
>= 2) {
3252 mat_column
.writemask
= WRITEMASK_XY
;
3253 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3254 SWIZZLE_X
, SWIZZLE_Y
);
3255 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3257 mat_column
.writemask
= WRITEMASK_X
;
3258 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3259 SWIZZLE_X
, SWIZZLE_X
);
3260 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3263 if (ir
->type
->vector_elements
> 2) {
3264 if (ir
->type
->vector_elements
== 4) {
3265 mat_column
.writemask
= WRITEMASK_ZW
;
3266 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3267 SWIZZLE_X
, SWIZZLE_Y
);
3268 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3270 mat_column
.writemask
= WRITEMASK_Z
;
3271 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3272 SWIZZLE_Y
, SWIZZLE_Y
);
3273 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3274 mat_column
.writemask
= WRITEMASK_XYZW
;
3275 src
.swizzle
= SWIZZLE_XYZW
;
3281 unreachable("Illegal matrix constant type.\n");
3290 elements
= ir
->type
->vector_elements
;
3291 switch (ir
->type
->base_type
) {
3292 case GLSL_TYPE_FLOAT
:
3294 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3295 values
[i
].f
= ir
->value
.f
[i
];
3298 case GLSL_TYPE_DOUBLE
:
3299 gl_type
= GL_DOUBLE
;
3300 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3301 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3304 case GLSL_TYPE_INT64
:
3305 gl_type
= GL_INT64_ARB
;
3306 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3307 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3310 case GLSL_TYPE_UINT64
:
3311 gl_type
= GL_UNSIGNED_INT64_ARB
;
3312 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3313 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3316 case GLSL_TYPE_UINT
:
3317 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3318 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3319 if (native_integers
)
3320 values
[i
].u
= ir
->value
.u
[i
];
3322 values
[i
].f
= ir
->value
.u
[i
];
3326 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3327 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3328 if (native_integers
)
3329 values
[i
].i
= ir
->value
.i
[i
];
3331 values
[i
].f
= ir
->value
.i
[i
];
3334 case GLSL_TYPE_BOOL
:
3335 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3336 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3337 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3340 case GLSL_TYPE_SAMPLER
:
3341 case GLSL_TYPE_IMAGE
:
3342 gl_type
= GL_UNSIGNED_INT
;
3344 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3345 values
[1].u
= ir
->value
.u64
[0] >> 32;
3348 assert(!"Non-float/uint/int/bool/sampler/image constant");
3351 this->result
= st_src_reg(file
, -1, ir
->type
);
3352 this->result
.index
= add_constant(file
,
3356 &this->result
.swizzle
);
3360 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3362 exec_node
*param
= ir
->actual_parameters
.get_head();
3363 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3364 ir_variable
*location
= deref
->variable_referenced();
3365 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3366 /* Calculate the surface offset */
3368 unsigned array_size
= 0, base
= 0;
3370 st_src_reg resource
;
3372 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3374 if (has_hw_atomics
) {
3375 variable_storage
*entry
= find_variable_storage(location
);
3376 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3377 location
->data
.binding
);
3380 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3382 _mesa_hash_table_insert(this->variables
, location
, entry
);
3384 atomic_info
[num_atomics
].location
= location
->data
.location
;
3385 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3386 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3387 if (atomic_info
[num_atomics
].size
== 0)
3388 atomic_info
[num_atomics
].size
= 1;
3389 atomic_info
[num_atomics
].array_id
= 0;
3393 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3394 if (atomic_info
[entry
->index
].array_id
== 0) {
3395 num_atomic_arrays
++;
3396 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3398 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3401 buffer
.index
= index
;
3402 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3403 buffer
.has_index2
= true;
3405 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3406 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3407 *buffer
.reladdr
= offset
;
3408 emit_arl(ir
, sampler_reladdr
, offset
);
3410 offset
= st_src_reg_for_int(0);
3414 st_src_reg
buffer(PROGRAM_BUFFER
, location
->data
.binding
,
3415 GLSL_TYPE_ATOMIC_UINT
);
3417 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3418 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3419 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3420 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3421 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3423 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3428 ir
->return_deref
->accept(this);
3429 st_dst_reg
dst(this->result
);
3430 dst
.writemask
= WRITEMASK_X
;
3432 glsl_to_tgsi_instruction
*inst
;
3434 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3435 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3436 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3437 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3438 st_src_reg_for_int(1));
3439 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3440 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3441 st_src_reg_for_int(-1));
3442 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3444 param
= param
->get_next();
3445 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3448 st_src_reg data
= this->result
, data2
= undef_src
;
3449 enum tgsi_opcode opcode
;
3450 switch (ir
->callee
->intrinsic_id
) {
3451 case ir_intrinsic_atomic_counter_add
:
3452 opcode
= TGSI_OPCODE_ATOMUADD
;
3454 case ir_intrinsic_atomic_counter_min
:
3455 opcode
= TGSI_OPCODE_ATOMIMIN
;
3457 case ir_intrinsic_atomic_counter_max
:
3458 opcode
= TGSI_OPCODE_ATOMIMAX
;
3460 case ir_intrinsic_atomic_counter_and
:
3461 opcode
= TGSI_OPCODE_ATOMAND
;
3463 case ir_intrinsic_atomic_counter_or
:
3464 opcode
= TGSI_OPCODE_ATOMOR
;
3466 case ir_intrinsic_atomic_counter_xor
:
3467 opcode
= TGSI_OPCODE_ATOMXOR
;
3469 case ir_intrinsic_atomic_counter_exchange
:
3470 opcode
= TGSI_OPCODE_ATOMXCHG
;
3472 case ir_intrinsic_atomic_counter_comp_swap
: {
3473 opcode
= TGSI_OPCODE_ATOMCAS
;
3474 param
= param
->get_next();
3475 val
= ((ir_instruction
*)param
)->as_rvalue();
3477 data2
= this->result
;
3481 assert(!"Unexpected intrinsic");
3485 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3488 inst
->resource
= resource
;
3492 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3494 exec_node
*param
= ir
->actual_parameters
.get_head();
3496 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3498 param
= param
->get_next();
3499 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3501 ir_constant
*const_block
= block
->as_constant();
3502 int buf_base
= st_context(ctx
)->has_hw_atomics
3503 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
3506 buf_base
+ (const_block
? const_block
->value
.u
[0] : 0),
3510 block
->accept(this);
3511 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3512 *buffer
.reladdr
= this->result
;
3513 emit_arl(ir
, sampler_reladdr
, this->result
);
3516 /* Calculate the surface offset */
3517 offset
->accept(this);
3518 st_src_reg off
= this->result
;
3520 st_dst_reg dst
= undef_dst
;
3521 if (ir
->return_deref
) {
3522 ir
->return_deref
->accept(this);
3523 dst
= st_dst_reg(this->result
);
3524 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3527 glsl_to_tgsi_instruction
*inst
;
3529 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3530 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3531 if (dst
.type
== GLSL_TYPE_BOOL
)
3532 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3533 st_src_reg_for_int(0));
3534 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3535 param
= param
->get_next();
3536 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3539 param
= param
->get_next();
3540 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3542 dst
.writemask
= write_mask
->value
.u
[0];
3544 dst
.type
= this->result
.type
;
3545 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3547 param
= param
->get_next();
3548 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3551 st_src_reg data
= this->result
, data2
= undef_src
;
3552 enum tgsi_opcode opcode
;
3553 switch (ir
->callee
->intrinsic_id
) {
3554 case ir_intrinsic_ssbo_atomic_add
:
3555 opcode
= TGSI_OPCODE_ATOMUADD
;
3557 case ir_intrinsic_ssbo_atomic_min
:
3558 opcode
= TGSI_OPCODE_ATOMIMIN
;
3560 case ir_intrinsic_ssbo_atomic_max
:
3561 opcode
= TGSI_OPCODE_ATOMIMAX
;
3563 case ir_intrinsic_ssbo_atomic_and
:
3564 opcode
= TGSI_OPCODE_ATOMAND
;
3566 case ir_intrinsic_ssbo_atomic_or
:
3567 opcode
= TGSI_OPCODE_ATOMOR
;
3569 case ir_intrinsic_ssbo_atomic_xor
:
3570 opcode
= TGSI_OPCODE_ATOMXOR
;
3572 case ir_intrinsic_ssbo_atomic_exchange
:
3573 opcode
= TGSI_OPCODE_ATOMXCHG
;
3575 case ir_intrinsic_ssbo_atomic_comp_swap
:
3576 opcode
= TGSI_OPCODE_ATOMCAS
;
3577 param
= param
->get_next();
3578 val
= ((ir_instruction
*)param
)->as_rvalue();
3580 data2
= this->result
;
3583 assert(!"Unexpected intrinsic");
3587 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3590 param
= param
->get_next();
3591 ir_constant
*access
= NULL
;
3592 if (!param
->is_tail_sentinel()) {
3593 access
= ((ir_instruction
*)param
)->as_constant();
3597 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3601 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3603 switch (ir
->callee
->intrinsic_id
) {
3604 case ir_intrinsic_memory_barrier
:
3605 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3606 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3607 TGSI_MEMBAR_ATOMIC_BUFFER
|
3608 TGSI_MEMBAR_SHADER_IMAGE
|
3609 TGSI_MEMBAR_SHARED
));
3611 case ir_intrinsic_memory_barrier_atomic_counter
:
3612 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3613 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3615 case ir_intrinsic_memory_barrier_buffer
:
3616 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3617 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3619 case ir_intrinsic_memory_barrier_image
:
3620 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3621 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3623 case ir_intrinsic_memory_barrier_shared
:
3624 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3625 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3627 case ir_intrinsic_group_memory_barrier
:
3628 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3629 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3630 TGSI_MEMBAR_ATOMIC_BUFFER
|
3631 TGSI_MEMBAR_SHADER_IMAGE
|
3632 TGSI_MEMBAR_SHARED
|
3633 TGSI_MEMBAR_THREAD_GROUP
));
3636 assert(!"Unexpected memory barrier intrinsic");
3641 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3643 exec_node
*param
= ir
->actual_parameters
.get_head();
3645 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3647 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3649 /* Calculate the surface offset */
3650 offset
->accept(this);
3651 st_src_reg off
= this->result
;
3653 st_dst_reg dst
= undef_dst
;
3654 if (ir
->return_deref
) {
3655 ir
->return_deref
->accept(this);
3656 dst
= st_dst_reg(this->result
);
3657 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3660 glsl_to_tgsi_instruction
*inst
;
3662 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3663 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3664 inst
->resource
= buffer
;
3665 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3666 param
= param
->get_next();
3667 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3670 param
= param
->get_next();
3671 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3673 dst
.writemask
= write_mask
->value
.u
[0];
3675 dst
.type
= this->result
.type
;
3676 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3677 inst
->resource
= buffer
;
3679 param
= param
->get_next();
3680 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3683 st_src_reg data
= this->result
, data2
= undef_src
;
3684 enum tgsi_opcode opcode
;
3685 switch (ir
->callee
->intrinsic_id
) {
3686 case ir_intrinsic_shared_atomic_add
:
3687 opcode
= TGSI_OPCODE_ATOMUADD
;
3689 case ir_intrinsic_shared_atomic_min
:
3690 opcode
= TGSI_OPCODE_ATOMIMIN
;
3692 case ir_intrinsic_shared_atomic_max
:
3693 opcode
= TGSI_OPCODE_ATOMIMAX
;
3695 case ir_intrinsic_shared_atomic_and
:
3696 opcode
= TGSI_OPCODE_ATOMAND
;
3698 case ir_intrinsic_shared_atomic_or
:
3699 opcode
= TGSI_OPCODE_ATOMOR
;
3701 case ir_intrinsic_shared_atomic_xor
:
3702 opcode
= TGSI_OPCODE_ATOMXOR
;
3704 case ir_intrinsic_shared_atomic_exchange
:
3705 opcode
= TGSI_OPCODE_ATOMXCHG
;
3707 case ir_intrinsic_shared_atomic_comp_swap
:
3708 opcode
= TGSI_OPCODE_ATOMCAS
;
3709 param
= param
->get_next();
3710 val
= ((ir_instruction
*)param
)->as_rvalue();
3712 data2
= this->result
;
3715 assert(!"Unexpected intrinsic");
3719 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3720 inst
->resource
= buffer
;
3725 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3726 bool *memory_coherent
, bool *memory_volatile
,
3727 bool *memory_restrict
, bool *memory_read_only
,
3728 unsigned *image_format
)
3731 switch (ir
->ir_type
) {
3732 case ir_type_dereference_record
: {
3733 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3734 const glsl_type
*struct_type
= deref_record
->record
->type
;
3735 int fild_idx
= deref_record
->field_idx
;
3737 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3739 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3741 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3743 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3745 struct_type
->fields
.structure
[fild_idx
].memory_read_only
;
3747 struct_type
->fields
.structure
[fild_idx
].image_format
;
3751 case ir_type_dereference_array
: {
3752 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3753 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3754 memory_coherent
, memory_volatile
, memory_restrict
,
3755 memory_read_only
, image_format
);
3759 case ir_type_dereference_variable
: {
3760 ir_variable
*var
= ir
->variable_referenced();
3762 *type
= var
->type
->without_array();
3763 *memory_coherent
= var
->data
.memory_coherent
;
3764 *memory_volatile
= var
->data
.memory_volatile
;
3765 *memory_restrict
= var
->data
.memory_restrict
;
3766 *memory_read_only
= var
->data
.memory_read_only
;
3767 *image_format
= var
->data
.image_format
;
3777 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3779 exec_node
*param
= ir
->actual_parameters
.get_head();
3781 ir_dereference
*img
= (ir_dereference
*)param
;
3782 const ir_variable
*imgvar
= img
->variable_referenced();
3783 unsigned sampler_array_size
= 1, sampler_base
= 0;
3784 bool memory_coherent
= false, memory_volatile
= false,
3785 memory_restrict
= false, memory_read_only
= false;
3786 unsigned image_format
= 0;
3787 const glsl_type
*type
= NULL
;
3789 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3790 &memory_restrict
, &memory_read_only
, &image_format
);
3793 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3795 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3796 &index
, &reladdr
, !imgvar
->contains_bindless());
3798 image
.index
= index
;
3799 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3800 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3801 *image
.reladdr
= reladdr
;
3802 emit_arl(ir
, sampler_reladdr
, reladdr
);
3805 st_dst_reg dst
= undef_dst
;
3806 if (ir
->return_deref
) {
3807 ir
->return_deref
->accept(this);
3808 dst
= st_dst_reg(this->result
);
3809 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3812 glsl_to_tgsi_instruction
*inst
;
3814 st_src_reg bindless
;
3815 if (imgvar
->contains_bindless()) {
3817 bindless
= this->result
;
3820 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3821 dst
.writemask
= WRITEMASK_XYZ
;
3822 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3823 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3824 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3825 st_dst_reg dstres
= st_dst_reg(res
);
3826 dstres
.writemask
= WRITEMASK_W
;
3827 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3828 res
.swizzle
= SWIZZLE_WWWW
;
3829 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3831 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3833 st_dst_reg coord_dst
;
3834 coord
= get_temp(glsl_type::ivec4_type
);
3835 coord_dst
= st_dst_reg(coord
);
3836 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3837 param
= param
->get_next();
3838 ((ir_dereference
*)param
)->accept(this);
3839 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3840 coord
.swizzle
= SWIZZLE_XXXX
;
3841 switch (type
->coordinate_components()) {
3842 case 4: assert(!"unexpected coord count");
3844 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3846 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3849 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3850 param
= param
->get_next();
3851 ((ir_dereference
*)param
)->accept(this);
3852 st_src_reg sample
= this->result
;
3853 sample
.swizzle
= SWIZZLE_XXXX
;
3854 coord_dst
.writemask
= WRITEMASK_W
;
3855 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3856 coord
.swizzle
|= SWIZZLE_W
<< 9;
3859 param
= param
->get_next();
3860 if (!param
->is_tail_sentinel()) {
3861 ((ir_dereference
*)param
)->accept(this);
3862 arg1
= this->result
;
3863 param
= param
->get_next();
3866 if (!param
->is_tail_sentinel()) {
3867 ((ir_dereference
*)param
)->accept(this);
3868 arg2
= this->result
;
3869 param
= param
->get_next();
3872 assert(param
->is_tail_sentinel());
3874 enum tgsi_opcode opcode
;
3875 switch (ir
->callee
->intrinsic_id
) {
3876 case ir_intrinsic_image_load
:
3877 opcode
= TGSI_OPCODE_LOAD
;
3879 case ir_intrinsic_image_store
:
3880 opcode
= TGSI_OPCODE_STORE
;
3882 case ir_intrinsic_image_atomic_add
:
3883 opcode
= TGSI_OPCODE_ATOMUADD
;
3885 case ir_intrinsic_image_atomic_min
:
3886 opcode
= TGSI_OPCODE_ATOMIMIN
;
3888 case ir_intrinsic_image_atomic_max
:
3889 opcode
= TGSI_OPCODE_ATOMIMAX
;
3891 case ir_intrinsic_image_atomic_and
:
3892 opcode
= TGSI_OPCODE_ATOMAND
;
3894 case ir_intrinsic_image_atomic_or
:
3895 opcode
= TGSI_OPCODE_ATOMOR
;
3897 case ir_intrinsic_image_atomic_xor
:
3898 opcode
= TGSI_OPCODE_ATOMXOR
;
3900 case ir_intrinsic_image_atomic_exchange
:
3901 opcode
= TGSI_OPCODE_ATOMXCHG
;
3903 case ir_intrinsic_image_atomic_comp_swap
:
3904 opcode
= TGSI_OPCODE_ATOMCAS
;
3907 assert(!"Unexpected intrinsic");
3911 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3912 if (opcode
== TGSI_OPCODE_STORE
)
3913 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3916 if (imgvar
->contains_bindless()) {
3917 inst
->resource
= bindless
;
3918 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3919 SWIZZLE_X
, SWIZZLE_Y
);
3921 inst
->resource
= image
;
3922 inst
->sampler_array_size
= sampler_array_size
;
3923 inst
->sampler_base
= sampler_base
;
3926 inst
->tex_target
= type
->sampler_index();
3927 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3928 _mesa_get_shader_image_format(image_format
));
3929 inst
->read_only
= memory_read_only
;
3931 if (memory_coherent
)
3932 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3933 if (memory_restrict
)
3934 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3935 if (memory_volatile
)
3936 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3940 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
3942 ir
->return_deref
->accept(this);
3943 st_dst_reg dst
= st_dst_reg(this->result
);
3945 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3947 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3948 unsigned num_src
= 0;
3949 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3950 assert(num_src
< ARRAY_SIZE(src
));
3952 this->result
.file
= PROGRAM_UNDEFINED
;
3953 param
->accept(this);
3954 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3956 src
[num_src
] = this->result
;
3960 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3964 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3966 ir_function_signature
*sig
= ir
->callee
;
3968 /* Filter out intrinsics */
3969 switch (sig
->intrinsic_id
) {
3970 case ir_intrinsic_atomic_counter_read
:
3971 case ir_intrinsic_atomic_counter_increment
:
3972 case ir_intrinsic_atomic_counter_predecrement
:
3973 case ir_intrinsic_atomic_counter_add
:
3974 case ir_intrinsic_atomic_counter_min
:
3975 case ir_intrinsic_atomic_counter_max
:
3976 case ir_intrinsic_atomic_counter_and
:
3977 case ir_intrinsic_atomic_counter_or
:
3978 case ir_intrinsic_atomic_counter_xor
:
3979 case ir_intrinsic_atomic_counter_exchange
:
3980 case ir_intrinsic_atomic_counter_comp_swap
:
3981 visit_atomic_counter_intrinsic(ir
);
3984 case ir_intrinsic_ssbo_load
:
3985 case ir_intrinsic_ssbo_store
:
3986 case ir_intrinsic_ssbo_atomic_add
:
3987 case ir_intrinsic_ssbo_atomic_min
:
3988 case ir_intrinsic_ssbo_atomic_max
:
3989 case ir_intrinsic_ssbo_atomic_and
:
3990 case ir_intrinsic_ssbo_atomic_or
:
3991 case ir_intrinsic_ssbo_atomic_xor
:
3992 case ir_intrinsic_ssbo_atomic_exchange
:
3993 case ir_intrinsic_ssbo_atomic_comp_swap
:
3994 visit_ssbo_intrinsic(ir
);
3997 case ir_intrinsic_memory_barrier
:
3998 case ir_intrinsic_memory_barrier_atomic_counter
:
3999 case ir_intrinsic_memory_barrier_buffer
:
4000 case ir_intrinsic_memory_barrier_image
:
4001 case ir_intrinsic_memory_barrier_shared
:
4002 case ir_intrinsic_group_memory_barrier
:
4003 visit_membar_intrinsic(ir
);
4006 case ir_intrinsic_shared_load
:
4007 case ir_intrinsic_shared_store
:
4008 case ir_intrinsic_shared_atomic_add
:
4009 case ir_intrinsic_shared_atomic_min
:
4010 case ir_intrinsic_shared_atomic_max
:
4011 case ir_intrinsic_shared_atomic_and
:
4012 case ir_intrinsic_shared_atomic_or
:
4013 case ir_intrinsic_shared_atomic_xor
:
4014 case ir_intrinsic_shared_atomic_exchange
:
4015 case ir_intrinsic_shared_atomic_comp_swap
:
4016 visit_shared_intrinsic(ir
);
4019 case ir_intrinsic_image_load
:
4020 case ir_intrinsic_image_store
:
4021 case ir_intrinsic_image_atomic_add
:
4022 case ir_intrinsic_image_atomic_min
:
4023 case ir_intrinsic_image_atomic_max
:
4024 case ir_intrinsic_image_atomic_and
:
4025 case ir_intrinsic_image_atomic_or
:
4026 case ir_intrinsic_image_atomic_xor
:
4027 case ir_intrinsic_image_atomic_exchange
:
4028 case ir_intrinsic_image_atomic_comp_swap
:
4029 case ir_intrinsic_image_size
:
4030 case ir_intrinsic_image_samples
:
4031 visit_image_intrinsic(ir
);
4034 case ir_intrinsic_shader_clock
:
4035 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4038 case ir_intrinsic_vote_all
:
4039 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4041 case ir_intrinsic_vote_any
:
4042 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4044 case ir_intrinsic_vote_eq
:
4045 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4047 case ir_intrinsic_ballot
:
4048 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4050 case ir_intrinsic_read_first_invocation
:
4051 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4053 case ir_intrinsic_read_invocation
:
4054 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4057 case ir_intrinsic_invalid
:
4058 case ir_intrinsic_generic_load
:
4059 case ir_intrinsic_generic_store
:
4060 case ir_intrinsic_generic_atomic_add
:
4061 case ir_intrinsic_generic_atomic_and
:
4062 case ir_intrinsic_generic_atomic_or
:
4063 case ir_intrinsic_generic_atomic_xor
:
4064 case ir_intrinsic_generic_atomic_min
:
4065 case ir_intrinsic_generic_atomic_max
:
4066 case ir_intrinsic_generic_atomic_exchange
:
4067 case ir_intrinsic_generic_atomic_comp_swap
:
4068 case ir_intrinsic_begin_invocation_interlock
:
4069 case ir_intrinsic_end_invocation_interlock
:
4070 unreachable("Invalid intrinsic");
4075 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4076 unsigned *array_elements
,
4078 st_src_reg
*indirect
,
4081 switch (tail
->ir_type
) {
4082 case ir_type_dereference_record
: {
4083 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4084 const glsl_type
*struct_type
= deref_record
->record
->type
;
4085 int field_index
= deref_record
->field_idx
;
4087 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4089 assert(field_index
>= 0);
4090 *location
+= struct_type
->record_location_offset(field_index
);
4094 case ir_type_dereference_array
: {
4095 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4097 void *mem_ctx
= ralloc_parent(deref_arr
);
4098 ir_constant
*array_index
=
4099 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4102 st_src_reg temp_reg
;
4103 st_dst_reg temp_dst
;
4105 temp_reg
= get_temp(glsl_type::uint_type
);
4106 temp_dst
= st_dst_reg(temp_reg
);
4107 temp_dst
.writemask
= 1;
4109 deref_arr
->array_index
->accept(this);
4110 if (*array_elements
!= 1)
4111 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4113 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4115 if (indirect
->file
== PROGRAM_UNDEFINED
)
4116 *indirect
= temp_reg
;
4118 temp_dst
= st_dst_reg(*indirect
);
4119 temp_dst
.writemask
= 1;
4120 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4123 *index
+= array_index
->value
.u
[0] * *array_elements
;
4125 *array_elements
*= deref_arr
->array
->type
->length
;
4127 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4136 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4137 unsigned *array_size
,
4140 st_src_reg
*reladdr
,
4143 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4144 unsigned location
= 0;
4145 ir_variable
*var
= ir
->variable_referenced();
4147 memset(reladdr
, 0, sizeof(*reladdr
));
4148 reladdr
->file
= PROGRAM_UNDEFINED
;
4154 location
= var
->data
.location
;
4155 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4158 * If we end up with no indirect then adjust the base to the index,
4159 * and set the array size to 1.
4161 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4167 assert(location
!= 0xffffffff);
4168 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4169 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4174 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4176 if (offset
.reladdr
|| offset
.reladdr2
||
4177 offset
.has_index2
||
4178 offset
.file
== PROGRAM_UNIFORM
||
4179 offset
.file
== PROGRAM_CONSTANT
||
4180 offset
.file
== PROGRAM_STATE_VAR
) {
4181 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4182 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4183 tmp_dst
.writemask
= WRITEMASK_XY
;
4184 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4192 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4194 ir_variable
*var
= ir
->variable_referenced();
4196 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4197 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4200 /* Convert from bound sampler/image to bindless handle. */
4201 bool is_image
= ir
->type
->is_image();
4202 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4204 unsigned array_size
= 1, base
= 0;
4206 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4208 resource
.index
= index
;
4209 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4210 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4211 *resource
.reladdr
= reladdr
;
4212 emit_arl(ir
, sampler_reladdr
, reladdr
);
4215 this->result
= get_temp(glsl_type::uvec2_type
);
4216 st_dst_reg
dst(this->result
);
4217 dst
.writemask
= WRITEMASK_XY
;
4219 glsl_to_tgsi_instruction
*inst
= emit_asm(
4220 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4222 inst
->tex_target
= ir
->type
->sampler_index();
4223 inst
->resource
= resource
;
4224 inst
->sampler_array_size
= array_size
;
4225 inst
->sampler_base
= base
;
4231 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4233 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4234 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4235 st_src_reg levels_src
, reladdr
;
4236 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4237 glsl_to_tgsi_instruction
*inst
= NULL
;
4238 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4239 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4240 unsigned sampler_array_size
= 1, sampler_base
= 0;
4241 bool is_cube_array
= false, is_cube_shadow
= false;
4242 ir_variable
*var
= ir
->sampler
->variable_referenced();
4245 /* if we are a cube array sampler or a cube shadow */
4246 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4247 is_cube_array
= sampler_type
->sampler_array
;
4248 is_cube_shadow
= sampler_type
->sampler_shadow
;
4251 if (ir
->coordinate
) {
4252 ir
->coordinate
->accept(this);
4254 /* Put our coords in a temp. We'll need to modify them for shadow,
4255 * projection, or LOD, so the only case we'd use it as-is is if
4256 * we're doing plain old texturing. The optimization passes on
4257 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4259 coord
= get_temp(glsl_type::vec4_type
);
4260 coord_dst
= st_dst_reg(coord
);
4261 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4262 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4265 if (ir
->projector
) {
4266 ir
->projector
->accept(this);
4267 projector
= this->result
;
4270 /* Storage for our result. Ideally for an assignment we'd be using
4271 * the actual storage for the result here, instead.
4273 result_src
= get_temp(ir
->type
);
4274 result_dst
= st_dst_reg(result_src
);
4275 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4279 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4281 ir
->offset
->accept(this);
4282 offset
[0] = this->result
;
4286 if (is_cube_array
|| is_cube_shadow
) {
4287 opcode
= TGSI_OPCODE_TXB2
;
4290 opcode
= TGSI_OPCODE_TXB
;
4292 ir
->lod_info
.bias
->accept(this);
4293 lod_info
= this->result
;
4295 ir
->offset
->accept(this);
4296 offset
[0] = this->result
;
4300 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4301 opcode
= TGSI_OPCODE_TEX_LZ
;
4303 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4304 ir
->lod_info
.lod
->accept(this);
4305 lod_info
= this->result
;
4308 ir
->offset
->accept(this);
4309 offset
[0] = this->result
;
4313 opcode
= TGSI_OPCODE_TXD
;
4314 ir
->lod_info
.grad
.dPdx
->accept(this);
4316 ir
->lod_info
.grad
.dPdy
->accept(this);
4319 ir
->offset
->accept(this);
4320 offset
[0] = this->result
;
4324 opcode
= TGSI_OPCODE_TXQ
;
4325 ir
->lod_info
.lod
->accept(this);
4326 lod_info
= this->result
;
4328 case ir_query_levels
:
4329 opcode
= TGSI_OPCODE_TXQ
;
4330 lod_info
= undef_src
;
4331 levels_src
= get_temp(ir
->type
);
4334 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4335 opcode
= TGSI_OPCODE_TXF_LZ
;
4337 opcode
= TGSI_OPCODE_TXF
;
4338 ir
->lod_info
.lod
->accept(this);
4339 lod_info
= this->result
;
4342 ir
->offset
->accept(this);
4343 offset
[0] = this->result
;
4347 opcode
= TGSI_OPCODE_TXF
;
4348 ir
->lod_info
.sample_index
->accept(this);
4349 sample_index
= this->result
;
4352 opcode
= TGSI_OPCODE_TG4
;
4353 ir
->lod_info
.component
->accept(this);
4354 component
= this->result
;
4356 ir
->offset
->accept(this);
4357 if (ir
->offset
->type
->is_array()) {
4358 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4359 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4360 offset
[i
] = this->result
;
4361 offset
[i
].index
+= i
* type_size(elt_type
);
4362 offset
[i
].type
= elt_type
->base_type
;
4363 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4364 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4367 offset
[0] = canonicalize_gather_offset(this->result
);
4372 opcode
= TGSI_OPCODE_LODQ
;
4374 case ir_texture_samples
:
4375 opcode
= TGSI_OPCODE_TXQS
;
4377 case ir_samples_identical
:
4378 unreachable("Unexpected ir_samples_identical opcode");
4381 if (ir
->projector
) {
4382 if (opcode
== TGSI_OPCODE_TEX
) {
4383 /* Slot the projector in as the last component of the coord. */
4384 coord_dst
.writemask
= WRITEMASK_W
;
4385 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4386 coord_dst
.writemask
= WRITEMASK_XYZW
;
4387 opcode
= TGSI_OPCODE_TXP
;
4389 st_src_reg coord_w
= coord
;
4390 coord_w
.swizzle
= SWIZZLE_WWWW
;
4392 /* For the other TEX opcodes there's no projective version
4393 * since the last slot is taken up by LOD info. Do the
4394 * projective divide now.
4396 coord_dst
.writemask
= WRITEMASK_W
;
4397 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4399 /* In the case where we have to project the coordinates "by hand,"
4400 * the shadow comparator value must also be projected.
4402 st_src_reg tmp_src
= coord
;
4403 if (ir
->shadow_comparator
) {
4404 /* Slot the shadow value in as the second to last component of the
4407 ir
->shadow_comparator
->accept(this);
4409 tmp_src
= get_temp(glsl_type::vec4_type
);
4410 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4412 /* Projective division not allowed for array samplers. */
4413 assert(!sampler_type
->sampler_array
);
4415 tmp_dst
.writemask
= WRITEMASK_Z
;
4416 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4418 tmp_dst
.writemask
= WRITEMASK_XY
;
4419 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4422 coord_dst
.writemask
= WRITEMASK_XYZ
;
4423 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4425 coord_dst
.writemask
= WRITEMASK_XYZW
;
4426 coord
.swizzle
= SWIZZLE_XYZW
;
4430 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4431 * shadow comparator was put in the correct place (and projected) by the
4432 * code, above, that handles by-hand projection.
4434 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4435 /* Slot the shadow value in as the second to last component of the
4438 ir
->shadow_comparator
->accept(this);
4440 if (is_cube_array
) {
4441 cube_sc
= get_temp(glsl_type::float_type
);
4442 cube_sc_dst
= st_dst_reg(cube_sc
);
4443 cube_sc_dst
.writemask
= WRITEMASK_X
;
4444 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4445 cube_sc_dst
.writemask
= WRITEMASK_X
;
4448 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4449 sampler_type
->sampler_array
) ||
4450 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4451 coord_dst
.writemask
= WRITEMASK_W
;
4453 coord_dst
.writemask
= WRITEMASK_Z
;
4455 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4456 coord_dst
.writemask
= WRITEMASK_XYZW
;
4460 if (ir
->op
== ir_txf_ms
) {
4461 coord_dst
.writemask
= WRITEMASK_W
;
4462 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4463 coord_dst
.writemask
= WRITEMASK_XYZW
;
4464 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4465 opcode
== TGSI_OPCODE_TXF
) {
4466 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4467 coord_dst
.writemask
= WRITEMASK_W
;
4468 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4469 coord_dst
.writemask
= WRITEMASK_XYZW
;
4472 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4475 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4476 &index
, &reladdr
, !var
->contains_bindless());
4478 sampler
.index
= index
;
4479 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4480 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4481 *sampler
.reladdr
= reladdr
;
4482 emit_arl(ir
, sampler_reladdr
, reladdr
);
4485 st_src_reg bindless
;
4486 if (var
->contains_bindless()) {
4487 ir
->sampler
->accept(this);
4488 bindless
= this->result
;
4491 if (opcode
== TGSI_OPCODE_TXD
)
4492 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4493 else if (opcode
== TGSI_OPCODE_TXQ
) {
4494 if (ir
->op
== ir_query_levels
) {
4495 /* the level is stored in W */
4496 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4497 result_dst
.writemask
= WRITEMASK_X
;
4498 levels_src
.swizzle
= SWIZZLE_WWWW
;
4499 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4501 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4502 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4503 inst
= emit_asm(ir
, opcode
, result_dst
);
4504 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4505 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4506 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4507 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4508 } else if (opcode
== TGSI_OPCODE_TG4
) {
4509 if (is_cube_array
&& ir
->shadow_comparator
) {
4510 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4512 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4515 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4517 if (ir
->shadow_comparator
)
4518 inst
->tex_shadow
= GL_TRUE
;
4520 if (var
->contains_bindless()) {
4521 inst
->resource
= bindless
;
4522 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4523 SWIZZLE_X
, SWIZZLE_Y
);
4525 inst
->resource
= sampler
;
4526 inst
->sampler_array_size
= sampler_array_size
;
4527 inst
->sampler_base
= sampler_base
;
4531 if (!inst
->tex_offsets
)
4532 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4533 MAX_GLSL_TEXTURE_OFFSET
);
4535 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4536 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4537 inst
->tex_offsets
[i
] = offset
[i
];
4538 inst
->tex_offset_num_offset
= i
;
4541 inst
->tex_target
= sampler_type
->sampler_index();
4542 inst
->tex_type
= ir
->type
->base_type
;
4544 this->result
= result_src
;
4548 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4550 assert(!ir
->get_value());
4552 emit_asm(ir
, TGSI_OPCODE_RET
);
4556 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4558 if (ir
->condition
) {
4559 ir
->condition
->accept(this);
4560 st_src_reg condition
= this->result
;
4562 /* Convert the bool condition to a float so we can negate. */
4563 if (native_integers
) {
4564 st_src_reg temp
= get_temp(ir
->condition
->type
);
4565 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4566 condition
, st_src_reg_for_float(1.0));
4570 condition
.negate
= ~condition
.negate
;
4571 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4573 /* unconditional kil */
4574 emit_asm(ir
, TGSI_OPCODE_KILL
);
4579 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4581 enum tgsi_opcode if_opcode
;
4582 glsl_to_tgsi_instruction
*if_inst
;
4584 ir
->condition
->accept(this);
4585 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4587 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4589 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4591 this->instructions
.push_tail(if_inst
);
4593 visit_exec_list(&ir
->then_instructions
, this);
4595 if (!ir
->else_instructions
.is_empty()) {
4596 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4597 visit_exec_list(&ir
->else_instructions
, this);
4600 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4605 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4607 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4609 ir
->stream
->accept(this);
4610 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4614 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4616 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4618 ir
->stream
->accept(this);
4619 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4623 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4625 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4626 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4628 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4631 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4633 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4635 result
.file
= PROGRAM_UNDEFINED
;
4642 num_input_arrays
= 0;
4643 num_output_arrays
= 0;
4645 num_atomic_arrays
= 0;
4647 num_address_regs
= 0;
4650 indirect_addr_consts
= false;
4651 wpos_transform_const
= -1;
4652 native_integers
= false;
4653 mem_ctx
= ralloc_context(NULL
);
4657 shader_program
= NULL
;
4662 use_shared_memory
= false;
4663 has_tex_txf_lz
= false;
4667 static void var_destroy(struct hash_entry
*entry
)
4669 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4674 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4676 _mesa_hash_table_destroy(variables
, var_destroy
);
4678 ralloc_free(mem_ctx
);
4681 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4688 * Count resources used by the given gpu program (number of texture
4692 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4694 v
->samplers_used
= 0;
4696 prog
->info
.textures_used_by_txf
= 0;
4698 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4699 if (inst
->info
->is_tex
) {
4700 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4701 unsigned idx
= inst
->sampler_base
+ i
;
4702 v
->samplers_used
|= 1u << idx
;
4704 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4705 v
->sampler_types
[idx
] = inst
->tex_type
;
4706 v
->sampler_targets
[idx
] =
4707 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4709 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4710 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4715 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4716 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4718 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4719 is_resource_instruction(inst
->op
) ||
4720 inst
->op
== TGSI_OPCODE_STORE
)) {
4721 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4722 v
->use_shared_memory
= true;
4723 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4724 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4725 unsigned idx
= inst
->sampler_base
+ i
;
4726 v
->images_used
|= 1 << idx
;
4727 v
->image_targets
[idx
] =
4728 st_translate_texture_target(inst
->tex_target
, false);
4729 v
->image_formats
[idx
] = inst
->image_format
;
4730 v
->image_wr
[idx
] = !inst
->read_only
;
4735 prog
->SamplersUsed
= v
->samplers_used
;
4737 if (v
->shader_program
!= NULL
)
4738 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4742 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4743 * are read from the given src in this instruction
4746 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4748 int read_mask
= 0, comp
;
4750 /* Now, given the src swizzle and the written channels, find which
4751 * components are actually read
4753 for (comp
= 0; comp
< 4; ++comp
) {
4754 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4756 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4757 read_mask
|= 1 << coord
;
4764 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4765 * instruction is the first instruction to write to register T0. There are
4766 * several lowering passes done in GLSL IR (e.g. branches and
4767 * relative addressing) that create a large number of conditional assignments
4768 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4770 * Here is why this conversion is safe:
4771 * CMP T0, T1 T2 T0 can be expanded to:
4777 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4778 * as the original program. If (T1 < 0.0) evaluates to false, executing
4779 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4780 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4781 * because any instruction that was going to read from T0 after this was going
4782 * to read a garbage value anyway.
4785 glsl_to_tgsi_visitor::simplify_cmp(void)
4787 int tempWritesSize
= 0;
4788 unsigned *tempWrites
= NULL
;
4789 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4791 memset(outputWrites
, 0, sizeof(outputWrites
));
4793 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4794 unsigned prevWriteMask
= 0;
4796 /* Give up if we encounter relative addressing or flow control. */
4797 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4798 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4799 inst
->info
->is_branch
||
4800 inst
->op
== TGSI_OPCODE_CONT
||
4801 inst
->op
== TGSI_OPCODE_END
||
4802 inst
->op
== TGSI_OPCODE_RET
) {
4806 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4807 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4808 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4809 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4810 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4811 if (inst
->dst
[0].index
>= tempWritesSize
) {
4812 const int inc
= 4096;
4814 tempWrites
= (unsigned*)
4816 (tempWritesSize
+ inc
) * sizeof(unsigned));
4820 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4821 tempWritesSize
+= inc
;
4824 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4825 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4829 /* For a CMP to be considered a conditional write, the destination
4830 * register and source register two must be the same. */
4831 if (inst
->op
== TGSI_OPCODE_CMP
4832 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4833 && inst
->src
[2].file
== inst
->dst
[0].file
4834 && inst
->src
[2].index
== inst
->dst
[0].index
4835 && inst
->dst
[0].writemask
==
4836 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4838 inst
->op
= TGSI_OPCODE_MOV
;
4839 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4840 inst
->src
[0] = inst
->src
[1];
4848 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4850 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4851 int old_idx
= src
->index
;
4852 if (renames
[old_idx
].valid
)
4853 src
->index
= renames
[old_idx
].new_reg
;
4857 /* Replaces all references to a temporary register index with another index. */
4859 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4861 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4863 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4864 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4865 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4866 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4869 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4870 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4871 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4872 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4875 rename_temp_handle_src(renames
, &inst
->resource
);
4876 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4877 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4879 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4880 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4881 int old_idx
= inst
->dst
[j
].index
;
4882 if (renames
[old_idx
].valid
)
4883 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4885 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4886 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4892 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4894 int depth
= 0; /* loop depth */
4895 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4898 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4899 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4900 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4901 if (first_writes
[inst
->dst
[j
].index
] == -1)
4902 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4906 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4909 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4919 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4921 int depth
= 0; /* loop depth */
4922 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4925 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4926 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4927 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4928 if (first_reads
[inst
->src
[j
].index
] == -1)
4929 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4932 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4933 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4934 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4935 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4938 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4941 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4951 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4953 int depth
= 0; /* loop depth */
4954 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4957 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4958 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4959 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4960 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4962 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4963 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4964 if (first_writes
[inst
->dst
[j
].index
] == -1)
4965 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4966 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4969 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4970 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4971 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4973 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4976 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4979 for (k
= 0; k
< this->next_temp
; k
++) {
4980 if (last_reads
[k
] == -2) {
4992 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4994 int depth
= 0; /* loop depth */
4998 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4999 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5000 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
5001 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5004 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
5006 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
5008 for (k
= 0; k
< this->next_temp
; k
++) {
5009 if (last_writes
[k
] == -2) {
5020 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5021 * channels for copy propagation and updates following instructions to
5022 * use the original versions.
5024 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5025 * will occur. As an example, a TXP production before this pass:
5027 * 0: MOV TEMP[1], INPUT[4].xyyy;
5028 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5029 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5033 * 0: MOV TEMP[1], INPUT[4].xyyy;
5034 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5035 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5037 * which allows for dead code elimination on TEMP[1]'s writes.
5040 glsl_to_tgsi_visitor::copy_propagate(void)
5042 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5043 glsl_to_tgsi_instruction
*,
5044 this->next_temp
* 4);
5045 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5048 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5049 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5050 || inst
->dst
[0].index
< this->next_temp
);
5052 /* First, do any copy propagation possible into the src regs. */
5053 for (int r
= 0; r
< 3; r
++) {
5054 glsl_to_tgsi_instruction
*first
= NULL
;
5056 int acp_base
= inst
->src
[r
].index
* 4;
5058 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5059 inst
->src
[r
].reladdr
||
5060 inst
->src
[r
].reladdr2
)
5063 /* See if we can find entries in the ACP consisting of MOVs
5064 * from the same src register for all the swizzled channels
5065 * of this src register reference.
5067 for (int i
= 0; i
< 4; i
++) {
5068 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5069 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5076 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5081 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5082 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5083 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5084 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5092 /* We've now validated that we can copy-propagate to
5093 * replace this src register reference. Do it.
5095 inst
->src
[r
].file
= first
->src
[0].file
;
5096 inst
->src
[r
].index
= first
->src
[0].index
;
5097 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5098 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5099 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5100 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5103 for (int i
= 0; i
< 4; i
++) {
5104 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5105 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5106 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5108 inst
->src
[r
].swizzle
= swizzle
;
5113 case TGSI_OPCODE_BGNLOOP
:
5114 case TGSI_OPCODE_ENDLOOP
:
5115 /* End of a basic block, clear the ACP entirely. */
5116 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5119 case TGSI_OPCODE_IF
:
5120 case TGSI_OPCODE_UIF
:
5124 case TGSI_OPCODE_ENDIF
:
5125 case TGSI_OPCODE_ELSE
:
5126 /* Clear all channels written inside the block from the ACP, but
5127 * leaving those that were not touched.
5129 for (int r
= 0; r
< this->next_temp
; r
++) {
5130 for (int c
= 0; c
< 4; c
++) {
5131 if (!acp
[4 * r
+ c
])
5134 if (acp_level
[4 * r
+ c
] >= level
)
5135 acp
[4 * r
+ c
] = NULL
;
5138 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5143 /* Continuing the block, clear any written channels from
5146 for (int d
= 0; d
< 2; d
++) {
5147 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5148 /* Any temporary might be written, so no copy propagation
5149 * across this instruction.
5151 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5152 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5153 inst
->dst
[d
].reladdr
) {
5154 /* Any output might be written, so no copy propagation
5155 * from outputs across this instruction.
5157 for (int r
= 0; r
< this->next_temp
; r
++) {
5158 for (int c
= 0; c
< 4; c
++) {
5159 if (!acp
[4 * r
+ c
])
5162 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5163 acp
[4 * r
+ c
] = NULL
;
5166 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5167 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5168 /* Clear where it's used as dst. */
5169 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5170 for (int c
= 0; c
< 4; c
++) {
5171 if (inst
->dst
[d
].writemask
& (1 << c
))
5172 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5176 /* Clear where it's used as src. */
5177 for (int r
= 0; r
< this->next_temp
; r
++) {
5178 for (int c
= 0; c
< 4; c
++) {
5179 if (!acp
[4 * r
+ c
])
5182 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5184 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5185 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5186 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5187 acp
[4 * r
+ c
] = NULL
;
5196 /* If this is a copy, add it to the ACP. */
5197 if (inst
->op
== TGSI_OPCODE_MOV
&&
5198 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5199 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5200 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5201 !inst
->dst
[0].reladdr
&&
5202 !inst
->dst
[0].reladdr2
&&
5204 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5205 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5206 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5207 !inst
->src
[0].reladdr
&&
5208 !inst
->src
[0].reladdr2
&&
5209 !inst
->src
[0].negate
&&
5210 !inst
->src
[0].abs
) {
5211 for (int i
= 0; i
< 4; i
++) {
5212 if (inst
->dst
[0].writemask
& (1 << i
)) {
5213 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5214 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5220 ralloc_free(acp_level
);
5225 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5227 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5228 /* Clear where it's used as src. */
5229 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5230 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5235 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5238 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5239 * will occur. As an example, a TXP production after copy propagation but
5242 * 0: MOV TEMP[1], INPUT[4].xyyy;
5243 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5244 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5246 * and after this pass:
5248 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5251 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5253 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5254 glsl_to_tgsi_instruction
*,
5255 this->next_temp
* 4);
5256 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5260 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5261 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5262 || inst
->dst
[0].index
< this->next_temp
);
5265 case TGSI_OPCODE_BGNLOOP
:
5266 case TGSI_OPCODE_ENDLOOP
:
5267 case TGSI_OPCODE_CONT
:
5268 case TGSI_OPCODE_BRK
:
5269 /* End of a basic block, clear the write array entirely.
5271 * This keeps us from killing dead code when the writes are
5272 * on either side of a loop, even when the register isn't touched
5273 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5274 * dead code of this type, so it shouldn't make a difference as long as
5275 * the dead code elimination pass in the GLSL compiler does its job.
5277 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5280 case TGSI_OPCODE_ENDIF
:
5281 case TGSI_OPCODE_ELSE
:
5282 /* Promote the recorded level of all channels written inside the
5283 * preceding if or else block to the level above the if/else block.
5285 for (int r
= 0; r
< this->next_temp
; r
++) {
5286 for (int c
= 0; c
< 4; c
++) {
5287 if (!writes
[4 * r
+ c
])
5290 if (write_level
[4 * r
+ c
] == level
)
5291 write_level
[4 * r
+ c
] = level
-1;
5294 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5298 case TGSI_OPCODE_IF
:
5299 case TGSI_OPCODE_UIF
:
5301 /* fallthrough to default case to mark the condition as read */
5303 /* Continuing the block, clear any channels from the write array that
5304 * are read by this instruction.
5306 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5307 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5308 /* Any temporary might be read, so no dead code elimination
5309 * across this instruction.
5311 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5312 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5313 /* Clear where it's used as src. */
5314 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5315 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5316 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5317 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5319 for (int c
= 0; c
< 4; c
++) {
5320 if (src_chans
& (1 << c
))
5321 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5324 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5325 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5327 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5328 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5329 /* Any temporary might be read, so no dead code elimination
5330 * across this instruction.
5332 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5333 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5334 /* Clear where it's used as src. */
5335 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5336 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5337 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5338 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5340 for (int c
= 0; c
< 4; c
++) {
5341 if (src_chans
& (1 << c
))
5342 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5345 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5346 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5349 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5352 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5353 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5354 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5355 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5357 for (int c
= 0; c
< 4; c
++) {
5358 if (src_chans
& (1 << c
))
5359 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5362 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5363 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5365 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5366 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5367 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5372 /* If this instruction writes to a temporary, add it to the write array.
5373 * If there is already an instruction in the write array for one or more
5374 * of the channels, flag that channel write as dead.
5376 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5377 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5378 !inst
->dst
[i
].reladdr
) {
5379 for (int c
= 0; c
< 4; c
++) {
5380 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5381 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5382 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5385 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5387 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5388 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5395 /* Anything still in the write array at this point is dead code. */
5396 for (int r
= 0; r
< this->next_temp
; r
++) {
5397 for (int c
= 0; c
< 4; c
++) {
5398 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5400 inst
->dead_mask
|= (1 << c
);
5404 /* Now actually remove the instructions that are completely dead and update
5405 * the writemask of other instructions with dead channels.
5407 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5408 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5410 /* No amount of dead masks should remove memory stores */
5411 if (inst
->info
->is_store
)
5414 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5419 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5420 if (inst
->dead_mask
== WRITEMASK_XY
||
5421 inst
->dead_mask
== WRITEMASK_ZW
)
5422 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5424 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5428 ralloc_free(write_level
);
5429 ralloc_free(writes
);
5434 /* merge DFRACEXP instructions into one. */
5436 glsl_to_tgsi_visitor::merge_two_dsts(void)
5438 /* We never delete inst, but we may delete its successor. */
5439 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5440 glsl_to_tgsi_instruction
*inst2
;
5443 if (num_inst_dst_regs(inst
) != 2)
5446 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5447 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5450 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5451 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5453 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5458 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5459 while (!inst2
->is_tail_sentinel()) {
5460 if (inst
->op
== inst2
->op
&&
5461 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5462 inst
->src
[0].file
== inst2
->src
[0].file
&&
5463 inst
->src
[0].index
== inst2
->src
[0].index
&&
5464 inst
->src
[0].type
== inst2
->src
[0].type
&&
5465 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5467 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5470 if (inst2
->is_tail_sentinel()) {
5471 /* Undefined destinations are not allowed, substitute with an unused
5472 * temporary register.
5474 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5475 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5476 inst
->dst
[defined
^ 1].writemask
= 0;
5480 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5486 /* Merges temporary registers together where possible to reduce the number of
5487 * registers needed to run a program.
5489 * Produces optimal code only after copy propagation and dead code elimination
5492 glsl_to_tgsi_visitor::merge_registers(void)
5494 struct lifetime
*lifetimes
=
5495 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5497 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5498 this->next_temp
, lifetimes
)) {
5499 struct rename_reg_pair
*renames
=
5500 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5501 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5502 rename_temp_registers(renames
);
5503 ralloc_free(renames
);
5506 ralloc_free(lifetimes
);
5509 /* Reassign indices to temporary registers by reusing unused indices created
5510 * by optimization passes. */
5512 glsl_to_tgsi_visitor::renumber_registers(void)
5516 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5517 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5519 for (i
= 0; i
< this->next_temp
; i
++) {
5520 first_writes
[i
] = -1;
5522 get_first_temp_write(first_writes
);
5524 for (i
= 0; i
< this->next_temp
; i
++) {
5525 if (first_writes
[i
] < 0) continue;
5526 if (i
!= new_index
) {
5527 renames
[i
].new_reg
= new_index
;
5528 renames
[i
].valid
= true;
5533 rename_temp_registers(renames
);
5534 this->next_temp
= new_index
;
5535 ralloc_free(renames
);
5536 ralloc_free(first_writes
);
5540 void glsl_to_tgsi_visitor::print_stats()
5542 int narray_registers
= 0;
5543 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5544 narray_registers
+= this->array_sizes
[i
];
5546 int ninstructions
= 0;
5547 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &instructions
) {
5551 simple_mtx_lock(&print_stats_mutex
);
5552 stats_log
<< next_array
<< ", "
5553 << next_temp
<< ", "
5554 << narray_registers
<< ", "
5555 << next_temp
+ narray_registers
<< ", "
5556 << ninstructions
<< "\n";
5557 simple_mtx_unlock(&print_stats_mutex
);
5560 /* ------------------------- TGSI conversion stuff -------------------------- */
5563 * Intermediate state used during shader translation.
5565 struct st_translate
{
5566 struct ureg_program
*ureg
;
5568 unsigned temps_size
;
5569 struct ureg_dst
*temps
;
5571 struct ureg_dst
*arrays
;
5572 unsigned num_temp_arrays
;
5573 struct ureg_src
*constants
;
5575 struct ureg_src
*immediates
;
5577 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5578 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5579 struct ureg_dst address
[3];
5580 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5581 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5582 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5583 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5584 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5585 struct ureg_src shared_memory
;
5586 unsigned *array_sizes
;
5587 struct inout_decl
*input_decls
;
5588 unsigned num_input_decls
;
5589 struct inout_decl
*output_decls
;
5590 unsigned num_output_decls
;
5592 const ubyte
*inputMapping
;
5593 const ubyte
*outputMapping
;
5595 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5599 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5601 _mesa_sysval_to_semantic(unsigned sysval
)
5605 case SYSTEM_VALUE_VERTEX_ID
:
5606 return TGSI_SEMANTIC_VERTEXID
;
5607 case SYSTEM_VALUE_INSTANCE_ID
:
5608 return TGSI_SEMANTIC_INSTANCEID
;
5609 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5610 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5611 case SYSTEM_VALUE_BASE_VERTEX
:
5612 return TGSI_SEMANTIC_BASEVERTEX
;
5613 case SYSTEM_VALUE_BASE_INSTANCE
:
5614 return TGSI_SEMANTIC_BASEINSTANCE
;
5615 case SYSTEM_VALUE_DRAW_ID
:
5616 return TGSI_SEMANTIC_DRAWID
;
5618 /* Geometry shader */
5619 case SYSTEM_VALUE_INVOCATION_ID
:
5620 return TGSI_SEMANTIC_INVOCATIONID
;
5622 /* Fragment shader */
5623 case SYSTEM_VALUE_FRAG_COORD
:
5624 return TGSI_SEMANTIC_POSITION
;
5625 case SYSTEM_VALUE_FRONT_FACE
:
5626 return TGSI_SEMANTIC_FACE
;
5627 case SYSTEM_VALUE_SAMPLE_ID
:
5628 return TGSI_SEMANTIC_SAMPLEID
;
5629 case SYSTEM_VALUE_SAMPLE_POS
:
5630 return TGSI_SEMANTIC_SAMPLEPOS
;
5631 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5632 return TGSI_SEMANTIC_SAMPLEMASK
;
5633 case SYSTEM_VALUE_HELPER_INVOCATION
:
5634 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5636 /* Tessellation shader */
5637 case SYSTEM_VALUE_TESS_COORD
:
5638 return TGSI_SEMANTIC_TESSCOORD
;
5639 case SYSTEM_VALUE_VERTICES_IN
:
5640 return TGSI_SEMANTIC_VERTICESIN
;
5641 case SYSTEM_VALUE_PRIMITIVE_ID
:
5642 return TGSI_SEMANTIC_PRIMID
;
5643 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5644 return TGSI_SEMANTIC_TESSOUTER
;
5645 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5646 return TGSI_SEMANTIC_TESSINNER
;
5648 /* Compute shader */
5649 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5650 return TGSI_SEMANTIC_THREAD_ID
;
5651 case SYSTEM_VALUE_WORK_GROUP_ID
:
5652 return TGSI_SEMANTIC_BLOCK_ID
;
5653 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5654 return TGSI_SEMANTIC_GRID_SIZE
;
5655 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5656 return TGSI_SEMANTIC_BLOCK_SIZE
;
5658 /* ARB_shader_ballot */
5659 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5660 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5661 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5662 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5663 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5664 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5665 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5666 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5667 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5668 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5669 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5670 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5671 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5672 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5675 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5676 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5677 case SYSTEM_VALUE_VERTEX_CNT
:
5679 assert(!"Unexpected SYSTEM_VALUE_ enum");
5680 return TGSI_SEMANTIC_COUNT
;
5685 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5687 static struct ureg_src
5688 emit_immediate(struct st_translate
*t
,
5689 gl_constant_value values
[4],
5690 GLenum type
, int size
)
5692 struct ureg_program
*ureg
= t
->ureg
;
5696 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5698 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5700 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5701 case GL_UNSIGNED_INT64_ARB
:
5702 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5704 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5705 case GL_UNSIGNED_INT
:
5707 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5709 assert(!"should not get here - type must be float, int, uint, or bool");
5710 return ureg_src_undef();
5715 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5717 static struct ureg_dst
5718 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5724 case PROGRAM_UNDEFINED
:
5725 return ureg_dst_undef();
5727 case PROGRAM_TEMPORARY
:
5728 /* Allocate space for temporaries on demand. */
5729 if (index
>= t
->temps_size
) {
5730 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5732 t
->temps
= (struct ureg_dst
*)
5734 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5736 return ureg_dst_undef();
5738 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5739 t
->temps_size
+= inc
;
5742 if (ureg_dst_is_undef(t
->temps
[index
]))
5743 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5745 return t
->temps
[index
];
5748 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5749 array
= array_id
- 1;
5751 if (ureg_dst_is_undef(t
->arrays
[array
]))
5752 t
->arrays
[array
] = ureg_DECL_array_temporary(
5753 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5755 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5757 case PROGRAM_OUTPUT
:
5759 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5760 assert(index
< 2 * FRAG_RESULT_MAX
);
5761 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5762 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5763 assert(index
< VARYING_SLOT_TESS_MAX
);
5765 assert(index
< VARYING_SLOT_MAX
);
5767 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5768 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5769 return t
->outputs
[t
->outputMapping
[index
]];
5772 struct inout_decl
*decl
=
5773 find_inout_array(t
->output_decls
,
5774 t
->num_output_decls
, array_id
);
5775 unsigned mesa_index
= decl
->mesa_index
;
5776 int slot
= t
->outputMapping
[mesa_index
];
5778 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5780 struct ureg_dst dst
= t
->outputs
[slot
];
5781 dst
.ArrayID
= array_id
;
5782 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5785 case PROGRAM_ADDRESS
:
5786 return t
->address
[index
];
5789 assert(!"unknown dst register file");
5790 return ureg_dst_undef();
5794 static struct ureg_src
5795 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5797 static struct ureg_src
5798 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5799 unsigned addr_index
)
5801 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5802 return ureg_src(t
->address
[addr_index
]);
5804 return translate_src(t
, reladdr
);
5808 * Create a TGSI ureg_dst register from an st_dst_reg.
5810 static struct ureg_dst
5811 translate_dst(struct st_translate
*t
,
5812 const st_dst_reg
*dst_reg
,
5815 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5818 if (dst
.File
== TGSI_FILE_NULL
)
5821 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5824 dst
= ureg_saturate(dst
);
5826 if (dst_reg
->reladdr
!= NULL
) {
5827 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5828 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5831 if (dst_reg
->has_index2
) {
5832 if (dst_reg
->reladdr2
)
5833 dst
= ureg_dst_dimension_indirect(dst
,
5834 translate_addr(t
, dst_reg
->reladdr2
, 1),
5837 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5844 * Create a TGSI ureg_src register from an st_src_reg.
5846 static struct ureg_src
5847 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5849 struct ureg_src src
;
5850 int index
= src_reg
->index
;
5851 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5853 switch (src_reg
->file
) {
5854 case PROGRAM_UNDEFINED
:
5855 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5858 case PROGRAM_TEMPORARY
:
5860 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
5861 src_reg
->array_id
));
5864 case PROGRAM_OUTPUT
: {
5865 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
5867 assert(dst
.WriteMask
!= 0);
5868 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5869 src
= ureg_swizzle(ureg_src(dst
),
5873 MIN2(shift
+ 3, 3));
5877 case PROGRAM_UNIFORM
:
5878 assert(src_reg
->index
>= 0);
5879 src
= src_reg
->index
< t
->num_constants
?
5880 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5882 case PROGRAM_STATE_VAR
:
5883 case PROGRAM_CONSTANT
: /* ie, immediate */
5884 if (src_reg
->has_index2
)
5885 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5887 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5888 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5891 case PROGRAM_IMMEDIATE
:
5892 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5893 src
= t
->immediates
[src_reg
->index
];
5897 /* GLSL inputs are 64-bit containers, so we have to
5898 * map back to the original index and add the offset after
5900 index
-= double_reg2
;
5901 if (!src_reg
->array_id
) {
5902 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5903 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5904 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5907 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
5910 unsigned mesa_index
= decl
->mesa_index
;
5911 int slot
= t
->inputMapping
[mesa_index
];
5913 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5915 src
= t
->inputs
[slot
];
5916 src
.ArrayID
= src_reg
->array_id
;
5917 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5921 case PROGRAM_ADDRESS
:
5922 src
= ureg_src(t
->address
[src_reg
->index
]);
5925 case PROGRAM_SYSTEM_VALUE
:
5926 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5927 src
= t
->systemValues
[src_reg
->index
];
5930 case PROGRAM_HW_ATOMIC
:
5931 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
5936 assert(!"unknown src register file");
5937 return ureg_src_undef();
5940 if (src_reg
->has_index2
) {
5941 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5942 * and UBO constant buffers (buffer, position).
5944 if (src_reg
->reladdr2
)
5945 src
= ureg_src_dimension_indirect(src
,
5946 translate_addr(t
, src_reg
->reladdr2
, 1),
5949 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5952 src
= ureg_swizzle(src
,
5953 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5954 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5955 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5956 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5959 src
= ureg_abs(src
);
5961 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5962 src
= ureg_negate(src
);
5964 if (src_reg
->reladdr
!= NULL
) {
5965 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5966 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5972 static struct tgsi_texture_offset
5973 translate_tex_offset(struct st_translate
*t
,
5974 const st_src_reg
*in_offset
)
5976 struct tgsi_texture_offset offset
;
5977 struct ureg_src src
= translate_src(t
, in_offset
);
5979 offset
.File
= src
.File
;
5980 offset
.Index
= src
.Index
;
5981 offset
.SwizzleX
= src
.SwizzleX
;
5982 offset
.SwizzleY
= src
.SwizzleY
;
5983 offset
.SwizzleZ
= src
.SwizzleZ
;
5986 assert(!src
.Indirect
);
5987 assert(!src
.DimIndirect
);
5988 assert(!src
.Dimension
);
5989 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5990 assert(!src
.Negate
);
5996 compile_tgsi_instruction(struct st_translate
*t
,
5997 const glsl_to_tgsi_instruction
*inst
)
5999 struct ureg_program
*ureg
= t
->ureg
;
6001 struct ureg_dst dst
[2];
6002 struct ureg_src src
[4];
6003 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
6007 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
6009 num_dst
= num_inst_dst_regs(inst
);
6010 num_src
= num_inst_src_regs(inst
);
6012 for (i
= 0; i
< num_dst
; i
++)
6013 dst
[i
] = translate_dst(t
,
6017 for (i
= 0; i
< num_src
; i
++)
6018 src
[i
] = translate_src(t
, &inst
->src
[i
]);
6021 case TGSI_OPCODE_BGNLOOP
:
6022 case TGSI_OPCODE_ELSE
:
6023 case TGSI_OPCODE_ENDLOOP
:
6024 case TGSI_OPCODE_IF
:
6025 case TGSI_OPCODE_UIF
:
6026 assert(num_dst
== 0);
6027 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
6030 case TGSI_OPCODE_TEX
:
6031 case TGSI_OPCODE_TEX_LZ
:
6032 case TGSI_OPCODE_TXB
:
6033 case TGSI_OPCODE_TXD
:
6034 case TGSI_OPCODE_TXL
:
6035 case TGSI_OPCODE_TXP
:
6036 case TGSI_OPCODE_TXQ
:
6037 case TGSI_OPCODE_TXQS
:
6038 case TGSI_OPCODE_TXF
:
6039 case TGSI_OPCODE_TXF_LZ
:
6040 case TGSI_OPCODE_TEX2
:
6041 case TGSI_OPCODE_TXB2
:
6042 case TGSI_OPCODE_TXL2
:
6043 case TGSI_OPCODE_TG4
:
6044 case TGSI_OPCODE_LODQ
:
6045 case TGSI_OPCODE_SAMP2HND
:
6046 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
6047 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
6049 /* Bindless samplers. */
6050 src
[num_src
] = translate_src(t
, &inst
->resource
);
6052 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
6053 if (inst
->resource
.reladdr
)
6055 ureg_src_indirect(src
[num_src
],
6056 translate_addr(t
, inst
->resource
.reladdr
, 2));
6058 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
6059 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
6061 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6067 st_translate_texture_type(inst
->tex_type
),
6068 texoffsets
, inst
->tex_offset_num_offset
,
6072 case TGSI_OPCODE_RESQ
:
6073 case TGSI_OPCODE_LOAD
:
6074 case TGSI_OPCODE_ATOMUADD
:
6075 case TGSI_OPCODE_ATOMXCHG
:
6076 case TGSI_OPCODE_ATOMCAS
:
6077 case TGSI_OPCODE_ATOMAND
:
6078 case TGSI_OPCODE_ATOMOR
:
6079 case TGSI_OPCODE_ATOMXOR
:
6080 case TGSI_OPCODE_ATOMUMIN
:
6081 case TGSI_OPCODE_ATOMUMAX
:
6082 case TGSI_OPCODE_ATOMIMIN
:
6083 case TGSI_OPCODE_ATOMIMAX
:
6084 case TGSI_OPCODE_IMG2HND
:
6085 for (i
= num_src
- 1; i
>= 0; i
--)
6086 src
[i
+ 1] = src
[i
];
6088 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6089 src
[0] = t
->shared_memory
;
6090 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6091 src
[0] = t
->buffers
[inst
->resource
.index
];
6092 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6093 src
[0] = translate_src(t
, &inst
->resource
);
6094 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6095 assert(inst
->resource
.has_index2
);
6096 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6098 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6099 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6100 src
[0] = t
->images
[inst
->resource
.index
];
6102 /* Bindless images. */
6103 src
[0] = translate_src(t
, &inst
->resource
);
6105 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6107 if (inst
->resource
.reladdr
)
6108 src
[0] = ureg_src_indirect(src
[0],
6109 translate_addr(t
, inst
->resource
.reladdr
, 2));
6110 assert(src
[0].File
!= TGSI_FILE_NULL
);
6111 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6112 inst
->buffer_access
,
6113 tex_target
, inst
->image_format
);
6116 case TGSI_OPCODE_STORE
:
6117 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6118 dst
[0] = ureg_dst(t
->shared_memory
);
6119 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6120 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6122 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6123 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6125 /* Bindless images. */
6126 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6128 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6130 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6131 if (inst
->resource
.reladdr
)
6132 dst
[0] = ureg_dst_indirect(dst
[0],
6133 translate_addr(t
, inst
->resource
.reladdr
, 2));
6134 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6135 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6136 inst
->buffer_access
,
6137 tex_target
, inst
->image_format
);
6144 src
, num_src
, inst
->precise
);
6150 * Emit the TGSI instructions for inverting and adjusting WPOS.
6151 * This code is unavoidable because it also depends on whether
6152 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6155 emit_wpos_adjustment(struct gl_context
*ctx
,
6156 struct st_translate
*t
,
6157 int wpos_transform_const
,
6159 GLfloat adjX
, GLfloat adjY
[2])
6161 struct ureg_program
*ureg
= t
->ureg
;
6163 assert(wpos_transform_const
>= 0);
6165 /* Fragment program uses fragment position input.
6166 * Need to replace instances of INPUT[WPOS] with temp T
6167 * where T = INPUT[WPOS] is inverted by Y.
6169 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6170 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6171 struct ureg_src
*wpos
=
6172 ctx
->Const
.GLSLFragCoordIsSysVal
?
6173 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6174 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6175 struct ureg_src wpos_input
= *wpos
;
6177 /* First, apply the coordinate shift: */
6178 if (adjX
|| adjY
[0] || adjY
[1]) {
6179 if (adjY
[0] != adjY
[1]) {
6180 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6181 * depending on whether inversion is actually going to be applied
6182 * or not, which is determined by testing against the inversion
6183 * state variable used below, which will be either +1 or -1.
6185 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6187 ureg_CMP(ureg
, adj_temp
,
6188 ureg_scalar(wpostrans
, invert
? 2 : 0),
6189 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6190 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6191 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6193 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6194 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6196 wpos_input
= ureg_src(wpos_temp
);
6198 /* MOV wpos_temp, input[wpos]
6200 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6203 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6204 * inversion/identity, or the other way around if we're drawing to an FBO.
6207 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6210 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6212 ureg_scalar(wpostrans
, 0),
6213 ureg_scalar(wpostrans
, 1));
6215 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6218 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6220 ureg_scalar(wpostrans
, 2),
6221 ureg_scalar(wpostrans
, 3));
6224 /* Use wpos_temp as position input from here on:
6226 *wpos
= ureg_src(wpos_temp
);
6231 * Emit fragment position/ooordinate code.
6234 emit_wpos(struct st_context
*st
,
6235 struct st_translate
*t
,
6236 const struct gl_program
*program
,
6237 struct ureg_program
*ureg
,
6238 int wpos_transform_const
)
6240 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6241 GLfloat adjX
= 0.0f
;
6242 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6243 boolean invert
= FALSE
;
6245 /* Query the pixel center conventions supported by the pipe driver and set
6246 * adjX, adjY to help out if it cannot handle the requested one internally.
6248 * The bias of the y-coordinate depends on whether y-inversion takes place
6249 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6250 * drawing to an FBO (causes additional inversion), and whether the pipe
6251 * driver origin and the requested origin differ (the latter condition is
6252 * stored in the 'invert' variable).
6254 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6256 * center shift only:
6261 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6262 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6263 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6264 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6266 * inversion and center shift:
6267 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6268 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6269 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6270 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6272 if (program
->OriginUpperLeft
) {
6273 /* Fragment shader wants origin in upper-left */
6274 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6275 /* the driver supports upper-left origin */
6277 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6278 /* the driver supports lower-left origin, need to invert Y */
6279 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6280 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6287 /* Fragment shader wants origin in lower-left */
6288 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6289 /* the driver supports lower-left origin */
6290 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6291 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6292 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6293 /* the driver supports upper-left origin, need to invert Y */
6299 if (program
->PixelCenterInteger
) {
6300 /* Fragment shader wants pixel center integer */
6301 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6302 /* the driver supports pixel center integer */
6304 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6305 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6307 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6308 /* the driver supports pixel center half integer, need to bias X,Y */
6317 /* Fragment shader wants pixel center half integer */
6318 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6319 /* the driver supports pixel center half integer */
6321 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6322 /* the driver supports pixel center integer, need to bias X,Y */
6323 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6324 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6325 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6331 /* we invert after adjustment so that we avoid the MOV to temporary,
6332 * and reuse the adjustment ADD instead */
6333 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6337 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6338 * TGSI uses +1 for front, -1 for back.
6339 * This function converts the TGSI value to the GL value. Simply clamping/
6340 * saturating the value to [0,1] does the job.
6343 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6345 struct ureg_program
*ureg
= t
->ureg
;
6346 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6347 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6349 if (ctx
->Const
.NativeIntegers
) {
6350 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6353 /* MOV_SAT face_temp, input[face] */
6354 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6357 /* Use face_temp as face input from here on: */
6358 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6362 emit_compute_block_size(const struct gl_program
*prog
,
6363 struct ureg_program
*ureg
) {
6364 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6365 prog
->info
.cs
.local_size
[0]);
6366 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6367 prog
->info
.cs
.local_size
[1]);
6368 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6369 prog
->info
.cs
.local_size
[2]);
6372 struct sort_inout_decls
{
6373 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6374 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6377 const ubyte
*mapping
;
6380 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6382 * This is for the benefit of older drivers which are broken when the
6383 * declarations aren't sorted in this way.
6386 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6388 const ubyte mapping
[])
6390 sort_inout_decls sorter
;
6391 sorter
.mapping
= mapping
;
6392 std::sort(decls
, decls
+ count
, sorter
);
6395 static enum tgsi_interpolate_mode
6396 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6398 switch (glsl_qual
) {
6399 case INTERP_MODE_NONE
:
6400 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6401 return TGSI_INTERPOLATE_COLOR
;
6402 return TGSI_INTERPOLATE_PERSPECTIVE
;
6403 case INTERP_MODE_SMOOTH
:
6404 return TGSI_INTERPOLATE_PERSPECTIVE
;
6405 case INTERP_MODE_FLAT
:
6406 return TGSI_INTERPOLATE_CONSTANT
;
6407 case INTERP_MODE_NOPERSPECTIVE
:
6408 return TGSI_INTERPOLATE_LINEAR
;
6410 assert(0 && "unexpected interp mode in st_translate_interp()");
6411 return TGSI_INTERPOLATE_PERSPECTIVE
;
6416 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6417 * \param program the program to translate
6418 * \param numInputs number of input registers used
6419 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6421 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6422 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6424 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6425 * \param numOutputs number of output registers used
6426 * \param outputMapping maps Mesa fragment program outputs to TGSI
6428 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6429 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6432 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6434 extern "C" enum pipe_error
6435 st_translate_program(
6436 struct gl_context
*ctx
,
6437 enum pipe_shader_type procType
,
6438 struct ureg_program
*ureg
,
6439 glsl_to_tgsi_visitor
*program
,
6440 const struct gl_program
*proginfo
,
6442 const ubyte inputMapping
[],
6443 const ubyte inputSlotToAttr
[],
6444 const ubyte inputSemanticName
[],
6445 const ubyte inputSemanticIndex
[],
6446 const ubyte interpMode
[],
6448 const ubyte outputMapping
[],
6449 const ubyte outputSemanticName
[],
6450 const ubyte outputSemanticIndex
[])
6452 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6453 struct st_translate
*t
;
6455 struct gl_program_constants
*frag_const
=
6456 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6457 enum pipe_error ret
= PIPE_OK
;
6459 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6460 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6462 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6463 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6464 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6465 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6466 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6467 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6468 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6469 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6470 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6471 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6473 t
= CALLOC_STRUCT(st_translate
);
6475 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6479 t
->procType
= procType
;
6480 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6481 t
->inputMapping
= inputMapping
;
6482 t
->outputMapping
= outputMapping
;
6484 t
->num_temp_arrays
= program
->next_array
;
6485 if (t
->num_temp_arrays
)
6486 t
->arrays
= (struct ureg_dst
*)
6487 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6490 * Declare input attributes.
6493 case PIPE_SHADER_FRAGMENT
:
6494 case PIPE_SHADER_GEOMETRY
:
6495 case PIPE_SHADER_TESS_EVAL
:
6496 case PIPE_SHADER_TESS_CTRL
:
6497 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6499 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6500 struct inout_decl
*decl
= &program
->inputs
[i
];
6501 unsigned slot
= inputMapping
[decl
->mesa_index
];
6502 struct ureg_src src
;
6503 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6505 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6506 if (tgsi_usage_mask
== 1)
6507 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6508 else if (tgsi_usage_mask
== 2)
6509 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6511 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6514 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6515 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6516 if (procType
== PIPE_SHADER_FRAGMENT
) {
6518 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6519 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6520 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6522 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6525 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6526 (enum tgsi_semantic
) inputSemanticName
[slot
],
6527 inputSemanticIndex
[slot
],
6528 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6529 decl
->array_id
, decl
->size
);
6531 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6532 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6533 /* The ArrayID is set up in dst_register */
6534 t
->inputs
[slot
+ j
] = src
;
6535 t
->inputs
[slot
+ j
].ArrayID
= 0;
6536 t
->inputs
[slot
+ j
].Index
+= j
;
6541 case PIPE_SHADER_VERTEX
:
6542 for (i
= 0; i
< numInputs
; i
++) {
6543 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6546 case PIPE_SHADER_COMPUTE
:
6553 * Declare output attributes.
6556 case PIPE_SHADER_FRAGMENT
:
6557 case PIPE_SHADER_COMPUTE
:
6559 case PIPE_SHADER_GEOMETRY
:
6560 case PIPE_SHADER_TESS_EVAL
:
6561 case PIPE_SHADER_TESS_CTRL
:
6562 case PIPE_SHADER_VERTEX
:
6563 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6565 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6566 struct inout_decl
*decl
= &program
->outputs
[i
];
6567 unsigned slot
= outputMapping
[decl
->mesa_index
];
6568 struct ureg_dst dst
;
6569 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6571 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6572 if (tgsi_usage_mask
== 1)
6573 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6574 else if (tgsi_usage_mask
== 2)
6575 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6577 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6580 dst
= ureg_DECL_output_layout(ureg
,
6581 (enum tgsi_semantic
) outputSemanticName
[slot
],
6582 outputSemanticIndex
[slot
],
6583 decl
->gs_out_streams
,
6584 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6585 dst
.Invariant
= decl
->invariant
;
6586 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6587 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6588 /* The ArrayID is set up in dst_register */
6589 t
->outputs
[slot
+ j
] = dst
;
6590 t
->outputs
[slot
+ j
].ArrayID
= 0;
6591 t
->outputs
[slot
+ j
].Index
+= j
;
6592 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6601 if (procType
== PIPE_SHADER_FRAGMENT
) {
6602 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6603 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6604 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6606 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6607 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6610 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6611 /* Must do this after setting up t->inputs. */
6612 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6613 program
->wpos_transform_const
);
6616 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6617 emit_face_var(ctx
, t
);
6619 for (i
= 0; i
< numOutputs
; i
++) {
6620 switch (outputSemanticName
[i
]) {
6621 case TGSI_SEMANTIC_POSITION
:
6622 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6623 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6624 outputSemanticIndex
[i
]);
6625 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6627 case TGSI_SEMANTIC_STENCIL
:
6628 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6629 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6630 outputSemanticIndex
[i
]);
6631 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6633 case TGSI_SEMANTIC_COLOR
:
6634 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6635 TGSI_SEMANTIC_COLOR
,
6636 outputSemanticIndex
[i
]);
6638 case TGSI_SEMANTIC_SAMPLEMASK
:
6639 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6640 TGSI_SEMANTIC_SAMPLEMASK
,
6641 outputSemanticIndex
[i
]);
6642 /* TODO: If we ever support more than 32 samples, this will have
6643 * to become an array.
6645 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6648 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6649 ret
= PIPE_ERROR_BAD_INPUT
;
6654 else if (procType
== PIPE_SHADER_VERTEX
) {
6655 for (i
= 0; i
< numOutputs
; i
++) {
6656 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6657 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6659 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6660 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6661 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6666 if (procType
== PIPE_SHADER_COMPUTE
) {
6667 emit_compute_block_size(proginfo
, ureg
);
6670 /* Declare address register.
6672 if (program
->num_address_regs
> 0) {
6673 assert(program
->num_address_regs
<= 3);
6674 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6675 t
->address
[i
] = ureg_DECL_address(ureg
);
6678 /* Declare misc input registers
6681 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6683 for (i
= 0; sysInputs
; i
++) {
6684 if (sysInputs
& (1ull << i
)) {
6685 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6687 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6689 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6690 semName
== TGSI_SEMANTIC_VERTEXID
) {
6691 /* From Gallium perspective, these system values are always
6692 * integer, and require native integer support. However, if
6693 * native integer is supported on the vertex stage but not the
6694 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6695 * assumes these system values are floats. To resolve the
6696 * inconsistency, we insert a U2F.
6698 struct st_context
*st
= st_context(ctx
);
6699 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6700 assert(procType
== PIPE_SHADER_VERTEX
);
6701 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6703 if (!ctx
->Const
.NativeIntegers
) {
6704 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6705 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6706 t
->systemValues
[i
]);
6707 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6711 if (procType
== PIPE_SHADER_FRAGMENT
&&
6712 semName
== TGSI_SEMANTIC_POSITION
)
6713 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6714 program
->wpos_transform_const
);
6716 sysInputs
&= ~(1ull << i
);
6721 t
->array_sizes
= program
->array_sizes
;
6722 t
->input_decls
= program
->inputs
;
6723 t
->num_input_decls
= program
->num_inputs
;
6724 t
->output_decls
= program
->outputs
;
6725 t
->num_output_decls
= program
->num_outputs
;
6727 /* Emit constants and uniforms. TGSI uses a single index space for these,
6728 * so we put all the translated regs in t->constants.
6730 if (proginfo
->Parameters
) {
6731 t
->constants
= (struct ureg_src
*)
6732 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6733 if (t
->constants
== NULL
) {
6734 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6737 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6739 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6740 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6742 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6743 case PROGRAM_STATE_VAR
:
6744 case PROGRAM_UNIFORM
:
6745 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6748 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6749 * addressing of the const buffer.
6750 * FIXME: Be smarter and recognize param arrays:
6751 * indirect addressing is only valid within the referenced
6754 case PROGRAM_CONSTANT
:
6755 if (program
->indirect_addr_consts
)
6756 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6758 t
->constants
[i
] = emit_immediate(t
,
6759 proginfo
->Parameters
->ParameterValues
+ pvo
,
6760 proginfo
->Parameters
->Parameters
[i
].DataType
,
6769 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6770 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6771 unsigned num_const_vecs
= (size
+ 15) / 16;
6772 unsigned first
, last
;
6773 assert(num_const_vecs
> 0);
6775 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6776 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6779 /* Emit immediate values.
6781 t
->immediates
= (struct ureg_src
*)
6782 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6783 if (t
->immediates
== NULL
) {
6784 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6787 t
->num_immediates
= program
->num_immediates
;
6790 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6791 assert(i
< program
->num_immediates
);
6792 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6794 assert(i
== program
->num_immediates
);
6796 /* texture samplers */
6797 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6798 if (program
->samplers_used
& (1u << i
)) {
6799 enum tgsi_return_type type
=
6800 st_translate_texture_type(program
->sampler_types
[i
]);
6802 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6804 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
6805 type
, type
, type
, type
);
6809 /* Declare atomic and shader storage buffers. */
6811 struct gl_program
*prog
= program
->prog
;
6813 if (!st_context(ctx
)->has_hw_atomics
) {
6814 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6815 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6816 assert(index
< frag_const
->MaxAtomicBuffers
);
6817 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6820 for (i
= 0; i
< program
->num_atomics
; i
++) {
6821 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
6822 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
6823 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
6824 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
6829 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6830 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6832 if (!st_context(ctx
)->has_hw_atomics
)
6833 index
+= frag_const
->MaxAtomicBuffers
;
6835 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6839 if (program
->use_shared_memory
)
6840 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6842 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6843 if (program
->images_used
& (1 << i
)) {
6844 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6845 program
->image_targets
[i
],
6846 program
->image_formats
[i
],
6847 program
->image_wr
[i
],
6852 /* Emit each instruction in turn:
6854 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6855 compile_tgsi_instruction(t
, inst
);
6857 /* Set the next shader stage hint for VS and TES. */
6859 case PIPE_SHADER_VERTEX
:
6860 case PIPE_SHADER_TESS_EVAL
:
6861 if (program
->shader_program
->SeparateShader
)
6864 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6865 if (program
->shader_program
->_LinkedShaders
[i
]) {
6866 ureg_set_next_shader_processor(
6867 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6873 ; /* nothing - silence compiler warning */
6881 t
->num_constants
= 0;
6882 free(t
->immediates
);
6883 t
->num_immediates
= 0;
6889 /* ----------------------------- End TGSI code ------------------------------ */
6893 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6894 * generating Mesa IR.
6896 static struct gl_program
*
6897 get_mesa_program_tgsi(struct gl_context
*ctx
,
6898 struct gl_shader_program
*shader_program
,
6899 struct gl_linked_shader
*shader
)
6901 glsl_to_tgsi_visitor
* v
;
6902 struct gl_program
*prog
;
6903 struct gl_shader_compiler_options
*options
=
6904 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6905 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6906 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6907 unsigned skip_merge_registers
;
6909 validate_ir_tree(shader
->ir
);
6911 prog
= shader
->Program
;
6913 prog
->Parameters
= _mesa_new_parameter_list();
6914 v
= new glsl_to_tgsi_visitor();
6917 v
->shader_program
= shader_program
;
6919 v
->options
= options
;
6920 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6922 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6923 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6924 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6925 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6926 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6927 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6928 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6930 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6931 _mesa_key_pointer_equal
);
6932 skip_merge_registers
=
6933 pscreen
->get_shader_param(pscreen
, ptarget
,
6934 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6936 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6939 /* Remove reads from output registers. */
6940 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6941 lower_output_reads(shader
->Stage
, shader
->ir
);
6943 /* Emit intermediate IR for main(). */
6944 visit_exec_list(shader
->ir
, v
);
6947 /* Print out some information (for debugging purposes) used by the
6948 * optimization passes. */
6951 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6952 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6953 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6954 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6956 for (i
= 0; i
< v
->next_temp
; i
++) {
6957 first_writes
[i
] = -1;
6958 first_reads
[i
] = -1;
6959 last_writes
[i
] = -1;
6962 v
->get_first_temp_read(first_reads
);
6963 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6964 v
->get_last_temp_write(last_writes
);
6965 for (i
= 0; i
< v
->next_temp
; i
++)
6966 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6970 ralloc_free(first_writes
);
6971 ralloc_free(first_reads
);
6972 ralloc_free(last_writes
);
6973 ralloc_free(last_reads
);
6977 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6979 v
->copy_propagate();
6981 while (v
->eliminate_dead_code());
6983 v
->merge_two_dsts();
6984 if (!skip_merge_registers
)
6985 v
->merge_registers();
6986 v
->renumber_registers();
6988 /* Write the END instruction. */
6989 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6991 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6993 _mesa_log("GLSL IR for linked %s program %d:\n",
6994 _mesa_shader_stage_to_string(shader
->Stage
),
6995 shader_program
->Name
);
6996 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
7000 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
7001 _mesa_copy_linked_program_data(shader_program
, shader
);
7002 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
7003 &prog
->info
.inputs_read
,
7004 prog
->info
.vs
.double_inputs_read
,
7005 &prog
->info
.patch_inputs_read
);
7006 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
7007 &prog
->info
.outputs_written
, 0ULL,
7008 &prog
->info
.patch_outputs_written
);
7009 count_resources(v
, prog
);
7011 /* The GLSL IR won't be needed anymore. */
7012 ralloc_free(shader
->ir
);
7015 /* This must be done before the uniform storage is associated. */
7016 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
7017 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
7018 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
))) {
7019 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
7020 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
7023 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
7024 wposTransformState
);
7027 /* Avoid reallocation of the program parameter list, because the uniform
7028 * storage is only associated with the original parameter list.
7029 * This should be enough for Bitmap and DrawPixels constants.
7031 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
7033 /* This has to be done last. Any operation the can cause
7034 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7035 * program constant) has to happen before creating this linkage.
7037 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
7038 if (!shader_program
->data
->LinkStatus
) {
7039 free_glsl_to_tgsi_visitor(v
);
7040 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7044 struct st_vertex_program
*stvp
;
7045 struct st_fragment_program
*stfp
;
7046 struct st_common_program
*stp
;
7047 struct st_compute_program
*stcp
;
7049 switch (shader
->Stage
) {
7050 case MESA_SHADER_VERTEX
:
7051 stvp
= (struct st_vertex_program
*)prog
;
7052 stvp
->glsl_to_tgsi
= v
;
7054 case MESA_SHADER_FRAGMENT
:
7055 stfp
= (struct st_fragment_program
*)prog
;
7056 stfp
->glsl_to_tgsi
= v
;
7058 case MESA_SHADER_TESS_CTRL
:
7059 case MESA_SHADER_TESS_EVAL
:
7060 case MESA_SHADER_GEOMETRY
:
7061 stp
= st_common_program(prog
);
7062 stp
->glsl_to_tgsi
= v
;
7064 case MESA_SHADER_COMPUTE
:
7065 stcp
= (struct st_compute_program
*)prog
;
7066 stcp
->glsl_to_tgsi
= v
;
7069 assert(!"should not be reached");
7073 PRINT_STATS(v
->print_stats());
7078 /* See if there are unsupported control flow statements. */
7079 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7081 const struct gl_shader_compiler_options
*options
;
7083 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7089 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7091 /* Other functions are skipped (same as glsl_to_tgsi). */
7092 if (strcmp(ir
->name
, "main") == 0)
7093 return visit_continue
;
7095 return visit_continue_with_parent
;
7098 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7100 if (!ir
->callee
->is_intrinsic()) {
7101 unsupported
= true; /* it's a function call */
7104 return visit_continue
;
7107 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7109 if (options
->EmitNoMainReturn
) {
7113 return visit_continue
;
7120 has_unsupported_control_flow(exec_list
*ir
,
7121 const struct gl_shader_compiler_options
*options
)
7123 ir_control_flow_info_visitor
visitor(options
);
7124 visit_list_elements(&visitor
, ir
);
7125 return visitor
.unsupported
;
7132 * Called via ctx->Driver.LinkShader()
7133 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7134 * with code lowering and other optimizations.
7137 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7139 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7141 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7142 pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
,
7143 PIPE_SHADER_CAP_PREFERRED_IR
);
7144 bool use_nir
= preferred_ir
== PIPE_SHADER_IR_NIR
;
7146 /* Return early if we are loading the shader from on-disk cache */
7147 if (st_load_ir_from_disk_cache(ctx
, prog
, use_nir
)) {
7151 assert(prog
->data
->LinkStatus
);
7153 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7154 if (prog
->_LinkedShaders
[i
] == NULL
)
7157 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7158 exec_list
*ir
= shader
->ir
;
7159 gl_shader_stage stage
= shader
->Stage
;
7160 const struct gl_shader_compiler_options
*options
=
7161 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7162 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7163 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7164 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7165 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7166 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7167 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7168 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
7169 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7170 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7172 /* If there are forms of indirect addressing that the driver
7173 * cannot handle, perform the lowering pass.
7175 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7176 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7177 lower_variable_index_to_cond_assign(stage
, ir
,
7178 options
->EmitNoIndirectInput
,
7179 options
->EmitNoIndirectOutput
,
7180 options
->EmitNoIndirectTemp
,
7181 options
->EmitNoIndirectUniform
);
7184 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7185 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7187 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7188 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7189 LOWER_UNPACK_SNORM_2x16
|
7190 LOWER_PACK_UNORM_2x16
|
7191 LOWER_UNPACK_UNORM_2x16
|
7192 LOWER_PACK_SNORM_4x8
|
7193 LOWER_UNPACK_SNORM_4x8
|
7194 LOWER_UNPACK_UNORM_4x8
|
7195 LOWER_PACK_UNORM_4x8
;
7197 if (ctx
->Extensions
.ARB_gpu_shader5
)
7198 lower_inst
|= LOWER_PACK_USE_BFI
|
7200 if (!ctx
->st
->has_half_float_packing
)
7201 lower_inst
|= LOWER_PACK_HALF_2x16
|
7202 LOWER_UNPACK_HALF_2x16
;
7204 lower_packing_builtins(ir
, lower_inst
);
7207 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7208 lower_offset_arrays(ir
);
7209 do_mat_op_to_vec(ir
);
7211 if (stage
== MESA_SHADER_FRAGMENT
)
7212 lower_blend_equation_advanced(
7213 shader
, ctx
->Extensions
.KHR_blend_equation_advanced_coherent
);
7215 lower_instructions(ir
,
7220 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
7221 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7224 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7225 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7226 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7227 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7228 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7229 /* Assume that if ARB_gpu_shader5 is not supported
7230 * then all of the extended integer functions need
7231 * lowering. It may be necessary to add some caps
7232 * for individual instructions.
7234 (!ctx
->Extensions
.ARB_gpu_shader5
7235 ? BIT_COUNT_TO_MATH
|
7239 FIND_LSB_TO_FLOAT_CAST
|
7240 FIND_MSB_TO_FLOAT_CAST
|
7244 do_vec_index_to_cond_assign(ir
);
7245 lower_vector_insert(ir
, true);
7246 lower_quadop_vector(ir
, false);
7248 if (options
->MaxIfDepth
== 0) {
7252 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7253 /* Do it once and repeat only if there's unsupported control flow. */
7255 do_common_optimization(ir
, true, true, options
,
7256 ctx
->Const
.NativeIntegers
);
7257 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7258 options
->MaxIfDepth
, if_threshold
);
7259 } while (has_unsupported_control_flow(ir
, options
));
7261 /* Repeat it until it stops making changes. */
7264 progress
= do_common_optimization(ir
, true, true, options
,
7265 ctx
->Const
.NativeIntegers
);
7266 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7267 options
->MaxIfDepth
, if_threshold
);
7271 /* Do this again to lower ir_binop_vector_extract introduced
7272 * by optimization passes.
7274 do_vec_index_to_cond_assign(ir
);
7276 validate_ir_tree(ir
);
7279 build_program_resource_list(ctx
, prog
);
7282 return st_link_nir(ctx
, prog
);
7284 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7285 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7289 struct gl_program
*linked_prog
=
7290 get_mesa_program_tgsi(ctx
, prog
, shader
);
7291 st_set_prog_affected_state_flags(linked_prog
);
7294 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7295 _mesa_shader_stage_to_program(i
),
7297 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7307 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7308 const ubyte outputMapping
[],
7309 struct pipe_stream_output_info
*so
)
7311 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7314 struct gl_transform_feedback_info
*info
=
7315 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7316 st_translate_stream_output_info2(info
, outputMapping
, so
);
7320 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7321 const ubyte outputMapping
[],
7322 struct pipe_stream_output_info
*so
)
7326 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7327 so
->output
[i
].register_index
=
7328 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7329 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7330 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7331 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7332 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7333 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7336 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7337 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7339 so
->num_outputs
= info
->NumOutputs
;