2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static int swizzle_for_size(int size
);
71 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
73 unsigned num_elements
= 4;
76 type
= type
->without_array();
77 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
78 num_elements
= type
->vector_elements
;
81 int swizzle
= swizzle_for_size(num_elements
);
82 assert(num_elements
+ component
<= 4);
84 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
89 * This struct is a corresponding struct to TGSI ureg_src.
93 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
94 int component
= 0, unsigned array_id
= 0)
96 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
99 this->swizzle
= swizzle_for_type(type
, component
);
102 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
103 this->reladdr
= NULL
;
104 this->reladdr2
= NULL
;
105 this->has_index2
= false;
106 this->double_reg2
= false;
107 this->array_id
= array_id
;
108 this->is_double_vertex_input
= false;
111 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
113 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
118 this->swizzle
= SWIZZLE_XYZW
;
120 this->reladdr
= NULL
;
121 this->reladdr2
= NULL
;
122 this->has_index2
= false;
123 this->double_reg2
= false;
125 this->is_double_vertex_input
= false;
128 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
130 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
134 this->index2D
= index2D
;
135 this->swizzle
= SWIZZLE_XYZW
;
137 this->reladdr
= NULL
;
138 this->reladdr2
= NULL
;
139 this->has_index2
= false;
140 this->double_reg2
= false;
142 this->is_double_vertex_input
= false;
147 this->type
= GLSL_TYPE_ERROR
;
148 this->file
= PROGRAM_UNDEFINED
;
153 this->reladdr
= NULL
;
154 this->reladdr2
= NULL
;
155 this->has_index2
= false;
156 this->double_reg2
= false;
158 this->is_double_vertex_input
= false;
161 explicit st_src_reg(st_dst_reg reg
);
163 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
165 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
166 int negate
:4; /**< NEGATE_XYZW mask from mesa */
167 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
168 unsigned has_index2
:1;
169 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
171 * Is this the second half of a double register pair?
172 * currently used for input mapping only.
174 unsigned double_reg2
:1;
175 unsigned is_double_vertex_input
:1;
176 unsigned array_id
:10;
178 /** Register index should be offset by the integer in this reg. */
180 st_src_reg
*reladdr2
;
185 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
187 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
191 this->writemask
= writemask
;
192 this->reladdr
= NULL
;
193 this->reladdr2
= NULL
;
194 this->has_index2
= false;
199 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
201 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
205 this->writemask
= writemask
;
206 this->reladdr
= NULL
;
207 this->reladdr2
= NULL
;
208 this->has_index2
= false;
215 this->type
= GLSL_TYPE_ERROR
;
216 this->file
= PROGRAM_UNDEFINED
;
220 this->reladdr
= NULL
;
221 this->reladdr2
= NULL
;
222 this->has_index2
= false;
226 explicit st_dst_reg(st_src_reg reg
);
228 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
230 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
231 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
232 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
233 unsigned has_index2
:1;
234 unsigned array_id
:10;
236 /** Register index should be offset by the integer in this reg. */
238 st_src_reg
*reladdr2
;
241 st_src_reg::st_src_reg(st_dst_reg reg
)
243 this->type
= reg
.type
;
244 this->file
= reg
.file
;
245 this->index
= reg
.index
;
246 this->swizzle
= SWIZZLE_XYZW
;
248 this->reladdr
= reg
.reladdr
;
249 this->index2D
= reg
.index2D
;
250 this->reladdr2
= reg
.reladdr2
;
251 this->has_index2
= reg
.has_index2
;
252 this->double_reg2
= false;
253 this->array_id
= reg
.array_id
;
254 this->is_double_vertex_input
= false;
257 st_dst_reg::st_dst_reg(st_src_reg reg
)
259 this->type
= reg
.type
;
260 this->file
= reg
.file
;
261 this->index
= reg
.index
;
262 this->writemask
= WRITEMASK_XYZW
;
263 this->reladdr
= reg
.reladdr
;
264 this->index2D
= reg
.index2D
;
265 this->reladdr2
= reg
.reladdr2
;
266 this->has_index2
= reg
.has_index2
;
267 this->array_id
= reg
.array_id
;
270 class glsl_to_tgsi_instruction
: public exec_node
{
272 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
276 st_src_reg resource
; /**< sampler or buffer register */
277 st_src_reg
*tex_offsets
;
279 /** Pointer to the ir source this tree came from for debugging */
282 unsigned op
:8; /**< TGSI opcode */
284 unsigned is_64bit_expanded
:1;
285 unsigned sampler_base
:5;
286 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
287 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
288 glsl_base_type tex_type
:4;
289 unsigned tex_shadow
:1;
290 unsigned image_format
:9;
291 unsigned tex_offset_num_offset
:3;
292 unsigned dead_mask
:4; /**< Used in dead code elimination */
293 unsigned buffer_access
:3; /**< buffer access type */
295 const struct tgsi_opcode_info
*info
;
298 class variable_storage
: public exec_node
{
300 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
301 unsigned array_id
= 0)
302 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
304 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
307 gl_register_file file
;
310 /* Explicit component location. This is given in terms of the GLSL-style
311 * swizzles where each double is a single component, i.e. for 64-bit types
312 * it can only be 0 or 1.
315 ir_variable
*var
; /* variable that maps to this, if any */
319 class immediate_storage
: public exec_node
{
321 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
323 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
324 this->size32
= size32
;
328 /* doubles are stored across 2 gl_constant_values */
329 gl_constant_value values
[4];
330 int size32
; /**< Number of 32-bit components (1-4) */
331 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
334 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
335 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
339 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
342 unsigned gs_out_streams
;
343 enum glsl_interp_mode interp
;
344 enum glsl_base_type base_type
;
345 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
348 static struct inout_decl
*
349 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
351 assert(array_id
!= 0);
353 for (unsigned i
= 0; i
< count
; i
++) {
354 struct inout_decl
*decl
= &decls
[i
];
356 if (array_id
== decl
->array_id
) {
364 static enum glsl_base_type
365 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
368 return GLSL_TYPE_ERROR
;
369 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
371 return decl
->base_type
;
372 return GLSL_TYPE_ERROR
;
375 struct rename_reg_pair
{
380 struct glsl_to_tgsi_visitor
: public ir_visitor
{
382 glsl_to_tgsi_visitor();
383 ~glsl_to_tgsi_visitor();
385 struct gl_context
*ctx
;
386 struct gl_program
*prog
;
387 struct gl_shader_program
*shader_program
;
388 struct gl_linked_shader
*shader
;
389 struct gl_shader_compiler_options
*options
;
393 unsigned *array_sizes
;
394 unsigned max_num_arrays
;
397 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
399 unsigned num_input_arrays
;
400 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
401 unsigned num_outputs
;
402 unsigned num_output_arrays
;
404 int num_address_regs
;
405 uint32_t samplers_used
;
406 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
407 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
410 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
411 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
412 bool indirect_addr_consts
;
413 int wpos_transform_const
;
416 bool native_integers
;
419 bool use_shared_memory
;
421 variable_storage
*find_variable_storage(ir_variable
*var
);
423 int add_constant(gl_register_file file
, gl_constant_value values
[8],
424 int size
, int datatype
, uint16_t *swizzle_out
);
426 st_src_reg
get_temp(const glsl_type
*type
);
427 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
429 st_src_reg
st_src_reg_for_double(double val
);
430 st_src_reg
st_src_reg_for_float(float val
);
431 st_src_reg
st_src_reg_for_int(int val
);
432 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
435 * \name Visit methods
437 * As typical for the visitor pattern, there must be one \c visit method for
438 * each concrete subclass of \c ir_instruction. Virtual base classes within
439 * the hierarchy should not have \c visit methods.
442 virtual void visit(ir_variable
*);
443 virtual void visit(ir_loop
*);
444 virtual void visit(ir_loop_jump
*);
445 virtual void visit(ir_function_signature
*);
446 virtual void visit(ir_function
*);
447 virtual void visit(ir_expression
*);
448 virtual void visit(ir_swizzle
*);
449 virtual void visit(ir_dereference_variable
*);
450 virtual void visit(ir_dereference_array
*);
451 virtual void visit(ir_dereference_record
*);
452 virtual void visit(ir_assignment
*);
453 virtual void visit(ir_constant
*);
454 virtual void visit(ir_call
*);
455 virtual void visit(ir_return
*);
456 virtual void visit(ir_discard
*);
457 virtual void visit(ir_texture
*);
458 virtual void visit(ir_if
*);
459 virtual void visit(ir_emit_vertex
*);
460 virtual void visit(ir_end_primitive
*);
461 virtual void visit(ir_barrier
*);
464 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
466 void visit_atomic_counter_intrinsic(ir_call
*);
467 void visit_ssbo_intrinsic(ir_call
*);
468 void visit_membar_intrinsic(ir_call
*);
469 void visit_shared_intrinsic(ir_call
*);
470 void visit_image_intrinsic(ir_call
*);
474 /** List of variable_storage */
477 /** List of immediate_storage */
478 exec_list immediates
;
479 unsigned num_immediates
;
481 /** List of glsl_to_tgsi_instruction */
482 exec_list instructions
;
484 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
485 st_dst_reg dst
= undef_dst
,
486 st_src_reg src0
= undef_src
,
487 st_src_reg src1
= undef_src
,
488 st_src_reg src2
= undef_src
,
489 st_src_reg src3
= undef_src
);
491 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
492 st_dst_reg dst
, st_dst_reg dst1
,
493 st_src_reg src0
= undef_src
,
494 st_src_reg src1
= undef_src
,
495 st_src_reg src2
= undef_src
,
496 st_src_reg src3
= undef_src
);
498 unsigned get_opcode(unsigned op
,
500 st_src_reg src0
, st_src_reg src1
);
503 * Emit the correct dot-product instruction for the type of arguments
505 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
511 void emit_scalar(ir_instruction
*ir
, unsigned op
,
512 st_dst_reg dst
, st_src_reg src0
);
514 void emit_scalar(ir_instruction
*ir
, unsigned op
,
515 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
517 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
519 void get_deref_offsets(ir_dereference
*ir
,
520 unsigned *array_size
,
525 void calc_deref_offsets(ir_dereference
*tail
,
526 unsigned *array_elements
,
528 st_src_reg
*indirect
,
530 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
532 bool try_emit_mad(ir_expression
*ir
,
534 bool try_emit_mad_for_and_not(ir_expression
*ir
,
537 void emit_swz(ir_expression
*ir
);
539 bool process_move_condition(ir_rvalue
*ir
);
541 void simplify_cmp(void);
543 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
544 void get_first_temp_read(int *first_reads
);
545 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
546 void get_last_temp_write(int *last_writes
);
548 void copy_propagate(void);
549 int eliminate_dead_code(void);
551 void merge_two_dsts(void);
552 void merge_registers(void);
553 void renumber_registers(void);
555 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
556 st_dst_reg
*l
, st_src_reg
*r
,
557 st_src_reg
*cond
, bool cond_swap
);
562 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
563 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
564 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
567 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
570 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
574 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
577 prog
->data
->LinkStatus
= GL_FALSE
;
581 swizzle_for_size(int size
)
583 static const int size_swizzles
[4] = {
584 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
585 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
586 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
587 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
590 assert((size
>= 1) && (size
<= 4));
591 return size_swizzles
[size
- 1];
595 is_resource_instruction(unsigned opcode
)
598 case TGSI_OPCODE_RESQ
:
599 case TGSI_OPCODE_LOAD
:
600 case TGSI_OPCODE_ATOMUADD
:
601 case TGSI_OPCODE_ATOMXCHG
:
602 case TGSI_OPCODE_ATOMCAS
:
603 case TGSI_OPCODE_ATOMAND
:
604 case TGSI_OPCODE_ATOMOR
:
605 case TGSI_OPCODE_ATOMXOR
:
606 case TGSI_OPCODE_ATOMUMIN
:
607 case TGSI_OPCODE_ATOMUMAX
:
608 case TGSI_OPCODE_ATOMIMIN
:
609 case TGSI_OPCODE_ATOMIMAX
:
617 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
619 return op
->info
->num_dst
;
623 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
625 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
626 op
->info
->num_src
- 1 : op
->info
->num_src
;
629 glsl_to_tgsi_instruction
*
630 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
631 st_dst_reg dst
, st_dst_reg dst1
,
632 st_src_reg src0
, st_src_reg src1
,
633 st_src_reg src2
, st_src_reg src3
)
635 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
636 int num_reladdr
= 0, i
, j
;
637 bool dst_is_64bit
[2];
639 op
= get_opcode(op
, dst
, src0
, src1
);
641 /* If we have to do relative addressing, we want to load the ARL
642 * reg directly for one of the regs, and preload the other reladdr
643 * sources into temps.
645 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
646 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
647 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
648 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
649 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
650 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
652 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
653 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
654 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
655 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
657 if (dst
.reladdr
|| dst
.reladdr2
) {
659 emit_arl(ir
, address_reg
, *dst
.reladdr
);
661 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
665 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
668 assert(num_reladdr
== 0);
670 /* inst->op has only 8 bits. */
671 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
674 inst
->info
= tgsi_get_opcode_info(op
);
681 inst
->is_64bit_expanded
= false;
684 inst
->tex_offsets
= NULL
;
685 inst
->tex_offset_num_offset
= 0;
687 inst
->tex_shadow
= 0;
688 /* default to float, for paths where this is not initialized
689 * (since 0==UINT which is likely wrong):
691 inst
->tex_type
= GLSL_TYPE_FLOAT
;
693 /* Update indirect addressing status used by TGSI */
694 if (dst
.reladdr
|| dst
.reladdr2
) {
696 case PROGRAM_STATE_VAR
:
697 case PROGRAM_CONSTANT
:
698 case PROGRAM_UNIFORM
:
699 this->indirect_addr_consts
= true;
701 case PROGRAM_IMMEDIATE
:
702 assert(!"immediates should not have indirect addressing");
709 for (i
= 0; i
< 4; i
++) {
710 if(inst
->src
[i
].reladdr
) {
711 switch(inst
->src
[i
].file
) {
712 case PROGRAM_STATE_VAR
:
713 case PROGRAM_CONSTANT
:
714 case PROGRAM_UNIFORM
:
715 this->indirect_addr_consts
= true;
717 case PROGRAM_IMMEDIATE
:
718 assert(!"immediates should not have indirect addressing");
728 * This section contains the double processing.
729 * GLSL just represents doubles as single channel values,
730 * however most HW and TGSI represent doubles as pairs of register channels.
732 * so we have to fixup destination writemask/index and src swizzle/indexes.
733 * dest writemasks need to translate from single channel write mask
734 * to a dual-channel writemask, but also need to modify the index,
735 * if we are touching the Z,W fields in the pre-translated writemask.
737 * src channels have similiar index modifications along with swizzle
738 * changes to we pick the XY, ZW pairs from the correct index.
740 * GLSL [0].x -> TGSI [0].xy
741 * GLSL [0].y -> TGSI [0].zw
742 * GLSL [0].z -> TGSI [1].xy
743 * GLSL [0].w -> TGSI [1].zw
745 for (j
= 0; j
< 2; j
++) {
746 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
747 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
748 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
749 if (glsl_base_type_is_64bit(type
))
750 dst_is_64bit
[j
] = true;
754 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
755 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
756 glsl_to_tgsi_instruction
*dinst
= NULL
;
757 int initial_src_swz
[4], initial_src_idx
[4];
758 int initial_dst_idx
[2], initial_dst_writemask
[2];
759 /* select the writemask for dst0 or dst1 */
760 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
762 /* copy out the writemask, index and swizzles for all src/dsts. */
763 for (j
= 0; j
< 2; j
++) {
764 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
765 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
768 for (j
= 0; j
< 4; j
++) {
769 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
770 initial_src_idx
[j
] = inst
->src
[j
].index
;
774 * scan all the components in the dst writemask
775 * generate an instruction for each of them if required.
780 int i
= u_bit_scan(&writemask
);
782 /* before emitting the instruction, see if we have to adjust load / store
784 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
785 addr
.file
== PROGRAM_UNDEFINED
) {
786 /* We have to advance the buffer address by 16 */
787 addr
= get_temp(glsl_type::uint_type
);
788 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
789 inst
->src
[0], st_src_reg_for_int(16));
792 /* first time use previous instruction */
796 /* create a new instructions for subsequent attempts */
797 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
802 this->instructions
.push_tail(dinst
);
803 dinst
->is_64bit_expanded
= true;
805 /* modify the destination if we are splitting */
806 for (j
= 0; j
< 2; j
++) {
807 if (dst_is_64bit
[j
]) {
808 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
809 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
811 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
812 dinst
->src
[0] = addr
;
813 if (dinst
->op
!= TGSI_OPCODE_STORE
)
814 dinst
->dst
[j
].index
++;
817 /* if we aren't writing to a double, just get the bit of the initial writemask
819 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
823 /* modify the src registers */
824 for (j
= 0; j
< 4; j
++) {
825 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
827 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
828 dinst
->src
[j
].index
= initial_src_idx
[j
];
830 dinst
->src
[j
].double_reg2
= true;
831 dinst
->src
[j
].index
++;
835 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
837 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
840 /* some opcodes are special case in what they use as sources
841 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
842 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
843 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
844 op
== TGSI_OPCODE_DLDEXP
||
845 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
846 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
853 this->instructions
.push_tail(inst
);
860 glsl_to_tgsi_instruction
*
861 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
863 st_src_reg src0
, st_src_reg src1
,
864 st_src_reg src2
, st_src_reg src3
)
866 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
870 * Determines whether to use an integer, unsigned integer, or float opcode
871 * based on the operands and input opcode, then emits the result.
874 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
876 st_src_reg src0
, st_src_reg src1
)
878 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
880 if (op
== TGSI_OPCODE_MOV
)
883 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
884 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
885 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
886 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
888 if (is_resource_instruction(op
))
890 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
891 type
= GLSL_TYPE_DOUBLE
;
892 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
893 type
= GLSL_TYPE_FLOAT
;
894 else if (native_integers
)
895 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
897 #define case5(c, f, i, u, d) \
898 case TGSI_OPCODE_##c: \
899 if (type == GLSL_TYPE_DOUBLE) \
900 op = TGSI_OPCODE_##d; \
901 else if (type == GLSL_TYPE_INT) \
902 op = TGSI_OPCODE_##i; \
903 else if (type == GLSL_TYPE_UINT) \
904 op = TGSI_OPCODE_##u; \
906 op = TGSI_OPCODE_##f; \
909 #define case4(c, f, i, u) \
910 case TGSI_OPCODE_##c: \
911 if (type == GLSL_TYPE_INT) \
912 op = TGSI_OPCODE_##i; \
913 else if (type == GLSL_TYPE_UINT) \
914 op = TGSI_OPCODE_##u; \
916 op = TGSI_OPCODE_##f; \
919 #define case3(f, i, u) case4(f, f, i, u)
920 #define case4d(f, i, u, d) case5(f, f, i, u, d)
921 #define case3fid(f, i, d) case5(f, f, i, i, d)
922 #define case2fi(f, i) case4(f, f, i, i)
923 #define case2iu(i, u) case4(i, LAST, i, u)
925 #define casecomp(c, f, i, u, d) \
926 case TGSI_OPCODE_##c: \
927 if (type == GLSL_TYPE_DOUBLE) \
928 op = TGSI_OPCODE_##d; \
929 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
930 op = TGSI_OPCODE_##i; \
931 else if (type == GLSL_TYPE_UINT) \
932 op = TGSI_OPCODE_##u; \
933 else if (native_integers) \
934 op = TGSI_OPCODE_##f; \
936 op = TGSI_OPCODE_##c; \
940 case3fid(ADD
, UADD
, DADD
);
941 case3fid(MUL
, UMUL
, DMUL
);
942 case3fid(MAD
, UMAD
, DMAD
);
943 case3fid(FMA
, UMAD
, DFMA
);
944 case3(DIV
, IDIV
, UDIV
);
945 case4d(MAX
, IMAX
, UMAX
, DMAX
);
946 case4d(MIN
, IMIN
, UMIN
, DMIN
);
949 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
950 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
951 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
952 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
956 case3fid(SSG
, ISSG
, DSSG
);
957 case3fid(ABS
, IABS
, DABS
);
961 case2iu(IMUL_HI
, UMUL_HI
);
963 case3fid(SQRT
, SQRT
, DSQRT
);
965 case3fid(RCP
, RCP
, DRCP
);
966 case3fid(RSQ
, RSQ
, DRSQ
);
968 case3fid(FRC
, FRC
, DFRAC
);
969 case3fid(TRUNC
, TRUNC
, DTRUNC
);
970 case3fid(CEIL
, CEIL
, DCEIL
);
971 case3fid(FLR
, FLR
, DFLR
);
972 case3fid(ROUND
, ROUND
, DROUND
);
974 case2iu(ATOMIMAX
, ATOMUMAX
);
975 case2iu(ATOMIMIN
, ATOMUMIN
);
980 assert(op
!= TGSI_OPCODE_LAST
);
984 glsl_to_tgsi_instruction
*
985 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
986 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
989 static const unsigned dot_opcodes
[] = {
990 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
993 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
997 * Emits TGSI scalar opcodes to produce unique answers across channels.
999 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1000 * channel determines the result across all channels. So to do a vec4
1001 * of this operation, we want to emit a scalar per source channel used
1002 * to produce dest channels.
1005 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1007 st_src_reg orig_src0
, st_src_reg orig_src1
)
1010 int done_mask
= ~dst
.writemask
;
1012 /* TGSI RCP is a scalar operation splatting results to all channels,
1013 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1016 for (i
= 0; i
< 4; i
++) {
1017 GLuint this_mask
= (1 << i
);
1018 st_src_reg src0
= orig_src0
;
1019 st_src_reg src1
= orig_src1
;
1021 if (done_mask
& this_mask
)
1024 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1025 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1026 for (j
= i
+ 1; j
< 4; j
++) {
1027 /* If there is another enabled component in the destination that is
1028 * derived from the same inputs, generate its value on this pass as
1031 if (!(done_mask
& (1 << j
)) &&
1032 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1033 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1034 this_mask
|= (1 << j
);
1037 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1038 src0_swiz
, src0_swiz
);
1039 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1040 src1_swiz
, src1_swiz
);
1042 dst
.writemask
= this_mask
;
1043 emit_asm(ir
, op
, dst
, src0
, src1
);
1044 done_mask
|= this_mask
;
1049 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1050 st_dst_reg dst
, st_src_reg src0
)
1052 st_src_reg undef
= undef_src
;
1054 undef
.swizzle
= SWIZZLE_XXXX
;
1056 emit_scalar(ir
, op
, dst
, src0
, undef
);
1060 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1061 st_dst_reg dst
, st_src_reg src0
)
1063 int op
= TGSI_OPCODE_ARL
;
1065 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1066 op
= TGSI_OPCODE_UARL
;
1068 assert(dst
.file
== PROGRAM_ADDRESS
);
1069 if (dst
.index
>= this->num_address_regs
)
1070 this->num_address_regs
= dst
.index
+ 1;
1072 emit_asm(NULL
, op
, dst
, src0
);
1076 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1077 gl_constant_value values
[8], int size
, int datatype
,
1078 uint16_t *swizzle_out
)
1080 if (file
== PROGRAM_CONSTANT
) {
1081 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1082 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1083 size
, datatype
, &swizzle
);
1085 *swizzle_out
= swizzle
;
1089 assert(file
== PROGRAM_IMMEDIATE
);
1092 immediate_storage
*entry
;
1093 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1096 /* Search immediate storage to see if we already have an identical
1097 * immediate that we can use instead of adding a duplicate entry.
1099 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1100 immediate_storage
*tmp
= entry
;
1102 for (i
= 0; i
* 4 < size32
; i
++) {
1103 int slot_size
= MIN2(size32
- (i
* 4), 4);
1104 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1106 if (memcmp(tmp
->values
, &values
[i
* 4],
1107 slot_size
* sizeof(gl_constant_value
)))
1110 /* Everything matches, keep going until the full size is matched */
1111 tmp
= (immediate_storage
*)tmp
->next
;
1114 /* The full value matched */
1115 if (i
* 4 >= size32
)
1121 for (i
= 0; i
* 4 < size32
; i
++) {
1122 int slot_size
= MIN2(size32
- (i
* 4), 4);
1123 /* Add this immediate to the list. */
1124 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1125 this->immediates
.push_tail(entry
);
1126 this->num_immediates
++;
1132 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1134 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1135 union gl_constant_value uval
;
1138 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1144 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1146 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1147 union gl_constant_value uval
[2];
1149 memcpy(uval
, &val
, sizeof(uval
));
1150 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1151 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1156 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1158 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1159 union gl_constant_value uval
;
1161 assert(native_integers
);
1164 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1170 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1172 if (native_integers
)
1173 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1174 st_src_reg_for_int(val
);
1176 return st_src_reg_for_float(val
);
1180 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1182 return st_glsl_attrib_type_size(type
, is_vs_input
);
1186 type_size(const struct glsl_type
*type
)
1188 return st_glsl_type_size(type
);
1192 * If the given GLSL type is an array or matrix or a structure containing
1193 * an array/matrix member, return true. Else return false.
1195 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1196 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1197 * we have an array that might be indexed with a variable, we need to use
1198 * the later storage type.
1201 type_has_array_or_matrix(const glsl_type
*type
)
1203 if (type
->is_array() || type
->is_matrix())
1206 if (type
->is_record()) {
1207 for (unsigned i
= 0; i
< type
->length
; i
++) {
1208 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1219 * In the initial pass of codegen, we assign temporary numbers to
1220 * intermediate results. (not SSA -- variable assignments will reuse
1224 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1228 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1232 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1233 if (next_array
>= max_num_arrays
) {
1234 max_num_arrays
+= 32;
1235 array_sizes
= (unsigned*)
1236 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1239 src
.file
= PROGRAM_ARRAY
;
1241 src
.array_id
= next_array
+ 1;
1242 array_sizes
[next_array
] = type_size(type
);
1246 src
.file
= PROGRAM_TEMPORARY
;
1247 src
.index
= next_temp
;
1248 next_temp
+= type_size(type
);
1251 if (type
->is_array() || type
->is_record()) {
1252 src
.swizzle
= SWIZZLE_NOOP
;
1254 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1261 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1264 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1265 if (entry
->var
== var
)
1273 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1275 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1276 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1277 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1280 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1282 const ir_state_slot
*const slots
= ir
->get_state_slots();
1283 assert(slots
!= NULL
);
1285 /* Check if this statevar's setup in the STATE file exactly
1286 * matches how we'll want to reference it as a
1287 * struct/array/whatever. If not, then we need to move it into
1288 * temporary storage and hope that it'll get copy-propagated
1291 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1292 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1297 variable_storage
*storage
;
1299 if (i
== ir
->get_num_state_slots()) {
1300 /* We'll set the index later. */
1301 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1302 this->variables
.push_tail(storage
);
1306 /* The variable_storage constructor allocates slots based on the size
1307 * of the type. However, this had better match the number of state
1308 * elements that we're going to copy into the new temporary.
1310 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1312 dst
= st_dst_reg(get_temp(ir
->type
));
1314 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1317 this->variables
.push_tail(storage
);
1321 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1322 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1323 (gl_state_index
*)slots
[i
].tokens
);
1325 if (storage
->file
== PROGRAM_STATE_VAR
) {
1326 if (storage
->index
== -1) {
1327 storage
->index
= index
;
1329 assert(index
== storage
->index
+ (int)i
);
1332 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1333 * the data being moved since MOV does not care about the type of
1334 * data it is moving, and we don't want to declare registers with
1335 * array or struct types.
1337 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1338 src
.swizzle
= slots
[i
].swizzle
;
1339 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1340 /* even a float takes up a whole vec4 reg in a struct/array. */
1345 if (storage
->file
== PROGRAM_TEMPORARY
&&
1346 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1347 fail_link(this->shader_program
,
1348 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1349 ir
->name
, dst
.index
- storage
->index
,
1350 type_size(ir
->type
));
1356 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1358 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1360 visit_exec_list(&ir
->body_instructions
, this);
1362 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1366 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1369 case ir_loop_jump::jump_break
:
1370 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1372 case ir_loop_jump::jump_continue
:
1373 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1380 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1387 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1389 /* Ignore function bodies other than main() -- we shouldn't see calls to
1390 * them since they should all be inlined before we get to glsl_to_tgsi.
1392 if (strcmp(ir
->name
, "main") == 0) {
1393 const ir_function_signature
*sig
;
1396 sig
= ir
->matching_signature(NULL
, &empty
, false);
1400 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1407 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1409 int nonmul_operand
= 1 - mul_operand
;
1411 st_dst_reg result_dst
;
1413 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1414 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1417 expr
->operands
[0]->accept(this);
1419 expr
->operands
[1]->accept(this);
1421 ir
->operands
[nonmul_operand
]->accept(this);
1424 this->result
= get_temp(ir
->type
);
1425 result_dst
= st_dst_reg(this->result
);
1426 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1427 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1433 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1435 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1436 * implemented using multiplication, and logical-or is implemented using
1437 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1438 * As result, the logical expression (a & !b) can be rewritten as:
1442 * - (a * 1) - (a * b)
1446 * This final expression can be implemented as a single MAD(a, -b, a)
1450 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1452 const int other_operand
= 1 - try_operand
;
1455 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1456 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1459 ir
->operands
[other_operand
]->accept(this);
1461 expr
->operands
[0]->accept(this);
1464 b
.negate
= ~b
.negate
;
1466 this->result
= get_temp(ir
->type
);
1467 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1473 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1474 st_src_reg
*reg
, int *num_reladdr
)
1476 if (!reg
->reladdr
&& !reg
->reladdr2
)
1479 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1480 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1482 if (*num_reladdr
!= 1) {
1483 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1485 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1493 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1495 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1497 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1499 if (ir
->operation
== ir_binop_add
) {
1500 if (try_emit_mad(ir
, 1))
1502 if (try_emit_mad(ir
, 0))
1506 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1508 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1509 if (try_emit_mad_for_and_not(ir
, 1))
1511 if (try_emit_mad_for_and_not(ir
, 0))
1515 if (ir
->operation
== ir_quadop_vector
)
1516 assert(!"ir_quadop_vector should have been lowered");
1518 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1519 this->result
.file
= PROGRAM_UNDEFINED
;
1520 ir
->operands
[operand
]->accept(this);
1521 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1522 printf("Failed to get tree for expression operand:\n");
1523 ir
->operands
[operand
]->print();
1527 op
[operand
] = this->result
;
1529 /* Matrix expression operands should have been broken down to vector
1530 * operations already.
1532 assert(!ir
->operands
[operand
]->type
->is_matrix());
1535 visit_expression(ir
, op
);
1538 /* The non-recursive part of the expression visitor lives in a separate
1539 * function and should be prevented from being inlined, to avoid a stack
1540 * explosion when deeply nested expressions are visited.
1543 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1545 st_src_reg result_src
;
1546 st_dst_reg result_dst
;
1548 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1549 if (ir
->operands
[1]) {
1550 vector_elements
= MAX2(vector_elements
,
1551 ir
->operands
[1]->type
->vector_elements
);
1554 this->result
.file
= PROGRAM_UNDEFINED
;
1556 /* Storage for our result. Ideally for an assignment we'd be using
1557 * the actual storage for the result here, instead.
1559 result_src
= get_temp(ir
->type
);
1560 /* convenience for the emit functions below. */
1561 result_dst
= st_dst_reg(result_src
);
1562 /* Limit writes to the channels that will be used by result_src later.
1563 * This does limit this temp's use as a temporary for multi-instruction
1566 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1568 switch (ir
->operation
) {
1569 case ir_unop_logic_not
:
1570 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1571 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1573 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1574 * older GPUs implement SEQ using multiple instructions (i915 uses two
1575 * SGE instructions and a MUL instruction). Since our logic values are
1576 * 0.0 and 1.0, 1-x also implements !x.
1578 op
[0].negate
= ~op
[0].negate
;
1579 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1583 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1584 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1585 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1586 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1588 op
[0].negate
= ~op
[0].negate
;
1592 case ir_unop_subroutine_to_int
:
1593 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1596 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1599 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1602 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1606 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1610 assert(!"not reached: should be handled by ir_explog_to_explog2");
1613 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1616 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1619 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1621 case ir_unop_saturate
: {
1622 glsl_to_tgsi_instruction
*inst
;
1623 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1624 inst
->saturate
= true;
1629 case ir_unop_dFdx_coarse
:
1630 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1632 case ir_unop_dFdx_fine
:
1633 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1636 case ir_unop_dFdy_coarse
:
1637 case ir_unop_dFdy_fine
:
1639 /* The X component contains 1 or -1 depending on whether the framebuffer
1640 * is a FBO or the window system buffer, respectively.
1641 * It is then multiplied with the source operand of DDY.
1643 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1644 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1646 unsigned transform_y_index
=
1647 _mesa_add_state_reference(this->prog
->Parameters
,
1650 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1652 glsl_type::vec4_type
);
1653 transform_y
.swizzle
= SWIZZLE_XXXX
;
1655 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1657 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1658 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1659 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1663 case ir_unop_frexp_sig
:
1664 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1667 case ir_unop_frexp_exp
:
1668 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1671 case ir_unop_noise
: {
1672 /* At some point, a motivated person could add a better
1673 * implementation of noise. Currently not even the nvidia
1674 * binary drivers do anything more than this. In any case, the
1675 * place to do this is in the GL state tracker, not the poor
1678 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1683 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1686 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1690 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1693 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1694 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1696 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1699 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1700 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1702 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1706 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1708 case ir_binop_greater
:
1709 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1711 case ir_binop_lequal
:
1712 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1714 case ir_binop_gequal
:
1715 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1717 case ir_binop_equal
:
1718 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1720 case ir_binop_nequal
:
1721 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1723 case ir_binop_all_equal
:
1724 /* "==" operator producing a scalar boolean. */
1725 if (ir
->operands
[0]->type
->is_vector() ||
1726 ir
->operands
[1]->type
->is_vector()) {
1727 st_src_reg temp
= get_temp(native_integers
?
1728 glsl_type::uvec4_type
:
1729 glsl_type::vec4_type
);
1731 if (native_integers
) {
1732 st_dst_reg temp_dst
= st_dst_reg(temp
);
1733 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1735 if (ir
->operands
[0]->type
->is_boolean() &&
1736 ir
->operands
[1]->as_constant() &&
1737 ir
->operands
[1]->as_constant()->is_one()) {
1738 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1740 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1743 /* Emit 1-3 AND operations to combine the SEQ results. */
1744 switch (ir
->operands
[0]->type
->vector_elements
) {
1748 temp_dst
.writemask
= WRITEMASK_Y
;
1749 temp1
.swizzle
= SWIZZLE_YYYY
;
1750 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1751 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1754 temp_dst
.writemask
= WRITEMASK_X
;
1755 temp1
.swizzle
= SWIZZLE_XXXX
;
1756 temp2
.swizzle
= SWIZZLE_YYYY
;
1757 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1758 temp_dst
.writemask
= WRITEMASK_Y
;
1759 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1760 temp2
.swizzle
= SWIZZLE_WWWW
;
1761 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1764 temp1
.swizzle
= SWIZZLE_XXXX
;
1765 temp2
.swizzle
= SWIZZLE_YYYY
;
1766 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1768 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1770 /* After the dot-product, the value will be an integer on the
1771 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1773 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1775 /* Negating the result of the dot-product gives values on the range
1776 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1777 * This is achieved using SGE.
1779 st_src_reg sge_src
= result_src
;
1780 sge_src
.negate
= ~sge_src
.negate
;
1781 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1784 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1787 case ir_binop_any_nequal
:
1788 /* "!=" operator producing a scalar boolean. */
1789 if (ir
->operands
[0]->type
->is_vector() ||
1790 ir
->operands
[1]->type
->is_vector()) {
1791 st_src_reg temp
= get_temp(native_integers
?
1792 glsl_type::uvec4_type
:
1793 glsl_type::vec4_type
);
1794 if (ir
->operands
[0]->type
->is_boolean() &&
1795 ir
->operands
[1]->as_constant() &&
1796 ir
->operands
[1]->as_constant()->is_zero()) {
1797 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1799 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1802 if (native_integers
) {
1803 st_dst_reg temp_dst
= st_dst_reg(temp
);
1804 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1806 /* Emit 1-3 OR operations to combine the SNE results. */
1807 switch (ir
->operands
[0]->type
->vector_elements
) {
1811 temp_dst
.writemask
= WRITEMASK_Y
;
1812 temp1
.swizzle
= SWIZZLE_YYYY
;
1813 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1814 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1817 temp_dst
.writemask
= WRITEMASK_X
;
1818 temp1
.swizzle
= SWIZZLE_XXXX
;
1819 temp2
.swizzle
= SWIZZLE_YYYY
;
1820 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1821 temp_dst
.writemask
= WRITEMASK_Y
;
1822 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1823 temp2
.swizzle
= SWIZZLE_WWWW
;
1824 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1827 temp1
.swizzle
= SWIZZLE_XXXX
;
1828 temp2
.swizzle
= SWIZZLE_YYYY
;
1829 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1831 /* After the dot-product, the value will be an integer on the
1832 * range [0,4]. Zero stays zero, and positive values become 1.0.
1834 glsl_to_tgsi_instruction
*const dp
=
1835 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1836 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1837 /* The clamping to [0,1] can be done for free in the fragment
1838 * shader with a saturate.
1840 dp
->saturate
= true;
1842 /* Negating the result of the dot-product gives values on the range
1843 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1844 * achieved using SLT.
1846 st_src_reg slt_src
= result_src
;
1847 slt_src
.negate
= ~slt_src
.negate
;
1848 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1852 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1856 case ir_binop_logic_xor
:
1857 if (native_integers
)
1858 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1860 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1863 case ir_binop_logic_or
: {
1864 if (native_integers
) {
1865 /* If integers are used as booleans, we can use an actual "or"
1868 assert(native_integers
);
1869 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1871 /* After the addition, the value will be an integer on the
1872 * range [0,2]. Zero stays zero, and positive values become 1.0.
1874 glsl_to_tgsi_instruction
*add
=
1875 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1876 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1877 /* The clamping to [0,1] can be done for free in the fragment
1878 * shader with a saturate if floats are being used as boolean values.
1880 add
->saturate
= true;
1882 /* Negating the result of the addition gives values on the range
1883 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1884 * is achieved using SLT.
1886 st_src_reg slt_src
= result_src
;
1887 slt_src
.negate
= ~slt_src
.negate
;
1888 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1894 case ir_binop_logic_and
:
1895 /* If native integers are disabled, the bool args are stored as float 0.0
1896 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1897 * actual AND opcode.
1899 if (native_integers
)
1900 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1902 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1906 assert(ir
->operands
[0]->type
->is_vector());
1907 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1908 emit_dp(ir
, result_dst
, op
[0], op
[1],
1909 ir
->operands
[0]->type
->vector_elements
);
1914 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1916 /* This is the only instruction sequence that makes the game "Risen"
1917 * render correctly. ABS is not required for the game, but since GLSL
1918 * declares negative values as "undefined", allowing us to do whatever
1919 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1922 emit_scalar(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1923 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, result_src
);
1924 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1928 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1931 if (native_integers
) {
1932 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1935 /* fallthrough to next case otherwise */
1937 if (native_integers
) {
1938 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1941 /* fallthrough to next case otherwise */
1944 /* Converting between signed and unsigned integers is a no-op. */
1946 result_src
.type
= result_dst
.type
;
1949 if (native_integers
) {
1950 /* Booleans are stored as integers using ~0 for true and 0 for false.
1951 * GLSL requires that int(bool) return 1 for true and 0 for false.
1952 * This conversion is done with AND, but it could be done with NEG.
1954 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1956 /* Booleans and integers are both stored as floats when native
1957 * integers are disabled.
1963 if (native_integers
)
1964 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1966 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1969 if (native_integers
)
1970 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1972 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1974 case ir_unop_bitcast_f2i
:
1975 case ir_unop_bitcast_f2u
:
1976 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1978 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1981 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1984 case ir_unop_bitcast_i2f
:
1985 case ir_unop_bitcast_u2f
:
1987 result_src
.type
= GLSL_TYPE_FLOAT
;
1990 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1993 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1996 if (native_integers
)
1997 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1999 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2002 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2005 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2008 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2010 case ir_unop_round_even
:
2011 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2014 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2018 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2021 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2024 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2027 case ir_unop_bit_not
:
2028 if (native_integers
) {
2029 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2033 if (native_integers
) {
2034 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2037 case ir_binop_lshift
:
2038 if (native_integers
) {
2039 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2042 case ir_binop_rshift
:
2043 if (native_integers
) {
2044 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2047 case ir_binop_bit_and
:
2048 if (native_integers
) {
2049 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2052 case ir_binop_bit_xor
:
2053 if (native_integers
) {
2054 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2057 case ir_binop_bit_or
:
2058 if (native_integers
) {
2059 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2063 assert(!"GLSL 1.30 features unsupported");
2066 case ir_binop_ubo_load
: {
2067 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2068 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2069 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2070 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2071 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2074 cbuf
.type
= ir
->type
->base_type
;
2075 cbuf
.file
= PROGRAM_CONSTANT
;
2077 cbuf
.reladdr
= NULL
;
2080 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2082 if (const_offset_ir
) {
2083 /* Constant index into constant buffer */
2084 cbuf
.reladdr
= NULL
;
2085 cbuf
.index
= const_offset
/ 16;
2088 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2089 st_src_reg offset
= op
[1];
2091 /* The OpenGL spec is written in such a way that accesses with
2092 * non-constant offset are almost always vec4-aligned. The only
2093 * exception to this are members of structs in arrays of structs:
2094 * each struct in an array of structs is at least vec4-aligned,
2095 * but single-element and [ui]vec2 members of the struct may be at
2096 * an offset that is not a multiple of 16 bytes.
2098 * Here, we extract that offset, relying on previous passes to always
2099 * generate offset expressions of the form (+ expr constant_offset).
2101 * Note that the std430 layout, which allows more cases of alignment
2102 * less than vec4 in arrays, is not supported for uniform blocks, so
2103 * we do not have to deal with it here.
2105 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2106 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2107 if (const_offset_ir
) {
2108 const_offset
= const_offset_ir
->value
.u
[0];
2109 cbuf
.index
= const_offset
/ 16;
2110 offset_expr
->operands
[0]->accept(this);
2111 offset
= this->result
;
2115 /* Relative/variable index into constant buffer */
2116 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2117 st_src_reg_for_int(4));
2118 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2119 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2122 if (const_uniform_block
) {
2123 /* Constant constant buffer */
2124 cbuf
.reladdr2
= NULL
;
2125 cbuf
.index2D
= const_block
;
2126 cbuf
.has_index2
= true;
2129 /* Relative/variable constant buffer */
2130 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2132 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2133 cbuf
.has_index2
= true;
2136 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2137 if (glsl_base_type_is_64bit(cbuf
.type
))
2138 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2139 const_offset
% 16 / 8,
2140 const_offset
% 16 / 8,
2141 const_offset
% 16 / 8);
2143 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2144 const_offset
% 16 / 4,
2145 const_offset
% 16 / 4,
2146 const_offset
% 16 / 4);
2148 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2149 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2151 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2156 /* note: we have to reorder the three args here */
2157 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2160 if (this->ctx
->Const
.NativeIntegers
)
2161 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2163 op
[0].negate
= ~op
[0].negate
;
2164 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2167 case ir_triop_bitfield_extract
:
2168 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2170 case ir_quadop_bitfield_insert
:
2171 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2173 case ir_unop_bitfield_reverse
:
2174 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2176 case ir_unop_bit_count
:
2177 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2179 case ir_unop_find_msb
:
2180 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2182 case ir_unop_find_lsb
:
2183 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2185 case ir_binop_imul_high
:
2186 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2189 /* In theory, MAD is incorrect here. */
2191 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2193 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2195 case ir_unop_interpolate_at_centroid
:
2196 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2198 case ir_binop_interpolate_at_offset
: {
2199 /* The y coordinate needs to be flipped for the default fb */
2200 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2201 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2203 unsigned transform_y_index
=
2204 _mesa_add_state_reference(this->prog
->Parameters
,
2207 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2209 glsl_type::vec4_type
);
2210 transform_y
.swizzle
= SWIZZLE_XXXX
;
2212 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2213 st_dst_reg temp_dst
= st_dst_reg(temp
);
2215 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2216 temp_dst
.writemask
= WRITEMASK_Y
;
2217 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2218 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2221 case ir_binop_interpolate_at_sample
:
2222 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2226 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2229 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2232 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2235 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2238 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2241 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2243 case ir_unop_unpack_double_2x32
:
2244 case ir_unop_pack_double_2x32
:
2245 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2248 case ir_binop_ldexp
:
2249 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2250 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2252 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2256 case ir_unop_pack_half_2x16
:
2257 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2259 case ir_unop_unpack_half_2x16
:
2260 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2263 case ir_unop_get_buffer_size
: {
2264 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2267 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2268 (const_offset
? const_offset
->value
.u
[0] : 0),
2270 if (!const_offset
) {
2271 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2272 *buffer
.reladdr
= op
[0];
2273 emit_arl(ir
, sampler_reladdr
, op
[0]);
2275 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2279 case ir_unop_vote_any
:
2280 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2282 case ir_unop_vote_all
:
2283 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2285 case ir_unop_vote_eq
:
2286 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2289 case ir_unop_pack_snorm_2x16
:
2290 case ir_unop_pack_unorm_2x16
:
2291 case ir_unop_pack_snorm_4x8
:
2292 case ir_unop_pack_unorm_4x8
:
2294 case ir_unop_unpack_snorm_2x16
:
2295 case ir_unop_unpack_unorm_2x16
:
2296 case ir_unop_unpack_snorm_4x8
:
2297 case ir_unop_unpack_unorm_4x8
:
2299 case ir_quadop_vector
:
2300 case ir_binop_vector_extract
:
2301 case ir_triop_vector_insert
:
2302 case ir_binop_carry
:
2303 case ir_binop_borrow
:
2304 case ir_unop_ssbo_unsized_array_length
:
2305 /* This operation is not supported, or should have already been handled.
2307 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2311 this->result
= result_src
;
2316 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2322 /* Note that this is only swizzles in expressions, not those on the left
2323 * hand side of an assignment, which do write masking. See ir_assignment
2327 ir
->val
->accept(this);
2329 assert(src
.file
!= PROGRAM_UNDEFINED
);
2330 assert(ir
->type
->vector_elements
> 0);
2332 for (i
= 0; i
< 4; i
++) {
2333 if (i
< ir
->type
->vector_elements
) {
2336 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2339 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2342 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2345 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2349 /* If the type is smaller than a vec4, replicate the last
2352 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2356 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2361 /* Test if the variable is an array. Note that geometry and
2362 * tessellation shader inputs are outputs are always arrays (except
2363 * for patch inputs), so only the array element type is considered.
2366 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2368 const glsl_type
*type
= var
->type
;
2370 *remove_array
= false;
2372 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2373 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2376 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2377 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2378 stage
== MESA_SHADER_TESS_CTRL
) &&
2380 if (!var
->type
->is_array())
2381 return false; /* a system value probably */
2383 type
= var
->type
->fields
.array
;
2384 *remove_array
= true;
2387 return type
->is_array() || type
->is_matrix();
2391 st_translate_interp_loc(ir_variable
*var
)
2393 if (var
->data
.centroid
)
2394 return TGSI_INTERPOLATE_LOC_CENTROID
;
2395 else if (var
->data
.sample
)
2396 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2398 return TGSI_INTERPOLATE_LOC_CENTER
;
2402 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2404 variable_storage
*entry
= find_variable_storage(ir
->var
);
2405 ir_variable
*var
= ir
->var
;
2409 switch (var
->data
.mode
) {
2410 case ir_var_uniform
:
2411 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2412 var
->data
.param_index
);
2413 this->variables
.push_tail(entry
);
2415 case ir_var_shader_in
: {
2416 /* The linker assigns locations for varyings and attributes,
2417 * including deprecated builtins (like gl_Color), user-assign
2418 * generic attributes (glBindVertexLocation), and
2419 * user-defined varyings.
2421 assert(var
->data
.location
!= -1);
2423 const glsl_type
*type_without_array
= var
->type
->without_array();
2424 struct inout_decl
*decl
= &inputs
[num_inputs
];
2425 unsigned component
= var
->data
.location_frac
;
2426 unsigned num_components
;
2429 if (type_without_array
->is_64bit())
2430 component
= component
/ 2;
2431 if (type_without_array
->vector_elements
)
2432 num_components
= type_without_array
->vector_elements
;
2436 decl
->mesa_index
= var
->data
.location
;
2437 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2438 decl
->interp_loc
= st_translate_interp_loc(var
);
2439 decl
->base_type
= type_without_array
->base_type
;
2440 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2442 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2443 decl
->array_id
= num_input_arrays
+ 1;
2450 decl
->size
= type_size(var
->type
->fields
.array
);
2452 decl
->size
= type_size(var
->type
);
2454 entry
= new(mem_ctx
) variable_storage(var
,
2458 entry
->component
= component
;
2460 this->variables
.push_tail(entry
);
2463 case ir_var_shader_out
: {
2464 assert(var
->data
.location
!= -1);
2466 const glsl_type
*type_without_array
= var
->type
->without_array();
2467 struct inout_decl
*decl
= &outputs
[num_outputs
];
2468 unsigned component
= var
->data
.location_frac
;
2469 unsigned num_components
;
2472 if (type_without_array
->is_64bit())
2473 component
= component
/ 2;
2474 if (type_without_array
->vector_elements
)
2475 num_components
= type_without_array
->vector_elements
;
2479 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2480 decl
->base_type
= type_without_array
->base_type
;
2481 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2482 if (var
->data
.stream
& (1u << 31)) {
2483 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2485 assert(var
->data
.stream
< 4);
2486 decl
->gs_out_streams
= 0;
2487 for (unsigned i
= 0; i
< num_components
; ++i
)
2488 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2491 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2492 decl
->array_id
= num_output_arrays
+ 1;
2493 num_output_arrays
++;
2499 decl
->size
= type_size(var
->type
->fields
.array
);
2501 decl
->size
= type_size(var
->type
);
2503 entry
= new(mem_ctx
) variable_storage(var
,
2507 entry
->component
= component
;
2509 this->variables
.push_tail(entry
);
2512 case ir_var_system_value
:
2513 entry
= new(mem_ctx
) variable_storage(var
,
2514 PROGRAM_SYSTEM_VALUE
,
2515 var
->data
.location
);
2518 case ir_var_temporary
:
2519 st_src_reg src
= get_temp(var
->type
);
2521 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2523 this->variables
.push_tail(entry
);
2529 printf("Failed to make storage for %s\n", var
->name
);
2534 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2535 entry
->component
, entry
->array_id
);
2536 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2537 this->result
.is_double_vertex_input
= true;
2538 if (!native_integers
)
2539 this->result
.type
= GLSL_TYPE_FLOAT
;
2543 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2544 GLbitfield64
* usage_mask
,
2545 GLbitfield64 double_usage_mask
,
2546 GLbitfield
* patch_usage_mask
)
2551 /* Fix array declarations by removing unused array elements at both ends
2552 * of the arrays. For example, mat4[3] where only mat[1] is used.
2554 for (i
= 0; i
< count
; i
++) {
2555 struct inout_decl
*decl
= &decls
[i
];
2556 if (!decl
->array_id
)
2559 /* Shrink the beginning. */
2560 for (j
= 0; j
< (int)decl
->size
; j
++) {
2561 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2562 if (*patch_usage_mask
&
2563 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2567 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2569 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2578 /* Shrink the end. */
2579 for (j
= decl
->size
-1; j
>= 0; j
--) {
2580 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2581 if (*patch_usage_mask
&
2582 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2586 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2588 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2595 /* When not all entries of an array are accessed, we mark them as used
2596 * here anyway, to ensure that the input/output mapping logic doesn't get
2599 * TODO This happens when an array isn't used via indirect access, which
2600 * some game ports do (at least eON-based). There is an optimization
2601 * opportunity here by replacing the array declaration with non-array
2602 * declarations of those slots that are actually used.
2604 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2605 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2606 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2608 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2614 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2618 int element_size
= type_size(ir
->type
);
2621 index
= ir
->array_index
->constant_expression_value();
2623 ir
->array
->accept(this);
2626 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2627 switch (this->prog
->Target
) {
2628 case GL_TESS_CONTROL_PROGRAM_NV
:
2629 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2630 !ir
->variable_referenced()->data
.patch
;
2632 case GL_TESS_EVALUATION_PROGRAM_NV
:
2633 is_2D
= src
.file
== PROGRAM_INPUT
&&
2634 !ir
->variable_referenced()->data
.patch
;
2636 case GL_GEOMETRY_PROGRAM_NV
:
2637 is_2D
= src
.file
== PROGRAM_INPUT
;
2647 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2648 src
.file
== PROGRAM_INPUT
)
2649 element_size
= attrib_type_size(ir
->type
, true);
2651 src
.index2D
= index
->value
.i
[0];
2652 src
.has_index2
= true;
2654 src
.index
+= index
->value
.i
[0] * element_size
;
2656 /* Variable index array dereference. It eats the "vec4" of the
2657 * base of the array and an index that offsets the TGSI register
2660 ir
->array_index
->accept(this);
2662 st_src_reg index_reg
;
2664 if (element_size
== 1) {
2665 index_reg
= this->result
;
2667 index_reg
= get_temp(native_integers
?
2668 glsl_type::int_type
: glsl_type::float_type
);
2670 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2671 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2674 /* If there was already a relative address register involved, add the
2675 * new and the old together to get the new offset.
2677 if (!is_2D
&& src
.reladdr
!= NULL
) {
2678 st_src_reg accum_reg
= get_temp(native_integers
?
2679 glsl_type::int_type
: glsl_type::float_type
);
2681 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2682 index_reg
, *src
.reladdr
);
2684 index_reg
= accum_reg
;
2688 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2689 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2691 src
.has_index2
= true;
2693 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2694 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2698 /* Change the register type to the element type of the array. */
2699 src
.type
= ir
->type
->base_type
;
2705 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2708 const glsl_type
*struct_type
= ir
->record
->type
;
2711 ir
->record
->accept(this);
2713 for (i
= 0; i
< struct_type
->length
; i
++) {
2714 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2716 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2719 /* If the type is smaller than a vec4, replicate the last channel out. */
2720 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2721 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2723 this->result
.swizzle
= SWIZZLE_NOOP
;
2725 this->result
.index
+= offset
;
2726 this->result
.type
= ir
->type
->base_type
;
2730 * We want to be careful in assignment setup to hit the actual storage
2731 * instead of potentially using a temporary like we might with the
2732 * ir_dereference handler.
2735 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2737 /* The LHS must be a dereference. If the LHS is a variable indexed array
2738 * access of a vector, it must be separated into a series conditional moves
2739 * before reaching this point (see ir_vec_index_to_cond_assign).
2741 assert(ir
->as_dereference());
2742 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2744 assert(!deref_array
->array
->type
->is_vector());
2747 /* Use the rvalue deref handler for the most part. We write swizzles using
2748 * the writemask, but we do extract the base component for enhanced layouts
2749 * from the source swizzle.
2752 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2753 return st_dst_reg(v
->result
);
2757 * Process the condition of a conditional assignment
2759 * Examines the condition of a conditional assignment to generate the optimal
2760 * first operand of a \c CMP instruction. If the condition is a relational
2761 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2762 * used as the source for the \c CMP instruction. Otherwise the comparison
2763 * is processed to a boolean result, and the boolean result is used as the
2764 * operand to the CMP instruction.
2767 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2769 ir_rvalue
*src_ir
= ir
;
2771 bool switch_order
= false;
2773 ir_expression
*const expr
= ir
->as_expression();
2775 if (native_integers
) {
2776 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2777 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2778 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2779 type
== GLSL_TYPE_BOOL
) {
2780 if (expr
->operation
== ir_binop_equal
) {
2781 if (expr
->operands
[0]->is_zero()) {
2782 src_ir
= expr
->operands
[1];
2783 switch_order
= true;
2785 else if (expr
->operands
[1]->is_zero()) {
2786 src_ir
= expr
->operands
[0];
2787 switch_order
= true;
2790 else if (expr
->operation
== ir_binop_nequal
) {
2791 if (expr
->operands
[0]->is_zero()) {
2792 src_ir
= expr
->operands
[1];
2794 else if (expr
->operands
[1]->is_zero()) {
2795 src_ir
= expr
->operands
[0];
2801 src_ir
->accept(this);
2802 return switch_order
;
2805 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2806 bool zero_on_left
= false;
2808 if (expr
->operands
[0]->is_zero()) {
2809 src_ir
= expr
->operands
[1];
2810 zero_on_left
= true;
2811 } else if (expr
->operands
[1]->is_zero()) {
2812 src_ir
= expr
->operands
[0];
2813 zero_on_left
= false;
2817 * (a < 0) T F F ( a < 0) T F F
2818 * (0 < a) F F T (-a < 0) F F T
2819 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2820 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2821 * (a > 0) F F T (-a < 0) F F T
2822 * (0 > a) T F F ( a < 0) T F F
2823 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2824 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2826 * Note that exchanging the order of 0 and 'a' in the comparison simply
2827 * means that the value of 'a' should be negated.
2830 switch (expr
->operation
) {
2832 switch_order
= false;
2833 negate
= zero_on_left
;
2836 case ir_binop_greater
:
2837 switch_order
= false;
2838 negate
= !zero_on_left
;
2841 case ir_binop_lequal
:
2842 switch_order
= true;
2843 negate
= !zero_on_left
;
2846 case ir_binop_gequal
:
2847 switch_order
= true;
2848 negate
= zero_on_left
;
2852 /* This isn't the right kind of comparison afterall, so make sure
2853 * the whole condition is visited.
2861 src_ir
->accept(this);
2863 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2864 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2865 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2866 * computing the condition.
2869 this->result
.negate
= ~this->result
.negate
;
2871 return switch_order
;
2875 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2876 st_dst_reg
*l
, st_src_reg
*r
,
2877 st_src_reg
*cond
, bool cond_swap
)
2879 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2880 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2881 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2887 if (type
->is_array()) {
2888 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2889 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2894 if (type
->is_matrix()) {
2895 const struct glsl_type
*vec_type
;
2897 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2898 type
->vector_elements
, 1);
2900 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2901 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2906 assert(type
->is_scalar() || type
->is_vector());
2908 l
->type
= type
->base_type
;
2909 r
->type
= type
->base_type
;
2911 st_src_reg l_src
= st_src_reg(*l
);
2912 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2914 if (native_integers
) {
2915 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2916 cond_swap
? l_src
: *r
,
2917 cond_swap
? *r
: l_src
);
2919 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2920 cond_swap
? l_src
: *r
,
2921 cond_swap
? *r
: l_src
);
2924 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2928 if (type
->is_dual_slot()) {
2930 if (r
->is_double_vertex_input
== false)
2936 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2942 ir
->rhs
->accept(this);
2945 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2949 int first_enabled_chan
= 0;
2951 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2953 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2954 variable
->data
.mode
== ir_var_shader_out
&&
2955 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2956 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2957 assert(ir
->lhs
->type
->is_scalar());
2958 assert(ir
->write_mask
== WRITEMASK_X
);
2960 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2961 l
.writemask
= WRITEMASK_Z
;
2963 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2964 l
.writemask
= WRITEMASK_Y
;
2966 } else if (ir
->write_mask
== 0) {
2967 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2969 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2972 l
.writemask
= u_bit_consecutive(0, num_elements
);
2974 /* The type is a struct or an array of (array of) structs. */
2975 l
.writemask
= WRITEMASK_XYZW
;
2978 l
.writemask
= ir
->write_mask
;
2981 for (int i
= 0; i
< 4; i
++) {
2982 if (l
.writemask
& (1 << i
)) {
2983 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2988 l
.writemask
= l
.writemask
<< dst_component
;
2990 /* Swizzle a small RHS vector into the channels being written.
2992 * glsl ir treats write_mask as dictating how many channels are
2993 * present on the RHS while TGSI treats write_mask as just
2994 * showing which channels of the vec4 RHS get written.
2996 for (int i
= 0; i
< 4; i
++) {
2997 if (l
.writemask
& (1 << i
))
2998 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3000 swizzles
[i
] = first_enabled_chan
;
3002 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3003 swizzles
[2], swizzles
[3]);
3006 assert(l
.file
!= PROGRAM_UNDEFINED
);
3007 assert(r
.file
!= PROGRAM_UNDEFINED
);
3009 if (ir
->condition
) {
3010 const bool switch_order
= this->process_move_condition(ir
->condition
);
3011 st_src_reg condition
= this->result
;
3013 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3014 } else if (ir
->rhs
->as_expression() &&
3015 this->instructions
.get_tail() &&
3016 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3017 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3018 type_size(ir
->lhs
->type
) == 1 &&
3019 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3020 /* To avoid emitting an extra MOV when assigning an expression to a
3021 * variable, emit the last instruction of the expression again, but
3022 * replace the destination register with the target of the assignment.
3023 * Dead code elimination will remove the original instruction.
3025 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3026 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3027 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3028 new_inst
->saturate
= inst
->saturate
;
3029 inst
->dead_mask
= inst
->dst
[0].writemask
;
3031 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3037 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3040 GLdouble stack_vals
[4] = { 0 };
3041 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3042 GLenum gl_type
= GL_NONE
;
3044 static int in_array
= 0;
3045 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3047 /* Unfortunately, 4 floats is all we can get into
3048 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3049 * aggregate constant and move each constant value into it. If we
3050 * get lucky, copy propagation will eliminate the extra moves.
3052 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3053 st_src_reg temp_base
= get_temp(ir
->type
);
3054 st_dst_reg temp
= st_dst_reg(temp_base
);
3056 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3057 int size
= type_size(field_value
->type
);
3061 field_value
->accept(this);
3064 for (i
= 0; i
< (unsigned int)size
; i
++) {
3065 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3071 this->result
= temp_base
;
3075 if (ir
->type
->is_array()) {
3076 st_src_reg temp_base
= get_temp(ir
->type
);
3077 st_dst_reg temp
= st_dst_reg(temp_base
);
3078 int size
= type_size(ir
->type
->fields
.array
);
3083 for (i
= 0; i
< ir
->type
->length
; i
++) {
3084 ir
->array_elements
[i
]->accept(this);
3086 for (int j
= 0; j
< size
; j
++) {
3087 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3093 this->result
= temp_base
;
3098 if (ir
->type
->is_matrix()) {
3099 st_src_reg mat
= get_temp(ir
->type
);
3100 st_dst_reg mat_column
= st_dst_reg(mat
);
3102 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3103 switch (ir
->type
->base_type
) {
3104 case GLSL_TYPE_FLOAT
:
3105 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3107 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3108 src
.index
= add_constant(file
,
3110 ir
->type
->vector_elements
,
3113 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3115 case GLSL_TYPE_DOUBLE
:
3116 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3117 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3118 src
.index
= add_constant(file
,
3120 ir
->type
->vector_elements
,
3123 if (ir
->type
->vector_elements
>= 2) {
3124 mat_column
.writemask
= WRITEMASK_XY
;
3125 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3126 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3128 mat_column
.writemask
= WRITEMASK_X
;
3129 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3130 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3133 if (ir
->type
->vector_elements
> 2) {
3134 if (ir
->type
->vector_elements
== 4) {
3135 mat_column
.writemask
= WRITEMASK_ZW
;
3136 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3137 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3139 mat_column
.writemask
= WRITEMASK_Z
;
3140 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3141 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3142 mat_column
.writemask
= WRITEMASK_XYZW
;
3143 src
.swizzle
= SWIZZLE_XYZW
;
3149 unreachable("Illegal matrix constant type.\n");
3158 switch (ir
->type
->base_type
) {
3159 case GLSL_TYPE_FLOAT
:
3161 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3162 values
[i
].f
= ir
->value
.f
[i
];
3165 case GLSL_TYPE_DOUBLE
:
3166 gl_type
= GL_DOUBLE
;
3167 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3168 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3171 case GLSL_TYPE_UINT
:
3172 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3173 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3174 if (native_integers
)
3175 values
[i
].u
= ir
->value
.u
[i
];
3177 values
[i
].f
= ir
->value
.u
[i
];
3181 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3182 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3183 if (native_integers
)
3184 values
[i
].i
= ir
->value
.i
[i
];
3186 values
[i
].f
= ir
->value
.i
[i
];
3189 case GLSL_TYPE_BOOL
:
3190 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3191 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3192 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3196 assert(!"Non-float/uint/int/bool constant");
3199 this->result
= st_src_reg(file
, -1, ir
->type
);
3200 this->result
.index
= add_constant(file
,
3202 ir
->type
->vector_elements
,
3204 &this->result
.swizzle
);
3208 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3210 exec_node
*param
= ir
->actual_parameters
.get_head();
3211 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3212 ir_variable
*location
= deref
->variable_referenced();
3215 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3217 /* Calculate the surface offset */
3219 unsigned array_size
= 0, base
= 0;
3222 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3224 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3225 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3226 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3227 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3228 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3230 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3233 ir
->return_deref
->accept(this);
3234 st_dst_reg
dst(this->result
);
3235 dst
.writemask
= WRITEMASK_X
;
3237 glsl_to_tgsi_instruction
*inst
;
3239 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3240 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3241 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3242 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3243 st_src_reg_for_int(1));
3244 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3245 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3246 st_src_reg_for_int(-1));
3247 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3249 param
= param
->get_next();
3250 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3253 st_src_reg data
= this->result
, data2
= undef_src
;
3255 switch (ir
->callee
->intrinsic_id
) {
3256 case ir_intrinsic_atomic_counter_add
:
3257 opcode
= TGSI_OPCODE_ATOMUADD
;
3259 case ir_intrinsic_atomic_counter_min
:
3260 opcode
= TGSI_OPCODE_ATOMIMIN
;
3262 case ir_intrinsic_atomic_counter_max
:
3263 opcode
= TGSI_OPCODE_ATOMIMAX
;
3265 case ir_intrinsic_atomic_counter_and
:
3266 opcode
= TGSI_OPCODE_ATOMAND
;
3268 case ir_intrinsic_atomic_counter_or
:
3269 opcode
= TGSI_OPCODE_ATOMOR
;
3271 case ir_intrinsic_atomic_counter_xor
:
3272 opcode
= TGSI_OPCODE_ATOMXOR
;
3274 case ir_intrinsic_atomic_counter_exchange
:
3275 opcode
= TGSI_OPCODE_ATOMXCHG
;
3277 case ir_intrinsic_atomic_counter_comp_swap
: {
3278 opcode
= TGSI_OPCODE_ATOMCAS
;
3279 param
= param
->get_next();
3280 val
= ((ir_instruction
*)param
)->as_rvalue();
3282 data2
= this->result
;
3286 assert(!"Unexpected intrinsic");
3290 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3293 inst
->resource
= buffer
;
3297 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3299 exec_node
*param
= ir
->actual_parameters
.get_head();
3301 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3303 param
= param
->get_next();
3304 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3306 ir_constant
*const_block
= block
->as_constant();
3310 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3311 (const_block
? const_block
->value
.u
[0] : 0),
3315 block
->accept(this);
3316 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3317 *buffer
.reladdr
= this->result
;
3318 emit_arl(ir
, sampler_reladdr
, this->result
);
3321 /* Calculate the surface offset */
3322 offset
->accept(this);
3323 st_src_reg off
= this->result
;
3325 st_dst_reg dst
= undef_dst
;
3326 if (ir
->return_deref
) {
3327 ir
->return_deref
->accept(this);
3328 dst
= st_dst_reg(this->result
);
3329 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3332 glsl_to_tgsi_instruction
*inst
;
3334 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3335 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3336 if (dst
.type
== GLSL_TYPE_BOOL
)
3337 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3338 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3339 param
= param
->get_next();
3340 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3343 param
= param
->get_next();
3344 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3346 dst
.writemask
= write_mask
->value
.u
[0];
3348 dst
.type
= this->result
.type
;
3349 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3351 param
= param
->get_next();
3352 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3355 st_src_reg data
= this->result
, data2
= undef_src
;
3357 switch (ir
->callee
->intrinsic_id
) {
3358 case ir_intrinsic_ssbo_atomic_add
:
3359 opcode
= TGSI_OPCODE_ATOMUADD
;
3361 case ir_intrinsic_ssbo_atomic_min
:
3362 opcode
= TGSI_OPCODE_ATOMIMIN
;
3364 case ir_intrinsic_ssbo_atomic_max
:
3365 opcode
= TGSI_OPCODE_ATOMIMAX
;
3367 case ir_intrinsic_ssbo_atomic_and
:
3368 opcode
= TGSI_OPCODE_ATOMAND
;
3370 case ir_intrinsic_ssbo_atomic_or
:
3371 opcode
= TGSI_OPCODE_ATOMOR
;
3373 case ir_intrinsic_ssbo_atomic_xor
:
3374 opcode
= TGSI_OPCODE_ATOMXOR
;
3376 case ir_intrinsic_ssbo_atomic_exchange
:
3377 opcode
= TGSI_OPCODE_ATOMXCHG
;
3379 case ir_intrinsic_ssbo_atomic_comp_swap
:
3380 opcode
= TGSI_OPCODE_ATOMCAS
;
3381 param
= param
->get_next();
3382 val
= ((ir_instruction
*)param
)->as_rvalue();
3384 data2
= this->result
;
3387 assert(!"Unexpected intrinsic");
3391 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3394 param
= param
->get_next();
3395 ir_constant
*access
= NULL
;
3396 if (!param
->is_tail_sentinel()) {
3397 access
= ((ir_instruction
*)param
)->as_constant();
3401 /* The emit_asm() might have actually split the op into pieces, e.g. for
3402 * double stores. We have to go back and fix up all the generated ops.
3404 unsigned op
= inst
->op
;
3406 inst
->resource
= buffer
;
3408 inst
->buffer_access
= access
->value
.u
[0];
3409 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3410 if (inst
->op
== TGSI_OPCODE_UADD
)
3411 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3412 } while (inst
&& inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3416 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3418 switch (ir
->callee
->intrinsic_id
) {
3419 case ir_intrinsic_memory_barrier
:
3420 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3421 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3422 TGSI_MEMBAR_ATOMIC_BUFFER
|
3423 TGSI_MEMBAR_SHADER_IMAGE
|
3424 TGSI_MEMBAR_SHARED
));
3426 case ir_intrinsic_memory_barrier_atomic_counter
:
3427 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3428 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3430 case ir_intrinsic_memory_barrier_buffer
:
3431 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3432 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3434 case ir_intrinsic_memory_barrier_image
:
3435 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3436 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3438 case ir_intrinsic_memory_barrier_shared
:
3439 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3440 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3442 case ir_intrinsic_group_memory_barrier
:
3443 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3444 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3445 TGSI_MEMBAR_ATOMIC_BUFFER
|
3446 TGSI_MEMBAR_SHADER_IMAGE
|
3447 TGSI_MEMBAR_SHARED
|
3448 TGSI_MEMBAR_THREAD_GROUP
));
3451 assert(!"Unexpected memory barrier intrinsic");
3456 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3458 exec_node
*param
= ir
->actual_parameters
.get_head();
3460 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3462 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3464 /* Calculate the surface offset */
3465 offset
->accept(this);
3466 st_src_reg off
= this->result
;
3468 st_dst_reg dst
= undef_dst
;
3469 if (ir
->return_deref
) {
3470 ir
->return_deref
->accept(this);
3471 dst
= st_dst_reg(this->result
);
3472 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3475 glsl_to_tgsi_instruction
*inst
;
3477 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3478 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3479 inst
->resource
= buffer
;
3480 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3481 param
= param
->get_next();
3482 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3485 param
= param
->get_next();
3486 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3488 dst
.writemask
= write_mask
->value
.u
[0];
3490 dst
.type
= this->result
.type
;
3491 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3492 inst
->resource
= buffer
;
3494 param
= param
->get_next();
3495 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3498 st_src_reg data
= this->result
, data2
= undef_src
;
3500 switch (ir
->callee
->intrinsic_id
) {
3501 case ir_intrinsic_shared_atomic_add
:
3502 opcode
= TGSI_OPCODE_ATOMUADD
;
3504 case ir_intrinsic_shared_atomic_min
:
3505 opcode
= TGSI_OPCODE_ATOMIMIN
;
3507 case ir_intrinsic_shared_atomic_max
:
3508 opcode
= TGSI_OPCODE_ATOMIMAX
;
3510 case ir_intrinsic_shared_atomic_and
:
3511 opcode
= TGSI_OPCODE_ATOMAND
;
3513 case ir_intrinsic_shared_atomic_or
:
3514 opcode
= TGSI_OPCODE_ATOMOR
;
3516 case ir_intrinsic_shared_atomic_xor
:
3517 opcode
= TGSI_OPCODE_ATOMXOR
;
3519 case ir_intrinsic_shared_atomic_exchange
:
3520 opcode
= TGSI_OPCODE_ATOMXCHG
;
3522 case ir_intrinsic_shared_atomic_comp_swap
:
3523 opcode
= TGSI_OPCODE_ATOMCAS
;
3524 param
= param
->get_next();
3525 val
= ((ir_instruction
*)param
)->as_rvalue();
3527 data2
= this->result
;
3530 assert(!"Unexpected intrinsic");
3534 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3535 inst
->resource
= buffer
;
3540 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3542 exec_node
*param
= ir
->actual_parameters
.get_head();
3544 ir_dereference
*img
= (ir_dereference
*)param
;
3545 const ir_variable
*imgvar
= img
->variable_referenced();
3546 const glsl_type
*type
= imgvar
->type
->without_array();
3547 unsigned sampler_array_size
= 1, sampler_base
= 0;
3550 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3552 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3553 (uint16_t*)&image
.index
, &reladdr
, true);
3555 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3556 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3557 *image
.reladdr
= reladdr
;
3558 emit_arl(ir
, sampler_reladdr
, reladdr
);
3561 st_dst_reg dst
= undef_dst
;
3562 if (ir
->return_deref
) {
3563 ir
->return_deref
->accept(this);
3564 dst
= st_dst_reg(this->result
);
3565 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3568 glsl_to_tgsi_instruction
*inst
;
3570 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3571 dst
.writemask
= WRITEMASK_XYZ
;
3572 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3573 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3574 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3575 st_dst_reg dstres
= st_dst_reg(res
);
3576 dstres
.writemask
= WRITEMASK_W
;
3577 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3578 res
.swizzle
= SWIZZLE_WWWW
;
3579 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3581 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3583 st_dst_reg coord_dst
;
3584 coord
= get_temp(glsl_type::ivec4_type
);
3585 coord_dst
= st_dst_reg(coord
);
3586 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3587 param
= param
->get_next();
3588 ((ir_dereference
*)param
)->accept(this);
3589 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3590 coord
.swizzle
= SWIZZLE_XXXX
;
3591 switch (type
->coordinate_components()) {
3592 case 4: assert(!"unexpected coord count");
3594 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3596 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3599 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3600 param
= param
->get_next();
3601 ((ir_dereference
*)param
)->accept(this);
3602 st_src_reg sample
= this->result
;
3603 sample
.swizzle
= SWIZZLE_XXXX
;
3604 coord_dst
.writemask
= WRITEMASK_W
;
3605 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3606 coord
.swizzle
|= SWIZZLE_W
<< 9;
3609 param
= param
->get_next();
3610 if (!param
->is_tail_sentinel()) {
3611 ((ir_dereference
*)param
)->accept(this);
3612 arg1
= this->result
;
3613 param
= param
->get_next();
3616 if (!param
->is_tail_sentinel()) {
3617 ((ir_dereference
*)param
)->accept(this);
3618 arg2
= this->result
;
3619 param
= param
->get_next();
3622 assert(param
->is_tail_sentinel());
3625 switch (ir
->callee
->intrinsic_id
) {
3626 case ir_intrinsic_image_load
:
3627 opcode
= TGSI_OPCODE_LOAD
;
3629 case ir_intrinsic_image_store
:
3630 opcode
= TGSI_OPCODE_STORE
;
3632 case ir_intrinsic_image_atomic_add
:
3633 opcode
= TGSI_OPCODE_ATOMUADD
;
3635 case ir_intrinsic_image_atomic_min
:
3636 opcode
= TGSI_OPCODE_ATOMIMIN
;
3638 case ir_intrinsic_image_atomic_max
:
3639 opcode
= TGSI_OPCODE_ATOMIMAX
;
3641 case ir_intrinsic_image_atomic_and
:
3642 opcode
= TGSI_OPCODE_ATOMAND
;
3644 case ir_intrinsic_image_atomic_or
:
3645 opcode
= TGSI_OPCODE_ATOMOR
;
3647 case ir_intrinsic_image_atomic_xor
:
3648 opcode
= TGSI_OPCODE_ATOMXOR
;
3650 case ir_intrinsic_image_atomic_exchange
:
3651 opcode
= TGSI_OPCODE_ATOMXCHG
;
3653 case ir_intrinsic_image_atomic_comp_swap
:
3654 opcode
= TGSI_OPCODE_ATOMCAS
;
3657 assert(!"Unexpected intrinsic");
3661 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3662 if (opcode
== TGSI_OPCODE_STORE
)
3663 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3666 inst
->resource
= image
;
3667 inst
->sampler_array_size
= sampler_array_size
;
3668 inst
->sampler_base
= sampler_base
;
3670 switch (type
->sampler_dimensionality
) {
3671 case GLSL_SAMPLER_DIM_1D
:
3672 inst
->tex_target
= (type
->sampler_array
)
3673 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3675 case GLSL_SAMPLER_DIM_2D
:
3676 inst
->tex_target
= (type
->sampler_array
)
3677 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3679 case GLSL_SAMPLER_DIM_3D
:
3680 inst
->tex_target
= TEXTURE_3D_INDEX
;
3682 case GLSL_SAMPLER_DIM_CUBE
:
3683 inst
->tex_target
= (type
->sampler_array
)
3684 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3686 case GLSL_SAMPLER_DIM_RECT
:
3687 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3689 case GLSL_SAMPLER_DIM_BUF
:
3690 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3692 case GLSL_SAMPLER_DIM_EXTERNAL
:
3693 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3695 case GLSL_SAMPLER_DIM_MS
:
3696 inst
->tex_target
= (type
->sampler_array
)
3697 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3700 assert(!"Should not get here.");
3703 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3704 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3706 if (imgvar
->data
.image_coherent
)
3707 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3708 if (imgvar
->data
.image_restrict
)
3709 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3710 if (imgvar
->data
.image_volatile
)
3711 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3715 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3717 ir_function_signature
*sig
= ir
->callee
;
3719 /* Filter out intrinsics */
3720 switch (sig
->intrinsic_id
) {
3721 case ir_intrinsic_atomic_counter_read
:
3722 case ir_intrinsic_atomic_counter_increment
:
3723 case ir_intrinsic_atomic_counter_predecrement
:
3724 case ir_intrinsic_atomic_counter_add
:
3725 case ir_intrinsic_atomic_counter_min
:
3726 case ir_intrinsic_atomic_counter_max
:
3727 case ir_intrinsic_atomic_counter_and
:
3728 case ir_intrinsic_atomic_counter_or
:
3729 case ir_intrinsic_atomic_counter_xor
:
3730 case ir_intrinsic_atomic_counter_exchange
:
3731 case ir_intrinsic_atomic_counter_comp_swap
:
3732 visit_atomic_counter_intrinsic(ir
);
3735 case ir_intrinsic_ssbo_load
:
3736 case ir_intrinsic_ssbo_store
:
3737 case ir_intrinsic_ssbo_atomic_add
:
3738 case ir_intrinsic_ssbo_atomic_min
:
3739 case ir_intrinsic_ssbo_atomic_max
:
3740 case ir_intrinsic_ssbo_atomic_and
:
3741 case ir_intrinsic_ssbo_atomic_or
:
3742 case ir_intrinsic_ssbo_atomic_xor
:
3743 case ir_intrinsic_ssbo_atomic_exchange
:
3744 case ir_intrinsic_ssbo_atomic_comp_swap
:
3745 visit_ssbo_intrinsic(ir
);
3748 case ir_intrinsic_memory_barrier
:
3749 case ir_intrinsic_memory_barrier_atomic_counter
:
3750 case ir_intrinsic_memory_barrier_buffer
:
3751 case ir_intrinsic_memory_barrier_image
:
3752 case ir_intrinsic_memory_barrier_shared
:
3753 case ir_intrinsic_group_memory_barrier
:
3754 visit_membar_intrinsic(ir
);
3757 case ir_intrinsic_shared_load
:
3758 case ir_intrinsic_shared_store
:
3759 case ir_intrinsic_shared_atomic_add
:
3760 case ir_intrinsic_shared_atomic_min
:
3761 case ir_intrinsic_shared_atomic_max
:
3762 case ir_intrinsic_shared_atomic_and
:
3763 case ir_intrinsic_shared_atomic_or
:
3764 case ir_intrinsic_shared_atomic_xor
:
3765 case ir_intrinsic_shared_atomic_exchange
:
3766 case ir_intrinsic_shared_atomic_comp_swap
:
3767 visit_shared_intrinsic(ir
);
3770 case ir_intrinsic_image_load
:
3771 case ir_intrinsic_image_store
:
3772 case ir_intrinsic_image_atomic_add
:
3773 case ir_intrinsic_image_atomic_min
:
3774 case ir_intrinsic_image_atomic_max
:
3775 case ir_intrinsic_image_atomic_and
:
3776 case ir_intrinsic_image_atomic_or
:
3777 case ir_intrinsic_image_atomic_xor
:
3778 case ir_intrinsic_image_atomic_exchange
:
3779 case ir_intrinsic_image_atomic_comp_swap
:
3780 case ir_intrinsic_image_size
:
3781 case ir_intrinsic_image_samples
:
3782 visit_image_intrinsic(ir
);
3785 case ir_intrinsic_invalid
:
3786 case ir_intrinsic_generic_load
:
3787 case ir_intrinsic_generic_store
:
3788 case ir_intrinsic_generic_atomic_add
:
3789 case ir_intrinsic_generic_atomic_and
:
3790 case ir_intrinsic_generic_atomic_or
:
3791 case ir_intrinsic_generic_atomic_xor
:
3792 case ir_intrinsic_generic_atomic_min
:
3793 case ir_intrinsic_generic_atomic_max
:
3794 case ir_intrinsic_generic_atomic_exchange
:
3795 case ir_intrinsic_generic_atomic_comp_swap
:
3796 case ir_intrinsic_shader_clock
:
3797 unreachable("Invalid intrinsic");
3802 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3803 unsigned *array_elements
,
3805 st_src_reg
*indirect
,
3808 switch (tail
->ir_type
) {
3809 case ir_type_dereference_record
: {
3810 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3811 const glsl_type
*struct_type
= deref_record
->record
->type
;
3812 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3814 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3816 assert(field_index
>= 0);
3817 *location
+= struct_type
->record_location_offset(field_index
);
3821 case ir_type_dereference_array
: {
3822 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3823 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3826 st_src_reg temp_reg
;
3827 st_dst_reg temp_dst
;
3829 temp_reg
= get_temp(glsl_type::uint_type
);
3830 temp_dst
= st_dst_reg(temp_reg
);
3831 temp_dst
.writemask
= 1;
3833 deref_arr
->array_index
->accept(this);
3834 if (*array_elements
!= 1)
3835 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3837 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3839 if (indirect
->file
== PROGRAM_UNDEFINED
)
3840 *indirect
= temp_reg
;
3842 temp_dst
= st_dst_reg(*indirect
);
3843 temp_dst
.writemask
= 1;
3844 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3847 *index
+= array_index
->value
.u
[0] * *array_elements
;
3849 *array_elements
*= deref_arr
->array
->type
->length
;
3851 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3860 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3861 unsigned *array_size
,
3864 st_src_reg
*reladdr
,
3867 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3868 unsigned location
= 0;
3869 ir_variable
*var
= ir
->variable_referenced();
3871 memset(reladdr
, 0, sizeof(*reladdr
));
3872 reladdr
->file
= PROGRAM_UNDEFINED
;
3878 location
= var
->data
.location
;
3879 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3882 * If we end up with no indirect then adjust the base to the index,
3883 * and set the array size to 1.
3885 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3891 assert(location
!= 0xffffffff);
3892 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3893 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3898 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3900 if (offset
.reladdr
|| offset
.reladdr2
) {
3901 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3902 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3903 tmp_dst
.writemask
= WRITEMASK_XY
;
3904 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
3912 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3914 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3915 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3916 st_src_reg levels_src
, reladdr
;
3917 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3918 glsl_to_tgsi_instruction
*inst
= NULL
;
3919 unsigned opcode
= TGSI_OPCODE_NOP
;
3920 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3921 unsigned sampler_array_size
= 1, sampler_base
= 0;
3922 uint16_t sampler_index
= 0;
3923 bool is_cube_array
= false;
3926 /* if we are a cube array sampler */
3927 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3928 sampler_type
->sampler_array
)) {
3929 is_cube_array
= true;
3932 if (ir
->coordinate
) {
3933 ir
->coordinate
->accept(this);
3935 /* Put our coords in a temp. We'll need to modify them for shadow,
3936 * projection, or LOD, so the only case we'd use it as-is is if
3937 * we're doing plain old texturing. The optimization passes on
3938 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3940 coord
= get_temp(glsl_type::vec4_type
);
3941 coord_dst
= st_dst_reg(coord
);
3942 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3943 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3946 if (ir
->projector
) {
3947 ir
->projector
->accept(this);
3948 projector
= this->result
;
3951 /* Storage for our result. Ideally for an assignment we'd be using
3952 * the actual storage for the result here, instead.
3954 result_src
= get_temp(ir
->type
);
3955 result_dst
= st_dst_reg(result_src
);
3959 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3961 ir
->offset
->accept(this);
3962 offset
[0] = this->result
;
3966 if (is_cube_array
||
3967 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3968 opcode
= TGSI_OPCODE_TXB2
;
3971 opcode
= TGSI_OPCODE_TXB
;
3973 ir
->lod_info
.bias
->accept(this);
3974 lod_info
= this->result
;
3976 ir
->offset
->accept(this);
3977 offset
[0] = this->result
;
3981 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3982 ir
->lod_info
.lod
->accept(this);
3983 lod_info
= this->result
;
3985 ir
->offset
->accept(this);
3986 offset
[0] = this->result
;
3990 opcode
= TGSI_OPCODE_TXD
;
3991 ir
->lod_info
.grad
.dPdx
->accept(this);
3993 ir
->lod_info
.grad
.dPdy
->accept(this);
3996 ir
->offset
->accept(this);
3997 offset
[0] = this->result
;
4001 opcode
= TGSI_OPCODE_TXQ
;
4002 ir
->lod_info
.lod
->accept(this);
4003 lod_info
= this->result
;
4005 case ir_query_levels
:
4006 opcode
= TGSI_OPCODE_TXQ
;
4007 lod_info
= undef_src
;
4008 levels_src
= get_temp(ir
->type
);
4011 opcode
= TGSI_OPCODE_TXF
;
4012 ir
->lod_info
.lod
->accept(this);
4013 lod_info
= this->result
;
4015 ir
->offset
->accept(this);
4016 offset
[0] = this->result
;
4020 opcode
= TGSI_OPCODE_TXF
;
4021 ir
->lod_info
.sample_index
->accept(this);
4022 sample_index
= this->result
;
4025 opcode
= TGSI_OPCODE_TG4
;
4026 ir
->lod_info
.component
->accept(this);
4027 component
= this->result
;
4029 ir
->offset
->accept(this);
4030 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4031 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4032 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4033 offset
[i
] = this->result
;
4034 offset
[i
].index
+= i
* type_size(elt_type
);
4035 offset
[i
].type
= elt_type
->base_type
;
4036 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4037 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4040 offset
[0] = canonicalize_gather_offset(this->result
);
4045 opcode
= TGSI_OPCODE_LODQ
;
4047 case ir_texture_samples
:
4048 opcode
= TGSI_OPCODE_TXQS
;
4050 case ir_samples_identical
:
4051 unreachable("Unexpected ir_samples_identical opcode");
4054 if (ir
->projector
) {
4055 if (opcode
== TGSI_OPCODE_TEX
) {
4056 /* Slot the projector in as the last component of the coord. */
4057 coord_dst
.writemask
= WRITEMASK_W
;
4058 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4059 coord_dst
.writemask
= WRITEMASK_XYZW
;
4060 opcode
= TGSI_OPCODE_TXP
;
4062 st_src_reg coord_w
= coord
;
4063 coord_w
.swizzle
= SWIZZLE_WWWW
;
4065 /* For the other TEX opcodes there's no projective version
4066 * since the last slot is taken up by LOD info. Do the
4067 * projective divide now.
4069 coord_dst
.writemask
= WRITEMASK_W
;
4070 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4072 /* In the case where we have to project the coordinates "by hand,"
4073 * the shadow comparator value must also be projected.
4075 st_src_reg tmp_src
= coord
;
4076 if (ir
->shadow_comparator
) {
4077 /* Slot the shadow value in as the second to last component of the
4080 ir
->shadow_comparator
->accept(this);
4082 tmp_src
= get_temp(glsl_type::vec4_type
);
4083 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4085 /* Projective division not allowed for array samplers. */
4086 assert(!sampler_type
->sampler_array
);
4088 tmp_dst
.writemask
= WRITEMASK_Z
;
4089 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4091 tmp_dst
.writemask
= WRITEMASK_XY
;
4092 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4095 coord_dst
.writemask
= WRITEMASK_XYZ
;
4096 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4098 coord_dst
.writemask
= WRITEMASK_XYZW
;
4099 coord
.swizzle
= SWIZZLE_XYZW
;
4103 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4104 * comparator was put in the correct place (and projected) by the code,
4105 * above, that handles by-hand projection.
4107 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4108 /* Slot the shadow value in as the second to last component of the
4111 ir
->shadow_comparator
->accept(this);
4113 if (is_cube_array
) {
4114 cube_sc
= get_temp(glsl_type::float_type
);
4115 cube_sc_dst
= st_dst_reg(cube_sc
);
4116 cube_sc_dst
.writemask
= WRITEMASK_X
;
4117 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4118 cube_sc_dst
.writemask
= WRITEMASK_X
;
4121 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4122 sampler_type
->sampler_array
) ||
4123 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4124 coord_dst
.writemask
= WRITEMASK_W
;
4126 coord_dst
.writemask
= WRITEMASK_Z
;
4128 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4129 coord_dst
.writemask
= WRITEMASK_XYZW
;
4133 if (ir
->op
== ir_txf_ms
) {
4134 coord_dst
.writemask
= WRITEMASK_W
;
4135 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4136 coord_dst
.writemask
= WRITEMASK_XYZW
;
4137 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4138 opcode
== TGSI_OPCODE_TXF
) {
4139 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4140 coord_dst
.writemask
= WRITEMASK_W
;
4141 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4142 coord_dst
.writemask
= WRITEMASK_XYZW
;
4145 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4146 &sampler_index
, &reladdr
, true);
4147 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4148 emit_arl(ir
, sampler_reladdr
, reladdr
);
4150 if (opcode
== TGSI_OPCODE_TXD
)
4151 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4152 else if (opcode
== TGSI_OPCODE_TXQ
) {
4153 if (ir
->op
== ir_query_levels
) {
4154 /* the level is stored in W */
4155 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4156 result_dst
.writemask
= WRITEMASK_X
;
4157 levels_src
.swizzle
= SWIZZLE_WWWW
;
4158 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4160 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4161 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4162 inst
= emit_asm(ir
, opcode
, result_dst
);
4163 } else if (opcode
== TGSI_OPCODE_TXF
) {
4164 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4165 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4166 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4167 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4168 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4169 } else if (opcode
== TGSI_OPCODE_TG4
) {
4170 if (is_cube_array
&& ir
->shadow_comparator
) {
4171 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4173 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4176 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4178 if (ir
->shadow_comparator
)
4179 inst
->tex_shadow
= GL_TRUE
;
4181 inst
->resource
.index
= sampler_index
;
4182 inst
->sampler_array_size
= sampler_array_size
;
4183 inst
->sampler_base
= sampler_base
;
4185 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4186 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4187 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4191 if (!inst
->tex_offsets
)
4192 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4194 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4195 inst
->tex_offsets
[i
] = offset
[i
];
4196 inst
->tex_offset_num_offset
= i
;
4199 switch (sampler_type
->sampler_dimensionality
) {
4200 case GLSL_SAMPLER_DIM_1D
:
4201 inst
->tex_target
= (sampler_type
->sampler_array
)
4202 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4204 case GLSL_SAMPLER_DIM_2D
:
4205 inst
->tex_target
= (sampler_type
->sampler_array
)
4206 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4208 case GLSL_SAMPLER_DIM_3D
:
4209 inst
->tex_target
= TEXTURE_3D_INDEX
;
4211 case GLSL_SAMPLER_DIM_CUBE
:
4212 inst
->tex_target
= (sampler_type
->sampler_array
)
4213 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4215 case GLSL_SAMPLER_DIM_RECT
:
4216 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4218 case GLSL_SAMPLER_DIM_BUF
:
4219 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4221 case GLSL_SAMPLER_DIM_EXTERNAL
:
4222 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4224 case GLSL_SAMPLER_DIM_MS
:
4225 inst
->tex_target
= (sampler_type
->sampler_array
)
4226 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4229 assert(!"Should not get here.");
4232 inst
->tex_type
= ir
->type
->base_type
;
4234 this->result
= result_src
;
4238 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4240 assert(!ir
->get_value());
4242 emit_asm(ir
, TGSI_OPCODE_RET
);
4246 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4248 if (ir
->condition
) {
4249 ir
->condition
->accept(this);
4250 st_src_reg condition
= this->result
;
4252 /* Convert the bool condition to a float so we can negate. */
4253 if (native_integers
) {
4254 st_src_reg temp
= get_temp(ir
->condition
->type
);
4255 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4256 condition
, st_src_reg_for_float(1.0));
4260 condition
.negate
= ~condition
.negate
;
4261 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4263 /* unconditional kil */
4264 emit_asm(ir
, TGSI_OPCODE_KILL
);
4269 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4272 glsl_to_tgsi_instruction
*if_inst
;
4274 ir
->condition
->accept(this);
4275 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4277 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4279 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4281 this->instructions
.push_tail(if_inst
);
4283 visit_exec_list(&ir
->then_instructions
, this);
4285 if (!ir
->else_instructions
.is_empty()) {
4286 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4287 visit_exec_list(&ir
->else_instructions
, this);
4290 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4295 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4297 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4299 ir
->stream
->accept(this);
4300 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4304 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4306 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4308 ir
->stream
->accept(this);
4309 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4313 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4315 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4316 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4318 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4321 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4323 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4325 result
.file
= PROGRAM_UNDEFINED
;
4332 num_input_arrays
= 0;
4333 num_output_arrays
= 0;
4335 num_address_regs
= 0;
4339 indirect_addr_consts
= false;
4340 wpos_transform_const
= -1;
4342 native_integers
= false;
4343 mem_ctx
= ralloc_context(NULL
);
4346 shader_program
= NULL
;
4351 use_shared_memory
= false;
4354 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4357 ralloc_free(mem_ctx
);
4360 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4367 * Count resources used by the given gpu program (number of texture
4371 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4373 v
->samplers_used
= 0;
4374 v
->buffers_used
= 0;
4377 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4378 if (inst
->info
->is_tex
) {
4379 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4380 unsigned idx
= inst
->sampler_base
+ i
;
4381 v
->samplers_used
|= 1u << idx
;
4383 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4384 v
->sampler_types
[idx
] = inst
->tex_type
;
4385 v
->sampler_targets
[idx
] =
4386 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4388 if (inst
->tex_shadow
) {
4389 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4394 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4395 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4397 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4398 is_resource_instruction(inst
->op
) ||
4399 inst
->op
== TGSI_OPCODE_STORE
)) {
4400 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4401 v
->buffers_used
|= 1 << inst
->resource
.index
;
4402 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4403 v
->use_shared_memory
= true;
4405 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4406 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4407 unsigned idx
= inst
->sampler_base
+ i
;
4408 v
->images_used
|= 1 << idx
;
4409 v
->image_targets
[idx
] =
4410 st_translate_texture_target(inst
->tex_target
, false);
4411 v
->image_formats
[idx
] = inst
->image_format
;
4416 prog
->SamplersUsed
= v
->samplers_used
;
4418 if (v
->shader_program
!= NULL
)
4419 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4423 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4424 * are read from the given src in this instruction
4427 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4429 int read_mask
= 0, comp
;
4431 /* Now, given the src swizzle and the written channels, find which
4432 * components are actually read
4434 for (comp
= 0; comp
< 4; ++comp
) {
4435 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4437 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4438 read_mask
|= 1 << coord
;
4445 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4446 * instruction is the first instruction to write to register T0. There are
4447 * several lowering passes done in GLSL IR (e.g. branches and
4448 * relative addressing) that create a large number of conditional assignments
4449 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4451 * Here is why this conversion is safe:
4452 * CMP T0, T1 T2 T0 can be expanded to:
4458 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4459 * as the original program. If (T1 < 0.0) evaluates to false, executing
4460 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4461 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4462 * because any instruction that was going to read from T0 after this was going
4463 * to read a garbage value anyway.
4466 glsl_to_tgsi_visitor::simplify_cmp(void)
4468 int tempWritesSize
= 0;
4469 unsigned *tempWrites
= NULL
;
4470 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4472 memset(outputWrites
, 0, sizeof(outputWrites
));
4474 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4475 unsigned prevWriteMask
= 0;
4477 /* Give up if we encounter relative addressing or flow control. */
4478 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4479 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4480 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4481 inst
->op
== TGSI_OPCODE_CONT
||
4482 inst
->op
== TGSI_OPCODE_END
||
4483 inst
->op
== TGSI_OPCODE_RET
) {
4487 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4488 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4489 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4490 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4491 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4492 if (inst
->dst
[0].index
>= tempWritesSize
) {
4493 const int inc
= 4096;
4495 tempWrites
= (unsigned*)
4497 (tempWritesSize
+ inc
) * sizeof(unsigned));
4501 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4502 tempWritesSize
+= inc
;
4505 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4506 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4510 /* For a CMP to be considered a conditional write, the destination
4511 * register and source register two must be the same. */
4512 if (inst
->op
== TGSI_OPCODE_CMP
4513 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4514 && inst
->src
[2].file
== inst
->dst
[0].file
4515 && inst
->src
[2].index
== inst
->dst
[0].index
4516 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4518 inst
->op
= TGSI_OPCODE_MOV
;
4519 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4520 inst
->src
[0] = inst
->src
[1];
4527 /* Replaces all references to a temporary register index with another index. */
4529 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4531 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4534 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4535 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4536 for (k
= 0; k
< num_renames
; k
++)
4537 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4538 inst
->src
[j
].index
= renames
[k
].new_reg
;
4541 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4542 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4543 for (k
= 0; k
< num_renames
; k
++)
4544 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4545 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4548 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4549 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4550 for (k
= 0; k
< num_renames
; k
++)
4551 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4552 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4558 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4560 int depth
= 0; /* loop depth */
4561 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4564 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4565 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4566 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4567 if (first_reads
[inst
->src
[j
].index
] == -1)
4568 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4571 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4572 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4573 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4574 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4577 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4580 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4590 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4592 int depth
= 0; /* loop depth */
4593 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4596 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4597 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4598 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4599 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4601 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4602 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4603 if (first_writes
[inst
->dst
[j
].index
] == -1)
4604 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4605 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4608 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4609 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4610 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4612 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4615 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4618 for (k
= 0; k
< this->next_temp
; k
++) {
4619 if (last_reads
[k
] == -2) {
4631 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4633 int depth
= 0; /* loop depth */
4637 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4638 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4639 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4640 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4643 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4645 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4647 for (k
= 0; k
< this->next_temp
; k
++) {
4648 if (last_writes
[k
] == -2) {
4659 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4660 * channels for copy propagation and updates following instructions to
4661 * use the original versions.
4663 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4664 * will occur. As an example, a TXP production before this pass:
4666 * 0: MOV TEMP[1], INPUT[4].xyyy;
4667 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4668 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4672 * 0: MOV TEMP[1], INPUT[4].xyyy;
4673 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4674 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4676 * which allows for dead code elimination on TEMP[1]'s writes.
4679 glsl_to_tgsi_visitor::copy_propagate(void)
4681 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4682 glsl_to_tgsi_instruction
*,
4683 this->next_temp
* 4);
4684 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4687 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4688 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4689 || inst
->dst
[0].index
< this->next_temp
);
4691 /* First, do any copy propagation possible into the src regs. */
4692 for (int r
= 0; r
< 3; r
++) {
4693 glsl_to_tgsi_instruction
*first
= NULL
;
4695 int acp_base
= inst
->src
[r
].index
* 4;
4697 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4698 inst
->src
[r
].reladdr
||
4699 inst
->src
[r
].reladdr2
)
4702 /* See if we can find entries in the ACP consisting of MOVs
4703 * from the same src register for all the swizzled channels
4704 * of this src register reference.
4706 for (int i
= 0; i
< 4; i
++) {
4707 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4708 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4715 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4720 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4721 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4722 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4723 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4731 /* We've now validated that we can copy-propagate to
4732 * replace this src register reference. Do it.
4734 inst
->src
[r
].file
= first
->src
[0].file
;
4735 inst
->src
[r
].index
= first
->src
[0].index
;
4736 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4737 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4738 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4739 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4742 for (int i
= 0; i
< 4; i
++) {
4743 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4744 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4745 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4747 inst
->src
[r
].swizzle
= swizzle
;
4752 case TGSI_OPCODE_BGNLOOP
:
4753 case TGSI_OPCODE_ENDLOOP
:
4754 /* End of a basic block, clear the ACP entirely. */
4755 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4758 case TGSI_OPCODE_IF
:
4759 case TGSI_OPCODE_UIF
:
4763 case TGSI_OPCODE_ENDIF
:
4764 case TGSI_OPCODE_ELSE
:
4765 /* Clear all channels written inside the block from the ACP, but
4766 * leaving those that were not touched.
4768 for (int r
= 0; r
< this->next_temp
; r
++) {
4769 for (int c
= 0; c
< 4; c
++) {
4770 if (!acp
[4 * r
+ c
])
4773 if (acp_level
[4 * r
+ c
] >= level
)
4774 acp
[4 * r
+ c
] = NULL
;
4777 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4782 /* Continuing the block, clear any written channels from
4785 for (int d
= 0; d
< 2; d
++) {
4786 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4787 /* Any temporary might be written, so no copy propagation
4788 * across this instruction.
4790 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4791 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4792 inst
->dst
[d
].reladdr
) {
4793 /* Any output might be written, so no copy propagation
4794 * from outputs across this instruction.
4796 for (int r
= 0; r
< this->next_temp
; r
++) {
4797 for (int c
= 0; c
< 4; c
++) {
4798 if (!acp
[4 * r
+ c
])
4801 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4802 acp
[4 * r
+ c
] = NULL
;
4805 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4806 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4807 /* Clear where it's used as dst. */
4808 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4809 for (int c
= 0; c
< 4; c
++) {
4810 if (inst
->dst
[d
].writemask
& (1 << c
))
4811 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4815 /* Clear where it's used as src. */
4816 for (int r
= 0; r
< this->next_temp
; r
++) {
4817 for (int c
= 0; c
< 4; c
++) {
4818 if (!acp
[4 * r
+ c
])
4821 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4823 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4824 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4825 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4826 acp
[4 * r
+ c
] = NULL
;
4835 /* If this is a copy, add it to the ACP. */
4836 if (inst
->op
== TGSI_OPCODE_MOV
&&
4837 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4838 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4839 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4840 !inst
->dst
[0].reladdr
&&
4841 !inst
->dst
[0].reladdr2
&&
4843 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4844 !inst
->src
[0].reladdr
&&
4845 !inst
->src
[0].reladdr2
&&
4846 !inst
->src
[0].negate
) {
4847 for (int i
= 0; i
< 4; i
++) {
4848 if (inst
->dst
[0].writemask
& (1 << i
)) {
4849 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4850 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4856 ralloc_free(acp_level
);
4861 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4864 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4865 * will occur. As an example, a TXP production after copy propagation but
4868 * 0: MOV TEMP[1], INPUT[4].xyyy;
4869 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4870 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4872 * and after this pass:
4874 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4877 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4879 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4880 glsl_to_tgsi_instruction
*,
4881 this->next_temp
* 4);
4882 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4886 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4887 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4888 || inst
->dst
[0].index
< this->next_temp
);
4891 case TGSI_OPCODE_BGNLOOP
:
4892 case TGSI_OPCODE_ENDLOOP
:
4893 case TGSI_OPCODE_CONT
:
4894 case TGSI_OPCODE_BRK
:
4895 /* End of a basic block, clear the write array entirely.
4897 * This keeps us from killing dead code when the writes are
4898 * on either side of a loop, even when the register isn't touched
4899 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4900 * dead code of this type, so it shouldn't make a difference as long as
4901 * the dead code elimination pass in the GLSL compiler does its job.
4903 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4906 case TGSI_OPCODE_ENDIF
:
4907 case TGSI_OPCODE_ELSE
:
4908 /* Promote the recorded level of all channels written inside the
4909 * preceding if or else block to the level above the if/else block.
4911 for (int r
= 0; r
< this->next_temp
; r
++) {
4912 for (int c
= 0; c
< 4; c
++) {
4913 if (!writes
[4 * r
+ c
])
4916 if (write_level
[4 * r
+ c
] == level
)
4917 write_level
[4 * r
+ c
] = level
-1;
4920 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4924 case TGSI_OPCODE_IF
:
4925 case TGSI_OPCODE_UIF
:
4927 /* fallthrough to default case to mark the condition as read */
4929 /* Continuing the block, clear any channels from the write array that
4930 * are read by this instruction.
4932 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4933 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4934 /* Any temporary might be read, so no dead code elimination
4935 * across this instruction.
4937 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4938 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4939 /* Clear where it's used as src. */
4940 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4941 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4942 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4943 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4945 for (int c
= 0; c
< 4; c
++) {
4946 if (src_chans
& (1 << c
))
4947 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4951 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4952 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4953 /* Any temporary might be read, so no dead code elimination
4954 * across this instruction.
4956 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4957 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4958 /* Clear where it's used as src. */
4959 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4960 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4961 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4962 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4964 for (int c
= 0; c
< 4; c
++) {
4965 if (src_chans
& (1 << c
))
4966 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4973 /* If this instruction writes to a temporary, add it to the write array.
4974 * If there is already an instruction in the write array for one or more
4975 * of the channels, flag that channel write as dead.
4977 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4978 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4979 !inst
->dst
[i
].reladdr
) {
4980 for (int c
= 0; c
< 4; c
++) {
4981 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4982 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4983 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4986 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4988 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4989 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4996 /* Anything still in the write array at this point is dead code. */
4997 for (int r
= 0; r
< this->next_temp
; r
++) {
4998 for (int c
= 0; c
< 4; c
++) {
4999 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5001 inst
->dead_mask
|= (1 << c
);
5005 /* Now actually remove the instructions that are completely dead and update
5006 * the writemask of other instructions with dead channels.
5008 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5009 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5011 /* No amount of dead masks should remove memory stores */
5012 if (inst
->info
->is_store
)
5015 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5020 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5021 if (inst
->dead_mask
== WRITEMASK_XY
||
5022 inst
->dead_mask
== WRITEMASK_ZW
)
5023 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5025 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5029 ralloc_free(write_level
);
5030 ralloc_free(writes
);
5035 /* merge DFRACEXP instructions into one. */
5037 glsl_to_tgsi_visitor::merge_two_dsts(void)
5039 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5040 glsl_to_tgsi_instruction
*inst2
;
5042 if (num_inst_dst_regs(inst
) != 2)
5045 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5046 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5049 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5052 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5053 inst
->src
[0].index
== inst2
->src
[0].index
&&
5054 inst
->src
[0].type
== inst2
->src
[0].type
&&
5055 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5057 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5063 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5065 inst
->dst
[0] = inst2
->dst
[0];
5066 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5067 inst
->dst
[1] = inst2
->dst
[1];
5078 /* Merges temporary registers together where possible to reduce the number of
5079 * registers needed to run a program.
5081 * Produces optimal code only after copy propagation and dead code elimination
5084 glsl_to_tgsi_visitor::merge_registers(void)
5086 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5087 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5088 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5090 int num_renames
= 0;
5092 /* Read the indices of the last read and first write to each temp register
5093 * into an array so that we don't have to traverse the instruction list as
5095 for (i
= 0; i
< this->next_temp
; i
++) {
5097 first_writes
[i
] = -1;
5099 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5101 /* Start looking for registers with non-overlapping usages that can be
5102 * merged together. */
5103 for (i
= 0; i
< this->next_temp
; i
++) {
5104 /* Don't touch unused registers. */
5105 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5107 for (j
= 0; j
< this->next_temp
; j
++) {
5108 /* Don't touch unused registers. */
5109 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5111 /* We can merge the two registers if the first write to j is after or
5112 * in the same instruction as the last read from i. Note that the
5113 * register at index i will always be used earlier or at the same time
5114 * as the register at index j. */
5115 if (first_writes
[i
] <= first_writes
[j
] &&
5116 last_reads
[i
] <= first_writes
[j
]) {
5117 renames
[num_renames
].old_reg
= j
;
5118 renames
[num_renames
].new_reg
= i
;
5121 /* Update the first_writes and last_reads arrays with the new
5122 * values for the merged register index, and mark the newly unused
5123 * register index as such. */
5124 assert(last_reads
[j
] >= last_reads
[i
]);
5125 last_reads
[i
] = last_reads
[j
];
5126 first_writes
[j
] = -1;
5132 rename_temp_registers(num_renames
, renames
);
5133 ralloc_free(renames
);
5134 ralloc_free(last_reads
);
5135 ralloc_free(first_writes
);
5138 /* Reassign indices to temporary registers by reusing unused indices created
5139 * by optimization passes. */
5141 glsl_to_tgsi_visitor::renumber_registers(void)
5145 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5146 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5147 int num_renames
= 0;
5148 for (i
= 0; i
< this->next_temp
; i
++) {
5149 first_reads
[i
] = -1;
5151 get_first_temp_read(first_reads
);
5153 for (i
= 0; i
< this->next_temp
; i
++) {
5154 if (first_reads
[i
] < 0) continue;
5155 if (i
!= new_index
) {
5156 renames
[num_renames
].old_reg
= i
;
5157 renames
[num_renames
].new_reg
= new_index
;
5163 rename_temp_registers(num_renames
, renames
);
5164 this->next_temp
= new_index
;
5165 ralloc_free(renames
);
5166 ralloc_free(first_reads
);
5169 /* ------------------------- TGSI conversion stuff -------------------------- */
5172 * Intermediate state used during shader translation.
5174 struct st_translate
{
5175 struct ureg_program
*ureg
;
5177 unsigned temps_size
;
5178 struct ureg_dst
*temps
;
5180 struct ureg_dst
*arrays
;
5181 unsigned num_temp_arrays
;
5182 struct ureg_src
*constants
;
5184 struct ureg_src
*immediates
;
5186 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5187 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5188 struct ureg_dst address
[3];
5189 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5190 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5191 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5192 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5193 struct ureg_src shared_memory
;
5194 unsigned *array_sizes
;
5195 struct inout_decl
*input_decls
;
5196 unsigned num_input_decls
;
5197 struct inout_decl
*output_decls
;
5198 unsigned num_output_decls
;
5200 const GLuint
*inputMapping
;
5201 const GLuint
*outputMapping
;
5203 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5206 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5208 _mesa_sysval_to_semantic(unsigned sysval
)
5212 case SYSTEM_VALUE_VERTEX_ID
:
5213 return TGSI_SEMANTIC_VERTEXID
;
5214 case SYSTEM_VALUE_INSTANCE_ID
:
5215 return TGSI_SEMANTIC_INSTANCEID
;
5216 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5217 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5218 case SYSTEM_VALUE_BASE_VERTEX
:
5219 return TGSI_SEMANTIC_BASEVERTEX
;
5220 case SYSTEM_VALUE_BASE_INSTANCE
:
5221 return TGSI_SEMANTIC_BASEINSTANCE
;
5222 case SYSTEM_VALUE_DRAW_ID
:
5223 return TGSI_SEMANTIC_DRAWID
;
5225 /* Geometry shader */
5226 case SYSTEM_VALUE_INVOCATION_ID
:
5227 return TGSI_SEMANTIC_INVOCATIONID
;
5229 /* Fragment shader */
5230 case SYSTEM_VALUE_FRAG_COORD
:
5231 return TGSI_SEMANTIC_POSITION
;
5232 case SYSTEM_VALUE_FRONT_FACE
:
5233 return TGSI_SEMANTIC_FACE
;
5234 case SYSTEM_VALUE_SAMPLE_ID
:
5235 return TGSI_SEMANTIC_SAMPLEID
;
5236 case SYSTEM_VALUE_SAMPLE_POS
:
5237 return TGSI_SEMANTIC_SAMPLEPOS
;
5238 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5239 return TGSI_SEMANTIC_SAMPLEMASK
;
5240 case SYSTEM_VALUE_HELPER_INVOCATION
:
5241 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5243 /* Tessellation shader */
5244 case SYSTEM_VALUE_TESS_COORD
:
5245 return TGSI_SEMANTIC_TESSCOORD
;
5246 case SYSTEM_VALUE_VERTICES_IN
:
5247 return TGSI_SEMANTIC_VERTICESIN
;
5248 case SYSTEM_VALUE_PRIMITIVE_ID
:
5249 return TGSI_SEMANTIC_PRIMID
;
5250 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5251 return TGSI_SEMANTIC_TESSOUTER
;
5252 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5253 return TGSI_SEMANTIC_TESSINNER
;
5255 /* Compute shader */
5256 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5257 return TGSI_SEMANTIC_THREAD_ID
;
5258 case SYSTEM_VALUE_WORK_GROUP_ID
:
5259 return TGSI_SEMANTIC_BLOCK_ID
;
5260 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5261 return TGSI_SEMANTIC_GRID_SIZE
;
5262 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5263 return TGSI_SEMANTIC_BLOCK_SIZE
;
5266 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5267 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5268 case SYSTEM_VALUE_VERTEX_CNT
:
5270 assert(!"Unexpected SYSTEM_VALUE_ enum");
5271 return TGSI_SEMANTIC_COUNT
;
5276 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5278 static struct ureg_src
5279 emit_immediate(struct st_translate
*t
,
5280 gl_constant_value values
[4],
5283 struct ureg_program
*ureg
= t
->ureg
;
5288 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5290 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5292 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5293 case GL_UNSIGNED_INT
:
5295 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5297 assert(!"should not get here - type must be float, int, uint, or bool");
5298 return ureg_src_undef();
5303 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5305 static struct ureg_dst
5306 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5312 case PROGRAM_UNDEFINED
:
5313 return ureg_dst_undef();
5315 case PROGRAM_TEMPORARY
:
5316 /* Allocate space for temporaries on demand. */
5317 if (index
>= t
->temps_size
) {
5318 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5320 t
->temps
= (struct ureg_dst
*)
5322 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5324 return ureg_dst_undef();
5326 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5327 t
->temps_size
+= inc
;
5330 if (ureg_dst_is_undef(t
->temps
[index
]))
5331 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5333 return t
->temps
[index
];
5336 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5337 array
= array_id
- 1;
5339 if (ureg_dst_is_undef(t
->arrays
[array
]))
5340 t
->arrays
[array
] = ureg_DECL_array_temporary(
5341 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5343 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5345 case PROGRAM_OUTPUT
:
5347 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5348 assert(index
< 2 * FRAG_RESULT_MAX
);
5349 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5350 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5351 assert(index
< VARYING_SLOT_TESS_MAX
);
5353 assert(index
< VARYING_SLOT_MAX
);
5355 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5356 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5357 return t
->outputs
[t
->outputMapping
[index
]];
5360 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5361 unsigned mesa_index
= decl
->mesa_index
;
5362 int slot
= t
->outputMapping
[mesa_index
];
5364 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5366 struct ureg_dst dst
= t
->outputs
[slot
];
5367 dst
.ArrayID
= array_id
;
5368 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5371 case PROGRAM_ADDRESS
:
5372 return t
->address
[index
];
5375 assert(!"unknown dst register file");
5376 return ureg_dst_undef();
5381 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5383 static struct ureg_src
5384 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5386 int index
= reg
->index
;
5387 int double_reg2
= reg
->double_reg2
? 1 : 0;
5390 case PROGRAM_UNDEFINED
:
5391 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5393 case PROGRAM_TEMPORARY
:
5395 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5397 case PROGRAM_OUTPUT
: {
5398 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5399 assert(dst
.WriteMask
!= 0);
5400 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5401 return ureg_swizzle(ureg_src(dst
),
5405 MIN2(shift
+ 3, 3));
5408 case PROGRAM_UNIFORM
:
5409 assert(reg
->index
>= 0);
5410 return reg
->index
< t
->num_constants
?
5411 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5412 case PROGRAM_STATE_VAR
:
5413 case PROGRAM_CONSTANT
: /* ie, immediate */
5414 if (reg
->has_index2
)
5415 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5417 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5418 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5420 case PROGRAM_IMMEDIATE
:
5421 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5422 return t
->immediates
[reg
->index
];
5425 /* GLSL inputs are 64-bit containers, so we have to
5426 * map back to the original index and add the offset after
5428 index
-= double_reg2
;
5429 if (!reg
->array_id
) {
5430 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5431 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5432 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5435 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5436 unsigned mesa_index
= decl
->mesa_index
;
5437 int slot
= t
->inputMapping
[mesa_index
];
5439 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5441 struct ureg_src src
= t
->inputs
[slot
];
5442 src
.ArrayID
= reg
->array_id
;
5443 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5446 case PROGRAM_ADDRESS
:
5447 return ureg_src(t
->address
[reg
->index
]);
5449 case PROGRAM_SYSTEM_VALUE
:
5450 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5451 return t
->systemValues
[reg
->index
];
5454 assert(!"unknown src register file");
5455 return ureg_src_undef();
5460 * Create a TGSI ureg_dst register from an st_dst_reg.
5462 static struct ureg_dst
5463 translate_dst(struct st_translate
*t
,
5464 const st_dst_reg
*dst_reg
,
5467 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5470 if (dst
.File
== TGSI_FILE_NULL
)
5473 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5476 dst
= ureg_saturate(dst
);
5478 if (dst_reg
->reladdr
!= NULL
) {
5479 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5480 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5483 if (dst_reg
->has_index2
) {
5484 if (dst_reg
->reladdr2
)
5485 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5488 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5495 * Create a TGSI ureg_src register from an st_src_reg.
5497 static struct ureg_src
5498 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5500 struct ureg_src src
= src_register(t
, src_reg
);
5502 if (src_reg
->has_index2
) {
5503 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5504 * and UBO constant buffers (buffer, position).
5506 if (src_reg
->reladdr2
)
5507 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5510 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5513 src
= ureg_swizzle(src
,
5514 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5515 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5516 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5517 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5519 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5520 src
= ureg_negate(src
);
5522 if (src_reg
->reladdr
!= NULL
) {
5523 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5524 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5530 static struct tgsi_texture_offset
5531 translate_tex_offset(struct st_translate
*t
,
5532 const st_src_reg
*in_offset
)
5534 struct tgsi_texture_offset offset
;
5535 struct ureg_src src
= translate_src(t
, in_offset
);
5537 offset
.File
= src
.File
;
5538 offset
.Index
= src
.Index
;
5539 offset
.SwizzleX
= src
.SwizzleX
;
5540 offset
.SwizzleY
= src
.SwizzleY
;
5541 offset
.SwizzleZ
= src
.SwizzleZ
;
5544 assert(!src
.Indirect
);
5545 assert(!src
.DimIndirect
);
5546 assert(!src
.Dimension
);
5547 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5548 assert(!src
.Negate
);
5554 compile_tgsi_instruction(struct st_translate
*t
,
5555 const glsl_to_tgsi_instruction
*inst
)
5557 struct ureg_program
*ureg
= t
->ureg
;
5559 struct ureg_dst dst
[2];
5560 struct ureg_src src
[4];
5561 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5565 unsigned tex_target
= 0;
5567 num_dst
= num_inst_dst_regs(inst
);
5568 num_src
= num_inst_src_regs(inst
);
5570 for (i
= 0; i
< num_dst
; i
++)
5571 dst
[i
] = translate_dst(t
,
5575 for (i
= 0; i
< num_src
; i
++)
5576 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5579 case TGSI_OPCODE_BGNLOOP
:
5580 case TGSI_OPCODE_ELSE
:
5581 case TGSI_OPCODE_ENDLOOP
:
5582 case TGSI_OPCODE_IF
:
5583 case TGSI_OPCODE_UIF
:
5584 assert(num_dst
== 0);
5585 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5588 case TGSI_OPCODE_TEX
:
5589 case TGSI_OPCODE_TXB
:
5590 case TGSI_OPCODE_TXD
:
5591 case TGSI_OPCODE_TXL
:
5592 case TGSI_OPCODE_TXP
:
5593 case TGSI_OPCODE_TXQ
:
5594 case TGSI_OPCODE_TXQS
:
5595 case TGSI_OPCODE_TXF
:
5596 case TGSI_OPCODE_TEX2
:
5597 case TGSI_OPCODE_TXB2
:
5598 case TGSI_OPCODE_TXL2
:
5599 case TGSI_OPCODE_TG4
:
5600 case TGSI_OPCODE_LODQ
:
5601 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5602 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5603 if (inst
->resource
.reladdr
)
5605 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5607 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5608 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5610 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5616 texoffsets
, inst
->tex_offset_num_offset
,
5620 case TGSI_OPCODE_RESQ
:
5621 case TGSI_OPCODE_LOAD
:
5622 case TGSI_OPCODE_ATOMUADD
:
5623 case TGSI_OPCODE_ATOMXCHG
:
5624 case TGSI_OPCODE_ATOMCAS
:
5625 case TGSI_OPCODE_ATOMAND
:
5626 case TGSI_OPCODE_ATOMOR
:
5627 case TGSI_OPCODE_ATOMXOR
:
5628 case TGSI_OPCODE_ATOMUMIN
:
5629 case TGSI_OPCODE_ATOMUMAX
:
5630 case TGSI_OPCODE_ATOMIMIN
:
5631 case TGSI_OPCODE_ATOMIMAX
:
5632 for (i
= num_src
- 1; i
>= 0; i
--)
5633 src
[i
+ 1] = src
[i
];
5635 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5636 src
[0] = t
->shared_memory
;
5637 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5638 src
[0] = t
->buffers
[inst
->resource
.index
];
5640 src
[0] = t
->images
[inst
->resource
.index
];
5641 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5643 if (inst
->resource
.reladdr
)
5644 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5645 assert(src
[0].File
!= TGSI_FILE_NULL
);
5646 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5647 inst
->buffer_access
,
5648 tex_target
, inst
->image_format
);
5651 case TGSI_OPCODE_STORE
:
5652 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5653 dst
[0] = ureg_dst(t
->shared_memory
);
5654 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5655 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5657 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5658 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5660 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5661 if (inst
->resource
.reladdr
)
5662 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5663 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5664 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5665 inst
->buffer_access
,
5666 tex_target
, inst
->image_format
);
5669 case TGSI_OPCODE_SCS
:
5670 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5671 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5684 * Emit the TGSI instructions for inverting and adjusting WPOS.
5685 * This code is unavoidable because it also depends on whether
5686 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5689 emit_wpos_adjustment(struct gl_context
*ctx
,
5690 struct st_translate
*t
,
5691 int wpos_transform_const
,
5693 GLfloat adjX
, GLfloat adjY
[2])
5695 struct ureg_program
*ureg
= t
->ureg
;
5697 assert(wpos_transform_const
>= 0);
5699 /* Fragment program uses fragment position input.
5700 * Need to replace instances of INPUT[WPOS] with temp T
5701 * where T = INPUT[WPOS] is inverted by Y.
5703 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5704 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5705 struct ureg_src
*wpos
=
5706 ctx
->Const
.GLSLFragCoordIsSysVal
?
5707 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5708 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5709 struct ureg_src wpos_input
= *wpos
;
5711 /* First, apply the coordinate shift: */
5712 if (adjX
|| adjY
[0] || adjY
[1]) {
5713 if (adjY
[0] != adjY
[1]) {
5714 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5715 * depending on whether inversion is actually going to be applied
5716 * or not, which is determined by testing against the inversion
5717 * state variable used below, which will be either +1 or -1.
5719 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5721 ureg_CMP(ureg
, adj_temp
,
5722 ureg_scalar(wpostrans
, invert
? 2 : 0),
5723 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5724 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5725 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5727 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5728 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5730 wpos_input
= ureg_src(wpos_temp
);
5732 /* MOV wpos_temp, input[wpos]
5734 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5737 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5738 * inversion/identity, or the other way around if we're drawing to an FBO.
5741 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5744 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5746 ureg_scalar(wpostrans
, 0),
5747 ureg_scalar(wpostrans
, 1));
5749 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5752 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5754 ureg_scalar(wpostrans
, 2),
5755 ureg_scalar(wpostrans
, 3));
5758 /* Use wpos_temp as position input from here on:
5760 *wpos
= ureg_src(wpos_temp
);
5765 * Emit fragment position/ooordinate code.
5768 emit_wpos(struct st_context
*st
,
5769 struct st_translate
*t
,
5770 const struct gl_program
*program
,
5771 struct ureg_program
*ureg
,
5772 int wpos_transform_const
)
5774 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5775 GLfloat adjX
= 0.0f
;
5776 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5777 boolean invert
= FALSE
;
5779 /* Query the pixel center conventions supported by the pipe driver and set
5780 * adjX, adjY to help out if it cannot handle the requested one internally.
5782 * The bias of the y-coordinate depends on whether y-inversion takes place
5783 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5784 * drawing to an FBO (causes additional inversion), and whether the pipe
5785 * driver origin and the requested origin differ (the latter condition is
5786 * stored in the 'invert' variable).
5788 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5790 * center shift only:
5795 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5796 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5797 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5798 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5800 * inversion and center shift:
5801 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5802 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5803 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5804 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5806 if (program
->OriginUpperLeft
) {
5807 /* Fragment shader wants origin in upper-left */
5808 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5809 /* the driver supports upper-left origin */
5811 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5812 /* the driver supports lower-left origin, need to invert Y */
5813 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5814 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5821 /* Fragment shader wants origin in lower-left */
5822 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5823 /* the driver supports lower-left origin */
5824 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5825 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5826 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5827 /* the driver supports upper-left origin, need to invert Y */
5833 if (program
->PixelCenterInteger
) {
5834 /* Fragment shader wants pixel center integer */
5835 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5836 /* the driver supports pixel center integer */
5838 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5839 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5841 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5842 /* the driver supports pixel center half integer, need to bias X,Y */
5851 /* Fragment shader wants pixel center half integer */
5852 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5853 /* the driver supports pixel center half integer */
5855 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5856 /* the driver supports pixel center integer, need to bias X,Y */
5857 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5858 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5859 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5865 /* we invert after adjustment so that we avoid the MOV to temporary,
5866 * and reuse the adjustment ADD instead */
5867 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5871 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5872 * TGSI uses +1 for front, -1 for back.
5873 * This function converts the TGSI value to the GL value. Simply clamping/
5874 * saturating the value to [0,1] does the job.
5877 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5879 struct ureg_program
*ureg
= t
->ureg
;
5880 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5881 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5883 if (ctx
->Const
.NativeIntegers
) {
5884 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5887 /* MOV_SAT face_temp, input[face] */
5888 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5891 /* Use face_temp as face input from here on: */
5892 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5896 emit_compute_block_size(const struct gl_program
*prog
,
5897 struct ureg_program
*ureg
) {
5898 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5899 prog
->info
.cs
.local_size
[0]);
5900 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
5901 prog
->info
.cs
.local_size
[1]);
5902 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
5903 prog
->info
.cs
.local_size
[2]);
5906 struct sort_inout_decls
{
5907 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
5908 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
5911 const GLuint
*mapping
;
5914 /* Sort the given array of decls by the corresponding slot (TGSI file index).
5916 * This is for the benefit of older drivers which are broken when the
5917 * declarations aren't sorted in this way.
5920 sort_inout_decls_by_slot(struct inout_decl
*decls
,
5922 const GLuint mapping
[])
5924 sort_inout_decls sorter
;
5925 sorter
.mapping
= mapping
;
5926 std::sort(decls
, decls
+ count
, sorter
);
5930 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
5932 switch (glsl_qual
) {
5933 case INTERP_MODE_NONE
:
5934 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
5935 return TGSI_INTERPOLATE_COLOR
;
5936 return TGSI_INTERPOLATE_PERSPECTIVE
;
5937 case INTERP_MODE_SMOOTH
:
5938 return TGSI_INTERPOLATE_PERSPECTIVE
;
5939 case INTERP_MODE_FLAT
:
5940 return TGSI_INTERPOLATE_CONSTANT
;
5941 case INTERP_MODE_NOPERSPECTIVE
:
5942 return TGSI_INTERPOLATE_LINEAR
;
5944 assert(0 && "unexpected interp mode in st_translate_interp()");
5945 return TGSI_INTERPOLATE_PERSPECTIVE
;
5950 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5951 * \param program the program to translate
5952 * \param numInputs number of input registers used
5953 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5955 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5956 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5958 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5959 * \param numOutputs number of output registers used
5960 * \param outputMapping maps Mesa fragment program outputs to TGSI
5962 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5963 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5966 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5968 extern "C" enum pipe_error
5969 st_translate_program(
5970 struct gl_context
*ctx
,
5972 struct ureg_program
*ureg
,
5973 glsl_to_tgsi_visitor
*program
,
5974 const struct gl_program
*proginfo
,
5976 const GLuint inputMapping
[],
5977 const GLuint inputSlotToAttr
[],
5978 const ubyte inputSemanticName
[],
5979 const ubyte inputSemanticIndex
[],
5980 const GLuint interpMode
[],
5982 const GLuint outputMapping
[],
5983 const GLuint outputSlotToAttr
[],
5984 const ubyte outputSemanticName
[],
5985 const ubyte outputSemanticIndex
[])
5987 struct st_translate
*t
;
5989 struct gl_program_constants
*frag_const
=
5990 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
5991 enum pipe_error ret
= PIPE_OK
;
5993 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5994 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5996 t
= CALLOC_STRUCT(st_translate
);
5998 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6002 t
->procType
= procType
;
6003 t
->inputMapping
= inputMapping
;
6004 t
->outputMapping
= outputMapping
;
6006 t
->num_temp_arrays
= program
->next_array
;
6007 if (t
->num_temp_arrays
)
6008 t
->arrays
= (struct ureg_dst
*)
6009 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6012 * Declare input attributes.
6015 case PIPE_SHADER_FRAGMENT
:
6016 case PIPE_SHADER_GEOMETRY
:
6017 case PIPE_SHADER_TESS_EVAL
:
6018 case PIPE_SHADER_TESS_CTRL
:
6019 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6021 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6022 struct inout_decl
*decl
= &program
->inputs
[i
];
6023 unsigned slot
= inputMapping
[decl
->mesa_index
];
6024 struct ureg_src src
;
6025 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6027 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6028 if (tgsi_usage_mask
== 1)
6029 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6030 else if (tgsi_usage_mask
== 2)
6031 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6033 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6036 unsigned interp_mode
= 0;
6037 unsigned interp_location
= 0;
6038 if (procType
== PIPE_SHADER_FRAGMENT
) {
6040 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6042 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6044 interp_location
= decl
->interp_loc
;
6047 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6048 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6049 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6050 decl
->array_id
, decl
->size
);
6052 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6053 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6054 /* The ArrayID is set up in dst_register */
6055 t
->inputs
[slot
+ j
] = src
;
6056 t
->inputs
[slot
+ j
].ArrayID
= 0;
6057 t
->inputs
[slot
+ j
].Index
+= j
;
6062 case PIPE_SHADER_VERTEX
:
6063 for (i
= 0; i
< numInputs
; i
++) {
6064 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6067 case PIPE_SHADER_COMPUTE
:
6074 * Declare output attributes.
6077 case PIPE_SHADER_FRAGMENT
:
6078 case PIPE_SHADER_COMPUTE
:
6080 case PIPE_SHADER_GEOMETRY
:
6081 case PIPE_SHADER_TESS_EVAL
:
6082 case PIPE_SHADER_TESS_CTRL
:
6083 case PIPE_SHADER_VERTEX
:
6084 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6086 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6087 struct inout_decl
*decl
= &program
->outputs
[i
];
6088 unsigned slot
= outputMapping
[decl
->mesa_index
];
6089 struct ureg_dst dst
;
6090 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6092 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6093 if (tgsi_usage_mask
== 1)
6094 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6095 else if (tgsi_usage_mask
== 2)
6096 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6098 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6101 dst
= ureg_DECL_output_layout(ureg
,
6102 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6103 decl
->gs_out_streams
,
6104 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6106 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6107 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6108 /* The ArrayID is set up in dst_register */
6109 t
->outputs
[slot
+ j
] = dst
;
6110 t
->outputs
[slot
+ j
].ArrayID
= 0;
6111 t
->outputs
[slot
+ j
].Index
+= j
;
6120 if (procType
== PIPE_SHADER_FRAGMENT
) {
6121 if (program
->shader
->info
.EarlyFragmentTests
)
6122 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6124 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6125 /* Must do this after setting up t->inputs. */
6126 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6127 program
->wpos_transform_const
);
6130 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6131 emit_face_var(ctx
, t
);
6133 for (i
= 0; i
< numOutputs
; i
++) {
6134 switch (outputSemanticName
[i
]) {
6135 case TGSI_SEMANTIC_POSITION
:
6136 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6137 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6138 outputSemanticIndex
[i
]);
6139 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6141 case TGSI_SEMANTIC_STENCIL
:
6142 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6143 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6144 outputSemanticIndex
[i
]);
6145 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6147 case TGSI_SEMANTIC_COLOR
:
6148 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6149 TGSI_SEMANTIC_COLOR
,
6150 outputSemanticIndex
[i
]);
6152 case TGSI_SEMANTIC_SAMPLEMASK
:
6153 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6154 TGSI_SEMANTIC_SAMPLEMASK
,
6155 outputSemanticIndex
[i
]);
6156 /* TODO: If we ever support more than 32 samples, this will have
6157 * to become an array.
6159 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6162 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6163 ret
= PIPE_ERROR_BAD_INPUT
;
6168 else if (procType
== PIPE_SHADER_VERTEX
) {
6169 for (i
= 0; i
< numOutputs
; i
++) {
6170 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6171 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6173 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6174 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6175 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6180 if (procType
== PIPE_SHADER_COMPUTE
) {
6181 emit_compute_block_size(proginfo
, ureg
);
6184 /* Declare address register.
6186 if (program
->num_address_regs
> 0) {
6187 assert(program
->num_address_regs
<= 3);
6188 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6189 t
->address
[i
] = ureg_DECL_address(ureg
);
6192 /* Declare misc input registers
6195 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6197 for (i
= 0; sysInputs
; i
++) {
6198 if (sysInputs
& (1 << i
)) {
6199 unsigned semName
= _mesa_sysval_to_semantic(i
);
6201 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6203 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6204 semName
== TGSI_SEMANTIC_VERTEXID
) {
6205 /* From Gallium perspective, these system values are always
6206 * integer, and require native integer support. However, if
6207 * native integer is supported on the vertex stage but not the
6208 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6209 * assumes these system values are floats. To resolve the
6210 * inconsistency, we insert a U2F.
6212 struct st_context
*st
= st_context(ctx
);
6213 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6214 assert(procType
== PIPE_SHADER_VERTEX
);
6215 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6217 if (!ctx
->Const
.NativeIntegers
) {
6218 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6219 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6220 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6224 if (procType
== PIPE_SHADER_FRAGMENT
&&
6225 semName
== TGSI_SEMANTIC_POSITION
)
6226 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6227 program
->wpos_transform_const
);
6229 sysInputs
&= ~(1 << i
);
6234 t
->array_sizes
= program
->array_sizes
;
6235 t
->input_decls
= program
->inputs
;
6236 t
->num_input_decls
= program
->num_inputs
;
6237 t
->output_decls
= program
->outputs
;
6238 t
->num_output_decls
= program
->num_outputs
;
6240 /* Emit constants and uniforms. TGSI uses a single index space for these,
6241 * so we put all the translated regs in t->constants.
6243 if (proginfo
->Parameters
) {
6244 t
->constants
= (struct ureg_src
*)
6245 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6246 if (t
->constants
== NULL
) {
6247 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6250 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6252 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6253 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6254 case PROGRAM_STATE_VAR
:
6255 case PROGRAM_UNIFORM
:
6256 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6259 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6260 * addressing of the const buffer.
6261 * FIXME: Be smarter and recognize param arrays:
6262 * indirect addressing is only valid within the referenced
6265 case PROGRAM_CONSTANT
:
6266 if (program
->indirect_addr_consts
)
6267 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6269 t
->constants
[i
] = emit_immediate(t
,
6270 proginfo
->Parameters
->ParameterValues
[i
],
6271 proginfo
->Parameters
->Parameters
[i
].DataType
,
6280 if (program
->shader
) {
6281 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6283 for (i
= 0; i
< num_ubos
; i
++) {
6284 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6285 unsigned num_const_vecs
= (size
+ 15) / 16;
6286 unsigned first
, last
;
6287 assert(num_const_vecs
> 0);
6289 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6290 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6294 /* Emit immediate values.
6296 t
->immediates
= (struct ureg_src
*)
6297 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6298 if (t
->immediates
== NULL
) {
6299 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6302 t
->num_immediates
= program
->num_immediates
;
6305 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6306 assert(i
< program
->num_immediates
);
6307 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6309 assert(i
== program
->num_immediates
);
6311 /* texture samplers */
6312 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6313 if (program
->samplers_used
& (1u << i
)) {
6316 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6318 switch (program
->sampler_types
[i
]) {
6320 type
= TGSI_RETURN_TYPE_SINT
;
6322 case GLSL_TYPE_UINT
:
6323 type
= TGSI_RETURN_TYPE_UINT
;
6325 case GLSL_TYPE_FLOAT
:
6326 type
= TGSI_RETURN_TYPE_FLOAT
;
6329 unreachable("not reached");
6332 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6333 type
, type
, type
, type
);
6337 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6338 if (program
->buffers_used
& (1 << i
)) {
6339 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6343 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6345 if (program
->buffers_used
& (1 << i
)) {
6346 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6350 if (program
->use_shared_memory
)
6351 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6353 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6354 if (program
->images_used
& (1 << i
)) {
6355 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6356 program
->image_targets
[i
],
6357 program
->image_formats
[i
],
6362 /* Emit each instruction in turn:
6364 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6365 compile_tgsi_instruction(t
, inst
);
6367 /* Set the next shader stage hint for VS and TES. */
6369 case PIPE_SHADER_VERTEX
:
6370 case PIPE_SHADER_TESS_EVAL
:
6371 if (program
->shader_program
->SeparateShader
)
6374 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6375 if (program
->shader_program
->_LinkedShaders
[i
]) {
6379 case MESA_SHADER_TESS_CTRL
:
6380 next
= PIPE_SHADER_TESS_CTRL
;
6382 case MESA_SHADER_TESS_EVAL
:
6383 next
= PIPE_SHADER_TESS_EVAL
;
6385 case MESA_SHADER_GEOMETRY
:
6386 next
= PIPE_SHADER_GEOMETRY
;
6388 case MESA_SHADER_FRAGMENT
:
6389 next
= PIPE_SHADER_FRAGMENT
;
6396 ureg_set_next_shader_processor(ureg
, next
);
6408 t
->num_constants
= 0;
6409 free(t
->immediates
);
6410 t
->num_immediates
= 0;
6416 /* ----------------------------- End TGSI code ------------------------------ */
6420 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6421 * generating Mesa IR.
6423 static struct gl_program
*
6424 get_mesa_program_tgsi(struct gl_context
*ctx
,
6425 struct gl_shader_program
*shader_program
,
6426 struct gl_linked_shader
*shader
)
6428 glsl_to_tgsi_visitor
* v
;
6429 struct gl_program
*prog
;
6430 struct gl_shader_compiler_options
*options
=
6431 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6432 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6433 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6435 validate_ir_tree(shader
->ir
);
6437 prog
= shader
->Program
;
6439 prog
->Parameters
= _mesa_new_parameter_list();
6440 v
= new glsl_to_tgsi_visitor();
6443 v
->shader_program
= shader_program
;
6445 v
->options
= options
;
6446 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6447 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6449 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6450 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6451 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6452 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6454 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6457 /* Remove reads from output registers. */
6458 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6459 lower_output_reads(shader
->Stage
, shader
->ir
);
6461 /* Emit intermediate IR for main(). */
6462 visit_exec_list(shader
->ir
, v
);
6465 /* Print out some information (for debugging purposes) used by the
6466 * optimization passes. */
6469 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6470 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6471 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6472 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6474 for (i
= 0; i
< v
->next_temp
; i
++) {
6475 first_writes
[i
] = -1;
6476 first_reads
[i
] = -1;
6477 last_writes
[i
] = -1;
6480 v
->get_first_temp_read(first_reads
);
6481 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6482 v
->get_last_temp_write(last_writes
);
6483 for (i
= 0; i
< v
->next_temp
; i
++)
6484 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6488 ralloc_free(first_writes
);
6489 ralloc_free(first_reads
);
6490 ralloc_free(last_writes
);
6491 ralloc_free(last_reads
);
6495 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6498 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6499 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6500 v
->copy_propagate();
6502 while (v
->eliminate_dead_code());
6504 v
->merge_two_dsts();
6505 v
->merge_registers();
6506 v
->renumber_registers();
6508 /* Write the END instruction. */
6509 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6511 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6513 _mesa_log("GLSL IR for linked %s program %d:\n",
6514 _mesa_shader_stage_to_string(shader
->Stage
),
6515 shader_program
->Name
);
6516 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6520 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6521 _mesa_copy_linked_program_data(shader_program
, shader
);
6522 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6523 &prog
->info
.inputs_read
,
6524 prog
->info
.double_inputs_read
,
6525 &prog
->info
.patch_inputs_read
);
6526 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6527 &prog
->info
.outputs_written
, 0ULL,
6528 &prog
->info
.patch_outputs_written
);
6529 count_resources(v
, prog
);
6531 /* The GLSL IR won't be needed anymore. */
6532 ralloc_free(shader
->ir
);
6535 /* This must be done before the uniform storage is associated. */
6536 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6537 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6538 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6539 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6540 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6543 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6544 wposTransformState
);
6547 /* Avoid reallocation of the program parameter list, because the uniform
6548 * storage is only associated with the original parameter list.
6549 * This should be enough for Bitmap and DrawPixels constants.
6551 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6553 /* This has to be done last. Any operation the can cause
6554 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6555 * program constant) has to happen before creating this linkage.
6557 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6558 if (!shader_program
->data
->LinkStatus
) {
6559 free_glsl_to_tgsi_visitor(v
);
6560 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6564 struct st_vertex_program
*stvp
;
6565 struct st_fragment_program
*stfp
;
6566 struct st_geometry_program
*stgp
;
6567 struct st_tessctrl_program
*sttcp
;
6568 struct st_tesseval_program
*sttep
;
6569 struct st_compute_program
*stcp
;
6571 switch (shader
->Stage
) {
6572 case MESA_SHADER_VERTEX
:
6573 stvp
= (struct st_vertex_program
*)prog
;
6574 stvp
->glsl_to_tgsi
= v
;
6576 case MESA_SHADER_FRAGMENT
:
6577 stfp
= (struct st_fragment_program
*)prog
;
6578 stfp
->glsl_to_tgsi
= v
;
6580 case MESA_SHADER_GEOMETRY
:
6581 stgp
= (struct st_geometry_program
*)prog
;
6582 stgp
->glsl_to_tgsi
= v
;
6584 case MESA_SHADER_TESS_CTRL
:
6585 sttcp
= (struct st_tessctrl_program
*)prog
;
6586 sttcp
->glsl_to_tgsi
= v
;
6588 case MESA_SHADER_TESS_EVAL
:
6589 sttep
= (struct st_tesseval_program
*)prog
;
6590 sttep
->glsl_to_tgsi
= v
;
6592 case MESA_SHADER_COMPUTE
:
6593 stcp
= (struct st_compute_program
*)prog
;
6594 stcp
->glsl_to_tgsi
= v
;
6597 assert(!"should not be reached");
6605 set_affected_state_flags(uint64_t *states
,
6606 struct gl_program
*prog
,
6607 struct gl_linked_shader
*shader
,
6608 uint64_t new_constants
,
6609 uint64_t new_sampler_views
,
6610 uint64_t new_samplers
,
6611 uint64_t new_images
,
6614 uint64_t new_atomics
)
6616 if (prog
->Parameters
->NumParameters
)
6617 *states
|= new_constants
;
6619 if (shader
->num_samplers
)
6620 *states
|= new_sampler_views
| new_samplers
;
6622 if (shader
->NumImages
)
6623 *states
|= new_images
;
6625 if (shader
->NumUniformBlocks
)
6626 *states
|= new_ubos
;
6628 if (shader
->NumShaderStorageBlocks
)
6629 *states
|= new_ssbos
;
6631 if (prog
->info
.num_abos
)
6632 *states
|= new_atomics
;
6635 static struct gl_program
*
6636 get_mesa_program(struct gl_context
*ctx
,
6637 struct gl_shader_program
*shader_program
,
6638 struct gl_linked_shader
*shader
)
6640 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6641 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6642 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6643 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6644 struct gl_program
*prog
= NULL
;
6646 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6647 /* TODO only for GLSL VS/FS for now: */
6648 switch (shader
->Stage
) {
6649 case MESA_SHADER_VERTEX
:
6650 case MESA_SHADER_FRAGMENT
:
6651 prog
= st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6656 prog
= get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6662 /* This determines which states will be updated when the shader is
6665 switch (shader
->Stage
) {
6666 case MESA_SHADER_VERTEX
:
6667 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6669 *states
= ST_NEW_VS_STATE
|
6671 ST_NEW_VERTEX_ARRAYS
;
6673 set_affected_state_flags(states
, prog
, shader
,
6674 ST_NEW_VS_CONSTANTS
,
6675 ST_NEW_VS_SAMPLER_VIEWS
,
6676 ST_NEW_RENDER_SAMPLERS
,
6683 case MESA_SHADER_TESS_CTRL
:
6684 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6686 *states
= ST_NEW_TCS_STATE
;
6688 set_affected_state_flags(states
, prog
, shader
,
6689 ST_NEW_TCS_CONSTANTS
,
6690 ST_NEW_TCS_SAMPLER_VIEWS
,
6691 ST_NEW_RENDER_SAMPLERS
,
6695 ST_NEW_TCS_ATOMICS
);
6698 case MESA_SHADER_TESS_EVAL
:
6699 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6701 *states
= ST_NEW_TES_STATE
|
6704 set_affected_state_flags(states
, prog
, shader
,
6705 ST_NEW_TES_CONSTANTS
,
6706 ST_NEW_TES_SAMPLER_VIEWS
,
6707 ST_NEW_RENDER_SAMPLERS
,
6711 ST_NEW_TES_ATOMICS
);
6714 case MESA_SHADER_GEOMETRY
:
6715 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6717 *states
= ST_NEW_GS_STATE
|
6720 set_affected_state_flags(states
, prog
, shader
,
6721 ST_NEW_GS_CONSTANTS
,
6722 ST_NEW_GS_SAMPLER_VIEWS
,
6723 ST_NEW_RENDER_SAMPLERS
,
6730 case MESA_SHADER_FRAGMENT
:
6731 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6733 /* gl_FragCoord and glDrawPixels always use constants. */
6734 *states
= ST_NEW_FS_STATE
|
6735 ST_NEW_SAMPLE_SHADING
|
6736 ST_NEW_FS_CONSTANTS
;
6738 set_affected_state_flags(states
, prog
, shader
,
6739 ST_NEW_FS_CONSTANTS
,
6740 ST_NEW_FS_SAMPLER_VIEWS
,
6741 ST_NEW_RENDER_SAMPLERS
,
6748 case MESA_SHADER_COMPUTE
:
6749 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6751 *states
= ST_NEW_CS_STATE
;
6753 set_affected_state_flags(states
, prog
, shader
,
6754 ST_NEW_CS_CONSTANTS
,
6755 ST_NEW_CS_SAMPLER_VIEWS
,
6764 unreachable("unhandled shader stage");
6771 /* See if there are unsupported control flow statements. */
6772 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6774 const struct gl_shader_compiler_options
*options
;
6776 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6782 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6784 /* Other functions are skipped (same as glsl_to_tgsi). */
6785 if (strcmp(ir
->name
, "main") == 0)
6786 return visit_continue
;
6788 return visit_continue_with_parent
;
6791 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6793 if (!ir
->callee
->is_intrinsic()) {
6794 unsupported
= true; /* it's a function call */
6797 return visit_continue
;
6800 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6802 if (options
->EmitNoMainReturn
) {
6806 return visit_continue
;
6813 has_unsupported_control_flow(exec_list
*ir
,
6814 const struct gl_shader_compiler_options
*options
)
6816 ir_control_flow_info_visitor
visitor(options
);
6817 visit_list_elements(&visitor
, ir
);
6818 return visitor
.unsupported
;
6825 * Called via ctx->Driver.LinkShader()
6826 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6827 * with code lowering and other optimizations.
6830 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6832 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6833 assert(prog
->data
->LinkStatus
);
6835 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6836 if (prog
->_LinkedShaders
[i
] == NULL
)
6839 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6840 gl_shader_stage stage
= prog
->_LinkedShaders
[i
]->Stage
;
6841 const struct gl_shader_compiler_options
*options
=
6842 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6843 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6844 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6845 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6846 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6847 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6848 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6849 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6851 /* If there are forms of indirect addressing that the driver
6852 * cannot handle, perform the lowering pass.
6854 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6855 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6856 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6857 options
->EmitNoIndirectInput
,
6858 options
->EmitNoIndirectOutput
,
6859 options
->EmitNoIndirectTemp
,
6860 options
->EmitNoIndirectUniform
);
6863 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6864 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6865 LOWER_UNPACK_SNORM_2x16
|
6866 LOWER_PACK_UNORM_2x16
|
6867 LOWER_UNPACK_UNORM_2x16
|
6868 LOWER_PACK_SNORM_4x8
|
6869 LOWER_UNPACK_SNORM_4x8
|
6870 LOWER_UNPACK_UNORM_4x8
|
6871 LOWER_PACK_UNORM_4x8
;
6873 if (ctx
->Extensions
.ARB_gpu_shader5
)
6874 lower_inst
|= LOWER_PACK_USE_BFI
|
6876 if (!ctx
->st
->has_half_float_packing
)
6877 lower_inst
|= LOWER_PACK_HALF_2x16
|
6878 LOWER_UNPACK_HALF_2x16
;
6880 lower_packing_builtins(ir
, lower_inst
);
6883 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6884 lower_offset_arrays(ir
);
6885 do_mat_op_to_vec(ir
);
6886 lower_instructions(ir
,
6892 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6895 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6896 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6897 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6898 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6899 /* Assume that if ARB_gpu_shader5 is not supported
6900 * then all of the extended integer functions need
6901 * lowering. It may be necessary to add some caps
6902 * for individual instructions.
6904 (!ctx
->Extensions
.ARB_gpu_shader5
6905 ? BIT_COUNT_TO_MATH
|
6909 FIND_LSB_TO_FLOAT_CAST
|
6910 FIND_MSB_TO_FLOAT_CAST
|
6914 do_vec_index_to_cond_assign(ir
);
6915 lower_vector_insert(ir
, true);
6916 lower_quadop_vector(ir
, false);
6918 if (options
->MaxIfDepth
== 0) {
6922 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6923 /* Do it once and repeat only if there's unsupported control flow. */
6925 do_common_optimization(ir
, true, true, options
,
6926 ctx
->Const
.NativeIntegers
);
6927 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6928 options
->MaxIfDepth
, if_threshold
);
6929 } while (has_unsupported_control_flow(ir
, options
));
6931 /* Repeat it until it stops making changes. */
6934 progress
= do_common_optimization(ir
, true, true, options
,
6935 ctx
->Const
.NativeIntegers
);
6936 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6937 options
->MaxIfDepth
, if_threshold
);
6941 validate_ir_tree(ir
);
6944 build_program_resource_list(ctx
, prog
);
6946 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6947 struct gl_program
*linked_prog
;
6949 if (prog
->_LinkedShaders
[i
] == NULL
)
6952 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6955 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6956 _mesa_shader_stage_to_program(i
),
6958 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6969 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6970 const GLuint outputMapping
[],
6971 struct pipe_stream_output_info
*so
)
6973 struct gl_transform_feedback_info
*info
=
6974 glsl_to_tgsi
->shader_program
->xfb_program
->sh
.LinkedTransformFeedback
;
6975 st_translate_stream_output_info2(info
, outputMapping
, so
);
6979 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
6980 const GLuint outputMapping
[],
6981 struct pipe_stream_output_info
*so
)
6985 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6986 so
->output
[i
].register_index
=
6987 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6988 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6989 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6990 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6991 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6992 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6995 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6996 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6998 so
->num_outputs
= info
->NumOutputs
;