2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
128 static struct inout_decl
*
129 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
131 assert(array_id
!= 0);
133 for (unsigned i
= 0; i
< count
; i
++) {
134 struct inout_decl
*decl
= &decls
[i
];
136 if (array_id
== decl
->array_id
) {
144 static enum glsl_base_type
145 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
148 return GLSL_TYPE_ERROR
;
149 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
151 return decl
->base_type
;
152 return GLSL_TYPE_ERROR
;
155 struct glsl_to_tgsi_visitor
: public ir_visitor
{
157 glsl_to_tgsi_visitor();
158 ~glsl_to_tgsi_visitor();
160 struct gl_context
*ctx
;
161 struct gl_program
*prog
;
162 struct gl_shader_program
*shader_program
;
163 struct gl_linked_shader
*shader
;
164 struct gl_shader_compiler_options
*options
;
168 unsigned *array_sizes
;
169 unsigned max_num_arrays
;
172 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
174 unsigned num_input_arrays
;
175 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
176 unsigned num_outputs
;
177 unsigned num_output_arrays
;
179 int num_address_regs
;
180 uint32_t samplers_used
;
181 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
182 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
184 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
185 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
186 bool indirect_addr_consts
;
187 int wpos_transform_const
;
190 bool native_integers
;
193 bool use_shared_memory
;
197 variable_storage
*find_variable_storage(ir_variable
*var
);
199 int add_constant(gl_register_file file
, gl_constant_value values
[8],
200 int size
, int datatype
, uint16_t *swizzle_out
);
202 st_src_reg
get_temp(const glsl_type
*type
);
203 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
205 st_src_reg
st_src_reg_for_double(double val
);
206 st_src_reg
st_src_reg_for_float(float val
);
207 st_src_reg
st_src_reg_for_int(int val
);
208 st_src_reg
st_src_reg_for_int64(int64_t val
);
209 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
212 * \name Visit methods
214 * As typical for the visitor pattern, there must be one \c visit method for
215 * each concrete subclass of \c ir_instruction. Virtual base classes within
216 * the hierarchy should not have \c visit methods.
219 virtual void visit(ir_variable
*);
220 virtual void visit(ir_loop
*);
221 virtual void visit(ir_loop_jump
*);
222 virtual void visit(ir_function_signature
*);
223 virtual void visit(ir_function
*);
224 virtual void visit(ir_expression
*);
225 virtual void visit(ir_swizzle
*);
226 virtual void visit(ir_dereference_variable
*);
227 virtual void visit(ir_dereference_array
*);
228 virtual void visit(ir_dereference_record
*);
229 virtual void visit(ir_assignment
*);
230 virtual void visit(ir_constant
*);
231 virtual void visit(ir_call
*);
232 virtual void visit(ir_return
*);
233 virtual void visit(ir_discard
*);
234 virtual void visit(ir_texture
*);
235 virtual void visit(ir_if
*);
236 virtual void visit(ir_emit_vertex
*);
237 virtual void visit(ir_end_primitive
*);
238 virtual void visit(ir_barrier
*);
241 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
243 void visit_atomic_counter_intrinsic(ir_call
*);
244 void visit_ssbo_intrinsic(ir_call
*);
245 void visit_membar_intrinsic(ir_call
*);
246 void visit_shared_intrinsic(ir_call
*);
247 void visit_image_intrinsic(ir_call
*);
248 void visit_generic_intrinsic(ir_call
*, unsigned op
);
252 /** List of variable_storage */
253 struct hash_table
*variables
;
255 /** List of immediate_storage */
256 exec_list immediates
;
257 unsigned num_immediates
;
259 /** List of glsl_to_tgsi_instruction */
260 exec_list instructions
;
262 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
263 st_dst_reg dst
= undef_dst
,
264 st_src_reg src0
= undef_src
,
265 st_src_reg src1
= undef_src
,
266 st_src_reg src2
= undef_src
,
267 st_src_reg src3
= undef_src
);
269 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
270 st_dst_reg dst
, st_dst_reg dst1
,
271 st_src_reg src0
= undef_src
,
272 st_src_reg src1
= undef_src
,
273 st_src_reg src2
= undef_src
,
274 st_src_reg src3
= undef_src
);
276 unsigned get_opcode(unsigned op
,
278 st_src_reg src0
, st_src_reg src1
);
281 * Emit the correct dot-product instruction for the type of arguments
283 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
289 void emit_scalar(ir_instruction
*ir
, unsigned op
,
290 st_dst_reg dst
, st_src_reg src0
);
292 void emit_scalar(ir_instruction
*ir
, unsigned op
,
293 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
295 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
297 void get_deref_offsets(ir_dereference
*ir
,
298 unsigned *array_size
,
303 void calc_deref_offsets(ir_dereference
*tail
,
304 unsigned *array_elements
,
306 st_src_reg
*indirect
,
308 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
315 void emit_swz(ir_expression
*ir
);
317 bool process_move_condition(ir_rvalue
*ir
);
319 void simplify_cmp(void);
321 void rename_temp_registers(struct rename_reg_pair
*renames
);
322 void get_first_temp_read(int *first_reads
);
323 void get_first_temp_write(int *first_writes
);
324 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
325 void get_last_temp_write(int *last_writes
);
327 void copy_propagate(void);
328 int eliminate_dead_code(void);
330 void merge_two_dsts(void);
331 void merge_registers(void);
332 void renumber_registers(void);
334 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
335 st_dst_reg
*l
, st_src_reg
*r
,
336 st_src_reg
*cond
, bool cond_swap
);
341 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
342 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
343 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
346 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
349 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
353 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
356 prog
->data
->LinkStatus
= linking_failure
;
360 swizzle_for_size(int size
)
362 static const int size_swizzles
[4] = {
363 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
364 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
365 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
366 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
369 assert((size
>= 1) && (size
<= 4));
370 return size_swizzles
[size
- 1];
374 glsl_to_tgsi_instruction
*
375 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
376 st_dst_reg dst
, st_dst_reg dst1
,
377 st_src_reg src0
, st_src_reg src1
,
378 st_src_reg src2
, st_src_reg src3
)
380 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
381 int num_reladdr
= 0, i
, j
;
382 bool dst_is_64bit
[2];
384 op
= get_opcode(op
, dst
, src0
, src1
);
386 /* If we have to do relative addressing, we want to load the ARL
387 * reg directly for one of the regs, and preload the other reladdr
388 * sources into temps.
390 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
391 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
392 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
393 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
394 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
395 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
397 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
398 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
399 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
400 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
402 if (dst
.reladdr
|| dst
.reladdr2
) {
404 emit_arl(ir
, address_reg
, *dst
.reladdr
);
406 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
410 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
413 assert(num_reladdr
== 0);
415 /* inst->op has only 8 bits. */
416 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
419 inst
->precise
= this->precise
;
420 inst
->info
= tgsi_get_opcode_info(op
);
427 inst
->is_64bit_expanded
= false;
430 inst
->tex_offsets
= NULL
;
431 inst
->tex_offset_num_offset
= 0;
433 inst
->tex_shadow
= 0;
434 /* default to float, for paths where this is not initialized
435 * (since 0==UINT which is likely wrong):
437 inst
->tex_type
= GLSL_TYPE_FLOAT
;
439 /* Update indirect addressing status used by TGSI */
440 if (dst
.reladdr
|| dst
.reladdr2
) {
442 case PROGRAM_STATE_VAR
:
443 case PROGRAM_CONSTANT
:
444 case PROGRAM_UNIFORM
:
445 this->indirect_addr_consts
= true;
447 case PROGRAM_IMMEDIATE
:
448 assert(!"immediates should not have indirect addressing");
455 for (i
= 0; i
< 4; i
++) {
456 if(inst
->src
[i
].reladdr
) {
457 switch(inst
->src
[i
].file
) {
458 case PROGRAM_STATE_VAR
:
459 case PROGRAM_CONSTANT
:
460 case PROGRAM_UNIFORM
:
461 this->indirect_addr_consts
= true;
463 case PROGRAM_IMMEDIATE
:
464 assert(!"immediates should not have indirect addressing");
474 * This section contains the double processing.
475 * GLSL just represents doubles as single channel values,
476 * however most HW and TGSI represent doubles as pairs of register channels.
478 * so we have to fixup destination writemask/index and src swizzle/indexes.
479 * dest writemasks need to translate from single channel write mask
480 * to a dual-channel writemask, but also need to modify the index,
481 * if we are touching the Z,W fields in the pre-translated writemask.
483 * src channels have similiar index modifications along with swizzle
484 * changes to we pick the XY, ZW pairs from the correct index.
486 * GLSL [0].x -> TGSI [0].xy
487 * GLSL [0].y -> TGSI [0].zw
488 * GLSL [0].z -> TGSI [1].xy
489 * GLSL [0].w -> TGSI [1].zw
491 for (j
= 0; j
< 2; j
++) {
492 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
493 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
494 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
495 if (glsl_base_type_is_64bit(type
))
496 dst_is_64bit
[j
] = true;
500 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
501 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
502 glsl_to_tgsi_instruction
*dinst
= NULL
;
503 int initial_src_swz
[4], initial_src_idx
[4];
504 int initial_dst_idx
[2], initial_dst_writemask
[2];
505 /* select the writemask for dst0 or dst1 */
506 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
508 /* copy out the writemask, index and swizzles for all src/dsts. */
509 for (j
= 0; j
< 2; j
++) {
510 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
511 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
514 for (j
= 0; j
< 4; j
++) {
515 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
516 initial_src_idx
[j
] = inst
->src
[j
].index
;
520 * scan all the components in the dst writemask
521 * generate an instruction for each of them if required.
526 int i
= u_bit_scan(&writemask
);
528 /* before emitting the instruction, see if we have to adjust load / store
530 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
531 addr
.file
== PROGRAM_UNDEFINED
) {
532 /* We have to advance the buffer address by 16 */
533 addr
= get_temp(glsl_type::uint_type
);
534 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
535 inst
->src
[0], st_src_reg_for_int(16));
538 /* first time use previous instruction */
542 /* create a new instructions for subsequent attempts */
543 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
548 this->instructions
.push_tail(dinst
);
549 dinst
->is_64bit_expanded
= true;
551 /* modify the destination if we are splitting */
552 for (j
= 0; j
< 2; j
++) {
553 if (dst_is_64bit
[j
]) {
554 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
555 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
557 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
558 dinst
->src
[0] = addr
;
559 if (dinst
->op
!= TGSI_OPCODE_STORE
)
560 dinst
->dst
[j
].index
++;
563 /* if we aren't writing to a double, just get the bit of the initial writemask
565 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
569 /* modify the src registers */
570 for (j
= 0; j
< 4; j
++) {
571 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
573 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
574 dinst
->src
[j
].index
= initial_src_idx
[j
];
576 dinst
->src
[j
].double_reg2
= true;
577 dinst
->src
[j
].index
++;
581 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
583 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
586 /* some opcodes are special case in what they use as sources
587 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
588 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
589 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
590 op
== TGSI_OPCODE_DLDEXP
||
591 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
592 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
599 this->instructions
.push_tail(inst
);
606 glsl_to_tgsi_instruction
*
607 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
609 st_src_reg src0
, st_src_reg src1
,
610 st_src_reg src2
, st_src_reg src3
)
612 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
616 * Determines whether to use an integer, unsigned integer, or float opcode
617 * based on the operands and input opcode, then emits the result.
620 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
622 st_src_reg src0
, st_src_reg src1
)
624 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
626 if (op
== TGSI_OPCODE_MOV
)
629 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
630 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
631 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
632 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
634 if (is_resource_instruction(op
))
636 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
637 type
= GLSL_TYPE_INT64
;
638 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
639 type
= GLSL_TYPE_UINT64
;
640 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
641 type
= GLSL_TYPE_DOUBLE
;
642 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
643 type
= GLSL_TYPE_FLOAT
;
644 else if (native_integers
)
645 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
647 #define case7(c, f, i, u, d, i64, ui64) \
648 case TGSI_OPCODE_##c: \
649 if (type == GLSL_TYPE_UINT64) \
650 op = TGSI_OPCODE_##ui64; \
651 else if (type == GLSL_TYPE_INT64) \
652 op = TGSI_OPCODE_##i64; \
653 else if (type == GLSL_TYPE_DOUBLE) \
654 op = TGSI_OPCODE_##d; \
655 else if (type == GLSL_TYPE_INT) \
656 op = TGSI_OPCODE_##i; \
657 else if (type == GLSL_TYPE_UINT) \
658 op = TGSI_OPCODE_##u; \
660 op = TGSI_OPCODE_##f; \
663 #define casecomp(c, f, i, u, d, i64, ui64) \
664 case TGSI_OPCODE_##c: \
665 if (type == GLSL_TYPE_INT64) \
666 op = TGSI_OPCODE_##i64; \
667 else if (type == GLSL_TYPE_UINT64) \
668 op = TGSI_OPCODE_##ui64; \
669 else if (type == GLSL_TYPE_DOUBLE) \
670 op = TGSI_OPCODE_##d; \
671 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
672 op = TGSI_OPCODE_##i; \
673 else if (type == GLSL_TYPE_UINT) \
674 op = TGSI_OPCODE_##u; \
675 else if (native_integers) \
676 op = TGSI_OPCODE_##f; \
678 op = TGSI_OPCODE_##c; \
682 /* Some instructions are initially selected without considering the type.
683 * This fixes the type:
685 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
687 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
688 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
689 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
690 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
691 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
692 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
693 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
694 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
695 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
696 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
697 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
698 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
699 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
700 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
701 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
702 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
704 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
705 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
706 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
707 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
708 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
709 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
710 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
711 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
713 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
714 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
715 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
716 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
721 assert(op
!= TGSI_OPCODE_LAST
);
725 glsl_to_tgsi_instruction
*
726 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
727 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
730 static const unsigned dot_opcodes
[] = {
731 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
734 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
738 * Emits TGSI scalar opcodes to produce unique answers across channels.
740 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
741 * channel determines the result across all channels. So to do a vec4
742 * of this operation, we want to emit a scalar per source channel used
743 * to produce dest channels.
746 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
748 st_src_reg orig_src0
, st_src_reg orig_src1
)
751 int done_mask
= ~dst
.writemask
;
753 /* TGSI RCP is a scalar operation splatting results to all channels,
754 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
757 for (i
= 0; i
< 4; i
++) {
758 GLuint this_mask
= (1 << i
);
759 st_src_reg src0
= orig_src0
;
760 st_src_reg src1
= orig_src1
;
762 if (done_mask
& this_mask
)
765 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
766 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
767 for (j
= i
+ 1; j
< 4; j
++) {
768 /* If there is another enabled component in the destination that is
769 * derived from the same inputs, generate its value on this pass as
772 if (!(done_mask
& (1 << j
)) &&
773 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
774 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
775 this_mask
|= (1 << j
);
778 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
779 src0_swiz
, src0_swiz
);
780 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
781 src1_swiz
, src1_swiz
);
783 dst
.writemask
= this_mask
;
784 emit_asm(ir
, op
, dst
, src0
, src1
);
785 done_mask
|= this_mask
;
790 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
791 st_dst_reg dst
, st_src_reg src0
)
793 st_src_reg undef
= undef_src
;
795 undef
.swizzle
= SWIZZLE_XXXX
;
797 emit_scalar(ir
, op
, dst
, src0
, undef
);
801 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
802 st_dst_reg dst
, st_src_reg src0
)
804 int op
= TGSI_OPCODE_ARL
;
806 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
807 op
= TGSI_OPCODE_UARL
;
809 assert(dst
.file
== PROGRAM_ADDRESS
);
810 if (dst
.index
>= this->num_address_regs
)
811 this->num_address_regs
= dst
.index
+ 1;
813 emit_asm(NULL
, op
, dst
, src0
);
817 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
818 gl_constant_value values
[8], int size
, int datatype
,
819 uint16_t *swizzle_out
)
821 if (file
== PROGRAM_CONSTANT
) {
822 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
823 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
824 size
, datatype
, &swizzle
);
826 *swizzle_out
= swizzle
;
830 assert(file
== PROGRAM_IMMEDIATE
);
833 immediate_storage
*entry
;
834 int size32
= size
* ((datatype
== GL_DOUBLE
||
835 datatype
== GL_INT64_ARB
||
836 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
839 /* Search immediate storage to see if we already have an identical
840 * immediate that we can use instead of adding a duplicate entry.
842 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
843 immediate_storage
*tmp
= entry
;
845 for (i
= 0; i
* 4 < size32
; i
++) {
846 int slot_size
= MIN2(size32
- (i
* 4), 4);
847 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
849 if (memcmp(tmp
->values
, &values
[i
* 4],
850 slot_size
* sizeof(gl_constant_value
)))
853 /* Everything matches, keep going until the full size is matched */
854 tmp
= (immediate_storage
*)tmp
->next
;
857 /* The full value matched */
864 for (i
= 0; i
* 4 < size32
; i
++) {
865 int slot_size
= MIN2(size32
- (i
* 4), 4);
866 /* Add this immediate to the list. */
867 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
868 this->immediates
.push_tail(entry
);
869 this->num_immediates
++;
875 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
877 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
878 union gl_constant_value uval
;
881 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
887 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
889 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
890 union gl_constant_value uval
[2];
892 memcpy(uval
, &val
, sizeof(uval
));
893 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
894 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
899 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
901 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
902 union gl_constant_value uval
;
904 assert(native_integers
);
907 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
913 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
915 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
916 union gl_constant_value uval
[2];
918 memcpy(uval
, &val
, sizeof(uval
));
919 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
920 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
926 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
929 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
930 st_src_reg_for_int(val
);
932 return st_src_reg_for_float(val
);
936 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
938 return type
->count_attribute_slots(is_vs_input
);
942 type_size(const struct glsl_type
*type
)
944 return type
->count_attribute_slots(false);
948 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
949 exec_list
*instructions
, ir_constant
*access
)
952 * emit_asm() might have actually split the op into pieces, e.g. for
953 * double stores. We have to go back and fix up all the generated ops.
955 unsigned op
= inst
->op
;
957 inst
->resource
= *buf
;
959 inst
->buffer_access
= access
->value
.u
[0];
961 if (inst
== instructions
->get_head_raw())
963 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
965 if (inst
->op
== TGSI_OPCODE_UADD
) {
966 if (inst
== instructions
->get_head_raw())
968 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
970 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
974 * If the given GLSL type is an array or matrix or a structure containing
975 * an array/matrix member, return true. Else return false.
977 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
978 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
979 * we have an array that might be indexed with a variable, we need to use
980 * the later storage type.
983 type_has_array_or_matrix(const glsl_type
*type
)
985 if (type
->is_array() || type
->is_matrix())
988 if (type
->is_record()) {
989 for (unsigned i
= 0; i
< type
->length
; i
++) {
990 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1001 * In the initial pass of codegen, we assign temporary numbers to
1002 * intermediate results. (not SSA -- variable assignments will reuse
1006 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1010 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1015 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1016 if (next_array
>= max_num_arrays
) {
1017 max_num_arrays
+= 32;
1018 array_sizes
= (unsigned*)
1019 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1022 src
.file
= PROGRAM_ARRAY
;
1024 src
.array_id
= next_array
+ 1;
1025 array_sizes
[next_array
] = type_size(type
);
1029 src
.file
= PROGRAM_TEMPORARY
;
1030 src
.index
= next_temp
;
1031 next_temp
+= type_size(type
);
1034 if (type
->is_array() || type
->is_record()) {
1035 src
.swizzle
= SWIZZLE_NOOP
;
1037 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1044 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1046 struct hash_entry
*entry
;
1048 entry
= _mesa_hash_table_search(this->variables
, var
);
1052 return (variable_storage
*)entry
->data
;
1056 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1058 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1059 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1060 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1063 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1065 const ir_state_slot
*const slots
= ir
->get_state_slots();
1066 assert(slots
!= NULL
);
1068 /* Check if this statevar's setup in the STATE file exactly
1069 * matches how we'll want to reference it as a
1070 * struct/array/whatever. If not, then we need to move it into
1071 * temporary storage and hope that it'll get copy-propagated
1074 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1075 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1080 variable_storage
*storage
;
1082 if (i
== ir
->get_num_state_slots()) {
1083 /* We'll set the index later. */
1084 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1086 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1090 /* The variable_storage constructor allocates slots based on the size
1091 * of the type. However, this had better match the number of state
1092 * elements that we're going to copy into the new temporary.
1094 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1096 dst
= st_dst_reg(get_temp(ir
->type
));
1098 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1101 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1105 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1106 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1107 (gl_state_index
*)slots
[i
].tokens
);
1109 if (storage
->file
== PROGRAM_STATE_VAR
) {
1110 if (storage
->index
== -1) {
1111 storage
->index
= index
;
1113 assert(index
== storage
->index
+ (int)i
);
1116 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1117 * the data being moved since MOV does not care about the type of
1118 * data it is moving, and we don't want to declare registers with
1119 * array or struct types.
1121 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1122 src
.swizzle
= slots
[i
].swizzle
;
1123 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1124 /* even a float takes up a whole vec4 reg in a struct/array. */
1129 if (storage
->file
== PROGRAM_TEMPORARY
&&
1130 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1131 fail_link(this->shader_program
,
1132 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1133 ir
->name
, dst
.index
- storage
->index
,
1134 type_size(ir
->type
));
1140 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1142 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1144 visit_exec_list(&ir
->body_instructions
, this);
1146 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1150 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1153 case ir_loop_jump::jump_break
:
1154 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1156 case ir_loop_jump::jump_continue
:
1157 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1164 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1171 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1173 /* Ignore function bodies other than main() -- we shouldn't see calls to
1174 * them since they should all be inlined before we get to glsl_to_tgsi.
1176 if (strcmp(ir
->name
, "main") == 0) {
1177 const ir_function_signature
*sig
;
1180 sig
= ir
->matching_signature(NULL
, &empty
, false);
1184 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1191 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1193 int nonmul_operand
= 1 - mul_operand
;
1195 st_dst_reg result_dst
;
1197 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1198 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1201 expr
->operands
[0]->accept(this);
1203 expr
->operands
[1]->accept(this);
1205 ir
->operands
[nonmul_operand
]->accept(this);
1208 this->result
= get_temp(ir
->type
);
1209 result_dst
= st_dst_reg(this->result
);
1210 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1211 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1217 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1219 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1220 * implemented using multiplication, and logical-or is implemented using
1221 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1222 * As result, the logical expression (a & !b) can be rewritten as:
1226 * - (a * 1) - (a * b)
1230 * This final expression can be implemented as a single MAD(a, -b, a)
1234 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1236 const int other_operand
= 1 - try_operand
;
1239 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1240 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1243 ir
->operands
[other_operand
]->accept(this);
1245 expr
->operands
[0]->accept(this);
1248 b
.negate
= ~b
.negate
;
1250 this->result
= get_temp(ir
->type
);
1251 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1257 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1258 st_src_reg
*reg
, int *num_reladdr
)
1260 if (!reg
->reladdr
&& !reg
->reladdr2
)
1263 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1264 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1266 if (*num_reladdr
!= 1) {
1267 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1269 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1277 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1279 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1281 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1283 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1284 if (try_emit_mad(ir
, 1))
1286 if (try_emit_mad(ir
, 0))
1290 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1292 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1293 if (try_emit_mad_for_and_not(ir
, 1))
1295 if (try_emit_mad_for_and_not(ir
, 0))
1299 if (ir
->operation
== ir_quadop_vector
)
1300 assert(!"ir_quadop_vector should have been lowered");
1302 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1303 this->result
.file
= PROGRAM_UNDEFINED
;
1304 ir
->operands
[operand
]->accept(this);
1305 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1306 printf("Failed to get tree for expression operand:\n");
1307 ir
->operands
[operand
]->print();
1311 op
[operand
] = this->result
;
1313 /* Matrix expression operands should have been broken down to vector
1314 * operations already.
1316 assert(!ir
->operands
[operand
]->type
->is_matrix());
1319 visit_expression(ir
, op
);
1322 /* The non-recursive part of the expression visitor lives in a separate
1323 * function and should be prevented from being inlined, to avoid a stack
1324 * explosion when deeply nested expressions are visited.
1327 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1329 st_src_reg result_src
;
1330 st_dst_reg result_dst
;
1332 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1333 if (ir
->operands
[1]) {
1334 vector_elements
= MAX2(vector_elements
,
1335 ir
->operands
[1]->type
->vector_elements
);
1338 this->result
.file
= PROGRAM_UNDEFINED
;
1340 /* Storage for our result. Ideally for an assignment we'd be using
1341 * the actual storage for the result here, instead.
1343 result_src
= get_temp(ir
->type
);
1344 /* convenience for the emit functions below. */
1345 result_dst
= st_dst_reg(result_src
);
1346 /* Limit writes to the channels that will be used by result_src later.
1347 * This does limit this temp's use as a temporary for multi-instruction
1350 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1352 switch (ir
->operation
) {
1353 case ir_unop_logic_not
:
1354 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1355 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1357 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1358 * older GPUs implement SEQ using multiple instructions (i915 uses two
1359 * SGE instructions and a MUL instruction). Since our logic values are
1360 * 0.0 and 1.0, 1-x also implements !x.
1362 op
[0].negate
= ~op
[0].negate
;
1363 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1367 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1368 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1369 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1370 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1371 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1372 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1374 op
[0].negate
= ~op
[0].negate
;
1378 case ir_unop_subroutine_to_int
:
1379 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1382 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1383 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1384 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1385 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1386 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1387 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1389 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1392 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1395 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1399 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1402 assert(!"not reached: should be handled by exp_to_exp2");
1405 assert(!"not reached: should be handled by log_to_log2");
1408 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1411 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1414 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1416 case ir_unop_saturate
: {
1417 glsl_to_tgsi_instruction
*inst
;
1418 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1419 inst
->saturate
= true;
1424 case ir_unop_dFdx_coarse
:
1425 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1427 case ir_unop_dFdx_fine
:
1428 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1431 case ir_unop_dFdy_coarse
:
1432 case ir_unop_dFdy_fine
:
1434 /* The X component contains 1 or -1 depending on whether the framebuffer
1435 * is a FBO or the window system buffer, respectively.
1436 * It is then multiplied with the source operand of DDY.
1438 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1439 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1441 unsigned transform_y_index
=
1442 _mesa_add_state_reference(this->prog
->Parameters
,
1445 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1447 glsl_type::vec4_type
);
1448 transform_y
.swizzle
= SWIZZLE_XXXX
;
1450 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1452 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1453 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1454 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1458 case ir_unop_frexp_sig
:
1459 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1462 case ir_unop_frexp_exp
:
1463 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1466 case ir_unop_noise
: {
1467 /* At some point, a motivated person could add a better
1468 * implementation of noise. Currently not even the nvidia
1469 * binary drivers do anything more than this. In any case, the
1470 * place to do this is in the GL state tracker, not the poor
1473 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1478 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1481 op
[1].negate
= ~op
[1].negate
;
1482 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1486 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1489 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1492 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1493 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1495 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1499 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1501 case ir_binop_greater
:
1502 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1504 case ir_binop_lequal
:
1505 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1507 case ir_binop_gequal
:
1508 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1510 case ir_binop_equal
:
1511 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1513 case ir_binop_nequal
:
1514 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1516 case ir_binop_all_equal
:
1517 /* "==" operator producing a scalar boolean. */
1518 if (ir
->operands
[0]->type
->is_vector() ||
1519 ir
->operands
[1]->type
->is_vector()) {
1520 st_src_reg temp
= get_temp(native_integers
?
1521 glsl_type::uvec4_type
:
1522 glsl_type::vec4_type
);
1524 if (native_integers
) {
1525 st_dst_reg temp_dst
= st_dst_reg(temp
);
1526 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1528 if (ir
->operands
[0]->type
->is_boolean() &&
1529 ir
->operands
[1]->as_constant() &&
1530 ir
->operands
[1]->as_constant()->is_one()) {
1531 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1533 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1536 /* Emit 1-3 AND operations to combine the SEQ results. */
1537 switch (ir
->operands
[0]->type
->vector_elements
) {
1541 temp_dst
.writemask
= WRITEMASK_Y
;
1542 temp1
.swizzle
= SWIZZLE_YYYY
;
1543 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1544 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1547 temp_dst
.writemask
= WRITEMASK_X
;
1548 temp1
.swizzle
= SWIZZLE_XXXX
;
1549 temp2
.swizzle
= SWIZZLE_YYYY
;
1550 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1551 temp_dst
.writemask
= WRITEMASK_Y
;
1552 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1553 temp2
.swizzle
= SWIZZLE_WWWW
;
1554 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1557 temp1
.swizzle
= SWIZZLE_XXXX
;
1558 temp2
.swizzle
= SWIZZLE_YYYY
;
1559 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1561 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1563 /* After the dot-product, the value will be an integer on the
1564 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1566 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1568 /* Negating the result of the dot-product gives values on the range
1569 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1570 * This is achieved using SGE.
1572 st_src_reg sge_src
= result_src
;
1573 sge_src
.negate
= ~sge_src
.negate
;
1574 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1577 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1580 case ir_binop_any_nequal
:
1581 /* "!=" operator producing a scalar boolean. */
1582 if (ir
->operands
[0]->type
->is_vector() ||
1583 ir
->operands
[1]->type
->is_vector()) {
1584 st_src_reg temp
= get_temp(native_integers
?
1585 glsl_type::uvec4_type
:
1586 glsl_type::vec4_type
);
1587 if (ir
->operands
[0]->type
->is_boolean() &&
1588 ir
->operands
[1]->as_constant() &&
1589 ir
->operands
[1]->as_constant()->is_zero()) {
1590 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1592 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1595 if (native_integers
) {
1596 st_dst_reg temp_dst
= st_dst_reg(temp
);
1597 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1599 /* Emit 1-3 OR operations to combine the SNE results. */
1600 switch (ir
->operands
[0]->type
->vector_elements
) {
1604 temp_dst
.writemask
= WRITEMASK_Y
;
1605 temp1
.swizzle
= SWIZZLE_YYYY
;
1606 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1607 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1610 temp_dst
.writemask
= WRITEMASK_X
;
1611 temp1
.swizzle
= SWIZZLE_XXXX
;
1612 temp2
.swizzle
= SWIZZLE_YYYY
;
1613 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1614 temp_dst
.writemask
= WRITEMASK_Y
;
1615 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1616 temp2
.swizzle
= SWIZZLE_WWWW
;
1617 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1620 temp1
.swizzle
= SWIZZLE_XXXX
;
1621 temp2
.swizzle
= SWIZZLE_YYYY
;
1622 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1624 /* After the dot-product, the value will be an integer on the
1625 * range [0,4]. Zero stays zero, and positive values become 1.0.
1627 glsl_to_tgsi_instruction
*const dp
=
1628 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1629 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1630 /* The clamping to [0,1] can be done for free in the fragment
1631 * shader with a saturate.
1633 dp
->saturate
= true;
1635 /* Negating the result of the dot-product gives values on the range
1636 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1637 * achieved using SLT.
1639 st_src_reg slt_src
= result_src
;
1640 slt_src
.negate
= ~slt_src
.negate
;
1641 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1645 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1649 case ir_binop_logic_xor
:
1650 if (native_integers
)
1651 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1653 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1656 case ir_binop_logic_or
: {
1657 if (native_integers
) {
1658 /* If integers are used as booleans, we can use an actual "or"
1661 assert(native_integers
);
1662 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1664 /* After the addition, the value will be an integer on the
1665 * range [0,2]. Zero stays zero, and positive values become 1.0.
1667 glsl_to_tgsi_instruction
*add
=
1668 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1669 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1670 /* The clamping to [0,1] can be done for free in the fragment
1671 * shader with a saturate if floats are being used as boolean values.
1673 add
->saturate
= true;
1675 /* Negating the result of the addition gives values on the range
1676 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1677 * is achieved using SLT.
1679 st_src_reg slt_src
= result_src
;
1680 slt_src
.negate
= ~slt_src
.negate
;
1681 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1687 case ir_binop_logic_and
:
1688 /* If native integers are disabled, the bool args are stored as float 0.0
1689 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1690 * actual AND opcode.
1692 if (native_integers
)
1693 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1695 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1699 assert(ir
->operands
[0]->type
->is_vector());
1700 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1701 emit_dp(ir
, result_dst
, op
[0], op
[1],
1702 ir
->operands
[0]->type
->vector_elements
);
1707 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1709 /* This is the only instruction sequence that makes the game "Risen"
1710 * render correctly. ABS is not required for the game, but since GLSL
1711 * declares negative values as "undefined", allowing us to do whatever
1712 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1715 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1716 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1720 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1723 if (native_integers
) {
1724 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1727 /* fallthrough to next case otherwise */
1729 if (native_integers
) {
1730 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1733 /* fallthrough to next case otherwise */
1736 case ir_unop_i642u64
:
1737 case ir_unop_u642i64
:
1738 /* Converting between signed and unsigned integers is a no-op. */
1740 result_src
.type
= result_dst
.type
;
1743 if (native_integers
) {
1744 /* Booleans are stored as integers using ~0 for true and 0 for false.
1745 * GLSL requires that int(bool) return 1 for true and 0 for false.
1746 * This conversion is done with AND, but it could be done with NEG.
1748 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1750 /* Booleans and integers are both stored as floats when native
1751 * integers are disabled.
1757 if (native_integers
)
1758 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1760 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1763 if (native_integers
)
1764 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1766 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1768 case ir_unop_bitcast_f2i
:
1769 case ir_unop_bitcast_f2u
:
1770 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1771 if (op
[0].negate
|| op
[0].abs
)
1772 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1775 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1778 case ir_unop_bitcast_i2f
:
1779 case ir_unop_bitcast_u2f
:
1781 result_src
.type
= GLSL_TYPE_FLOAT
;
1784 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1787 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1790 if (native_integers
)
1791 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1793 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1795 case ir_unop_bitcast_u642d
:
1796 case ir_unop_bitcast_i642d
:
1798 result_src
.type
= GLSL_TYPE_DOUBLE
;
1800 case ir_unop_bitcast_d2i64
:
1802 result_src
.type
= GLSL_TYPE_INT64
;
1804 case ir_unop_bitcast_d2u64
:
1806 result_src
.type
= GLSL_TYPE_UINT64
;
1809 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1812 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1815 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1817 case ir_unop_round_even
:
1818 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1821 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1825 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1828 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1831 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1834 case ir_unop_bit_not
:
1835 if (native_integers
) {
1836 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1840 if (native_integers
) {
1841 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1844 case ir_binop_lshift
:
1845 case ir_binop_rshift
:
1846 if (native_integers
) {
1847 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
1851 if (glsl_base_type_is_64bit(op
[0].type
)) {
1852 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1855 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
1856 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1861 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1864 case ir_binop_bit_and
:
1865 if (native_integers
) {
1866 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1869 case ir_binop_bit_xor
:
1870 if (native_integers
) {
1871 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1874 case ir_binop_bit_or
:
1875 if (native_integers
) {
1876 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1880 assert(!"GLSL 1.30 features unsupported");
1883 case ir_binop_ubo_load
: {
1884 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1885 ir_rvalue
*block
= ir
->operands
[0];
1886 ir_rvalue
*offset
= ir
->operands
[1];
1887 ir_constant
*const_block
= block
->as_constant();
1889 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1890 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1891 ir
->type
->base_type
);
1893 cbuf
.has_index2
= true;
1896 block
->accept(this);
1897 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1898 *cbuf
.reladdr
= this->result
;
1899 emit_arl(ir
, sampler_reladdr
, this->result
);
1902 /* Calculate the surface offset */
1903 offset
->accept(this);
1904 st_src_reg off
= this->result
;
1906 glsl_to_tgsi_instruction
*inst
=
1907 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1909 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1910 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1911 st_src_reg_for_int(0));
1913 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1916 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1917 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1918 unsigned const_offset
= const_offset_ir
?
1919 const_offset_ir
->value
.u
[0] : 0;
1920 unsigned const_block
= const_uniform_block
?
1921 const_uniform_block
->value
.u
[0] + 1 : 1;
1922 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1925 cbuf
.type
= ir
->type
->base_type
;
1926 cbuf
.file
= PROGRAM_CONSTANT
;
1928 cbuf
.reladdr
= NULL
;
1931 cbuf
.index2D
= const_block
;
1933 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1935 if (const_offset_ir
) {
1936 /* Constant index into constant buffer */
1937 cbuf
.reladdr
= NULL
;
1938 cbuf
.index
= const_offset
/ 16;
1940 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
1941 st_src_reg offset
= op
[1];
1943 /* The OpenGL spec is written in such a way that accesses with
1944 * non-constant offset are almost always vec4-aligned. The only
1945 * exception to this are members of structs in arrays of structs:
1946 * each struct in an array of structs is at least vec4-aligned,
1947 * but single-element and [ui]vec2 members of the struct may be at
1948 * an offset that is not a multiple of 16 bytes.
1950 * Here, we extract that offset, relying on previous passes to
1951 * always generate offset expressions of the form
1952 * (+ expr constant_offset).
1954 * Note that the std430 layout, which allows more cases of
1955 * alignment less than vec4 in arrays, is not supported for
1956 * uniform blocks, so we do not have to deal with it here.
1958 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
1959 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
1960 if (const_offset_ir
) {
1961 const_offset
= const_offset_ir
->value
.u
[0];
1962 cbuf
.index
= const_offset
/ 16;
1963 offset_expr
->operands
[0]->accept(this);
1964 offset
= this->result
;
1968 /* Relative/variable index into constant buffer */
1969 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
1970 st_src_reg_for_int(4));
1971 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1972 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
1975 if (const_uniform_block
) {
1976 /* Constant constant buffer */
1977 cbuf
.reladdr2
= NULL
;
1979 /* Relative/variable constant buffer */
1980 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
1981 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
1983 cbuf
.has_index2
= true;
1985 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1986 if (glsl_base_type_is_64bit(cbuf
.type
))
1987 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
1988 const_offset
% 16 / 8,
1989 const_offset
% 16 / 8,
1990 const_offset
% 16 / 8);
1992 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
1993 const_offset
% 16 / 4,
1994 const_offset
% 16 / 4,
1995 const_offset
% 16 / 4);
1997 if (ir
->type
->is_boolean()) {
1998 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
1999 st_src_reg_for_int(0));
2001 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2007 /* note: we have to reorder the three args here */
2008 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2011 if (this->ctx
->Const
.NativeIntegers
)
2012 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2014 op
[0].negate
= ~op
[0].negate
;
2015 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2018 case ir_triop_bitfield_extract
:
2019 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2021 case ir_quadop_bitfield_insert
:
2022 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2024 case ir_unop_bitfield_reverse
:
2025 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2027 case ir_unop_bit_count
:
2028 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2030 case ir_unop_find_msb
:
2031 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2033 case ir_unop_find_lsb
:
2034 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2036 case ir_binop_imul_high
:
2037 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2040 /* In theory, MAD is incorrect here. */
2042 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2044 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2046 case ir_unop_interpolate_at_centroid
:
2047 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2049 case ir_binop_interpolate_at_offset
: {
2050 /* The y coordinate needs to be flipped for the default fb */
2051 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2052 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2054 unsigned transform_y_index
=
2055 _mesa_add_state_reference(this->prog
->Parameters
,
2058 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2060 glsl_type::vec4_type
);
2061 transform_y
.swizzle
= SWIZZLE_XXXX
;
2063 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2064 st_dst_reg temp_dst
= st_dst_reg(temp
);
2066 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2067 temp_dst
.writemask
= WRITEMASK_Y
;
2068 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2069 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2072 case ir_binop_interpolate_at_sample
:
2073 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2077 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2080 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2083 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2086 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2089 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2092 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2094 case ir_unop_unpack_double_2x32
:
2095 case ir_unop_pack_double_2x32
:
2096 case ir_unop_unpack_int_2x32
:
2097 case ir_unop_pack_int_2x32
:
2098 case ir_unop_unpack_uint_2x32
:
2099 case ir_unop_pack_uint_2x32
:
2100 case ir_unop_unpack_sampler_2x32
:
2101 case ir_unop_pack_sampler_2x32
:
2102 case ir_unop_unpack_image_2x32
:
2103 case ir_unop_pack_image_2x32
:
2104 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2107 case ir_binop_ldexp
:
2108 if (ir
->operands
[0]->type
->is_double()) {
2109 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2111 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2115 case ir_unop_pack_half_2x16
:
2116 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2118 case ir_unop_unpack_half_2x16
:
2119 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2122 case ir_unop_get_buffer_size
: {
2123 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2126 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2127 (const_offset
? const_offset
->value
.u
[0] : 0),
2129 if (!const_offset
) {
2130 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2131 *buffer
.reladdr
= op
[0];
2132 emit_arl(ir
, sampler_reladdr
, op
[0]);
2134 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2140 case ir_unop_b2i64
: {
2141 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2142 st_dst_reg temp_dst
= st_dst_reg(temp
);
2143 unsigned orig_swz
= op
[0].swizzle
;
2145 * To convert unsigned to 64-bit:
2146 * zero Y channel, copy X channel.
2148 temp_dst
.writemask
= WRITEMASK_Y
;
2149 if (vector_elements
> 1)
2150 temp_dst
.writemask
|= WRITEMASK_W
;
2151 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2152 temp_dst
.writemask
= WRITEMASK_X
;
2153 if (vector_elements
> 1)
2154 temp_dst
.writemask
|= WRITEMASK_Z
;
2155 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2156 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2157 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2158 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2160 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2162 result_src
.type
= GLSL_TYPE_UINT64
;
2163 if (vector_elements
> 2) {
2164 /* Subtle: We rely on the fact that get_temp here returns the next
2165 * TGSI temporary register directly after the temp register used for
2166 * the first two components, so that the result gets picked up
2169 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2170 st_dst_reg temp_dst
= st_dst_reg(temp
);
2171 temp_dst
.writemask
= WRITEMASK_Y
;
2172 if (vector_elements
> 3)
2173 temp_dst
.writemask
|= WRITEMASK_W
;
2174 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2176 temp_dst
.writemask
= WRITEMASK_X
;
2177 if (vector_elements
> 3)
2178 temp_dst
.writemask
|= WRITEMASK_Z
;
2179 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2180 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2181 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2182 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2184 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2191 case ir_unop_i642u
: {
2192 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2193 st_dst_reg temp_dst
= st_dst_reg(temp
);
2194 unsigned orig_swz
= op
[0].swizzle
;
2195 unsigned orig_idx
= op
[0].index
;
2197 temp_dst
.writemask
= WRITEMASK_X
;
2199 for (el
= 0; el
< vector_elements
; el
++) {
2200 unsigned swz
= GET_SWZ(orig_swz
, el
);
2202 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2204 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2206 op
[0].index
= orig_idx
+ 1;
2207 op
[0].type
= GLSL_TYPE_UINT
;
2208 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2209 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2212 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2213 result_src
.type
= GLSL_TYPE_UINT
;
2215 result_src
.type
= GLSL_TYPE_INT
;
2219 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int64(0));
2222 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2225 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2228 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2231 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2234 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2237 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2240 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2243 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2246 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2249 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2251 /* these might be needed */
2252 case ir_unop_pack_snorm_2x16
:
2253 case ir_unop_pack_unorm_2x16
:
2254 case ir_unop_pack_snorm_4x8
:
2255 case ir_unop_pack_unorm_4x8
:
2257 case ir_unop_unpack_snorm_2x16
:
2258 case ir_unop_unpack_unorm_2x16
:
2259 case ir_unop_unpack_snorm_4x8
:
2260 case ir_unop_unpack_unorm_4x8
:
2262 case ir_quadop_vector
:
2263 case ir_binop_vector_extract
:
2264 case ir_triop_vector_insert
:
2265 case ir_binop_carry
:
2266 case ir_binop_borrow
:
2267 case ir_unop_ssbo_unsized_array_length
:
2268 /* This operation is not supported, or should have already been handled.
2270 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2274 this->result
= result_src
;
2279 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2285 /* Note that this is only swizzles in expressions, not those on the left
2286 * hand side of an assignment, which do write masking. See ir_assignment
2290 ir
->val
->accept(this);
2292 assert(src
.file
!= PROGRAM_UNDEFINED
);
2293 assert(ir
->type
->vector_elements
> 0);
2295 for (i
= 0; i
< 4; i
++) {
2296 if (i
< ir
->type
->vector_elements
) {
2299 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2302 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2305 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2308 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2312 /* If the type is smaller than a vec4, replicate the last
2315 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2319 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2324 /* Test if the variable is an array. Note that geometry and
2325 * tessellation shader inputs are outputs are always arrays (except
2326 * for patch inputs), so only the array element type is considered.
2329 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2331 const glsl_type
*type
= var
->type
;
2333 *remove_array
= false;
2335 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2336 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2339 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2340 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2341 stage
== MESA_SHADER_TESS_CTRL
) &&
2343 if (!var
->type
->is_array())
2344 return false; /* a system value probably */
2346 type
= var
->type
->fields
.array
;
2347 *remove_array
= true;
2350 return type
->is_array() || type
->is_matrix();
2354 st_translate_interp_loc(ir_variable
*var
)
2356 if (var
->data
.centroid
)
2357 return TGSI_INTERPOLATE_LOC_CENTROID
;
2358 else if (var
->data
.sample
)
2359 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2361 return TGSI_INTERPOLATE_LOC_CENTER
;
2365 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2367 variable_storage
*entry
= find_variable_storage(ir
->var
);
2368 ir_variable
*var
= ir
->var
;
2372 switch (var
->data
.mode
) {
2373 case ir_var_uniform
:
2374 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2375 var
->data
.param_index
);
2376 _mesa_hash_table_insert(this->variables
, var
, entry
);
2378 case ir_var_shader_in
: {
2379 /* The linker assigns locations for varyings and attributes,
2380 * including deprecated builtins (like gl_Color), user-assign
2381 * generic attributes (glBindVertexLocation), and
2382 * user-defined varyings.
2384 assert(var
->data
.location
!= -1);
2386 const glsl_type
*type_without_array
= var
->type
->without_array();
2387 struct inout_decl
*decl
= &inputs
[num_inputs
];
2388 unsigned component
= var
->data
.location_frac
;
2389 unsigned num_components
;
2392 if (type_without_array
->is_64bit())
2393 component
= component
/ 2;
2394 if (type_without_array
->vector_elements
)
2395 num_components
= type_without_array
->vector_elements
;
2399 decl
->mesa_index
= var
->data
.location
;
2400 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2401 decl
->interp_loc
= st_translate_interp_loc(var
);
2402 decl
->base_type
= type_without_array
->base_type
;
2403 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2405 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2406 decl
->array_id
= num_input_arrays
+ 1;
2413 decl
->size
= type_size(var
->type
->fields
.array
);
2415 decl
->size
= type_size(var
->type
);
2417 entry
= new(mem_ctx
) variable_storage(var
,
2421 entry
->component
= component
;
2423 _mesa_hash_table_insert(this->variables
, var
, entry
);
2427 case ir_var_shader_out
: {
2428 assert(var
->data
.location
!= -1);
2430 const glsl_type
*type_without_array
= var
->type
->without_array();
2431 struct inout_decl
*decl
= &outputs
[num_outputs
];
2432 unsigned component
= var
->data
.location_frac
;
2433 unsigned num_components
;
2436 if (type_without_array
->is_64bit())
2437 component
= component
/ 2;
2438 if (type_without_array
->vector_elements
)
2439 num_components
= type_without_array
->vector_elements
;
2443 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2444 decl
->base_type
= type_without_array
->base_type
;
2445 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2446 if (var
->data
.stream
& (1u << 31)) {
2447 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2449 assert(var
->data
.stream
< 4);
2450 decl
->gs_out_streams
= 0;
2451 for (unsigned i
= 0; i
< num_components
; ++i
)
2452 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2455 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2456 decl
->array_id
= num_output_arrays
+ 1;
2457 num_output_arrays
++;
2463 decl
->size
= type_size(var
->type
->fields
.array
);
2465 decl
->size
= type_size(var
->type
);
2467 if (var
->data
.fb_fetch_output
) {
2468 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2469 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2470 var
->type
, component
, decl
->array_id
);
2471 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2472 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2475 entry
= new(mem_ctx
) variable_storage(var
,
2480 entry
->component
= component
;
2482 _mesa_hash_table_insert(this->variables
, var
, entry
);
2486 case ir_var_system_value
:
2487 entry
= new(mem_ctx
) variable_storage(var
,
2488 PROGRAM_SYSTEM_VALUE
,
2489 var
->data
.location
);
2492 case ir_var_temporary
:
2493 st_src_reg src
= get_temp(var
->type
);
2495 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2497 _mesa_hash_table_insert(this->variables
, var
, entry
);
2503 printf("Failed to make storage for %s\n", var
->name
);
2508 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2509 entry
->component
, entry
->array_id
);
2510 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2511 var
->data
.mode
== ir_var_shader_in
&&
2512 var
->type
->without_array()->is_double())
2513 this->result
.is_double_vertex_input
= true;
2514 if (!native_integers
)
2515 this->result
.type
= GLSL_TYPE_FLOAT
;
2519 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2520 GLbitfield64
* usage_mask
,
2521 GLbitfield64 double_usage_mask
,
2522 GLbitfield
* patch_usage_mask
)
2527 /* Fix array declarations by removing unused array elements at both ends
2528 * of the arrays. For example, mat4[3] where only mat[1] is used.
2530 for (i
= 0; i
< count
; i
++) {
2531 struct inout_decl
*decl
= &decls
[i
];
2532 if (!decl
->array_id
)
2535 /* Shrink the beginning. */
2536 for (j
= 0; j
< (int)decl
->size
; j
++) {
2537 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2538 if (*patch_usage_mask
&
2539 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2543 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2545 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2554 /* Shrink the end. */
2555 for (j
= decl
->size
-1; j
>= 0; j
--) {
2556 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2557 if (*patch_usage_mask
&
2558 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2562 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2564 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2571 /* When not all entries of an array are accessed, we mark them as used
2572 * here anyway, to ensure that the input/output mapping logic doesn't get
2575 * TODO This happens when an array isn't used via indirect access, which
2576 * some game ports do (at least eON-based). There is an optimization
2577 * opportunity here by replacing the array declaration with non-array
2578 * declarations of those slots that are actually used.
2580 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2581 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2582 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2584 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2590 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2595 ir_variable
*var
= ir
->variable_referenced();
2597 /* We only need the logic provided by st_glsl_storage_type_size()
2598 * for arrays of structs. Indirect sampler and image indexing is handled
2601 int element_size
= ir
->type
->without_array()->is_record() ?
2602 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2603 type_size(ir
->type
);
2605 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2607 ir
->array
->accept(this);
2610 if (!src
.has_index2
) {
2611 switch (this->prog
->Target
) {
2612 case GL_TESS_CONTROL_PROGRAM_NV
:
2613 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2614 !ir
->variable_referenced()->data
.patch
;
2616 case GL_TESS_EVALUATION_PROGRAM_NV
:
2617 is_2D
= src
.file
== PROGRAM_INPUT
&&
2618 !ir
->variable_referenced()->data
.patch
;
2620 case GL_GEOMETRY_PROGRAM_NV
:
2621 is_2D
= src
.file
== PROGRAM_INPUT
;
2631 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2632 src
.file
== PROGRAM_INPUT
)
2633 element_size
= attrib_type_size(ir
->type
, true);
2635 src
.index2D
= index
->value
.i
[0];
2636 src
.has_index2
= true;
2638 src
.index
+= index
->value
.i
[0] * element_size
;
2640 /* Variable index array dereference. It eats the "vec4" of the
2641 * base of the array and an index that offsets the TGSI register
2644 ir
->array_index
->accept(this);
2646 st_src_reg index_reg
;
2648 if (element_size
== 1) {
2649 index_reg
= this->result
;
2651 index_reg
= get_temp(native_integers
?
2652 glsl_type::int_type
: glsl_type::float_type
);
2654 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2655 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2658 /* If there was already a relative address register involved, add the
2659 * new and the old together to get the new offset.
2661 if (!is_2D
&& src
.reladdr
!= NULL
) {
2662 st_src_reg accum_reg
= get_temp(native_integers
?
2663 glsl_type::int_type
: glsl_type::float_type
);
2665 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2666 index_reg
, *src
.reladdr
);
2668 index_reg
= accum_reg
;
2672 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2673 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2675 src
.has_index2
= true;
2677 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2678 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2682 /* Change the register type to the element type of the array. */
2683 src
.type
= ir
->type
->base_type
;
2689 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2692 const glsl_type
*struct_type
= ir
->record
->type
;
2693 ir_variable
*var
= ir
->record
->variable_referenced();
2696 ir
->record
->accept(this);
2698 assert(ir
->field_idx
>= 0);
2700 for (i
= 0; i
< struct_type
->length
; i
++) {
2701 if (i
== (unsigned) ir
->field_idx
)
2703 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2704 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2707 /* If the type is smaller than a vec4, replicate the last channel out. */
2708 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2709 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2711 this->result
.swizzle
= SWIZZLE_NOOP
;
2713 this->result
.index
+= offset
;
2714 this->result
.type
= ir
->type
->base_type
;
2718 * We want to be careful in assignment setup to hit the actual storage
2719 * instead of potentially using a temporary like we might with the
2720 * ir_dereference handler.
2723 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2725 /* The LHS must be a dereference. If the LHS is a variable indexed array
2726 * access of a vector, it must be separated into a series conditional moves
2727 * before reaching this point (see ir_vec_index_to_cond_assign).
2729 assert(ir
->as_dereference());
2730 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2732 assert(!deref_array
->array
->type
->is_vector());
2735 /* Use the rvalue deref handler for the most part. We write swizzles using
2736 * the writemask, but we do extract the base component for enhanced layouts
2737 * from the source swizzle.
2740 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2741 return st_dst_reg(v
->result
);
2745 * Process the condition of a conditional assignment
2747 * Examines the condition of a conditional assignment to generate the optimal
2748 * first operand of a \c CMP instruction. If the condition is a relational
2749 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2750 * used as the source for the \c CMP instruction. Otherwise the comparison
2751 * is processed to a boolean result, and the boolean result is used as the
2752 * operand to the CMP instruction.
2755 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2757 ir_rvalue
*src_ir
= ir
;
2759 bool switch_order
= false;
2761 ir_expression
*const expr
= ir
->as_expression();
2763 if (native_integers
) {
2764 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2765 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2766 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2767 type
== GLSL_TYPE_BOOL
) {
2768 if (expr
->operation
== ir_binop_equal
) {
2769 if (expr
->operands
[0]->is_zero()) {
2770 src_ir
= expr
->operands
[1];
2771 switch_order
= true;
2773 else if (expr
->operands
[1]->is_zero()) {
2774 src_ir
= expr
->operands
[0];
2775 switch_order
= true;
2778 else if (expr
->operation
== ir_binop_nequal
) {
2779 if (expr
->operands
[0]->is_zero()) {
2780 src_ir
= expr
->operands
[1];
2782 else if (expr
->operands
[1]->is_zero()) {
2783 src_ir
= expr
->operands
[0];
2789 src_ir
->accept(this);
2790 return switch_order
;
2793 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2794 bool zero_on_left
= false;
2796 if (expr
->operands
[0]->is_zero()) {
2797 src_ir
= expr
->operands
[1];
2798 zero_on_left
= true;
2799 } else if (expr
->operands
[1]->is_zero()) {
2800 src_ir
= expr
->operands
[0];
2801 zero_on_left
= false;
2805 * (a < 0) T F F ( a < 0) T F F
2806 * (0 < a) F F T (-a < 0) F F T
2807 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2808 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2809 * (a > 0) F F T (-a < 0) F F T
2810 * (0 > a) T F F ( a < 0) T F F
2811 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2812 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2814 * Note that exchanging the order of 0 and 'a' in the comparison simply
2815 * means that the value of 'a' should be negated.
2818 switch (expr
->operation
) {
2820 switch_order
= false;
2821 negate
= zero_on_left
;
2824 case ir_binop_greater
:
2825 switch_order
= false;
2826 negate
= !zero_on_left
;
2829 case ir_binop_lequal
:
2830 switch_order
= true;
2831 negate
= !zero_on_left
;
2834 case ir_binop_gequal
:
2835 switch_order
= true;
2836 negate
= zero_on_left
;
2840 /* This isn't the right kind of comparison afterall, so make sure
2841 * the whole condition is visited.
2849 src_ir
->accept(this);
2851 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2852 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2853 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2854 * computing the condition.
2857 this->result
.negate
= ~this->result
.negate
;
2859 return switch_order
;
2863 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2864 st_dst_reg
*l
, st_src_reg
*r
,
2865 st_src_reg
*cond
, bool cond_swap
)
2867 if (type
->is_record()) {
2868 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2869 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2875 if (type
->is_array()) {
2876 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2877 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2882 if (type
->is_matrix()) {
2883 const struct glsl_type
*vec_type
;
2885 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2886 type
->vector_elements
, 1);
2888 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2889 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2894 assert(type
->is_scalar() || type
->is_vector());
2896 l
->type
= type
->base_type
;
2897 r
->type
= type
->base_type
;
2899 st_src_reg l_src
= st_src_reg(*l
);
2900 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2902 if (native_integers
) {
2903 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2904 cond_swap
? l_src
: *r
,
2905 cond_swap
? *r
: l_src
);
2907 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2908 cond_swap
? l_src
: *r
,
2909 cond_swap
? *r
: l_src
);
2912 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2916 if (type
->is_dual_slot()) {
2918 if (r
->is_double_vertex_input
== false)
2924 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2930 /* all generated instructions need to be flaged as precise */
2931 this->precise
= is_precise(ir
->lhs
->variable_referenced());
2932 ir
->rhs
->accept(this);
2935 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2939 int first_enabled_chan
= 0;
2941 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2943 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2944 variable
->data
.mode
== ir_var_shader_out
&&
2945 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2946 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2947 assert(ir
->lhs
->type
->is_scalar());
2948 assert(ir
->write_mask
== WRITEMASK_X
);
2950 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2951 l
.writemask
= WRITEMASK_Z
;
2953 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2954 l
.writemask
= WRITEMASK_Y
;
2956 } else if (ir
->write_mask
== 0) {
2957 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2959 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2962 l
.writemask
= u_bit_consecutive(0, num_elements
);
2964 /* The type is a struct or an array of (array of) structs. */
2965 l
.writemask
= WRITEMASK_XYZW
;
2968 l
.writemask
= ir
->write_mask
;
2971 for (int i
= 0; i
< 4; i
++) {
2972 if (l
.writemask
& (1 << i
)) {
2973 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2978 l
.writemask
= l
.writemask
<< dst_component
;
2980 /* Swizzle a small RHS vector into the channels being written.
2982 * glsl ir treats write_mask as dictating how many channels are
2983 * present on the RHS while TGSI treats write_mask as just
2984 * showing which channels of the vec4 RHS get written.
2986 for (int i
= 0; i
< 4; i
++) {
2987 if (l
.writemask
& (1 << i
))
2988 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2990 swizzles
[i
] = first_enabled_chan
;
2992 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2993 swizzles
[2], swizzles
[3]);
2996 assert(l
.file
!= PROGRAM_UNDEFINED
);
2997 assert(r
.file
!= PROGRAM_UNDEFINED
);
2999 if (ir
->condition
) {
3000 const bool switch_order
= this->process_move_condition(ir
->condition
);
3001 st_src_reg condition
= this->result
;
3003 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3004 } else if (ir
->rhs
->as_expression() &&
3005 this->instructions
.get_tail() &&
3006 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3007 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3008 type_size(ir
->lhs
->type
) == 1 &&
3009 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3010 /* To avoid emitting an extra MOV when assigning an expression to a
3011 * variable, emit the last instruction of the expression again, but
3012 * replace the destination register with the target of the assignment.
3013 * Dead code elimination will remove the original instruction.
3015 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3016 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3017 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3018 new_inst
->saturate
= inst
->saturate
;
3019 new_inst
->resource
= inst
->resource
;
3020 inst
->dead_mask
= inst
->dst
[0].writemask
;
3022 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3029 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3032 GLdouble stack_vals
[4] = { 0 };
3033 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3034 GLenum gl_type
= GL_NONE
;
3036 static int in_array
= 0;
3037 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3039 /* Unfortunately, 4 floats is all we can get into
3040 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3041 * aggregate constant and move each constant value into it. If we
3042 * get lucky, copy propagation will eliminate the extra moves.
3044 if (ir
->type
->is_record()) {
3045 st_src_reg temp_base
= get_temp(ir
->type
);
3046 st_dst_reg temp
= st_dst_reg(temp_base
);
3048 for (i
= 0; i
< ir
->type
->length
; i
++) {
3049 ir_constant
*const field_value
= ir
->get_record_field(i
);
3050 int size
= type_size(field_value
->type
);
3054 field_value
->accept(this);
3057 for (i
= 0; i
< (unsigned int)size
; i
++) {
3058 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3064 this->result
= temp_base
;
3068 if (ir
->type
->is_array()) {
3069 st_src_reg temp_base
= get_temp(ir
->type
);
3070 st_dst_reg temp
= st_dst_reg(temp_base
);
3071 int size
= type_size(ir
->type
->fields
.array
);
3076 for (i
= 0; i
< ir
->type
->length
; i
++) {
3077 ir
->const_elements
[i
]->accept(this);
3079 for (int j
= 0; j
< size
; j
++) {
3080 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3086 this->result
= temp_base
;
3091 if (ir
->type
->is_matrix()) {
3092 st_src_reg mat
= get_temp(ir
->type
);
3093 st_dst_reg mat_column
= st_dst_reg(mat
);
3095 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3096 switch (ir
->type
->base_type
) {
3097 case GLSL_TYPE_FLOAT
:
3098 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3100 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3101 src
.index
= add_constant(file
,
3103 ir
->type
->vector_elements
,
3106 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3108 case GLSL_TYPE_DOUBLE
:
3109 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3110 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3111 src
.index
= add_constant(file
,
3113 ir
->type
->vector_elements
,
3116 if (ir
->type
->vector_elements
>= 2) {
3117 mat_column
.writemask
= WRITEMASK_XY
;
3118 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3119 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3121 mat_column
.writemask
= WRITEMASK_X
;
3122 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3123 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3126 if (ir
->type
->vector_elements
> 2) {
3127 if (ir
->type
->vector_elements
== 4) {
3128 mat_column
.writemask
= WRITEMASK_ZW
;
3129 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3130 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3132 mat_column
.writemask
= WRITEMASK_Z
;
3133 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3134 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3135 mat_column
.writemask
= WRITEMASK_XYZW
;
3136 src
.swizzle
= SWIZZLE_XYZW
;
3142 unreachable("Illegal matrix constant type.\n");
3151 switch (ir
->type
->base_type
) {
3152 case GLSL_TYPE_FLOAT
:
3154 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3155 values
[i
].f
= ir
->value
.f
[i
];
3158 case GLSL_TYPE_DOUBLE
:
3159 gl_type
= GL_DOUBLE
;
3160 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3161 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3164 case GLSL_TYPE_INT64
:
3165 gl_type
= GL_INT64_ARB
;
3166 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3167 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3170 case GLSL_TYPE_UINT64
:
3171 gl_type
= GL_UNSIGNED_INT64_ARB
;
3172 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3173 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3176 case GLSL_TYPE_UINT
:
3177 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3178 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3179 if (native_integers
)
3180 values
[i
].u
= ir
->value
.u
[i
];
3182 values
[i
].f
= ir
->value
.u
[i
];
3186 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3187 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3188 if (native_integers
)
3189 values
[i
].i
= ir
->value
.i
[i
];
3191 values
[i
].f
= ir
->value
.i
[i
];
3194 case GLSL_TYPE_BOOL
:
3195 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3196 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3197 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3201 assert(!"Non-float/uint/int/bool constant");
3204 this->result
= st_src_reg(file
, -1, ir
->type
);
3205 this->result
.index
= add_constant(file
,
3207 ir
->type
->vector_elements
,
3209 &this->result
.swizzle
);
3213 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3215 exec_node
*param
= ir
->actual_parameters
.get_head();
3216 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3217 ir_variable
*location
= deref
->variable_referenced();
3220 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3222 /* Calculate the surface offset */
3224 unsigned array_size
= 0, base
= 0;
3227 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3229 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3230 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3231 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3232 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3233 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3235 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3238 ir
->return_deref
->accept(this);
3239 st_dst_reg
dst(this->result
);
3240 dst
.writemask
= WRITEMASK_X
;
3242 glsl_to_tgsi_instruction
*inst
;
3244 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3245 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3246 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3247 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3248 st_src_reg_for_int(1));
3249 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3250 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3251 st_src_reg_for_int(-1));
3252 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3254 param
= param
->get_next();
3255 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3258 st_src_reg data
= this->result
, data2
= undef_src
;
3260 switch (ir
->callee
->intrinsic_id
) {
3261 case ir_intrinsic_atomic_counter_add
:
3262 opcode
= TGSI_OPCODE_ATOMUADD
;
3264 case ir_intrinsic_atomic_counter_min
:
3265 opcode
= TGSI_OPCODE_ATOMIMIN
;
3267 case ir_intrinsic_atomic_counter_max
:
3268 opcode
= TGSI_OPCODE_ATOMIMAX
;
3270 case ir_intrinsic_atomic_counter_and
:
3271 opcode
= TGSI_OPCODE_ATOMAND
;
3273 case ir_intrinsic_atomic_counter_or
:
3274 opcode
= TGSI_OPCODE_ATOMOR
;
3276 case ir_intrinsic_atomic_counter_xor
:
3277 opcode
= TGSI_OPCODE_ATOMXOR
;
3279 case ir_intrinsic_atomic_counter_exchange
:
3280 opcode
= TGSI_OPCODE_ATOMXCHG
;
3282 case ir_intrinsic_atomic_counter_comp_swap
: {
3283 opcode
= TGSI_OPCODE_ATOMCAS
;
3284 param
= param
->get_next();
3285 val
= ((ir_instruction
*)param
)->as_rvalue();
3287 data2
= this->result
;
3291 assert(!"Unexpected intrinsic");
3295 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3298 inst
->resource
= buffer
;
3302 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3304 exec_node
*param
= ir
->actual_parameters
.get_head();
3306 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3308 param
= param
->get_next();
3309 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3311 ir_constant
*const_block
= block
->as_constant();
3315 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3316 (const_block
? const_block
->value
.u
[0] : 0),
3320 block
->accept(this);
3321 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3322 *buffer
.reladdr
= this->result
;
3323 emit_arl(ir
, sampler_reladdr
, this->result
);
3326 /* Calculate the surface offset */
3327 offset
->accept(this);
3328 st_src_reg off
= this->result
;
3330 st_dst_reg dst
= undef_dst
;
3331 if (ir
->return_deref
) {
3332 ir
->return_deref
->accept(this);
3333 dst
= st_dst_reg(this->result
);
3334 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3337 glsl_to_tgsi_instruction
*inst
;
3339 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3340 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3341 if (dst
.type
== GLSL_TYPE_BOOL
)
3342 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3343 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3344 param
= param
->get_next();
3345 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3348 param
= param
->get_next();
3349 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3351 dst
.writemask
= write_mask
->value
.u
[0];
3353 dst
.type
= this->result
.type
;
3354 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3356 param
= param
->get_next();
3357 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3360 st_src_reg data
= this->result
, data2
= undef_src
;
3362 switch (ir
->callee
->intrinsic_id
) {
3363 case ir_intrinsic_ssbo_atomic_add
:
3364 opcode
= TGSI_OPCODE_ATOMUADD
;
3366 case ir_intrinsic_ssbo_atomic_min
:
3367 opcode
= TGSI_OPCODE_ATOMIMIN
;
3369 case ir_intrinsic_ssbo_atomic_max
:
3370 opcode
= TGSI_OPCODE_ATOMIMAX
;
3372 case ir_intrinsic_ssbo_atomic_and
:
3373 opcode
= TGSI_OPCODE_ATOMAND
;
3375 case ir_intrinsic_ssbo_atomic_or
:
3376 opcode
= TGSI_OPCODE_ATOMOR
;
3378 case ir_intrinsic_ssbo_atomic_xor
:
3379 opcode
= TGSI_OPCODE_ATOMXOR
;
3381 case ir_intrinsic_ssbo_atomic_exchange
:
3382 opcode
= TGSI_OPCODE_ATOMXCHG
;
3384 case ir_intrinsic_ssbo_atomic_comp_swap
:
3385 opcode
= TGSI_OPCODE_ATOMCAS
;
3386 param
= param
->get_next();
3387 val
= ((ir_instruction
*)param
)->as_rvalue();
3389 data2
= this->result
;
3392 assert(!"Unexpected intrinsic");
3396 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3399 param
= param
->get_next();
3400 ir_constant
*access
= NULL
;
3401 if (!param
->is_tail_sentinel()) {
3402 access
= ((ir_instruction
*)param
)->as_constant();
3406 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3410 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3412 switch (ir
->callee
->intrinsic_id
) {
3413 case ir_intrinsic_memory_barrier
:
3414 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3415 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3416 TGSI_MEMBAR_ATOMIC_BUFFER
|
3417 TGSI_MEMBAR_SHADER_IMAGE
|
3418 TGSI_MEMBAR_SHARED
));
3420 case ir_intrinsic_memory_barrier_atomic_counter
:
3421 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3422 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3424 case ir_intrinsic_memory_barrier_buffer
:
3425 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3426 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3428 case ir_intrinsic_memory_barrier_image
:
3429 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3430 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3432 case ir_intrinsic_memory_barrier_shared
:
3433 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3434 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3436 case ir_intrinsic_group_memory_barrier
:
3437 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3438 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3439 TGSI_MEMBAR_ATOMIC_BUFFER
|
3440 TGSI_MEMBAR_SHADER_IMAGE
|
3441 TGSI_MEMBAR_SHARED
|
3442 TGSI_MEMBAR_THREAD_GROUP
));
3445 assert(!"Unexpected memory barrier intrinsic");
3450 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3452 exec_node
*param
= ir
->actual_parameters
.get_head();
3454 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3456 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3458 /* Calculate the surface offset */
3459 offset
->accept(this);
3460 st_src_reg off
= this->result
;
3462 st_dst_reg dst
= undef_dst
;
3463 if (ir
->return_deref
) {
3464 ir
->return_deref
->accept(this);
3465 dst
= st_dst_reg(this->result
);
3466 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3469 glsl_to_tgsi_instruction
*inst
;
3471 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3472 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3473 inst
->resource
= buffer
;
3474 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3475 param
= param
->get_next();
3476 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3479 param
= param
->get_next();
3480 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3482 dst
.writemask
= write_mask
->value
.u
[0];
3484 dst
.type
= this->result
.type
;
3485 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3486 inst
->resource
= buffer
;
3488 param
= param
->get_next();
3489 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3492 st_src_reg data
= this->result
, data2
= undef_src
;
3494 switch (ir
->callee
->intrinsic_id
) {
3495 case ir_intrinsic_shared_atomic_add
:
3496 opcode
= TGSI_OPCODE_ATOMUADD
;
3498 case ir_intrinsic_shared_atomic_min
:
3499 opcode
= TGSI_OPCODE_ATOMIMIN
;
3501 case ir_intrinsic_shared_atomic_max
:
3502 opcode
= TGSI_OPCODE_ATOMIMAX
;
3504 case ir_intrinsic_shared_atomic_and
:
3505 opcode
= TGSI_OPCODE_ATOMAND
;
3507 case ir_intrinsic_shared_atomic_or
:
3508 opcode
= TGSI_OPCODE_ATOMOR
;
3510 case ir_intrinsic_shared_atomic_xor
:
3511 opcode
= TGSI_OPCODE_ATOMXOR
;
3513 case ir_intrinsic_shared_atomic_exchange
:
3514 opcode
= TGSI_OPCODE_ATOMXCHG
;
3516 case ir_intrinsic_shared_atomic_comp_swap
:
3517 opcode
= TGSI_OPCODE_ATOMCAS
;
3518 param
= param
->get_next();
3519 val
= ((ir_instruction
*)param
)->as_rvalue();
3521 data2
= this->result
;
3524 assert(!"Unexpected intrinsic");
3528 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3529 inst
->resource
= buffer
;
3534 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3535 bool *memory_coherent
, bool *memory_volatile
,
3536 bool *memory_restrict
, unsigned *image_format
)
3539 switch (ir
->ir_type
) {
3540 case ir_type_dereference_record
: {
3541 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3542 const glsl_type
*struct_type
= deref_record
->record
->type
;
3543 int fild_idx
= deref_record
->field_idx
;
3545 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3547 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3549 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3551 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3553 struct_type
->fields
.structure
[fild_idx
].image_format
;
3557 case ir_type_dereference_array
: {
3558 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3559 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3560 memory_coherent
, memory_volatile
, memory_restrict
,
3565 case ir_type_dereference_variable
: {
3566 ir_variable
*var
= ir
->variable_referenced();
3568 *type
= var
->type
->without_array();
3569 *memory_coherent
= var
->data
.memory_coherent
;
3570 *memory_volatile
= var
->data
.memory_volatile
;
3571 *memory_restrict
= var
->data
.memory_restrict
;
3572 *image_format
= var
->data
.image_format
;
3582 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3584 exec_node
*param
= ir
->actual_parameters
.get_head();
3586 ir_dereference
*img
= (ir_dereference
*)param
;
3587 const ir_variable
*imgvar
= img
->variable_referenced();
3588 unsigned sampler_array_size
= 1, sampler_base
= 0;
3589 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3590 unsigned image_format
= 0;
3591 const glsl_type
*type
= NULL
;
3593 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3594 &memory_restrict
, &image_format
);
3597 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3599 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3600 &index
, &reladdr
, !imgvar
->contains_bindless());
3602 image
.index
= index
;
3603 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3604 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3605 *image
.reladdr
= reladdr
;
3606 emit_arl(ir
, sampler_reladdr
, reladdr
);
3609 st_dst_reg dst
= undef_dst
;
3610 if (ir
->return_deref
) {
3611 ir
->return_deref
->accept(this);
3612 dst
= st_dst_reg(this->result
);
3613 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3616 glsl_to_tgsi_instruction
*inst
;
3618 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3619 dst
.writemask
= WRITEMASK_XYZ
;
3620 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3621 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3622 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3623 st_dst_reg dstres
= st_dst_reg(res
);
3624 dstres
.writemask
= WRITEMASK_W
;
3625 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3626 res
.swizzle
= SWIZZLE_WWWW
;
3627 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3629 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3631 st_dst_reg coord_dst
;
3632 coord
= get_temp(glsl_type::ivec4_type
);
3633 coord_dst
= st_dst_reg(coord
);
3634 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3635 param
= param
->get_next();
3636 ((ir_dereference
*)param
)->accept(this);
3637 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3638 coord
.swizzle
= SWIZZLE_XXXX
;
3639 switch (type
->coordinate_components()) {
3640 case 4: assert(!"unexpected coord count");
3642 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3644 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3647 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3648 param
= param
->get_next();
3649 ((ir_dereference
*)param
)->accept(this);
3650 st_src_reg sample
= this->result
;
3651 sample
.swizzle
= SWIZZLE_XXXX
;
3652 coord_dst
.writemask
= WRITEMASK_W
;
3653 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3654 coord
.swizzle
|= SWIZZLE_W
<< 9;
3657 param
= param
->get_next();
3658 if (!param
->is_tail_sentinel()) {
3659 ((ir_dereference
*)param
)->accept(this);
3660 arg1
= this->result
;
3661 param
= param
->get_next();
3664 if (!param
->is_tail_sentinel()) {
3665 ((ir_dereference
*)param
)->accept(this);
3666 arg2
= this->result
;
3667 param
= param
->get_next();
3670 assert(param
->is_tail_sentinel());
3673 switch (ir
->callee
->intrinsic_id
) {
3674 case ir_intrinsic_image_load
:
3675 opcode
= TGSI_OPCODE_LOAD
;
3677 case ir_intrinsic_image_store
:
3678 opcode
= TGSI_OPCODE_STORE
;
3680 case ir_intrinsic_image_atomic_add
:
3681 opcode
= TGSI_OPCODE_ATOMUADD
;
3683 case ir_intrinsic_image_atomic_min
:
3684 opcode
= TGSI_OPCODE_ATOMIMIN
;
3686 case ir_intrinsic_image_atomic_max
:
3687 opcode
= TGSI_OPCODE_ATOMIMAX
;
3689 case ir_intrinsic_image_atomic_and
:
3690 opcode
= TGSI_OPCODE_ATOMAND
;
3692 case ir_intrinsic_image_atomic_or
:
3693 opcode
= TGSI_OPCODE_ATOMOR
;
3695 case ir_intrinsic_image_atomic_xor
:
3696 opcode
= TGSI_OPCODE_ATOMXOR
;
3698 case ir_intrinsic_image_atomic_exchange
:
3699 opcode
= TGSI_OPCODE_ATOMXCHG
;
3701 case ir_intrinsic_image_atomic_comp_swap
:
3702 opcode
= TGSI_OPCODE_ATOMCAS
;
3705 assert(!"Unexpected intrinsic");
3709 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3710 if (opcode
== TGSI_OPCODE_STORE
)
3711 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3714 if (imgvar
->contains_bindless()) {
3716 inst
->resource
= this->result
;
3717 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3718 SWIZZLE_X
, SWIZZLE_Y
);
3720 inst
->resource
= image
;
3721 inst
->sampler_array_size
= sampler_array_size
;
3722 inst
->sampler_base
= sampler_base
;
3725 inst
->tex_target
= type
->sampler_index();
3726 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3727 _mesa_get_shader_image_format(image_format
));
3729 if (memory_coherent
)
3730 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3731 if (memory_restrict
)
3732 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3733 if (memory_volatile
)
3734 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3738 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3740 ir
->return_deref
->accept(this);
3741 st_dst_reg dst
= st_dst_reg(this->result
);
3743 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3745 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3746 unsigned num_src
= 0;
3747 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3748 assert(num_src
< ARRAY_SIZE(src
));
3750 this->result
.file
= PROGRAM_UNDEFINED
;
3751 param
->accept(this);
3752 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3754 src
[num_src
] = this->result
;
3758 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3762 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3764 ir_function_signature
*sig
= ir
->callee
;
3766 /* Filter out intrinsics */
3767 switch (sig
->intrinsic_id
) {
3768 case ir_intrinsic_atomic_counter_read
:
3769 case ir_intrinsic_atomic_counter_increment
:
3770 case ir_intrinsic_atomic_counter_predecrement
:
3771 case ir_intrinsic_atomic_counter_add
:
3772 case ir_intrinsic_atomic_counter_min
:
3773 case ir_intrinsic_atomic_counter_max
:
3774 case ir_intrinsic_atomic_counter_and
:
3775 case ir_intrinsic_atomic_counter_or
:
3776 case ir_intrinsic_atomic_counter_xor
:
3777 case ir_intrinsic_atomic_counter_exchange
:
3778 case ir_intrinsic_atomic_counter_comp_swap
:
3779 visit_atomic_counter_intrinsic(ir
);
3782 case ir_intrinsic_ssbo_load
:
3783 case ir_intrinsic_ssbo_store
:
3784 case ir_intrinsic_ssbo_atomic_add
:
3785 case ir_intrinsic_ssbo_atomic_min
:
3786 case ir_intrinsic_ssbo_atomic_max
:
3787 case ir_intrinsic_ssbo_atomic_and
:
3788 case ir_intrinsic_ssbo_atomic_or
:
3789 case ir_intrinsic_ssbo_atomic_xor
:
3790 case ir_intrinsic_ssbo_atomic_exchange
:
3791 case ir_intrinsic_ssbo_atomic_comp_swap
:
3792 visit_ssbo_intrinsic(ir
);
3795 case ir_intrinsic_memory_barrier
:
3796 case ir_intrinsic_memory_barrier_atomic_counter
:
3797 case ir_intrinsic_memory_barrier_buffer
:
3798 case ir_intrinsic_memory_barrier_image
:
3799 case ir_intrinsic_memory_barrier_shared
:
3800 case ir_intrinsic_group_memory_barrier
:
3801 visit_membar_intrinsic(ir
);
3804 case ir_intrinsic_shared_load
:
3805 case ir_intrinsic_shared_store
:
3806 case ir_intrinsic_shared_atomic_add
:
3807 case ir_intrinsic_shared_atomic_min
:
3808 case ir_intrinsic_shared_atomic_max
:
3809 case ir_intrinsic_shared_atomic_and
:
3810 case ir_intrinsic_shared_atomic_or
:
3811 case ir_intrinsic_shared_atomic_xor
:
3812 case ir_intrinsic_shared_atomic_exchange
:
3813 case ir_intrinsic_shared_atomic_comp_swap
:
3814 visit_shared_intrinsic(ir
);
3817 case ir_intrinsic_image_load
:
3818 case ir_intrinsic_image_store
:
3819 case ir_intrinsic_image_atomic_add
:
3820 case ir_intrinsic_image_atomic_min
:
3821 case ir_intrinsic_image_atomic_max
:
3822 case ir_intrinsic_image_atomic_and
:
3823 case ir_intrinsic_image_atomic_or
:
3824 case ir_intrinsic_image_atomic_xor
:
3825 case ir_intrinsic_image_atomic_exchange
:
3826 case ir_intrinsic_image_atomic_comp_swap
:
3827 case ir_intrinsic_image_size
:
3828 case ir_intrinsic_image_samples
:
3829 visit_image_intrinsic(ir
);
3832 case ir_intrinsic_shader_clock
:
3833 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3836 case ir_intrinsic_vote_all
:
3837 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3839 case ir_intrinsic_vote_any
:
3840 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3842 case ir_intrinsic_vote_eq
:
3843 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3845 case ir_intrinsic_ballot
:
3846 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3848 case ir_intrinsic_read_first_invocation
:
3849 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
3851 case ir_intrinsic_read_invocation
:
3852 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
3855 case ir_intrinsic_invalid
:
3856 case ir_intrinsic_generic_load
:
3857 case ir_intrinsic_generic_store
:
3858 case ir_intrinsic_generic_atomic_add
:
3859 case ir_intrinsic_generic_atomic_and
:
3860 case ir_intrinsic_generic_atomic_or
:
3861 case ir_intrinsic_generic_atomic_xor
:
3862 case ir_intrinsic_generic_atomic_min
:
3863 case ir_intrinsic_generic_atomic_max
:
3864 case ir_intrinsic_generic_atomic_exchange
:
3865 case ir_intrinsic_generic_atomic_comp_swap
:
3866 unreachable("Invalid intrinsic");
3871 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3872 unsigned *array_elements
,
3874 st_src_reg
*indirect
,
3877 switch (tail
->ir_type
) {
3878 case ir_type_dereference_record
: {
3879 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3880 const glsl_type
*struct_type
= deref_record
->record
->type
;
3881 int field_index
= deref_record
->field_idx
;
3883 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3885 assert(field_index
>= 0);
3886 *location
+= struct_type
->record_location_offset(field_index
);
3890 case ir_type_dereference_array
: {
3891 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3893 void *mem_ctx
= ralloc_parent(deref_arr
);
3894 ir_constant
*array_index
=
3895 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
3898 st_src_reg temp_reg
;
3899 st_dst_reg temp_dst
;
3901 temp_reg
= get_temp(glsl_type::uint_type
);
3902 temp_dst
= st_dst_reg(temp_reg
);
3903 temp_dst
.writemask
= 1;
3905 deref_arr
->array_index
->accept(this);
3906 if (*array_elements
!= 1)
3907 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3909 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3911 if (indirect
->file
== PROGRAM_UNDEFINED
)
3912 *indirect
= temp_reg
;
3914 temp_dst
= st_dst_reg(*indirect
);
3915 temp_dst
.writemask
= 1;
3916 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3919 *index
+= array_index
->value
.u
[0] * *array_elements
;
3921 *array_elements
*= deref_arr
->array
->type
->length
;
3923 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3932 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3933 unsigned *array_size
,
3936 st_src_reg
*reladdr
,
3939 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3940 unsigned location
= 0;
3941 ir_variable
*var
= ir
->variable_referenced();
3943 memset(reladdr
, 0, sizeof(*reladdr
));
3944 reladdr
->file
= PROGRAM_UNDEFINED
;
3950 location
= var
->data
.location
;
3951 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3954 * If we end up with no indirect then adjust the base to the index,
3955 * and set the array size to 1.
3957 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3963 assert(location
!= 0xffffffff);
3964 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3965 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3970 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3972 if (offset
.reladdr
|| offset
.reladdr2
) {
3973 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3974 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3975 tmp_dst
.writemask
= WRITEMASK_XY
;
3976 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
3984 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3986 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3987 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3988 st_src_reg levels_src
, reladdr
;
3989 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3990 glsl_to_tgsi_instruction
*inst
= NULL
;
3991 unsigned opcode
= TGSI_OPCODE_NOP
;
3992 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3993 unsigned sampler_array_size
= 1, sampler_base
= 0;
3994 bool is_cube_array
= false, is_cube_shadow
= false;
3995 ir_variable
*var
= ir
->sampler
->variable_referenced();
3998 /* if we are a cube array sampler or a cube shadow */
3999 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4000 is_cube_array
= sampler_type
->sampler_array
;
4001 is_cube_shadow
= sampler_type
->sampler_shadow
;
4004 if (ir
->coordinate
) {
4005 ir
->coordinate
->accept(this);
4007 /* Put our coords in a temp. We'll need to modify them for shadow,
4008 * projection, or LOD, so the only case we'd use it as-is is if
4009 * we're doing plain old texturing. The optimization passes on
4010 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4012 coord
= get_temp(glsl_type::vec4_type
);
4013 coord_dst
= st_dst_reg(coord
);
4014 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4015 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4018 if (ir
->projector
) {
4019 ir
->projector
->accept(this);
4020 projector
= this->result
;
4023 /* Storage for our result. Ideally for an assignment we'd be using
4024 * the actual storage for the result here, instead.
4026 result_src
= get_temp(ir
->type
);
4027 result_dst
= st_dst_reg(result_src
);
4028 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4032 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4034 ir
->offset
->accept(this);
4035 offset
[0] = this->result
;
4039 if (is_cube_array
|| is_cube_shadow
) {
4040 opcode
= TGSI_OPCODE_TXB2
;
4043 opcode
= TGSI_OPCODE_TXB
;
4045 ir
->lod_info
.bias
->accept(this);
4046 lod_info
= this->result
;
4048 ir
->offset
->accept(this);
4049 offset
[0] = this->result
;
4053 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4054 opcode
= TGSI_OPCODE_TEX_LZ
;
4056 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4057 ir
->lod_info
.lod
->accept(this);
4058 lod_info
= this->result
;
4061 ir
->offset
->accept(this);
4062 offset
[0] = this->result
;
4066 opcode
= TGSI_OPCODE_TXD
;
4067 ir
->lod_info
.grad
.dPdx
->accept(this);
4069 ir
->lod_info
.grad
.dPdy
->accept(this);
4072 ir
->offset
->accept(this);
4073 offset
[0] = this->result
;
4077 opcode
= TGSI_OPCODE_TXQ
;
4078 ir
->lod_info
.lod
->accept(this);
4079 lod_info
= this->result
;
4081 case ir_query_levels
:
4082 opcode
= TGSI_OPCODE_TXQ
;
4083 lod_info
= undef_src
;
4084 levels_src
= get_temp(ir
->type
);
4087 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4088 opcode
= TGSI_OPCODE_TXF_LZ
;
4090 opcode
= TGSI_OPCODE_TXF
;
4091 ir
->lod_info
.lod
->accept(this);
4092 lod_info
= this->result
;
4095 ir
->offset
->accept(this);
4096 offset
[0] = this->result
;
4100 opcode
= TGSI_OPCODE_TXF
;
4101 ir
->lod_info
.sample_index
->accept(this);
4102 sample_index
= this->result
;
4105 opcode
= TGSI_OPCODE_TG4
;
4106 ir
->lod_info
.component
->accept(this);
4107 component
= this->result
;
4109 ir
->offset
->accept(this);
4110 if (ir
->offset
->type
->is_array()) {
4111 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4112 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4113 offset
[i
] = this->result
;
4114 offset
[i
].index
+= i
* type_size(elt_type
);
4115 offset
[i
].type
= elt_type
->base_type
;
4116 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4117 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4120 offset
[0] = canonicalize_gather_offset(this->result
);
4125 opcode
= TGSI_OPCODE_LODQ
;
4127 case ir_texture_samples
:
4128 opcode
= TGSI_OPCODE_TXQS
;
4130 case ir_samples_identical
:
4131 unreachable("Unexpected ir_samples_identical opcode");
4134 if (ir
->projector
) {
4135 if (opcode
== TGSI_OPCODE_TEX
) {
4136 /* Slot the projector in as the last component of the coord. */
4137 coord_dst
.writemask
= WRITEMASK_W
;
4138 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4139 coord_dst
.writemask
= WRITEMASK_XYZW
;
4140 opcode
= TGSI_OPCODE_TXP
;
4142 st_src_reg coord_w
= coord
;
4143 coord_w
.swizzle
= SWIZZLE_WWWW
;
4145 /* For the other TEX opcodes there's no projective version
4146 * since the last slot is taken up by LOD info. Do the
4147 * projective divide now.
4149 coord_dst
.writemask
= WRITEMASK_W
;
4150 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4152 /* In the case where we have to project the coordinates "by hand,"
4153 * the shadow comparator value must also be projected.
4155 st_src_reg tmp_src
= coord
;
4156 if (ir
->shadow_comparator
) {
4157 /* Slot the shadow value in as the second to last component of the
4160 ir
->shadow_comparator
->accept(this);
4162 tmp_src
= get_temp(glsl_type::vec4_type
);
4163 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4165 /* Projective division not allowed for array samplers. */
4166 assert(!sampler_type
->sampler_array
);
4168 tmp_dst
.writemask
= WRITEMASK_Z
;
4169 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4171 tmp_dst
.writemask
= WRITEMASK_XY
;
4172 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4175 coord_dst
.writemask
= WRITEMASK_XYZ
;
4176 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4178 coord_dst
.writemask
= WRITEMASK_XYZW
;
4179 coord
.swizzle
= SWIZZLE_XYZW
;
4183 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4184 * comparator was put in the correct place (and projected) by the code,
4185 * above, that handles by-hand projection.
4187 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4188 /* Slot the shadow value in as the second to last component of the
4191 ir
->shadow_comparator
->accept(this);
4193 if (is_cube_array
) {
4194 cube_sc
= get_temp(glsl_type::float_type
);
4195 cube_sc_dst
= st_dst_reg(cube_sc
);
4196 cube_sc_dst
.writemask
= WRITEMASK_X
;
4197 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4198 cube_sc_dst
.writemask
= WRITEMASK_X
;
4201 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4202 sampler_type
->sampler_array
) ||
4203 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4204 coord_dst
.writemask
= WRITEMASK_W
;
4206 coord_dst
.writemask
= WRITEMASK_Z
;
4208 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4209 coord_dst
.writemask
= WRITEMASK_XYZW
;
4213 if (ir
->op
== ir_txf_ms
) {
4214 coord_dst
.writemask
= WRITEMASK_W
;
4215 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4216 coord_dst
.writemask
= WRITEMASK_XYZW
;
4217 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4218 opcode
== TGSI_OPCODE_TXF
) {
4219 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4220 coord_dst
.writemask
= WRITEMASK_W
;
4221 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4222 coord_dst
.writemask
= WRITEMASK_XYZW
;
4225 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4228 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4229 &index
, &reladdr
, !var
->contains_bindless());
4231 sampler
.index
= index
;
4232 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4233 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4234 *sampler
.reladdr
= reladdr
;
4235 emit_arl(ir
, sampler_reladdr
, reladdr
);
4238 if (opcode
== TGSI_OPCODE_TXD
)
4239 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4240 else if (opcode
== TGSI_OPCODE_TXQ
) {
4241 if (ir
->op
== ir_query_levels
) {
4242 /* the level is stored in W */
4243 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4244 result_dst
.writemask
= WRITEMASK_X
;
4245 levels_src
.swizzle
= SWIZZLE_WWWW
;
4246 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4248 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4249 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4250 inst
= emit_asm(ir
, opcode
, result_dst
);
4251 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4252 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4253 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4254 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4255 } else if (opcode
== TGSI_OPCODE_TG4
) {
4256 if (is_cube_array
&& ir
->shadow_comparator
) {
4257 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4259 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4262 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4264 if (ir
->shadow_comparator
)
4265 inst
->tex_shadow
= GL_TRUE
;
4267 if (var
->contains_bindless()) {
4268 ir
->sampler
->accept(this);
4269 inst
->resource
= this->result
;
4270 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4271 SWIZZLE_X
, SWIZZLE_Y
);
4273 inst
->resource
= sampler
;
4274 inst
->sampler_array_size
= sampler_array_size
;
4275 inst
->sampler_base
= sampler_base
;
4279 if (!inst
->tex_offsets
)
4280 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4282 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4283 inst
->tex_offsets
[i
] = offset
[i
];
4284 inst
->tex_offset_num_offset
= i
;
4287 inst
->tex_target
= sampler_type
->sampler_index();
4288 inst
->tex_type
= ir
->type
->base_type
;
4290 this->result
= result_src
;
4294 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4296 assert(!ir
->get_value());
4298 emit_asm(ir
, TGSI_OPCODE_RET
);
4302 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4304 if (ir
->condition
) {
4305 ir
->condition
->accept(this);
4306 st_src_reg condition
= this->result
;
4308 /* Convert the bool condition to a float so we can negate. */
4309 if (native_integers
) {
4310 st_src_reg temp
= get_temp(ir
->condition
->type
);
4311 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4312 condition
, st_src_reg_for_float(1.0));
4316 condition
.negate
= ~condition
.negate
;
4317 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4319 /* unconditional kil */
4320 emit_asm(ir
, TGSI_OPCODE_KILL
);
4325 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4328 glsl_to_tgsi_instruction
*if_inst
;
4330 ir
->condition
->accept(this);
4331 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4333 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4335 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4337 this->instructions
.push_tail(if_inst
);
4339 visit_exec_list(&ir
->then_instructions
, this);
4341 if (!ir
->else_instructions
.is_empty()) {
4342 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4343 visit_exec_list(&ir
->else_instructions
, this);
4346 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4351 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4353 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4355 ir
->stream
->accept(this);
4356 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4360 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4362 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4364 ir
->stream
->accept(this);
4365 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4369 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4371 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4372 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4374 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4377 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4379 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4381 result
.file
= PROGRAM_UNDEFINED
;
4388 num_input_arrays
= 0;
4389 num_output_arrays
= 0;
4391 num_address_regs
= 0;
4394 indirect_addr_consts
= false;
4395 wpos_transform_const
= -1;
4397 native_integers
= false;
4398 mem_ctx
= ralloc_context(NULL
);
4402 shader_program
= NULL
;
4407 use_shared_memory
= false;
4408 has_tex_txf_lz
= false;
4412 static void var_destroy(struct hash_entry
*entry
)
4414 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4419 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4421 _mesa_hash_table_destroy(variables
, var_destroy
);
4423 ralloc_free(mem_ctx
);
4426 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4433 * Count resources used by the given gpu program (number of texture
4437 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4439 v
->samplers_used
= 0;
4442 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4443 if (inst
->info
->is_tex
) {
4444 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4445 unsigned idx
= inst
->sampler_base
+ i
;
4446 v
->samplers_used
|= 1u << idx
;
4448 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4449 v
->sampler_types
[idx
] = inst
->tex_type
;
4450 v
->sampler_targets
[idx
] =
4451 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4453 if (inst
->tex_shadow
) {
4454 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4459 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4460 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4462 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4463 is_resource_instruction(inst
->op
) ||
4464 inst
->op
== TGSI_OPCODE_STORE
)) {
4465 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4466 v
->use_shared_memory
= true;
4467 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4468 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4469 unsigned idx
= inst
->sampler_base
+ i
;
4470 v
->images_used
|= 1 << idx
;
4471 v
->image_targets
[idx
] =
4472 st_translate_texture_target(inst
->tex_target
, false);
4473 v
->image_formats
[idx
] = inst
->image_format
;
4478 prog
->SamplersUsed
= v
->samplers_used
;
4480 if (v
->shader_program
!= NULL
)
4481 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4485 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4486 * are read from the given src in this instruction
4489 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4491 int read_mask
= 0, comp
;
4493 /* Now, given the src swizzle and the written channels, find which
4494 * components are actually read
4496 for (comp
= 0; comp
< 4; ++comp
) {
4497 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4499 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4500 read_mask
|= 1 << coord
;
4507 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4508 * instruction is the first instruction to write to register T0. There are
4509 * several lowering passes done in GLSL IR (e.g. branches and
4510 * relative addressing) that create a large number of conditional assignments
4511 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4513 * Here is why this conversion is safe:
4514 * CMP T0, T1 T2 T0 can be expanded to:
4520 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4521 * as the original program. If (T1 < 0.0) evaluates to false, executing
4522 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4523 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4524 * because any instruction that was going to read from T0 after this was going
4525 * to read a garbage value anyway.
4528 glsl_to_tgsi_visitor::simplify_cmp(void)
4530 int tempWritesSize
= 0;
4531 unsigned *tempWrites
= NULL
;
4532 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4534 memset(outputWrites
, 0, sizeof(outputWrites
));
4536 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4537 unsigned prevWriteMask
= 0;
4539 /* Give up if we encounter relative addressing or flow control. */
4540 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4541 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4542 inst
->info
->is_branch
||
4543 inst
->op
== TGSI_OPCODE_CONT
||
4544 inst
->op
== TGSI_OPCODE_END
||
4545 inst
->op
== TGSI_OPCODE_RET
) {
4549 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4550 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4551 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4552 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4553 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4554 if (inst
->dst
[0].index
>= tempWritesSize
) {
4555 const int inc
= 4096;
4557 tempWrites
= (unsigned*)
4559 (tempWritesSize
+ inc
) * sizeof(unsigned));
4563 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4564 tempWritesSize
+= inc
;
4567 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4568 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4572 /* For a CMP to be considered a conditional write, the destination
4573 * register and source register two must be the same. */
4574 if (inst
->op
== TGSI_OPCODE_CMP
4575 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4576 && inst
->src
[2].file
== inst
->dst
[0].file
4577 && inst
->src
[2].index
== inst
->dst
[0].index
4578 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4580 inst
->op
= TGSI_OPCODE_MOV
;
4581 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4582 inst
->src
[0] = inst
->src
[1];
4589 /* Replaces all references to a temporary register index with another index. */
4591 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4593 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4595 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4596 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4597 int old_idx
= inst
->src
[j
].index
;
4598 if (renames
[old_idx
].valid
)
4599 inst
->src
[j
].index
= renames
[old_idx
].new_reg
;
4603 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4604 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4605 int old_idx
= inst
->tex_offsets
[j
].index
;
4606 if (renames
[old_idx
].valid
)
4607 inst
->tex_offsets
[j
].index
= renames
[old_idx
].new_reg
;
4611 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
4612 int old_idx
= inst
->resource
.index
;
4613 if (renames
[old_idx
].valid
)
4614 inst
->resource
.index
= renames
[old_idx
].new_reg
;
4617 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4618 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4619 int old_idx
= inst
->dst
[j
].index
;
4620 if (renames
[old_idx
].valid
)
4621 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;}
4627 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4629 int depth
= 0; /* loop depth */
4630 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4633 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4634 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4635 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4636 if (first_writes
[inst
->dst
[j
].index
] == -1)
4637 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4641 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4644 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4654 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4656 int depth
= 0; /* loop depth */
4657 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4660 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4661 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4662 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4663 if (first_reads
[inst
->src
[j
].index
] == -1)
4664 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4667 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4668 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4669 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4670 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4673 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4676 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4686 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4688 int depth
= 0; /* loop depth */
4689 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4692 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4693 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4694 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4695 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4697 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4698 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4699 if (first_writes
[inst
->dst
[j
].index
] == -1)
4700 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4701 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4704 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4705 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4706 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4708 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4711 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4714 for (k
= 0; k
< this->next_temp
; k
++) {
4715 if (last_reads
[k
] == -2) {
4727 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4729 int depth
= 0; /* loop depth */
4733 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4734 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4735 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4736 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4739 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4741 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4743 for (k
= 0; k
< this->next_temp
; k
++) {
4744 if (last_writes
[k
] == -2) {
4755 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4756 * channels for copy propagation and updates following instructions to
4757 * use the original versions.
4759 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4760 * will occur. As an example, a TXP production before this pass:
4762 * 0: MOV TEMP[1], INPUT[4].xyyy;
4763 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4764 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4768 * 0: MOV TEMP[1], INPUT[4].xyyy;
4769 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4770 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4772 * which allows for dead code elimination on TEMP[1]'s writes.
4775 glsl_to_tgsi_visitor::copy_propagate(void)
4777 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4778 glsl_to_tgsi_instruction
*,
4779 this->next_temp
* 4);
4780 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4783 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4784 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4785 || inst
->dst
[0].index
< this->next_temp
);
4787 /* First, do any copy propagation possible into the src regs. */
4788 for (int r
= 0; r
< 3; r
++) {
4789 glsl_to_tgsi_instruction
*first
= NULL
;
4791 int acp_base
= inst
->src
[r
].index
* 4;
4793 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4794 inst
->src
[r
].reladdr
||
4795 inst
->src
[r
].reladdr2
)
4798 /* See if we can find entries in the ACP consisting of MOVs
4799 * from the same src register for all the swizzled channels
4800 * of this src register reference.
4802 for (int i
= 0; i
< 4; i
++) {
4803 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4804 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4811 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4816 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4817 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4818 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4819 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4827 /* We've now validated that we can copy-propagate to
4828 * replace this src register reference. Do it.
4830 inst
->src
[r
].file
= first
->src
[0].file
;
4831 inst
->src
[r
].index
= first
->src
[0].index
;
4832 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4833 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4834 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4835 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4838 for (int i
= 0; i
< 4; i
++) {
4839 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4840 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4841 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4843 inst
->src
[r
].swizzle
= swizzle
;
4848 case TGSI_OPCODE_BGNLOOP
:
4849 case TGSI_OPCODE_ENDLOOP
:
4850 /* End of a basic block, clear the ACP entirely. */
4851 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4854 case TGSI_OPCODE_IF
:
4855 case TGSI_OPCODE_UIF
:
4859 case TGSI_OPCODE_ENDIF
:
4860 case TGSI_OPCODE_ELSE
:
4861 /* Clear all channels written inside the block from the ACP, but
4862 * leaving those that were not touched.
4864 for (int r
= 0; r
< this->next_temp
; r
++) {
4865 for (int c
= 0; c
< 4; c
++) {
4866 if (!acp
[4 * r
+ c
])
4869 if (acp_level
[4 * r
+ c
] >= level
)
4870 acp
[4 * r
+ c
] = NULL
;
4873 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4878 /* Continuing the block, clear any written channels from
4881 for (int d
= 0; d
< 2; d
++) {
4882 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4883 /* Any temporary might be written, so no copy propagation
4884 * across this instruction.
4886 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4887 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4888 inst
->dst
[d
].reladdr
) {
4889 /* Any output might be written, so no copy propagation
4890 * from outputs across this instruction.
4892 for (int r
= 0; r
< this->next_temp
; r
++) {
4893 for (int c
= 0; c
< 4; c
++) {
4894 if (!acp
[4 * r
+ c
])
4897 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4898 acp
[4 * r
+ c
] = NULL
;
4901 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4902 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4903 /* Clear where it's used as dst. */
4904 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4905 for (int c
= 0; c
< 4; c
++) {
4906 if (inst
->dst
[d
].writemask
& (1 << c
))
4907 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4911 /* Clear where it's used as src. */
4912 for (int r
= 0; r
< this->next_temp
; r
++) {
4913 for (int c
= 0; c
< 4; c
++) {
4914 if (!acp
[4 * r
+ c
])
4917 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4919 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4920 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4921 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4922 acp
[4 * r
+ c
] = NULL
;
4931 /* If this is a copy, add it to the ACP. */
4932 if (inst
->op
== TGSI_OPCODE_MOV
&&
4933 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4934 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4935 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4936 !inst
->dst
[0].reladdr
&&
4937 !inst
->dst
[0].reladdr2
&&
4939 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4940 !inst
->src
[0].reladdr
&&
4941 !inst
->src
[0].reladdr2
&&
4942 !inst
->src
[0].negate
&&
4943 !inst
->src
[0].abs
) {
4944 for (int i
= 0; i
< 4; i
++) {
4945 if (inst
->dst
[0].writemask
& (1 << i
)) {
4946 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4947 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4953 ralloc_free(acp_level
);
4958 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4961 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4962 * will occur. As an example, a TXP production after copy propagation but
4965 * 0: MOV TEMP[1], INPUT[4].xyyy;
4966 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4967 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4969 * and after this pass:
4971 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4974 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4976 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4977 glsl_to_tgsi_instruction
*,
4978 this->next_temp
* 4);
4979 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4983 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4984 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4985 || inst
->dst
[0].index
< this->next_temp
);
4988 case TGSI_OPCODE_BGNLOOP
:
4989 case TGSI_OPCODE_ENDLOOP
:
4990 case TGSI_OPCODE_CONT
:
4991 case TGSI_OPCODE_BRK
:
4992 /* End of a basic block, clear the write array entirely.
4994 * This keeps us from killing dead code when the writes are
4995 * on either side of a loop, even when the register isn't touched
4996 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4997 * dead code of this type, so it shouldn't make a difference as long as
4998 * the dead code elimination pass in the GLSL compiler does its job.
5000 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5003 case TGSI_OPCODE_ENDIF
:
5004 case TGSI_OPCODE_ELSE
:
5005 /* Promote the recorded level of all channels written inside the
5006 * preceding if or else block to the level above the if/else block.
5008 for (int r
= 0; r
< this->next_temp
; r
++) {
5009 for (int c
= 0; c
< 4; c
++) {
5010 if (!writes
[4 * r
+ c
])
5013 if (write_level
[4 * r
+ c
] == level
)
5014 write_level
[4 * r
+ c
] = level
-1;
5017 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5021 case TGSI_OPCODE_IF
:
5022 case TGSI_OPCODE_UIF
:
5024 /* fallthrough to default case to mark the condition as read */
5026 /* Continuing the block, clear any channels from the write array that
5027 * are read by this instruction.
5029 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5030 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5031 /* Any temporary might be read, so no dead code elimination
5032 * across this instruction.
5034 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5035 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5036 /* Clear where it's used as src. */
5037 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5038 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5039 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5040 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5042 for (int c
= 0; c
< 4; c
++) {
5043 if (src_chans
& (1 << c
))
5044 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5048 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5049 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5050 /* Any temporary might be read, so no dead code elimination
5051 * across this instruction.
5053 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5054 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5055 /* Clear where it's used as src. */
5056 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5057 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5058 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5059 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5061 for (int c
= 0; c
< 4; c
++) {
5062 if (src_chans
& (1 << c
))
5063 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5068 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5071 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5072 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5073 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5074 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5076 for (int c
= 0; c
< 4; c
++) {
5077 if (src_chans
& (1 << c
))
5078 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5085 /* If this instruction writes to a temporary, add it to the write array.
5086 * If there is already an instruction in the write array for one or more
5087 * of the channels, flag that channel write as dead.
5089 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5090 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5091 !inst
->dst
[i
].reladdr
) {
5092 for (int c
= 0; c
< 4; c
++) {
5093 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5094 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5095 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5098 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5100 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5101 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5108 /* Anything still in the write array at this point is dead code. */
5109 for (int r
= 0; r
< this->next_temp
; r
++) {
5110 for (int c
= 0; c
< 4; c
++) {
5111 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5113 inst
->dead_mask
|= (1 << c
);
5117 /* Now actually remove the instructions that are completely dead and update
5118 * the writemask of other instructions with dead channels.
5120 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5121 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5123 /* No amount of dead masks should remove memory stores */
5124 if (inst
->info
->is_store
)
5127 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5132 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5133 if (inst
->dead_mask
== WRITEMASK_XY
||
5134 inst
->dead_mask
== WRITEMASK_ZW
)
5135 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5137 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5141 ralloc_free(write_level
);
5142 ralloc_free(writes
);
5147 /* merge DFRACEXP instructions into one. */
5149 glsl_to_tgsi_visitor::merge_two_dsts(void)
5151 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5152 glsl_to_tgsi_instruction
*inst2
;
5154 if (num_inst_dst_regs(inst
) != 2)
5157 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5158 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5161 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5164 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5165 inst
->src
[0].index
== inst2
->src
[0].index
&&
5166 inst
->src
[0].type
== inst2
->src
[0].type
&&
5167 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5169 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5175 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5177 inst
->dst
[0] = inst2
->dst
[0];
5178 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5179 inst
->dst
[1] = inst2
->dst
[1];
5190 /* Merges temporary registers together where possible to reduce the number of
5191 * registers needed to run a program.
5193 * Produces optimal code only after copy propagation and dead code elimination
5196 glsl_to_tgsi_visitor::merge_registers(void)
5199 struct lifetime
*lifetimes
=
5200 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5202 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5203 this->next_temp
, lifetimes
)) {
5204 struct rename_reg_pair
*renames
=
5205 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5206 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5207 rename_temp_registers(renames
);
5208 ralloc_free(renames
);
5211 ralloc_free(lifetimes
);
5214 /* Reassign indices to temporary registers by reusing unused indices created
5215 * by optimization passes. */
5217 glsl_to_tgsi_visitor::renumber_registers(void)
5221 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5222 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5224 for (i
= 0; i
< this->next_temp
; i
++) {
5225 first_writes
[i
] = -1;
5227 get_first_temp_write(first_writes
);
5229 for (i
= 0; i
< this->next_temp
; i
++) {
5230 if (first_writes
[i
] < 0) continue;
5231 if (i
!= new_index
) {
5232 renames
[i
].new_reg
= new_index
;
5233 renames
[i
].valid
= true;
5238 rename_temp_registers(renames
);
5239 this->next_temp
= new_index
;
5240 ralloc_free(renames
);
5241 ralloc_free(first_writes
);
5244 /* ------------------------- TGSI conversion stuff -------------------------- */
5247 * Intermediate state used during shader translation.
5249 struct st_translate
{
5250 struct ureg_program
*ureg
;
5252 unsigned temps_size
;
5253 struct ureg_dst
*temps
;
5255 struct ureg_dst
*arrays
;
5256 unsigned num_temp_arrays
;
5257 struct ureg_src
*constants
;
5259 struct ureg_src
*immediates
;
5261 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5262 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5263 struct ureg_dst address
[3];
5264 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5265 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5266 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5267 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5268 struct ureg_src shared_memory
;
5269 unsigned *array_sizes
;
5270 struct inout_decl
*input_decls
;
5271 unsigned num_input_decls
;
5272 struct inout_decl
*output_decls
;
5273 unsigned num_output_decls
;
5275 const ubyte
*inputMapping
;
5276 const ubyte
*outputMapping
;
5278 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5281 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5283 _mesa_sysval_to_semantic(unsigned sysval
)
5287 case SYSTEM_VALUE_VERTEX_ID
:
5288 return TGSI_SEMANTIC_VERTEXID
;
5289 case SYSTEM_VALUE_INSTANCE_ID
:
5290 return TGSI_SEMANTIC_INSTANCEID
;
5291 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5292 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5293 case SYSTEM_VALUE_BASE_VERTEX
:
5294 return TGSI_SEMANTIC_BASEVERTEX
;
5295 case SYSTEM_VALUE_BASE_INSTANCE
:
5296 return TGSI_SEMANTIC_BASEINSTANCE
;
5297 case SYSTEM_VALUE_DRAW_ID
:
5298 return TGSI_SEMANTIC_DRAWID
;
5300 /* Geometry shader */
5301 case SYSTEM_VALUE_INVOCATION_ID
:
5302 return TGSI_SEMANTIC_INVOCATIONID
;
5304 /* Fragment shader */
5305 case SYSTEM_VALUE_FRAG_COORD
:
5306 return TGSI_SEMANTIC_POSITION
;
5307 case SYSTEM_VALUE_FRONT_FACE
:
5308 return TGSI_SEMANTIC_FACE
;
5309 case SYSTEM_VALUE_SAMPLE_ID
:
5310 return TGSI_SEMANTIC_SAMPLEID
;
5311 case SYSTEM_VALUE_SAMPLE_POS
:
5312 return TGSI_SEMANTIC_SAMPLEPOS
;
5313 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5314 return TGSI_SEMANTIC_SAMPLEMASK
;
5315 case SYSTEM_VALUE_HELPER_INVOCATION
:
5316 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5318 /* Tessellation shader */
5319 case SYSTEM_VALUE_TESS_COORD
:
5320 return TGSI_SEMANTIC_TESSCOORD
;
5321 case SYSTEM_VALUE_VERTICES_IN
:
5322 return TGSI_SEMANTIC_VERTICESIN
;
5323 case SYSTEM_VALUE_PRIMITIVE_ID
:
5324 return TGSI_SEMANTIC_PRIMID
;
5325 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5326 return TGSI_SEMANTIC_TESSOUTER
;
5327 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5328 return TGSI_SEMANTIC_TESSINNER
;
5330 /* Compute shader */
5331 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5332 return TGSI_SEMANTIC_THREAD_ID
;
5333 case SYSTEM_VALUE_WORK_GROUP_ID
:
5334 return TGSI_SEMANTIC_BLOCK_ID
;
5335 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5336 return TGSI_SEMANTIC_GRID_SIZE
;
5337 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5338 return TGSI_SEMANTIC_BLOCK_SIZE
;
5340 /* ARB_shader_ballot */
5341 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5342 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5343 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5344 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5345 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5346 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5347 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5348 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5349 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5350 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5351 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5352 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5353 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5354 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5357 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5358 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5359 case SYSTEM_VALUE_VERTEX_CNT
:
5361 assert(!"Unexpected SYSTEM_VALUE_ enum");
5362 return TGSI_SEMANTIC_COUNT
;
5367 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5369 static struct ureg_src
5370 emit_immediate(struct st_translate
*t
,
5371 gl_constant_value values
[4],
5374 struct ureg_program
*ureg
= t
->ureg
;
5379 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5381 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5383 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5384 case GL_UNSIGNED_INT64_ARB
:
5385 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5387 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5388 case GL_UNSIGNED_INT
:
5390 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5392 assert(!"should not get here - type must be float, int, uint, or bool");
5393 return ureg_src_undef();
5398 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5400 static struct ureg_dst
5401 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5407 case PROGRAM_UNDEFINED
:
5408 return ureg_dst_undef();
5410 case PROGRAM_TEMPORARY
:
5411 /* Allocate space for temporaries on demand. */
5412 if (index
>= t
->temps_size
) {
5413 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5415 t
->temps
= (struct ureg_dst
*)
5417 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5419 return ureg_dst_undef();
5421 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5422 t
->temps_size
+= inc
;
5425 if (ureg_dst_is_undef(t
->temps
[index
]))
5426 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5428 return t
->temps
[index
];
5431 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5432 array
= array_id
- 1;
5434 if (ureg_dst_is_undef(t
->arrays
[array
]))
5435 t
->arrays
[array
] = ureg_DECL_array_temporary(
5436 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5438 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5440 case PROGRAM_OUTPUT
:
5442 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5443 assert(index
< 2 * FRAG_RESULT_MAX
);
5444 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5445 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5446 assert(index
< VARYING_SLOT_TESS_MAX
);
5448 assert(index
< VARYING_SLOT_MAX
);
5450 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5451 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5452 return t
->outputs
[t
->outputMapping
[index
]];
5455 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5456 unsigned mesa_index
= decl
->mesa_index
;
5457 int slot
= t
->outputMapping
[mesa_index
];
5459 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5461 struct ureg_dst dst
= t
->outputs
[slot
];
5462 dst
.ArrayID
= array_id
;
5463 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5466 case PROGRAM_ADDRESS
:
5467 return t
->address
[index
];
5470 assert(!"unknown dst register file");
5471 return ureg_dst_undef();
5476 * Create a TGSI ureg_dst register from an st_dst_reg.
5478 static struct ureg_dst
5479 translate_dst(struct st_translate
*t
,
5480 const st_dst_reg
*dst_reg
,
5483 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5486 if (dst
.File
== TGSI_FILE_NULL
)
5489 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5492 dst
= ureg_saturate(dst
);
5494 if (dst_reg
->reladdr
!= NULL
) {
5495 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5496 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5499 if (dst_reg
->has_index2
) {
5500 if (dst_reg
->reladdr2
)
5501 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5504 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5511 * Create a TGSI ureg_src register from an st_src_reg.
5513 static struct ureg_src
5514 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5516 struct ureg_src src
;
5517 int index
= src_reg
->index
;
5518 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5520 switch(src_reg
->file
) {
5521 case PROGRAM_UNDEFINED
:
5522 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5525 case PROGRAM_TEMPORARY
:
5527 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
));
5530 case PROGRAM_OUTPUT
: {
5531 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
);
5532 assert(dst
.WriteMask
!= 0);
5533 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5534 src
= ureg_swizzle(ureg_src(dst
),
5538 MIN2(shift
+ 3, 3));
5542 case PROGRAM_UNIFORM
:
5543 assert(src_reg
->index
>= 0);
5544 src
= src_reg
->index
< t
->num_constants
?
5545 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5547 case PROGRAM_STATE_VAR
:
5548 case PROGRAM_CONSTANT
: /* ie, immediate */
5549 if (src_reg
->has_index2
)
5550 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5552 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5553 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5556 case PROGRAM_IMMEDIATE
:
5557 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5558 src
= t
->immediates
[src_reg
->index
];
5562 /* GLSL inputs are 64-bit containers, so we have to
5563 * map back to the original index and add the offset after
5565 index
-= double_reg2
;
5566 if (!src_reg
->array_id
) {
5567 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5568 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5569 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5572 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
,
5574 unsigned mesa_index
= decl
->mesa_index
;
5575 int slot
= t
->inputMapping
[mesa_index
];
5577 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5579 src
= t
->inputs
[slot
];
5580 src
.ArrayID
= src_reg
->array_id
;
5581 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5585 case PROGRAM_ADDRESS
:
5586 src
= ureg_src(t
->address
[src_reg
->index
]);
5589 case PROGRAM_SYSTEM_VALUE
:
5590 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5591 src
= t
->systemValues
[src_reg
->index
];
5595 assert(!"unknown src register file");
5596 return ureg_src_undef();
5599 if (src_reg
->has_index2
) {
5600 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5601 * and UBO constant buffers (buffer, position).
5603 if (src_reg
->reladdr2
)
5604 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5607 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5610 src
= ureg_swizzle(src
,
5611 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5612 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5613 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5614 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5617 src
= ureg_abs(src
);
5619 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5620 src
= ureg_negate(src
);
5622 if (src_reg
->reladdr
!= NULL
) {
5623 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5624 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5630 static struct tgsi_texture_offset
5631 translate_tex_offset(struct st_translate
*t
,
5632 const st_src_reg
*in_offset
)
5634 struct tgsi_texture_offset offset
;
5635 struct ureg_src src
= translate_src(t
, in_offset
);
5637 offset
.File
= src
.File
;
5638 offset
.Index
= src
.Index
;
5639 offset
.SwizzleX
= src
.SwizzleX
;
5640 offset
.SwizzleY
= src
.SwizzleY
;
5641 offset
.SwizzleZ
= src
.SwizzleZ
;
5644 assert(!src
.Indirect
);
5645 assert(!src
.DimIndirect
);
5646 assert(!src
.Dimension
);
5647 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5648 assert(!src
.Negate
);
5654 compile_tgsi_instruction(struct st_translate
*t
,
5655 const glsl_to_tgsi_instruction
*inst
)
5657 struct ureg_program
*ureg
= t
->ureg
;
5659 struct ureg_dst dst
[2];
5660 struct ureg_src src
[4];
5661 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5665 unsigned tex_target
= 0;
5667 num_dst
= num_inst_dst_regs(inst
);
5668 num_src
= num_inst_src_regs(inst
);
5670 for (i
= 0; i
< num_dst
; i
++)
5671 dst
[i
] = translate_dst(t
,
5675 for (i
= 0; i
< num_src
; i
++)
5676 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5679 case TGSI_OPCODE_BGNLOOP
:
5680 case TGSI_OPCODE_ELSE
:
5681 case TGSI_OPCODE_ENDLOOP
:
5682 case TGSI_OPCODE_IF
:
5683 case TGSI_OPCODE_UIF
:
5684 assert(num_dst
== 0);
5685 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5688 case TGSI_OPCODE_TEX
:
5689 case TGSI_OPCODE_TEX_LZ
:
5690 case TGSI_OPCODE_TXB
:
5691 case TGSI_OPCODE_TXD
:
5692 case TGSI_OPCODE_TXL
:
5693 case TGSI_OPCODE_TXP
:
5694 case TGSI_OPCODE_TXQ
:
5695 case TGSI_OPCODE_TXQS
:
5696 case TGSI_OPCODE_TXF
:
5697 case TGSI_OPCODE_TXF_LZ
:
5698 case TGSI_OPCODE_TEX2
:
5699 case TGSI_OPCODE_TXB2
:
5700 case TGSI_OPCODE_TXL2
:
5701 case TGSI_OPCODE_TG4
:
5702 case TGSI_OPCODE_LODQ
:
5703 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5704 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5706 /* Bindless samplers. */
5707 src
[num_src
] = translate_src(t
, &inst
->resource
);
5709 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5710 if (inst
->resource
.reladdr
)
5712 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5714 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5715 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5717 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5723 st_translate_texture_type(inst
->tex_type
),
5724 texoffsets
, inst
->tex_offset_num_offset
,
5728 case TGSI_OPCODE_RESQ
:
5729 case TGSI_OPCODE_LOAD
:
5730 case TGSI_OPCODE_ATOMUADD
:
5731 case TGSI_OPCODE_ATOMXCHG
:
5732 case TGSI_OPCODE_ATOMCAS
:
5733 case TGSI_OPCODE_ATOMAND
:
5734 case TGSI_OPCODE_ATOMOR
:
5735 case TGSI_OPCODE_ATOMXOR
:
5736 case TGSI_OPCODE_ATOMUMIN
:
5737 case TGSI_OPCODE_ATOMUMAX
:
5738 case TGSI_OPCODE_ATOMIMIN
:
5739 case TGSI_OPCODE_ATOMIMAX
:
5740 for (i
= num_src
- 1; i
>= 0; i
--)
5741 src
[i
+ 1] = src
[i
];
5743 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5744 src
[0] = t
->shared_memory
;
5745 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5746 src
[0] = t
->buffers
[inst
->resource
.index
];
5747 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
5748 assert(inst
->resource
.has_index2
);
5749 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
5751 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
5752 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5753 src
[0] = t
->images
[inst
->resource
.index
];
5755 /* Bindless images. */
5756 src
[0] = translate_src(t
, &inst
->resource
);
5758 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5760 if (inst
->resource
.reladdr
)
5761 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5762 assert(src
[0].File
!= TGSI_FILE_NULL
);
5763 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5764 inst
->buffer_access
,
5765 tex_target
, inst
->image_format
);
5768 case TGSI_OPCODE_STORE
:
5769 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5770 dst
[0] = ureg_dst(t
->shared_memory
);
5771 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5772 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5774 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5775 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5777 /* Bindless images. */
5778 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
5780 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5782 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5783 if (inst
->resource
.reladdr
)
5784 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5785 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5786 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5787 inst
->buffer_access
,
5788 tex_target
, inst
->image_format
);
5795 src
, num_src
, inst
->precise
);
5801 * Emit the TGSI instructions for inverting and adjusting WPOS.
5802 * This code is unavoidable because it also depends on whether
5803 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5806 emit_wpos_adjustment(struct gl_context
*ctx
,
5807 struct st_translate
*t
,
5808 int wpos_transform_const
,
5810 GLfloat adjX
, GLfloat adjY
[2])
5812 struct ureg_program
*ureg
= t
->ureg
;
5814 assert(wpos_transform_const
>= 0);
5816 /* Fragment program uses fragment position input.
5817 * Need to replace instances of INPUT[WPOS] with temp T
5818 * where T = INPUT[WPOS] is inverted by Y.
5820 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5821 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5822 struct ureg_src
*wpos
=
5823 ctx
->Const
.GLSLFragCoordIsSysVal
?
5824 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5825 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5826 struct ureg_src wpos_input
= *wpos
;
5828 /* First, apply the coordinate shift: */
5829 if (adjX
|| adjY
[0] || adjY
[1]) {
5830 if (adjY
[0] != adjY
[1]) {
5831 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5832 * depending on whether inversion is actually going to be applied
5833 * or not, which is determined by testing against the inversion
5834 * state variable used below, which will be either +1 or -1.
5836 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5838 ureg_CMP(ureg
, adj_temp
,
5839 ureg_scalar(wpostrans
, invert
? 2 : 0),
5840 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5841 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5842 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5844 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5845 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5847 wpos_input
= ureg_src(wpos_temp
);
5849 /* MOV wpos_temp, input[wpos]
5851 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5854 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5855 * inversion/identity, or the other way around if we're drawing to an FBO.
5858 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5861 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5863 ureg_scalar(wpostrans
, 0),
5864 ureg_scalar(wpostrans
, 1));
5866 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5869 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5871 ureg_scalar(wpostrans
, 2),
5872 ureg_scalar(wpostrans
, 3));
5875 /* Use wpos_temp as position input from here on:
5877 *wpos
= ureg_src(wpos_temp
);
5882 * Emit fragment position/ooordinate code.
5885 emit_wpos(struct st_context
*st
,
5886 struct st_translate
*t
,
5887 const struct gl_program
*program
,
5888 struct ureg_program
*ureg
,
5889 int wpos_transform_const
)
5891 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5892 GLfloat adjX
= 0.0f
;
5893 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5894 boolean invert
= FALSE
;
5896 /* Query the pixel center conventions supported by the pipe driver and set
5897 * adjX, adjY to help out if it cannot handle the requested one internally.
5899 * The bias of the y-coordinate depends on whether y-inversion takes place
5900 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5901 * drawing to an FBO (causes additional inversion), and whether the pipe
5902 * driver origin and the requested origin differ (the latter condition is
5903 * stored in the 'invert' variable).
5905 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5907 * center shift only:
5912 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5913 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5914 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5915 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5917 * inversion and center shift:
5918 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5919 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5920 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5921 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5923 if (program
->OriginUpperLeft
) {
5924 /* Fragment shader wants origin in upper-left */
5925 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5926 /* the driver supports upper-left origin */
5928 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5929 /* the driver supports lower-left origin, need to invert Y */
5930 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5931 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5938 /* Fragment shader wants origin in lower-left */
5939 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5940 /* the driver supports lower-left origin */
5941 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5942 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5943 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5944 /* the driver supports upper-left origin, need to invert Y */
5950 if (program
->PixelCenterInteger
) {
5951 /* Fragment shader wants pixel center integer */
5952 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5953 /* the driver supports pixel center integer */
5955 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5956 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5958 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5959 /* the driver supports pixel center half integer, need to bias X,Y */
5968 /* Fragment shader wants pixel center half integer */
5969 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5970 /* the driver supports pixel center half integer */
5972 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5973 /* the driver supports pixel center integer, need to bias X,Y */
5974 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5975 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5976 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5982 /* we invert after adjustment so that we avoid the MOV to temporary,
5983 * and reuse the adjustment ADD instead */
5984 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5988 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5989 * TGSI uses +1 for front, -1 for back.
5990 * This function converts the TGSI value to the GL value. Simply clamping/
5991 * saturating the value to [0,1] does the job.
5994 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5996 struct ureg_program
*ureg
= t
->ureg
;
5997 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5998 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6000 if (ctx
->Const
.NativeIntegers
) {
6001 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6004 /* MOV_SAT face_temp, input[face] */
6005 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6008 /* Use face_temp as face input from here on: */
6009 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6013 emit_compute_block_size(const struct gl_program
*prog
,
6014 struct ureg_program
*ureg
) {
6015 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6016 prog
->info
.cs
.local_size
[0]);
6017 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6018 prog
->info
.cs
.local_size
[1]);
6019 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6020 prog
->info
.cs
.local_size
[2]);
6023 struct sort_inout_decls
{
6024 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6025 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6028 const ubyte
*mapping
;
6031 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6033 * This is for the benefit of older drivers which are broken when the
6034 * declarations aren't sorted in this way.
6037 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6039 const ubyte mapping
[])
6041 sort_inout_decls sorter
;
6042 sorter
.mapping
= mapping
;
6043 std::sort(decls
, decls
+ count
, sorter
);
6047 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6049 switch (glsl_qual
) {
6050 case INTERP_MODE_NONE
:
6051 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6052 return TGSI_INTERPOLATE_COLOR
;
6053 return TGSI_INTERPOLATE_PERSPECTIVE
;
6054 case INTERP_MODE_SMOOTH
:
6055 return TGSI_INTERPOLATE_PERSPECTIVE
;
6056 case INTERP_MODE_FLAT
:
6057 return TGSI_INTERPOLATE_CONSTANT
;
6058 case INTERP_MODE_NOPERSPECTIVE
:
6059 return TGSI_INTERPOLATE_LINEAR
;
6061 assert(0 && "unexpected interp mode in st_translate_interp()");
6062 return TGSI_INTERPOLATE_PERSPECTIVE
;
6067 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6068 * \param program the program to translate
6069 * \param numInputs number of input registers used
6070 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6072 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6073 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6075 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6076 * \param numOutputs number of output registers used
6077 * \param outputMapping maps Mesa fragment program outputs to TGSI
6079 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6080 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6083 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6085 extern "C" enum pipe_error
6086 st_translate_program(
6087 struct gl_context
*ctx
,
6089 struct ureg_program
*ureg
,
6090 glsl_to_tgsi_visitor
*program
,
6091 const struct gl_program
*proginfo
,
6093 const ubyte inputMapping
[],
6094 const ubyte inputSlotToAttr
[],
6095 const ubyte inputSemanticName
[],
6096 const ubyte inputSemanticIndex
[],
6097 const ubyte interpMode
[],
6099 const ubyte outputMapping
[],
6100 const ubyte outputSemanticName
[],
6101 const ubyte outputSemanticIndex
[])
6103 struct st_translate
*t
;
6105 struct gl_program_constants
*frag_const
=
6106 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6107 enum pipe_error ret
= PIPE_OK
;
6109 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6110 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6112 t
= CALLOC_STRUCT(st_translate
);
6114 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6118 t
->procType
= procType
;
6119 t
->inputMapping
= inputMapping
;
6120 t
->outputMapping
= outputMapping
;
6122 t
->num_temp_arrays
= program
->next_array
;
6123 if (t
->num_temp_arrays
)
6124 t
->arrays
= (struct ureg_dst
*)
6125 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6128 * Declare input attributes.
6131 case PIPE_SHADER_FRAGMENT
:
6132 case PIPE_SHADER_GEOMETRY
:
6133 case PIPE_SHADER_TESS_EVAL
:
6134 case PIPE_SHADER_TESS_CTRL
:
6135 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6137 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6138 struct inout_decl
*decl
= &program
->inputs
[i
];
6139 unsigned slot
= inputMapping
[decl
->mesa_index
];
6140 struct ureg_src src
;
6141 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6143 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6144 if (tgsi_usage_mask
== 1)
6145 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6146 else if (tgsi_usage_mask
== 2)
6147 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6149 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6152 unsigned interp_mode
= 0;
6153 unsigned interp_location
= 0;
6154 if (procType
== PIPE_SHADER_FRAGMENT
) {
6156 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6158 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6160 interp_location
= decl
->interp_loc
;
6163 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6164 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6165 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6166 decl
->array_id
, decl
->size
);
6168 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6169 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6170 /* The ArrayID is set up in dst_register */
6171 t
->inputs
[slot
+ j
] = src
;
6172 t
->inputs
[slot
+ j
].ArrayID
= 0;
6173 t
->inputs
[slot
+ j
].Index
+= j
;
6178 case PIPE_SHADER_VERTEX
:
6179 for (i
= 0; i
< numInputs
; i
++) {
6180 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6183 case PIPE_SHADER_COMPUTE
:
6190 * Declare output attributes.
6193 case PIPE_SHADER_FRAGMENT
:
6194 case PIPE_SHADER_COMPUTE
:
6196 case PIPE_SHADER_GEOMETRY
:
6197 case PIPE_SHADER_TESS_EVAL
:
6198 case PIPE_SHADER_TESS_CTRL
:
6199 case PIPE_SHADER_VERTEX
:
6200 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6202 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6203 struct inout_decl
*decl
= &program
->outputs
[i
];
6204 unsigned slot
= outputMapping
[decl
->mesa_index
];
6205 struct ureg_dst dst
;
6206 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6208 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6209 if (tgsi_usage_mask
== 1)
6210 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6211 else if (tgsi_usage_mask
== 2)
6212 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6214 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6217 dst
= ureg_DECL_output_layout(ureg
,
6218 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6219 decl
->gs_out_streams
,
6220 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6222 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6223 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6224 /* The ArrayID is set up in dst_register */
6225 t
->outputs
[slot
+ j
] = dst
;
6226 t
->outputs
[slot
+ j
].ArrayID
= 0;
6227 t
->outputs
[slot
+ j
].Index
+= j
;
6236 if (procType
== PIPE_SHADER_FRAGMENT
) {
6237 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6238 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6239 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6241 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6242 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6245 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6246 /* Must do this after setting up t->inputs. */
6247 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6248 program
->wpos_transform_const
);
6251 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6252 emit_face_var(ctx
, t
);
6254 for (i
= 0; i
< numOutputs
; i
++) {
6255 switch (outputSemanticName
[i
]) {
6256 case TGSI_SEMANTIC_POSITION
:
6257 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6258 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6259 outputSemanticIndex
[i
]);
6260 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6262 case TGSI_SEMANTIC_STENCIL
:
6263 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6264 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6265 outputSemanticIndex
[i
]);
6266 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6268 case TGSI_SEMANTIC_COLOR
:
6269 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6270 TGSI_SEMANTIC_COLOR
,
6271 outputSemanticIndex
[i
]);
6273 case TGSI_SEMANTIC_SAMPLEMASK
:
6274 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6275 TGSI_SEMANTIC_SAMPLEMASK
,
6276 outputSemanticIndex
[i
]);
6277 /* TODO: If we ever support more than 32 samples, this will have
6278 * to become an array.
6280 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6283 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6284 ret
= PIPE_ERROR_BAD_INPUT
;
6289 else if (procType
== PIPE_SHADER_VERTEX
) {
6290 for (i
= 0; i
< numOutputs
; i
++) {
6291 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6292 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6294 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6295 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6296 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6301 if (procType
== PIPE_SHADER_COMPUTE
) {
6302 emit_compute_block_size(proginfo
, ureg
);
6305 /* Declare address register.
6307 if (program
->num_address_regs
> 0) {
6308 assert(program
->num_address_regs
<= 3);
6309 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6310 t
->address
[i
] = ureg_DECL_address(ureg
);
6313 /* Declare misc input registers
6316 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6318 for (i
= 0; sysInputs
; i
++) {
6319 if (sysInputs
& (1 << i
)) {
6320 unsigned semName
= _mesa_sysval_to_semantic(i
);
6322 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6324 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6325 semName
== TGSI_SEMANTIC_VERTEXID
) {
6326 /* From Gallium perspective, these system values are always
6327 * integer, and require native integer support. However, if
6328 * native integer is supported on the vertex stage but not the
6329 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6330 * assumes these system values are floats. To resolve the
6331 * inconsistency, we insert a U2F.
6333 struct st_context
*st
= st_context(ctx
);
6334 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6335 assert(procType
== PIPE_SHADER_VERTEX
);
6336 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6338 if (!ctx
->Const
.NativeIntegers
) {
6339 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6340 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6341 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6345 if (procType
== PIPE_SHADER_FRAGMENT
&&
6346 semName
== TGSI_SEMANTIC_POSITION
)
6347 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6348 program
->wpos_transform_const
);
6350 sysInputs
&= ~(1 << i
);
6355 t
->array_sizes
= program
->array_sizes
;
6356 t
->input_decls
= program
->inputs
;
6357 t
->num_input_decls
= program
->num_inputs
;
6358 t
->output_decls
= program
->outputs
;
6359 t
->num_output_decls
= program
->num_outputs
;
6361 /* Emit constants and uniforms. TGSI uses a single index space for these,
6362 * so we put all the translated regs in t->constants.
6364 if (proginfo
->Parameters
) {
6365 t
->constants
= (struct ureg_src
*)
6366 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6367 if (t
->constants
== NULL
) {
6368 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6371 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6373 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6374 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6375 case PROGRAM_STATE_VAR
:
6376 case PROGRAM_UNIFORM
:
6377 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6380 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6381 * addressing of the const buffer.
6382 * FIXME: Be smarter and recognize param arrays:
6383 * indirect addressing is only valid within the referenced
6386 case PROGRAM_CONSTANT
:
6387 if (program
->indirect_addr_consts
)
6388 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6390 t
->constants
[i
] = emit_immediate(t
,
6391 proginfo
->Parameters
->ParameterValues
[i
],
6392 proginfo
->Parameters
->Parameters
[i
].DataType
,
6401 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6402 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6403 unsigned num_const_vecs
= (size
+ 15) / 16;
6404 unsigned first
, last
;
6405 assert(num_const_vecs
> 0);
6407 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6408 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6411 /* Emit immediate values.
6413 t
->immediates
= (struct ureg_src
*)
6414 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6415 if (t
->immediates
== NULL
) {
6416 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6419 t
->num_immediates
= program
->num_immediates
;
6422 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6423 assert(i
< program
->num_immediates
);
6424 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6426 assert(i
== program
->num_immediates
);
6428 /* texture samplers */
6429 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6430 if (program
->samplers_used
& (1u << i
)) {
6431 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6433 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6435 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6436 type
, type
, type
, type
);
6440 /* Declare atomic and shader storage buffers. */
6442 struct gl_program
*prog
= program
->prog
;
6444 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6445 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6446 assert(index
< frag_const
->MaxAtomicBuffers
);
6447 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6450 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6451 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6452 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6453 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6457 if (program
->use_shared_memory
)
6458 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6460 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6461 if (program
->images_used
& (1 << i
)) {
6462 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6463 program
->image_targets
[i
],
6464 program
->image_formats
[i
],
6469 /* Emit each instruction in turn:
6471 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6472 compile_tgsi_instruction(t
, inst
);
6474 /* Set the next shader stage hint for VS and TES. */
6476 case PIPE_SHADER_VERTEX
:
6477 case PIPE_SHADER_TESS_EVAL
:
6478 if (program
->shader_program
->SeparateShader
)
6481 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6482 if (program
->shader_program
->_LinkedShaders
[i
]) {
6483 ureg_set_next_shader_processor(
6484 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6496 t
->num_constants
= 0;
6497 free(t
->immediates
);
6498 t
->num_immediates
= 0;
6504 /* ----------------------------- End TGSI code ------------------------------ */
6508 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6509 * generating Mesa IR.
6511 static struct gl_program
*
6512 get_mesa_program_tgsi(struct gl_context
*ctx
,
6513 struct gl_shader_program
*shader_program
,
6514 struct gl_linked_shader
*shader
)
6516 glsl_to_tgsi_visitor
* v
;
6517 struct gl_program
*prog
;
6518 struct gl_shader_compiler_options
*options
=
6519 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6520 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6521 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6522 unsigned skip_merge_registers
;
6524 validate_ir_tree(shader
->ir
);
6526 prog
= shader
->Program
;
6528 prog
->Parameters
= _mesa_new_parameter_list();
6529 v
= new glsl_to_tgsi_visitor();
6532 v
->shader_program
= shader_program
;
6534 v
->options
= options
;
6535 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6536 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6538 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6539 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6540 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6541 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6542 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6543 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6545 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6546 _mesa_key_pointer_equal
);
6547 skip_merge_registers
=
6548 pscreen
->get_shader_param(pscreen
, ptarget
,
6549 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6551 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6554 /* Remove reads from output registers. */
6555 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6556 lower_output_reads(shader
->Stage
, shader
->ir
);
6558 /* Emit intermediate IR for main(). */
6559 visit_exec_list(shader
->ir
, v
);
6562 /* Print out some information (for debugging purposes) used by the
6563 * optimization passes. */
6566 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6567 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6568 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6569 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6571 for (i
= 0; i
< v
->next_temp
; i
++) {
6572 first_writes
[i
] = -1;
6573 first_reads
[i
] = -1;
6574 last_writes
[i
] = -1;
6577 v
->get_first_temp_read(first_reads
);
6578 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6579 v
->get_last_temp_write(last_writes
);
6580 for (i
= 0; i
< v
->next_temp
; i
++)
6581 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6585 ralloc_free(first_writes
);
6586 ralloc_free(first_reads
);
6587 ralloc_free(last_writes
);
6588 ralloc_free(last_reads
);
6592 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6595 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6596 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6597 v
->copy_propagate();
6599 while (v
->eliminate_dead_code());
6601 v
->merge_two_dsts();
6602 if (!skip_merge_registers
)
6603 v
->merge_registers();
6604 v
->renumber_registers();
6606 /* Write the END instruction. */
6607 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6609 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6611 _mesa_log("GLSL IR for linked %s program %d:\n",
6612 _mesa_shader_stage_to_string(shader
->Stage
),
6613 shader_program
->Name
);
6614 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6618 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6619 _mesa_copy_linked_program_data(shader_program
, shader
);
6620 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6621 &prog
->info
.inputs_read
,
6622 prog
->info
.double_inputs_read
,
6623 &prog
->info
.patch_inputs_read
);
6624 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6625 &prog
->info
.outputs_written
, 0ULL,
6626 &prog
->info
.patch_outputs_written
);
6627 count_resources(v
, prog
);
6629 /* The GLSL IR won't be needed anymore. */
6630 ralloc_free(shader
->ir
);
6633 /* This must be done before the uniform storage is associated. */
6634 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6635 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6636 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6637 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6638 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6641 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6642 wposTransformState
);
6645 /* Avoid reallocation of the program parameter list, because the uniform
6646 * storage is only associated with the original parameter list.
6647 * This should be enough for Bitmap and DrawPixels constants.
6649 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6651 /* This has to be done last. Any operation the can cause
6652 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6653 * program constant) has to happen before creating this linkage.
6655 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6656 if (!shader_program
->data
->LinkStatus
) {
6657 free_glsl_to_tgsi_visitor(v
);
6658 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6662 struct st_vertex_program
*stvp
;
6663 struct st_fragment_program
*stfp
;
6664 struct st_common_program
*stp
;
6665 struct st_compute_program
*stcp
;
6667 switch (shader
->Stage
) {
6668 case MESA_SHADER_VERTEX
:
6669 stvp
= (struct st_vertex_program
*)prog
;
6670 stvp
->glsl_to_tgsi
= v
;
6672 case MESA_SHADER_FRAGMENT
:
6673 stfp
= (struct st_fragment_program
*)prog
;
6674 stfp
->glsl_to_tgsi
= v
;
6676 case MESA_SHADER_TESS_CTRL
:
6677 case MESA_SHADER_TESS_EVAL
:
6678 case MESA_SHADER_GEOMETRY
:
6679 stp
= st_common_program(prog
);
6680 stp
->glsl_to_tgsi
= v
;
6682 case MESA_SHADER_COMPUTE
:
6683 stcp
= (struct st_compute_program
*)prog
;
6684 stcp
->glsl_to_tgsi
= v
;
6687 assert(!"should not be reached");
6694 /* See if there are unsupported control flow statements. */
6695 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6697 const struct gl_shader_compiler_options
*options
;
6699 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6705 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6707 /* Other functions are skipped (same as glsl_to_tgsi). */
6708 if (strcmp(ir
->name
, "main") == 0)
6709 return visit_continue
;
6711 return visit_continue_with_parent
;
6714 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6716 if (!ir
->callee
->is_intrinsic()) {
6717 unsupported
= true; /* it's a function call */
6720 return visit_continue
;
6723 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6725 if (options
->EmitNoMainReturn
) {
6729 return visit_continue
;
6736 has_unsupported_control_flow(exec_list
*ir
,
6737 const struct gl_shader_compiler_options
*options
)
6739 ir_control_flow_info_visitor
visitor(options
);
6740 visit_list_elements(&visitor
, ir
);
6741 return visitor
.unsupported
;
6748 * Called via ctx->Driver.LinkShader()
6749 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6750 * with code lowering and other optimizations.
6753 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6755 /* Return early if we are loading the shader from on-disk cache */
6756 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6760 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6761 assert(prog
->data
->LinkStatus
);
6763 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6764 if (prog
->_LinkedShaders
[i
] == NULL
)
6767 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6768 exec_list
*ir
= shader
->ir
;
6769 gl_shader_stage stage
= shader
->Stage
;
6770 const struct gl_shader_compiler_options
*options
=
6771 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6772 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
6773 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6774 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6775 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6776 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6777 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6778 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6780 /* If there are forms of indirect addressing that the driver
6781 * cannot handle, perform the lowering pass.
6783 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6784 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6785 lower_variable_index_to_cond_assign(stage
, ir
,
6786 options
->EmitNoIndirectInput
,
6787 options
->EmitNoIndirectOutput
,
6788 options
->EmitNoIndirectTemp
,
6789 options
->EmitNoIndirectUniform
);
6792 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6793 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6795 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6796 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6797 LOWER_UNPACK_SNORM_2x16
|
6798 LOWER_PACK_UNORM_2x16
|
6799 LOWER_UNPACK_UNORM_2x16
|
6800 LOWER_PACK_SNORM_4x8
|
6801 LOWER_UNPACK_SNORM_4x8
|
6802 LOWER_UNPACK_UNORM_4x8
|
6803 LOWER_PACK_UNORM_4x8
;
6805 if (ctx
->Extensions
.ARB_gpu_shader5
)
6806 lower_inst
|= LOWER_PACK_USE_BFI
|
6808 if (!ctx
->st
->has_half_float_packing
)
6809 lower_inst
|= LOWER_PACK_HALF_2x16
|
6810 LOWER_UNPACK_HALF_2x16
;
6812 lower_packing_builtins(ir
, lower_inst
);
6815 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6816 lower_offset_arrays(ir
);
6817 do_mat_op_to_vec(ir
);
6819 if (stage
== MESA_SHADER_FRAGMENT
)
6820 lower_blend_equation_advanced(shader
);
6822 lower_instructions(ir
,
6828 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6831 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6832 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6833 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6834 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6835 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6836 /* Assume that if ARB_gpu_shader5 is not supported
6837 * then all of the extended integer functions need
6838 * lowering. It may be necessary to add some caps
6839 * for individual instructions.
6841 (!ctx
->Extensions
.ARB_gpu_shader5
6842 ? BIT_COUNT_TO_MATH
|
6846 FIND_LSB_TO_FLOAT_CAST
|
6847 FIND_MSB_TO_FLOAT_CAST
|
6851 do_vec_index_to_cond_assign(ir
);
6852 lower_vector_insert(ir
, true);
6853 lower_quadop_vector(ir
, false);
6855 if (options
->MaxIfDepth
== 0) {
6859 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6860 /* Do it once and repeat only if there's unsupported control flow. */
6862 do_common_optimization(ir
, true, true, options
,
6863 ctx
->Const
.NativeIntegers
);
6864 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6865 options
->MaxIfDepth
, if_threshold
);
6866 } while (has_unsupported_control_flow(ir
, options
));
6868 /* Repeat it until it stops making changes. */
6871 progress
= do_common_optimization(ir
, true, true, options
,
6872 ctx
->Const
.NativeIntegers
);
6873 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6874 options
->MaxIfDepth
, if_threshold
);
6878 validate_ir_tree(ir
);
6881 build_program_resource_list(ctx
, prog
);
6883 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6884 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6888 enum pipe_shader_type ptarget
=
6889 pipe_shader_type_from_mesa(shader
->Stage
);
6890 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6891 pscreen
->get_shader_param(pscreen
, ptarget
,
6892 PIPE_SHADER_CAP_PREFERRED_IR
);
6894 struct gl_program
*linked_prog
= NULL
;
6895 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6896 /* TODO only for GLSL VS/FS/CS for now: */
6897 switch (shader
->Stage
) {
6898 case MESA_SHADER_VERTEX
:
6899 case MESA_SHADER_FRAGMENT
:
6900 case MESA_SHADER_COMPUTE
:
6901 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6906 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6910 st_set_prog_affected_state_flags(linked_prog
);
6911 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6912 _mesa_shader_stage_to_program(i
),
6914 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6924 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6925 const ubyte outputMapping
[],
6926 struct pipe_stream_output_info
*so
)
6928 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
6931 struct gl_transform_feedback_info
*info
=
6932 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
6933 st_translate_stream_output_info2(info
, outputMapping
, so
);
6937 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
6938 const ubyte outputMapping
[],
6939 struct pipe_stream_output_info
*so
)
6943 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6944 so
->output
[i
].register_index
=
6945 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6946 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6947 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6948 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6949 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6950 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6953 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6954 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6956 so
->num_outputs
= info
->NumOutputs
;