2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
57 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
58 (1 << PROGRAM_CONSTANT) | \
59 (1 << PROGRAM_UNIFORM))
61 #define MAX_GLSL_TEXTURE_OFFSET 4
66 static int swizzle_for_size(int size
);
69 * This struct is a corresponding struct to TGSI ureg_src.
73 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
83 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
85 this->reladdr2
= NULL
;
86 this->has_index2
= false;
87 this->double_reg2
= false;
89 this->is_double_vertex_input
= false;
92 st_src_reg(gl_register_file file
, int index
, int type
)
98 this->swizzle
= SWIZZLE_XYZW
;
100 this->reladdr
= NULL
;
101 this->reladdr2
= NULL
;
102 this->has_index2
= false;
103 this->double_reg2
= false;
105 this->is_double_vertex_input
= false;
108 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
113 this->index2D
= index2D
;
114 this->swizzle
= SWIZZLE_XYZW
;
116 this->reladdr
= NULL
;
117 this->reladdr2
= NULL
;
118 this->has_index2
= false;
119 this->double_reg2
= false;
121 this->is_double_vertex_input
= false;
126 this->type
= GLSL_TYPE_ERROR
;
127 this->file
= PROGRAM_UNDEFINED
;
132 this->reladdr
= NULL
;
133 this->reladdr2
= NULL
;
134 this->has_index2
= false;
135 this->double_reg2
= false;
137 this->is_double_vertex_input
= false;
140 explicit st_src_reg(st_dst_reg reg
);
142 gl_register_file file
; /**< PROGRAM_* from Mesa */
143 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
145 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
146 int negate
; /**< NEGATE_XYZW mask from mesa */
147 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
148 /** Register index should be offset by the integer in this reg. */
150 st_src_reg
*reladdr2
;
153 * Is this the second half of a double register pair?
154 * currently used for input mapping only.
158 bool is_double_vertex_input
;
163 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
168 this->writemask
= writemask
;
169 this->cond_mask
= COND_TR
;
170 this->reladdr
= NULL
;
171 this->reladdr2
= NULL
;
172 this->has_index2
= false;
177 st_dst_reg(gl_register_file file
, int writemask
, int type
)
182 this->writemask
= writemask
;
183 this->cond_mask
= COND_TR
;
184 this->reladdr
= NULL
;
185 this->reladdr2
= NULL
;
186 this->has_index2
= false;
193 this->type
= GLSL_TYPE_ERROR
;
194 this->file
= PROGRAM_UNDEFINED
;
198 this->cond_mask
= COND_TR
;
199 this->reladdr
= NULL
;
200 this->reladdr2
= NULL
;
201 this->has_index2
= false;
205 explicit st_dst_reg(st_src_reg reg
);
207 gl_register_file file
; /**< PROGRAM_* from Mesa */
208 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
210 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
212 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
213 /** Register index should be offset by the integer in this reg. */
215 st_src_reg
*reladdr2
;
220 st_src_reg::st_src_reg(st_dst_reg reg
)
222 this->type
= reg
.type
;
223 this->file
= reg
.file
;
224 this->index
= reg
.index
;
225 this->swizzle
= SWIZZLE_XYZW
;
227 this->reladdr
= reg
.reladdr
;
228 this->index2D
= reg
.index2D
;
229 this->reladdr2
= reg
.reladdr2
;
230 this->has_index2
= reg
.has_index2
;
231 this->double_reg2
= false;
232 this->array_id
= reg
.array_id
;
233 this->is_double_vertex_input
= false;
236 st_dst_reg::st_dst_reg(st_src_reg reg
)
238 this->type
= reg
.type
;
239 this->file
= reg
.file
;
240 this->index
= reg
.index
;
241 this->writemask
= WRITEMASK_XYZW
;
242 this->cond_mask
= COND_TR
;
243 this->reladdr
= reg
.reladdr
;
244 this->index2D
= reg
.index2D
;
245 this->reladdr2
= reg
.reladdr2
;
246 this->has_index2
= reg
.has_index2
;
247 this->array_id
= reg
.array_id
;
250 class glsl_to_tgsi_instruction
: public exec_node
{
252 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
257 /** Pointer to the ir source this tree came from for debugging */
259 GLboolean cond_update
;
261 st_src_reg sampler
; /**< sampler register */
263 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
264 int tex_target
; /**< One of TEXTURE_*_INDEX */
265 glsl_base_type tex_type
;
266 GLboolean tex_shadow
;
267 unsigned image_format
;
269 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
270 unsigned tex_offset_num_offset
;
271 int dead_mask
; /**< Used in dead code elimination */
273 st_src_reg buffer
; /**< buffer register */
274 unsigned buffer_access
; /**< buffer access type */
276 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
277 const struct tgsi_opcode_info
*info
;
280 class variable_storage
: public exec_node
{
282 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
283 unsigned array_id
= 0)
284 : file(file
), index(index
), var(var
), array_id(array_id
)
289 gl_register_file file
;
291 ir_variable
*var
; /* variable that maps to this, if any */
295 class immediate_storage
: public exec_node
{
297 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
299 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
300 this->size32
= size32
;
304 /* doubles are stored across 2 gl_constant_values */
305 gl_constant_value values
[4];
306 int size32
; /**< Number of 32-bit components (1-4) */
307 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
310 class function_entry
: public exec_node
{
312 ir_function_signature
*sig
;
315 * identifier of this function signature used by the program.
317 * At the point that TGSI instructions for function calls are
318 * generated, we don't know the address of the first instruction of
319 * the function body. So we make the BranchTarget that is called a
320 * small integer and rewrite them during set_branchtargets().
325 * Pointer to first instruction of the function body.
327 * Set during function body emits after main() is processed.
329 glsl_to_tgsi_instruction
*bgn_inst
;
332 * Index of the first instruction of the function body in actual TGSI.
334 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
338 /** Storage for the return value. */
339 st_src_reg return_reg
;
342 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
343 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
353 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
357 for (i
= 0; i
< count
; i
++) {
358 struct array_decl
*decl
= &arrays
[i
];
360 if (array_id
== decl
->array_id
) {
361 return decl
->array_type
;
364 return GLSL_TYPE_ERROR
;
367 struct rename_reg_pair
{
372 struct glsl_to_tgsi_visitor
: public ir_visitor
{
374 glsl_to_tgsi_visitor();
375 ~glsl_to_tgsi_visitor();
377 function_entry
*current_function
;
379 struct gl_context
*ctx
;
380 struct gl_program
*prog
;
381 struct gl_shader_program
*shader_program
;
382 struct gl_shader
*shader
;
383 struct gl_shader_compiler_options
*options
;
387 unsigned *array_sizes
;
388 unsigned max_num_arrays
;
391 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
392 unsigned num_input_arrays
;
393 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
394 unsigned num_output_arrays
;
396 int num_address_regs
;
398 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
399 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
402 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
403 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
404 bool indirect_addr_consts
;
405 int wpos_transform_const
;
408 bool native_integers
;
411 bool use_shared_memory
;
413 variable_storage
*find_variable_storage(ir_variable
*var
);
415 int add_constant(gl_register_file file
, gl_constant_value values
[8],
416 int size
, int datatype
, GLuint
*swizzle_out
);
418 function_entry
*get_function_signature(ir_function_signature
*sig
);
420 st_src_reg
get_temp(const glsl_type
*type
);
421 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
423 st_src_reg
st_src_reg_for_double(double val
);
424 st_src_reg
st_src_reg_for_float(float val
);
425 st_src_reg
st_src_reg_for_int(int val
);
426 st_src_reg
st_src_reg_for_type(int type
, int val
);
429 * \name Visit methods
431 * As typical for the visitor pattern, there must be one \c visit method for
432 * each concrete subclass of \c ir_instruction. Virtual base classes within
433 * the hierarchy should not have \c visit methods.
436 virtual void visit(ir_variable
*);
437 virtual void visit(ir_loop
*);
438 virtual void visit(ir_loop_jump
*);
439 virtual void visit(ir_function_signature
*);
440 virtual void visit(ir_function
*);
441 virtual void visit(ir_expression
*);
442 virtual void visit(ir_swizzle
*);
443 virtual void visit(ir_dereference_variable
*);
444 virtual void visit(ir_dereference_array
*);
445 virtual void visit(ir_dereference_record
*);
446 virtual void visit(ir_assignment
*);
447 virtual void visit(ir_constant
*);
448 virtual void visit(ir_call
*);
449 virtual void visit(ir_return
*);
450 virtual void visit(ir_discard
*);
451 virtual void visit(ir_texture
*);
452 virtual void visit(ir_if
*);
453 virtual void visit(ir_emit_vertex
*);
454 virtual void visit(ir_end_primitive
*);
455 virtual void visit(ir_barrier
*);
458 void visit_atomic_counter_intrinsic(ir_call
*);
459 void visit_ssbo_intrinsic(ir_call
*);
460 void visit_membar_intrinsic(ir_call
*);
461 void visit_shared_intrinsic(ir_call
*);
462 void visit_image_intrinsic(ir_call
*);
466 /** List of variable_storage */
469 /** List of immediate_storage */
470 exec_list immediates
;
471 unsigned num_immediates
;
473 /** List of function_entry */
474 exec_list function_signatures
;
475 int next_signature_id
;
477 /** List of glsl_to_tgsi_instruction */
478 exec_list instructions
;
480 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
481 st_dst_reg dst
= undef_dst
,
482 st_src_reg src0
= undef_src
,
483 st_src_reg src1
= undef_src
,
484 st_src_reg src2
= undef_src
,
485 st_src_reg src3
= undef_src
);
487 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
488 st_dst_reg dst
, st_dst_reg dst1
,
489 st_src_reg src0
= undef_src
,
490 st_src_reg src1
= undef_src
,
491 st_src_reg src2
= undef_src
,
492 st_src_reg src3
= undef_src
);
494 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
496 st_src_reg src0
, st_src_reg src1
);
499 * Emit the correct dot-product instruction for the type of arguments
501 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
507 void emit_scalar(ir_instruction
*ir
, unsigned op
,
508 st_dst_reg dst
, st_src_reg src0
);
510 void emit_scalar(ir_instruction
*ir
, unsigned op
,
511 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
513 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
515 void get_deref_offsets(ir_dereference
*ir
,
516 unsigned *array_size
,
519 st_src_reg
*reladdr
);
520 void calc_deref_offsets(ir_dereference
*head
,
521 ir_dereference
*tail
,
522 unsigned *array_elements
,
525 st_src_reg
*indirect
,
528 bool try_emit_mad(ir_expression
*ir
,
530 bool try_emit_mad_for_and_not(ir_expression
*ir
,
533 void emit_swz(ir_expression
*ir
);
535 bool process_move_condition(ir_rvalue
*ir
);
537 void simplify_cmp(void);
539 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
540 void get_first_temp_read(int *first_reads
);
541 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
542 void get_last_temp_write(int *last_writes
);
544 void copy_propagate(void);
545 int eliminate_dead_code(void);
547 void merge_two_dsts(void);
548 void merge_registers(void);
549 void renumber_registers(void);
551 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
552 st_dst_reg
*l
, st_src_reg
*r
,
553 st_src_reg
*cond
, bool cond_swap
);
558 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
559 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
560 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
563 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
566 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
570 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
573 prog
->LinkStatus
= GL_FALSE
;
577 swizzle_for_size(int size
)
579 static const int size_swizzles
[4] = {
580 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
581 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
582 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
583 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
586 assert((size
>= 1) && (size
<= 4));
587 return size_swizzles
[size
- 1];
591 is_resource_instruction(unsigned opcode
)
594 case TGSI_OPCODE_RESQ
:
595 case TGSI_OPCODE_LOAD
:
596 case TGSI_OPCODE_ATOMUADD
:
597 case TGSI_OPCODE_ATOMXCHG
:
598 case TGSI_OPCODE_ATOMCAS
:
599 case TGSI_OPCODE_ATOMAND
:
600 case TGSI_OPCODE_ATOMOR
:
601 case TGSI_OPCODE_ATOMXOR
:
602 case TGSI_OPCODE_ATOMUMIN
:
603 case TGSI_OPCODE_ATOMUMAX
:
604 case TGSI_OPCODE_ATOMIMIN
:
605 case TGSI_OPCODE_ATOMIMAX
:
613 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
615 return op
->info
->num_dst
;
619 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
621 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
622 op
->info
->num_src
- 1 : op
->info
->num_src
;
625 glsl_to_tgsi_instruction
*
626 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
627 st_dst_reg dst
, st_dst_reg dst1
,
628 st_src_reg src0
, st_src_reg src1
,
629 st_src_reg src2
, st_src_reg src3
)
631 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
632 int num_reladdr
= 0, i
, j
;
633 bool dst_is_double
[2];
635 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
637 /* If we have to do relative addressing, we want to load the ARL
638 * reg directly for one of the regs, and preload the other reladdr
639 * sources into temps.
641 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
642 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
643 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
644 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
645 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
646 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
648 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
649 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
650 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
651 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
653 if (dst
.reladdr
|| dst
.reladdr2
) {
655 emit_arl(ir
, address_reg
, *dst
.reladdr
);
657 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
661 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
664 assert(num_reladdr
== 0);
667 inst
->info
= tgsi_get_opcode_info(op
);
676 /* default to float, for paths where this is not initialized
677 * (since 0==UINT which is likely wrong):
679 inst
->tex_type
= GLSL_TYPE_FLOAT
;
681 inst
->function
= NULL
;
683 /* Update indirect addressing status used by TGSI */
684 if (dst
.reladdr
|| dst
.reladdr2
) {
686 case PROGRAM_STATE_VAR
:
687 case PROGRAM_CONSTANT
:
688 case PROGRAM_UNIFORM
:
689 this->indirect_addr_consts
= true;
691 case PROGRAM_IMMEDIATE
:
692 assert(!"immediates should not have indirect addressing");
699 for (i
= 0; i
< 4; i
++) {
700 if(inst
->src
[i
].reladdr
) {
701 switch(inst
->src
[i
].file
) {
702 case PROGRAM_STATE_VAR
:
703 case PROGRAM_CONSTANT
:
704 case PROGRAM_UNIFORM
:
705 this->indirect_addr_consts
= true;
707 case PROGRAM_IMMEDIATE
:
708 assert(!"immediates should not have indirect addressing");
718 * This section contains the double processing.
719 * GLSL just represents doubles as single channel values,
720 * however most HW and TGSI represent doubles as pairs of register channels.
722 * so we have to fixup destination writemask/index and src swizzle/indexes.
723 * dest writemasks need to translate from single channel write mask
724 * to a dual-channel writemask, but also need to modify the index,
725 * if we are touching the Z,W fields in the pre-translated writemask.
727 * src channels have similiar index modifications along with swizzle
728 * changes to we pick the XY, ZW pairs from the correct index.
730 * GLSL [0].x -> TGSI [0].xy
731 * GLSL [0].y -> TGSI [0].zw
732 * GLSL [0].z -> TGSI [1].xy
733 * GLSL [0].w -> TGSI [1].zw
735 for (j
= 0; j
< 2; j
++) {
736 dst_is_double
[j
] = false;
737 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
738 dst_is_double
[j
] = true;
739 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
740 unsigned type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
741 if (type
== GLSL_TYPE_DOUBLE
)
742 dst_is_double
[j
] = true;
746 if (dst_is_double
[0] || dst_is_double
[1] ||
747 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
748 glsl_to_tgsi_instruction
*dinst
= NULL
;
749 int initial_src_swz
[4], initial_src_idx
[4];
750 int initial_dst_idx
[2], initial_dst_writemask
[2];
751 /* select the writemask for dst0 or dst1 */
752 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
754 /* copy out the writemask, index and swizzles for all src/dsts. */
755 for (j
= 0; j
< 2; j
++) {
756 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
757 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
760 for (j
= 0; j
< 4; j
++) {
761 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
762 initial_src_idx
[j
] = inst
->src
[j
].index
;
766 * scan all the components in the dst writemask
767 * generate an instruction for each of them if required.
772 int i
= u_bit_scan(&writemask
);
774 /* before emitting the instruction, see if we have to adjust store
776 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
777 addr
.file
== PROGRAM_UNDEFINED
) {
778 /* We have to advance the buffer address by 16 */
779 addr
= get_temp(glsl_type::uint_type
);
780 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
781 inst
->src
[0], st_src_reg_for_int(16));
785 /* first time use previous instruction */
789 /* create a new instructions for subsequent attempts */
790 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
795 this->instructions
.push_tail(dinst
);
797 /* modify the destination if we are splitting */
798 for (j
= 0; j
< 2; j
++) {
799 if (dst_is_double
[j
]) {
800 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
801 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
803 if (dinst
->op
== TGSI_OPCODE_STORE
) {
804 dinst
->src
[0] = addr
;
806 dinst
->dst
[j
].index
++;
810 /* if we aren't writing to a double, just get the bit of the initial writemask
812 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
816 /* modify the src registers */
817 for (j
= 0; j
< 4; j
++) {
818 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
820 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
821 dinst
->src
[j
].index
= initial_src_idx
[j
];
823 dinst
->src
[j
].double_reg2
= true;
824 dinst
->src
[j
].index
++;
828 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
830 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
833 /* some opcodes are special case in what they use as sources
834 - F2D is a float src0, DLDEXP is integer src1 */
835 if (op
== TGSI_OPCODE_F2D
||
836 op
== TGSI_OPCODE_DLDEXP
||
837 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
838 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
845 this->instructions
.push_tail(inst
);
852 glsl_to_tgsi_instruction
*
853 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
855 st_src_reg src0
, st_src_reg src1
,
856 st_src_reg src2
, st_src_reg src3
)
858 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
862 * Determines whether to use an integer, unsigned integer, or float opcode
863 * based on the operands and input opcode, then emits the result.
866 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
868 st_src_reg src0
, st_src_reg src1
)
870 int type
= GLSL_TYPE_FLOAT
;
872 if (op
== TGSI_OPCODE_MOV
)
875 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
876 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
877 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
878 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
880 if (is_resource_instruction(op
))
882 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
883 type
= GLSL_TYPE_DOUBLE
;
884 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
885 type
= GLSL_TYPE_FLOAT
;
886 else if (native_integers
)
887 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
889 #define case5(c, f, i, u, d) \
890 case TGSI_OPCODE_##c: \
891 if (type == GLSL_TYPE_DOUBLE) \
892 op = TGSI_OPCODE_##d; \
893 else if (type == GLSL_TYPE_INT) \
894 op = TGSI_OPCODE_##i; \
895 else if (type == GLSL_TYPE_UINT) \
896 op = TGSI_OPCODE_##u; \
898 op = TGSI_OPCODE_##f; \
901 #define case4(c, f, i, u) \
902 case TGSI_OPCODE_##c: \
903 if (type == GLSL_TYPE_INT) \
904 op = TGSI_OPCODE_##i; \
905 else if (type == GLSL_TYPE_UINT) \
906 op = TGSI_OPCODE_##u; \
908 op = TGSI_OPCODE_##f; \
911 #define case3(f, i, u) case4(f, f, i, u)
912 #define case4d(f, i, u, d) case5(f, f, i, u, d)
913 #define case3fid(f, i, d) case5(f, f, i, i, d)
914 #define case2fi(f, i) case4(f, f, i, i)
915 #define case2iu(i, u) case4(i, LAST, i, u)
917 #define casecomp(c, f, i, u, d) \
918 case TGSI_OPCODE_##c: \
919 if (type == GLSL_TYPE_DOUBLE) \
920 op = TGSI_OPCODE_##d; \
921 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
922 op = TGSI_OPCODE_##i; \
923 else if (type == GLSL_TYPE_UINT) \
924 op = TGSI_OPCODE_##u; \
925 else if (native_integers) \
926 op = TGSI_OPCODE_##f; \
928 op = TGSI_OPCODE_##c; \
932 case3fid(ADD
, UADD
, DADD
);
933 case3fid(MUL
, UMUL
, DMUL
);
934 case3fid(MAD
, UMAD
, DMAD
);
935 case3fid(FMA
, UMAD
, DFMA
);
936 case3(DIV
, IDIV
, UDIV
);
937 case4d(MAX
, IMAX
, UMAX
, DMAX
);
938 case4d(MIN
, IMIN
, UMIN
, DMIN
);
941 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
942 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
943 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
944 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
948 case3fid(SSG
, ISSG
, DSSG
);
949 case3fid(ABS
, IABS
, DABS
);
953 case2iu(IMUL_HI
, UMUL_HI
);
955 case3fid(SQRT
, SQRT
, DSQRT
);
957 case3fid(RCP
, RCP
, DRCP
);
958 case3fid(RSQ
, RSQ
, DRSQ
);
960 case3fid(FRC
, FRC
, DFRAC
);
961 case3fid(TRUNC
, TRUNC
, DTRUNC
);
962 case3fid(CEIL
, CEIL
, DCEIL
);
963 case3fid(FLR
, FLR
, DFLR
);
964 case3fid(ROUND
, ROUND
, DROUND
);
966 case2iu(ATOMIMAX
, ATOMUMAX
);
967 case2iu(ATOMIMIN
, ATOMUMIN
);
972 assert(op
!= TGSI_OPCODE_LAST
);
976 glsl_to_tgsi_instruction
*
977 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
978 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
981 static const unsigned dot_opcodes
[] = {
982 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
985 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
989 * Emits TGSI scalar opcodes to produce unique answers across channels.
991 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
992 * channel determines the result across all channels. So to do a vec4
993 * of this operation, we want to emit a scalar per source channel used
994 * to produce dest channels.
997 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
999 st_src_reg orig_src0
, st_src_reg orig_src1
)
1002 int done_mask
= ~dst
.writemask
;
1004 /* TGSI RCP is a scalar operation splatting results to all channels,
1005 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1008 for (i
= 0; i
< 4; i
++) {
1009 GLuint this_mask
= (1 << i
);
1010 st_src_reg src0
= orig_src0
;
1011 st_src_reg src1
= orig_src1
;
1013 if (done_mask
& this_mask
)
1016 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1017 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1018 for (j
= i
+ 1; j
< 4; j
++) {
1019 /* If there is another enabled component in the destination that is
1020 * derived from the same inputs, generate its value on this pass as
1023 if (!(done_mask
& (1 << j
)) &&
1024 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1025 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1026 this_mask
|= (1 << j
);
1029 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1030 src0_swiz
, src0_swiz
);
1031 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1032 src1_swiz
, src1_swiz
);
1034 dst
.writemask
= this_mask
;
1035 emit_asm(ir
, op
, dst
, src0
, src1
);
1036 done_mask
|= this_mask
;
1041 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1042 st_dst_reg dst
, st_src_reg src0
)
1044 st_src_reg undef
= undef_src
;
1046 undef
.swizzle
= SWIZZLE_XXXX
;
1048 emit_scalar(ir
, op
, dst
, src0
, undef
);
1052 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1053 st_dst_reg dst
, st_src_reg src0
)
1055 int op
= TGSI_OPCODE_ARL
;
1057 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1058 op
= TGSI_OPCODE_UARL
;
1060 assert(dst
.file
== PROGRAM_ADDRESS
);
1061 if (dst
.index
>= this->num_address_regs
)
1062 this->num_address_regs
= dst
.index
+ 1;
1064 emit_asm(NULL
, op
, dst
, src0
);
1068 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1069 gl_constant_value values
[8], int size
, int datatype
,
1070 GLuint
*swizzle_out
)
1072 if (file
== PROGRAM_CONSTANT
) {
1073 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1074 size
, datatype
, swizzle_out
);
1077 assert(file
== PROGRAM_IMMEDIATE
);
1080 immediate_storage
*entry
;
1081 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1084 /* Search immediate storage to see if we already have an identical
1085 * immediate that we can use instead of adding a duplicate entry.
1087 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1088 immediate_storage
*tmp
= entry
;
1090 for (i
= 0; i
* 4 < size32
; i
++) {
1091 int slot_size
= MIN2(size32
- (i
* 4), 4);
1092 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1094 if (memcmp(tmp
->values
, &values
[i
* 4],
1095 slot_size
* sizeof(gl_constant_value
)))
1098 /* Everything matches, keep going until the full size is matched */
1099 tmp
= (immediate_storage
*)tmp
->next
;
1102 /* The full value matched */
1103 if (i
* 4 >= size32
)
1109 for (i
= 0; i
* 4 < size32
; i
++) {
1110 int slot_size
= MIN2(size32
- (i
* 4), 4);
1111 /* Add this immediate to the list. */
1112 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1113 this->immediates
.push_tail(entry
);
1114 this->num_immediates
++;
1120 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1122 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1123 union gl_constant_value uval
;
1126 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1132 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1134 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1135 union gl_constant_value uval
[2];
1137 uval
[0].u
= *(uint32_t *)&val
;
1138 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1139 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1145 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1147 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1148 union gl_constant_value uval
;
1150 assert(native_integers
);
1153 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1159 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1161 if (native_integers
)
1162 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1163 st_src_reg_for_int(val
);
1165 return st_src_reg_for_float(val
);
1169 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1174 switch (type
->base_type
) {
1175 case GLSL_TYPE_UINT
:
1177 case GLSL_TYPE_FLOAT
:
1178 case GLSL_TYPE_BOOL
:
1179 if (type
->is_matrix()) {
1180 return type
->matrix_columns
;
1182 /* Regardless of size of vector, it gets a vec4. This is bad
1183 * packing for things like floats, but otherwise arrays become a
1184 * mess. Hopefully a later pass over the code can pack scalars
1185 * down if appropriate.
1190 case GLSL_TYPE_DOUBLE
:
1191 if (type
->is_matrix()) {
1192 if (type
->vector_elements
<= 2 || is_vs_input
)
1193 return type
->matrix_columns
;
1195 return type
->matrix_columns
* 2;
1197 /* For doubles if we have a double or dvec2 they fit in one
1198 * vec4, else they need 2 vec4s.
1200 if (type
->vector_elements
<= 2 || is_vs_input
)
1206 case GLSL_TYPE_ARRAY
:
1207 assert(type
->length
> 0);
1208 return attrib_type_size(type
->fields
.array
, is_vs_input
) * type
->length
;
1209 case GLSL_TYPE_STRUCT
:
1211 for (i
= 0; i
< type
->length
; i
++) {
1212 size
+= attrib_type_size(type
->fields
.structure
[i
].type
, is_vs_input
);
1215 case GLSL_TYPE_SAMPLER
:
1216 case GLSL_TYPE_IMAGE
:
1217 case GLSL_TYPE_SUBROUTINE
:
1218 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1222 case GLSL_TYPE_ATOMIC_UINT
:
1223 case GLSL_TYPE_INTERFACE
:
1224 case GLSL_TYPE_VOID
:
1225 case GLSL_TYPE_ERROR
:
1226 case GLSL_TYPE_FUNCTION
:
1227 assert(!"Invalid type in type_size");
1234 type_size(const struct glsl_type
*type
)
1236 return attrib_type_size(type
, false);
1240 * If the given GLSL type is an array or matrix or a structure containing
1241 * an array/matrix member, return true. Else return false.
1243 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1244 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1245 * we have an array that might be indexed with a variable, we need to use
1246 * the later storage type.
1249 type_has_array_or_matrix(const glsl_type
*type
)
1251 if (type
->is_array() || type
->is_matrix())
1254 if (type
->is_record()) {
1255 for (unsigned i
= 0; i
< type
->length
; i
++) {
1256 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1267 * In the initial pass of codegen, we assign temporary numbers to
1268 * intermediate results. (not SSA -- variable assignments will reuse
1272 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1276 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1280 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1281 if (next_array
>= max_num_arrays
) {
1282 max_num_arrays
+= 32;
1283 array_sizes
= (unsigned*)
1284 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1287 src
.file
= PROGRAM_ARRAY
;
1288 src
.index
= next_array
<< 16 | 0x8000;
1289 array_sizes
[next_array
] = type_size(type
);
1293 src
.file
= PROGRAM_TEMPORARY
;
1294 src
.index
= next_temp
;
1295 next_temp
+= type_size(type
);
1298 if (type
->is_array() || type
->is_record()) {
1299 src
.swizzle
= SWIZZLE_NOOP
;
1301 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1308 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1311 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1312 if (entry
->var
== var
)
1320 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1322 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1323 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1325 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1326 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1329 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1331 const ir_state_slot
*const slots
= ir
->get_state_slots();
1332 assert(slots
!= NULL
);
1334 /* Check if this statevar's setup in the STATE file exactly
1335 * matches how we'll want to reference it as a
1336 * struct/array/whatever. If not, then we need to move it into
1337 * temporary storage and hope that it'll get copy-propagated
1340 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1341 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1346 variable_storage
*storage
;
1348 if (i
== ir
->get_num_state_slots()) {
1349 /* We'll set the index later. */
1350 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1351 this->variables
.push_tail(storage
);
1355 /* The variable_storage constructor allocates slots based on the size
1356 * of the type. However, this had better match the number of state
1357 * elements that we're going to copy into the new temporary.
1359 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1361 dst
= st_dst_reg(get_temp(ir
->type
));
1363 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1365 this->variables
.push_tail(storage
);
1369 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1370 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1371 (gl_state_index
*)slots
[i
].tokens
);
1373 if (storage
->file
== PROGRAM_STATE_VAR
) {
1374 if (storage
->index
== -1) {
1375 storage
->index
= index
;
1377 assert(index
== storage
->index
+ (int)i
);
1380 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1381 * the data being moved since MOV does not care about the type of
1382 * data it is moving, and we don't want to declare registers with
1383 * array or struct types.
1385 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1386 src
.swizzle
= slots
[i
].swizzle
;
1387 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1388 /* even a float takes up a whole vec4 reg in a struct/array. */
1393 if (storage
->file
== PROGRAM_TEMPORARY
&&
1394 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1395 fail_link(this->shader_program
,
1396 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1397 ir
->name
, dst
.index
- storage
->index
,
1398 type_size(ir
->type
));
1404 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1406 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1408 visit_exec_list(&ir
->body_instructions
, this);
1410 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1414 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1417 case ir_loop_jump::jump_break
:
1418 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1420 case ir_loop_jump::jump_continue
:
1421 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1428 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1435 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1437 /* Ignore function bodies other than main() -- we shouldn't see calls to
1438 * them since they should all be inlined before we get to glsl_to_tgsi.
1440 if (strcmp(ir
->name
, "main") == 0) {
1441 const ir_function_signature
*sig
;
1444 sig
= ir
->matching_signature(NULL
, &empty
, false);
1448 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1455 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1457 int nonmul_operand
= 1 - mul_operand
;
1459 st_dst_reg result_dst
;
1461 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1462 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1465 expr
->operands
[0]->accept(this);
1467 expr
->operands
[1]->accept(this);
1469 ir
->operands
[nonmul_operand
]->accept(this);
1472 this->result
= get_temp(ir
->type
);
1473 result_dst
= st_dst_reg(this->result
);
1474 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1475 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1481 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1483 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1484 * implemented using multiplication, and logical-or is implemented using
1485 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1486 * As result, the logical expression (a & !b) can be rewritten as:
1490 * - (a * 1) - (a * b)
1494 * This final expression can be implemented as a single MAD(a, -b, a)
1498 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1500 const int other_operand
= 1 - try_operand
;
1503 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1504 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1507 ir
->operands
[other_operand
]->accept(this);
1509 expr
->operands
[0]->accept(this);
1512 b
.negate
= ~b
.negate
;
1514 this->result
= get_temp(ir
->type
);
1515 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1521 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1522 st_src_reg
*reg
, int *num_reladdr
)
1524 if (!reg
->reladdr
&& !reg
->reladdr2
)
1527 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1528 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1530 if (*num_reladdr
!= 1) {
1531 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1533 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1541 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1543 unsigned int operand
;
1544 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1545 st_src_reg result_src
;
1546 st_dst_reg result_dst
;
1548 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1550 if (ir
->operation
== ir_binop_add
) {
1551 if (try_emit_mad(ir
, 1))
1553 if (try_emit_mad(ir
, 0))
1557 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1559 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1560 if (try_emit_mad_for_and_not(ir
, 1))
1562 if (try_emit_mad_for_and_not(ir
, 0))
1566 if (ir
->operation
== ir_quadop_vector
)
1567 assert(!"ir_quadop_vector should have been lowered");
1569 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1570 this->result
.file
= PROGRAM_UNDEFINED
;
1571 ir
->operands
[operand
]->accept(this);
1572 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1573 printf("Failed to get tree for expression operand:\n");
1574 ir
->operands
[operand
]->print();
1578 op
[operand
] = this->result
;
1580 /* Matrix expression operands should have been broken down to vector
1581 * operations already.
1583 assert(!ir
->operands
[operand
]->type
->is_matrix());
1586 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1587 if (ir
->operands
[1]) {
1588 vector_elements
= MAX2(vector_elements
,
1589 ir
->operands
[1]->type
->vector_elements
);
1592 this->result
.file
= PROGRAM_UNDEFINED
;
1594 /* Storage for our result. Ideally for an assignment we'd be using
1595 * the actual storage for the result here, instead.
1597 result_src
= get_temp(ir
->type
);
1598 /* convenience for the emit functions below. */
1599 result_dst
= st_dst_reg(result_src
);
1600 /* Limit writes to the channels that will be used by result_src later.
1601 * This does limit this temp's use as a temporary for multi-instruction
1604 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1606 switch (ir
->operation
) {
1607 case ir_unop_logic_not
:
1608 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1609 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1611 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1612 * older GPUs implement SEQ using multiple instructions (i915 uses two
1613 * SGE instructions and a MUL instruction). Since our logic values are
1614 * 0.0 and 1.0, 1-x also implements !x.
1616 op
[0].negate
= ~op
[0].negate
;
1617 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1621 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1622 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1623 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1624 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1626 op
[0].negate
= ~op
[0].negate
;
1630 case ir_unop_subroutine_to_int
:
1631 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1634 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1637 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1640 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1644 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1648 assert(!"not reached: should be handled by ir_explog_to_explog2");
1651 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1654 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1657 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1659 case ir_unop_saturate
: {
1660 glsl_to_tgsi_instruction
*inst
;
1661 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1662 inst
->saturate
= true;
1667 case ir_unop_dFdx_coarse
:
1668 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1670 case ir_unop_dFdx_fine
:
1671 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1674 case ir_unop_dFdy_coarse
:
1675 case ir_unop_dFdy_fine
:
1677 /* The X component contains 1 or -1 depending on whether the framebuffer
1678 * is a FBO or the window system buffer, respectively.
1679 * It is then multiplied with the source operand of DDY.
1681 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1682 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1684 unsigned transform_y_index
=
1685 _mesa_add_state_reference(this->prog
->Parameters
,
1688 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1690 glsl_type::vec4_type
);
1691 transform_y
.swizzle
= SWIZZLE_XXXX
;
1693 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1695 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1696 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1697 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1701 case ir_unop_frexp_sig
:
1702 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1705 case ir_unop_frexp_exp
:
1706 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1709 case ir_unop_noise
: {
1710 /* At some point, a motivated person could add a better
1711 * implementation of noise. Currently not even the nvidia
1712 * binary drivers do anything more than this. In any case, the
1713 * place to do this is in the GL state tracker, not the poor
1716 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1721 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1724 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1728 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1731 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1732 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1734 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1737 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1738 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1740 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1744 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1746 case ir_binop_greater
:
1747 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1749 case ir_binop_lequal
:
1750 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1752 case ir_binop_gequal
:
1753 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1755 case ir_binop_equal
:
1756 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1758 case ir_binop_nequal
:
1759 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_all_equal
:
1762 /* "==" operator producing a scalar boolean. */
1763 if (ir
->operands
[0]->type
->is_vector() ||
1764 ir
->operands
[1]->type
->is_vector()) {
1765 st_src_reg temp
= get_temp(native_integers
?
1766 glsl_type::uvec4_type
:
1767 glsl_type::vec4_type
);
1769 if (native_integers
) {
1770 st_dst_reg temp_dst
= st_dst_reg(temp
);
1771 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1773 if (ir
->operands
[0]->type
->is_boolean() &&
1774 ir
->operands
[1]->as_constant() &&
1775 ir
->operands
[1]->as_constant()->is_one()) {
1776 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1778 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1781 /* Emit 1-3 AND operations to combine the SEQ results. */
1782 switch (ir
->operands
[0]->type
->vector_elements
) {
1786 temp_dst
.writemask
= WRITEMASK_Y
;
1787 temp1
.swizzle
= SWIZZLE_YYYY
;
1788 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1789 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1792 temp_dst
.writemask
= WRITEMASK_X
;
1793 temp1
.swizzle
= SWIZZLE_XXXX
;
1794 temp2
.swizzle
= SWIZZLE_YYYY
;
1795 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1796 temp_dst
.writemask
= WRITEMASK_Y
;
1797 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1798 temp2
.swizzle
= SWIZZLE_WWWW
;
1799 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1802 temp1
.swizzle
= SWIZZLE_XXXX
;
1803 temp2
.swizzle
= SWIZZLE_YYYY
;
1804 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1806 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1808 /* After the dot-product, the value will be an integer on the
1809 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1811 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1813 /* Negating the result of the dot-product gives values on the range
1814 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1815 * This is achieved using SGE.
1817 st_src_reg sge_src
= result_src
;
1818 sge_src
.negate
= ~sge_src
.negate
;
1819 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1822 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1825 case ir_binop_any_nequal
:
1826 /* "!=" operator producing a scalar boolean. */
1827 if (ir
->operands
[0]->type
->is_vector() ||
1828 ir
->operands
[1]->type
->is_vector()) {
1829 st_src_reg temp
= get_temp(native_integers
?
1830 glsl_type::uvec4_type
:
1831 glsl_type::vec4_type
);
1832 if (ir
->operands
[0]->type
->is_boolean() &&
1833 ir
->operands
[1]->as_constant() &&
1834 ir
->operands
[1]->as_constant()->is_zero()) {
1835 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1837 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1840 if (native_integers
) {
1841 st_dst_reg temp_dst
= st_dst_reg(temp
);
1842 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1844 /* Emit 1-3 OR operations to combine the SNE results. */
1845 switch (ir
->operands
[0]->type
->vector_elements
) {
1849 temp_dst
.writemask
= WRITEMASK_Y
;
1850 temp1
.swizzle
= SWIZZLE_YYYY
;
1851 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1852 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1855 temp_dst
.writemask
= WRITEMASK_X
;
1856 temp1
.swizzle
= SWIZZLE_XXXX
;
1857 temp2
.swizzle
= SWIZZLE_YYYY
;
1858 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1859 temp_dst
.writemask
= WRITEMASK_Y
;
1860 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1861 temp2
.swizzle
= SWIZZLE_WWWW
;
1862 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1865 temp1
.swizzle
= SWIZZLE_XXXX
;
1866 temp2
.swizzle
= SWIZZLE_YYYY
;
1867 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1869 /* After the dot-product, the value will be an integer on the
1870 * range [0,4]. Zero stays zero, and positive values become 1.0.
1872 glsl_to_tgsi_instruction
*const dp
=
1873 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1874 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1875 /* The clamping to [0,1] can be done for free in the fragment
1876 * shader with a saturate.
1878 dp
->saturate
= true;
1880 /* Negating the result of the dot-product gives values on the range
1881 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1882 * achieved using SLT.
1884 st_src_reg slt_src
= result_src
;
1885 slt_src
.negate
= ~slt_src
.negate
;
1886 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1890 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1894 case ir_binop_logic_xor
:
1895 if (native_integers
)
1896 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1898 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1901 case ir_binop_logic_or
: {
1902 if (native_integers
) {
1903 /* If integers are used as booleans, we can use an actual "or"
1906 assert(native_integers
);
1907 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1909 /* After the addition, the value will be an integer on the
1910 * range [0,2]. Zero stays zero, and positive values become 1.0.
1912 glsl_to_tgsi_instruction
*add
=
1913 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1914 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1915 /* The clamping to [0,1] can be done for free in the fragment
1916 * shader with a saturate if floats are being used as boolean values.
1918 add
->saturate
= true;
1920 /* Negating the result of the addition gives values on the range
1921 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1922 * is achieved using SLT.
1924 st_src_reg slt_src
= result_src
;
1925 slt_src
.negate
= ~slt_src
.negate
;
1926 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1932 case ir_binop_logic_and
:
1933 /* If native integers are disabled, the bool args are stored as float 0.0
1934 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1935 * actual AND opcode.
1937 if (native_integers
)
1938 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1940 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1944 assert(ir
->operands
[0]->type
->is_vector());
1945 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1946 emit_dp(ir
, result_dst
, op
[0], op
[1],
1947 ir
->operands
[0]->type
->vector_elements
);
1952 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1954 /* sqrt(x) = x * rsq(x). */
1955 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1956 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1957 /* For incoming channels <= 0, set the result to 0. */
1958 op
[0].negate
= ~op
[0].negate
;
1959 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1960 op
[0], result_src
, st_src_reg_for_float(0.0));
1964 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1967 if (native_integers
) {
1968 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1971 /* fallthrough to next case otherwise */
1973 if (native_integers
) {
1974 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1977 /* fallthrough to next case otherwise */
1980 /* Converting between signed and unsigned integers is a no-op. */
1984 if (native_integers
) {
1985 /* Booleans are stored as integers using ~0 for true and 0 for false.
1986 * GLSL requires that int(bool) return 1 for true and 0 for false.
1987 * This conversion is done with AND, but it could be done with NEG.
1989 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1991 /* Booleans and integers are both stored as floats when native
1992 * integers are disabled.
1998 if (native_integers
)
1999 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2001 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2004 if (native_integers
)
2005 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2007 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2009 case ir_unop_bitcast_f2i
:
2011 result_src
.type
= GLSL_TYPE_INT
;
2013 case ir_unop_bitcast_f2u
:
2015 result_src
.type
= GLSL_TYPE_UINT
;
2017 case ir_unop_bitcast_i2f
:
2018 case ir_unop_bitcast_u2f
:
2020 result_src
.type
= GLSL_TYPE_FLOAT
;
2023 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2026 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2029 if (native_integers
)
2030 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2032 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2035 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2038 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2041 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2043 case ir_unop_round_even
:
2044 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2047 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2051 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2054 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2057 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2060 case ir_unop_bit_not
:
2061 if (native_integers
) {
2062 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2066 if (native_integers
) {
2067 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2070 case ir_binop_lshift
:
2071 if (native_integers
) {
2072 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2075 case ir_binop_rshift
:
2076 if (native_integers
) {
2077 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2080 case ir_binop_bit_and
:
2081 if (native_integers
) {
2082 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2085 case ir_binop_bit_xor
:
2086 if (native_integers
) {
2087 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2090 case ir_binop_bit_or
:
2091 if (native_integers
) {
2092 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2096 assert(!"GLSL 1.30 features unsupported");
2099 case ir_binop_ubo_load
: {
2100 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2101 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2102 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2103 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2104 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2107 cbuf
.type
= ir
->type
->base_type
;
2108 cbuf
.file
= PROGRAM_CONSTANT
;
2110 cbuf
.reladdr
= NULL
;
2113 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2115 if (const_offset_ir
) {
2116 /* Constant index into constant buffer */
2117 cbuf
.reladdr
= NULL
;
2118 cbuf
.index
= const_offset
/ 16;
2121 /* Relative/variable index into constant buffer */
2122 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2123 st_src_reg_for_int(4));
2124 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2125 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2128 if (const_uniform_block
) {
2129 /* Constant constant buffer */
2130 cbuf
.reladdr2
= NULL
;
2131 cbuf
.index2D
= const_block
;
2132 cbuf
.has_index2
= true;
2135 /* Relative/variable constant buffer */
2136 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2138 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2139 cbuf
.has_index2
= true;
2142 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2143 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2144 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2145 const_offset
% 16 / 8,
2146 const_offset
% 16 / 8,
2147 const_offset
% 16 / 8);
2149 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2150 const_offset
% 16 / 4,
2151 const_offset
% 16 / 4,
2152 const_offset
% 16 / 4);
2154 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2155 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2157 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2162 /* note: we have to reorder the three args here */
2163 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2166 if (this->ctx
->Const
.NativeIntegers
)
2167 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2169 op
[0].negate
= ~op
[0].negate
;
2170 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2173 case ir_triop_bitfield_extract
:
2174 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2176 case ir_quadop_bitfield_insert
:
2177 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2179 case ir_unop_bitfield_reverse
:
2180 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2182 case ir_unop_bit_count
:
2183 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2185 case ir_unop_find_msb
:
2186 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2188 case ir_unop_find_lsb
:
2189 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2191 case ir_binop_imul_high
:
2192 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2195 /* In theory, MAD is incorrect here. */
2197 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2199 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2201 case ir_unop_interpolate_at_centroid
:
2202 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2204 case ir_binop_interpolate_at_offset
:
2205 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2207 case ir_binop_interpolate_at_sample
:
2208 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2212 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2215 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2218 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2221 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2224 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2227 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2229 case ir_unop_unpack_double_2x32
:
2230 case ir_unop_pack_double_2x32
:
2231 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2234 case ir_binop_ldexp
:
2235 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2236 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2238 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2242 case ir_unop_pack_half_2x16
:
2243 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2245 case ir_unop_unpack_half_2x16
:
2246 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2249 case ir_unop_get_buffer_size
: {
2250 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2253 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2254 (const_offset
? const_offset
->value
.u
[0] : 0),
2256 if (!const_offset
) {
2257 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2258 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
2259 emit_arl(ir
, sampler_reladdr
, op
[0]);
2261 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2265 case ir_unop_pack_snorm_2x16
:
2266 case ir_unop_pack_unorm_2x16
:
2267 case ir_unop_pack_snorm_4x8
:
2268 case ir_unop_pack_unorm_4x8
:
2270 case ir_unop_unpack_snorm_2x16
:
2271 case ir_unop_unpack_unorm_2x16
:
2272 case ir_unop_unpack_snorm_4x8
:
2273 case ir_unop_unpack_unorm_4x8
:
2275 case ir_quadop_vector
:
2276 case ir_binop_vector_extract
:
2277 case ir_triop_vector_insert
:
2278 case ir_binop_carry
:
2279 case ir_binop_borrow
:
2280 case ir_unop_ssbo_unsized_array_length
:
2281 /* This operation is not supported, or should have already been handled.
2283 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2287 this->result
= result_src
;
2292 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2298 /* Note that this is only swizzles in expressions, not those on the left
2299 * hand side of an assignment, which do write masking. See ir_assignment
2303 ir
->val
->accept(this);
2305 assert(src
.file
!= PROGRAM_UNDEFINED
);
2306 assert(ir
->type
->vector_elements
> 0);
2308 for (i
= 0; i
< 4; i
++) {
2309 if (i
< ir
->type
->vector_elements
) {
2312 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2315 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2318 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2321 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2325 /* If the type is smaller than a vec4, replicate the last
2328 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2332 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2337 /* Test if the variable is an array. Note that geometry and
2338 * tessellation shader inputs are outputs are always arrays (except
2339 * for patch inputs), so only the array element type is considered.
2342 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2344 const glsl_type
*type
= var
->type
;
2346 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2347 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2352 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2353 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2354 stage
== MESA_SHADER_TESS_CTRL
) &&
2356 if (!var
->type
->is_array())
2357 return false; /* a system value probably */
2359 type
= var
->type
->fields
.array
;
2363 return type
->is_array() || type
->is_matrix();
2367 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2369 variable_storage
*entry
= find_variable_storage(ir
->var
);
2370 ir_variable
*var
= ir
->var
;
2374 switch (var
->data
.mode
) {
2375 case ir_var_uniform
:
2376 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2377 var
->data
.param_index
);
2378 this->variables
.push_tail(entry
);
2380 case ir_var_shader_in
:
2381 /* The linker assigns locations for varyings and attributes,
2382 * including deprecated builtins (like gl_Color), user-assign
2383 * generic attributes (glBindVertexLocation), and
2384 * user-defined varyings.
2386 assert(var
->data
.location
!= -1);
2388 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2389 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2391 decl
->mesa_index
= var
->data
.location
;
2392 decl
->array_id
= num_input_arrays
+ 1;
2394 decl
->array_size
= type_size(var
->type
->fields
.array
);
2395 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2397 decl
->array_size
= type_size(var
->type
);
2398 decl
->array_type
= var
->type
->without_array()->base_type
;
2402 entry
= new(mem_ctx
) variable_storage(var
,
2408 entry
= new(mem_ctx
) variable_storage(var
,
2410 var
->data
.location
);
2412 this->variables
.push_tail(entry
);
2414 case ir_var_shader_out
:
2415 assert(var
->data
.location
!= -1);
2417 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2418 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2420 decl
->mesa_index
= var
->data
.location
;
2421 decl
->array_id
= num_output_arrays
+ 1;
2423 decl
->array_size
= type_size(var
->type
->fields
.array
);
2424 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2426 decl
->array_size
= type_size(var
->type
);
2427 decl
->array_type
= var
->type
->without_array()->base_type
;
2429 num_output_arrays
++;
2431 entry
= new(mem_ctx
) variable_storage(var
,
2437 entry
= new(mem_ctx
) variable_storage(var
,
2442 this->variables
.push_tail(entry
);
2444 case ir_var_system_value
:
2445 entry
= new(mem_ctx
) variable_storage(var
,
2446 PROGRAM_SYSTEM_VALUE
,
2447 var
->data
.location
);
2450 case ir_var_temporary
:
2451 st_src_reg src
= get_temp(var
->type
);
2453 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2454 this->variables
.push_tail(entry
);
2460 printf("Failed to make storage for %s\n", var
->name
);
2465 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2466 this->result
.array_id
= entry
->array_id
;
2467 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2468 this->result
.is_double_vertex_input
= true;
2469 if (!native_integers
)
2470 this->result
.type
= GLSL_TYPE_FLOAT
;
2474 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2475 GLbitfield64 usage_mask
,
2476 GLbitfield64 double_usage_mask
,
2477 GLbitfield patch_usage_mask
)
2481 /* Fix array declarations by removing unused array elements at both ends
2482 * of the arrays. For example, mat4[3] where only mat[1] is used.
2484 for (i
= 0; i
< count
; i
++) {
2485 struct array_decl
*decl
= &arrays
[i
];
2487 /* Shrink the beginning. */
2488 for (j
= 0; j
< decl
->array_size
; j
++) {
2489 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2490 if (patch_usage_mask
&
2491 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2495 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2497 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2506 /* Shrink the end. */
2507 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2508 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2509 if (patch_usage_mask
&
2510 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2514 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2516 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2526 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2530 int element_size
= type_size(ir
->type
);
2533 index
= ir
->array_index
->constant_expression_value();
2535 ir
->array
->accept(this);
2538 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2539 switch (this->prog
->Target
) {
2540 case GL_TESS_CONTROL_PROGRAM_NV
:
2541 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2542 !ir
->variable_referenced()->data
.patch
;
2544 case GL_TESS_EVALUATION_PROGRAM_NV
:
2545 is_2D
= src
.file
== PROGRAM_INPUT
&&
2546 !ir
->variable_referenced()->data
.patch
;
2548 case GL_GEOMETRY_PROGRAM_NV
:
2549 is_2D
= src
.file
== PROGRAM_INPUT
;
2559 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2560 src
.file
== PROGRAM_INPUT
)
2561 element_size
= attrib_type_size(ir
->type
, true);
2563 src
.index2D
= index
->value
.i
[0];
2564 src
.has_index2
= true;
2566 src
.index
+= index
->value
.i
[0] * element_size
;
2568 /* Variable index array dereference. It eats the "vec4" of the
2569 * base of the array and an index that offsets the TGSI register
2572 ir
->array_index
->accept(this);
2574 st_src_reg index_reg
;
2576 if (element_size
== 1) {
2577 index_reg
= this->result
;
2579 index_reg
= get_temp(native_integers
?
2580 glsl_type::int_type
: glsl_type::float_type
);
2582 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2583 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2586 /* If there was already a relative address register involved, add the
2587 * new and the old together to get the new offset.
2589 if (!is_2D
&& src
.reladdr
!= NULL
) {
2590 st_src_reg accum_reg
= get_temp(native_integers
?
2591 glsl_type::int_type
: glsl_type::float_type
);
2593 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2594 index_reg
, *src
.reladdr
);
2596 index_reg
= accum_reg
;
2600 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2601 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2603 src
.has_index2
= true;
2605 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2606 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2610 /* If the type is smaller than a vec4, replicate the last channel out. */
2611 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2612 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2614 src
.swizzle
= SWIZZLE_NOOP
;
2616 /* Change the register type to the element type of the array. */
2617 src
.type
= ir
->type
->base_type
;
2623 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2626 const glsl_type
*struct_type
= ir
->record
->type
;
2629 ir
->record
->accept(this);
2631 for (i
= 0; i
< struct_type
->length
; i
++) {
2632 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2634 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2637 /* If the type is smaller than a vec4, replicate the last channel out. */
2638 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2639 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2641 this->result
.swizzle
= SWIZZLE_NOOP
;
2643 this->result
.index
+= offset
;
2644 this->result
.type
= ir
->type
->base_type
;
2648 * We want to be careful in assignment setup to hit the actual storage
2649 * instead of potentially using a temporary like we might with the
2650 * ir_dereference handler.
2653 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2655 /* The LHS must be a dereference. If the LHS is a variable indexed array
2656 * access of a vector, it must be separated into a series conditional moves
2657 * before reaching this point (see ir_vec_index_to_cond_assign).
2659 assert(ir
->as_dereference());
2660 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2662 assert(!deref_array
->array
->type
->is_vector());
2665 /* Use the rvalue deref handler for the most part. We'll ignore
2666 * swizzles in it and write swizzles using writemask, though.
2669 return st_dst_reg(v
->result
);
2673 * Process the condition of a conditional assignment
2675 * Examines the condition of a conditional assignment to generate the optimal
2676 * first operand of a \c CMP instruction. If the condition is a relational
2677 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2678 * used as the source for the \c CMP instruction. Otherwise the comparison
2679 * is processed to a boolean result, and the boolean result is used as the
2680 * operand to the CMP instruction.
2683 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2685 ir_rvalue
*src_ir
= ir
;
2687 bool switch_order
= false;
2689 ir_expression
*const expr
= ir
->as_expression();
2691 if (native_integers
) {
2692 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2693 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2694 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2695 type
== GLSL_TYPE_BOOL
) {
2696 if (expr
->operation
== ir_binop_equal
) {
2697 if (expr
->operands
[0]->is_zero()) {
2698 src_ir
= expr
->operands
[1];
2699 switch_order
= true;
2701 else if (expr
->operands
[1]->is_zero()) {
2702 src_ir
= expr
->operands
[0];
2703 switch_order
= true;
2706 else if (expr
->operation
== ir_binop_nequal
) {
2707 if (expr
->operands
[0]->is_zero()) {
2708 src_ir
= expr
->operands
[1];
2710 else if (expr
->operands
[1]->is_zero()) {
2711 src_ir
= expr
->operands
[0];
2717 src_ir
->accept(this);
2718 return switch_order
;
2721 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2722 bool zero_on_left
= false;
2724 if (expr
->operands
[0]->is_zero()) {
2725 src_ir
= expr
->operands
[1];
2726 zero_on_left
= true;
2727 } else if (expr
->operands
[1]->is_zero()) {
2728 src_ir
= expr
->operands
[0];
2729 zero_on_left
= false;
2733 * (a < 0) T F F ( a < 0) T F F
2734 * (0 < a) F F T (-a < 0) F F T
2735 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2736 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2737 * (a > 0) F F T (-a < 0) F F T
2738 * (0 > a) T F F ( a < 0) T F F
2739 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2740 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2742 * Note that exchanging the order of 0 and 'a' in the comparison simply
2743 * means that the value of 'a' should be negated.
2746 switch (expr
->operation
) {
2748 switch_order
= false;
2749 negate
= zero_on_left
;
2752 case ir_binop_greater
:
2753 switch_order
= false;
2754 negate
= !zero_on_left
;
2757 case ir_binop_lequal
:
2758 switch_order
= true;
2759 negate
= !zero_on_left
;
2762 case ir_binop_gequal
:
2763 switch_order
= true;
2764 negate
= zero_on_left
;
2768 /* This isn't the right kind of comparison afterall, so make sure
2769 * the whole condition is visited.
2777 src_ir
->accept(this);
2779 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2780 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2781 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2782 * computing the condition.
2785 this->result
.negate
= ~this->result
.negate
;
2787 return switch_order
;
2791 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2792 st_dst_reg
*l
, st_src_reg
*r
,
2793 st_src_reg
*cond
, bool cond_swap
)
2795 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2796 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2797 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2803 if (type
->is_array()) {
2804 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2805 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2810 if (type
->is_matrix()) {
2811 const struct glsl_type
*vec_type
;
2813 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2814 type
->vector_elements
, 1);
2816 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2817 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2822 assert(type
->is_scalar() || type
->is_vector());
2824 r
->type
= type
->base_type
;
2826 st_src_reg l_src
= st_src_reg(*l
);
2827 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2829 if (native_integers
) {
2830 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2831 cond_swap
? l_src
: *r
,
2832 cond_swap
? *r
: l_src
);
2834 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2835 cond_swap
? l_src
: *r
,
2836 cond_swap
? *r
: l_src
);
2839 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2843 if (type
->is_dual_slot_double()) {
2845 if (r
->is_double_vertex_input
== false)
2851 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2856 ir
->rhs
->accept(this);
2859 l
= get_assignment_lhs(ir
->lhs
, this);
2861 /* FINISHME: This should really set to the correct maximal writemask for each
2862 * FINISHME: component written (in the loops below). This case can only
2863 * FINISHME: occur for matrices, arrays, and structures.
2865 if (ir
->write_mask
== 0) {
2866 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2868 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2869 if (ir
->lhs
->type
->without_array()->is_double()) {
2870 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2872 l
.writemask
= WRITEMASK_X
;
2875 l
.writemask
= WRITEMASK_XY
;
2878 l
.writemask
= WRITEMASK_XYZ
;
2881 l
.writemask
= WRITEMASK_XYZW
;
2885 l
.writemask
= WRITEMASK_XYZW
;
2887 } else if (ir
->lhs
->type
->is_scalar() &&
2888 !ir
->lhs
->type
->is_double() &&
2889 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2890 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2891 * FINISHME: W component of fragment shader output zero, work correctly.
2893 l
.writemask
= WRITEMASK_XYZW
;
2896 int first_enabled_chan
= 0;
2899 l
.writemask
= ir
->write_mask
;
2901 for (int i
= 0; i
< 4; i
++) {
2902 if (l
.writemask
& (1 << i
)) {
2903 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2908 /* Swizzle a small RHS vector into the channels being written.
2910 * glsl ir treats write_mask as dictating how many channels are
2911 * present on the RHS while TGSI treats write_mask as just
2912 * showing which channels of the vec4 RHS get written.
2914 for (int i
= 0; i
< 4; i
++) {
2915 if (l
.writemask
& (1 << i
))
2916 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2918 swizzles
[i
] = first_enabled_chan
;
2920 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2921 swizzles
[2], swizzles
[3]);
2924 assert(l
.file
!= PROGRAM_UNDEFINED
);
2925 assert(r
.file
!= PROGRAM_UNDEFINED
);
2927 if (ir
->condition
) {
2928 const bool switch_order
= this->process_move_condition(ir
->condition
);
2929 st_src_reg condition
= this->result
;
2931 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2932 } else if (ir
->rhs
->as_expression() &&
2933 this->instructions
.get_tail() &&
2934 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2935 type_size(ir
->lhs
->type
) == 1 &&
2936 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2937 /* To avoid emitting an extra MOV when assigning an expression to a
2938 * variable, emit the last instruction of the expression again, but
2939 * replace the destination register with the target of the assignment.
2940 * Dead code elimination will remove the original instruction.
2942 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2943 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2944 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2945 new_inst
->saturate
= inst
->saturate
;
2946 inst
->dead_mask
= inst
->dst
[0].writemask
;
2948 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2954 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2957 GLdouble stack_vals
[4] = { 0 };
2958 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2959 GLenum gl_type
= GL_NONE
;
2961 static int in_array
= 0;
2962 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2964 /* Unfortunately, 4 floats is all we can get into
2965 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2966 * aggregate constant and move each constant value into it. If we
2967 * get lucky, copy propagation will eliminate the extra moves.
2969 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2970 st_src_reg temp_base
= get_temp(ir
->type
);
2971 st_dst_reg temp
= st_dst_reg(temp_base
);
2973 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2974 int size
= type_size(field_value
->type
);
2978 field_value
->accept(this);
2981 for (i
= 0; i
< (unsigned int)size
; i
++) {
2982 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2988 this->result
= temp_base
;
2992 if (ir
->type
->is_array()) {
2993 st_src_reg temp_base
= get_temp(ir
->type
);
2994 st_dst_reg temp
= st_dst_reg(temp_base
);
2995 int size
= type_size(ir
->type
->fields
.array
);
3000 for (i
= 0; i
< ir
->type
->length
; i
++) {
3001 ir
->array_elements
[i
]->accept(this);
3003 for (int j
= 0; j
< size
; j
++) {
3004 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3010 this->result
= temp_base
;
3015 if (ir
->type
->is_matrix()) {
3016 st_src_reg mat
= get_temp(ir
->type
);
3017 st_dst_reg mat_column
= st_dst_reg(mat
);
3019 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3020 switch (ir
->type
->base_type
) {
3021 case GLSL_TYPE_FLOAT
:
3022 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3024 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3025 src
.index
= add_constant(file
,
3027 ir
->type
->vector_elements
,
3030 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3032 case GLSL_TYPE_DOUBLE
:
3033 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3034 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3035 src
.index
= add_constant(file
,
3037 ir
->type
->vector_elements
,
3040 if (ir
->type
->vector_elements
>= 2) {
3041 mat_column
.writemask
= WRITEMASK_XY
;
3042 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3043 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3045 mat_column
.writemask
= WRITEMASK_X
;
3046 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3047 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3050 if (ir
->type
->vector_elements
> 2) {
3051 if (ir
->type
->vector_elements
== 4) {
3052 mat_column
.writemask
= WRITEMASK_ZW
;
3053 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3054 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3056 mat_column
.writemask
= WRITEMASK_Z
;
3057 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3058 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3059 mat_column
.writemask
= WRITEMASK_XYZW
;
3060 src
.swizzle
= SWIZZLE_XYZW
;
3066 unreachable("Illegal matrix constant type.\n");
3075 switch (ir
->type
->base_type
) {
3076 case GLSL_TYPE_FLOAT
:
3078 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3079 values
[i
].f
= ir
->value
.f
[i
];
3082 case GLSL_TYPE_DOUBLE
:
3083 gl_type
= GL_DOUBLE
;
3084 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3085 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3086 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3089 case GLSL_TYPE_UINT
:
3090 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3091 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3092 if (native_integers
)
3093 values
[i
].u
= ir
->value
.u
[i
];
3095 values
[i
].f
= ir
->value
.u
[i
];
3099 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3100 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3101 if (native_integers
)
3102 values
[i
].i
= ir
->value
.i
[i
];
3104 values
[i
].f
= ir
->value
.i
[i
];
3107 case GLSL_TYPE_BOOL
:
3108 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3109 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3110 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3114 assert(!"Non-float/uint/int/bool constant");
3117 this->result
= st_src_reg(file
, -1, ir
->type
);
3118 this->result
.index
= add_constant(file
,
3120 ir
->type
->vector_elements
,
3122 &this->result
.swizzle
);
3126 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3128 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3129 if (entry
->sig
== sig
)
3133 entry
= ralloc(mem_ctx
, function_entry
);
3135 entry
->sig_id
= this->next_signature_id
++;
3136 entry
->bgn_inst
= NULL
;
3138 /* Allocate storage for all the parameters. */
3139 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3140 variable_storage
*storage
;
3142 storage
= find_variable_storage(param
);
3145 st_src_reg src
= get_temp(param
->type
);
3147 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3148 this->variables
.push_tail(storage
);
3151 if (!sig
->return_type
->is_void()) {
3152 entry
->return_reg
= get_temp(sig
->return_type
);
3154 entry
->return_reg
= undef_src
;
3157 this->function_signatures
.push_tail(entry
);
3162 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3164 const char *callee
= ir
->callee
->function_name();
3165 ir_dereference
*deref
= static_cast<ir_dereference
*>(
3166 ir
->actual_parameters
.get_head());
3167 ir_variable
*location
= deref
->variable_referenced();
3170 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3172 /* Calculate the surface offset */
3174 unsigned array_size
= 0, base
= 0, index
= 0;
3176 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
);
3178 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3179 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3180 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3181 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3182 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3184 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3187 ir
->return_deref
->accept(this);
3188 st_dst_reg
dst(this->result
);
3189 dst
.writemask
= WRITEMASK_X
;
3191 glsl_to_tgsi_instruction
*inst
;
3193 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3194 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3195 inst
->buffer
= buffer
;
3196 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3197 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3198 st_src_reg_for_int(1));
3199 inst
->buffer
= buffer
;
3200 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3201 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3202 st_src_reg_for_int(-1));
3203 inst
->buffer
= buffer
;
3204 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3209 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3211 const char *callee
= ir
->callee
->function_name();
3212 exec_node
*param
= ir
->actual_parameters
.get_head();
3214 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3216 param
= param
->get_next();
3217 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3219 ir_constant
*const_block
= block
->as_constant();
3223 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3224 (const_block
? const_block
->value
.u
[0] : 0),
3228 block
->accept(this);
3229 emit_arl(ir
, sampler_reladdr
, this->result
);
3230 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3231 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3234 /* Calculate the surface offset */
3235 offset
->accept(this);
3236 st_src_reg off
= this->result
;
3238 st_dst_reg dst
= undef_dst
;
3239 if (ir
->return_deref
) {
3240 ir
->return_deref
->accept(this);
3241 dst
= st_dst_reg(this->result
);
3242 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3245 glsl_to_tgsi_instruction
*inst
;
3247 if (!strcmp("__intrinsic_load_ssbo", callee
)) {
3248 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3249 if (dst
.type
== GLSL_TYPE_BOOL
)
3250 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3251 } else if (!strcmp("__intrinsic_store_ssbo", callee
)) {
3252 param
= param
->get_next();
3253 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3256 param
= param
->get_next();
3257 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3259 dst
.writemask
= write_mask
->value
.u
[0];
3261 dst
.type
= this->result
.type
;
3262 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3264 param
= param
->get_next();
3265 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3268 st_src_reg data
= this->result
, data2
= undef_src
;
3270 if (!strcmp("__intrinsic_atomic_add_ssbo", callee
))
3271 opcode
= TGSI_OPCODE_ATOMUADD
;
3272 else if (!strcmp("__intrinsic_atomic_min_ssbo", callee
))
3273 opcode
= TGSI_OPCODE_ATOMIMIN
;
3274 else if (!strcmp("__intrinsic_atomic_max_ssbo", callee
))
3275 opcode
= TGSI_OPCODE_ATOMIMAX
;
3276 else if (!strcmp("__intrinsic_atomic_and_ssbo", callee
))
3277 opcode
= TGSI_OPCODE_ATOMAND
;
3278 else if (!strcmp("__intrinsic_atomic_or_ssbo", callee
))
3279 opcode
= TGSI_OPCODE_ATOMOR
;
3280 else if (!strcmp("__intrinsic_atomic_xor_ssbo", callee
))
3281 opcode
= TGSI_OPCODE_ATOMXOR
;
3282 else if (!strcmp("__intrinsic_atomic_exchange_ssbo", callee
))
3283 opcode
= TGSI_OPCODE_ATOMXCHG
;
3284 else if (!strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3285 opcode
= TGSI_OPCODE_ATOMCAS
;
3286 param
= param
->get_next();
3287 val
= ((ir_instruction
*)param
)->as_rvalue();
3289 data2
= this->result
;
3291 assert(!"Unexpected intrinsic");
3295 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3298 param
= param
->get_next();
3299 ir_constant
*access
= NULL
;
3300 if (!param
->is_tail_sentinel()) {
3301 access
= ((ir_instruction
*)param
)->as_constant();
3305 /* The emit_asm() might have actually split the op into pieces, e.g. for
3306 * double stores. We have to go back and fix up all the generated ops.
3308 unsigned op
= inst
->op
;
3310 inst
->buffer
= buffer
;
3312 inst
->buffer_access
= access
->value
.u
[0];
3313 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3314 if (inst
->op
== TGSI_OPCODE_UADD
)
3315 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3316 } while (inst
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
&& inst
->op
== op
);
3320 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3322 const char *callee
= ir
->callee
->function_name();
3324 if (!strcmp("__intrinsic_memory_barrier", callee
))
3325 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3326 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3327 TGSI_MEMBAR_ATOMIC_BUFFER
|
3328 TGSI_MEMBAR_SHADER_IMAGE
|
3329 TGSI_MEMBAR_SHARED
));
3330 else if (!strcmp("__intrinsic_memory_barrier_atomic_counter", callee
))
3331 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3332 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3333 else if (!strcmp("__intrinsic_memory_barrier_buffer", callee
))
3334 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3335 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3336 else if (!strcmp("__intrinsic_memory_barrier_image", callee
))
3337 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3338 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3339 else if (!strcmp("__intrinsic_memory_barrier_shared", callee
))
3340 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3341 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3342 else if (!strcmp("__intrinsic_group_memory_barrier", callee
))
3343 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3344 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3345 TGSI_MEMBAR_ATOMIC_BUFFER
|
3346 TGSI_MEMBAR_SHADER_IMAGE
|
3347 TGSI_MEMBAR_SHARED
|
3348 TGSI_MEMBAR_THREAD_GROUP
));
3350 assert(!"Unexpected memory barrier intrinsic");
3354 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3356 const char *callee
= ir
->callee
->function_name();
3357 exec_node
*param
= ir
->actual_parameters
.get_head();
3359 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3361 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3363 /* Calculate the surface offset */
3364 offset
->accept(this);
3365 st_src_reg off
= this->result
;
3367 st_dst_reg dst
= undef_dst
;
3368 if (ir
->return_deref
) {
3369 ir
->return_deref
->accept(this);
3370 dst
= st_dst_reg(this->result
);
3371 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3374 glsl_to_tgsi_instruction
*inst
;
3376 if (!strcmp("__intrinsic_load_shared", callee
)) {
3377 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3378 inst
->buffer
= buffer
;
3379 } else if (!strcmp("__intrinsic_store_shared", callee
)) {
3380 param
= param
->get_next();
3381 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3384 param
= param
->get_next();
3385 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3387 dst
.writemask
= write_mask
->value
.u
[0];
3389 dst
.type
= this->result
.type
;
3390 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3391 inst
->buffer
= buffer
;
3393 param
= param
->get_next();
3394 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3397 st_src_reg data
= this->result
, data2
= undef_src
;
3399 if (!strcmp("__intrinsic_atomic_add_shared", callee
))
3400 opcode
= TGSI_OPCODE_ATOMUADD
;
3401 else if (!strcmp("__intrinsic_atomic_min_shared", callee
))
3402 opcode
= TGSI_OPCODE_ATOMIMIN
;
3403 else if (!strcmp("__intrinsic_atomic_max_shared", callee
))
3404 opcode
= TGSI_OPCODE_ATOMIMAX
;
3405 else if (!strcmp("__intrinsic_atomic_and_shared", callee
))
3406 opcode
= TGSI_OPCODE_ATOMAND
;
3407 else if (!strcmp("__intrinsic_atomic_or_shared", callee
))
3408 opcode
= TGSI_OPCODE_ATOMOR
;
3409 else if (!strcmp("__intrinsic_atomic_xor_shared", callee
))
3410 opcode
= TGSI_OPCODE_ATOMXOR
;
3411 else if (!strcmp("__intrinsic_atomic_exchange_shared", callee
))
3412 opcode
= TGSI_OPCODE_ATOMXCHG
;
3413 else if (!strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3414 opcode
= TGSI_OPCODE_ATOMCAS
;
3415 param
= param
->get_next();
3416 val
= ((ir_instruction
*)param
)->as_rvalue();
3418 data2
= this->result
;
3420 assert(!"Unexpected intrinsic");
3424 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3425 inst
->buffer
= buffer
;
3430 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3432 const char *callee
= ir
->callee
->function_name();
3433 exec_node
*param
= ir
->actual_parameters
.get_head();
3435 ir_dereference
*img
= (ir_dereference
*)param
;
3436 const ir_variable
*imgvar
= img
->variable_referenced();
3437 const glsl_type
*type
= imgvar
->type
->without_array();
3438 unsigned sampler_array_size
= 1, sampler_base
= 0;
3441 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3443 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3444 (unsigned int *)&image
.index
, &reladdr
);
3445 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3446 emit_arl(ir
, sampler_reladdr
, reladdr
);
3447 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3448 memcpy(image
.reladdr
, &sampler_reladdr
, sizeof(reladdr
));
3451 st_dst_reg dst
= undef_dst
;
3452 if (ir
->return_deref
) {
3453 ir
->return_deref
->accept(this);
3454 dst
= st_dst_reg(this->result
);
3455 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3458 glsl_to_tgsi_instruction
*inst
;
3460 if (!strcmp("__intrinsic_image_size", callee
)) {
3461 dst
.writemask
= WRITEMASK_XYZ
;
3462 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3463 } else if (!strcmp("__intrinsic_image_samples", callee
)) {
3464 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3465 st_dst_reg dstres
= st_dst_reg(res
);
3466 dstres
.writemask
= WRITEMASK_W
;
3467 emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3468 res
.swizzle
= SWIZZLE_WWWW
;
3469 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3471 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3473 st_dst_reg coord_dst
;
3474 coord
= get_temp(glsl_type::ivec4_type
);
3475 coord_dst
= st_dst_reg(coord
);
3476 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3477 param
= param
->get_next();
3478 ((ir_dereference
*)param
)->accept(this);
3479 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3480 coord
.swizzle
= SWIZZLE_XXXX
;
3481 switch (type
->coordinate_components()) {
3482 case 4: assert(!"unexpected coord count");
3484 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3486 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3489 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3490 param
= param
->get_next();
3491 ((ir_dereference
*)param
)->accept(this);
3492 st_src_reg sample
= this->result
;
3493 sample
.swizzle
= SWIZZLE_XXXX
;
3494 coord_dst
.writemask
= WRITEMASK_W
;
3495 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3496 coord
.swizzle
|= SWIZZLE_W
<< 9;
3499 param
= param
->get_next();
3500 if (!param
->is_tail_sentinel()) {
3501 ((ir_dereference
*)param
)->accept(this);
3502 arg1
= this->result
;
3503 param
= param
->get_next();
3506 if (!param
->is_tail_sentinel()) {
3507 ((ir_dereference
*)param
)->accept(this);
3508 arg2
= this->result
;
3509 param
= param
->get_next();
3512 assert(param
->is_tail_sentinel());
3515 if (!strcmp("__intrinsic_image_load", callee
))
3516 opcode
= TGSI_OPCODE_LOAD
;
3517 else if (!strcmp("__intrinsic_image_store", callee
))
3518 opcode
= TGSI_OPCODE_STORE
;
3519 else if (!strcmp("__intrinsic_image_atomic_add", callee
))
3520 opcode
= TGSI_OPCODE_ATOMUADD
;
3521 else if (!strcmp("__intrinsic_image_atomic_min", callee
))
3522 opcode
= TGSI_OPCODE_ATOMIMIN
;
3523 else if (!strcmp("__intrinsic_image_atomic_max", callee
))
3524 opcode
= TGSI_OPCODE_ATOMIMAX
;
3525 else if (!strcmp("__intrinsic_image_atomic_and", callee
))
3526 opcode
= TGSI_OPCODE_ATOMAND
;
3527 else if (!strcmp("__intrinsic_image_atomic_or", callee
))
3528 opcode
= TGSI_OPCODE_ATOMOR
;
3529 else if (!strcmp("__intrinsic_image_atomic_xor", callee
))
3530 opcode
= TGSI_OPCODE_ATOMXOR
;
3531 else if (!strcmp("__intrinsic_image_atomic_exchange", callee
))
3532 opcode
= TGSI_OPCODE_ATOMXCHG
;
3533 else if (!strcmp("__intrinsic_image_atomic_comp_swap", callee
))
3534 opcode
= TGSI_OPCODE_ATOMCAS
;
3536 assert(!"Unexpected intrinsic");
3540 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3541 if (opcode
== TGSI_OPCODE_STORE
)
3542 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3545 inst
->buffer
= image
;
3546 inst
->sampler_array_size
= sampler_array_size
;
3547 inst
->sampler_base
= sampler_base
;
3549 switch (type
->sampler_dimensionality
) {
3550 case GLSL_SAMPLER_DIM_1D
:
3551 inst
->tex_target
= (type
->sampler_array
)
3552 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3554 case GLSL_SAMPLER_DIM_2D
:
3555 inst
->tex_target
= (type
->sampler_array
)
3556 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3558 case GLSL_SAMPLER_DIM_3D
:
3559 inst
->tex_target
= TEXTURE_3D_INDEX
;
3561 case GLSL_SAMPLER_DIM_CUBE
:
3562 inst
->tex_target
= (type
->sampler_array
)
3563 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3565 case GLSL_SAMPLER_DIM_RECT
:
3566 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3568 case GLSL_SAMPLER_DIM_BUF
:
3569 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3571 case GLSL_SAMPLER_DIM_EXTERNAL
:
3572 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3574 case GLSL_SAMPLER_DIM_MS
:
3575 inst
->tex_target
= (type
->sampler_array
)
3576 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3579 assert(!"Should not get here.");
3582 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3583 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3587 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3589 glsl_to_tgsi_instruction
*call_inst
;
3590 ir_function_signature
*sig
= ir
->callee
;
3591 const char *callee
= sig
->function_name();
3592 function_entry
*entry
;
3595 /* Filter out intrinsics */
3596 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3597 !strcmp("__intrinsic_atomic_increment", callee
) ||
3598 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
3599 visit_atomic_counter_intrinsic(ir
);
3603 if (!strcmp("__intrinsic_load_ssbo", callee
) ||
3604 !strcmp("__intrinsic_store_ssbo", callee
) ||
3605 !strcmp("__intrinsic_atomic_add_ssbo", callee
) ||
3606 !strcmp("__intrinsic_atomic_min_ssbo", callee
) ||
3607 !strcmp("__intrinsic_atomic_max_ssbo", callee
) ||
3608 !strcmp("__intrinsic_atomic_and_ssbo", callee
) ||
3609 !strcmp("__intrinsic_atomic_or_ssbo", callee
) ||
3610 !strcmp("__intrinsic_atomic_xor_ssbo", callee
) ||
3611 !strcmp("__intrinsic_atomic_exchange_ssbo", callee
) ||
3612 !strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3613 visit_ssbo_intrinsic(ir
);
3617 if (!strcmp("__intrinsic_memory_barrier", callee
) ||
3618 !strcmp("__intrinsic_memory_barrier_atomic_counter", callee
) ||
3619 !strcmp("__intrinsic_memory_barrier_buffer", callee
) ||
3620 !strcmp("__intrinsic_memory_barrier_image", callee
) ||
3621 !strcmp("__intrinsic_memory_barrier_shared", callee
) ||
3622 !strcmp("__intrinsic_group_memory_barrier", callee
)) {
3623 visit_membar_intrinsic(ir
);
3627 if (!strcmp("__intrinsic_load_shared", callee
) ||
3628 !strcmp("__intrinsic_store_shared", callee
) ||
3629 !strcmp("__intrinsic_atomic_add_shared", callee
) ||
3630 !strcmp("__intrinsic_atomic_min_shared", callee
) ||
3631 !strcmp("__intrinsic_atomic_max_shared", callee
) ||
3632 !strcmp("__intrinsic_atomic_and_shared", callee
) ||
3633 !strcmp("__intrinsic_atomic_or_shared", callee
) ||
3634 !strcmp("__intrinsic_atomic_xor_shared", callee
) ||
3635 !strcmp("__intrinsic_atomic_exchange_shared", callee
) ||
3636 !strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3637 visit_shared_intrinsic(ir
);
3641 if (!strcmp("__intrinsic_image_load", callee
) ||
3642 !strcmp("__intrinsic_image_store", callee
) ||
3643 !strcmp("__intrinsic_image_atomic_add", callee
) ||
3644 !strcmp("__intrinsic_image_atomic_min", callee
) ||
3645 !strcmp("__intrinsic_image_atomic_max", callee
) ||
3646 !strcmp("__intrinsic_image_atomic_and", callee
) ||
3647 !strcmp("__intrinsic_image_atomic_or", callee
) ||
3648 !strcmp("__intrinsic_image_atomic_xor", callee
) ||
3649 !strcmp("__intrinsic_image_atomic_exchange", callee
) ||
3650 !strcmp("__intrinsic_image_atomic_comp_swap", callee
) ||
3651 !strcmp("__intrinsic_image_size", callee
) ||
3652 !strcmp("__intrinsic_image_samples", callee
)) {
3653 visit_image_intrinsic(ir
);
3657 entry
= get_function_signature(sig
);
3658 /* Process in parameters. */
3659 foreach_two_lists(formal_node
, &sig
->parameters
,
3660 actual_node
, &ir
->actual_parameters
) {
3661 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3662 ir_variable
*param
= (ir_variable
*) formal_node
;
3664 if (param
->data
.mode
== ir_var_function_in
||
3665 param
->data
.mode
== ir_var_function_inout
) {
3666 variable_storage
*storage
= find_variable_storage(param
);
3669 param_rval
->accept(this);
3670 st_src_reg r
= this->result
;
3673 l
.file
= storage
->file
;
3674 l
.index
= storage
->index
;
3676 l
.writemask
= WRITEMASK_XYZW
;
3677 l
.cond_mask
= COND_TR
;
3679 for (i
= 0; i
< type_size(param
->type
); i
++) {
3680 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3687 /* Emit call instruction */
3688 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3689 call_inst
->function
= entry
;
3691 /* Process out parameters. */
3692 foreach_two_lists(formal_node
, &sig
->parameters
,
3693 actual_node
, &ir
->actual_parameters
) {
3694 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3695 ir_variable
*param
= (ir_variable
*) formal_node
;
3697 if (param
->data
.mode
== ir_var_function_out
||
3698 param
->data
.mode
== ir_var_function_inout
) {
3699 variable_storage
*storage
= find_variable_storage(param
);
3703 r
.file
= storage
->file
;
3704 r
.index
= storage
->index
;
3706 r
.swizzle
= SWIZZLE_NOOP
;
3709 param_rval
->accept(this);
3710 st_dst_reg l
= st_dst_reg(this->result
);
3712 for (i
= 0; i
< type_size(param
->type
); i
++) {
3713 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3720 /* Process return value. */
3721 this->result
= entry
->return_reg
;
3725 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3726 ir_dereference
*tail
,
3727 unsigned *array_elements
,
3730 st_src_reg
*indirect
,
3733 switch (tail
->ir_type
) {
3734 case ir_type_dereference_record
: {
3735 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3736 const glsl_type
*struct_type
= deref_record
->record
->type
;
3737 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3739 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3741 assert(field_index
>= 0);
3742 *location
+= struct_type
->record_location_offset(field_index
);
3746 case ir_type_dereference_array
: {
3747 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3748 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3751 st_src_reg temp_reg
;
3752 st_dst_reg temp_dst
;
3754 temp_reg
= get_temp(glsl_type::uint_type
);
3755 temp_dst
= st_dst_reg(temp_reg
);
3756 temp_dst
.writemask
= 1;
3758 deref_arr
->array_index
->accept(this);
3759 if (*array_elements
!= 1)
3760 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3762 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3764 if (indirect
->file
== PROGRAM_UNDEFINED
)
3765 *indirect
= temp_reg
;
3767 temp_dst
= st_dst_reg(*indirect
);
3768 temp_dst
.writemask
= 1;
3769 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3772 *index
+= array_index
->value
.u
[0] * *array_elements
;
3774 *array_elements
*= deref_arr
->array
->type
->length
;
3776 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3785 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3786 unsigned *array_size
,
3789 st_src_reg
*reladdr
)
3791 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3792 unsigned location
= 0;
3793 ir_variable
*var
= ir
->variable_referenced();
3795 memset(reladdr
, 0, sizeof(*reladdr
));
3796 reladdr
->file
= PROGRAM_UNDEFINED
;
3802 location
= var
->data
.location
;
3803 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3806 * If we end up with no indirect then adjust the base to the index,
3807 * and set the array size to 1.
3809 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3814 if (location
!= 0xffffffff) {
3815 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3816 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3821 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3823 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3824 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3825 st_src_reg levels_src
, reladdr
;
3826 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3827 glsl_to_tgsi_instruction
*inst
= NULL
;
3828 unsigned opcode
= TGSI_OPCODE_NOP
;
3829 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3830 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
3831 bool is_cube_array
= false;
3834 /* if we are a cube array sampler */
3835 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3836 sampler_type
->sampler_array
)) {
3837 is_cube_array
= true;
3840 if (ir
->coordinate
) {
3841 ir
->coordinate
->accept(this);
3843 /* Put our coords in a temp. We'll need to modify them for shadow,
3844 * projection, or LOD, so the only case we'd use it as is is if
3845 * we're doing plain old texturing. The optimization passes on
3846 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3848 coord
= get_temp(glsl_type::vec4_type
);
3849 coord_dst
= st_dst_reg(coord
);
3850 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3851 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3854 if (ir
->projector
) {
3855 ir
->projector
->accept(this);
3856 projector
= this->result
;
3859 /* Storage for our result. Ideally for an assignment we'd be using
3860 * the actual storage for the result here, instead.
3862 result_src
= get_temp(ir
->type
);
3863 result_dst
= st_dst_reg(result_src
);
3867 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3869 ir
->offset
->accept(this);
3870 offset
[0] = this->result
;
3874 if (is_cube_array
||
3875 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3876 opcode
= TGSI_OPCODE_TXB2
;
3879 opcode
= TGSI_OPCODE_TXB
;
3881 ir
->lod_info
.bias
->accept(this);
3882 lod_info
= this->result
;
3884 ir
->offset
->accept(this);
3885 offset
[0] = this->result
;
3889 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3890 ir
->lod_info
.lod
->accept(this);
3891 lod_info
= this->result
;
3893 ir
->offset
->accept(this);
3894 offset
[0] = this->result
;
3898 opcode
= TGSI_OPCODE_TXD
;
3899 ir
->lod_info
.grad
.dPdx
->accept(this);
3901 ir
->lod_info
.grad
.dPdy
->accept(this);
3904 ir
->offset
->accept(this);
3905 offset
[0] = this->result
;
3909 opcode
= TGSI_OPCODE_TXQ
;
3910 ir
->lod_info
.lod
->accept(this);
3911 lod_info
= this->result
;
3913 case ir_query_levels
:
3914 opcode
= TGSI_OPCODE_TXQ
;
3915 lod_info
= undef_src
;
3916 levels_src
= get_temp(ir
->type
);
3919 opcode
= TGSI_OPCODE_TXF
;
3920 ir
->lod_info
.lod
->accept(this);
3921 lod_info
= this->result
;
3923 ir
->offset
->accept(this);
3924 offset
[0] = this->result
;
3928 opcode
= TGSI_OPCODE_TXF
;
3929 ir
->lod_info
.sample_index
->accept(this);
3930 sample_index
= this->result
;
3933 opcode
= TGSI_OPCODE_TG4
;
3934 ir
->lod_info
.component
->accept(this);
3935 component
= this->result
;
3937 ir
->offset
->accept(this);
3938 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3939 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3940 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3941 offset
[i
] = this->result
;
3942 offset
[i
].index
+= i
* type_size(elt_type
);
3943 offset
[i
].type
= elt_type
->base_type
;
3944 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3947 offset
[0] = this->result
;
3952 opcode
= TGSI_OPCODE_LODQ
;
3954 case ir_texture_samples
:
3955 opcode
= TGSI_OPCODE_TXQS
;
3957 case ir_samples_identical
:
3958 unreachable("Unexpected ir_samples_identical opcode");
3961 if (ir
->projector
) {
3962 if (opcode
== TGSI_OPCODE_TEX
) {
3963 /* Slot the projector in as the last component of the coord. */
3964 coord_dst
.writemask
= WRITEMASK_W
;
3965 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3966 coord_dst
.writemask
= WRITEMASK_XYZW
;
3967 opcode
= TGSI_OPCODE_TXP
;
3969 st_src_reg coord_w
= coord
;
3970 coord_w
.swizzle
= SWIZZLE_WWWW
;
3972 /* For the other TEX opcodes there's no projective version
3973 * since the last slot is taken up by LOD info. Do the
3974 * projective divide now.
3976 coord_dst
.writemask
= WRITEMASK_W
;
3977 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3979 /* In the case where we have to project the coordinates "by hand,"
3980 * the shadow comparator value must also be projected.
3982 st_src_reg tmp_src
= coord
;
3983 if (ir
->shadow_comparitor
) {
3984 /* Slot the shadow value in as the second to last component of the
3987 ir
->shadow_comparitor
->accept(this);
3989 tmp_src
= get_temp(glsl_type::vec4_type
);
3990 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3992 /* Projective division not allowed for array samplers. */
3993 assert(!sampler_type
->sampler_array
);
3995 tmp_dst
.writemask
= WRITEMASK_Z
;
3996 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3998 tmp_dst
.writemask
= WRITEMASK_XY
;
3999 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4002 coord_dst
.writemask
= WRITEMASK_XYZ
;
4003 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4005 coord_dst
.writemask
= WRITEMASK_XYZW
;
4006 coord
.swizzle
= SWIZZLE_XYZW
;
4010 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4011 * comparator was put in the correct place (and projected) by the code,
4012 * above, that handles by-hand projection.
4014 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4015 /* Slot the shadow value in as the second to last component of the
4018 ir
->shadow_comparitor
->accept(this);
4020 if (is_cube_array
) {
4021 cube_sc
= get_temp(glsl_type::float_type
);
4022 cube_sc_dst
= st_dst_reg(cube_sc
);
4023 cube_sc_dst
.writemask
= WRITEMASK_X
;
4024 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4025 cube_sc_dst
.writemask
= WRITEMASK_X
;
4028 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4029 sampler_type
->sampler_array
) ||
4030 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4031 coord_dst
.writemask
= WRITEMASK_W
;
4033 coord_dst
.writemask
= WRITEMASK_Z
;
4035 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4036 coord_dst
.writemask
= WRITEMASK_XYZW
;
4040 if (ir
->op
== ir_txf_ms
) {
4041 coord_dst
.writemask
= WRITEMASK_W
;
4042 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4043 coord_dst
.writemask
= WRITEMASK_XYZW
;
4044 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4045 opcode
== TGSI_OPCODE_TXF
) {
4046 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4047 coord_dst
.writemask
= WRITEMASK_W
;
4048 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4049 coord_dst
.writemask
= WRITEMASK_XYZW
;
4052 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4053 &sampler_index
, &reladdr
);
4054 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4055 emit_arl(ir
, sampler_reladdr
, reladdr
);
4057 if (opcode
== TGSI_OPCODE_TXD
)
4058 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4059 else if (opcode
== TGSI_OPCODE_TXQ
) {
4060 if (ir
->op
== ir_query_levels
) {
4061 /* the level is stored in W */
4062 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4063 result_dst
.writemask
= WRITEMASK_X
;
4064 levels_src
.swizzle
= SWIZZLE_WWWW
;
4065 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4067 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4068 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4069 inst
= emit_asm(ir
, opcode
, result_dst
);
4070 } else if (opcode
== TGSI_OPCODE_TXF
) {
4071 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4072 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4073 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4074 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4075 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4076 } else if (opcode
== TGSI_OPCODE_TG4
) {
4077 if (is_cube_array
&& ir
->shadow_comparitor
) {
4078 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4080 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4083 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4085 if (ir
->shadow_comparitor
)
4086 inst
->tex_shadow
= GL_TRUE
;
4088 inst
->sampler
.index
= sampler_index
;
4089 inst
->sampler_array_size
= sampler_array_size
;
4090 inst
->sampler_base
= sampler_base
;
4092 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4093 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4094 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4098 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4099 inst
->tex_offsets
[i
] = offset
[i
];
4100 inst
->tex_offset_num_offset
= i
;
4103 switch (sampler_type
->sampler_dimensionality
) {
4104 case GLSL_SAMPLER_DIM_1D
:
4105 inst
->tex_target
= (sampler_type
->sampler_array
)
4106 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4108 case GLSL_SAMPLER_DIM_2D
:
4109 inst
->tex_target
= (sampler_type
->sampler_array
)
4110 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4112 case GLSL_SAMPLER_DIM_3D
:
4113 inst
->tex_target
= TEXTURE_3D_INDEX
;
4115 case GLSL_SAMPLER_DIM_CUBE
:
4116 inst
->tex_target
= (sampler_type
->sampler_array
)
4117 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4119 case GLSL_SAMPLER_DIM_RECT
:
4120 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4122 case GLSL_SAMPLER_DIM_BUF
:
4123 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4125 case GLSL_SAMPLER_DIM_EXTERNAL
:
4126 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4128 case GLSL_SAMPLER_DIM_MS
:
4129 inst
->tex_target
= (sampler_type
->sampler_array
)
4130 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4133 assert(!"Should not get here.");
4136 inst
->tex_type
= ir
->type
->base_type
;
4138 this->result
= result_src
;
4142 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4144 if (ir
->get_value()) {
4148 assert(current_function
);
4150 ir
->get_value()->accept(this);
4151 st_src_reg r
= this->result
;
4153 l
= st_dst_reg(current_function
->return_reg
);
4155 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4156 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4162 emit_asm(ir
, TGSI_OPCODE_RET
);
4166 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4168 if (ir
->condition
) {
4169 ir
->condition
->accept(this);
4170 st_src_reg condition
= this->result
;
4172 /* Convert the bool condition to a float so we can negate. */
4173 if (native_integers
) {
4174 st_src_reg temp
= get_temp(ir
->condition
->type
);
4175 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4176 condition
, st_src_reg_for_float(1.0));
4180 condition
.negate
= ~condition
.negate
;
4181 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4183 /* unconditional kil */
4184 emit_asm(ir
, TGSI_OPCODE_KILL
);
4189 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4192 glsl_to_tgsi_instruction
*if_inst
;
4194 ir
->condition
->accept(this);
4195 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4197 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4199 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4201 this->instructions
.push_tail(if_inst
);
4203 visit_exec_list(&ir
->then_instructions
, this);
4205 if (!ir
->else_instructions
.is_empty()) {
4206 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4207 visit_exec_list(&ir
->else_instructions
, this);
4210 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4215 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4217 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4219 ir
->stream
->accept(this);
4220 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4224 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4226 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4228 ir
->stream
->accept(this);
4229 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4233 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4235 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4236 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4238 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4241 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4243 result
.file
= PROGRAM_UNDEFINED
;
4248 num_input_arrays
= 0;
4249 num_output_arrays
= 0;
4250 next_signature_id
= 1;
4252 current_function
= NULL
;
4253 num_address_regs
= 0;
4257 indirect_addr_consts
= false;
4258 wpos_transform_const
= -1;
4260 native_integers
= false;
4261 mem_ctx
= ralloc_context(NULL
);
4264 shader_program
= NULL
;
4269 use_shared_memory
= false;
4272 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4275 ralloc_free(mem_ctx
);
4278 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4285 * Count resources used by the given gpu program (number of texture
4289 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4291 v
->samplers_used
= 0;
4292 v
->buffers_used
= 0;
4295 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4296 if (inst
->info
->is_tex
) {
4297 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4298 unsigned idx
= inst
->sampler_base
+ i
;
4299 v
->samplers_used
|= 1 << idx
;
4301 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4302 v
->sampler_types
[idx
] = inst
->tex_type
;
4303 v
->sampler_targets
[idx
] =
4304 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4306 if (inst
->tex_shadow
) {
4307 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4311 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4312 is_resource_instruction(inst
->op
) ||
4313 inst
->op
== TGSI_OPCODE_STORE
)) {
4314 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4315 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4316 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4317 v
->use_shared_memory
= true;
4319 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4320 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4321 unsigned idx
= inst
->sampler_base
+ i
;
4322 v
->images_used
|= 1 << idx
;
4323 v
->image_targets
[idx
] =
4324 st_translate_texture_target(inst
->tex_target
, false);
4325 v
->image_formats
[idx
] = inst
->image_format
;
4330 prog
->SamplersUsed
= v
->samplers_used
;
4332 if (v
->shader_program
!= NULL
)
4333 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4337 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4338 * are read from the given src in this instruction
4341 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4343 int read_mask
= 0, comp
;
4345 /* Now, given the src swizzle and the written channels, find which
4346 * components are actually read
4348 for (comp
= 0; comp
< 4; ++comp
) {
4349 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4351 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4352 read_mask
|= 1 << coord
;
4359 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4360 * instruction is the first instruction to write to register T0. There are
4361 * several lowering passes done in GLSL IR (e.g. branches and
4362 * relative addressing) that create a large number of conditional assignments
4363 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4365 * Here is why this conversion is safe:
4366 * CMP T0, T1 T2 T0 can be expanded to:
4372 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4373 * as the original program. If (T1 < 0.0) evaluates to false, executing
4374 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4375 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4376 * because any instruction that was going to read from T0 after this was going
4377 * to read a garbage value anyway.
4380 glsl_to_tgsi_visitor::simplify_cmp(void)
4382 int tempWritesSize
= 0;
4383 unsigned *tempWrites
= NULL
;
4384 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4386 memset(outputWrites
, 0, sizeof(outputWrites
));
4388 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4389 unsigned prevWriteMask
= 0;
4391 /* Give up if we encounter relative addressing or flow control. */
4392 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4393 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4394 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4395 inst
->op
== TGSI_OPCODE_BGNSUB
||
4396 inst
->op
== TGSI_OPCODE_CONT
||
4397 inst
->op
== TGSI_OPCODE_END
||
4398 inst
->op
== TGSI_OPCODE_ENDSUB
||
4399 inst
->op
== TGSI_OPCODE_RET
) {
4403 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4404 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4405 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4406 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4407 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4408 if (inst
->dst
[0].index
>= tempWritesSize
) {
4409 const int inc
= 4096;
4411 tempWrites
= (unsigned*)
4413 (tempWritesSize
+ inc
) * sizeof(unsigned));
4417 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4418 tempWritesSize
+= inc
;
4421 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4422 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4426 /* For a CMP to be considered a conditional write, the destination
4427 * register and source register two must be the same. */
4428 if (inst
->op
== TGSI_OPCODE_CMP
4429 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4430 && inst
->src
[2].file
== inst
->dst
[0].file
4431 && inst
->src
[2].index
== inst
->dst
[0].index
4432 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4434 inst
->op
= TGSI_OPCODE_MOV
;
4435 inst
->src
[0] = inst
->src
[1];
4442 /* Replaces all references to a temporary register index with another index. */
4444 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4446 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4449 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4450 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4451 for (k
= 0; k
< num_renames
; k
++)
4452 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4453 inst
->src
[j
].index
= renames
[k
].new_reg
;
4456 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4457 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4458 for (k
= 0; k
< num_renames
; k
++)
4459 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4460 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4463 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4464 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4465 for (k
= 0; k
< num_renames
; k
++)
4466 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4467 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4473 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4475 int depth
= 0; /* loop depth */
4476 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4479 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4480 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4481 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4482 if (first_reads
[inst
->src
[j
].index
] == -1)
4483 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4486 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4487 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4488 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4489 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4492 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4495 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4505 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4507 int depth
= 0; /* loop depth */
4508 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4511 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4512 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4513 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4514 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4516 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4517 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4518 if (first_writes
[inst
->dst
[j
].index
] == -1)
4519 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4520 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4523 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4524 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4525 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4527 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4530 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4533 for (k
= 0; k
< this->next_temp
; k
++) {
4534 if (last_reads
[k
] == -2) {
4546 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4548 int depth
= 0; /* loop depth */
4552 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4553 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4554 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4555 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4558 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4560 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4562 for (k
= 0; k
< this->next_temp
; k
++) {
4563 if (last_writes
[k
] == -2) {
4574 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4575 * channels for copy propagation and updates following instructions to
4576 * use the original versions.
4578 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4579 * will occur. As an example, a TXP production before this pass:
4581 * 0: MOV TEMP[1], INPUT[4].xyyy;
4582 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4583 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4587 * 0: MOV TEMP[1], INPUT[4].xyyy;
4588 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4589 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4591 * which allows for dead code elimination on TEMP[1]'s writes.
4594 glsl_to_tgsi_visitor::copy_propagate(void)
4596 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4597 glsl_to_tgsi_instruction
*,
4598 this->next_temp
* 4);
4599 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4602 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4603 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4604 || inst
->dst
[0].index
< this->next_temp
);
4606 /* First, do any copy propagation possible into the src regs. */
4607 for (int r
= 0; r
< 3; r
++) {
4608 glsl_to_tgsi_instruction
*first
= NULL
;
4610 int acp_base
= inst
->src
[r
].index
* 4;
4612 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4613 inst
->src
[r
].reladdr
||
4614 inst
->src
[r
].reladdr2
)
4617 /* See if we can find entries in the ACP consisting of MOVs
4618 * from the same src register for all the swizzled channels
4619 * of this src register reference.
4621 for (int i
= 0; i
< 4; i
++) {
4622 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4623 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4630 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4635 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4636 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4637 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4638 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4646 /* We've now validated that we can copy-propagate to
4647 * replace this src register reference. Do it.
4649 inst
->src
[r
].file
= first
->src
[0].file
;
4650 inst
->src
[r
].index
= first
->src
[0].index
;
4651 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4652 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4653 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4654 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4657 for (int i
= 0; i
< 4; i
++) {
4658 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4659 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4660 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4662 inst
->src
[r
].swizzle
= swizzle
;
4667 case TGSI_OPCODE_BGNLOOP
:
4668 case TGSI_OPCODE_ENDLOOP
:
4669 /* End of a basic block, clear the ACP entirely. */
4670 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4673 case TGSI_OPCODE_IF
:
4674 case TGSI_OPCODE_UIF
:
4678 case TGSI_OPCODE_ENDIF
:
4679 case TGSI_OPCODE_ELSE
:
4680 /* Clear all channels written inside the block from the ACP, but
4681 * leaving those that were not touched.
4683 for (int r
= 0; r
< this->next_temp
; r
++) {
4684 for (int c
= 0; c
< 4; c
++) {
4685 if (!acp
[4 * r
+ c
])
4688 if (acp_level
[4 * r
+ c
] >= level
)
4689 acp
[4 * r
+ c
] = NULL
;
4692 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4697 /* Continuing the block, clear any written channels from
4700 for (int d
= 0; d
< 2; d
++) {
4701 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4702 /* Any temporary might be written, so no copy propagation
4703 * across this instruction.
4705 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4706 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4707 inst
->dst
[d
].reladdr
) {
4708 /* Any output might be written, so no copy propagation
4709 * from outputs across this instruction.
4711 for (int r
= 0; r
< this->next_temp
; r
++) {
4712 for (int c
= 0; c
< 4; c
++) {
4713 if (!acp
[4 * r
+ c
])
4716 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4717 acp
[4 * r
+ c
] = NULL
;
4720 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4721 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4722 /* Clear where it's used as dst. */
4723 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4724 for (int c
= 0; c
< 4; c
++) {
4725 if (inst
->dst
[d
].writemask
& (1 << c
))
4726 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4730 /* Clear where it's used as src. */
4731 for (int r
= 0; r
< this->next_temp
; r
++) {
4732 for (int c
= 0; c
< 4; c
++) {
4733 if (!acp
[4 * r
+ c
])
4736 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4738 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4739 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4740 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4741 acp
[4 * r
+ c
] = NULL
;
4750 /* If this is a copy, add it to the ACP. */
4751 if (inst
->op
== TGSI_OPCODE_MOV
&&
4752 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4753 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4754 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4755 !inst
->dst
[0].reladdr
&&
4756 !inst
->dst
[0].reladdr2
&&
4758 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4759 !inst
->src
[0].reladdr
&&
4760 !inst
->src
[0].reladdr2
&&
4761 !inst
->src
[0].negate
) {
4762 for (int i
= 0; i
< 4; i
++) {
4763 if (inst
->dst
[0].writemask
& (1 << i
)) {
4764 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4765 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4771 ralloc_free(acp_level
);
4776 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4779 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4780 * will occur. As an example, a TXP production after copy propagation but
4783 * 0: MOV TEMP[1], INPUT[4].xyyy;
4784 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4785 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4787 * and after this pass:
4789 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4792 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4794 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4795 glsl_to_tgsi_instruction
*,
4796 this->next_temp
* 4);
4797 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4801 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4802 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4803 || inst
->dst
[0].index
< this->next_temp
);
4806 case TGSI_OPCODE_BGNLOOP
:
4807 case TGSI_OPCODE_ENDLOOP
:
4808 case TGSI_OPCODE_CONT
:
4809 case TGSI_OPCODE_BRK
:
4810 /* End of a basic block, clear the write array entirely.
4812 * This keeps us from killing dead code when the writes are
4813 * on either side of a loop, even when the register isn't touched
4814 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4815 * dead code of this type, so it shouldn't make a difference as long as
4816 * the dead code elimination pass in the GLSL compiler does its job.
4818 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4821 case TGSI_OPCODE_ENDIF
:
4822 case TGSI_OPCODE_ELSE
:
4823 /* Promote the recorded level of all channels written inside the
4824 * preceding if or else block to the level above the if/else block.
4826 for (int r
= 0; r
< this->next_temp
; r
++) {
4827 for (int c
= 0; c
< 4; c
++) {
4828 if (!writes
[4 * r
+ c
])
4831 if (write_level
[4 * r
+ c
] == level
)
4832 write_level
[4 * r
+ c
] = level
-1;
4835 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4839 case TGSI_OPCODE_IF
:
4840 case TGSI_OPCODE_UIF
:
4842 /* fallthrough to default case to mark the condition as read */
4844 /* Continuing the block, clear any channels from the write array that
4845 * are read by this instruction.
4847 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4848 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4849 /* Any temporary might be read, so no dead code elimination
4850 * across this instruction.
4852 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4853 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4854 /* Clear where it's used as src. */
4855 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4856 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4857 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4858 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4860 for (int c
= 0; c
< 4; c
++) {
4861 if (src_chans
& (1 << c
))
4862 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4866 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4867 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4868 /* Any temporary might be read, so no dead code elimination
4869 * across this instruction.
4871 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4872 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4873 /* Clear where it's used as src. */
4874 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4875 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4876 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4877 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4879 for (int c
= 0; c
< 4; c
++) {
4880 if (src_chans
& (1 << c
))
4881 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4888 /* If this instruction writes to a temporary, add it to the write array.
4889 * If there is already an instruction in the write array for one or more
4890 * of the channels, flag that channel write as dead.
4892 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4893 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4894 !inst
->dst
[i
].reladdr
) {
4895 for (int c
= 0; c
< 4; c
++) {
4896 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4897 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4898 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4901 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4903 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4904 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4911 /* Anything still in the write array at this point is dead code. */
4912 for (int r
= 0; r
< this->next_temp
; r
++) {
4913 for (int c
= 0; c
< 4; c
++) {
4914 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4916 inst
->dead_mask
|= (1 << c
);
4920 /* Now actually remove the instructions that are completely dead and update
4921 * the writemask of other instructions with dead channels.
4923 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4924 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4926 /* No amount of dead masks should remove memory stores */
4927 if (inst
->info
->is_store
)
4930 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4935 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4936 if (inst
->dead_mask
== WRITEMASK_XY
||
4937 inst
->dead_mask
== WRITEMASK_ZW
)
4938 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4940 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4944 ralloc_free(write_level
);
4945 ralloc_free(writes
);
4950 /* merge DFRACEXP instructions into one. */
4952 glsl_to_tgsi_visitor::merge_two_dsts(void)
4954 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4955 glsl_to_tgsi_instruction
*inst2
;
4957 if (num_inst_dst_regs(inst
) != 2)
4960 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4961 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4964 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4967 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4968 inst
->src
[0].index
== inst2
->src
[0].index
&&
4969 inst
->src
[0].type
== inst2
->src
[0].type
&&
4970 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4972 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4978 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4980 inst
->dst
[0] = inst2
->dst
[0];
4981 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4982 inst
->dst
[1] = inst2
->dst
[1];
4993 /* Merges temporary registers together where possible to reduce the number of
4994 * registers needed to run a program.
4996 * Produces optimal code only after copy propagation and dead code elimination
4999 glsl_to_tgsi_visitor::merge_registers(void)
5001 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5002 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5003 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5005 int num_renames
= 0;
5007 /* Read the indices of the last read and first write to each temp register
5008 * into an array so that we don't have to traverse the instruction list as
5010 for (i
= 0; i
< this->next_temp
; i
++) {
5012 first_writes
[i
] = -1;
5014 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5016 /* Start looking for registers with non-overlapping usages that can be
5017 * merged together. */
5018 for (i
= 0; i
< this->next_temp
; i
++) {
5019 /* Don't touch unused registers. */
5020 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5022 for (j
= 0; j
< this->next_temp
; j
++) {
5023 /* Don't touch unused registers. */
5024 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5026 /* We can merge the two registers if the first write to j is after or
5027 * in the same instruction as the last read from i. Note that the
5028 * register at index i will always be used earlier or at the same time
5029 * as the register at index j. */
5030 if (first_writes
[i
] <= first_writes
[j
] &&
5031 last_reads
[i
] <= first_writes
[j
]) {
5032 renames
[num_renames
].old_reg
= j
;
5033 renames
[num_renames
].new_reg
= i
;
5036 /* Update the first_writes and last_reads arrays with the new
5037 * values for the merged register index, and mark the newly unused
5038 * register index as such. */
5039 assert(last_reads
[j
] >= last_reads
[i
]);
5040 last_reads
[i
] = last_reads
[j
];
5041 first_writes
[j
] = -1;
5047 rename_temp_registers(num_renames
, renames
);
5048 ralloc_free(renames
);
5049 ralloc_free(last_reads
);
5050 ralloc_free(first_writes
);
5053 /* Reassign indices to temporary registers by reusing unused indices created
5054 * by optimization passes. */
5056 glsl_to_tgsi_visitor::renumber_registers(void)
5060 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5061 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5062 int num_renames
= 0;
5063 for (i
= 0; i
< this->next_temp
; i
++) {
5064 first_reads
[i
] = -1;
5066 get_first_temp_read(first_reads
);
5068 for (i
= 0; i
< this->next_temp
; i
++) {
5069 if (first_reads
[i
] < 0) continue;
5070 if (i
!= new_index
) {
5071 renames
[num_renames
].old_reg
= i
;
5072 renames
[num_renames
].new_reg
= new_index
;
5078 rename_temp_registers(num_renames
, renames
);
5079 this->next_temp
= new_index
;
5080 ralloc_free(renames
);
5081 ralloc_free(first_reads
);
5084 /* ------------------------- TGSI conversion stuff -------------------------- */
5086 unsigned branch_target
;
5091 * Intermediate state used during shader translation.
5093 struct st_translate
{
5094 struct ureg_program
*ureg
;
5096 unsigned temps_size
;
5097 struct ureg_dst
*temps
;
5099 struct ureg_dst
*arrays
;
5100 unsigned num_temp_arrays
;
5101 struct ureg_src
*constants
;
5103 struct ureg_src
*immediates
;
5105 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5106 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5107 struct ureg_dst address
[3];
5108 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5109 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5110 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5111 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5112 struct ureg_src shared_memory
;
5113 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5114 unsigned *array_sizes
;
5115 struct array_decl
*input_arrays
;
5116 struct array_decl
*output_arrays
;
5118 const GLuint
*inputMapping
;
5119 const GLuint
*outputMapping
;
5121 /* For every instruction that contains a label (eg CALL), keep
5122 * details so that we can go back afterwards and emit the correct
5123 * tgsi instruction number for each label.
5125 struct label
*labels
;
5126 unsigned labels_size
;
5127 unsigned labels_count
;
5129 /* Keep a record of the tgsi instruction number that each mesa
5130 * instruction starts at, will be used to fix up labels after
5135 unsigned insn_count
;
5137 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
5142 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5143 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
5146 TGSI_SEMANTIC_VERTEXID
,
5147 TGSI_SEMANTIC_INSTANCEID
,
5148 TGSI_SEMANTIC_VERTEXID_NOBASE
,
5149 TGSI_SEMANTIC_BASEVERTEX
,
5150 TGSI_SEMANTIC_BASEINSTANCE
,
5151 TGSI_SEMANTIC_DRAWID
,
5155 TGSI_SEMANTIC_INVOCATIONID
,
5159 TGSI_SEMANTIC_POSITION
,
5161 TGSI_SEMANTIC_SAMPLEID
,
5162 TGSI_SEMANTIC_SAMPLEPOS
,
5163 TGSI_SEMANTIC_SAMPLEMASK
,
5164 TGSI_SEMANTIC_HELPER_INVOCATION
,
5166 /* Tessellation shaders
5168 TGSI_SEMANTIC_TESSCOORD
,
5169 TGSI_SEMANTIC_VERTICESIN
,
5170 TGSI_SEMANTIC_PRIMID
,
5171 TGSI_SEMANTIC_TESSOUTER
,
5172 TGSI_SEMANTIC_TESSINNER
,
5176 TGSI_SEMANTIC_THREAD_ID
,
5177 TGSI_SEMANTIC_BLOCK_ID
,
5178 TGSI_SEMANTIC_GRID_SIZE
,
5182 * Make note of a branch to a label in the TGSI code.
5183 * After we've emitted all instructions, we'll go over the list
5184 * of labels built here and patch the TGSI code with the actual
5185 * location of each label.
5187 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5191 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5192 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5193 t
->labels
= (struct label
*)realloc(t
->labels
,
5194 t
->labels_size
* sizeof(struct label
));
5195 if (t
->labels
== NULL
) {
5196 static unsigned dummy
;
5202 i
= t
->labels_count
++;
5203 t
->labels
[i
].branch_target
= branch_target
;
5204 return &t
->labels
[i
].token
;
5208 * Called prior to emitting the TGSI code for each instruction.
5209 * Allocate additional space for instructions if needed.
5210 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5211 * the next TGSI instruction.
5213 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5215 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5216 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5217 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5218 if (t
->insn
== NULL
) {
5224 t
->insn
[t
->insn_count
++] = start
;
5228 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5230 static struct ureg_src
5231 emit_immediate(struct st_translate
*t
,
5232 gl_constant_value values
[4],
5235 struct ureg_program
*ureg
= t
->ureg
;
5240 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5242 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5244 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5245 case GL_UNSIGNED_INT
:
5247 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5249 assert(!"should not get here - type must be float, int, uint, or bool");
5250 return ureg_src_undef();
5255 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5257 static struct ureg_dst
5258 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5264 case PROGRAM_UNDEFINED
:
5265 return ureg_dst_undef();
5267 case PROGRAM_TEMPORARY
:
5268 /* Allocate space for temporaries on demand. */
5269 if (index
>= t
->temps_size
) {
5270 const int inc
= 4096;
5272 t
->temps
= (struct ureg_dst
*)
5274 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5276 return ureg_dst_undef();
5278 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5279 t
->temps_size
+= inc
;
5282 if (ureg_dst_is_undef(t
->temps
[index
]))
5283 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5285 return t
->temps
[index
];
5288 array
= index
>> 16;
5290 assert(array
< t
->num_temp_arrays
);
5292 if (ureg_dst_is_undef(t
->arrays
[array
]))
5293 t
->arrays
[array
] = ureg_DECL_array_temporary(
5294 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5296 return ureg_dst_array_offset(t
->arrays
[array
],
5297 (int)(index
& 0xFFFF) - 0x8000);
5299 case PROGRAM_OUTPUT
:
5301 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
5302 assert(index
< FRAG_RESULT_MAX
);
5303 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
5304 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
5305 assert(index
< VARYING_SLOT_TESS_MAX
);
5307 assert(index
< VARYING_SLOT_MAX
);
5309 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5310 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5311 return t
->outputs
[t
->outputMapping
[index
]];
5314 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
5315 unsigned mesa_index
= decl
->mesa_index
;
5316 int slot
= t
->outputMapping
[mesa_index
];
5318 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5319 assert(t
->outputs
[slot
].ArrayID
== array_id
);
5320 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
5323 case PROGRAM_ADDRESS
:
5324 return t
->address
[index
];
5327 assert(!"unknown dst register file");
5328 return ureg_dst_undef();
5333 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5335 static struct ureg_src
5336 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5338 int index
= reg
->index
;
5339 int double_reg2
= reg
->double_reg2
? 1 : 0;
5342 case PROGRAM_UNDEFINED
:
5343 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5345 case PROGRAM_TEMPORARY
:
5347 case PROGRAM_OUTPUT
:
5348 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5350 case PROGRAM_UNIFORM
:
5351 assert(reg
->index
>= 0);
5352 return reg
->index
< t
->num_constants
?
5353 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5354 case PROGRAM_STATE_VAR
:
5355 case PROGRAM_CONSTANT
: /* ie, immediate */
5356 if (reg
->has_index2
)
5357 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5359 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5360 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5362 case PROGRAM_IMMEDIATE
:
5363 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5364 return t
->immediates
[reg
->index
];
5367 /* GLSL inputs are 64-bit containers, so we have to
5368 * map back to the original index and add the offset after
5370 index
-= double_reg2
;
5371 if (!reg
->array_id
) {
5372 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5373 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5374 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5377 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
5378 unsigned mesa_index
= decl
->mesa_index
;
5379 int slot
= t
->inputMapping
[mesa_index
];
5381 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5382 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
5383 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
5386 case PROGRAM_ADDRESS
:
5387 return ureg_src(t
->address
[reg
->index
]);
5389 case PROGRAM_SYSTEM_VALUE
:
5390 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5391 return t
->systemValues
[reg
->index
];
5394 assert(!"unknown src register file");
5395 return ureg_src_undef();
5400 * Create a TGSI ureg_dst register from an st_dst_reg.
5402 static struct ureg_dst
5403 translate_dst(struct st_translate
*t
,
5404 const st_dst_reg
*dst_reg
,
5407 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5410 if (dst
.File
== TGSI_FILE_NULL
)
5413 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5416 dst
= ureg_saturate(dst
);
5418 if (dst_reg
->reladdr
!= NULL
) {
5419 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5420 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5423 if (dst_reg
->has_index2
) {
5424 if (dst_reg
->reladdr2
)
5425 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5428 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5435 * Create a TGSI ureg_src register from an st_src_reg.
5437 static struct ureg_src
5438 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5440 struct ureg_src src
= src_register(t
, src_reg
);
5442 if (src_reg
->has_index2
) {
5443 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5444 * and UBO constant buffers (buffer, position).
5446 if (src_reg
->reladdr2
)
5447 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5450 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5453 src
= ureg_swizzle(src
,
5454 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5455 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5456 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5457 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5459 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5460 src
= ureg_negate(src
);
5462 if (src_reg
->reladdr
!= NULL
) {
5463 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5464 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5470 static struct tgsi_texture_offset
5471 translate_tex_offset(struct st_translate
*t
,
5472 const st_src_reg
*in_offset
, int idx
)
5474 struct tgsi_texture_offset offset
;
5475 struct ureg_src imm_src
;
5476 struct ureg_dst dst
;
5479 switch (in_offset
->file
) {
5480 case PROGRAM_IMMEDIATE
:
5481 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
5482 imm_src
= t
->immediates
[in_offset
->index
];
5484 offset
.File
= imm_src
.File
;
5485 offset
.Index
= imm_src
.Index
;
5486 offset
.SwizzleX
= imm_src
.SwizzleX
;
5487 offset
.SwizzleY
= imm_src
.SwizzleY
;
5488 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
5491 case PROGRAM_TEMPORARY
:
5492 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
5493 offset
.File
= imm_src
.File
;
5494 offset
.Index
= imm_src
.Index
;
5495 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5496 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5497 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5501 array
= in_offset
->index
>> 16;
5504 assert(array
< (int)t
->num_temp_arrays
);
5506 dst
= t
->arrays
[array
];
5507 offset
.File
= dst
.File
;
5508 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
5509 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5510 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5511 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5521 compile_tgsi_instruction(struct st_translate
*t
,
5522 const glsl_to_tgsi_instruction
*inst
)
5524 struct ureg_program
*ureg
= t
->ureg
;
5526 struct ureg_dst dst
[2];
5527 struct ureg_src src
[4];
5528 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5532 unsigned tex_target
;
5534 num_dst
= num_inst_dst_regs(inst
);
5535 num_src
= num_inst_src_regs(inst
);
5537 for (i
= 0; i
< num_dst
; i
++)
5538 dst
[i
] = translate_dst(t
,
5542 for (i
= 0; i
< num_src
; i
++)
5543 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5546 case TGSI_OPCODE_BGNLOOP
:
5547 case TGSI_OPCODE_CAL
:
5548 case TGSI_OPCODE_ELSE
:
5549 case TGSI_OPCODE_ENDLOOP
:
5550 case TGSI_OPCODE_IF
:
5551 case TGSI_OPCODE_UIF
:
5552 assert(num_dst
== 0);
5553 ureg_label_insn(ureg
,
5557 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5560 case TGSI_OPCODE_TEX
:
5561 case TGSI_OPCODE_TXB
:
5562 case TGSI_OPCODE_TXD
:
5563 case TGSI_OPCODE_TXL
:
5564 case TGSI_OPCODE_TXP
:
5565 case TGSI_OPCODE_TXQ
:
5566 case TGSI_OPCODE_TXQS
:
5567 case TGSI_OPCODE_TXF
:
5568 case TGSI_OPCODE_TEX2
:
5569 case TGSI_OPCODE_TXB2
:
5570 case TGSI_OPCODE_TXL2
:
5571 case TGSI_OPCODE_TG4
:
5572 case TGSI_OPCODE_LODQ
:
5573 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5574 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5575 if (inst
->sampler
.reladdr
)
5577 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5579 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5580 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5582 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5588 texoffsets
, inst
->tex_offset_num_offset
,
5592 case TGSI_OPCODE_RESQ
:
5593 case TGSI_OPCODE_LOAD
:
5594 case TGSI_OPCODE_ATOMUADD
:
5595 case TGSI_OPCODE_ATOMXCHG
:
5596 case TGSI_OPCODE_ATOMCAS
:
5597 case TGSI_OPCODE_ATOMAND
:
5598 case TGSI_OPCODE_ATOMOR
:
5599 case TGSI_OPCODE_ATOMXOR
:
5600 case TGSI_OPCODE_ATOMUMIN
:
5601 case TGSI_OPCODE_ATOMUMAX
:
5602 case TGSI_OPCODE_ATOMIMIN
:
5603 case TGSI_OPCODE_ATOMIMAX
:
5604 for (i
= num_src
- 1; i
>= 0; i
--)
5605 src
[i
+ 1] = src
[i
];
5607 if (inst
->buffer
.file
== PROGRAM_MEMORY
)
5608 src
[0] = t
->shared_memory
;
5609 else if (inst
->buffer
.file
== PROGRAM_BUFFER
)
5610 src
[0] = t
->buffers
[inst
->buffer
.index
];
5612 src
[0] = t
->images
[inst
->buffer
.index
];
5613 if (inst
->buffer
.reladdr
)
5614 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5615 assert(src
[0].File
!= TGSI_FILE_NULL
);
5616 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5617 inst
->buffer_access
);
5620 case TGSI_OPCODE_STORE
:
5621 if (inst
->buffer
.file
== PROGRAM_MEMORY
)
5622 dst
[0] = ureg_dst(t
->shared_memory
);
5623 else if (inst
->buffer
.file
== PROGRAM_BUFFER
)
5624 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5626 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5627 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5628 if (inst
->buffer
.reladdr
)
5629 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5630 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5631 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5632 inst
->buffer_access
);
5635 case TGSI_OPCODE_SCS
:
5636 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5637 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5650 * Emit the TGSI instructions for inverting and adjusting WPOS.
5651 * This code is unavoidable because it also depends on whether
5652 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5655 emit_wpos_adjustment(struct gl_context
*ctx
,
5656 struct st_translate
*t
,
5657 int wpos_transform_const
,
5659 GLfloat adjX
, GLfloat adjY
[2])
5661 struct ureg_program
*ureg
= t
->ureg
;
5663 assert(wpos_transform_const
>= 0);
5665 /* Fragment program uses fragment position input.
5666 * Need to replace instances of INPUT[WPOS] with temp T
5667 * where T = INPUT[WPOS] is inverted by Y.
5669 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5670 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5671 struct ureg_src
*wpos
=
5672 ctx
->Const
.GLSLFragCoordIsSysVal
?
5673 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5674 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5675 struct ureg_src wpos_input
= *wpos
;
5677 /* First, apply the coordinate shift: */
5678 if (adjX
|| adjY
[0] || adjY
[1]) {
5679 if (adjY
[0] != adjY
[1]) {
5680 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5681 * depending on whether inversion is actually going to be applied
5682 * or not, which is determined by testing against the inversion
5683 * state variable used below, which will be either +1 or -1.
5685 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5687 ureg_CMP(ureg
, adj_temp
,
5688 ureg_scalar(wpostrans
, invert
? 2 : 0),
5689 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5690 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5691 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5693 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5694 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5696 wpos_input
= ureg_src(wpos_temp
);
5698 /* MOV wpos_temp, input[wpos]
5700 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5703 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5704 * inversion/identity, or the other way around if we're drawing to an FBO.
5707 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5710 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5712 ureg_scalar(wpostrans
, 0),
5713 ureg_scalar(wpostrans
, 1));
5715 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5718 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5720 ureg_scalar(wpostrans
, 2),
5721 ureg_scalar(wpostrans
, 3));
5724 /* Use wpos_temp as position input from here on:
5726 *wpos
= ureg_src(wpos_temp
);
5731 * Emit fragment position/ooordinate code.
5734 emit_wpos(struct st_context
*st
,
5735 struct st_translate
*t
,
5736 const struct gl_program
*program
,
5737 struct ureg_program
*ureg
,
5738 int wpos_transform_const
)
5740 const struct gl_fragment_program
*fp
=
5741 (const struct gl_fragment_program
*) program
;
5742 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5743 GLfloat adjX
= 0.0f
;
5744 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5745 boolean invert
= FALSE
;
5747 /* Query the pixel center conventions supported by the pipe driver and set
5748 * adjX, adjY to help out if it cannot handle the requested one internally.
5750 * The bias of the y-coordinate depends on whether y-inversion takes place
5751 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5752 * drawing to an FBO (causes additional inversion), and whether the the pipe
5753 * driver origin and the requested origin differ (the latter condition is
5754 * stored in the 'invert' variable).
5756 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5758 * center shift only:
5763 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5764 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5765 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5766 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5768 * inversion and center shift:
5769 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5770 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5771 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5772 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5774 if (fp
->OriginUpperLeft
) {
5775 /* Fragment shader wants origin in upper-left */
5776 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5777 /* the driver supports upper-left origin */
5779 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5780 /* the driver supports lower-left origin, need to invert Y */
5781 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5782 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5789 /* Fragment shader wants origin in lower-left */
5790 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5791 /* the driver supports lower-left origin */
5792 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5793 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5794 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5795 /* the driver supports upper-left origin, need to invert Y */
5801 if (fp
->PixelCenterInteger
) {
5802 /* Fragment shader wants pixel center integer */
5803 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5804 /* the driver supports pixel center integer */
5806 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5807 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5809 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5810 /* the driver supports pixel center half integer, need to bias X,Y */
5819 /* Fragment shader wants pixel center half integer */
5820 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5821 /* the driver supports pixel center half integer */
5823 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5824 /* the driver supports pixel center integer, need to bias X,Y */
5825 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5826 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5827 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5833 /* we invert after adjustment so that we avoid the MOV to temporary,
5834 * and reuse the adjustment ADD instead */
5835 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5839 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5840 * TGSI uses +1 for front, -1 for back.
5841 * This function converts the TGSI value to the GL value. Simply clamping/
5842 * saturating the value to [0,1] does the job.
5845 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5847 struct ureg_program
*ureg
= t
->ureg
;
5848 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5849 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5851 if (ctx
->Const
.NativeIntegers
) {
5852 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5855 /* MOV_SAT face_temp, input[face] */
5856 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5859 /* Use face_temp as face input from here on: */
5860 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5864 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5865 unsigned *array_id
, unsigned *array_size
)
5869 for (i
= 0; i
< count
; i
++) {
5870 struct array_decl
*decl
= &arrays
[i
];
5872 if (attr
== decl
->mesa_index
) {
5873 *array_id
= decl
->array_id
;
5874 *array_size
= decl
->array_size
;
5875 assert(*array_size
);
5883 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5884 * \param program the program to translate
5885 * \param numInputs number of input registers used
5886 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5888 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5889 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5891 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5892 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5893 * \param numOutputs number of output registers used
5894 * \param outputMapping maps Mesa fragment program outputs to TGSI
5896 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5897 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5900 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5902 extern "C" enum pipe_error
5903 st_translate_program(
5904 struct gl_context
*ctx
,
5906 struct ureg_program
*ureg
,
5907 glsl_to_tgsi_visitor
*program
,
5908 const struct gl_program
*proginfo
,
5910 const GLuint inputMapping
[],
5911 const GLuint inputSlotToAttr
[],
5912 const ubyte inputSemanticName
[],
5913 const ubyte inputSemanticIndex
[],
5914 const GLuint interpMode
[],
5915 const GLuint interpLocation
[],
5917 const GLuint outputMapping
[],
5918 const GLuint outputSlotToAttr
[],
5919 const ubyte outputSemanticName
[],
5920 const ubyte outputSemanticIndex
[])
5922 struct st_translate
*t
;
5924 struct gl_program_constants
*frag_const
=
5925 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
5926 enum pipe_error ret
= PIPE_OK
;
5928 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5929 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5931 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5932 TGSI_SEMANTIC_FACE
);
5933 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5934 TGSI_SEMANTIC_VERTEXID
);
5935 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5936 TGSI_SEMANTIC_INSTANCEID
);
5937 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5938 TGSI_SEMANTIC_SAMPLEID
);
5939 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5940 TGSI_SEMANTIC_SAMPLEPOS
);
5941 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5942 TGSI_SEMANTIC_SAMPLEMASK
);
5943 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5944 TGSI_SEMANTIC_INVOCATIONID
);
5945 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5946 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5947 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5948 TGSI_SEMANTIC_BASEVERTEX
);
5949 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5950 TGSI_SEMANTIC_TESSCOORD
);
5951 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_HELPER_INVOCATION
] ==
5952 TGSI_SEMANTIC_HELPER_INVOCATION
);
5953 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
] ==
5954 TGSI_SEMANTIC_THREAD_ID
);
5955 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_WORK_GROUP_ID
] ==
5956 TGSI_SEMANTIC_BLOCK_ID
);
5957 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_NUM_WORK_GROUPS
] ==
5958 TGSI_SEMANTIC_GRID_SIZE
);
5960 t
= CALLOC_STRUCT(st_translate
);
5962 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5966 t
->procType
= procType
;
5967 t
->inputMapping
= inputMapping
;
5968 t
->outputMapping
= outputMapping
;
5970 t
->num_temp_arrays
= program
->next_array
;
5971 if (t
->num_temp_arrays
)
5972 t
->arrays
= (struct ureg_dst
*)
5973 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5976 * Declare input attributes.
5979 case TGSI_PROCESSOR_FRAGMENT
:
5980 for (i
= 0; i
< numInputs
; i
++) {
5981 unsigned array_id
= 0;
5982 unsigned array_size
;
5984 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5985 program
->num_input_arrays
, &array_id
, &array_size
)) {
5986 /* We've found an array. Declare it so. */
5987 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5988 inputSemanticName
[i
], inputSemanticIndex
[i
],
5989 interpMode
[i
], 0, interpLocation
[i
],
5990 array_id
, array_size
);
5991 i
+= array_size
- 1;
5994 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5995 inputSemanticName
[i
], inputSemanticIndex
[i
],
5996 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
6000 case TGSI_PROCESSOR_GEOMETRY
:
6001 case TGSI_PROCESSOR_TESS_EVAL
:
6002 case TGSI_PROCESSOR_TESS_CTRL
:
6003 for (i
= 0; i
< numInputs
; i
++) {
6004 unsigned array_id
= 0;
6005 unsigned array_size
;
6007 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6008 program
->num_input_arrays
, &array_id
, &array_size
)) {
6009 /* We've found an array. Declare it so. */
6010 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6011 inputSemanticIndex
[i
],
6012 array_id
, array_size
);
6013 i
+= array_size
- 1;
6016 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6017 inputSemanticIndex
[i
], 0, 1);
6021 case TGSI_PROCESSOR_VERTEX
:
6022 for (i
= 0; i
< numInputs
; i
++) {
6023 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6026 case TGSI_PROCESSOR_COMPUTE
:
6033 * Declare output attributes.
6036 case TGSI_PROCESSOR_FRAGMENT
:
6037 case TGSI_PROCESSOR_COMPUTE
:
6039 case TGSI_PROCESSOR_GEOMETRY
:
6040 case TGSI_PROCESSOR_TESS_EVAL
:
6041 case TGSI_PROCESSOR_TESS_CTRL
:
6042 case TGSI_PROCESSOR_VERTEX
:
6043 for (i
= 0; i
< numOutputs
; i
++) {
6044 unsigned array_id
= 0;
6045 unsigned array_size
;
6047 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
6048 program
->num_output_arrays
, &array_id
, &array_size
)) {
6049 /* We've found an array. Declare it so. */
6050 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
6051 outputSemanticName
[i
],
6052 outputSemanticIndex
[i
],
6053 array_id
, array_size
);
6054 i
+= array_size
- 1;
6057 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6058 outputSemanticName
[i
],
6059 outputSemanticIndex
[i
]);
6067 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
6068 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6069 /* Must do this after setting up t->inputs. */
6070 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6071 program
->wpos_transform_const
);
6074 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6075 emit_face_var(ctx
, t
);
6077 for (i
= 0; i
< numOutputs
; i
++) {
6078 switch (outputSemanticName
[i
]) {
6079 case TGSI_SEMANTIC_POSITION
:
6080 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6081 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6082 outputSemanticIndex
[i
]);
6083 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6085 case TGSI_SEMANTIC_STENCIL
:
6086 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6087 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6088 outputSemanticIndex
[i
]);
6089 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6091 case TGSI_SEMANTIC_COLOR
:
6092 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6093 TGSI_SEMANTIC_COLOR
,
6094 outputSemanticIndex
[i
]);
6096 case TGSI_SEMANTIC_SAMPLEMASK
:
6097 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6098 TGSI_SEMANTIC_SAMPLEMASK
,
6099 outputSemanticIndex
[i
]);
6100 /* TODO: If we ever support more than 32 samples, this will have
6101 * to become an array.
6103 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6106 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6107 ret
= PIPE_ERROR_BAD_INPUT
;
6112 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
6113 for (i
= 0; i
< numOutputs
; i
++) {
6114 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6115 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6117 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6118 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6119 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6124 /* Declare address register.
6126 if (program
->num_address_regs
> 0) {
6127 assert(program
->num_address_regs
<= 3);
6128 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6129 t
->address
[i
] = ureg_DECL_address(ureg
);
6132 /* Declare misc input registers
6135 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6137 for (i
= 0; sysInputs
; i
++) {
6138 if (sysInputs
& (1 << i
)) {
6139 unsigned semName
= _mesa_sysval_to_semantic
[i
];
6141 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6143 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6144 semName
== TGSI_SEMANTIC_VERTEXID
) {
6145 /* From Gallium perspective, these system values are always
6146 * integer, and require native integer support. However, if
6147 * native integer is supported on the vertex stage but not the
6148 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6149 * assumes these system values are floats. To resolve the
6150 * inconsistency, we insert a U2F.
6152 struct st_context
*st
= st_context(ctx
);
6153 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6154 assert(procType
== TGSI_PROCESSOR_VERTEX
);
6155 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6157 if (!ctx
->Const
.NativeIntegers
) {
6158 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6159 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6160 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6164 if (procType
== TGSI_PROCESSOR_FRAGMENT
&&
6165 semName
== TGSI_SEMANTIC_POSITION
)
6166 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6167 program
->wpos_transform_const
);
6169 sysInputs
&= ~(1 << i
);
6174 t
->array_sizes
= program
->array_sizes
;
6175 t
->input_arrays
= program
->input_arrays
;
6176 t
->output_arrays
= program
->output_arrays
;
6178 /* Emit constants and uniforms. TGSI uses a single index space for these,
6179 * so we put all the translated regs in t->constants.
6181 if (proginfo
->Parameters
) {
6182 t
->constants
= (struct ureg_src
*)
6183 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6184 if (t
->constants
== NULL
) {
6185 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6188 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6190 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6191 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6192 case PROGRAM_STATE_VAR
:
6193 case PROGRAM_UNIFORM
:
6194 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6197 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6198 * addressing of the const buffer.
6199 * FIXME: Be smarter and recognize param arrays:
6200 * indirect addressing is only valid within the referenced
6203 case PROGRAM_CONSTANT
:
6204 if (program
->indirect_addr_consts
)
6205 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6207 t
->constants
[i
] = emit_immediate(t
,
6208 proginfo
->Parameters
->ParameterValues
[i
],
6209 proginfo
->Parameters
->Parameters
[i
].DataType
,
6218 if (program
->shader
) {
6219 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6221 for (i
= 0; i
< num_ubos
; i
++) {
6222 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6223 unsigned num_const_vecs
= (size
+ 15) / 16;
6224 unsigned first
, last
;
6225 assert(num_const_vecs
> 0);
6227 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6228 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6232 /* Emit immediate values.
6234 t
->immediates
= (struct ureg_src
*)
6235 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6236 if (t
->immediates
== NULL
) {
6237 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6240 t
->num_immediates
= program
->num_immediates
;
6243 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6244 assert(i
< program
->num_immediates
);
6245 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6247 assert(i
== program
->num_immediates
);
6249 /* texture samplers */
6250 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6251 if (program
->samplers_used
& (1 << i
)) {
6254 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6256 switch (program
->sampler_types
[i
]) {
6258 type
= TGSI_RETURN_TYPE_SINT
;
6260 case GLSL_TYPE_UINT
:
6261 type
= TGSI_RETURN_TYPE_UINT
;
6263 case GLSL_TYPE_FLOAT
:
6264 type
= TGSI_RETURN_TYPE_FLOAT
;
6267 unreachable("not reached");
6270 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6271 type
, type
, type
, type
);
6275 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6276 if (program
->buffers_used
& (1 << i
)) {
6277 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6281 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6283 if (program
->buffers_used
& (1 << i
)) {
6284 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6288 if (program
->use_shared_memory
)
6289 t
->shared_memory
= ureg_DECL_shared_memory(ureg
);
6291 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6292 if (program
->images_used
& (1 << i
)) {
6293 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6294 program
->image_targets
[i
],
6295 program
->image_formats
[i
],
6300 /* Emit each instruction in turn:
6302 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6303 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6304 compile_tgsi_instruction(t
, inst
);
6307 /* Fix up all emitted labels:
6309 for (i
= 0; i
< t
->labels_count
; i
++) {
6310 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6311 t
->insn
[t
->labels
[i
].branch_target
]);
6321 t
->num_constants
= 0;
6322 free(t
->immediates
);
6323 t
->num_immediates
= 0;
6326 debug_printf("%s: translate error flag set\n", __func__
);
6334 /* ----------------------------- End TGSI code ------------------------------ */
6338 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6339 * generating Mesa IR.
6341 static struct gl_program
*
6342 get_mesa_program(struct gl_context
*ctx
,
6343 struct gl_shader_program
*shader_program
,
6344 struct gl_shader
*shader
)
6346 glsl_to_tgsi_visitor
* v
;
6347 struct gl_program
*prog
;
6348 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6350 struct gl_shader_compiler_options
*options
=
6351 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
6352 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6353 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6355 validate_ir_tree(shader
->ir
);
6357 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6360 prog
->Parameters
= _mesa_new_parameter_list();
6361 v
= new glsl_to_tgsi_visitor();
6364 v
->shader_program
= shader_program
;
6366 v
->options
= options
;
6367 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6368 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6370 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6371 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6372 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6373 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6375 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6376 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6379 /* Remove reads from output registers. */
6380 lower_output_reads(shader
->Stage
, shader
->ir
);
6382 /* Emit intermediate IR for main(). */
6383 visit_exec_list(shader
->ir
, v
);
6385 /* Now emit bodies for any functions that were used. */
6387 progress
= GL_FALSE
;
6389 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6390 if (!entry
->bgn_inst
) {
6391 v
->current_function
= entry
;
6393 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6394 entry
->bgn_inst
->function
= entry
;
6396 visit_exec_list(&entry
->sig
->body
, v
);
6398 glsl_to_tgsi_instruction
*last
;
6399 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6400 if (last
->op
!= TGSI_OPCODE_RET
)
6401 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6403 glsl_to_tgsi_instruction
*end
;
6404 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6405 end
->function
= entry
;
6413 /* Print out some information (for debugging purposes) used by the
6414 * optimization passes. */
6417 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6418 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6419 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6420 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6422 for (i
= 0; i
< v
->next_temp
; i
++) {
6423 first_writes
[i
] = -1;
6424 first_reads
[i
] = -1;
6425 last_writes
[i
] = -1;
6428 v
->get_first_temp_read(first_reads
);
6429 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6430 v
->get_last_temp_write(last_writes
);
6431 for (i
= 0; i
< v
->next_temp
; i
++)
6432 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6436 ralloc_free(first_writes
);
6437 ralloc_free(first_reads
);
6438 ralloc_free(last_writes
);
6439 ralloc_free(last_reads
);
6443 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6446 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
6447 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
6448 v
->copy_propagate();
6450 while (v
->eliminate_dead_code());
6452 v
->merge_two_dsts();
6453 v
->merge_registers();
6454 v
->renumber_registers();
6456 /* Write the END instruction. */
6457 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6459 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6461 _mesa_log("GLSL IR for linked %s program %d:\n",
6462 _mesa_shader_stage_to_string(shader
->Stage
),
6463 shader_program
->Name
);
6464 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6468 prog
->Instructions
= NULL
;
6469 prog
->NumInstructions
= 0;
6471 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6472 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
6473 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
6474 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
6475 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
6476 count_resources(v
, prog
);
6478 /* The GLSL IR won't be needed anymore. */
6479 ralloc_free(shader
->ir
);
6482 /* This must be done before the uniform storage is associated. */
6483 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
6484 (prog
->InputsRead
& VARYING_BIT_POS
||
6485 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6486 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6487 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6490 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6491 wposTransformState
);
6494 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6496 /* Avoid reallocation of the program parameter list, because the uniform
6497 * storage is only associated with the original parameter list.
6498 * This should be enough for Bitmap and DrawPixels constants.
6500 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6502 /* This has to be done last. Any operation the can cause
6503 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6504 * program constant) has to happen before creating this linkage.
6506 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6507 if (!shader_program
->LinkStatus
) {
6508 free_glsl_to_tgsi_visitor(v
);
6512 struct st_vertex_program
*stvp
;
6513 struct st_fragment_program
*stfp
;
6514 struct st_geometry_program
*stgp
;
6515 struct st_tessctrl_program
*sttcp
;
6516 struct st_tesseval_program
*sttep
;
6517 struct st_compute_program
*stcp
;
6519 switch (shader
->Type
) {
6520 case GL_VERTEX_SHADER
:
6521 stvp
= (struct st_vertex_program
*)prog
;
6522 stvp
->glsl_to_tgsi
= v
;
6524 case GL_FRAGMENT_SHADER
:
6525 stfp
= (struct st_fragment_program
*)prog
;
6526 stfp
->glsl_to_tgsi
= v
;
6528 case GL_GEOMETRY_SHADER
:
6529 stgp
= (struct st_geometry_program
*)prog
;
6530 stgp
->glsl_to_tgsi
= v
;
6532 case GL_TESS_CONTROL_SHADER
:
6533 sttcp
= (struct st_tessctrl_program
*)prog
;
6534 sttcp
->glsl_to_tgsi
= v
;
6536 case GL_TESS_EVALUATION_SHADER
:
6537 sttep
= (struct st_tesseval_program
*)prog
;
6538 sttep
->glsl_to_tgsi
= v
;
6540 case GL_COMPUTE_SHADER
:
6541 stcp
= (struct st_compute_program
*)prog
;
6542 stcp
->glsl_to_tgsi
= v
;
6545 assert(!"should not be reached");
6555 st_dump_program_for_shader_db(struct gl_context
*ctx
,
6556 struct gl_shader_program
*prog
)
6558 /* Dump only successfully compiled and linked shaders to the specified
6559 * file. This is for shader-db.
6561 * These options allow some pre-processing of shaders while dumping,
6562 * because some apps have ill-formed shaders.
6564 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
6565 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
6567 if (dump_filename
&& prog
->Name
!= 0) {
6568 FILE *f
= fopen(dump_filename
, "a");
6571 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
6572 const struct gl_shader
*sh
= prog
->Shaders
[i
];
6574 bool skip_version
= false;
6579 source
= sh
->Source
;
6581 /* This string mustn't be changed. shader-db uses it to find
6582 * where the shader begins.
6584 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
6585 _mesa_shader_stage_to_string(sh
->Stage
),
6588 /* Dump the forced version if set. */
6589 if (ctx
->Const
.ForceGLSLVersion
) {
6590 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
6591 skip_version
= true;
6594 /* Insert directives (optional). */
6595 if (insert_directives
) {
6596 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
6597 fprintf(f
, "#version %i\n", prog
->Version
);
6598 fprintf(f
, "%s\n", insert_directives
);
6599 skip_version
= true;
6602 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
6603 const char *next_line
= strstr(source
, "\n");
6606 source
= next_line
+ 1;
6611 fprintf(f
, "%s", source
);
6621 * Called via ctx->Driver.LinkShader()
6622 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6623 * with code lowering and other optimizations.
6626 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6628 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6629 assert(prog
->LinkStatus
);
6631 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6632 if (prog
->_LinkedShaders
[i
] == NULL
)
6636 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6637 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6638 const struct gl_shader_compiler_options
*options
=
6639 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6640 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6641 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6642 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6643 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6644 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6646 /* If there are forms of indirect addressing that the driver
6647 * cannot handle, perform the lowering pass.
6649 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6650 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6651 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6652 options
->EmitNoIndirectInput
,
6653 options
->EmitNoIndirectOutput
,
6654 options
->EmitNoIndirectTemp
,
6655 options
->EmitNoIndirectUniform
);
6658 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6659 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6660 LOWER_UNPACK_SNORM_2x16
|
6661 LOWER_PACK_UNORM_2x16
|
6662 LOWER_UNPACK_UNORM_2x16
|
6663 LOWER_PACK_SNORM_4x8
|
6664 LOWER_UNPACK_SNORM_4x8
|
6665 LOWER_UNPACK_UNORM_4x8
|
6666 LOWER_PACK_UNORM_4x8
;
6668 if (ctx
->Extensions
.ARB_gpu_shader5
)
6669 lower_inst
|= LOWER_PACK_USE_BFI
|
6671 if (!ctx
->st
->has_half_float_packing
)
6672 lower_inst
|= LOWER_PACK_HALF_2x16
|
6673 LOWER_UNPACK_HALF_2x16
;
6675 lower_packing_builtins(ir
, lower_inst
);
6678 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6679 lower_offset_arrays(ir
);
6680 do_mat_op_to_vec(ir
);
6681 lower_instructions(ir
,
6687 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6690 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6691 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6692 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6693 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6695 do_vec_index_to_cond_assign(ir
);
6696 lower_vector_insert(ir
, true);
6697 lower_quadop_vector(ir
, false);
6699 if (options
->MaxIfDepth
== 0) {
6706 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6708 progress
= do_common_optimization(ir
, true, true, options
,
6709 ctx
->Const
.NativeIntegers
)
6712 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6716 validate_ir_tree(ir
);
6719 build_program_resource_list(prog
);
6721 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6722 struct gl_program
*linked_prog
;
6724 if (prog
->_LinkedShaders
[i
] == NULL
)
6727 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6730 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6732 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6733 _mesa_shader_stage_to_program(i
),
6735 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6737 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6742 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6745 st_dump_program_for_shader_db(ctx
, prog
);
6750 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6751 const GLuint outputMapping
[],
6752 struct pipe_stream_output_info
*so
)
6755 struct gl_transform_feedback_info
*info
=
6756 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6758 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6759 so
->output
[i
].register_index
=
6760 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6761 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6762 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6763 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6764 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6765 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6768 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6769 so
->stride
[i
] = info
->BufferStride
[i
];
6771 so
->num_outputs
= info
->NumOutputs
;