2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "glsl_parser_extras.h"
36 #include "ir_optimization.h"
38 #include "main/errors.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "main/shaderapi.h"
42 #include "program/prog_instruction.h"
43 #include "program/sampler.h"
45 #include "pipe/p_context.h"
46 #include "pipe/p_screen.h"
47 #include "tgsi/tgsi_ureg.h"
48 #include "tgsi/tgsi_info.h"
49 #include "util/u_math.h"
50 #include "util/u_memory.h"
51 #include "st_program.h"
52 #include "st_mesa_to_tgsi.h"
55 #define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
56 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
57 (1 << PROGRAM_CONSTANT) | \
58 (1 << PROGRAM_UNIFORM))
60 #define MAX_GLSL_TEXTURE_OFFSET 4
65 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to TGSI ureg_src.
72 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
84 this->reladdr2
= NULL
;
85 this->has_index2
= false;
86 this->double_reg2
= false;
89 st_src_reg(gl_register_file file
, int index
, int type
)
95 this->swizzle
= SWIZZLE_XYZW
;
98 this->reladdr2
= NULL
;
99 this->has_index2
= false;
100 this->double_reg2
= false;
103 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
108 this->index2D
= index2D
;
109 this->swizzle
= SWIZZLE_XYZW
;
111 this->reladdr
= NULL
;
112 this->reladdr2
= NULL
;
113 this->has_index2
= false;
114 this->double_reg2
= false;
119 this->type
= GLSL_TYPE_ERROR
;
120 this->file
= PROGRAM_UNDEFINED
;
125 this->reladdr
= NULL
;
126 this->reladdr2
= NULL
;
127 this->has_index2
= false;
128 this->double_reg2
= false;
131 explicit st_src_reg(st_dst_reg reg
);
133 gl_register_file file
; /**< PROGRAM_* from Mesa */
134 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
136 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
137 int negate
; /**< NEGATE_XYZW mask from mesa */
138 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
139 /** Register index should be offset by the integer in this reg. */
141 st_src_reg
*reladdr2
;
144 * Is this the second half of a double register pair?
145 * currently used for input mapping only.
152 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
156 this->writemask
= writemask
;
157 this->cond_mask
= COND_TR
;
158 this->reladdr
= NULL
;
162 st_dst_reg(gl_register_file file
, int writemask
, int type
)
166 this->writemask
= writemask
;
167 this->cond_mask
= COND_TR
;
168 this->reladdr
= NULL
;
174 this->type
= GLSL_TYPE_ERROR
;
175 this->file
= PROGRAM_UNDEFINED
;
178 this->cond_mask
= COND_TR
;
179 this->reladdr
= NULL
;
182 explicit st_dst_reg(st_src_reg reg
);
184 gl_register_file file
; /**< PROGRAM_* from Mesa */
185 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
186 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
188 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
189 /** Register index should be offset by the integer in this reg. */
193 st_src_reg::st_src_reg(st_dst_reg reg
)
195 this->type
= reg
.type
;
196 this->file
= reg
.file
;
197 this->index
= reg
.index
;
198 this->swizzle
= SWIZZLE_XYZW
;
200 this->reladdr
= reg
.reladdr
;
202 this->reladdr2
= NULL
;
203 this->has_index2
= false;
204 this->double_reg2
= false;
207 st_dst_reg::st_dst_reg(st_src_reg reg
)
209 this->type
= reg
.type
;
210 this->file
= reg
.file
;
211 this->index
= reg
.index
;
212 this->writemask
= WRITEMASK_XYZW
;
213 this->cond_mask
= COND_TR
;
214 this->reladdr
= reg
.reladdr
;
217 class glsl_to_tgsi_instruction
: public exec_node
{
219 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
224 /** Pointer to the ir source this tree came from for debugging */
226 GLboolean cond_update
;
228 st_src_reg sampler
; /**< sampler register */
229 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
230 int tex_target
; /**< One of TEXTURE_*_INDEX */
231 GLboolean tex_shadow
;
233 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
234 unsigned tex_offset_num_offset
;
235 int dead_mask
; /**< Used in dead code elimination */
237 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
240 class variable_storage
: public exec_node
{
242 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
243 : file(file
), index(index
), var(var
)
248 gl_register_file file
;
250 ir_variable
*var
; /* variable that maps to this, if any */
253 class immediate_storage
: public exec_node
{
255 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
257 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
258 this->size32
= size32
;
262 /* doubles are stored across 2 gl_constant_values */
263 gl_constant_value values
[4];
264 int size32
; /**< Number of 32-bit components (1-4) */
265 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
268 class function_entry
: public exec_node
{
270 ir_function_signature
*sig
;
273 * identifier of this function signature used by the program.
275 * At the point that TGSI instructions for function calls are
276 * generated, we don't know the address of the first instruction of
277 * the function body. So we make the BranchTarget that is called a
278 * small integer and rewrite them during set_branchtargets().
283 * Pointer to first instruction of the function body.
285 * Set during function body emits after main() is processed.
287 glsl_to_tgsi_instruction
*bgn_inst
;
290 * Index of the first instruction of the function body in actual TGSI.
292 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
296 /** Storage for the return value. */
297 st_src_reg return_reg
;
300 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
301 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
303 struct glsl_to_tgsi_visitor
: public ir_visitor
{
305 glsl_to_tgsi_visitor();
306 ~glsl_to_tgsi_visitor();
308 function_entry
*current_function
;
310 struct gl_context
*ctx
;
311 struct gl_program
*prog
;
312 struct gl_shader_program
*shader_program
;
313 struct gl_shader
*shader
;
314 struct gl_shader_compiler_options
*options
;
318 unsigned *array_sizes
;
319 unsigned max_num_arrays
;
322 int num_address_regs
;
324 bool indirect_addr_consts
;
325 int wpos_transform_const
;
328 bool native_integers
;
332 variable_storage
*find_variable_storage(ir_variable
*var
);
334 int add_constant(gl_register_file file
, gl_constant_value values
[8],
335 int size
, int datatype
, GLuint
*swizzle_out
);
337 function_entry
*get_function_signature(ir_function_signature
*sig
);
339 st_src_reg
get_temp(const glsl_type
*type
);
340 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
342 st_src_reg
st_src_reg_for_double(double val
);
343 st_src_reg
st_src_reg_for_float(float val
);
344 st_src_reg
st_src_reg_for_int(int val
);
345 st_src_reg
st_src_reg_for_type(int type
, int val
);
348 * \name Visit methods
350 * As typical for the visitor pattern, there must be one \c visit method for
351 * each concrete subclass of \c ir_instruction. Virtual base classes within
352 * the hierarchy should not have \c visit methods.
355 virtual void visit(ir_variable
*);
356 virtual void visit(ir_loop
*);
357 virtual void visit(ir_loop_jump
*);
358 virtual void visit(ir_function_signature
*);
359 virtual void visit(ir_function
*);
360 virtual void visit(ir_expression
*);
361 virtual void visit(ir_swizzle
*);
362 virtual void visit(ir_dereference_variable
*);
363 virtual void visit(ir_dereference_array
*);
364 virtual void visit(ir_dereference_record
*);
365 virtual void visit(ir_assignment
*);
366 virtual void visit(ir_constant
*);
367 virtual void visit(ir_call
*);
368 virtual void visit(ir_return
*);
369 virtual void visit(ir_discard
*);
370 virtual void visit(ir_texture
*);
371 virtual void visit(ir_if
*);
372 virtual void visit(ir_emit_vertex
*);
373 virtual void visit(ir_end_primitive
*);
378 /** List of variable_storage */
381 /** List of immediate_storage */
382 exec_list immediates
;
383 unsigned num_immediates
;
385 /** List of function_entry */
386 exec_list function_signatures
;
387 int next_signature_id
;
389 /** List of glsl_to_tgsi_instruction */
390 exec_list instructions
;
392 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
393 st_dst_reg dst
= undef_dst
,
394 st_src_reg src0
= undef_src
,
395 st_src_reg src1
= undef_src
,
396 st_src_reg src2
= undef_src
,
397 st_src_reg src3
= undef_src
);
399 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
400 st_dst_reg dst
, st_dst_reg dst1
,
401 st_src_reg src0
= undef_src
,
402 st_src_reg src1
= undef_src
,
403 st_src_reg src2
= undef_src
,
404 st_src_reg src3
= undef_src
);
406 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
408 st_src_reg src0
, st_src_reg src1
);
411 * Emit the correct dot-product instruction for the type of arguments
413 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
419 void emit_scalar(ir_instruction
*ir
, unsigned op
,
420 st_dst_reg dst
, st_src_reg src0
);
422 void emit_scalar(ir_instruction
*ir
, unsigned op
,
423 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
425 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
427 bool try_emit_mad(ir_expression
*ir
,
429 bool try_emit_mad_for_and_not(ir_expression
*ir
,
432 void emit_swz(ir_expression
*ir
);
434 bool process_move_condition(ir_rvalue
*ir
);
436 void simplify_cmp(void);
438 void rename_temp_register(int index
, int new_index
);
439 int get_first_temp_read(int index
);
440 int get_first_temp_write(int index
);
441 int get_last_temp_read(int index
);
442 int get_last_temp_write(int index
);
444 void copy_propagate(void);
445 int eliminate_dead_code(void);
447 void merge_two_dsts(void);
448 void merge_registers(void);
449 void renumber_registers(void);
451 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
452 st_dst_reg
*l
, st_src_reg
*r
,
453 st_src_reg
*cond
, bool cond_swap
);
458 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
459 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
460 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
463 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
466 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
470 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
473 prog
->LinkStatus
= GL_FALSE
;
477 swizzle_for_size(int size
)
479 static const int size_swizzles
[4] = {
480 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
481 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
482 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
483 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
486 assert((size
>= 1) && (size
<= 4));
487 return size_swizzles
[size
- 1];
491 is_tex_instruction(unsigned opcode
)
493 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
498 num_inst_dst_regs(unsigned opcode
)
500 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
501 return info
->num_dst
;
505 num_inst_src_regs(unsigned opcode
)
507 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
508 return info
->is_tex
? info
->num_src
- 1 : info
->num_src
;
511 glsl_to_tgsi_instruction
*
512 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
513 st_dst_reg dst
, st_dst_reg dst1
,
514 st_src_reg src0
, st_src_reg src1
,
515 st_src_reg src2
, st_src_reg src3
)
517 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
518 int num_reladdr
= 0, i
, j
;
520 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
522 /* If we have to do relative addressing, we want to load the ARL
523 * reg directly for one of the regs, and preload the other reladdr
524 * sources into temps.
526 num_reladdr
+= dst
.reladdr
!= NULL
;
527 num_reladdr
+= dst1
.reladdr
!= NULL
;
528 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
529 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
530 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
531 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
533 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
534 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
535 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
536 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
539 emit_arl(ir
, address_reg
, *dst
.reladdr
);
543 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
546 assert(num_reladdr
== 0);
558 inst
->function
= NULL
;
560 /* Update indirect addressing status used by TGSI */
563 case PROGRAM_STATE_VAR
:
564 case PROGRAM_CONSTANT
:
565 case PROGRAM_UNIFORM
:
566 this->indirect_addr_consts
= true;
568 case PROGRAM_IMMEDIATE
:
569 assert(!"immediates should not have indirect addressing");
576 for (i
= 0; i
< 4; i
++) {
577 if(inst
->src
[i
].reladdr
) {
578 switch(inst
->src
[i
].file
) {
579 case PROGRAM_STATE_VAR
:
580 case PROGRAM_CONSTANT
:
581 case PROGRAM_UNIFORM
:
582 this->indirect_addr_consts
= true;
584 case PROGRAM_IMMEDIATE
:
585 assert(!"immediates should not have indirect addressing");
594 this->instructions
.push_tail(inst
);
597 * This section contains the double processing.
598 * GLSL just represents doubles as single channel values,
599 * however most HW and TGSI represent doubles as pairs of register channels.
601 * so we have to fixup destination writemask/index and src swizzle/indexes.
602 * dest writemasks need to translate from single channel write mask
603 * to a dual-channel writemask, but also need to modify the index,
604 * if we are touching the Z,W fields in the pre-translated writemask.
606 * src channels have similiar index modifications along with swizzle
607 * changes to we pick the XY, ZW pairs from the correct index.
609 * GLSL [0].x -> TGSI [0].xy
610 * GLSL [0].y -> TGSI [0].zw
611 * GLSL [0].z -> TGSI [1].xy
612 * GLSL [0].w -> TGSI [1].zw
614 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
|| inst
->dst
[1].type
== GLSL_TYPE_DOUBLE
||
615 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
616 glsl_to_tgsi_instruction
*dinst
= NULL
;
617 int initial_src_swz
[4], initial_src_idx
[4];
618 int initial_dst_idx
[2], initial_dst_writemask
[2];
619 /* select the writemask for dst0 or dst1 */
620 unsigned writemask
= inst
->dst
[0].file
== PROGRAM_UNDEFINED
? inst
->dst
[1].writemask
: inst
->dst
[0].writemask
;
622 /* copy out the writemask, index and swizzles for all src/dsts. */
623 for (j
= 0; j
< 2; j
++) {
624 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
625 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
628 for (j
= 0; j
< 4; j
++) {
629 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
630 initial_src_idx
[j
] = inst
->src
[j
].index
;
634 * scan all the components in the dst writemask
635 * generate an instruction for each of them if required.
639 int i
= u_bit_scan(&writemask
);
641 /* first time use previous instruction */
645 /* create a new instructions for subsequent attempts */
646 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
650 this->instructions
.push_tail(dinst
);
653 /* modify the destination if we are splitting */
654 for (j
= 0; j
< 2; j
++) {
655 if (dinst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
) {
656 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
657 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
659 dinst
->dst
[j
].index
++;
661 /* if we aren't writing to a double, just get the bit of the initial writemask
663 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
667 /* modify the src registers */
668 for (j
= 0; j
< 4; j
++) {
669 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
671 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
672 dinst
->src
[j
].index
= initial_src_idx
[j
];
674 dinst
->src
[j
].double_reg2
= true;
675 dinst
->src
[j
].index
++;
679 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
681 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
684 /* some opcodes are special case in what they use as sources
685 - F2D is a float src0, DLDEXP is integer src1 */
686 if (op
== TGSI_OPCODE_F2D
||
687 op
== TGSI_OPCODE_DLDEXP
||
688 (op
== TGSI_OPCODE_UCMP
&& dinst
->dst
[0].type
== GLSL_TYPE_DOUBLE
)) {
689 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
701 glsl_to_tgsi_instruction
*
702 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
704 st_src_reg src0
, st_src_reg src1
,
705 st_src_reg src2
, st_src_reg src3
)
707 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
711 * Determines whether to use an integer, unsigned integer, or float opcode
712 * based on the operands and input opcode, then emits the result.
715 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
717 st_src_reg src0
, st_src_reg src1
)
719 int type
= GLSL_TYPE_FLOAT
;
721 if (op
== TGSI_OPCODE_MOV
)
724 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
725 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
726 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
727 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
729 if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
730 type
= GLSL_TYPE_DOUBLE
;
731 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
732 type
= GLSL_TYPE_FLOAT
;
733 else if (native_integers
)
734 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
736 #define case5(c, f, i, u, d) \
737 case TGSI_OPCODE_##c: \
738 if (type == GLSL_TYPE_DOUBLE) \
739 op = TGSI_OPCODE_##d; \
740 else if (type == GLSL_TYPE_INT) \
741 op = TGSI_OPCODE_##i; \
742 else if (type == GLSL_TYPE_UINT) \
743 op = TGSI_OPCODE_##u; \
745 op = TGSI_OPCODE_##f; \
748 #define case4(c, f, i, u) \
749 case TGSI_OPCODE_##c: \
750 if (type == GLSL_TYPE_INT) \
751 op = TGSI_OPCODE_##i; \
752 else if (type == GLSL_TYPE_UINT) \
753 op = TGSI_OPCODE_##u; \
755 op = TGSI_OPCODE_##f; \
758 #define case3(f, i, u) case4(f, f, i, u)
759 #define case4d(f, i, u, d) case5(f, f, i, u, d)
760 #define case3fid(f, i, d) case5(f, f, i, i, d)
761 #define case2fi(f, i) case4(f, f, i, i)
762 #define case2iu(i, u) case4(i, LAST, i, u)
764 #define casecomp(c, f, i, u, d) \
765 case TGSI_OPCODE_##c: \
766 if (type == GLSL_TYPE_DOUBLE) \
767 op = TGSI_OPCODE_##d; \
768 else if (type == GLSL_TYPE_INT) \
769 op = TGSI_OPCODE_##i; \
770 else if (type == GLSL_TYPE_UINT) \
771 op = TGSI_OPCODE_##u; \
772 else if (native_integers) \
773 op = TGSI_OPCODE_##f; \
775 op = TGSI_OPCODE_##c; \
779 case3fid(ADD
, UADD
, DADD
);
780 case3fid(MUL
, UMUL
, DMUL
);
781 case3fid(MAD
, UMAD
, DMAD
);
782 case3fid(FMA
, UMAD
, DFMA
);
783 case3(DIV
, IDIV
, UDIV
);
784 case4d(MAX
, IMAX
, UMAX
, DMAX
);
785 case4d(MIN
, IMIN
, UMIN
, DMIN
);
788 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
789 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
790 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
791 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
795 case3fid(SSG
, ISSG
, DSSG
);
796 case3fid(ABS
, IABS
, DABS
);
800 case2iu(IMUL_HI
, UMUL_HI
);
802 case3fid(SQRT
, SQRT
, DSQRT
);
804 case3fid(RCP
, RCP
, DRCP
);
805 case3fid(RSQ
, RSQ
, DRSQ
);
807 case3fid(FRC
, FRC
, DFRAC
);
808 case3fid(TRUNC
, TRUNC
, DTRUNC
);
809 case3fid(CEIL
, CEIL
, DCEIL
);
810 case3fid(FLR
, FLR
, DFLR
);
811 case3fid(ROUND
, ROUND
, DROUND
);
816 assert(op
!= TGSI_OPCODE_LAST
);
820 glsl_to_tgsi_instruction
*
821 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
822 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
825 static const unsigned dot_opcodes
[] = {
826 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
829 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
833 * Emits TGSI scalar opcodes to produce unique answers across channels.
835 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
836 * channel determines the result across all channels. So to do a vec4
837 * of this operation, we want to emit a scalar per source channel used
838 * to produce dest channels.
841 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
843 st_src_reg orig_src0
, st_src_reg orig_src1
)
846 int done_mask
= ~dst
.writemask
;
848 /* TGSI RCP is a scalar operation splatting results to all channels,
849 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
852 for (i
= 0; i
< 4; i
++) {
853 GLuint this_mask
= (1 << i
);
854 st_src_reg src0
= orig_src0
;
855 st_src_reg src1
= orig_src1
;
857 if (done_mask
& this_mask
)
860 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
861 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
862 for (j
= i
+ 1; j
< 4; j
++) {
863 /* If there is another enabled component in the destination that is
864 * derived from the same inputs, generate its value on this pass as
867 if (!(done_mask
& (1 << j
)) &&
868 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
869 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
870 this_mask
|= (1 << j
);
873 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
874 src0_swiz
, src0_swiz
);
875 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
876 src1_swiz
, src1_swiz
);
878 dst
.writemask
= this_mask
;
879 emit_asm(ir
, op
, dst
, src0
, src1
);
880 done_mask
|= this_mask
;
885 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
886 st_dst_reg dst
, st_src_reg src0
)
888 st_src_reg undef
= undef_src
;
890 undef
.swizzle
= SWIZZLE_XXXX
;
892 emit_scalar(ir
, op
, dst
, src0
, undef
);
896 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
897 st_dst_reg dst
, st_src_reg src0
)
899 int op
= TGSI_OPCODE_ARL
;
901 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
902 op
= TGSI_OPCODE_UARL
;
904 assert(dst
.file
== PROGRAM_ADDRESS
);
905 if (dst
.index
>= this->num_address_regs
)
906 this->num_address_regs
= dst
.index
+ 1;
908 emit_asm(NULL
, op
, dst
, src0
);
912 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
913 gl_constant_value values
[8], int size
, int datatype
,
916 if (file
== PROGRAM_CONSTANT
) {
917 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
918 size
, datatype
, swizzle_out
);
921 assert(file
== PROGRAM_IMMEDIATE
);
924 immediate_storage
*entry
;
925 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
928 /* Search immediate storage to see if we already have an identical
929 * immediate that we can use instead of adding a duplicate entry.
931 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
932 immediate_storage
*tmp
= entry
;
934 for (i
= 0; i
* 4 < size32
; i
++) {
935 int slot_size
= MIN2(size32
- (i
* 4), 4);
936 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
938 if (memcmp(tmp
->values
, &values
[i
* 4],
939 slot_size
* sizeof(gl_constant_value
)))
942 /* Everything matches, keep going until the full size is matched */
943 tmp
= (immediate_storage
*)tmp
->next
;
946 /* The full value matched */
953 for (i
= 0; i
* 4 < size32
; i
++) {
954 int slot_size
= MIN2(size32
- (i
* 4), 4);
955 /* Add this immediate to the list. */
956 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
957 this->immediates
.push_tail(entry
);
958 this->num_immediates
++;
964 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
966 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
967 union gl_constant_value uval
;
970 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
976 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
978 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
979 union gl_constant_value uval
[2];
981 uval
[0].u
= *(uint32_t *)&val
;
982 uval
[1].u
= *(((uint32_t *)&val
) + 1);
983 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
989 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
991 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
992 union gl_constant_value uval
;
994 assert(native_integers
);
997 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1003 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1005 if (native_integers
)
1006 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1007 st_src_reg_for_int(val
);
1009 return st_src_reg_for_float(val
);
1013 type_size(const struct glsl_type
*type
)
1018 switch (type
->base_type
) {
1019 case GLSL_TYPE_UINT
:
1021 case GLSL_TYPE_FLOAT
:
1022 case GLSL_TYPE_BOOL
:
1023 if (type
->is_matrix()) {
1024 return type
->matrix_columns
;
1026 /* Regardless of size of vector, it gets a vec4. This is bad
1027 * packing for things like floats, but otherwise arrays become a
1028 * mess. Hopefully a later pass over the code can pack scalars
1029 * down if appropriate.
1034 case GLSL_TYPE_DOUBLE
:
1035 if (type
->is_matrix()) {
1036 if (type
->vector_elements
<= 2)
1037 return type
->matrix_columns
;
1039 return type
->matrix_columns
* 2;
1041 /* For doubles if we have a double or dvec2 they fit in one
1042 * vec4, else they need 2 vec4s.
1044 if (type
->vector_elements
<= 2)
1050 case GLSL_TYPE_ARRAY
:
1051 assert(type
->length
> 0);
1052 return type_size(type
->fields
.array
) * type
->length
;
1053 case GLSL_TYPE_STRUCT
:
1055 for (i
= 0; i
< type
->length
; i
++) {
1056 size
+= type_size(type
->fields
.structure
[i
].type
);
1059 case GLSL_TYPE_SAMPLER
:
1060 case GLSL_TYPE_IMAGE
:
1061 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1065 case GLSL_TYPE_ATOMIC_UINT
:
1066 case GLSL_TYPE_INTERFACE
:
1067 case GLSL_TYPE_VOID
:
1068 case GLSL_TYPE_ERROR
:
1069 assert(!"Invalid type in type_size");
1076 * In the initial pass of codegen, we assign temporary numbers to
1077 * intermediate results. (not SSA -- variable assignments will reuse
1081 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1085 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1089 if (!options
->EmitNoIndirectTemp
&&
1090 (type
->is_array() || type
->is_matrix())) {
1092 if (next_array
>= max_num_arrays
) {
1093 max_num_arrays
+= 32;
1094 array_sizes
= (unsigned*)
1095 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1098 src
.file
= PROGRAM_ARRAY
;
1099 src
.index
= next_array
<< 16 | 0x8000;
1100 array_sizes
[next_array
] = type_size(type
);
1104 src
.file
= PROGRAM_TEMPORARY
;
1105 src
.index
= next_temp
;
1106 next_temp
+= type_size(type
);
1109 if (type
->is_array() || type
->is_record()) {
1110 src
.swizzle
= SWIZZLE_NOOP
;
1112 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1119 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1122 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1123 if (entry
->var
== var
)
1131 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1133 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1134 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1136 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1137 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1140 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1142 const ir_state_slot
*const slots
= ir
->get_state_slots();
1143 assert(slots
!= NULL
);
1145 /* Check if this statevar's setup in the STATE file exactly
1146 * matches how we'll want to reference it as a
1147 * struct/array/whatever. If not, then we need to move it into
1148 * temporary storage and hope that it'll get copy-propagated
1151 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1152 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1157 variable_storage
*storage
;
1159 if (i
== ir
->get_num_state_slots()) {
1160 /* We'll set the index later. */
1161 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1162 this->variables
.push_tail(storage
);
1166 /* The variable_storage constructor allocates slots based on the size
1167 * of the type. However, this had better match the number of state
1168 * elements that we're going to copy into the new temporary.
1170 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1172 dst
= st_dst_reg(get_temp(ir
->type
));
1174 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1176 this->variables
.push_tail(storage
);
1180 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1181 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1182 (gl_state_index
*)slots
[i
].tokens
);
1184 if (storage
->file
== PROGRAM_STATE_VAR
) {
1185 if (storage
->index
== -1) {
1186 storage
->index
= index
;
1188 assert(index
== storage
->index
+ (int)i
);
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1196 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1197 src
.swizzle
= slots
[i
].swizzle
;
1198 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1204 if (storage
->file
== PROGRAM_TEMPORARY
&&
1205 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1206 fail_link(this->shader_program
,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir
->name
, dst
.index
- storage
->index
,
1209 type_size(ir
->type
));
1215 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1217 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1219 visit_exec_list(&ir
->body_instructions
, this);
1221 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1228 case ir_loop_jump::jump_break
:
1229 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1231 case ir_loop_jump::jump_continue
:
1232 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1239 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1246 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1251 if (strcmp(ir
->name
, "main") == 0) {
1252 const ir_function_signature
*sig
;
1255 sig
= ir
->matching_signature(NULL
, &empty
, false);
1259 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1268 int nonmul_operand
= 1 - mul_operand
;
1270 st_dst_reg result_dst
;
1272 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1273 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1276 expr
->operands
[0]->accept(this);
1278 expr
->operands
[1]->accept(this);
1280 ir
->operands
[nonmul_operand
]->accept(this);
1283 this->result
= get_temp(ir
->type
);
1284 result_dst
= st_dst_reg(this->result
);
1285 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1286 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1292 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1294 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1295 * implemented using multiplication, and logical-or is implemented using
1296 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1297 * As result, the logical expression (a & !b) can be rewritten as:
1301 * - (a * 1) - (a * b)
1305 * This final expression can be implemented as a single MAD(a, -b, a)
1309 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1311 const int other_operand
= 1 - try_operand
;
1314 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1315 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1318 ir
->operands
[other_operand
]->accept(this);
1320 expr
->operands
[0]->accept(this);
1323 b
.negate
= ~b
.negate
;
1325 this->result
= get_temp(ir
->type
);
1326 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1332 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1333 st_src_reg
*reg
, int *num_reladdr
)
1335 if (!reg
->reladdr
&& !reg
->reladdr2
)
1338 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1339 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1341 if (*num_reladdr
!= 1) {
1342 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1344 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1352 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1354 unsigned int operand
;
1355 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1356 st_src_reg result_src
;
1357 st_dst_reg result_dst
;
1359 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1361 if (ir
->operation
== ir_binop_add
) {
1362 if (try_emit_mad(ir
, 1))
1364 if (try_emit_mad(ir
, 0))
1368 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1370 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1371 if (try_emit_mad_for_and_not(ir
, 1))
1373 if (try_emit_mad_for_and_not(ir
, 0))
1377 if (ir
->operation
== ir_quadop_vector
)
1378 assert(!"ir_quadop_vector should have been lowered");
1380 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1381 this->result
.file
= PROGRAM_UNDEFINED
;
1382 ir
->operands
[operand
]->accept(this);
1383 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1384 printf("Failed to get tree for expression operand:\n");
1385 ir
->operands
[operand
]->print();
1389 op
[operand
] = this->result
;
1391 /* Matrix expression operands should have been broken down to vector
1392 * operations already.
1394 assert(!ir
->operands
[operand
]->type
->is_matrix());
1397 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1398 if (ir
->operands
[1]) {
1399 vector_elements
= MAX2(vector_elements
,
1400 ir
->operands
[1]->type
->vector_elements
);
1403 this->result
.file
= PROGRAM_UNDEFINED
;
1405 /* Storage for our result. Ideally for an assignment we'd be using
1406 * the actual storage for the result here, instead.
1408 result_src
= get_temp(ir
->type
);
1409 /* convenience for the emit functions below. */
1410 result_dst
= st_dst_reg(result_src
);
1411 /* Limit writes to the channels that will be used by result_src later.
1412 * This does limit this temp's use as a temporary for multi-instruction
1415 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1417 switch (ir
->operation
) {
1418 case ir_unop_logic_not
:
1419 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1420 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1422 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1423 * older GPUs implement SEQ using multiple instructions (i915 uses two
1424 * SGE instructions and a MUL instruction). Since our logic values are
1425 * 0.0 and 1.0, 1-x also implements !x.
1427 op
[0].negate
= ~op
[0].negate
;
1428 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1432 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1433 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1434 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1435 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1437 op
[0].negate
= ~op
[0].negate
;
1442 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1445 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1448 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1452 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1456 assert(!"not reached: should be handled by ir_explog_to_explog2");
1459 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1462 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1465 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1467 case ir_unop_saturate
: {
1468 glsl_to_tgsi_instruction
*inst
;
1469 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1470 inst
->saturate
= true;
1475 case ir_unop_dFdx_coarse
:
1476 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1478 case ir_unop_dFdx_fine
:
1479 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1482 case ir_unop_dFdy_coarse
:
1483 case ir_unop_dFdy_fine
:
1485 /* The X component contains 1 or -1 depending on whether the framebuffer
1486 * is a FBO or the window system buffer, respectively.
1487 * It is then multiplied with the source operand of DDY.
1489 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1490 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1492 unsigned transform_y_index
=
1493 _mesa_add_state_reference(this->prog
->Parameters
,
1496 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1498 glsl_type::vec4_type
);
1499 transform_y
.swizzle
= SWIZZLE_XXXX
;
1501 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1503 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1504 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1505 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1509 case ir_unop_frexp_sig
:
1510 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1513 case ir_unop_frexp_exp
:
1514 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1517 case ir_unop_noise
: {
1518 /* At some point, a motivated person could add a better
1519 * implementation of noise. Currently not even the nvidia
1520 * binary drivers do anything more than this. In any case, the
1521 * place to do this is in the GL state tracker, not the poor
1524 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1529 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1532 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1536 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1539 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1540 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1542 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1545 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1546 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1548 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1552 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1554 case ir_binop_greater
:
1555 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1557 case ir_binop_lequal
:
1558 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1560 case ir_binop_gequal
:
1561 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1563 case ir_binop_equal
:
1564 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1566 case ir_binop_nequal
:
1567 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1569 case ir_binop_all_equal
:
1570 /* "==" operator producing a scalar boolean. */
1571 if (ir
->operands
[0]->type
->is_vector() ||
1572 ir
->operands
[1]->type
->is_vector()) {
1573 st_src_reg temp
= get_temp(native_integers
?
1574 glsl_type::uvec4_type
:
1575 glsl_type::vec4_type
);
1577 if (native_integers
) {
1578 st_dst_reg temp_dst
= st_dst_reg(temp
);
1579 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1581 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1583 /* Emit 1-3 AND operations to combine the SEQ results. */
1584 switch (ir
->operands
[0]->type
->vector_elements
) {
1588 temp_dst
.writemask
= WRITEMASK_Y
;
1589 temp1
.swizzle
= SWIZZLE_YYYY
;
1590 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1591 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1594 temp_dst
.writemask
= WRITEMASK_X
;
1595 temp1
.swizzle
= SWIZZLE_XXXX
;
1596 temp2
.swizzle
= SWIZZLE_YYYY
;
1597 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1598 temp_dst
.writemask
= WRITEMASK_Y
;
1599 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1600 temp2
.swizzle
= SWIZZLE_WWWW
;
1601 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1604 temp1
.swizzle
= SWIZZLE_XXXX
;
1605 temp2
.swizzle
= SWIZZLE_YYYY
;
1606 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1608 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1610 /* After the dot-product, the value will be an integer on the
1611 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1613 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1615 /* Negating the result of the dot-product gives values on the range
1616 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1617 * This is achieved using SGE.
1619 st_src_reg sge_src
= result_src
;
1620 sge_src
.negate
= ~sge_src
.negate
;
1621 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1624 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1627 case ir_binop_any_nequal
:
1628 /* "!=" operator producing a scalar boolean. */
1629 if (ir
->operands
[0]->type
->is_vector() ||
1630 ir
->operands
[1]->type
->is_vector()) {
1631 st_src_reg temp
= get_temp(native_integers
?
1632 glsl_type::uvec4_type
:
1633 glsl_type::vec4_type
);
1634 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1636 if (native_integers
) {
1637 st_dst_reg temp_dst
= st_dst_reg(temp
);
1638 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1640 /* Emit 1-3 OR operations to combine the SNE results. */
1641 switch (ir
->operands
[0]->type
->vector_elements
) {
1645 temp_dst
.writemask
= WRITEMASK_Y
;
1646 temp1
.swizzle
= SWIZZLE_YYYY
;
1647 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1648 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1651 temp_dst
.writemask
= WRITEMASK_X
;
1652 temp1
.swizzle
= SWIZZLE_XXXX
;
1653 temp2
.swizzle
= SWIZZLE_YYYY
;
1654 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1655 temp_dst
.writemask
= WRITEMASK_Y
;
1656 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1657 temp2
.swizzle
= SWIZZLE_WWWW
;
1658 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1661 temp1
.swizzle
= SWIZZLE_XXXX
;
1662 temp2
.swizzle
= SWIZZLE_YYYY
;
1663 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1665 /* After the dot-product, the value will be an integer on the
1666 * range [0,4]. Zero stays zero, and positive values become 1.0.
1668 glsl_to_tgsi_instruction
*const dp
=
1669 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1670 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1671 /* The clamping to [0,1] can be done for free in the fragment
1672 * shader with a saturate.
1674 dp
->saturate
= true;
1676 /* Negating the result of the dot-product gives values on the range
1677 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1678 * achieved using SLT.
1680 st_src_reg slt_src
= result_src
;
1681 slt_src
.negate
= ~slt_src
.negate
;
1682 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1686 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1691 assert(ir
->operands
[0]->type
->is_vector());
1693 if (native_integers
) {
1694 int dst_swizzle
= 0, op0_swizzle
, i
;
1695 st_src_reg accum
= op
[0];
1697 op0_swizzle
= op
[0].swizzle
;
1698 accum
.swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 0),
1699 GET_SWZ(op0_swizzle
, 0),
1700 GET_SWZ(op0_swizzle
, 0),
1701 GET_SWZ(op0_swizzle
, 0));
1702 for (i
= 0; i
< 4; i
++) {
1703 if (result_dst
.writemask
& (1 << i
)) {
1704 dst_swizzle
= MAKE_SWIZZLE4(i
, i
, i
, i
);
1709 assert(ir
->operands
[0]->type
->is_boolean());
1711 /* OR all the components together, since they should be either 0 or ~0
1713 switch (ir
->operands
[0]->type
->vector_elements
) {
1715 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 3),
1716 GET_SWZ(op0_swizzle
, 3),
1717 GET_SWZ(op0_swizzle
, 3),
1718 GET_SWZ(op0_swizzle
, 3));
1719 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1720 accum
= st_src_reg(result_dst
);
1721 accum
.swizzle
= dst_swizzle
;
1724 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 2),
1725 GET_SWZ(op0_swizzle
, 2),
1726 GET_SWZ(op0_swizzle
, 2),
1727 GET_SWZ(op0_swizzle
, 2));
1728 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1729 accum
= st_src_reg(result_dst
);
1730 accum
.swizzle
= dst_swizzle
;
1733 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 1),
1734 GET_SWZ(op0_swizzle
, 1),
1735 GET_SWZ(op0_swizzle
, 1),
1736 GET_SWZ(op0_swizzle
, 1));
1737 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1740 assert(!"Unexpected vector size");
1744 /* After the dot-product, the value will be an integer on the
1745 * range [0,4]. Zero stays zero, and positive values become 1.0.
1747 glsl_to_tgsi_instruction
*const dp
=
1748 emit_dp(ir
, result_dst
, op
[0], op
[0],
1749 ir
->operands
[0]->type
->vector_elements
);
1750 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
1751 result_dst
.type
== GLSL_TYPE_FLOAT
) {
1752 /* The clamping to [0,1] can be done for free in the fragment
1753 * shader with a saturate.
1755 dp
->saturate
= true;
1756 } else if (result_dst
.type
== GLSL_TYPE_FLOAT
) {
1757 /* Negating the result of the dot-product gives values on the range
1758 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1759 * is achieved using SLT.
1761 st_src_reg slt_src
= result_src
;
1762 slt_src
.negate
= ~slt_src
.negate
;
1763 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1766 /* Use SNE 0 if integers are being used as boolean values. */
1767 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, result_src
, st_src_reg_for_int(0));
1773 case ir_binop_logic_xor
:
1774 if (native_integers
)
1775 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1777 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1780 case ir_binop_logic_or
: {
1781 if (native_integers
) {
1782 /* If integers are used as booleans, we can use an actual "or"
1785 assert(native_integers
);
1786 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1788 /* After the addition, the value will be an integer on the
1789 * range [0,2]. Zero stays zero, and positive values become 1.0.
1791 glsl_to_tgsi_instruction
*add
=
1792 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1793 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1794 /* The clamping to [0,1] can be done for free in the fragment
1795 * shader with a saturate if floats are being used as boolean values.
1797 add
->saturate
= true;
1799 /* Negating the result of the addition gives values on the range
1800 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1801 * is achieved using SLT.
1803 st_src_reg slt_src
= result_src
;
1804 slt_src
.negate
= ~slt_src
.negate
;
1805 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1811 case ir_binop_logic_and
:
1812 /* If native integers are disabled, the bool args are stored as float 0.0
1813 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1814 * actual AND opcode.
1816 if (native_integers
)
1817 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1819 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1823 assert(ir
->operands
[0]->type
->is_vector());
1824 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1825 emit_dp(ir
, result_dst
, op
[0], op
[1],
1826 ir
->operands
[0]->type
->vector_elements
);
1831 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1833 /* sqrt(x) = x * rsq(x). */
1834 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1835 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1836 /* For incoming channels <= 0, set the result to 0. */
1837 op
[0].negate
= ~op
[0].negate
;
1838 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1839 op
[0], result_src
, st_src_reg_for_float(0.0));
1843 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1846 if (native_integers
) {
1847 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1850 /* fallthrough to next case otherwise */
1852 if (native_integers
) {
1853 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1856 /* fallthrough to next case otherwise */
1859 /* Converting between signed and unsigned integers is a no-op. */
1863 if (native_integers
) {
1864 /* Booleans are stored as integers using ~0 for true and 0 for false.
1865 * GLSL requires that int(bool) return 1 for true and 0 for false.
1866 * This conversion is done with AND, but it could be done with NEG.
1868 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1870 /* Booleans and integers are both stored as floats when native
1871 * integers are disabled.
1877 if (native_integers
)
1878 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1880 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1883 if (native_integers
)
1884 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1886 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1888 case ir_unop_bitcast_f2i
:
1890 result_src
.type
= GLSL_TYPE_INT
;
1892 case ir_unop_bitcast_f2u
:
1894 result_src
.type
= GLSL_TYPE_UINT
;
1896 case ir_unop_bitcast_i2f
:
1897 case ir_unop_bitcast_u2f
:
1899 result_src
.type
= GLSL_TYPE_FLOAT
;
1902 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1908 if (native_integers
)
1909 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1911 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1914 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1917 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1920 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1922 case ir_unop_round_even
:
1923 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1926 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1930 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1933 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1936 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1939 case ir_unop_bit_not
:
1940 if (native_integers
) {
1941 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1945 if (native_integers
) {
1946 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1949 case ir_binop_lshift
:
1950 if (native_integers
) {
1951 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
1954 case ir_binop_rshift
:
1955 if (native_integers
) {
1956 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
1959 case ir_binop_bit_and
:
1960 if (native_integers
) {
1961 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1964 case ir_binop_bit_xor
:
1965 if (native_integers
) {
1966 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1969 case ir_binop_bit_or
:
1970 if (native_integers
) {
1971 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1975 assert(!"GLSL 1.30 features unsupported");
1978 case ir_binop_ubo_load
: {
1979 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1980 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1981 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1982 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
1983 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1986 cbuf
.type
= ir
->type
->base_type
;
1987 cbuf
.file
= PROGRAM_CONSTANT
;
1989 cbuf
.reladdr
= NULL
;
1992 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1994 if (const_offset_ir
) {
1995 /* Constant index into constant buffer */
1996 cbuf
.reladdr
= NULL
;
1997 cbuf
.index
= const_offset
/ 16;
2000 /* Relative/variable index into constant buffer */
2001 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2002 st_src_reg_for_int(4));
2003 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2004 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2007 if (const_uniform_block
) {
2008 /* Constant constant buffer */
2009 cbuf
.reladdr2
= NULL
;
2010 cbuf
.index2D
= const_block
;
2011 cbuf
.has_index2
= true;
2014 /* Relative/variable constant buffer */
2015 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2017 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2018 cbuf
.has_index2
= true;
2021 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2022 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2023 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2024 const_offset
% 16 / 8,
2025 const_offset
% 16 / 8,
2026 const_offset
% 16 / 8);
2028 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2029 const_offset
% 16 / 4,
2030 const_offset
% 16 / 4,
2031 const_offset
% 16 / 4);
2033 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2034 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2036 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2041 /* note: we have to reorder the three args here */
2042 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2045 if (this->ctx
->Const
.NativeIntegers
)
2046 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2048 op
[0].negate
= ~op
[0].negate
;
2049 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2052 case ir_triop_bitfield_extract
:
2053 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2055 case ir_quadop_bitfield_insert
:
2056 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2058 case ir_unop_bitfield_reverse
:
2059 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2061 case ir_unop_bit_count
:
2062 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2064 case ir_unop_find_msb
:
2065 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2067 case ir_unop_find_lsb
:
2068 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2070 case ir_binop_imul_high
:
2071 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2074 /* In theory, MAD is incorrect here. */
2076 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2078 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2080 case ir_unop_interpolate_at_centroid
:
2081 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2083 case ir_binop_interpolate_at_offset
:
2084 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2086 case ir_binop_interpolate_at_sample
:
2087 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2091 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2094 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2097 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2100 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2103 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2106 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2108 case ir_unop_unpack_double_2x32
:
2109 case ir_unop_pack_double_2x32
:
2110 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2113 case ir_binop_ldexp
:
2114 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2115 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2117 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2121 case ir_unop_pack_snorm_2x16
:
2122 case ir_unop_pack_unorm_2x16
:
2123 case ir_unop_pack_half_2x16
:
2124 case ir_unop_pack_snorm_4x8
:
2125 case ir_unop_pack_unorm_4x8
:
2127 case ir_unop_unpack_snorm_2x16
:
2128 case ir_unop_unpack_unorm_2x16
:
2129 case ir_unop_unpack_half_2x16
:
2130 case ir_unop_unpack_half_2x16_split_x
:
2131 case ir_unop_unpack_half_2x16_split_y
:
2132 case ir_unop_unpack_snorm_4x8
:
2133 case ir_unop_unpack_unorm_4x8
:
2135 case ir_binop_pack_half_2x16_split
:
2138 case ir_quadop_vector
:
2139 case ir_binop_vector_extract
:
2140 case ir_triop_vector_insert
:
2141 case ir_binop_carry
:
2142 case ir_binop_borrow
:
2143 /* This operation is not supported, or should have already been handled.
2145 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2149 this->result
= result_src
;
2154 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2160 /* Note that this is only swizzles in expressions, not those on the left
2161 * hand side of an assignment, which do write masking. See ir_assignment
2165 ir
->val
->accept(this);
2167 assert(src
.file
!= PROGRAM_UNDEFINED
);
2168 assert(ir
->type
->vector_elements
> 0);
2170 for (i
= 0; i
< 4; i
++) {
2171 if (i
< ir
->type
->vector_elements
) {
2174 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2177 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2180 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2183 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2187 /* If the type is smaller than a vec4, replicate the last
2190 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2194 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2200 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2202 variable_storage
*entry
= find_variable_storage(ir
->var
);
2203 ir_variable
*var
= ir
->var
;
2206 switch (var
->data
.mode
) {
2207 case ir_var_uniform
:
2208 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2209 var
->data
.location
);
2210 this->variables
.push_tail(entry
);
2212 case ir_var_shader_in
:
2213 /* The linker assigns locations for varyings and attributes,
2214 * including deprecated builtins (like gl_Color), user-assign
2215 * generic attributes (glBindVertexLocation), and
2216 * user-defined varyings.
2218 assert(var
->data
.location
!= -1);
2219 entry
= new(mem_ctx
) variable_storage(var
,
2221 var
->data
.location
);
2223 case ir_var_shader_out
:
2224 assert(var
->data
.location
!= -1);
2225 entry
= new(mem_ctx
) variable_storage(var
,
2230 case ir_var_system_value
:
2231 entry
= new(mem_ctx
) variable_storage(var
,
2232 PROGRAM_SYSTEM_VALUE
,
2233 var
->data
.location
);
2236 case ir_var_temporary
:
2237 st_src_reg src
= get_temp(var
->type
);
2239 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2240 this->variables
.push_tail(entry
);
2246 printf("Failed to make storage for %s\n", var
->name
);
2251 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2252 if (!native_integers
)
2253 this->result
.type
= GLSL_TYPE_FLOAT
;
2257 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2261 int element_size
= type_size(ir
->type
);
2264 index
= ir
->array_index
->constant_expression_value();
2266 ir
->array
->accept(this);
2269 is_2D_input
= this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
&&
2270 src
.file
== PROGRAM_INPUT
&&
2271 ir
->array
->ir_type
!= ir_type_dereference_array
;
2278 src
.index2D
= index
->value
.i
[0];
2279 src
.has_index2
= true;
2281 src
.index
+= index
->value
.i
[0] * element_size
;
2283 /* Variable index array dereference. It eats the "vec4" of the
2284 * base of the array and an index that offsets the TGSI register
2287 ir
->array_index
->accept(this);
2289 st_src_reg index_reg
;
2291 if (element_size
== 1) {
2292 index_reg
= this->result
;
2294 index_reg
= get_temp(native_integers
?
2295 glsl_type::int_type
: glsl_type::float_type
);
2297 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2298 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2301 /* If there was already a relative address register involved, add the
2302 * new and the old together to get the new offset.
2304 if (!is_2D_input
&& src
.reladdr
!= NULL
) {
2305 st_src_reg accum_reg
= get_temp(native_integers
?
2306 glsl_type::int_type
: glsl_type::float_type
);
2308 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2309 index_reg
, *src
.reladdr
);
2311 index_reg
= accum_reg
;
2315 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2316 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2318 src
.has_index2
= true;
2320 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2321 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2325 /* If the type is smaller than a vec4, replicate the last channel out. */
2326 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2327 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2329 src
.swizzle
= SWIZZLE_NOOP
;
2331 /* Change the register type to the element type of the array. */
2332 src
.type
= ir
->type
->base_type
;
2338 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2341 const glsl_type
*struct_type
= ir
->record
->type
;
2344 ir
->record
->accept(this);
2346 for (i
= 0; i
< struct_type
->length
; i
++) {
2347 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2349 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2352 /* If the type is smaller than a vec4, replicate the last channel out. */
2353 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2354 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2356 this->result
.swizzle
= SWIZZLE_NOOP
;
2358 this->result
.index
+= offset
;
2359 this->result
.type
= ir
->type
->base_type
;
2363 * We want to be careful in assignment setup to hit the actual storage
2364 * instead of potentially using a temporary like we might with the
2365 * ir_dereference handler.
2368 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2370 /* The LHS must be a dereference. If the LHS is a variable indexed array
2371 * access of a vector, it must be separated into a series conditional moves
2372 * before reaching this point (see ir_vec_index_to_cond_assign).
2374 assert(ir
->as_dereference());
2375 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2377 assert(!deref_array
->array
->type
->is_vector());
2380 /* Use the rvalue deref handler for the most part. We'll ignore
2381 * swizzles in it and write swizzles using writemask, though.
2384 return st_dst_reg(v
->result
);
2388 * Process the condition of a conditional assignment
2390 * Examines the condition of a conditional assignment to generate the optimal
2391 * first operand of a \c CMP instruction. If the condition is a relational
2392 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2393 * used as the source for the \c CMP instruction. Otherwise the comparison
2394 * is processed to a boolean result, and the boolean result is used as the
2395 * operand to the CMP instruction.
2398 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2400 ir_rvalue
*src_ir
= ir
;
2402 bool switch_order
= false;
2404 ir_expression
*const expr
= ir
->as_expression();
2406 if (native_integers
) {
2407 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2408 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2409 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2410 type
== GLSL_TYPE_BOOL
) {
2411 if (expr
->operation
== ir_binop_equal
) {
2412 if (expr
->operands
[0]->is_zero()) {
2413 src_ir
= expr
->operands
[1];
2414 switch_order
= true;
2416 else if (expr
->operands
[1]->is_zero()) {
2417 src_ir
= expr
->operands
[0];
2418 switch_order
= true;
2421 else if (expr
->operation
== ir_binop_nequal
) {
2422 if (expr
->operands
[0]->is_zero()) {
2423 src_ir
= expr
->operands
[1];
2425 else if (expr
->operands
[1]->is_zero()) {
2426 src_ir
= expr
->operands
[0];
2432 src_ir
->accept(this);
2433 return switch_order
;
2436 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2437 bool zero_on_left
= false;
2439 if (expr
->operands
[0]->is_zero()) {
2440 src_ir
= expr
->operands
[1];
2441 zero_on_left
= true;
2442 } else if (expr
->operands
[1]->is_zero()) {
2443 src_ir
= expr
->operands
[0];
2444 zero_on_left
= false;
2448 * (a < 0) T F F ( a < 0) T F F
2449 * (0 < a) F F T (-a < 0) F F T
2450 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2451 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2452 * (a > 0) F F T (-a < 0) F F T
2453 * (0 > a) T F F ( a < 0) T F F
2454 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2455 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2457 * Note that exchanging the order of 0 and 'a' in the comparison simply
2458 * means that the value of 'a' should be negated.
2461 switch (expr
->operation
) {
2463 switch_order
= false;
2464 negate
= zero_on_left
;
2467 case ir_binop_greater
:
2468 switch_order
= false;
2469 negate
= !zero_on_left
;
2472 case ir_binop_lequal
:
2473 switch_order
= true;
2474 negate
= !zero_on_left
;
2477 case ir_binop_gequal
:
2478 switch_order
= true;
2479 negate
= zero_on_left
;
2483 /* This isn't the right kind of comparison afterall, so make sure
2484 * the whole condition is visited.
2492 src_ir
->accept(this);
2494 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2495 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2496 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2497 * computing the condition.
2500 this->result
.negate
= ~this->result
.negate
;
2502 return switch_order
;
2506 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2507 st_dst_reg
*l
, st_src_reg
*r
,
2508 st_src_reg
*cond
, bool cond_swap
)
2510 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2511 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2512 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2518 if (type
->is_array()) {
2519 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2520 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2525 if (type
->is_matrix()) {
2526 const struct glsl_type
*vec_type
;
2528 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2529 type
->vector_elements
, 1);
2531 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2532 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2537 assert(type
->is_scalar() || type
->is_vector());
2539 r
->type
= type
->base_type
;
2541 st_src_reg l_src
= st_src_reg(*l
);
2542 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2544 if (native_integers
) {
2545 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2546 cond_swap
? l_src
: *r
,
2547 cond_swap
? *r
: l_src
);
2549 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2550 cond_swap
? l_src
: *r
,
2551 cond_swap
? *r
: l_src
);
2554 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2561 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2566 ir
->rhs
->accept(this);
2569 l
= get_assignment_lhs(ir
->lhs
, this);
2571 /* FINISHME: This should really set to the correct maximal writemask for each
2572 * FINISHME: component written (in the loops below). This case can only
2573 * FINISHME: occur for matrices, arrays, and structures.
2575 if (ir
->write_mask
== 0) {
2576 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2577 l
.writemask
= WRITEMASK_XYZW
;
2578 } else if (ir
->lhs
->type
->is_scalar() &&
2579 !ir
->lhs
->type
->is_double() &&
2580 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2581 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2582 * FINISHME: W component of fragment shader output zero, work correctly.
2584 l
.writemask
= WRITEMASK_XYZW
;
2587 int first_enabled_chan
= 0;
2590 l
.writemask
= ir
->write_mask
;
2592 for (int i
= 0; i
< 4; i
++) {
2593 if (l
.writemask
& (1 << i
)) {
2594 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2599 /* Swizzle a small RHS vector into the channels being written.
2601 * glsl ir treats write_mask as dictating how many channels are
2602 * present on the RHS while TGSI treats write_mask as just
2603 * showing which channels of the vec4 RHS get written.
2605 for (int i
= 0; i
< 4; i
++) {
2606 if (l
.writemask
& (1 << i
))
2607 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2609 swizzles
[i
] = first_enabled_chan
;
2611 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2612 swizzles
[2], swizzles
[3]);
2615 assert(l
.file
!= PROGRAM_UNDEFINED
);
2616 assert(r
.file
!= PROGRAM_UNDEFINED
);
2618 if (ir
->condition
) {
2619 const bool switch_order
= this->process_move_condition(ir
->condition
);
2620 st_src_reg condition
= this->result
;
2622 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2623 } else if (ir
->rhs
->as_expression() &&
2624 this->instructions
.get_tail() &&
2625 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2626 type_size(ir
->lhs
->type
) == 1 &&
2627 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2628 /* To avoid emitting an extra MOV when assigning an expression to a
2629 * variable, emit the last instruction of the expression again, but
2630 * replace the destination register with the target of the assignment.
2631 * Dead code elimination will remove the original instruction.
2633 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2634 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2635 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2]);
2636 new_inst
->saturate
= inst
->saturate
;
2637 inst
->dead_mask
= inst
->dst
[0].writemask
;
2639 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2645 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2648 GLdouble stack_vals
[4] = { 0 };
2649 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2650 GLenum gl_type
= GL_NONE
;
2652 static int in_array
= 0;
2653 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2655 /* Unfortunately, 4 floats is all we can get into
2656 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2657 * aggregate constant and move each constant value into it. If we
2658 * get lucky, copy propagation will eliminate the extra moves.
2660 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2661 st_src_reg temp_base
= get_temp(ir
->type
);
2662 st_dst_reg temp
= st_dst_reg(temp_base
);
2664 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2665 int size
= type_size(field_value
->type
);
2669 field_value
->accept(this);
2672 for (i
= 0; i
< (unsigned int)size
; i
++) {
2673 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2679 this->result
= temp_base
;
2683 if (ir
->type
->is_array()) {
2684 st_src_reg temp_base
= get_temp(ir
->type
);
2685 st_dst_reg temp
= st_dst_reg(temp_base
);
2686 int size
= type_size(ir
->type
->fields
.array
);
2691 for (i
= 0; i
< ir
->type
->length
; i
++) {
2692 ir
->array_elements
[i
]->accept(this);
2694 for (int j
= 0; j
< size
; j
++) {
2695 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2701 this->result
= temp_base
;
2706 if (ir
->type
->is_matrix()) {
2707 st_src_reg mat
= get_temp(ir
->type
);
2708 st_dst_reg mat_column
= st_dst_reg(mat
);
2710 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2711 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
2712 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2714 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2715 src
.index
= add_constant(file
,
2717 ir
->type
->vector_elements
,
2720 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2729 switch (ir
->type
->base_type
) {
2730 case GLSL_TYPE_FLOAT
:
2732 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2733 values
[i
].f
= ir
->value
.f
[i
];
2736 case GLSL_TYPE_DOUBLE
:
2737 gl_type
= GL_DOUBLE
;
2738 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2739 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
2740 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
2743 case GLSL_TYPE_UINT
:
2744 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
2745 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2746 if (native_integers
)
2747 values
[i
].u
= ir
->value
.u
[i
];
2749 values
[i
].f
= ir
->value
.u
[i
];
2753 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
2754 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2755 if (native_integers
)
2756 values
[i
].i
= ir
->value
.i
[i
];
2758 values
[i
].f
= ir
->value
.i
[i
];
2761 case GLSL_TYPE_BOOL
:
2762 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
2763 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2764 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
2768 assert(!"Non-float/uint/int/bool constant");
2771 this->result
= st_src_reg(file
, -1, ir
->type
);
2772 this->result
.index
= add_constant(file
,
2774 ir
->type
->vector_elements
,
2776 &this->result
.swizzle
);
2780 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
2782 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
2783 if (entry
->sig
== sig
)
2787 entry
= ralloc(mem_ctx
, function_entry
);
2789 entry
->sig_id
= this->next_signature_id
++;
2790 entry
->bgn_inst
= NULL
;
2792 /* Allocate storage for all the parameters. */
2793 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
2794 variable_storage
*storage
;
2796 storage
= find_variable_storage(param
);
2799 st_src_reg src
= get_temp(param
->type
);
2801 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
2802 this->variables
.push_tail(storage
);
2805 if (!sig
->return_type
->is_void()) {
2806 entry
->return_reg
= get_temp(sig
->return_type
);
2808 entry
->return_reg
= undef_src
;
2811 this->function_signatures
.push_tail(entry
);
2816 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
2818 glsl_to_tgsi_instruction
*call_inst
;
2819 ir_function_signature
*sig
= ir
->callee
;
2820 function_entry
*entry
= get_function_signature(sig
);
2823 /* Process in parameters. */
2824 foreach_two_lists(formal_node
, &sig
->parameters
,
2825 actual_node
, &ir
->actual_parameters
) {
2826 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
2827 ir_variable
*param
= (ir_variable
*) formal_node
;
2829 if (param
->data
.mode
== ir_var_function_in
||
2830 param
->data
.mode
== ir_var_function_inout
) {
2831 variable_storage
*storage
= find_variable_storage(param
);
2834 param_rval
->accept(this);
2835 st_src_reg r
= this->result
;
2838 l
.file
= storage
->file
;
2839 l
.index
= storage
->index
;
2841 l
.writemask
= WRITEMASK_XYZW
;
2842 l
.cond_mask
= COND_TR
;
2844 for (i
= 0; i
< type_size(param
->type
); i
++) {
2845 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
2852 /* Emit call instruction */
2853 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
2854 call_inst
->function
= entry
;
2856 /* Process out parameters. */
2857 foreach_two_lists(formal_node
, &sig
->parameters
,
2858 actual_node
, &ir
->actual_parameters
) {
2859 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
2860 ir_variable
*param
= (ir_variable
*) formal_node
;
2862 if (param
->data
.mode
== ir_var_function_out
||
2863 param
->data
.mode
== ir_var_function_inout
) {
2864 variable_storage
*storage
= find_variable_storage(param
);
2868 r
.file
= storage
->file
;
2869 r
.index
= storage
->index
;
2871 r
.swizzle
= SWIZZLE_NOOP
;
2874 param_rval
->accept(this);
2875 st_dst_reg l
= st_dst_reg(this->result
);
2877 for (i
= 0; i
< type_size(param
->type
); i
++) {
2878 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
2885 /* Process return value. */
2886 this->result
= entry
->return_reg
;
2890 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
2892 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
2893 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
2894 st_src_reg levels_src
;
2895 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
2896 glsl_to_tgsi_instruction
*inst
= NULL
;
2897 unsigned opcode
= TGSI_OPCODE_NOP
;
2898 const glsl_type
*sampler_type
= ir
->sampler
->type
;
2899 ir_rvalue
*sampler_index
=
2900 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2901 bool is_cube_array
= false;
2904 /* if we are a cube array sampler */
2905 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2906 sampler_type
->sampler_array
)) {
2907 is_cube_array
= true;
2910 if (ir
->coordinate
) {
2911 ir
->coordinate
->accept(this);
2913 /* Put our coords in a temp. We'll need to modify them for shadow,
2914 * projection, or LOD, so the only case we'd use it as is is if
2915 * we're doing plain old texturing. The optimization passes on
2916 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
2918 coord
= get_temp(glsl_type::vec4_type
);
2919 coord_dst
= st_dst_reg(coord
);
2920 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2921 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
2924 if (ir
->projector
) {
2925 ir
->projector
->accept(this);
2926 projector
= this->result
;
2929 /* Storage for our result. Ideally for an assignment we'd be using
2930 * the actual storage for the result here, instead.
2932 result_src
= get_temp(ir
->type
);
2933 result_dst
= st_dst_reg(result_src
);
2937 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
2939 ir
->offset
->accept(this);
2940 offset
[0] = this->result
;
2944 if (is_cube_array
||
2945 sampler_type
== glsl_type::samplerCubeShadow_type
) {
2946 opcode
= TGSI_OPCODE_TXB2
;
2949 opcode
= TGSI_OPCODE_TXB
;
2951 ir
->lod_info
.bias
->accept(this);
2952 lod_info
= this->result
;
2954 ir
->offset
->accept(this);
2955 offset
[0] = this->result
;
2959 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
2960 ir
->lod_info
.lod
->accept(this);
2961 lod_info
= this->result
;
2963 ir
->offset
->accept(this);
2964 offset
[0] = this->result
;
2968 opcode
= TGSI_OPCODE_TXD
;
2969 ir
->lod_info
.grad
.dPdx
->accept(this);
2971 ir
->lod_info
.grad
.dPdy
->accept(this);
2974 ir
->offset
->accept(this);
2975 offset
[0] = this->result
;
2979 opcode
= TGSI_OPCODE_TXQ
;
2980 ir
->lod_info
.lod
->accept(this);
2981 lod_info
= this->result
;
2983 case ir_query_levels
:
2984 opcode
= TGSI_OPCODE_TXQ
;
2985 lod_info
= undef_src
;
2986 levels_src
= get_temp(ir
->type
);
2989 opcode
= TGSI_OPCODE_TXF
;
2990 ir
->lod_info
.lod
->accept(this);
2991 lod_info
= this->result
;
2993 ir
->offset
->accept(this);
2994 offset
[0] = this->result
;
2998 opcode
= TGSI_OPCODE_TXF
;
2999 ir
->lod_info
.sample_index
->accept(this);
3000 sample_index
= this->result
;
3003 opcode
= TGSI_OPCODE_TG4
;
3004 ir
->lod_info
.component
->accept(this);
3005 component
= this->result
;
3007 ir
->offset
->accept(this);
3008 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3009 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3010 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3011 offset
[i
] = this->result
;
3012 offset
[i
].index
+= i
* type_size(elt_type
);
3013 offset
[i
].type
= elt_type
->base_type
;
3014 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3017 offset
[0] = this->result
;
3022 opcode
= TGSI_OPCODE_LODQ
;
3026 if (ir
->projector
) {
3027 if (opcode
== TGSI_OPCODE_TEX
) {
3028 /* Slot the projector in as the last component of the coord. */
3029 coord_dst
.writemask
= WRITEMASK_W
;
3030 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3031 coord_dst
.writemask
= WRITEMASK_XYZW
;
3032 opcode
= TGSI_OPCODE_TXP
;
3034 st_src_reg coord_w
= coord
;
3035 coord_w
.swizzle
= SWIZZLE_WWWW
;
3037 /* For the other TEX opcodes there's no projective version
3038 * since the last slot is taken up by LOD info. Do the
3039 * projective divide now.
3041 coord_dst
.writemask
= WRITEMASK_W
;
3042 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3044 /* In the case where we have to project the coordinates "by hand,"
3045 * the shadow comparator value must also be projected.
3047 st_src_reg tmp_src
= coord
;
3048 if (ir
->shadow_comparitor
) {
3049 /* Slot the shadow value in as the second to last component of the
3052 ir
->shadow_comparitor
->accept(this);
3054 tmp_src
= get_temp(glsl_type::vec4_type
);
3055 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3057 /* Projective division not allowed for array samplers. */
3058 assert(!sampler_type
->sampler_array
);
3060 tmp_dst
.writemask
= WRITEMASK_Z
;
3061 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3063 tmp_dst
.writemask
= WRITEMASK_XY
;
3064 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
3067 coord_dst
.writemask
= WRITEMASK_XYZ
;
3068 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
3070 coord_dst
.writemask
= WRITEMASK_XYZW
;
3071 coord
.swizzle
= SWIZZLE_XYZW
;
3075 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
3076 * comparator was put in the correct place (and projected) by the code,
3077 * above, that handles by-hand projection.
3079 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
3080 /* Slot the shadow value in as the second to last component of the
3083 ir
->shadow_comparitor
->accept(this);
3085 if (is_cube_array
) {
3086 cube_sc
= get_temp(glsl_type::float_type
);
3087 cube_sc_dst
= st_dst_reg(cube_sc
);
3088 cube_sc_dst
.writemask
= WRITEMASK_X
;
3089 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
3090 cube_sc_dst
.writemask
= WRITEMASK_X
;
3093 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
3094 sampler_type
->sampler_array
) ||
3095 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3096 coord_dst
.writemask
= WRITEMASK_W
;
3098 coord_dst
.writemask
= WRITEMASK_Z
;
3100 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3101 coord_dst
.writemask
= WRITEMASK_XYZW
;
3105 if (ir
->op
== ir_txf_ms
) {
3106 coord_dst
.writemask
= WRITEMASK_W
;
3107 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
3108 coord_dst
.writemask
= WRITEMASK_XYZW
;
3109 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
3110 opcode
== TGSI_OPCODE_TXF
) {
3111 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
3112 coord_dst
.writemask
= WRITEMASK_W
;
3113 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
3114 coord_dst
.writemask
= WRITEMASK_XYZW
;
3117 if (sampler_index
) {
3118 sampler_index
->accept(this);
3119 emit_arl(ir
, sampler_reladdr
, this->result
);
3122 if (opcode
== TGSI_OPCODE_TXD
)
3123 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
3124 else if (opcode
== TGSI_OPCODE_TXQ
) {
3125 if (ir
->op
== ir_query_levels
) {
3126 /* the level is stored in W */
3127 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
3128 result_dst
.writemask
= WRITEMASK_X
;
3129 levels_src
.swizzle
= SWIZZLE_WWWW
;
3130 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
3132 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
3133 } else if (opcode
== TGSI_OPCODE_TXF
) {
3134 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3135 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
3136 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
3137 } else if (opcode
== TGSI_OPCODE_TEX2
) {
3138 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3139 } else if (opcode
== TGSI_OPCODE_TG4
) {
3140 if (is_cube_array
&& ir
->shadow_comparitor
) {
3141 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3143 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
3146 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3148 if (ir
->shadow_comparitor
)
3149 inst
->tex_shadow
= GL_TRUE
;
3151 inst
->sampler
.index
= _mesa_get_sampler_uniform_value(ir
->sampler
,
3152 this->shader_program
,
3154 if (sampler_index
) {
3155 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3156 memcpy(inst
->sampler
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3157 inst
->sampler_array_size
=
3158 ir
->sampler
->as_dereference_array()->array
->type
->array_size();
3160 inst
->sampler_array_size
= 1;
3164 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
3165 inst
->tex_offsets
[i
] = offset
[i
];
3166 inst
->tex_offset_num_offset
= i
;
3169 switch (sampler_type
->sampler_dimensionality
) {
3170 case GLSL_SAMPLER_DIM_1D
:
3171 inst
->tex_target
= (sampler_type
->sampler_array
)
3172 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3174 case GLSL_SAMPLER_DIM_2D
:
3175 inst
->tex_target
= (sampler_type
->sampler_array
)
3176 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3178 case GLSL_SAMPLER_DIM_3D
:
3179 inst
->tex_target
= TEXTURE_3D_INDEX
;
3181 case GLSL_SAMPLER_DIM_CUBE
:
3182 inst
->tex_target
= (sampler_type
->sampler_array
)
3183 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3185 case GLSL_SAMPLER_DIM_RECT
:
3186 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3188 case GLSL_SAMPLER_DIM_BUF
:
3189 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3191 case GLSL_SAMPLER_DIM_EXTERNAL
:
3192 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3194 case GLSL_SAMPLER_DIM_MS
:
3195 inst
->tex_target
= (sampler_type
->sampler_array
)
3196 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3199 assert(!"Should not get here.");
3202 this->result
= result_src
;
3206 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
3208 if (ir
->get_value()) {
3212 assert(current_function
);
3214 ir
->get_value()->accept(this);
3215 st_src_reg r
= this->result
;
3217 l
= st_dst_reg(current_function
->return_reg
);
3219 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
3220 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3226 emit_asm(ir
, TGSI_OPCODE_RET
);
3230 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
3232 if (ir
->condition
) {
3233 ir
->condition
->accept(this);
3234 st_src_reg condition
= this->result
;
3236 /* Convert the bool condition to a float so we can negate. */
3237 if (native_integers
) {
3238 st_src_reg temp
= get_temp(ir
->condition
->type
);
3239 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
3240 condition
, st_src_reg_for_float(1.0));
3244 condition
.negate
= ~condition
.negate
;
3245 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
3247 /* unconditional kil */
3248 emit_asm(ir
, TGSI_OPCODE_KILL
);
3253 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
3256 glsl_to_tgsi_instruction
*if_inst
;
3258 ir
->condition
->accept(this);
3259 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3261 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
3263 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
3265 this->instructions
.push_tail(if_inst
);
3267 visit_exec_list(&ir
->then_instructions
, this);
3269 if (!ir
->else_instructions
.is_empty()) {
3270 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
3271 visit_exec_list(&ir
->else_instructions
, this);
3274 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
3279 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
3281 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3283 ir
->stream
->accept(this);
3284 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
3288 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
3290 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3292 ir
->stream
->accept(this);
3293 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
3296 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
3298 result
.file
= PROGRAM_UNDEFINED
;
3303 next_signature_id
= 1;
3305 current_function
= NULL
;
3306 num_address_regs
= 0;
3308 indirect_addr_consts
= false;
3309 wpos_transform_const
= -1;
3311 native_integers
= false;
3312 mem_ctx
= ralloc_context(NULL
);
3315 shader_program
= NULL
;
3322 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
3325 ralloc_free(mem_ctx
);
3328 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
3335 * Count resources used by the given gpu program (number of texture
3339 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
3341 v
->samplers_used
= 0;
3343 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
3344 if (is_tex_instruction(inst
->op
)) {
3345 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
3346 v
->samplers_used
|= 1 << (inst
->sampler
.index
+ i
);
3348 if (inst
->tex_shadow
) {
3349 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
3354 prog
->SamplersUsed
= v
->samplers_used
;
3356 if (v
->shader_program
!= NULL
)
3357 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
3361 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
3362 * are read from the given src in this instruction
3365 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
3367 int read_mask
= 0, comp
;
3369 /* Now, given the src swizzle and the written channels, find which
3370 * components are actually read
3372 for (comp
= 0; comp
< 4; ++comp
) {
3373 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
3375 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
3376 read_mask
|= 1 << coord
;
3383 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
3384 * instruction is the first instruction to write to register T0. There are
3385 * several lowering passes done in GLSL IR (e.g. branches and
3386 * relative addressing) that create a large number of conditional assignments
3387 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
3389 * Here is why this conversion is safe:
3390 * CMP T0, T1 T2 T0 can be expanded to:
3396 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
3397 * as the original program. If (T1 < 0.0) evaluates to false, executing
3398 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
3399 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
3400 * because any instruction that was going to read from T0 after this was going
3401 * to read a garbage value anyway.
3404 glsl_to_tgsi_visitor::simplify_cmp(void)
3406 int tempWritesSize
= 0;
3407 unsigned *tempWrites
= NULL
;
3408 unsigned outputWrites
[MAX_PROGRAM_OUTPUTS
];
3410 memset(outputWrites
, 0, sizeof(outputWrites
));
3412 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3413 unsigned prevWriteMask
= 0;
3415 /* Give up if we encounter relative addressing or flow control. */
3416 if (inst
->dst
[0].reladdr
||
3417 inst
->dst
[1].reladdr
||
3418 tgsi_get_opcode_info(inst
->op
)->is_branch
||
3419 inst
->op
== TGSI_OPCODE_BGNSUB
||
3420 inst
->op
== TGSI_OPCODE_CONT
||
3421 inst
->op
== TGSI_OPCODE_END
||
3422 inst
->op
== TGSI_OPCODE_ENDSUB
||
3423 inst
->op
== TGSI_OPCODE_RET
) {
3427 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
3428 assert(inst
->dst
[0].index
< MAX_PROGRAM_OUTPUTS
);
3429 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
3430 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3431 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
3432 if (inst
->dst
[0].index
>= tempWritesSize
) {
3433 const int inc
= 4096;
3435 tempWrites
= (unsigned*)
3437 (tempWritesSize
+ inc
) * sizeof(unsigned));
3441 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
3442 tempWritesSize
+= inc
;
3445 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
3446 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3450 /* For a CMP to be considered a conditional write, the destination
3451 * register and source register two must be the same. */
3452 if (inst
->op
== TGSI_OPCODE_CMP
3453 && !(inst
->dst
[0].writemask
& prevWriteMask
)
3454 && inst
->src
[2].file
== inst
->dst
[0].file
3455 && inst
->src
[2].index
== inst
->dst
[0].index
3456 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
3458 inst
->op
= TGSI_OPCODE_MOV
;
3459 inst
->src
[0] = inst
->src
[1];
3466 /* Replaces all references to a temporary register index with another index. */
3468 glsl_to_tgsi_visitor::rename_temp_register(int index
, int new_index
)
3470 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3473 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3474 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3475 inst
->src
[j
].index
== index
) {
3476 inst
->src
[j
].index
= new_index
;
3480 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3481 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3482 inst
->tex_offsets
[j
].index
== index
) {
3483 inst
->tex_offsets
[j
].index
= new_index
;
3487 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3488 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
) {
3489 inst
->dst
[j
].index
= new_index
;
3496 glsl_to_tgsi_visitor::get_first_temp_read(int index
)
3498 int depth
= 0; /* loop depth */
3499 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3502 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3503 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3504 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3505 inst
->src
[j
].index
== index
) {
3506 return (depth
== 0) ? i
: loop_start
;
3509 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3510 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3511 inst
->tex_offsets
[j
].index
== index
) {
3512 return (depth
== 0) ? i
: loop_start
;
3515 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3518 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3529 glsl_to_tgsi_visitor::get_first_temp_write(int index
)
3531 int depth
= 0; /* loop depth */
3532 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3536 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3537 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3538 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
) {
3539 return (depth
== 0) ? i
: loop_start
;
3542 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3545 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3556 glsl_to_tgsi_visitor::get_last_temp_read(int index
)
3558 int depth
= 0; /* loop depth */
3559 int last
= -1; /* index of last instruction that reads the temporary */
3562 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3563 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3564 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3565 inst
->src
[j
].index
== index
) {
3566 last
= (depth
== 0) ? i
: -2;
3569 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3570 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3571 inst
->tex_offsets
[j
].index
== index
)
3572 last
= (depth
== 0) ? i
: -2;
3574 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3576 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3577 if (--depth
== 0 && last
== -2)
3587 glsl_to_tgsi_visitor::get_last_temp_write(int index
)
3589 int depth
= 0; /* loop depth */
3590 int last
= -1; /* index of last instruction that writes to the temporary */
3594 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3595 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3596 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
)
3597 last
= (depth
== 0) ? i
: -2;
3600 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3602 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3603 if (--depth
== 0 && last
== -2)
3613 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
3614 * channels for copy propagation and updates following instructions to
3615 * use the original versions.
3617 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3618 * will occur. As an example, a TXP production before this pass:
3620 * 0: MOV TEMP[1], INPUT[4].xyyy;
3621 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3622 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
3626 * 0: MOV TEMP[1], INPUT[4].xyyy;
3627 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3628 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3630 * which allows for dead code elimination on TEMP[1]'s writes.
3633 glsl_to_tgsi_visitor::copy_propagate(void)
3635 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
3636 glsl_to_tgsi_instruction
*,
3637 this->next_temp
* 4);
3638 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3641 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3642 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3643 || inst
->dst
[0].index
< this->next_temp
);
3645 /* First, do any copy propagation possible into the src regs. */
3646 for (int r
= 0; r
< 3; r
++) {
3647 glsl_to_tgsi_instruction
*first
= NULL
;
3649 int acp_base
= inst
->src
[r
].index
* 4;
3651 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
3652 inst
->src
[r
].reladdr
||
3653 inst
->src
[r
].reladdr2
)
3656 /* See if we can find entries in the ACP consisting of MOVs
3657 * from the same src register for all the swizzled channels
3658 * of this src register reference.
3660 for (int i
= 0; i
< 4; i
++) {
3661 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3662 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
3669 assert(acp_level
[acp_base
+ src_chan
] <= level
);
3674 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
3675 first
->src
[0].index
!= copy_chan
->src
[0].index
||
3676 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
3677 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
3685 /* We've now validated that we can copy-propagate to
3686 * replace this src register reference. Do it.
3688 inst
->src
[r
].file
= first
->src
[0].file
;
3689 inst
->src
[r
].index
= first
->src
[0].index
;
3690 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
3691 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
3692 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
3695 for (int i
= 0; i
< 4; i
++) {
3696 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3697 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
3698 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
3700 inst
->src
[r
].swizzle
= swizzle
;
3705 case TGSI_OPCODE_BGNLOOP
:
3706 case TGSI_OPCODE_ENDLOOP
:
3707 /* End of a basic block, clear the ACP entirely. */
3708 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3711 case TGSI_OPCODE_IF
:
3712 case TGSI_OPCODE_UIF
:
3716 case TGSI_OPCODE_ENDIF
:
3717 case TGSI_OPCODE_ELSE
:
3718 /* Clear all channels written inside the block from the ACP, but
3719 * leaving those that were not touched.
3721 for (int r
= 0; r
< this->next_temp
; r
++) {
3722 for (int c
= 0; c
< 4; c
++) {
3723 if (!acp
[4 * r
+ c
])
3726 if (acp_level
[4 * r
+ c
] >= level
)
3727 acp
[4 * r
+ c
] = NULL
;
3730 if (inst
->op
== TGSI_OPCODE_ENDIF
)
3735 /* Continuing the block, clear any written channels from
3738 for (int d
= 0; d
< 2; d
++) {
3739 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
3740 /* Any temporary might be written, so no copy propagation
3741 * across this instruction.
3743 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3744 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
3745 inst
->dst
[d
].reladdr
) {
3746 /* Any output might be written, so no copy propagation
3747 * from outputs across this instruction.
3749 for (int r
= 0; r
< this->next_temp
; r
++) {
3750 for (int c
= 0; c
< 4; c
++) {
3751 if (!acp
[4 * r
+ c
])
3754 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
3755 acp
[4 * r
+ c
] = NULL
;
3758 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
3759 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
3760 /* Clear where it's used as dst. */
3761 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
3762 for (int c
= 0; c
< 4; c
++) {
3763 if (inst
->dst
[d
].writemask
& (1 << c
))
3764 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
3768 /* Clear where it's used as src. */
3769 for (int r
= 0; r
< this->next_temp
; r
++) {
3770 for (int c
= 0; c
< 4; c
++) {
3771 if (!acp
[4 * r
+ c
])
3774 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
3776 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
3777 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
3778 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
3779 acp
[4 * r
+ c
] = NULL
;
3788 /* If this is a copy, add it to the ACP. */
3789 if (inst
->op
== TGSI_OPCODE_MOV
&&
3790 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
3791 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
3792 inst
->dst
[0].index
== inst
->src
[0].index
) &&
3793 !inst
->dst
[0].reladdr
&&
3795 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
3796 !inst
->src
[0].reladdr
&&
3797 !inst
->src
[0].reladdr2
&&
3798 !inst
->src
[0].negate
) {
3799 for (int i
= 0; i
< 4; i
++) {
3800 if (inst
->dst
[0].writemask
& (1 << i
)) {
3801 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
3802 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
3808 ralloc_free(acp_level
);
3813 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
3816 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3817 * will occur. As an example, a TXP production after copy propagation but
3820 * 0: MOV TEMP[1], INPUT[4].xyyy;
3821 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3822 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3824 * and after this pass:
3826 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3829 glsl_to_tgsi_visitor::eliminate_dead_code(void)
3831 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
3832 glsl_to_tgsi_instruction
*,
3833 this->next_temp
* 4);
3834 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3838 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3839 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3840 || inst
->dst
[0].index
< this->next_temp
);
3843 case TGSI_OPCODE_BGNLOOP
:
3844 case TGSI_OPCODE_ENDLOOP
:
3845 case TGSI_OPCODE_CONT
:
3846 case TGSI_OPCODE_BRK
:
3847 /* End of a basic block, clear the write array entirely.
3849 * This keeps us from killing dead code when the writes are
3850 * on either side of a loop, even when the register isn't touched
3851 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
3852 * dead code of this type, so it shouldn't make a difference as long as
3853 * the dead code elimination pass in the GLSL compiler does its job.
3855 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
3858 case TGSI_OPCODE_ENDIF
:
3859 case TGSI_OPCODE_ELSE
:
3860 /* Promote the recorded level of all channels written inside the
3861 * preceding if or else block to the level above the if/else block.
3863 for (int r
= 0; r
< this->next_temp
; r
++) {
3864 for (int c
= 0; c
< 4; c
++) {
3865 if (!writes
[4 * r
+ c
])
3868 if (write_level
[4 * r
+ c
] == level
)
3869 write_level
[4 * r
+ c
] = level
-1;
3872 if(inst
->op
== TGSI_OPCODE_ENDIF
)
3876 case TGSI_OPCODE_IF
:
3877 case TGSI_OPCODE_UIF
:
3879 /* fallthrough to default case to mark the condition as read */
3881 /* Continuing the block, clear any channels from the write array that
3882 * are read by this instruction.
3884 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
3885 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
3886 /* Any temporary might be read, so no dead code elimination
3887 * across this instruction.
3889 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
3890 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
3891 /* Clear where it's used as src. */
3892 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
3893 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
3894 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
3895 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
3897 for (int c
= 0; c
< 4; c
++) {
3898 if (src_chans
& (1 << c
))
3899 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
3903 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
3904 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
3905 /* Any temporary might be read, so no dead code elimination
3906 * across this instruction.
3908 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
3909 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
3910 /* Clear where it's used as src. */
3911 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
3912 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
3913 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
3914 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
3916 for (int c
= 0; c
< 4; c
++) {
3917 if (src_chans
& (1 << c
))
3918 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
3925 /* If this instruction writes to a temporary, add it to the write array.
3926 * If there is already an instruction in the write array for one or more
3927 * of the channels, flag that channel write as dead.
3929 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
3930 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
3931 !inst
->dst
[i
].reladdr
&&
3933 for (int c
= 0; c
< 4; c
++) {
3934 if (inst
->dst
[i
].writemask
& (1 << c
)) {
3935 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
3936 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
3939 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
3941 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
3942 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
3949 /* Anything still in the write array at this point is dead code. */
3950 for (int r
= 0; r
< this->next_temp
; r
++) {
3951 for (int c
= 0; c
< 4; c
++) {
3952 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
3954 inst
->dead_mask
|= (1 << c
);
3958 /* Now actually remove the instructions that are completely dead and update
3959 * the writemask of other instructions with dead channels.
3961 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3962 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
3964 else if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
3969 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
3970 if (inst
->dead_mask
== WRITEMASK_XY
||
3971 inst
->dead_mask
== WRITEMASK_ZW
)
3972 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
3974 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
3978 ralloc_free(write_level
);
3979 ralloc_free(writes
);
3984 /* merge DFRACEXP instructions into one. */
3986 glsl_to_tgsi_visitor::merge_two_dsts(void)
3988 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3989 glsl_to_tgsi_instruction
*inst2
;
3991 if (num_inst_dst_regs(inst
->op
) != 2)
3994 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
3995 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
3998 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4001 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4002 inst
->src
[0].index
== inst2
->src
[0].index
&&
4003 inst
->src
[0].type
== inst2
->src
[0].type
&&
4004 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4006 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4012 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4014 inst
->dst
[0] = inst2
->dst
[0];
4015 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4016 inst
->dst
[1] = inst2
->dst
[1];
4027 /* Merges temporary registers together where possible to reduce the number of
4028 * registers needed to run a program.
4030 * Produces optimal code only after copy propagation and dead code elimination
4033 glsl_to_tgsi_visitor::merge_registers(void)
4035 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4036 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4039 /* Read the indices of the last read and first write to each temp register
4040 * into an array so that we don't have to traverse the instruction list as
4042 for (i
= 0; i
< this->next_temp
; i
++) {
4043 last_reads
[i
] = get_last_temp_read(i
);
4044 first_writes
[i
] = get_first_temp_write(i
);
4047 /* Start looking for registers with non-overlapping usages that can be
4048 * merged together. */
4049 for (i
= 0; i
< this->next_temp
; i
++) {
4050 /* Don't touch unused registers. */
4051 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
4053 for (j
= 0; j
< this->next_temp
; j
++) {
4054 /* Don't touch unused registers. */
4055 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
4057 /* We can merge the two registers if the first write to j is after or
4058 * in the same instruction as the last read from i. Note that the
4059 * register at index i will always be used earlier or at the same time
4060 * as the register at index j. */
4061 if (first_writes
[i
] <= first_writes
[j
] &&
4062 last_reads
[i
] <= first_writes
[j
]) {
4063 rename_temp_register(j
, i
); /* Replace all references to j with i.*/
4065 /* Update the first_writes and last_reads arrays with the new
4066 * values for the merged register index, and mark the newly unused
4067 * register index as such. */
4068 last_reads
[i
] = last_reads
[j
];
4069 first_writes
[j
] = -1;
4075 ralloc_free(last_reads
);
4076 ralloc_free(first_writes
);
4079 /* Reassign indices to temporary registers by reusing unused indices created
4080 * by optimization passes. */
4082 glsl_to_tgsi_visitor::renumber_registers(void)
4087 for (i
= 0; i
< this->next_temp
; i
++) {
4088 if (get_first_temp_read(i
) < 0) continue;
4090 rename_temp_register(i
, new_index
);
4094 this->next_temp
= new_index
;
4098 * Returns a fragment program which implements the current pixel transfer ops.
4099 * Based on get_pixel_transfer_program in st_atom_pixeltransfer.c.
4102 get_pixel_transfer_visitor(struct st_fragment_program
*fp
,
4103 glsl_to_tgsi_visitor
*original
,
4104 int scale_and_bias
, int pixel_maps
)
4106 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4107 struct st_context
*st
= st_context(original
->ctx
);
4108 struct gl_program
*prog
= &fp
->Base
.Base
;
4109 struct gl_program_parameter_list
*params
= _mesa_new_parameter_list();
4110 st_src_reg coord
, src0
;
4112 glsl_to_tgsi_instruction
*inst
;
4114 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4115 v
->ctx
= original
->ctx
;
4117 v
->shader_program
= NULL
;
4119 v
->glsl_version
= original
->glsl_version
;
4120 v
->native_integers
= original
->native_integers
;
4121 v
->options
= original
->options
;
4122 v
->next_temp
= original
->next_temp
;
4123 v
->num_address_regs
= original
->num_address_regs
;
4124 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4125 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4126 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4127 v
->num_immediates
= original
->num_immediates
;
4130 * Get initial pixel color from the texture.
4131 * TEX colorTemp, fragment.texcoord[0], texture[0], 2D;
4133 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4134 src0
= v
->get_temp(glsl_type::vec4_type
);
4135 dst0
= st_dst_reg(src0
);
4136 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4137 inst
->sampler_array_size
= 1;
4138 inst
->tex_target
= TEXTURE_2D_INDEX
;
4140 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4141 prog
->SamplersUsed
|= (1 << 0); /* mark sampler 0 as used */
4142 v
->samplers_used
|= (1 << 0);
4144 if (scale_and_bias
) {
4145 static const gl_state_index scale_state
[STATE_LENGTH
] =
4146 { STATE_INTERNAL
, STATE_PT_SCALE
,
4147 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4148 static const gl_state_index bias_state
[STATE_LENGTH
] =
4149 { STATE_INTERNAL
, STATE_PT_BIAS
,
4150 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4151 GLint scale_p
, bias_p
;
4152 st_src_reg scale
, bias
;
4154 scale_p
= _mesa_add_state_reference(params
, scale_state
);
4155 bias_p
= _mesa_add_state_reference(params
, bias_state
);
4157 /* MAD colorTemp, colorTemp, scale, bias; */
4158 scale
= st_src_reg(PROGRAM_STATE_VAR
, scale_p
, GLSL_TYPE_FLOAT
);
4159 bias
= st_src_reg(PROGRAM_STATE_VAR
, bias_p
, GLSL_TYPE_FLOAT
);
4160 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MAD
, dst0
, src0
, scale
, bias
);
4164 st_src_reg temp
= v
->get_temp(glsl_type::vec4_type
);
4165 st_dst_reg temp_dst
= st_dst_reg(temp
);
4167 assert(st
->pixel_xfer
.pixelmap_texture
);
4170 /* With a little effort, we can do four pixel map look-ups with
4171 * two TEX instructions:
4174 /* TEX temp.rg, colorTemp.rgba, texture[1], 2D; */
4175 temp_dst
.writemask
= WRITEMASK_XY
; /* write R,G */
4176 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4177 inst
->sampler
.index
= 1;
4178 inst
->sampler_array_size
= 1;
4179 inst
->tex_target
= TEXTURE_2D_INDEX
;
4181 /* TEX temp.ba, colorTemp.baba, texture[1], 2D; */
4182 src0
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
4183 temp_dst
.writemask
= WRITEMASK_ZW
; /* write B,A */
4184 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4185 inst
->sampler
.index
= 1;
4186 inst
->sampler_array_size
= 1;
4187 inst
->tex_target
= TEXTURE_2D_INDEX
;
4189 prog
->SamplersUsed
|= (1 << 1); /* mark sampler 1 as used */
4190 v
->samplers_used
|= (1 << 1);
4192 /* MOV colorTemp, temp; */
4193 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MOV
, dst0
, temp
);
4196 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4198 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4199 glsl_to_tgsi_instruction
*newinst
;
4200 st_src_reg src_regs
[3];
4202 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4203 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4205 for (int i
= 0; i
< 3; i
++) {
4206 src_regs
[i
] = inst
->src
[i
];
4207 if (src_regs
[i
].file
== PROGRAM_INPUT
&&
4208 src_regs
[i
].index
== VARYING_SLOT_COL0
) {
4209 src_regs
[i
].file
= PROGRAM_TEMPORARY
;
4210 src_regs
[i
].index
= src0
.index
;
4212 else if (src_regs
[i
].file
== PROGRAM_INPUT
)
4213 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4216 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2]);
4217 newinst
->tex_target
= inst
->tex_target
;
4218 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4221 /* Make modifications to fragment program info. */
4222 prog
->Parameters
= _mesa_combine_parameter_lists(params
,
4223 original
->prog
->Parameters
);
4224 _mesa_free_parameter_list(params
);
4225 count_resources(v
, prog
);
4226 fp
->glsl_to_tgsi
= v
;
4230 * Make fragment program for glBitmap:
4231 * Sample the texture and kill the fragment if the bit is 0.
4232 * This program will be combined with the user's fragment program.
4234 * Based on make_bitmap_fragment_program in st_cb_bitmap.c.
4237 get_bitmap_visitor(struct st_fragment_program
*fp
,
4238 glsl_to_tgsi_visitor
*original
, int samplerIndex
)
4240 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4241 struct st_context
*st
= st_context(original
->ctx
);
4242 struct gl_program
*prog
= &fp
->Base
.Base
;
4243 st_src_reg coord
, src0
;
4245 glsl_to_tgsi_instruction
*inst
;
4247 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4248 v
->ctx
= original
->ctx
;
4250 v
->shader_program
= NULL
;
4252 v
->glsl_version
= original
->glsl_version
;
4253 v
->native_integers
= original
->native_integers
;
4254 v
->options
= original
->options
;
4255 v
->next_temp
= original
->next_temp
;
4256 v
->num_address_regs
= original
->num_address_regs
;
4257 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4258 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4259 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4260 v
->num_immediates
= original
->num_immediates
;
4262 /* TEX tmp0, fragment.texcoord[0], texture[0], 2D; */
4263 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4264 src0
= v
->get_temp(glsl_type::vec4_type
);
4265 dst0
= st_dst_reg(src0
);
4266 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4267 inst
->sampler
.index
= samplerIndex
;
4268 inst
->sampler_array_size
= 1;
4269 inst
->tex_target
= TEXTURE_2D_INDEX
;
4271 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4272 prog
->SamplersUsed
|= (1 << samplerIndex
); /* mark sampler as used */
4273 v
->samplers_used
|= (1 << samplerIndex
);
4275 /* KIL if -tmp0 < 0 # texel=0 -> keep / texel=0 -> discard */
4276 src0
.negate
= NEGATE_XYZW
;
4277 if (st
->bitmap
.tex_format
== PIPE_FORMAT_L8_UNORM
)
4278 src0
.swizzle
= SWIZZLE_XXXX
;
4279 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_KILL_IF
, undef_dst
, src0
);
4281 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4283 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4284 glsl_to_tgsi_instruction
*newinst
;
4285 st_src_reg src_regs
[3];
4287 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4288 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4290 for (int i
= 0; i
< 3; i
++) {
4291 src_regs
[i
] = inst
->src
[i
];
4292 if (src_regs
[i
].file
== PROGRAM_INPUT
)
4293 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4296 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2]);
4297 newinst
->tex_target
= inst
->tex_target
;
4298 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4301 /* Make modifications to fragment program info. */
4302 prog
->Parameters
= _mesa_clone_parameter_list(original
->prog
->Parameters
);
4303 count_resources(v
, prog
);
4304 fp
->glsl_to_tgsi
= v
;
4307 /* ------------------------- TGSI conversion stuff -------------------------- */
4309 unsigned branch_target
;
4314 * Intermediate state used during shader translation.
4316 struct st_translate
{
4317 struct ureg_program
*ureg
;
4319 unsigned temps_size
;
4320 struct ureg_dst
*temps
;
4322 struct ureg_dst
*arrays
;
4323 unsigned num_temp_arrays
;
4324 struct ureg_src
*constants
;
4326 struct ureg_src
*immediates
;
4328 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
4329 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
4330 struct ureg_dst address
[3];
4331 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
4332 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
4333 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
4334 unsigned *array_sizes
;
4336 const GLuint
*inputMapping
;
4337 const GLuint
*outputMapping
;
4339 /* For every instruction that contains a label (eg CALL), keep
4340 * details so that we can go back afterwards and emit the correct
4341 * tgsi instruction number for each label.
4343 struct label
*labels
;
4344 unsigned labels_size
;
4345 unsigned labels_count
;
4347 /* Keep a record of the tgsi instruction number that each mesa
4348 * instruction starts at, will be used to fix up labels after
4353 unsigned insn_count
;
4355 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
4360 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
4361 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
4364 TGSI_SEMANTIC_VERTEXID
,
4365 TGSI_SEMANTIC_INSTANCEID
,
4366 TGSI_SEMANTIC_VERTEXID_NOBASE
,
4367 TGSI_SEMANTIC_BASEVERTEX
,
4371 TGSI_SEMANTIC_INVOCATIONID
,
4376 TGSI_SEMANTIC_SAMPLEID
,
4377 TGSI_SEMANTIC_SAMPLEPOS
,
4378 TGSI_SEMANTIC_SAMPLEMASK
,
4382 * Make note of a branch to a label in the TGSI code.
4383 * After we've emitted all instructions, we'll go over the list
4384 * of labels built here and patch the TGSI code with the actual
4385 * location of each label.
4387 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
4391 if (t
->labels_count
+ 1 >= t
->labels_size
) {
4392 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
4393 t
->labels
= (struct label
*)realloc(t
->labels
,
4394 t
->labels_size
* sizeof(struct label
));
4395 if (t
->labels
== NULL
) {
4396 static unsigned dummy
;
4402 i
= t
->labels_count
++;
4403 t
->labels
[i
].branch_target
= branch_target
;
4404 return &t
->labels
[i
].token
;
4408 * Called prior to emitting the TGSI code for each instruction.
4409 * Allocate additional space for instructions if needed.
4410 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
4411 * the next TGSI instruction.
4413 static void set_insn_start(struct st_translate
*t
, unsigned start
)
4415 if (t
->insn_count
+ 1 >= t
->insn_size
) {
4416 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
4417 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
4418 if (t
->insn
== NULL
) {
4424 t
->insn
[t
->insn_count
++] = start
;
4428 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
4430 static struct ureg_src
4431 emit_immediate(struct st_translate
*t
,
4432 gl_constant_value values
[4],
4435 struct ureg_program
*ureg
= t
->ureg
;
4440 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
4442 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
4444 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
4445 case GL_UNSIGNED_INT
:
4447 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
4449 assert(!"should not get here - type must be float, int, uint, or bool");
4450 return ureg_src_undef();
4455 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
4457 static struct ureg_dst
4458 dst_register(struct st_translate
*t
,
4459 gl_register_file file
,
4465 case PROGRAM_UNDEFINED
:
4466 return ureg_dst_undef();
4468 case PROGRAM_TEMPORARY
:
4469 /* Allocate space for temporaries on demand. */
4470 if (index
>= t
->temps_size
) {
4471 const int inc
= 4096;
4473 t
->temps
= (struct ureg_dst
*)
4475 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
4477 return ureg_dst_undef();
4479 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
4480 t
->temps_size
+= inc
;
4483 if (ureg_dst_is_undef(t
->temps
[index
]))
4484 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
4486 return t
->temps
[index
];
4489 array
= index
>> 16;
4491 assert(array
< t
->num_temp_arrays
);
4493 if (ureg_dst_is_undef(t
->arrays
[array
]))
4494 t
->arrays
[array
] = ureg_DECL_array_temporary(
4495 t
->ureg
, t
->array_sizes
[array
], TRUE
);
4497 return ureg_dst_array_offset(t
->arrays
[array
],
4498 (int)(index
& 0xFFFF) - 0x8000);
4500 case PROGRAM_OUTPUT
:
4501 if (t
->procType
== TGSI_PROCESSOR_VERTEX
)
4502 assert(index
< VARYING_SLOT_MAX
);
4503 else if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
4504 assert(index
< FRAG_RESULT_MAX
);
4506 assert(index
< VARYING_SLOT_MAX
);
4508 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
4510 return t
->outputs
[t
->outputMapping
[index
]];
4512 case PROGRAM_ADDRESS
:
4513 return t
->address
[index
];
4516 assert(!"unknown dst register file");
4517 return ureg_dst_undef();
4522 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
4524 static struct ureg_src
4525 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
4527 int index
= reg
->index
;
4528 int double_reg2
= reg
->double_reg2
? 1 : 0;
4531 case PROGRAM_UNDEFINED
:
4532 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4534 case PROGRAM_TEMPORARY
:
4536 return ureg_src(dst_register(t
, reg
->file
, reg
->index
));
4538 case PROGRAM_UNIFORM
:
4539 assert(reg
->index
>= 0);
4540 return reg
->index
< t
->num_constants
?
4541 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4542 case PROGRAM_STATE_VAR
:
4543 case PROGRAM_CONSTANT
: /* ie, immediate */
4544 if (reg
->has_index2
)
4545 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
4547 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
4548 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4550 case PROGRAM_IMMEDIATE
:
4551 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
4552 return t
->immediates
[reg
->index
];
4555 /* GLSL inputs are 64-bit containers, so we have to
4556 * map back to the original index and add the offset after
4558 index
-= double_reg2
;
4559 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
4560 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
4562 case PROGRAM_OUTPUT
:
4563 assert(t
->outputMapping
[reg
->index
] < ARRAY_SIZE(t
->outputs
));
4564 return ureg_src(t
->outputs
[t
->outputMapping
[reg
->index
]]); /* not needed? */
4566 case PROGRAM_ADDRESS
:
4567 return ureg_src(t
->address
[reg
->index
]);
4569 case PROGRAM_SYSTEM_VALUE
:
4570 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
4571 return t
->systemValues
[reg
->index
];
4574 assert(!"unknown src register file");
4575 return ureg_src_undef();
4580 * Create a TGSI ureg_dst register from an st_dst_reg.
4582 static struct ureg_dst
4583 translate_dst(struct st_translate
*t
,
4584 const st_dst_reg
*dst_reg
,
4585 bool saturate
, bool clamp_color
)
4587 struct ureg_dst dst
= dst_register(t
,
4591 if (dst
.File
== TGSI_FILE_NULL
)
4594 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
4597 dst
= ureg_saturate(dst
);
4598 else if (clamp_color
&& dst_reg
->file
== PROGRAM_OUTPUT
) {
4599 /* Clamp colors for ARB_color_buffer_float. */
4600 switch (t
->procType
) {
4601 case TGSI_PROCESSOR_VERTEX
:
4602 /* This can only occur with a compatibility profile, which doesn't
4603 * support geometry shaders. */
4604 if (dst_reg
->index
== VARYING_SLOT_COL0
||
4605 dst_reg
->index
== VARYING_SLOT_COL1
||
4606 dst_reg
->index
== VARYING_SLOT_BFC0
||
4607 dst_reg
->index
== VARYING_SLOT_BFC1
) {
4608 dst
= ureg_saturate(dst
);
4612 case TGSI_PROCESSOR_FRAGMENT
:
4613 if (dst_reg
->index
== FRAG_RESULT_COLOR
||
4614 dst_reg
->index
>= FRAG_RESULT_DATA0
) {
4615 dst
= ureg_saturate(dst
);
4621 if (dst_reg
->reladdr
!= NULL
) {
4622 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
4623 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
4630 * Create a TGSI ureg_src register from an st_src_reg.
4632 static struct ureg_src
4633 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
4635 struct ureg_src src
= src_register(t
, src_reg
);
4637 if (src_reg
->has_index2
) {
4638 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
4639 * and UBO constant buffers (buffer, position).
4641 if (src_reg
->reladdr2
)
4642 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
4645 src
= ureg_src_dimension(src
, src_reg
->index2D
);
4648 src
= ureg_swizzle(src
,
4649 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
4650 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
4651 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
4652 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
4654 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
4655 src
= ureg_negate(src
);
4657 if (src_reg
->reladdr
!= NULL
) {
4658 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
4659 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
4665 static struct tgsi_texture_offset
4666 translate_tex_offset(struct st_translate
*t
,
4667 const st_src_reg
*in_offset
, int idx
)
4669 struct tgsi_texture_offset offset
;
4670 struct ureg_src imm_src
;
4671 struct ureg_dst dst
;
4674 switch (in_offset
->file
) {
4675 case PROGRAM_IMMEDIATE
:
4676 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
4677 imm_src
= t
->immediates
[in_offset
->index
];
4679 offset
.File
= imm_src
.File
;
4680 offset
.Index
= imm_src
.Index
;
4681 offset
.SwizzleX
= imm_src
.SwizzleX
;
4682 offset
.SwizzleY
= imm_src
.SwizzleY
;
4683 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
4686 case PROGRAM_TEMPORARY
:
4687 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
4688 offset
.File
= imm_src
.File
;
4689 offset
.Index
= imm_src
.Index
;
4690 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4691 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4692 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4696 array
= in_offset
->index
>> 16;
4699 assert(array
< (int)t
->num_temp_arrays
);
4701 dst
= t
->arrays
[array
];
4702 offset
.File
= dst
.File
;
4703 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
4704 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4705 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4706 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4716 compile_tgsi_instruction(struct st_translate
*t
,
4717 const glsl_to_tgsi_instruction
*inst
,
4718 bool clamp_dst_color_output
)
4720 struct ureg_program
*ureg
= t
->ureg
;
4722 struct ureg_dst dst
[2];
4723 struct ureg_src src
[4];
4724 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
4728 unsigned tex_target
;
4730 num_dst
= num_inst_dst_regs(inst
->op
);
4731 num_src
= num_inst_src_regs(inst
->op
);
4733 for (i
= 0; i
< num_dst
; i
++)
4734 dst
[i
] = translate_dst(t
,
4737 clamp_dst_color_output
);
4739 for (i
= 0; i
< num_src
; i
++)
4740 src
[i
] = translate_src(t
, &inst
->src
[i
]);
4743 case TGSI_OPCODE_BGNLOOP
:
4744 case TGSI_OPCODE_CAL
:
4745 case TGSI_OPCODE_ELSE
:
4746 case TGSI_OPCODE_ENDLOOP
:
4747 case TGSI_OPCODE_IF
:
4748 case TGSI_OPCODE_UIF
:
4749 assert(num_dst
== 0);
4750 ureg_label_insn(ureg
,
4754 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
4757 case TGSI_OPCODE_TEX
:
4758 case TGSI_OPCODE_TXB
:
4759 case TGSI_OPCODE_TXD
:
4760 case TGSI_OPCODE_TXL
:
4761 case TGSI_OPCODE_TXP
:
4762 case TGSI_OPCODE_TXQ
:
4763 case TGSI_OPCODE_TXF
:
4764 case TGSI_OPCODE_TEX2
:
4765 case TGSI_OPCODE_TXB2
:
4766 case TGSI_OPCODE_TXL2
:
4767 case TGSI_OPCODE_TG4
:
4768 case TGSI_OPCODE_LODQ
:
4769 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
4770 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
4771 if (inst
->sampler
.reladdr
)
4773 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
4775 for (i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4776 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
4778 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4784 texoffsets
, inst
->tex_offset_num_offset
,
4788 case TGSI_OPCODE_SCS
:
4789 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
4790 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
4803 * Emit the TGSI instructions for inverting and adjusting WPOS.
4804 * This code is unavoidable because it also depends on whether
4805 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
4808 emit_wpos_adjustment( struct st_translate
*t
,
4809 int wpos_transform_const
,
4811 GLfloat adjX
, GLfloat adjY
[2])
4813 struct ureg_program
*ureg
= t
->ureg
;
4815 assert(wpos_transform_const
>= 0);
4817 /* Fragment program uses fragment position input.
4818 * Need to replace instances of INPUT[WPOS] with temp T
4819 * where T = INPUT[WPOS] is inverted by Y.
4821 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
4822 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
4823 struct ureg_src wpos_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
4825 /* First, apply the coordinate shift: */
4826 if (adjX
|| adjY
[0] || adjY
[1]) {
4827 if (adjY
[0] != adjY
[1]) {
4828 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
4829 * depending on whether inversion is actually going to be applied
4830 * or not, which is determined by testing against the inversion
4831 * state variable used below, which will be either +1 or -1.
4833 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
4835 ureg_CMP(ureg
, adj_temp
,
4836 ureg_scalar(wpostrans
, invert
? 2 : 0),
4837 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
4838 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
4839 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
4841 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
4842 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
4844 wpos_input
= ureg_src(wpos_temp
);
4846 /* MOV wpos_temp, input[wpos]
4848 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
4851 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
4852 * inversion/identity, or the other way around if we're drawing to an FBO.
4855 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
4858 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4860 ureg_scalar(wpostrans
, 0),
4861 ureg_scalar(wpostrans
, 1));
4863 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
4866 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
4868 ureg_scalar(wpostrans
, 2),
4869 ureg_scalar(wpostrans
, 3));
4872 /* Use wpos_temp as position input from here on:
4874 t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]] = ureg_src(wpos_temp
);
4879 * Emit fragment position/ooordinate code.
4882 emit_wpos(struct st_context
*st
,
4883 struct st_translate
*t
,
4884 const struct gl_program
*program
,
4885 struct ureg_program
*ureg
,
4886 int wpos_transform_const
)
4888 const struct gl_fragment_program
*fp
=
4889 (const struct gl_fragment_program
*) program
;
4890 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
4891 GLfloat adjX
= 0.0f
;
4892 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
4893 boolean invert
= FALSE
;
4895 /* Query the pixel center conventions supported by the pipe driver and set
4896 * adjX, adjY to help out if it cannot handle the requested one internally.
4898 * The bias of the y-coordinate depends on whether y-inversion takes place
4899 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
4900 * drawing to an FBO (causes additional inversion), and whether the the pipe
4901 * driver origin and the requested origin differ (the latter condition is
4902 * stored in the 'invert' variable).
4904 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
4906 * center shift only:
4911 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
4912 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
4913 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
4914 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
4916 * inversion and center shift:
4917 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
4918 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
4919 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
4920 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
4922 if (fp
->OriginUpperLeft
) {
4923 /* Fragment shader wants origin in upper-left */
4924 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
4925 /* the driver supports upper-left origin */
4927 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
4928 /* the driver supports lower-left origin, need to invert Y */
4929 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
4930 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
4937 /* Fragment shader wants origin in lower-left */
4938 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
4939 /* the driver supports lower-left origin */
4940 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
4941 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
4942 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
4943 /* the driver supports upper-left origin, need to invert Y */
4949 if (fp
->PixelCenterInteger
) {
4950 /* Fragment shader wants pixel center integer */
4951 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
4952 /* the driver supports pixel center integer */
4954 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
4955 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
4957 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
4958 /* the driver supports pixel center half integer, need to bias X,Y */
4967 /* Fragment shader wants pixel center half integer */
4968 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
4969 /* the driver supports pixel center half integer */
4971 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
4972 /* the driver supports pixel center integer, need to bias X,Y */
4973 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
4974 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
4975 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
4981 /* we invert after adjustment so that we avoid the MOV to temporary,
4982 * and reuse the adjustment ADD instead */
4983 emit_wpos_adjustment(t
, wpos_transform_const
, invert
, adjX
, adjY
);
4987 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
4988 * TGSI uses +1 for front, -1 for back.
4989 * This function converts the TGSI value to the GL value. Simply clamping/
4990 * saturating the value to [0,1] does the job.
4993 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
4995 struct ureg_program
*ureg
= t
->ureg
;
4996 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
4997 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
4999 if (ctx
->Const
.NativeIntegers
) {
5000 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5003 /* MOV_SAT face_temp, input[face] */
5004 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5007 /* Use face_temp as face input from here on: */
5008 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5012 emit_edgeflags(struct st_translate
*t
)
5014 struct ureg_program
*ureg
= t
->ureg
;
5015 struct ureg_dst edge_dst
= t
->outputs
[t
->outputMapping
[VARYING_SLOT_EDGE
]];
5016 struct ureg_src edge_src
= t
->inputs
[t
->inputMapping
[VERT_ATTRIB_EDGEFLAG
]];
5018 ureg_MOV(ureg
, edge_dst
, edge_src
);
5022 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5023 * \param program the program to translate
5024 * \param numInputs number of input registers used
5025 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5027 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5028 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5030 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5031 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5032 * \param numOutputs number of output registers used
5033 * \param outputMapping maps Mesa fragment program outputs to TGSI
5035 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5036 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5039 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5041 extern "C" enum pipe_error
5042 st_translate_program(
5043 struct gl_context
*ctx
,
5045 struct ureg_program
*ureg
,
5046 glsl_to_tgsi_visitor
*program
,
5047 const struct gl_program
*proginfo
,
5049 const GLuint inputMapping
[],
5050 const ubyte inputSemanticName
[],
5051 const ubyte inputSemanticIndex
[],
5052 const GLuint interpMode
[],
5053 const GLuint interpLocation
[],
5055 const GLuint outputMapping
[],
5056 const ubyte outputSemanticName
[],
5057 const ubyte outputSemanticIndex
[],
5058 boolean passthrough_edgeflags
,
5059 boolean clamp_color
)
5061 struct st_translate
*t
;
5063 enum pipe_error ret
= PIPE_OK
;
5065 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5066 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5068 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5069 TGSI_SEMANTIC_FACE
);
5070 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5071 TGSI_SEMANTIC_VERTEXID
);
5072 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5073 TGSI_SEMANTIC_INSTANCEID
);
5074 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5075 TGSI_SEMANTIC_SAMPLEID
);
5076 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5077 TGSI_SEMANTIC_SAMPLEPOS
);
5078 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5079 TGSI_SEMANTIC_SAMPLEMASK
);
5080 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5081 TGSI_SEMANTIC_INVOCATIONID
);
5082 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5083 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5084 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5085 TGSI_SEMANTIC_BASEVERTEX
);
5087 t
= CALLOC_STRUCT(st_translate
);
5089 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5093 t
->procType
= procType
;
5094 t
->inputMapping
= inputMapping
;
5095 t
->outputMapping
= outputMapping
;
5097 t
->num_temp_arrays
= program
->next_array
;
5098 if (t
->num_temp_arrays
)
5099 t
->arrays
= (struct ureg_dst
*)
5100 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5103 * Declare input attributes.
5105 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
5106 for (i
= 0; i
< numInputs
; i
++) {
5107 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5108 inputSemanticName
[i
],
5109 inputSemanticIndex
[i
],
5111 interpLocation
[i
], 0, 1);
5114 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
5115 /* Must do this after setting up t->inputs. */
5116 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
5117 program
->wpos_transform_const
);
5120 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
5121 emit_face_var(ctx
, t
);
5124 * Declare output attributes.
5126 for (i
= 0; i
< numOutputs
; i
++) {
5127 switch (outputSemanticName
[i
]) {
5128 case TGSI_SEMANTIC_POSITION
:
5129 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5130 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
5131 outputSemanticIndex
[i
]);
5132 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
5134 case TGSI_SEMANTIC_STENCIL
:
5135 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5136 TGSI_SEMANTIC_STENCIL
, /* Stencil */
5137 outputSemanticIndex
[i
]);
5138 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
5140 case TGSI_SEMANTIC_COLOR
:
5141 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5142 TGSI_SEMANTIC_COLOR
,
5143 outputSemanticIndex
[i
]);
5145 case TGSI_SEMANTIC_SAMPLEMASK
:
5146 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5147 TGSI_SEMANTIC_SAMPLEMASK
,
5148 outputSemanticIndex
[i
]);
5149 /* TODO: If we ever support more than 32 samples, this will have
5150 * to become an array.
5152 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5155 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
5156 ret
= PIPE_ERROR_BAD_INPUT
;
5161 else if (procType
== TGSI_PROCESSOR_GEOMETRY
) {
5162 for (i
= 0; i
< numInputs
; i
++) {
5163 t
->inputs
[i
] = ureg_DECL_input(ureg
,
5164 inputSemanticName
[i
],
5165 inputSemanticIndex
[i
], 0, 1);
5168 for (i
= 0; i
< numOutputs
; i
++) {
5169 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5170 outputSemanticName
[i
],
5171 outputSemanticIndex
[i
]);
5175 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5177 for (i
= 0; i
< numInputs
; i
++) {
5178 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
5181 for (i
= 0; i
< numOutputs
; i
++) {
5182 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5183 outputSemanticName
[i
],
5184 outputSemanticIndex
[i
]);
5185 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
5186 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
5188 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
5189 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
5190 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5193 if (passthrough_edgeflags
)
5197 /* Declare address register.
5199 if (program
->num_address_regs
> 0) {
5200 assert(program
->num_address_regs
<= 3);
5201 for (int i
= 0; i
< program
->num_address_regs
; i
++)
5202 t
->address
[i
] = ureg_DECL_address(ureg
);
5205 /* Declare misc input registers
5208 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
5209 unsigned numSys
= 0;
5210 for (i
= 0; sysInputs
; i
++) {
5211 if (sysInputs
& (1 << i
)) {
5212 unsigned semName
= _mesa_sysval_to_semantic
[i
];
5213 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, numSys
, semName
, 0);
5214 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
5215 semName
== TGSI_SEMANTIC_VERTEXID
) {
5216 /* From Gallium perspective, these system values are always
5217 * integer, and require native integer support. However, if
5218 * native integer is supported on the vertex stage but not the
5219 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
5220 * assumes these system values are floats. To resolve the
5221 * inconsistency, we insert a U2F.
5223 struct st_context
*st
= st_context(ctx
);
5224 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5225 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5226 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
5227 if (!ctx
->Const
.NativeIntegers
) {
5228 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
5229 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
5230 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
5234 sysInputs
&= ~(1 << i
);
5239 t
->array_sizes
= program
->array_sizes
;
5241 /* Emit constants and uniforms. TGSI uses a single index space for these,
5242 * so we put all the translated regs in t->constants.
5244 if (proginfo
->Parameters
) {
5245 t
->constants
= (struct ureg_src
*)
5246 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
5247 if (t
->constants
== NULL
) {
5248 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5251 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
5253 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
5254 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
5255 case PROGRAM_STATE_VAR
:
5256 case PROGRAM_UNIFORM
:
5257 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5260 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
5261 * addressing of the const buffer.
5262 * FIXME: Be smarter and recognize param arrays:
5263 * indirect addressing is only valid within the referenced
5266 case PROGRAM_CONSTANT
:
5267 if (program
->indirect_addr_consts
)
5268 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5270 t
->constants
[i
] = emit_immediate(t
,
5271 proginfo
->Parameters
->ParameterValues
[i
],
5272 proginfo
->Parameters
->Parameters
[i
].DataType
,
5281 if (program
->shader
) {
5282 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
5284 for (i
= 0; i
< num_ubos
; i
++) {
5285 unsigned size
= program
->shader
->UniformBlocks
[i
].UniformBufferSize
;
5286 unsigned num_const_vecs
= (size
+ 15) / 16;
5287 unsigned first
, last
;
5288 assert(num_const_vecs
> 0);
5290 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
5291 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
5295 /* Emit immediate values.
5297 t
->immediates
= (struct ureg_src
*)
5298 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
5299 if (t
->immediates
== NULL
) {
5300 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5303 t
->num_immediates
= program
->num_immediates
;
5306 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
5307 assert(i
< program
->num_immediates
);
5308 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
5310 assert(i
== program
->num_immediates
);
5312 /* texture samplers */
5313 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
5314 if (program
->samplers_used
& (1 << i
)) {
5315 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
5319 /* Emit each instruction in turn:
5321 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
5322 set_insn_start(t
, ureg_get_instruction_number(ureg
));
5323 compile_tgsi_instruction(t
, inst
, clamp_color
);
5326 /* Fix up all emitted labels:
5328 for (i
= 0; i
< t
->labels_count
; i
++) {
5329 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
5330 t
->insn
[t
->labels
[i
].branch_target
]);
5340 t
->num_constants
= 0;
5341 free(t
->immediates
);
5342 t
->num_immediates
= 0;
5345 debug_printf("%s: translate error flag set\n", __func__
);
5353 /* ----------------------------- End TGSI code ------------------------------ */
5357 shader_stage_to_ptarget(gl_shader_stage stage
)
5360 case MESA_SHADER_VERTEX
:
5361 return PIPE_SHADER_VERTEX
;
5362 case MESA_SHADER_FRAGMENT
:
5363 return PIPE_SHADER_FRAGMENT
;
5364 case MESA_SHADER_GEOMETRY
:
5365 return PIPE_SHADER_GEOMETRY
;
5366 case MESA_SHADER_COMPUTE
:
5367 return PIPE_SHADER_COMPUTE
;
5370 assert(!"should not be reached");
5371 return PIPE_SHADER_VERTEX
;
5376 * Convert a shader's GLSL IR into a Mesa gl_program, although without
5377 * generating Mesa IR.
5379 static struct gl_program
*
5380 get_mesa_program(struct gl_context
*ctx
,
5381 struct gl_shader_program
*shader_program
,
5382 struct gl_shader
*shader
)
5384 glsl_to_tgsi_visitor
* v
;
5385 struct gl_program
*prog
;
5386 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
5388 struct gl_shader_compiler_options
*options
=
5389 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
5390 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5391 unsigned ptarget
= shader_stage_to_ptarget(shader
->Stage
);
5393 validate_ir_tree(shader
->ir
);
5395 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
5398 prog
->Parameters
= _mesa_new_parameter_list();
5399 v
= new glsl_to_tgsi_visitor();
5402 v
->shader_program
= shader_program
;
5404 v
->options
= options
;
5405 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
5406 v
->native_integers
= ctx
->Const
.NativeIntegers
;
5408 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
5409 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
5410 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
5411 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
5413 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
5414 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
5417 /* Remove reads from output registers. */
5418 lower_output_reads(shader
->ir
);
5420 /* Emit intermediate IR for main(). */
5421 visit_exec_list(shader
->ir
, v
);
5423 /* Now emit bodies for any functions that were used. */
5425 progress
= GL_FALSE
;
5427 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
5428 if (!entry
->bgn_inst
) {
5429 v
->current_function
= entry
;
5431 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
5432 entry
->bgn_inst
->function
= entry
;
5434 visit_exec_list(&entry
->sig
->body
, v
);
5436 glsl_to_tgsi_instruction
*last
;
5437 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
5438 if (last
->op
!= TGSI_OPCODE_RET
)
5439 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
5441 glsl_to_tgsi_instruction
*end
;
5442 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
5443 end
->function
= entry
;
5451 /* Print out some information (for debugging purposes) used by the
5452 * optimization passes. */
5453 for (i
= 0; i
< v
->next_temp
; i
++) {
5454 int fr
= v
->get_first_temp_read(i
);
5455 int fw
= v
->get_first_temp_write(i
);
5456 int lr
= v
->get_last_temp_read(i
);
5457 int lw
= v
->get_last_temp_write(i
);
5459 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, fr
, fw
, lr
, lw
);
5464 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
5466 v
->copy_propagate();
5467 while (v
->eliminate_dead_code());
5469 v
->merge_two_dsts();
5470 v
->merge_registers();
5471 v
->renumber_registers();
5473 /* Write the END instruction. */
5474 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
5476 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
5478 _mesa_log("GLSL IR for linked %s program %d:\n",
5479 _mesa_shader_stage_to_string(shader
->Stage
),
5480 shader_program
->Name
);
5481 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
5485 prog
->Instructions
= NULL
;
5486 prog
->NumInstructions
= 0;
5488 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
5489 count_resources(v
, prog
);
5491 /* This must be done before the uniform storage is associated. */
5492 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
5493 prog
->InputsRead
& VARYING_BIT_POS
){
5494 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
5495 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
5498 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
5499 wposTransformState
);
5502 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
5504 /* This has to be done last. Any operation the can cause
5505 * prog->ParameterValues to get reallocated (e.g., anything that adds a
5506 * program constant) has to happen before creating this linkage.
5508 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
5509 if (!shader_program
->LinkStatus
) {
5510 free_glsl_to_tgsi_visitor(v
);
5514 struct st_vertex_program
*stvp
;
5515 struct st_fragment_program
*stfp
;
5516 struct st_geometry_program
*stgp
;
5518 switch (shader
->Type
) {
5519 case GL_VERTEX_SHADER
:
5520 stvp
= (struct st_vertex_program
*)prog
;
5521 stvp
->glsl_to_tgsi
= v
;
5523 case GL_FRAGMENT_SHADER
:
5524 stfp
= (struct st_fragment_program
*)prog
;
5525 stfp
->glsl_to_tgsi
= v
;
5527 case GL_GEOMETRY_SHADER
:
5528 stgp
= (struct st_geometry_program
*)prog
;
5529 stgp
->glsl_to_tgsi
= v
;
5532 assert(!"should not be reached");
5543 * Called via ctx->Driver.LinkShader()
5544 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
5545 * with code lowering and other optimizations.
5548 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
5550 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5551 assert(prog
->LinkStatus
);
5553 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5554 if (prog
->_LinkedShaders
[i
] == NULL
)
5558 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
5559 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
5560 const struct gl_shader_compiler_options
*options
=
5561 &ctx
->Const
.ShaderCompilerOptions
[stage
];
5562 unsigned ptarget
= shader_stage_to_ptarget(stage
);
5563 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
5564 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
5565 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
5566 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
5568 /* If there are forms of indirect addressing that the driver
5569 * cannot handle, perform the lowering pass.
5571 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
5572 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
5573 lower_variable_index_to_cond_assign(ir
,
5574 options
->EmitNoIndirectInput
,
5575 options
->EmitNoIndirectOutput
,
5576 options
->EmitNoIndirectTemp
,
5577 options
->EmitNoIndirectUniform
);
5580 if (ctx
->Extensions
.ARB_shading_language_packing
) {
5581 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
5582 LOWER_UNPACK_SNORM_2x16
|
5583 LOWER_PACK_UNORM_2x16
|
5584 LOWER_UNPACK_UNORM_2x16
|
5585 LOWER_PACK_SNORM_4x8
|
5586 LOWER_UNPACK_SNORM_4x8
|
5587 LOWER_UNPACK_UNORM_4x8
|
5588 LOWER_PACK_UNORM_4x8
|
5589 LOWER_PACK_HALF_2x16
|
5590 LOWER_UNPACK_HALF_2x16
;
5592 lower_packing_builtins(ir
, lower_inst
);
5595 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
5596 lower_offset_arrays(ir
);
5597 do_mat_op_to_vec(ir
);
5598 lower_instructions(ir
,
5604 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
5607 (have_dround
? 0 : DOPS_TO_DFRAC
) |
5608 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
5609 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
5610 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
5612 lower_ubo_reference(prog
->_LinkedShaders
[i
], ir
);
5613 do_vec_index_to_cond_assign(ir
);
5614 lower_vector_insert(ir
, true);
5615 lower_quadop_vector(ir
, false);
5617 if (options
->MaxIfDepth
== 0) {
5624 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
5626 progress
= do_common_optimization(ir
, true, true, options
,
5627 ctx
->Const
.NativeIntegers
)
5630 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
5634 validate_ir_tree(ir
);
5637 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5638 struct gl_program
*linked_prog
;
5640 if (prog
->_LinkedShaders
[i
] == NULL
)
5643 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
5646 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5648 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
5649 _mesa_shader_stage_to_program(i
),
5651 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
5653 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5658 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
5665 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
5666 const GLuint outputMapping
[],
5667 struct pipe_stream_output_info
*so
)
5670 struct gl_transform_feedback_info
*info
=
5671 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
5673 for (i
= 0; i
< info
->NumOutputs
; i
++) {
5674 so
->output
[i
].register_index
=
5675 outputMapping
[info
->Outputs
[i
].OutputRegister
];
5676 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
5677 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
5678 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
5679 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
5680 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
5683 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
5684 so
->stride
[i
] = info
->BufferStride
[i
];
5686 so
->num_outputs
= info
->NumOutputs
;