2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
57 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
58 (1 << PROGRAM_CONSTANT) | \
59 (1 << PROGRAM_UNIFORM))
61 #define MAX_GLSL_TEXTURE_OFFSET 4
66 static int swizzle_for_size(int size
);
69 * This struct is a corresponding struct to TGSI ureg_src.
73 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
83 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
85 this->reladdr2
= NULL
;
86 this->has_index2
= false;
87 this->double_reg2
= false;
89 this->is_double_vertex_input
= false;
92 st_src_reg(gl_register_file file
, int index
, int type
)
98 this->swizzle
= SWIZZLE_XYZW
;
100 this->reladdr
= NULL
;
101 this->reladdr2
= NULL
;
102 this->has_index2
= false;
103 this->double_reg2
= false;
105 this->is_double_vertex_input
= false;
108 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
113 this->index2D
= index2D
;
114 this->swizzle
= SWIZZLE_XYZW
;
116 this->reladdr
= NULL
;
117 this->reladdr2
= NULL
;
118 this->has_index2
= false;
119 this->double_reg2
= false;
121 this->is_double_vertex_input
= false;
126 this->type
= GLSL_TYPE_ERROR
;
127 this->file
= PROGRAM_UNDEFINED
;
132 this->reladdr
= NULL
;
133 this->reladdr2
= NULL
;
134 this->has_index2
= false;
135 this->double_reg2
= false;
137 this->is_double_vertex_input
= false;
140 explicit st_src_reg(st_dst_reg reg
);
142 gl_register_file file
; /**< PROGRAM_* from Mesa */
143 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
145 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
146 int negate
; /**< NEGATE_XYZW mask from mesa */
147 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
148 /** Register index should be offset by the integer in this reg. */
150 st_src_reg
*reladdr2
;
153 * Is this the second half of a double register pair?
154 * currently used for input mapping only.
158 bool is_double_vertex_input
;
163 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
168 this->writemask
= writemask
;
169 this->reladdr
= NULL
;
170 this->reladdr2
= NULL
;
171 this->has_index2
= false;
176 st_dst_reg(gl_register_file file
, int writemask
, int type
)
181 this->writemask
= writemask
;
182 this->reladdr
= NULL
;
183 this->reladdr2
= NULL
;
184 this->has_index2
= false;
191 this->type
= GLSL_TYPE_ERROR
;
192 this->file
= PROGRAM_UNDEFINED
;
196 this->reladdr
= NULL
;
197 this->reladdr2
= NULL
;
198 this->has_index2
= false;
202 explicit st_dst_reg(st_src_reg reg
);
204 gl_register_file file
; /**< PROGRAM_* from Mesa */
205 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
207 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
208 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
209 /** Register index should be offset by the integer in this reg. */
211 st_src_reg
*reladdr2
;
216 st_src_reg::st_src_reg(st_dst_reg reg
)
218 this->type
= reg
.type
;
219 this->file
= reg
.file
;
220 this->index
= reg
.index
;
221 this->swizzle
= SWIZZLE_XYZW
;
223 this->reladdr
= reg
.reladdr
;
224 this->index2D
= reg
.index2D
;
225 this->reladdr2
= reg
.reladdr2
;
226 this->has_index2
= reg
.has_index2
;
227 this->double_reg2
= false;
228 this->array_id
= reg
.array_id
;
229 this->is_double_vertex_input
= false;
232 st_dst_reg::st_dst_reg(st_src_reg reg
)
234 this->type
= reg
.type
;
235 this->file
= reg
.file
;
236 this->index
= reg
.index
;
237 this->writemask
= WRITEMASK_XYZW
;
238 this->reladdr
= reg
.reladdr
;
239 this->index2D
= reg
.index2D
;
240 this->reladdr2
= reg
.reladdr2
;
241 this->has_index2
= reg
.has_index2
;
242 this->array_id
= reg
.array_id
;
245 class glsl_to_tgsi_instruction
: public exec_node
{
247 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
252 /** Pointer to the ir source this tree came from for debugging */
254 GLboolean cond_update
;
256 st_src_reg sampler
; /**< sampler register */
258 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
259 int tex_target
; /**< One of TEXTURE_*_INDEX */
260 glsl_base_type tex_type
;
261 GLboolean tex_shadow
;
262 unsigned image_format
;
264 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
265 unsigned tex_offset_num_offset
;
266 int dead_mask
; /**< Used in dead code elimination */
268 st_src_reg buffer
; /**< buffer register */
269 unsigned buffer_access
; /**< buffer access type */
271 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
272 const struct tgsi_opcode_info
*info
;
275 class variable_storage
: public exec_node
{
277 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
278 unsigned array_id
= 0)
279 : file(file
), index(index
), var(var
), array_id(array_id
)
284 gl_register_file file
;
286 ir_variable
*var
; /* variable that maps to this, if any */
290 class immediate_storage
: public exec_node
{
292 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
294 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
295 this->size32
= size32
;
299 /* doubles are stored across 2 gl_constant_values */
300 gl_constant_value values
[4];
301 int size32
; /**< Number of 32-bit components (1-4) */
302 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
305 class function_entry
: public exec_node
{
307 ir_function_signature
*sig
;
310 * identifier of this function signature used by the program.
312 * At the point that TGSI instructions for function calls are
313 * generated, we don't know the address of the first instruction of
314 * the function body. So we make the BranchTarget that is called a
315 * small integer and rewrite them during set_branchtargets().
320 * Pointer to first instruction of the function body.
322 * Set during function body emits after main() is processed.
324 glsl_to_tgsi_instruction
*bgn_inst
;
327 * Index of the first instruction of the function body in actual TGSI.
329 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
333 /** Storage for the return value. */
334 st_src_reg return_reg
;
337 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
338 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
348 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
352 for (i
= 0; i
< count
; i
++) {
353 struct array_decl
*decl
= &arrays
[i
];
355 if (array_id
== decl
->array_id
) {
356 return decl
->array_type
;
359 return GLSL_TYPE_ERROR
;
362 struct rename_reg_pair
{
367 struct glsl_to_tgsi_visitor
: public ir_visitor
{
369 glsl_to_tgsi_visitor();
370 ~glsl_to_tgsi_visitor();
372 function_entry
*current_function
;
374 struct gl_context
*ctx
;
375 struct gl_program
*prog
;
376 struct gl_shader_program
*shader_program
;
377 struct gl_shader
*shader
;
378 struct gl_shader_compiler_options
*options
;
382 unsigned *array_sizes
;
383 unsigned max_num_arrays
;
386 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
387 unsigned num_input_arrays
;
388 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
389 unsigned num_output_arrays
;
391 int num_address_regs
;
392 uint32_t samplers_used
;
393 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
394 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
397 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
398 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
399 bool indirect_addr_consts
;
400 int wpos_transform_const
;
403 bool native_integers
;
406 bool use_shared_memory
;
408 variable_storage
*find_variable_storage(ir_variable
*var
);
410 int add_constant(gl_register_file file
, gl_constant_value values
[8],
411 int size
, int datatype
, GLuint
*swizzle_out
);
413 function_entry
*get_function_signature(ir_function_signature
*sig
);
415 st_src_reg
get_temp(const glsl_type
*type
);
416 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
418 st_src_reg
st_src_reg_for_double(double val
);
419 st_src_reg
st_src_reg_for_float(float val
);
420 st_src_reg
st_src_reg_for_int(int val
);
421 st_src_reg
st_src_reg_for_type(int type
, int val
);
424 * \name Visit methods
426 * As typical for the visitor pattern, there must be one \c visit method for
427 * each concrete subclass of \c ir_instruction. Virtual base classes within
428 * the hierarchy should not have \c visit methods.
431 virtual void visit(ir_variable
*);
432 virtual void visit(ir_loop
*);
433 virtual void visit(ir_loop_jump
*);
434 virtual void visit(ir_function_signature
*);
435 virtual void visit(ir_function
*);
436 virtual void visit(ir_expression
*);
437 virtual void visit(ir_swizzle
*);
438 virtual void visit(ir_dereference_variable
*);
439 virtual void visit(ir_dereference_array
*);
440 virtual void visit(ir_dereference_record
*);
441 virtual void visit(ir_assignment
*);
442 virtual void visit(ir_constant
*);
443 virtual void visit(ir_call
*);
444 virtual void visit(ir_return
*);
445 virtual void visit(ir_discard
*);
446 virtual void visit(ir_texture
*);
447 virtual void visit(ir_if
*);
448 virtual void visit(ir_emit_vertex
*);
449 virtual void visit(ir_end_primitive
*);
450 virtual void visit(ir_barrier
*);
453 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
455 void visit_atomic_counter_intrinsic(ir_call
*);
456 void visit_ssbo_intrinsic(ir_call
*);
457 void visit_membar_intrinsic(ir_call
*);
458 void visit_shared_intrinsic(ir_call
*);
459 void visit_image_intrinsic(ir_call
*);
463 /** List of variable_storage */
466 /** List of immediate_storage */
467 exec_list immediates
;
468 unsigned num_immediates
;
470 /** List of function_entry */
471 exec_list function_signatures
;
472 int next_signature_id
;
474 /** List of glsl_to_tgsi_instruction */
475 exec_list instructions
;
477 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
478 st_dst_reg dst
= undef_dst
,
479 st_src_reg src0
= undef_src
,
480 st_src_reg src1
= undef_src
,
481 st_src_reg src2
= undef_src
,
482 st_src_reg src3
= undef_src
);
484 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
485 st_dst_reg dst
, st_dst_reg dst1
,
486 st_src_reg src0
= undef_src
,
487 st_src_reg src1
= undef_src
,
488 st_src_reg src2
= undef_src
,
489 st_src_reg src3
= undef_src
);
491 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
493 st_src_reg src0
, st_src_reg src1
);
496 * Emit the correct dot-product instruction for the type of arguments
498 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
504 void emit_scalar(ir_instruction
*ir
, unsigned op
,
505 st_dst_reg dst
, st_src_reg src0
);
507 void emit_scalar(ir_instruction
*ir
, unsigned op
,
508 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
510 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
512 void get_deref_offsets(ir_dereference
*ir
,
513 unsigned *array_size
,
516 st_src_reg
*reladdr
);
517 void calc_deref_offsets(ir_dereference
*head
,
518 ir_dereference
*tail
,
519 unsigned *array_elements
,
522 st_src_reg
*indirect
,
525 bool try_emit_mad(ir_expression
*ir
,
527 bool try_emit_mad_for_and_not(ir_expression
*ir
,
530 void emit_swz(ir_expression
*ir
);
532 bool process_move_condition(ir_rvalue
*ir
);
534 void simplify_cmp(void);
536 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
537 void get_first_temp_read(int *first_reads
);
538 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
539 void get_last_temp_write(int *last_writes
);
541 void copy_propagate(void);
542 int eliminate_dead_code(void);
544 void merge_two_dsts(void);
545 void merge_registers(void);
546 void renumber_registers(void);
548 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
549 st_dst_reg
*l
, st_src_reg
*r
,
550 st_src_reg
*cond
, bool cond_swap
);
555 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
556 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
557 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
560 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
563 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
567 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
570 prog
->LinkStatus
= GL_FALSE
;
574 swizzle_for_size(int size
)
576 static const int size_swizzles
[4] = {
577 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
578 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
579 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
580 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
583 assert((size
>= 1) && (size
<= 4));
584 return size_swizzles
[size
- 1];
588 is_resource_instruction(unsigned opcode
)
591 case TGSI_OPCODE_RESQ
:
592 case TGSI_OPCODE_LOAD
:
593 case TGSI_OPCODE_ATOMUADD
:
594 case TGSI_OPCODE_ATOMXCHG
:
595 case TGSI_OPCODE_ATOMCAS
:
596 case TGSI_OPCODE_ATOMAND
:
597 case TGSI_OPCODE_ATOMOR
:
598 case TGSI_OPCODE_ATOMXOR
:
599 case TGSI_OPCODE_ATOMUMIN
:
600 case TGSI_OPCODE_ATOMUMAX
:
601 case TGSI_OPCODE_ATOMIMIN
:
602 case TGSI_OPCODE_ATOMIMAX
:
610 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
612 return op
->info
->num_dst
;
616 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
618 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
619 op
->info
->num_src
- 1 : op
->info
->num_src
;
622 glsl_to_tgsi_instruction
*
623 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
624 st_dst_reg dst
, st_dst_reg dst1
,
625 st_src_reg src0
, st_src_reg src1
,
626 st_src_reg src2
, st_src_reg src3
)
628 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
629 int num_reladdr
= 0, i
, j
;
630 bool dst_is_double
[2];
632 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
634 /* If we have to do relative addressing, we want to load the ARL
635 * reg directly for one of the regs, and preload the other reladdr
636 * sources into temps.
638 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
639 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
640 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
641 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
642 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
643 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
645 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
646 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
647 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
648 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
650 if (dst
.reladdr
|| dst
.reladdr2
) {
652 emit_arl(ir
, address_reg
, *dst
.reladdr
);
654 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
658 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
661 assert(num_reladdr
== 0);
664 inst
->info
= tgsi_get_opcode_info(op
);
673 /* default to float, for paths where this is not initialized
674 * (since 0==UINT which is likely wrong):
676 inst
->tex_type
= GLSL_TYPE_FLOAT
;
678 inst
->function
= NULL
;
680 /* Update indirect addressing status used by TGSI */
681 if (dst
.reladdr
|| dst
.reladdr2
) {
683 case PROGRAM_STATE_VAR
:
684 case PROGRAM_CONSTANT
:
685 case PROGRAM_UNIFORM
:
686 this->indirect_addr_consts
= true;
688 case PROGRAM_IMMEDIATE
:
689 assert(!"immediates should not have indirect addressing");
696 for (i
= 0; i
< 4; i
++) {
697 if(inst
->src
[i
].reladdr
) {
698 switch(inst
->src
[i
].file
) {
699 case PROGRAM_STATE_VAR
:
700 case PROGRAM_CONSTANT
:
701 case PROGRAM_UNIFORM
:
702 this->indirect_addr_consts
= true;
704 case PROGRAM_IMMEDIATE
:
705 assert(!"immediates should not have indirect addressing");
715 * This section contains the double processing.
716 * GLSL just represents doubles as single channel values,
717 * however most HW and TGSI represent doubles as pairs of register channels.
719 * so we have to fixup destination writemask/index and src swizzle/indexes.
720 * dest writemasks need to translate from single channel write mask
721 * to a dual-channel writemask, but also need to modify the index,
722 * if we are touching the Z,W fields in the pre-translated writemask.
724 * src channels have similiar index modifications along with swizzle
725 * changes to we pick the XY, ZW pairs from the correct index.
727 * GLSL [0].x -> TGSI [0].xy
728 * GLSL [0].y -> TGSI [0].zw
729 * GLSL [0].z -> TGSI [1].xy
730 * GLSL [0].w -> TGSI [1].zw
732 for (j
= 0; j
< 2; j
++) {
733 dst_is_double
[j
] = false;
734 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
735 dst_is_double
[j
] = true;
736 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
737 unsigned type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
738 if (type
== GLSL_TYPE_DOUBLE
)
739 dst_is_double
[j
] = true;
743 if (dst_is_double
[0] || dst_is_double
[1] ||
744 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
745 glsl_to_tgsi_instruction
*dinst
= NULL
;
746 int initial_src_swz
[4], initial_src_idx
[4];
747 int initial_dst_idx
[2], initial_dst_writemask
[2];
748 /* select the writemask for dst0 or dst1 */
749 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
751 /* copy out the writemask, index and swizzles for all src/dsts. */
752 for (j
= 0; j
< 2; j
++) {
753 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
754 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
757 for (j
= 0; j
< 4; j
++) {
758 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
759 initial_src_idx
[j
] = inst
->src
[j
].index
;
763 * scan all the components in the dst writemask
764 * generate an instruction for each of them if required.
769 int i
= u_bit_scan(&writemask
);
771 /* before emitting the instruction, see if we have to adjust store
773 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
774 addr
.file
== PROGRAM_UNDEFINED
) {
775 /* We have to advance the buffer address by 16 */
776 addr
= get_temp(glsl_type::uint_type
);
777 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
778 inst
->src
[0], st_src_reg_for_int(16));
782 /* first time use previous instruction */
786 /* create a new instructions for subsequent attempts */
787 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
792 this->instructions
.push_tail(dinst
);
794 /* modify the destination if we are splitting */
795 for (j
= 0; j
< 2; j
++) {
796 if (dst_is_double
[j
]) {
797 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
798 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
800 if (dinst
->op
== TGSI_OPCODE_STORE
) {
801 dinst
->src
[0] = addr
;
803 dinst
->dst
[j
].index
++;
807 /* if we aren't writing to a double, just get the bit of the initial writemask
809 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
813 /* modify the src registers */
814 for (j
= 0; j
< 4; j
++) {
815 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
817 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
818 dinst
->src
[j
].index
= initial_src_idx
[j
];
820 dinst
->src
[j
].double_reg2
= true;
821 dinst
->src
[j
].index
++;
825 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
827 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
830 /* some opcodes are special case in what they use as sources
831 - F2D is a float src0, DLDEXP is integer src1 */
832 if (op
== TGSI_OPCODE_F2D
||
833 op
== TGSI_OPCODE_DLDEXP
||
834 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
835 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
842 this->instructions
.push_tail(inst
);
849 glsl_to_tgsi_instruction
*
850 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
852 st_src_reg src0
, st_src_reg src1
,
853 st_src_reg src2
, st_src_reg src3
)
855 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
859 * Determines whether to use an integer, unsigned integer, or float opcode
860 * based on the operands and input opcode, then emits the result.
863 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
865 st_src_reg src0
, st_src_reg src1
)
867 int type
= GLSL_TYPE_FLOAT
;
869 if (op
== TGSI_OPCODE_MOV
)
872 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
873 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
874 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
875 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
877 if (is_resource_instruction(op
))
879 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
880 type
= GLSL_TYPE_DOUBLE
;
881 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
882 type
= GLSL_TYPE_FLOAT
;
883 else if (native_integers
)
884 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
886 #define case5(c, f, i, u, d) \
887 case TGSI_OPCODE_##c: \
888 if (type == GLSL_TYPE_DOUBLE) \
889 op = TGSI_OPCODE_##d; \
890 else if (type == GLSL_TYPE_INT) \
891 op = TGSI_OPCODE_##i; \
892 else if (type == GLSL_TYPE_UINT) \
893 op = TGSI_OPCODE_##u; \
895 op = TGSI_OPCODE_##f; \
898 #define case4(c, f, i, u) \
899 case TGSI_OPCODE_##c: \
900 if (type == GLSL_TYPE_INT) \
901 op = TGSI_OPCODE_##i; \
902 else if (type == GLSL_TYPE_UINT) \
903 op = TGSI_OPCODE_##u; \
905 op = TGSI_OPCODE_##f; \
908 #define case3(f, i, u) case4(f, f, i, u)
909 #define case4d(f, i, u, d) case5(f, f, i, u, d)
910 #define case3fid(f, i, d) case5(f, f, i, i, d)
911 #define case2fi(f, i) case4(f, f, i, i)
912 #define case2iu(i, u) case4(i, LAST, i, u)
914 #define casecomp(c, f, i, u, d) \
915 case TGSI_OPCODE_##c: \
916 if (type == GLSL_TYPE_DOUBLE) \
917 op = TGSI_OPCODE_##d; \
918 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
919 op = TGSI_OPCODE_##i; \
920 else if (type == GLSL_TYPE_UINT) \
921 op = TGSI_OPCODE_##u; \
922 else if (native_integers) \
923 op = TGSI_OPCODE_##f; \
925 op = TGSI_OPCODE_##c; \
929 case3fid(ADD
, UADD
, DADD
);
930 case3fid(MUL
, UMUL
, DMUL
);
931 case3fid(MAD
, UMAD
, DMAD
);
932 case3fid(FMA
, UMAD
, DFMA
);
933 case3(DIV
, IDIV
, UDIV
);
934 case4d(MAX
, IMAX
, UMAX
, DMAX
);
935 case4d(MIN
, IMIN
, UMIN
, DMIN
);
938 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
939 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
940 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
941 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
945 case3fid(SSG
, ISSG
, DSSG
);
946 case3fid(ABS
, IABS
, DABS
);
950 case2iu(IMUL_HI
, UMUL_HI
);
952 case3fid(SQRT
, SQRT
, DSQRT
);
954 case3fid(RCP
, RCP
, DRCP
);
955 case3fid(RSQ
, RSQ
, DRSQ
);
957 case3fid(FRC
, FRC
, DFRAC
);
958 case3fid(TRUNC
, TRUNC
, DTRUNC
);
959 case3fid(CEIL
, CEIL
, DCEIL
);
960 case3fid(FLR
, FLR
, DFLR
);
961 case3fid(ROUND
, ROUND
, DROUND
);
963 case2iu(ATOMIMAX
, ATOMUMAX
);
964 case2iu(ATOMIMIN
, ATOMUMIN
);
969 assert(op
!= TGSI_OPCODE_LAST
);
973 glsl_to_tgsi_instruction
*
974 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
975 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
978 static const unsigned dot_opcodes
[] = {
979 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
982 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
986 * Emits TGSI scalar opcodes to produce unique answers across channels.
988 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
989 * channel determines the result across all channels. So to do a vec4
990 * of this operation, we want to emit a scalar per source channel used
991 * to produce dest channels.
994 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
996 st_src_reg orig_src0
, st_src_reg orig_src1
)
999 int done_mask
= ~dst
.writemask
;
1001 /* TGSI RCP is a scalar operation splatting results to all channels,
1002 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1005 for (i
= 0; i
< 4; i
++) {
1006 GLuint this_mask
= (1 << i
);
1007 st_src_reg src0
= orig_src0
;
1008 st_src_reg src1
= orig_src1
;
1010 if (done_mask
& this_mask
)
1013 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1014 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1015 for (j
= i
+ 1; j
< 4; j
++) {
1016 /* If there is another enabled component in the destination that is
1017 * derived from the same inputs, generate its value on this pass as
1020 if (!(done_mask
& (1 << j
)) &&
1021 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1022 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1023 this_mask
|= (1 << j
);
1026 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1027 src0_swiz
, src0_swiz
);
1028 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1029 src1_swiz
, src1_swiz
);
1031 dst
.writemask
= this_mask
;
1032 emit_asm(ir
, op
, dst
, src0
, src1
);
1033 done_mask
|= this_mask
;
1038 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1039 st_dst_reg dst
, st_src_reg src0
)
1041 st_src_reg undef
= undef_src
;
1043 undef
.swizzle
= SWIZZLE_XXXX
;
1045 emit_scalar(ir
, op
, dst
, src0
, undef
);
1049 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1050 st_dst_reg dst
, st_src_reg src0
)
1052 int op
= TGSI_OPCODE_ARL
;
1054 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1055 op
= TGSI_OPCODE_UARL
;
1057 assert(dst
.file
== PROGRAM_ADDRESS
);
1058 if (dst
.index
>= this->num_address_regs
)
1059 this->num_address_regs
= dst
.index
+ 1;
1061 emit_asm(NULL
, op
, dst
, src0
);
1065 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1066 gl_constant_value values
[8], int size
, int datatype
,
1067 GLuint
*swizzle_out
)
1069 if (file
== PROGRAM_CONSTANT
) {
1070 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1071 size
, datatype
, swizzle_out
);
1074 assert(file
== PROGRAM_IMMEDIATE
);
1077 immediate_storage
*entry
;
1078 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1081 /* Search immediate storage to see if we already have an identical
1082 * immediate that we can use instead of adding a duplicate entry.
1084 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1085 immediate_storage
*tmp
= entry
;
1087 for (i
= 0; i
* 4 < size32
; i
++) {
1088 int slot_size
= MIN2(size32
- (i
* 4), 4);
1089 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1091 if (memcmp(tmp
->values
, &values
[i
* 4],
1092 slot_size
* sizeof(gl_constant_value
)))
1095 /* Everything matches, keep going until the full size is matched */
1096 tmp
= (immediate_storage
*)tmp
->next
;
1099 /* The full value matched */
1100 if (i
* 4 >= size32
)
1106 for (i
= 0; i
* 4 < size32
; i
++) {
1107 int slot_size
= MIN2(size32
- (i
* 4), 4);
1108 /* Add this immediate to the list. */
1109 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1110 this->immediates
.push_tail(entry
);
1111 this->num_immediates
++;
1117 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1119 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1120 union gl_constant_value uval
;
1123 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1129 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1131 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1132 union gl_constant_value uval
[2];
1134 uval
[0].u
= *(uint32_t *)&val
;
1135 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1136 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1142 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1144 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1145 union gl_constant_value uval
;
1147 assert(native_integers
);
1150 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1156 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1158 if (native_integers
)
1159 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1160 st_src_reg_for_int(val
);
1162 return st_src_reg_for_float(val
);
1166 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1171 switch (type
->base_type
) {
1172 case GLSL_TYPE_UINT
:
1174 case GLSL_TYPE_FLOAT
:
1175 case GLSL_TYPE_BOOL
:
1176 if (type
->is_matrix()) {
1177 return type
->matrix_columns
;
1179 /* Regardless of size of vector, it gets a vec4. This is bad
1180 * packing for things like floats, but otherwise arrays become a
1181 * mess. Hopefully a later pass over the code can pack scalars
1182 * down if appropriate.
1187 case GLSL_TYPE_DOUBLE
:
1188 if (type
->is_matrix()) {
1189 if (type
->vector_elements
<= 2 || is_vs_input
)
1190 return type
->matrix_columns
;
1192 return type
->matrix_columns
* 2;
1194 /* For doubles if we have a double or dvec2 they fit in one
1195 * vec4, else they need 2 vec4s.
1197 if (type
->vector_elements
<= 2 || is_vs_input
)
1203 case GLSL_TYPE_ARRAY
:
1204 assert(type
->length
> 0);
1205 return attrib_type_size(type
->fields
.array
, is_vs_input
) * type
->length
;
1206 case GLSL_TYPE_STRUCT
:
1208 for (i
= 0; i
< type
->length
; i
++) {
1209 size
+= attrib_type_size(type
->fields
.structure
[i
].type
, is_vs_input
);
1212 case GLSL_TYPE_SAMPLER
:
1213 case GLSL_TYPE_IMAGE
:
1214 case GLSL_TYPE_SUBROUTINE
:
1215 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1219 case GLSL_TYPE_ATOMIC_UINT
:
1220 case GLSL_TYPE_INTERFACE
:
1221 case GLSL_TYPE_VOID
:
1222 case GLSL_TYPE_ERROR
:
1223 case GLSL_TYPE_FUNCTION
:
1224 assert(!"Invalid type in type_size");
1231 type_size(const struct glsl_type
*type
)
1233 return attrib_type_size(type
, false);
1237 * If the given GLSL type is an array or matrix or a structure containing
1238 * an array/matrix member, return true. Else return false.
1240 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1241 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1242 * we have an array that might be indexed with a variable, we need to use
1243 * the later storage type.
1246 type_has_array_or_matrix(const glsl_type
*type
)
1248 if (type
->is_array() || type
->is_matrix())
1251 if (type
->is_record()) {
1252 for (unsigned i
= 0; i
< type
->length
; i
++) {
1253 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1264 * In the initial pass of codegen, we assign temporary numbers to
1265 * intermediate results. (not SSA -- variable assignments will reuse
1269 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1273 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1277 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1278 if (next_array
>= max_num_arrays
) {
1279 max_num_arrays
+= 32;
1280 array_sizes
= (unsigned*)
1281 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1284 src
.file
= PROGRAM_ARRAY
;
1285 src
.index
= next_array
<< 16 | 0x8000;
1286 array_sizes
[next_array
] = type_size(type
);
1290 src
.file
= PROGRAM_TEMPORARY
;
1291 src
.index
= next_temp
;
1292 next_temp
+= type_size(type
);
1295 if (type
->is_array() || type
->is_record()) {
1296 src
.swizzle
= SWIZZLE_NOOP
;
1298 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1305 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1308 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1309 if (entry
->var
== var
)
1317 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1319 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1320 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1322 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1323 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1326 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1328 const ir_state_slot
*const slots
= ir
->get_state_slots();
1329 assert(slots
!= NULL
);
1331 /* Check if this statevar's setup in the STATE file exactly
1332 * matches how we'll want to reference it as a
1333 * struct/array/whatever. If not, then we need to move it into
1334 * temporary storage and hope that it'll get copy-propagated
1337 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1338 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1343 variable_storage
*storage
;
1345 if (i
== ir
->get_num_state_slots()) {
1346 /* We'll set the index later. */
1347 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1348 this->variables
.push_tail(storage
);
1352 /* The variable_storage constructor allocates slots based on the size
1353 * of the type. However, this had better match the number of state
1354 * elements that we're going to copy into the new temporary.
1356 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1358 dst
= st_dst_reg(get_temp(ir
->type
));
1360 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1362 this->variables
.push_tail(storage
);
1366 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1367 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1368 (gl_state_index
*)slots
[i
].tokens
);
1370 if (storage
->file
== PROGRAM_STATE_VAR
) {
1371 if (storage
->index
== -1) {
1372 storage
->index
= index
;
1374 assert(index
== storage
->index
+ (int)i
);
1377 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1378 * the data being moved since MOV does not care about the type of
1379 * data it is moving, and we don't want to declare registers with
1380 * array or struct types.
1382 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1383 src
.swizzle
= slots
[i
].swizzle
;
1384 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1385 /* even a float takes up a whole vec4 reg in a struct/array. */
1390 if (storage
->file
== PROGRAM_TEMPORARY
&&
1391 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1392 fail_link(this->shader_program
,
1393 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1394 ir
->name
, dst
.index
- storage
->index
,
1395 type_size(ir
->type
));
1401 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1403 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1405 visit_exec_list(&ir
->body_instructions
, this);
1407 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1411 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1414 case ir_loop_jump::jump_break
:
1415 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1417 case ir_loop_jump::jump_continue
:
1418 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1425 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1432 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1434 /* Ignore function bodies other than main() -- we shouldn't see calls to
1435 * them since they should all be inlined before we get to glsl_to_tgsi.
1437 if (strcmp(ir
->name
, "main") == 0) {
1438 const ir_function_signature
*sig
;
1441 sig
= ir
->matching_signature(NULL
, &empty
, false);
1445 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1452 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1454 int nonmul_operand
= 1 - mul_operand
;
1456 st_dst_reg result_dst
;
1458 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1459 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1462 expr
->operands
[0]->accept(this);
1464 expr
->operands
[1]->accept(this);
1466 ir
->operands
[nonmul_operand
]->accept(this);
1469 this->result
= get_temp(ir
->type
);
1470 result_dst
= st_dst_reg(this->result
);
1471 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1472 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1478 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1480 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1481 * implemented using multiplication, and logical-or is implemented using
1482 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1483 * As result, the logical expression (a & !b) can be rewritten as:
1487 * - (a * 1) - (a * b)
1491 * This final expression can be implemented as a single MAD(a, -b, a)
1495 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1497 const int other_operand
= 1 - try_operand
;
1500 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1501 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1504 ir
->operands
[other_operand
]->accept(this);
1506 expr
->operands
[0]->accept(this);
1509 b
.negate
= ~b
.negate
;
1511 this->result
= get_temp(ir
->type
);
1512 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1518 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1519 st_src_reg
*reg
, int *num_reladdr
)
1521 if (!reg
->reladdr
&& !reg
->reladdr2
)
1524 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1525 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1527 if (*num_reladdr
!= 1) {
1528 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1530 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1538 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1540 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1542 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1544 if (ir
->operation
== ir_binop_add
) {
1545 if (try_emit_mad(ir
, 1))
1547 if (try_emit_mad(ir
, 0))
1551 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1553 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1554 if (try_emit_mad_for_and_not(ir
, 1))
1556 if (try_emit_mad_for_and_not(ir
, 0))
1560 if (ir
->operation
== ir_quadop_vector
)
1561 assert(!"ir_quadop_vector should have been lowered");
1563 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1564 this->result
.file
= PROGRAM_UNDEFINED
;
1565 ir
->operands
[operand
]->accept(this);
1566 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1567 printf("Failed to get tree for expression operand:\n");
1568 ir
->operands
[operand
]->print();
1572 op
[operand
] = this->result
;
1574 /* Matrix expression operands should have been broken down to vector
1575 * operations already.
1577 assert(!ir
->operands
[operand
]->type
->is_matrix());
1580 visit_expression(ir
, op
);
1583 /* The non-recursive part of the expression visitor lives in a separate
1584 * function and should be prevented from being inlined, to avoid a stack
1585 * explosion when deeply nested expressions are visited.
1588 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1590 st_src_reg result_src
;
1591 st_dst_reg result_dst
;
1593 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1594 if (ir
->operands
[1]) {
1595 vector_elements
= MAX2(vector_elements
,
1596 ir
->operands
[1]->type
->vector_elements
);
1599 this->result
.file
= PROGRAM_UNDEFINED
;
1601 /* Storage for our result. Ideally for an assignment we'd be using
1602 * the actual storage for the result here, instead.
1604 result_src
= get_temp(ir
->type
);
1605 /* convenience for the emit functions below. */
1606 result_dst
= st_dst_reg(result_src
);
1607 /* Limit writes to the channels that will be used by result_src later.
1608 * This does limit this temp's use as a temporary for multi-instruction
1611 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1613 switch (ir
->operation
) {
1614 case ir_unop_logic_not
:
1615 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1616 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1618 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1619 * older GPUs implement SEQ using multiple instructions (i915 uses two
1620 * SGE instructions and a MUL instruction). Since our logic values are
1621 * 0.0 and 1.0, 1-x also implements !x.
1623 op
[0].negate
= ~op
[0].negate
;
1624 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1628 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1629 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1630 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1631 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1633 op
[0].negate
= ~op
[0].negate
;
1637 case ir_unop_subroutine_to_int
:
1638 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1641 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1644 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1647 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1651 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1655 assert(!"not reached: should be handled by ir_explog_to_explog2");
1658 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1661 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1664 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1666 case ir_unop_saturate
: {
1667 glsl_to_tgsi_instruction
*inst
;
1668 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1669 inst
->saturate
= true;
1674 case ir_unop_dFdx_coarse
:
1675 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1677 case ir_unop_dFdx_fine
:
1678 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1681 case ir_unop_dFdy_coarse
:
1682 case ir_unop_dFdy_fine
:
1684 /* The X component contains 1 or -1 depending on whether the framebuffer
1685 * is a FBO or the window system buffer, respectively.
1686 * It is then multiplied with the source operand of DDY.
1688 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1689 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1691 unsigned transform_y_index
=
1692 _mesa_add_state_reference(this->prog
->Parameters
,
1695 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1697 glsl_type::vec4_type
);
1698 transform_y
.swizzle
= SWIZZLE_XXXX
;
1700 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1702 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1703 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1704 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1708 case ir_unop_frexp_sig
:
1709 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1712 case ir_unop_frexp_exp
:
1713 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1716 case ir_unop_noise
: {
1717 /* At some point, a motivated person could add a better
1718 * implementation of noise. Currently not even the nvidia
1719 * binary drivers do anything more than this. In any case, the
1720 * place to do this is in the GL state tracker, not the poor
1723 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1728 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1731 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1735 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1738 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1739 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1741 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1744 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1745 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1747 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1751 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1753 case ir_binop_greater
:
1754 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1756 case ir_binop_lequal
:
1757 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1759 case ir_binop_gequal
:
1760 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1762 case ir_binop_equal
:
1763 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1765 case ir_binop_nequal
:
1766 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1768 case ir_binop_all_equal
:
1769 /* "==" operator producing a scalar boolean. */
1770 if (ir
->operands
[0]->type
->is_vector() ||
1771 ir
->operands
[1]->type
->is_vector()) {
1772 st_src_reg temp
= get_temp(native_integers
?
1773 glsl_type::uvec4_type
:
1774 glsl_type::vec4_type
);
1776 if (native_integers
) {
1777 st_dst_reg temp_dst
= st_dst_reg(temp
);
1778 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1780 if (ir
->operands
[0]->type
->is_boolean() &&
1781 ir
->operands
[1]->as_constant() &&
1782 ir
->operands
[1]->as_constant()->is_one()) {
1783 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1785 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1788 /* Emit 1-3 AND operations to combine the SEQ results. */
1789 switch (ir
->operands
[0]->type
->vector_elements
) {
1793 temp_dst
.writemask
= WRITEMASK_Y
;
1794 temp1
.swizzle
= SWIZZLE_YYYY
;
1795 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1796 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1799 temp_dst
.writemask
= WRITEMASK_X
;
1800 temp1
.swizzle
= SWIZZLE_XXXX
;
1801 temp2
.swizzle
= SWIZZLE_YYYY
;
1802 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1803 temp_dst
.writemask
= WRITEMASK_Y
;
1804 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1805 temp2
.swizzle
= SWIZZLE_WWWW
;
1806 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1809 temp1
.swizzle
= SWIZZLE_XXXX
;
1810 temp2
.swizzle
= SWIZZLE_YYYY
;
1811 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1813 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1815 /* After the dot-product, the value will be an integer on the
1816 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1818 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1820 /* Negating the result of the dot-product gives values on the range
1821 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1822 * This is achieved using SGE.
1824 st_src_reg sge_src
= result_src
;
1825 sge_src
.negate
= ~sge_src
.negate
;
1826 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1829 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1832 case ir_binop_any_nequal
:
1833 /* "!=" operator producing a scalar boolean. */
1834 if (ir
->operands
[0]->type
->is_vector() ||
1835 ir
->operands
[1]->type
->is_vector()) {
1836 st_src_reg temp
= get_temp(native_integers
?
1837 glsl_type::uvec4_type
:
1838 glsl_type::vec4_type
);
1839 if (ir
->operands
[0]->type
->is_boolean() &&
1840 ir
->operands
[1]->as_constant() &&
1841 ir
->operands
[1]->as_constant()->is_zero()) {
1842 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1844 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1847 if (native_integers
) {
1848 st_dst_reg temp_dst
= st_dst_reg(temp
);
1849 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1851 /* Emit 1-3 OR operations to combine the SNE results. */
1852 switch (ir
->operands
[0]->type
->vector_elements
) {
1856 temp_dst
.writemask
= WRITEMASK_Y
;
1857 temp1
.swizzle
= SWIZZLE_YYYY
;
1858 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1859 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1862 temp_dst
.writemask
= WRITEMASK_X
;
1863 temp1
.swizzle
= SWIZZLE_XXXX
;
1864 temp2
.swizzle
= SWIZZLE_YYYY
;
1865 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1866 temp_dst
.writemask
= WRITEMASK_Y
;
1867 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1868 temp2
.swizzle
= SWIZZLE_WWWW
;
1869 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1872 temp1
.swizzle
= SWIZZLE_XXXX
;
1873 temp2
.swizzle
= SWIZZLE_YYYY
;
1874 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1876 /* After the dot-product, the value will be an integer on the
1877 * range [0,4]. Zero stays zero, and positive values become 1.0.
1879 glsl_to_tgsi_instruction
*const dp
=
1880 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1881 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1882 /* The clamping to [0,1] can be done for free in the fragment
1883 * shader with a saturate.
1885 dp
->saturate
= true;
1887 /* Negating the result of the dot-product gives values on the range
1888 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1889 * achieved using SLT.
1891 st_src_reg slt_src
= result_src
;
1892 slt_src
.negate
= ~slt_src
.negate
;
1893 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1897 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1901 case ir_binop_logic_xor
:
1902 if (native_integers
)
1903 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1908 case ir_binop_logic_or
: {
1909 if (native_integers
) {
1910 /* If integers are used as booleans, we can use an actual "or"
1913 assert(native_integers
);
1914 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1916 /* After the addition, the value will be an integer on the
1917 * range [0,2]. Zero stays zero, and positive values become 1.0.
1919 glsl_to_tgsi_instruction
*add
=
1920 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1921 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1922 /* The clamping to [0,1] can be done for free in the fragment
1923 * shader with a saturate if floats are being used as boolean values.
1925 add
->saturate
= true;
1927 /* Negating the result of the addition gives values on the range
1928 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1929 * is achieved using SLT.
1931 st_src_reg slt_src
= result_src
;
1932 slt_src
.negate
= ~slt_src
.negate
;
1933 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1939 case ir_binop_logic_and
:
1940 /* If native integers are disabled, the bool args are stored as float 0.0
1941 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1942 * actual AND opcode.
1944 if (native_integers
)
1945 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1947 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1951 assert(ir
->operands
[0]->type
->is_vector());
1952 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1953 emit_dp(ir
, result_dst
, op
[0], op
[1],
1954 ir
->operands
[0]->type
->vector_elements
);
1959 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1961 /* sqrt(x) = x * rsq(x). */
1962 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1963 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1964 /* For incoming channels <= 0, set the result to 0. */
1965 op
[0].negate
= ~op
[0].negate
;
1966 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1967 op
[0], result_src
, st_src_reg_for_float(0.0));
1971 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1974 if (native_integers
) {
1975 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1978 /* fallthrough to next case otherwise */
1980 if (native_integers
) {
1981 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1984 /* fallthrough to next case otherwise */
1987 /* Converting between signed and unsigned integers is a no-op. */
1989 result_src
.type
= result_dst
.type
;
1992 if (native_integers
) {
1993 /* Booleans are stored as integers using ~0 for true and 0 for false.
1994 * GLSL requires that int(bool) return 1 for true and 0 for false.
1995 * This conversion is done with AND, but it could be done with NEG.
1997 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1999 /* Booleans and integers are both stored as floats when native
2000 * integers are disabled.
2006 if (native_integers
)
2007 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2009 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2012 if (native_integers
)
2013 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2015 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2017 case ir_unop_bitcast_f2i
:
2019 result_src
.type
= GLSL_TYPE_INT
;
2021 case ir_unop_bitcast_f2u
:
2023 result_src
.type
= GLSL_TYPE_UINT
;
2025 case ir_unop_bitcast_i2f
:
2026 case ir_unop_bitcast_u2f
:
2028 result_src
.type
= GLSL_TYPE_FLOAT
;
2031 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2034 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2037 if (native_integers
)
2038 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2040 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2043 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2046 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2049 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2051 case ir_unop_round_even
:
2052 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2055 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2059 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2062 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2065 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2068 case ir_unop_bit_not
:
2069 if (native_integers
) {
2070 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2074 if (native_integers
) {
2075 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2078 case ir_binop_lshift
:
2079 if (native_integers
) {
2080 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2083 case ir_binop_rshift
:
2084 if (native_integers
) {
2085 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2088 case ir_binop_bit_and
:
2089 if (native_integers
) {
2090 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2093 case ir_binop_bit_xor
:
2094 if (native_integers
) {
2095 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2098 case ir_binop_bit_or
:
2099 if (native_integers
) {
2100 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2104 assert(!"GLSL 1.30 features unsupported");
2107 case ir_binop_ubo_load
: {
2108 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2109 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2110 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2111 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2112 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2115 cbuf
.type
= ir
->type
->base_type
;
2116 cbuf
.file
= PROGRAM_CONSTANT
;
2118 cbuf
.reladdr
= NULL
;
2121 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2123 if (const_offset_ir
) {
2124 /* Constant index into constant buffer */
2125 cbuf
.reladdr
= NULL
;
2126 cbuf
.index
= const_offset
/ 16;
2129 /* Relative/variable index into constant buffer */
2130 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2131 st_src_reg_for_int(4));
2132 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2133 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2136 if (const_uniform_block
) {
2137 /* Constant constant buffer */
2138 cbuf
.reladdr2
= NULL
;
2139 cbuf
.index2D
= const_block
;
2140 cbuf
.has_index2
= true;
2143 /* Relative/variable constant buffer */
2144 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2146 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2147 cbuf
.has_index2
= true;
2150 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2151 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2152 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2153 const_offset
% 16 / 8,
2154 const_offset
% 16 / 8,
2155 const_offset
% 16 / 8);
2157 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2158 const_offset
% 16 / 4,
2159 const_offset
% 16 / 4,
2160 const_offset
% 16 / 4);
2162 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2163 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2165 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2170 /* note: we have to reorder the three args here */
2171 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2174 if (this->ctx
->Const
.NativeIntegers
)
2175 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2177 op
[0].negate
= ~op
[0].negate
;
2178 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2181 case ir_triop_bitfield_extract
:
2182 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2184 case ir_quadop_bitfield_insert
:
2185 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2187 case ir_unop_bitfield_reverse
:
2188 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2190 case ir_unop_bit_count
:
2191 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2193 case ir_unop_find_msb
:
2194 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2196 case ir_unop_find_lsb
:
2197 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2199 case ir_binop_imul_high
:
2200 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2203 /* In theory, MAD is incorrect here. */
2205 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2207 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2209 case ir_unop_interpolate_at_centroid
:
2210 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2212 case ir_binop_interpolate_at_offset
:
2213 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2215 case ir_binop_interpolate_at_sample
:
2216 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2220 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2223 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2226 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2229 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2232 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2235 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2237 case ir_unop_unpack_double_2x32
:
2238 case ir_unop_pack_double_2x32
:
2239 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2242 case ir_binop_ldexp
:
2243 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2244 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2246 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2250 case ir_unop_pack_half_2x16
:
2251 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2253 case ir_unop_unpack_half_2x16
:
2254 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2257 case ir_unop_get_buffer_size
: {
2258 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2261 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2262 (const_offset
? const_offset
->value
.u
[0] : 0),
2264 if (!const_offset
) {
2265 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2266 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
2267 emit_arl(ir
, sampler_reladdr
, op
[0]);
2269 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2273 case ir_unop_pack_snorm_2x16
:
2274 case ir_unop_pack_unorm_2x16
:
2275 case ir_unop_pack_snorm_4x8
:
2276 case ir_unop_pack_unorm_4x8
:
2278 case ir_unop_unpack_snorm_2x16
:
2279 case ir_unop_unpack_unorm_2x16
:
2280 case ir_unop_unpack_snorm_4x8
:
2281 case ir_unop_unpack_unorm_4x8
:
2283 case ir_quadop_vector
:
2284 case ir_binop_vector_extract
:
2285 case ir_triop_vector_insert
:
2286 case ir_binop_carry
:
2287 case ir_binop_borrow
:
2288 case ir_unop_ssbo_unsized_array_length
:
2289 /* This operation is not supported, or should have already been handled.
2291 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2295 this->result
= result_src
;
2300 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2306 /* Note that this is only swizzles in expressions, not those on the left
2307 * hand side of an assignment, which do write masking. See ir_assignment
2311 ir
->val
->accept(this);
2313 assert(src
.file
!= PROGRAM_UNDEFINED
);
2314 assert(ir
->type
->vector_elements
> 0);
2316 for (i
= 0; i
< 4; i
++) {
2317 if (i
< ir
->type
->vector_elements
) {
2320 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2323 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2326 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2329 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2333 /* If the type is smaller than a vec4, replicate the last
2336 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2340 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2345 /* Test if the variable is an array. Note that geometry and
2346 * tessellation shader inputs are outputs are always arrays (except
2347 * for patch inputs), so only the array element type is considered.
2350 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2352 const glsl_type
*type
= var
->type
;
2354 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2355 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2360 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2361 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2362 stage
== MESA_SHADER_TESS_CTRL
) &&
2364 if (!var
->type
->is_array())
2365 return false; /* a system value probably */
2367 type
= var
->type
->fields
.array
;
2371 return type
->is_array() || type
->is_matrix();
2375 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2377 variable_storage
*entry
= find_variable_storage(ir
->var
);
2378 ir_variable
*var
= ir
->var
;
2382 switch (var
->data
.mode
) {
2383 case ir_var_uniform
:
2384 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2385 var
->data
.param_index
);
2386 this->variables
.push_tail(entry
);
2388 case ir_var_shader_in
:
2389 /* The linker assigns locations for varyings and attributes,
2390 * including deprecated builtins (like gl_Color), user-assign
2391 * generic attributes (glBindVertexLocation), and
2392 * user-defined varyings.
2394 assert(var
->data
.location
!= -1);
2396 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2397 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2399 decl
->mesa_index
= var
->data
.location
;
2400 decl
->array_id
= num_input_arrays
+ 1;
2402 decl
->array_size
= type_size(var
->type
->fields
.array
);
2403 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2405 decl
->array_size
= type_size(var
->type
);
2406 decl
->array_type
= var
->type
->without_array()->base_type
;
2410 entry
= new(mem_ctx
) variable_storage(var
,
2416 entry
= new(mem_ctx
) variable_storage(var
,
2418 var
->data
.location
);
2420 this->variables
.push_tail(entry
);
2422 case ir_var_shader_out
:
2423 assert(var
->data
.location
!= -1);
2425 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2426 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2428 decl
->mesa_index
= var
->data
.location
;
2429 decl
->array_id
= num_output_arrays
+ 1;
2431 decl
->array_size
= type_size(var
->type
->fields
.array
);
2432 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2434 decl
->array_size
= type_size(var
->type
);
2435 decl
->array_type
= var
->type
->without_array()->base_type
;
2437 num_output_arrays
++;
2439 entry
= new(mem_ctx
) variable_storage(var
,
2445 entry
= new(mem_ctx
) variable_storage(var
,
2450 this->variables
.push_tail(entry
);
2452 case ir_var_system_value
:
2453 entry
= new(mem_ctx
) variable_storage(var
,
2454 PROGRAM_SYSTEM_VALUE
,
2455 var
->data
.location
);
2458 case ir_var_temporary
:
2459 st_src_reg src
= get_temp(var
->type
);
2461 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2462 this->variables
.push_tail(entry
);
2468 printf("Failed to make storage for %s\n", var
->name
);
2473 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2474 this->result
.array_id
= entry
->array_id
;
2475 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2476 this->result
.is_double_vertex_input
= true;
2477 if (!native_integers
)
2478 this->result
.type
= GLSL_TYPE_FLOAT
;
2482 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2483 GLbitfield64 usage_mask
,
2484 GLbitfield64 double_usage_mask
,
2485 GLbitfield patch_usage_mask
)
2489 /* Fix array declarations by removing unused array elements at both ends
2490 * of the arrays. For example, mat4[3] where only mat[1] is used.
2492 for (i
= 0; i
< count
; i
++) {
2493 struct array_decl
*decl
= &arrays
[i
];
2495 /* Shrink the beginning. */
2496 for (j
= 0; j
< decl
->array_size
; j
++) {
2497 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2498 if (patch_usage_mask
&
2499 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2503 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2505 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2514 /* Shrink the end. */
2515 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2516 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2517 if (patch_usage_mask
&
2518 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2522 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2524 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2534 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2538 int element_size
= type_size(ir
->type
);
2541 index
= ir
->array_index
->constant_expression_value();
2543 ir
->array
->accept(this);
2546 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2547 switch (this->prog
->Target
) {
2548 case GL_TESS_CONTROL_PROGRAM_NV
:
2549 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2550 !ir
->variable_referenced()->data
.patch
;
2552 case GL_TESS_EVALUATION_PROGRAM_NV
:
2553 is_2D
= src
.file
== PROGRAM_INPUT
&&
2554 !ir
->variable_referenced()->data
.patch
;
2556 case GL_GEOMETRY_PROGRAM_NV
:
2557 is_2D
= src
.file
== PROGRAM_INPUT
;
2567 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2568 src
.file
== PROGRAM_INPUT
)
2569 element_size
= attrib_type_size(ir
->type
, true);
2571 src
.index2D
= index
->value
.i
[0];
2572 src
.has_index2
= true;
2574 src
.index
+= index
->value
.i
[0] * element_size
;
2576 /* Variable index array dereference. It eats the "vec4" of the
2577 * base of the array and an index that offsets the TGSI register
2580 ir
->array_index
->accept(this);
2582 st_src_reg index_reg
;
2584 if (element_size
== 1) {
2585 index_reg
= this->result
;
2587 index_reg
= get_temp(native_integers
?
2588 glsl_type::int_type
: glsl_type::float_type
);
2590 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2591 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2594 /* If there was already a relative address register involved, add the
2595 * new and the old together to get the new offset.
2597 if (!is_2D
&& src
.reladdr
!= NULL
) {
2598 st_src_reg accum_reg
= get_temp(native_integers
?
2599 glsl_type::int_type
: glsl_type::float_type
);
2601 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2602 index_reg
, *src
.reladdr
);
2604 index_reg
= accum_reg
;
2608 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2609 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2611 src
.has_index2
= true;
2613 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2614 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2618 /* If the type is smaller than a vec4, replicate the last channel out. */
2619 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2620 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2622 src
.swizzle
= SWIZZLE_NOOP
;
2624 /* Change the register type to the element type of the array. */
2625 src
.type
= ir
->type
->base_type
;
2631 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2634 const glsl_type
*struct_type
= ir
->record
->type
;
2637 ir
->record
->accept(this);
2639 for (i
= 0; i
< struct_type
->length
; i
++) {
2640 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2642 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2645 /* If the type is smaller than a vec4, replicate the last channel out. */
2646 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2647 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2649 this->result
.swizzle
= SWIZZLE_NOOP
;
2651 this->result
.index
+= offset
;
2652 this->result
.type
= ir
->type
->base_type
;
2656 * We want to be careful in assignment setup to hit the actual storage
2657 * instead of potentially using a temporary like we might with the
2658 * ir_dereference handler.
2661 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2663 /* The LHS must be a dereference. If the LHS is a variable indexed array
2664 * access of a vector, it must be separated into a series conditional moves
2665 * before reaching this point (see ir_vec_index_to_cond_assign).
2667 assert(ir
->as_dereference());
2668 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2670 assert(!deref_array
->array
->type
->is_vector());
2673 /* Use the rvalue deref handler for the most part. We'll ignore
2674 * swizzles in it and write swizzles using writemask, though.
2677 return st_dst_reg(v
->result
);
2681 * Process the condition of a conditional assignment
2683 * Examines the condition of a conditional assignment to generate the optimal
2684 * first operand of a \c CMP instruction. If the condition is a relational
2685 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2686 * used as the source for the \c CMP instruction. Otherwise the comparison
2687 * is processed to a boolean result, and the boolean result is used as the
2688 * operand to the CMP instruction.
2691 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2693 ir_rvalue
*src_ir
= ir
;
2695 bool switch_order
= false;
2697 ir_expression
*const expr
= ir
->as_expression();
2699 if (native_integers
) {
2700 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2701 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2702 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2703 type
== GLSL_TYPE_BOOL
) {
2704 if (expr
->operation
== ir_binop_equal
) {
2705 if (expr
->operands
[0]->is_zero()) {
2706 src_ir
= expr
->operands
[1];
2707 switch_order
= true;
2709 else if (expr
->operands
[1]->is_zero()) {
2710 src_ir
= expr
->operands
[0];
2711 switch_order
= true;
2714 else if (expr
->operation
== ir_binop_nequal
) {
2715 if (expr
->operands
[0]->is_zero()) {
2716 src_ir
= expr
->operands
[1];
2718 else if (expr
->operands
[1]->is_zero()) {
2719 src_ir
= expr
->operands
[0];
2725 src_ir
->accept(this);
2726 return switch_order
;
2729 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2730 bool zero_on_left
= false;
2732 if (expr
->operands
[0]->is_zero()) {
2733 src_ir
= expr
->operands
[1];
2734 zero_on_left
= true;
2735 } else if (expr
->operands
[1]->is_zero()) {
2736 src_ir
= expr
->operands
[0];
2737 zero_on_left
= false;
2741 * (a < 0) T F F ( a < 0) T F F
2742 * (0 < a) F F T (-a < 0) F F T
2743 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2744 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2745 * (a > 0) F F T (-a < 0) F F T
2746 * (0 > a) T F F ( a < 0) T F F
2747 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2748 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2750 * Note that exchanging the order of 0 and 'a' in the comparison simply
2751 * means that the value of 'a' should be negated.
2754 switch (expr
->operation
) {
2756 switch_order
= false;
2757 negate
= zero_on_left
;
2760 case ir_binop_greater
:
2761 switch_order
= false;
2762 negate
= !zero_on_left
;
2765 case ir_binop_lequal
:
2766 switch_order
= true;
2767 negate
= !zero_on_left
;
2770 case ir_binop_gequal
:
2771 switch_order
= true;
2772 negate
= zero_on_left
;
2776 /* This isn't the right kind of comparison afterall, so make sure
2777 * the whole condition is visited.
2785 src_ir
->accept(this);
2787 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2788 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2789 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2790 * computing the condition.
2793 this->result
.negate
= ~this->result
.negate
;
2795 return switch_order
;
2799 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2800 st_dst_reg
*l
, st_src_reg
*r
,
2801 st_src_reg
*cond
, bool cond_swap
)
2803 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2804 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2805 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2811 if (type
->is_array()) {
2812 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2813 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2818 if (type
->is_matrix()) {
2819 const struct glsl_type
*vec_type
;
2821 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2822 type
->vector_elements
, 1);
2824 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2825 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2830 assert(type
->is_scalar() || type
->is_vector());
2832 r
->type
= type
->base_type
;
2834 st_src_reg l_src
= st_src_reg(*l
);
2835 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2837 if (native_integers
) {
2838 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2839 cond_swap
? l_src
: *r
,
2840 cond_swap
? *r
: l_src
);
2842 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2843 cond_swap
? l_src
: *r
,
2844 cond_swap
? *r
: l_src
);
2847 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2851 if (type
->is_dual_slot_double()) {
2853 if (r
->is_double_vertex_input
== false)
2859 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2864 ir
->rhs
->accept(this);
2867 l
= get_assignment_lhs(ir
->lhs
, this);
2869 /* FINISHME: This should really set to the correct maximal writemask for each
2870 * FINISHME: component written (in the loops below). This case can only
2871 * FINISHME: occur for matrices, arrays, and structures.
2873 if (ir
->write_mask
== 0) {
2874 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2876 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2877 if (ir
->lhs
->type
->without_array()->is_double()) {
2878 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2880 l
.writemask
= WRITEMASK_X
;
2883 l
.writemask
= WRITEMASK_XY
;
2886 l
.writemask
= WRITEMASK_XYZ
;
2889 l
.writemask
= WRITEMASK_XYZW
;
2893 l
.writemask
= WRITEMASK_XYZW
;
2895 } else if (ir
->lhs
->type
->is_scalar() &&
2896 !ir
->lhs
->type
->is_double() &&
2897 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2898 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2899 * FINISHME: W component of fragment shader output zero, work correctly.
2901 l
.writemask
= WRITEMASK_XYZW
;
2904 int first_enabled_chan
= 0;
2907 l
.writemask
= ir
->write_mask
;
2909 for (int i
= 0; i
< 4; i
++) {
2910 if (l
.writemask
& (1 << i
)) {
2911 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2916 /* Swizzle a small RHS vector into the channels being written.
2918 * glsl ir treats write_mask as dictating how many channels are
2919 * present on the RHS while TGSI treats write_mask as just
2920 * showing which channels of the vec4 RHS get written.
2922 for (int i
= 0; i
< 4; i
++) {
2923 if (l
.writemask
& (1 << i
))
2924 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2926 swizzles
[i
] = first_enabled_chan
;
2928 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2929 swizzles
[2], swizzles
[3]);
2932 assert(l
.file
!= PROGRAM_UNDEFINED
);
2933 assert(r
.file
!= PROGRAM_UNDEFINED
);
2935 if (ir
->condition
) {
2936 const bool switch_order
= this->process_move_condition(ir
->condition
);
2937 st_src_reg condition
= this->result
;
2939 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2940 } else if (ir
->rhs
->as_expression() &&
2941 this->instructions
.get_tail() &&
2942 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2943 type_size(ir
->lhs
->type
) == 1 &&
2944 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2945 /* To avoid emitting an extra MOV when assigning an expression to a
2946 * variable, emit the last instruction of the expression again, but
2947 * replace the destination register with the target of the assignment.
2948 * Dead code elimination will remove the original instruction.
2950 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2951 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2952 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2953 new_inst
->saturate
= inst
->saturate
;
2954 inst
->dead_mask
= inst
->dst
[0].writemask
;
2956 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2962 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2965 GLdouble stack_vals
[4] = { 0 };
2966 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2967 GLenum gl_type
= GL_NONE
;
2969 static int in_array
= 0;
2970 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2972 /* Unfortunately, 4 floats is all we can get into
2973 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2974 * aggregate constant and move each constant value into it. If we
2975 * get lucky, copy propagation will eliminate the extra moves.
2977 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2978 st_src_reg temp_base
= get_temp(ir
->type
);
2979 st_dst_reg temp
= st_dst_reg(temp_base
);
2981 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2982 int size
= type_size(field_value
->type
);
2986 field_value
->accept(this);
2989 for (i
= 0; i
< (unsigned int)size
; i
++) {
2990 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2996 this->result
= temp_base
;
3000 if (ir
->type
->is_array()) {
3001 st_src_reg temp_base
= get_temp(ir
->type
);
3002 st_dst_reg temp
= st_dst_reg(temp_base
);
3003 int size
= type_size(ir
->type
->fields
.array
);
3008 for (i
= 0; i
< ir
->type
->length
; i
++) {
3009 ir
->array_elements
[i
]->accept(this);
3011 for (int j
= 0; j
< size
; j
++) {
3012 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3018 this->result
= temp_base
;
3023 if (ir
->type
->is_matrix()) {
3024 st_src_reg mat
= get_temp(ir
->type
);
3025 st_dst_reg mat_column
= st_dst_reg(mat
);
3027 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3028 switch (ir
->type
->base_type
) {
3029 case GLSL_TYPE_FLOAT
:
3030 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3032 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3033 src
.index
= add_constant(file
,
3035 ir
->type
->vector_elements
,
3038 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3040 case GLSL_TYPE_DOUBLE
:
3041 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3042 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3043 src
.index
= add_constant(file
,
3045 ir
->type
->vector_elements
,
3048 if (ir
->type
->vector_elements
>= 2) {
3049 mat_column
.writemask
= WRITEMASK_XY
;
3050 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3051 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3053 mat_column
.writemask
= WRITEMASK_X
;
3054 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3055 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3058 if (ir
->type
->vector_elements
> 2) {
3059 if (ir
->type
->vector_elements
== 4) {
3060 mat_column
.writemask
= WRITEMASK_ZW
;
3061 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3062 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3064 mat_column
.writemask
= WRITEMASK_Z
;
3065 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3066 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3067 mat_column
.writemask
= WRITEMASK_XYZW
;
3068 src
.swizzle
= SWIZZLE_XYZW
;
3074 unreachable("Illegal matrix constant type.\n");
3083 switch (ir
->type
->base_type
) {
3084 case GLSL_TYPE_FLOAT
:
3086 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3087 values
[i
].f
= ir
->value
.f
[i
];
3090 case GLSL_TYPE_DOUBLE
:
3091 gl_type
= GL_DOUBLE
;
3092 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3093 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3094 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3097 case GLSL_TYPE_UINT
:
3098 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3099 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3100 if (native_integers
)
3101 values
[i
].u
= ir
->value
.u
[i
];
3103 values
[i
].f
= ir
->value
.u
[i
];
3107 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3108 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3109 if (native_integers
)
3110 values
[i
].i
= ir
->value
.i
[i
];
3112 values
[i
].f
= ir
->value
.i
[i
];
3115 case GLSL_TYPE_BOOL
:
3116 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3117 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3118 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3122 assert(!"Non-float/uint/int/bool constant");
3125 this->result
= st_src_reg(file
, -1, ir
->type
);
3126 this->result
.index
= add_constant(file
,
3128 ir
->type
->vector_elements
,
3130 &this->result
.swizzle
);
3134 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3136 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3137 if (entry
->sig
== sig
)
3141 entry
= ralloc(mem_ctx
, function_entry
);
3143 entry
->sig_id
= this->next_signature_id
++;
3144 entry
->bgn_inst
= NULL
;
3146 /* Allocate storage for all the parameters. */
3147 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3148 variable_storage
*storage
;
3150 storage
= find_variable_storage(param
);
3153 st_src_reg src
= get_temp(param
->type
);
3155 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3156 this->variables
.push_tail(storage
);
3159 if (!sig
->return_type
->is_void()) {
3160 entry
->return_reg
= get_temp(sig
->return_type
);
3162 entry
->return_reg
= undef_src
;
3165 this->function_signatures
.push_tail(entry
);
3170 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3172 const char *callee
= ir
->callee
->function_name();
3173 exec_node
*param
= ir
->actual_parameters
.get_head();
3174 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3175 ir_variable
*location
= deref
->variable_referenced();
3178 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3180 /* Calculate the surface offset */
3182 unsigned array_size
= 0, base
= 0, index
= 0;
3184 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
);
3186 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3187 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3188 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3189 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3190 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3192 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3195 ir
->return_deref
->accept(this);
3196 st_dst_reg
dst(this->result
);
3197 dst
.writemask
= WRITEMASK_X
;
3199 glsl_to_tgsi_instruction
*inst
;
3201 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3202 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3203 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3204 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3205 st_src_reg_for_int(1));
3206 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3207 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3208 st_src_reg_for_int(-1));
3209 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3211 param
= param
->get_next();
3212 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3215 st_src_reg data
= this->result
, data2
= undef_src
;
3217 if (!strcmp("__intrinsic_atomic_add", callee
))
3218 opcode
= TGSI_OPCODE_ATOMUADD
;
3219 else if (!strcmp("__intrinsic_atomic_min", callee
))
3220 opcode
= TGSI_OPCODE_ATOMIMIN
;
3221 else if (!strcmp("__intrinsic_atomic_max", callee
))
3222 opcode
= TGSI_OPCODE_ATOMIMAX
;
3223 else if (!strcmp("__intrinsic_atomic_and", callee
))
3224 opcode
= TGSI_OPCODE_ATOMAND
;
3225 else if (!strcmp("__intrinsic_atomic_or", callee
))
3226 opcode
= TGSI_OPCODE_ATOMOR
;
3227 else if (!strcmp("__intrinsic_atomic_xor", callee
))
3228 opcode
= TGSI_OPCODE_ATOMXOR
;
3229 else if (!strcmp("__intrinsic_atomic_exchange", callee
))
3230 opcode
= TGSI_OPCODE_ATOMXCHG
;
3231 else if (!strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3232 opcode
= TGSI_OPCODE_ATOMCAS
;
3233 param
= param
->get_next();
3234 val
= ((ir_instruction
*)param
)->as_rvalue();
3236 data2
= this->result
;
3237 } else if (!strcmp("__intrinsic_atomic_sub", callee
)) {
3238 opcode
= TGSI_OPCODE_ATOMUADD
;
3239 st_src_reg res
= get_temp(glsl_type::uvec4_type
);
3240 st_dst_reg dstres
= st_dst_reg(res
);
3241 dstres
.writemask
= dst
.writemask
;
3242 emit_asm(ir
, TGSI_OPCODE_INEG
, dstres
, data
);
3245 assert(!"Unexpected intrinsic");
3249 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3252 inst
->buffer
= buffer
;
3256 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3258 const char *callee
= ir
->callee
->function_name();
3259 exec_node
*param
= ir
->actual_parameters
.get_head();
3261 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3263 param
= param
->get_next();
3264 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3266 ir_constant
*const_block
= block
->as_constant();
3270 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3271 (const_block
? const_block
->value
.u
[0] : 0),
3275 block
->accept(this);
3276 emit_arl(ir
, sampler_reladdr
, this->result
);
3277 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3278 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3281 /* Calculate the surface offset */
3282 offset
->accept(this);
3283 st_src_reg off
= this->result
;
3285 st_dst_reg dst
= undef_dst
;
3286 if (ir
->return_deref
) {
3287 ir
->return_deref
->accept(this);
3288 dst
= st_dst_reg(this->result
);
3289 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3292 glsl_to_tgsi_instruction
*inst
;
3294 if (!strcmp("__intrinsic_load_ssbo", callee
)) {
3295 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3296 if (dst
.type
== GLSL_TYPE_BOOL
)
3297 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3298 } else if (!strcmp("__intrinsic_store_ssbo", callee
)) {
3299 param
= param
->get_next();
3300 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3303 param
= param
->get_next();
3304 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3306 dst
.writemask
= write_mask
->value
.u
[0];
3308 dst
.type
= this->result
.type
;
3309 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3311 param
= param
->get_next();
3312 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3315 st_src_reg data
= this->result
, data2
= undef_src
;
3317 if (!strcmp("__intrinsic_atomic_add_ssbo", callee
))
3318 opcode
= TGSI_OPCODE_ATOMUADD
;
3319 else if (!strcmp("__intrinsic_atomic_min_ssbo", callee
))
3320 opcode
= TGSI_OPCODE_ATOMIMIN
;
3321 else if (!strcmp("__intrinsic_atomic_max_ssbo", callee
))
3322 opcode
= TGSI_OPCODE_ATOMIMAX
;
3323 else if (!strcmp("__intrinsic_atomic_and_ssbo", callee
))
3324 opcode
= TGSI_OPCODE_ATOMAND
;
3325 else if (!strcmp("__intrinsic_atomic_or_ssbo", callee
))
3326 opcode
= TGSI_OPCODE_ATOMOR
;
3327 else if (!strcmp("__intrinsic_atomic_xor_ssbo", callee
))
3328 opcode
= TGSI_OPCODE_ATOMXOR
;
3329 else if (!strcmp("__intrinsic_atomic_exchange_ssbo", callee
))
3330 opcode
= TGSI_OPCODE_ATOMXCHG
;
3331 else if (!strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3332 opcode
= TGSI_OPCODE_ATOMCAS
;
3333 param
= param
->get_next();
3334 val
= ((ir_instruction
*)param
)->as_rvalue();
3336 data2
= this->result
;
3338 assert(!"Unexpected intrinsic");
3342 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3345 param
= param
->get_next();
3346 ir_constant
*access
= NULL
;
3347 if (!param
->is_tail_sentinel()) {
3348 access
= ((ir_instruction
*)param
)->as_constant();
3352 /* The emit_asm() might have actually split the op into pieces, e.g. for
3353 * double stores. We have to go back and fix up all the generated ops.
3355 unsigned op
= inst
->op
;
3357 inst
->buffer
= buffer
;
3359 inst
->buffer_access
= access
->value
.u
[0];
3360 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3361 if (inst
->op
== TGSI_OPCODE_UADD
)
3362 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3363 } while (inst
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
&& inst
->op
== op
);
3367 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3369 const char *callee
= ir
->callee
->function_name();
3371 if (!strcmp("__intrinsic_memory_barrier", callee
))
3372 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3373 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3374 TGSI_MEMBAR_ATOMIC_BUFFER
|
3375 TGSI_MEMBAR_SHADER_IMAGE
|
3376 TGSI_MEMBAR_SHARED
));
3377 else if (!strcmp("__intrinsic_memory_barrier_atomic_counter", callee
))
3378 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3379 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3380 else if (!strcmp("__intrinsic_memory_barrier_buffer", callee
))
3381 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3382 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3383 else if (!strcmp("__intrinsic_memory_barrier_image", callee
))
3384 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3385 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3386 else if (!strcmp("__intrinsic_memory_barrier_shared", callee
))
3387 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3388 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3389 else if (!strcmp("__intrinsic_group_memory_barrier", callee
))
3390 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3391 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3392 TGSI_MEMBAR_ATOMIC_BUFFER
|
3393 TGSI_MEMBAR_SHADER_IMAGE
|
3394 TGSI_MEMBAR_SHARED
|
3395 TGSI_MEMBAR_THREAD_GROUP
));
3397 assert(!"Unexpected memory barrier intrinsic");
3401 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3403 const char *callee
= ir
->callee
->function_name();
3404 exec_node
*param
= ir
->actual_parameters
.get_head();
3406 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3408 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3410 /* Calculate the surface offset */
3411 offset
->accept(this);
3412 st_src_reg off
= this->result
;
3414 st_dst_reg dst
= undef_dst
;
3415 if (ir
->return_deref
) {
3416 ir
->return_deref
->accept(this);
3417 dst
= st_dst_reg(this->result
);
3418 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3421 glsl_to_tgsi_instruction
*inst
;
3423 if (!strcmp("__intrinsic_load_shared", callee
)) {
3424 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3425 inst
->buffer
= buffer
;
3426 } else if (!strcmp("__intrinsic_store_shared", callee
)) {
3427 param
= param
->get_next();
3428 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3431 param
= param
->get_next();
3432 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3434 dst
.writemask
= write_mask
->value
.u
[0];
3436 dst
.type
= this->result
.type
;
3437 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3438 inst
->buffer
= buffer
;
3440 param
= param
->get_next();
3441 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3444 st_src_reg data
= this->result
, data2
= undef_src
;
3446 if (!strcmp("__intrinsic_atomic_add_shared", callee
))
3447 opcode
= TGSI_OPCODE_ATOMUADD
;
3448 else if (!strcmp("__intrinsic_atomic_min_shared", callee
))
3449 opcode
= TGSI_OPCODE_ATOMIMIN
;
3450 else if (!strcmp("__intrinsic_atomic_max_shared", callee
))
3451 opcode
= TGSI_OPCODE_ATOMIMAX
;
3452 else if (!strcmp("__intrinsic_atomic_and_shared", callee
))
3453 opcode
= TGSI_OPCODE_ATOMAND
;
3454 else if (!strcmp("__intrinsic_atomic_or_shared", callee
))
3455 opcode
= TGSI_OPCODE_ATOMOR
;
3456 else if (!strcmp("__intrinsic_atomic_xor_shared", callee
))
3457 opcode
= TGSI_OPCODE_ATOMXOR
;
3458 else if (!strcmp("__intrinsic_atomic_exchange_shared", callee
))
3459 opcode
= TGSI_OPCODE_ATOMXCHG
;
3460 else if (!strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3461 opcode
= TGSI_OPCODE_ATOMCAS
;
3462 param
= param
->get_next();
3463 val
= ((ir_instruction
*)param
)->as_rvalue();
3465 data2
= this->result
;
3467 assert(!"Unexpected intrinsic");
3471 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3472 inst
->buffer
= buffer
;
3477 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3479 const char *callee
= ir
->callee
->function_name();
3480 exec_node
*param
= ir
->actual_parameters
.get_head();
3482 ir_dereference
*img
= (ir_dereference
*)param
;
3483 const ir_variable
*imgvar
= img
->variable_referenced();
3484 const glsl_type
*type
= imgvar
->type
->without_array();
3485 unsigned sampler_array_size
= 1, sampler_base
= 0;
3488 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3490 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3491 (unsigned int *)&image
.index
, &reladdr
);
3492 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3493 emit_arl(ir
, sampler_reladdr
, reladdr
);
3494 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3495 memcpy(image
.reladdr
, &sampler_reladdr
, sizeof(reladdr
));
3498 st_dst_reg dst
= undef_dst
;
3499 if (ir
->return_deref
) {
3500 ir
->return_deref
->accept(this);
3501 dst
= st_dst_reg(this->result
);
3502 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3505 glsl_to_tgsi_instruction
*inst
;
3507 if (!strcmp("__intrinsic_image_size", callee
)) {
3508 dst
.writemask
= WRITEMASK_XYZ
;
3509 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3510 } else if (!strcmp("__intrinsic_image_samples", callee
)) {
3511 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3512 st_dst_reg dstres
= st_dst_reg(res
);
3513 dstres
.writemask
= WRITEMASK_W
;
3514 emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3515 res
.swizzle
= SWIZZLE_WWWW
;
3516 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3518 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3520 st_dst_reg coord_dst
;
3521 coord
= get_temp(glsl_type::ivec4_type
);
3522 coord_dst
= st_dst_reg(coord
);
3523 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3524 param
= param
->get_next();
3525 ((ir_dereference
*)param
)->accept(this);
3526 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3527 coord
.swizzle
= SWIZZLE_XXXX
;
3528 switch (type
->coordinate_components()) {
3529 case 4: assert(!"unexpected coord count");
3531 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3533 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3536 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3537 param
= param
->get_next();
3538 ((ir_dereference
*)param
)->accept(this);
3539 st_src_reg sample
= this->result
;
3540 sample
.swizzle
= SWIZZLE_XXXX
;
3541 coord_dst
.writemask
= WRITEMASK_W
;
3542 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3543 coord
.swizzle
|= SWIZZLE_W
<< 9;
3546 param
= param
->get_next();
3547 if (!param
->is_tail_sentinel()) {
3548 ((ir_dereference
*)param
)->accept(this);
3549 arg1
= this->result
;
3550 param
= param
->get_next();
3553 if (!param
->is_tail_sentinel()) {
3554 ((ir_dereference
*)param
)->accept(this);
3555 arg2
= this->result
;
3556 param
= param
->get_next();
3559 assert(param
->is_tail_sentinel());
3562 if (!strcmp("__intrinsic_image_load", callee
))
3563 opcode
= TGSI_OPCODE_LOAD
;
3564 else if (!strcmp("__intrinsic_image_store", callee
))
3565 opcode
= TGSI_OPCODE_STORE
;
3566 else if (!strcmp("__intrinsic_image_atomic_add", callee
))
3567 opcode
= TGSI_OPCODE_ATOMUADD
;
3568 else if (!strcmp("__intrinsic_image_atomic_min", callee
))
3569 opcode
= TGSI_OPCODE_ATOMIMIN
;
3570 else if (!strcmp("__intrinsic_image_atomic_max", callee
))
3571 opcode
= TGSI_OPCODE_ATOMIMAX
;
3572 else if (!strcmp("__intrinsic_image_atomic_and", callee
))
3573 opcode
= TGSI_OPCODE_ATOMAND
;
3574 else if (!strcmp("__intrinsic_image_atomic_or", callee
))
3575 opcode
= TGSI_OPCODE_ATOMOR
;
3576 else if (!strcmp("__intrinsic_image_atomic_xor", callee
))
3577 opcode
= TGSI_OPCODE_ATOMXOR
;
3578 else if (!strcmp("__intrinsic_image_atomic_exchange", callee
))
3579 opcode
= TGSI_OPCODE_ATOMXCHG
;
3580 else if (!strcmp("__intrinsic_image_atomic_comp_swap", callee
))
3581 opcode
= TGSI_OPCODE_ATOMCAS
;
3583 assert(!"Unexpected intrinsic");
3587 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3588 if (opcode
== TGSI_OPCODE_STORE
)
3589 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3592 inst
->buffer
= image
;
3593 inst
->sampler_array_size
= sampler_array_size
;
3594 inst
->sampler_base
= sampler_base
;
3596 switch (type
->sampler_dimensionality
) {
3597 case GLSL_SAMPLER_DIM_1D
:
3598 inst
->tex_target
= (type
->sampler_array
)
3599 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3601 case GLSL_SAMPLER_DIM_2D
:
3602 inst
->tex_target
= (type
->sampler_array
)
3603 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3605 case GLSL_SAMPLER_DIM_3D
:
3606 inst
->tex_target
= TEXTURE_3D_INDEX
;
3608 case GLSL_SAMPLER_DIM_CUBE
:
3609 inst
->tex_target
= (type
->sampler_array
)
3610 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3612 case GLSL_SAMPLER_DIM_RECT
:
3613 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3615 case GLSL_SAMPLER_DIM_BUF
:
3616 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3618 case GLSL_SAMPLER_DIM_EXTERNAL
:
3619 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3621 case GLSL_SAMPLER_DIM_MS
:
3622 inst
->tex_target
= (type
->sampler_array
)
3623 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3626 assert(!"Should not get here.");
3629 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3630 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3632 if (imgvar
->data
.image_coherent
)
3633 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3634 if (imgvar
->data
.image_restrict
)
3635 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3636 if (imgvar
->data
.image_volatile
)
3637 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3641 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3643 glsl_to_tgsi_instruction
*call_inst
;
3644 ir_function_signature
*sig
= ir
->callee
;
3645 const char *callee
= sig
->function_name();
3646 function_entry
*entry
;
3649 /* Filter out intrinsics */
3650 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3651 !strcmp("__intrinsic_atomic_increment", callee
) ||
3652 !strcmp("__intrinsic_atomic_predecrement", callee
) ||
3653 !strcmp("__intrinsic_atomic_add", callee
) ||
3654 !strcmp("__intrinsic_atomic_sub", callee
) ||
3655 !strcmp("__intrinsic_atomic_min", callee
) ||
3656 !strcmp("__intrinsic_atomic_max", callee
) ||
3657 !strcmp("__intrinsic_atomic_and", callee
) ||
3658 !strcmp("__intrinsic_atomic_or", callee
) ||
3659 !strcmp("__intrinsic_atomic_xor", callee
) ||
3660 !strcmp("__intrinsic_atomic_exchange", callee
) ||
3661 !strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3662 visit_atomic_counter_intrinsic(ir
);
3666 if (!strcmp("__intrinsic_load_ssbo", callee
) ||
3667 !strcmp("__intrinsic_store_ssbo", callee
) ||
3668 !strcmp("__intrinsic_atomic_add_ssbo", callee
) ||
3669 !strcmp("__intrinsic_atomic_min_ssbo", callee
) ||
3670 !strcmp("__intrinsic_atomic_max_ssbo", callee
) ||
3671 !strcmp("__intrinsic_atomic_and_ssbo", callee
) ||
3672 !strcmp("__intrinsic_atomic_or_ssbo", callee
) ||
3673 !strcmp("__intrinsic_atomic_xor_ssbo", callee
) ||
3674 !strcmp("__intrinsic_atomic_exchange_ssbo", callee
) ||
3675 !strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3676 visit_ssbo_intrinsic(ir
);
3680 if (!strcmp("__intrinsic_memory_barrier", callee
) ||
3681 !strcmp("__intrinsic_memory_barrier_atomic_counter", callee
) ||
3682 !strcmp("__intrinsic_memory_barrier_buffer", callee
) ||
3683 !strcmp("__intrinsic_memory_barrier_image", callee
) ||
3684 !strcmp("__intrinsic_memory_barrier_shared", callee
) ||
3685 !strcmp("__intrinsic_group_memory_barrier", callee
)) {
3686 visit_membar_intrinsic(ir
);
3690 if (!strcmp("__intrinsic_load_shared", callee
) ||
3691 !strcmp("__intrinsic_store_shared", callee
) ||
3692 !strcmp("__intrinsic_atomic_add_shared", callee
) ||
3693 !strcmp("__intrinsic_atomic_min_shared", callee
) ||
3694 !strcmp("__intrinsic_atomic_max_shared", callee
) ||
3695 !strcmp("__intrinsic_atomic_and_shared", callee
) ||
3696 !strcmp("__intrinsic_atomic_or_shared", callee
) ||
3697 !strcmp("__intrinsic_atomic_xor_shared", callee
) ||
3698 !strcmp("__intrinsic_atomic_exchange_shared", callee
) ||
3699 !strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3700 visit_shared_intrinsic(ir
);
3704 if (!strcmp("__intrinsic_image_load", callee
) ||
3705 !strcmp("__intrinsic_image_store", callee
) ||
3706 !strcmp("__intrinsic_image_atomic_add", callee
) ||
3707 !strcmp("__intrinsic_image_atomic_min", callee
) ||
3708 !strcmp("__intrinsic_image_atomic_max", callee
) ||
3709 !strcmp("__intrinsic_image_atomic_and", callee
) ||
3710 !strcmp("__intrinsic_image_atomic_or", callee
) ||
3711 !strcmp("__intrinsic_image_atomic_xor", callee
) ||
3712 !strcmp("__intrinsic_image_atomic_exchange", callee
) ||
3713 !strcmp("__intrinsic_image_atomic_comp_swap", callee
) ||
3714 !strcmp("__intrinsic_image_size", callee
) ||
3715 !strcmp("__intrinsic_image_samples", callee
)) {
3716 visit_image_intrinsic(ir
);
3720 entry
= get_function_signature(sig
);
3721 /* Process in parameters. */
3722 foreach_two_lists(formal_node
, &sig
->parameters
,
3723 actual_node
, &ir
->actual_parameters
) {
3724 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3725 ir_variable
*param
= (ir_variable
*) formal_node
;
3727 if (param
->data
.mode
== ir_var_function_in
||
3728 param
->data
.mode
== ir_var_function_inout
) {
3729 variable_storage
*storage
= find_variable_storage(param
);
3732 param_rval
->accept(this);
3733 st_src_reg r
= this->result
;
3736 l
.file
= storage
->file
;
3737 l
.index
= storage
->index
;
3739 l
.writemask
= WRITEMASK_XYZW
;
3741 for (i
= 0; i
< type_size(param
->type
); i
++) {
3742 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3749 /* Emit call instruction */
3750 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3751 call_inst
->function
= entry
;
3753 /* Process out parameters. */
3754 foreach_two_lists(formal_node
, &sig
->parameters
,
3755 actual_node
, &ir
->actual_parameters
) {
3756 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3757 ir_variable
*param
= (ir_variable
*) formal_node
;
3759 if (param
->data
.mode
== ir_var_function_out
||
3760 param
->data
.mode
== ir_var_function_inout
) {
3761 variable_storage
*storage
= find_variable_storage(param
);
3765 r
.file
= storage
->file
;
3766 r
.index
= storage
->index
;
3768 r
.swizzle
= SWIZZLE_NOOP
;
3771 param_rval
->accept(this);
3772 st_dst_reg l
= st_dst_reg(this->result
);
3774 for (i
= 0; i
< type_size(param
->type
); i
++) {
3775 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3782 /* Process return value. */
3783 this->result
= entry
->return_reg
;
3787 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3788 ir_dereference
*tail
,
3789 unsigned *array_elements
,
3792 st_src_reg
*indirect
,
3795 switch (tail
->ir_type
) {
3796 case ir_type_dereference_record
: {
3797 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3798 const glsl_type
*struct_type
= deref_record
->record
->type
;
3799 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3801 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3803 assert(field_index
>= 0);
3804 *location
+= struct_type
->record_location_offset(field_index
);
3808 case ir_type_dereference_array
: {
3809 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3810 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3813 st_src_reg temp_reg
;
3814 st_dst_reg temp_dst
;
3816 temp_reg
= get_temp(glsl_type::uint_type
);
3817 temp_dst
= st_dst_reg(temp_reg
);
3818 temp_dst
.writemask
= 1;
3820 deref_arr
->array_index
->accept(this);
3821 if (*array_elements
!= 1)
3822 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3824 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3826 if (indirect
->file
== PROGRAM_UNDEFINED
)
3827 *indirect
= temp_reg
;
3829 temp_dst
= st_dst_reg(*indirect
);
3830 temp_dst
.writemask
= 1;
3831 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3834 *index
+= array_index
->value
.u
[0] * *array_elements
;
3836 *array_elements
*= deref_arr
->array
->type
->length
;
3838 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3847 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3848 unsigned *array_size
,
3851 st_src_reg
*reladdr
)
3853 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3854 unsigned location
= 0;
3855 ir_variable
*var
= ir
->variable_referenced();
3857 memset(reladdr
, 0, sizeof(*reladdr
));
3858 reladdr
->file
= PROGRAM_UNDEFINED
;
3864 location
= var
->data
.location
;
3865 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3868 * If we end up with no indirect then adjust the base to the index,
3869 * and set the array size to 1.
3871 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3876 if (location
!= 0xffffffff) {
3877 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3878 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3883 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3885 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3886 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3887 st_src_reg levels_src
, reladdr
;
3888 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3889 glsl_to_tgsi_instruction
*inst
= NULL
;
3890 unsigned opcode
= TGSI_OPCODE_NOP
;
3891 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3892 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
3893 bool is_cube_array
= false;
3896 /* if we are a cube array sampler */
3897 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3898 sampler_type
->sampler_array
)) {
3899 is_cube_array
= true;
3902 if (ir
->coordinate
) {
3903 ir
->coordinate
->accept(this);
3905 /* Put our coords in a temp. We'll need to modify them for shadow,
3906 * projection, or LOD, so the only case we'd use it as is is if
3907 * we're doing plain old texturing. The optimization passes on
3908 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3910 coord
= get_temp(glsl_type::vec4_type
);
3911 coord_dst
= st_dst_reg(coord
);
3912 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3913 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3916 if (ir
->projector
) {
3917 ir
->projector
->accept(this);
3918 projector
= this->result
;
3921 /* Storage for our result. Ideally for an assignment we'd be using
3922 * the actual storage for the result here, instead.
3924 result_src
= get_temp(ir
->type
);
3925 result_dst
= st_dst_reg(result_src
);
3929 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3931 ir
->offset
->accept(this);
3932 offset
[0] = this->result
;
3936 if (is_cube_array
||
3937 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3938 opcode
= TGSI_OPCODE_TXB2
;
3941 opcode
= TGSI_OPCODE_TXB
;
3943 ir
->lod_info
.bias
->accept(this);
3944 lod_info
= this->result
;
3946 ir
->offset
->accept(this);
3947 offset
[0] = this->result
;
3951 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3952 ir
->lod_info
.lod
->accept(this);
3953 lod_info
= this->result
;
3955 ir
->offset
->accept(this);
3956 offset
[0] = this->result
;
3960 opcode
= TGSI_OPCODE_TXD
;
3961 ir
->lod_info
.grad
.dPdx
->accept(this);
3963 ir
->lod_info
.grad
.dPdy
->accept(this);
3966 ir
->offset
->accept(this);
3967 offset
[0] = this->result
;
3971 opcode
= TGSI_OPCODE_TXQ
;
3972 ir
->lod_info
.lod
->accept(this);
3973 lod_info
= this->result
;
3975 case ir_query_levels
:
3976 opcode
= TGSI_OPCODE_TXQ
;
3977 lod_info
= undef_src
;
3978 levels_src
= get_temp(ir
->type
);
3981 opcode
= TGSI_OPCODE_TXF
;
3982 ir
->lod_info
.lod
->accept(this);
3983 lod_info
= this->result
;
3985 ir
->offset
->accept(this);
3986 offset
[0] = this->result
;
3990 opcode
= TGSI_OPCODE_TXF
;
3991 ir
->lod_info
.sample_index
->accept(this);
3992 sample_index
= this->result
;
3995 opcode
= TGSI_OPCODE_TG4
;
3996 ir
->lod_info
.component
->accept(this);
3997 component
= this->result
;
3999 ir
->offset
->accept(this);
4000 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4001 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4002 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4003 offset
[i
] = this->result
;
4004 offset
[i
].index
+= i
* type_size(elt_type
);
4005 offset
[i
].type
= elt_type
->base_type
;
4006 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4009 offset
[0] = this->result
;
4014 opcode
= TGSI_OPCODE_LODQ
;
4016 case ir_texture_samples
:
4017 opcode
= TGSI_OPCODE_TXQS
;
4019 case ir_samples_identical
:
4020 unreachable("Unexpected ir_samples_identical opcode");
4023 if (ir
->projector
) {
4024 if (opcode
== TGSI_OPCODE_TEX
) {
4025 /* Slot the projector in as the last component of the coord. */
4026 coord_dst
.writemask
= WRITEMASK_W
;
4027 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4028 coord_dst
.writemask
= WRITEMASK_XYZW
;
4029 opcode
= TGSI_OPCODE_TXP
;
4031 st_src_reg coord_w
= coord
;
4032 coord_w
.swizzle
= SWIZZLE_WWWW
;
4034 /* For the other TEX opcodes there's no projective version
4035 * since the last slot is taken up by LOD info. Do the
4036 * projective divide now.
4038 coord_dst
.writemask
= WRITEMASK_W
;
4039 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4041 /* In the case where we have to project the coordinates "by hand,"
4042 * the shadow comparator value must also be projected.
4044 st_src_reg tmp_src
= coord
;
4045 if (ir
->shadow_comparitor
) {
4046 /* Slot the shadow value in as the second to last component of the
4049 ir
->shadow_comparitor
->accept(this);
4051 tmp_src
= get_temp(glsl_type::vec4_type
);
4052 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4054 /* Projective division not allowed for array samplers. */
4055 assert(!sampler_type
->sampler_array
);
4057 tmp_dst
.writemask
= WRITEMASK_Z
;
4058 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4060 tmp_dst
.writemask
= WRITEMASK_XY
;
4061 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4064 coord_dst
.writemask
= WRITEMASK_XYZ
;
4065 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4067 coord_dst
.writemask
= WRITEMASK_XYZW
;
4068 coord
.swizzle
= SWIZZLE_XYZW
;
4072 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4073 * comparator was put in the correct place (and projected) by the code,
4074 * above, that handles by-hand projection.
4076 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4077 /* Slot the shadow value in as the second to last component of the
4080 ir
->shadow_comparitor
->accept(this);
4082 if (is_cube_array
) {
4083 cube_sc
= get_temp(glsl_type::float_type
);
4084 cube_sc_dst
= st_dst_reg(cube_sc
);
4085 cube_sc_dst
.writemask
= WRITEMASK_X
;
4086 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4087 cube_sc_dst
.writemask
= WRITEMASK_X
;
4090 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4091 sampler_type
->sampler_array
) ||
4092 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4093 coord_dst
.writemask
= WRITEMASK_W
;
4095 coord_dst
.writemask
= WRITEMASK_Z
;
4097 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4098 coord_dst
.writemask
= WRITEMASK_XYZW
;
4102 if (ir
->op
== ir_txf_ms
) {
4103 coord_dst
.writemask
= WRITEMASK_W
;
4104 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4105 coord_dst
.writemask
= WRITEMASK_XYZW
;
4106 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4107 opcode
== TGSI_OPCODE_TXF
) {
4108 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4109 coord_dst
.writemask
= WRITEMASK_W
;
4110 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4111 coord_dst
.writemask
= WRITEMASK_XYZW
;
4114 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4115 &sampler_index
, &reladdr
);
4116 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4117 emit_arl(ir
, sampler_reladdr
, reladdr
);
4119 if (opcode
== TGSI_OPCODE_TXD
)
4120 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4121 else if (opcode
== TGSI_OPCODE_TXQ
) {
4122 if (ir
->op
== ir_query_levels
) {
4123 /* the level is stored in W */
4124 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4125 result_dst
.writemask
= WRITEMASK_X
;
4126 levels_src
.swizzle
= SWIZZLE_WWWW
;
4127 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4129 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4130 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4131 inst
= emit_asm(ir
, opcode
, result_dst
);
4132 } else if (opcode
== TGSI_OPCODE_TXF
) {
4133 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4134 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4135 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4136 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4137 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4138 } else if (opcode
== TGSI_OPCODE_TG4
) {
4139 if (is_cube_array
&& ir
->shadow_comparitor
) {
4140 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4142 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4145 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4147 if (ir
->shadow_comparitor
)
4148 inst
->tex_shadow
= GL_TRUE
;
4150 inst
->sampler
.index
= sampler_index
;
4151 inst
->sampler_array_size
= sampler_array_size
;
4152 inst
->sampler_base
= sampler_base
;
4154 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4155 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4156 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4160 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4161 inst
->tex_offsets
[i
] = offset
[i
];
4162 inst
->tex_offset_num_offset
= i
;
4165 switch (sampler_type
->sampler_dimensionality
) {
4166 case GLSL_SAMPLER_DIM_1D
:
4167 inst
->tex_target
= (sampler_type
->sampler_array
)
4168 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4170 case GLSL_SAMPLER_DIM_2D
:
4171 inst
->tex_target
= (sampler_type
->sampler_array
)
4172 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4174 case GLSL_SAMPLER_DIM_3D
:
4175 inst
->tex_target
= TEXTURE_3D_INDEX
;
4177 case GLSL_SAMPLER_DIM_CUBE
:
4178 inst
->tex_target
= (sampler_type
->sampler_array
)
4179 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4181 case GLSL_SAMPLER_DIM_RECT
:
4182 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4184 case GLSL_SAMPLER_DIM_BUF
:
4185 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4187 case GLSL_SAMPLER_DIM_EXTERNAL
:
4188 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4190 case GLSL_SAMPLER_DIM_MS
:
4191 inst
->tex_target
= (sampler_type
->sampler_array
)
4192 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4195 assert(!"Should not get here.");
4198 inst
->tex_type
= ir
->type
->base_type
;
4200 this->result
= result_src
;
4204 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4206 if (ir
->get_value()) {
4210 assert(current_function
);
4212 ir
->get_value()->accept(this);
4213 st_src_reg r
= this->result
;
4215 l
= st_dst_reg(current_function
->return_reg
);
4217 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4218 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4224 emit_asm(ir
, TGSI_OPCODE_RET
);
4228 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4230 if (ir
->condition
) {
4231 ir
->condition
->accept(this);
4232 st_src_reg condition
= this->result
;
4234 /* Convert the bool condition to a float so we can negate. */
4235 if (native_integers
) {
4236 st_src_reg temp
= get_temp(ir
->condition
->type
);
4237 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4238 condition
, st_src_reg_for_float(1.0));
4242 condition
.negate
= ~condition
.negate
;
4243 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4245 /* unconditional kil */
4246 emit_asm(ir
, TGSI_OPCODE_KILL
);
4251 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4254 glsl_to_tgsi_instruction
*if_inst
;
4256 ir
->condition
->accept(this);
4257 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4259 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4261 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4263 this->instructions
.push_tail(if_inst
);
4265 visit_exec_list(&ir
->then_instructions
, this);
4267 if (!ir
->else_instructions
.is_empty()) {
4268 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4269 visit_exec_list(&ir
->else_instructions
, this);
4272 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4277 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4279 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4281 ir
->stream
->accept(this);
4282 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4286 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4288 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4290 ir
->stream
->accept(this);
4291 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4295 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4297 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4298 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4300 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4303 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4305 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4307 result
.file
= PROGRAM_UNDEFINED
;
4312 num_input_arrays
= 0;
4313 num_output_arrays
= 0;
4314 next_signature_id
= 1;
4316 current_function
= NULL
;
4317 num_address_regs
= 0;
4321 indirect_addr_consts
= false;
4322 wpos_transform_const
= -1;
4324 native_integers
= false;
4325 mem_ctx
= ralloc_context(NULL
);
4328 shader_program
= NULL
;
4333 use_shared_memory
= false;
4336 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4339 ralloc_free(mem_ctx
);
4342 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4349 * Count resources used by the given gpu program (number of texture
4353 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4355 v
->samplers_used
= 0;
4356 v
->buffers_used
= 0;
4359 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4360 if (inst
->info
->is_tex
) {
4361 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4362 unsigned idx
= inst
->sampler_base
+ i
;
4363 v
->samplers_used
|= 1u << idx
;
4365 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4366 v
->sampler_types
[idx
] = inst
->tex_type
;
4367 v
->sampler_targets
[idx
] =
4368 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4370 if (inst
->tex_shadow
) {
4371 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4375 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4376 is_resource_instruction(inst
->op
) ||
4377 inst
->op
== TGSI_OPCODE_STORE
)) {
4378 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4379 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4380 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4381 v
->use_shared_memory
= true;
4383 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4384 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4385 unsigned idx
= inst
->sampler_base
+ i
;
4386 v
->images_used
|= 1 << idx
;
4387 v
->image_targets
[idx
] =
4388 st_translate_texture_target(inst
->tex_target
, false);
4389 v
->image_formats
[idx
] = inst
->image_format
;
4394 prog
->SamplersUsed
= v
->samplers_used
;
4396 if (v
->shader_program
!= NULL
)
4397 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4401 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4402 * are read from the given src in this instruction
4405 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4407 int read_mask
= 0, comp
;
4409 /* Now, given the src swizzle and the written channels, find which
4410 * components are actually read
4412 for (comp
= 0; comp
< 4; ++comp
) {
4413 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4415 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4416 read_mask
|= 1 << coord
;
4423 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4424 * instruction is the first instruction to write to register T0. There are
4425 * several lowering passes done in GLSL IR (e.g. branches and
4426 * relative addressing) that create a large number of conditional assignments
4427 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4429 * Here is why this conversion is safe:
4430 * CMP T0, T1 T2 T0 can be expanded to:
4436 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4437 * as the original program. If (T1 < 0.0) evaluates to false, executing
4438 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4439 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4440 * because any instruction that was going to read from T0 after this was going
4441 * to read a garbage value anyway.
4444 glsl_to_tgsi_visitor::simplify_cmp(void)
4446 int tempWritesSize
= 0;
4447 unsigned *tempWrites
= NULL
;
4448 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4450 memset(outputWrites
, 0, sizeof(outputWrites
));
4452 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4453 unsigned prevWriteMask
= 0;
4455 /* Give up if we encounter relative addressing or flow control. */
4456 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4457 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4458 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4459 inst
->op
== TGSI_OPCODE_BGNSUB
||
4460 inst
->op
== TGSI_OPCODE_CONT
||
4461 inst
->op
== TGSI_OPCODE_END
||
4462 inst
->op
== TGSI_OPCODE_ENDSUB
||
4463 inst
->op
== TGSI_OPCODE_RET
) {
4467 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4468 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4469 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4470 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4471 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4472 if (inst
->dst
[0].index
>= tempWritesSize
) {
4473 const int inc
= 4096;
4475 tempWrites
= (unsigned*)
4477 (tempWritesSize
+ inc
) * sizeof(unsigned));
4481 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4482 tempWritesSize
+= inc
;
4485 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4486 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4490 /* For a CMP to be considered a conditional write, the destination
4491 * register and source register two must be the same. */
4492 if (inst
->op
== TGSI_OPCODE_CMP
4493 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4494 && inst
->src
[2].file
== inst
->dst
[0].file
4495 && inst
->src
[2].index
== inst
->dst
[0].index
4496 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4498 inst
->op
= TGSI_OPCODE_MOV
;
4499 inst
->src
[0] = inst
->src
[1];
4506 /* Replaces all references to a temporary register index with another index. */
4508 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4510 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4513 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4514 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4515 for (k
= 0; k
< num_renames
; k
++)
4516 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4517 inst
->src
[j
].index
= renames
[k
].new_reg
;
4520 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4521 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4522 for (k
= 0; k
< num_renames
; k
++)
4523 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4524 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4527 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4528 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4529 for (k
= 0; k
< num_renames
; k
++)
4530 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4531 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4537 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4539 int depth
= 0; /* loop depth */
4540 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4543 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4544 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4545 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4546 if (first_reads
[inst
->src
[j
].index
] == -1)
4547 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4550 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4551 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4552 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4553 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4556 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4559 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4569 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4571 int depth
= 0; /* loop depth */
4572 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4575 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4576 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4577 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4578 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4580 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4581 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4582 if (first_writes
[inst
->dst
[j
].index
] == -1)
4583 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4584 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4587 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4588 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4589 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4591 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4594 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4597 for (k
= 0; k
< this->next_temp
; k
++) {
4598 if (last_reads
[k
] == -2) {
4610 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4612 int depth
= 0; /* loop depth */
4616 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4617 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4618 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4619 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4622 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4624 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4626 for (k
= 0; k
< this->next_temp
; k
++) {
4627 if (last_writes
[k
] == -2) {
4638 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4639 * channels for copy propagation and updates following instructions to
4640 * use the original versions.
4642 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4643 * will occur. As an example, a TXP production before this pass:
4645 * 0: MOV TEMP[1], INPUT[4].xyyy;
4646 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4647 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4651 * 0: MOV TEMP[1], INPUT[4].xyyy;
4652 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4653 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4655 * which allows for dead code elimination on TEMP[1]'s writes.
4658 glsl_to_tgsi_visitor::copy_propagate(void)
4660 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4661 glsl_to_tgsi_instruction
*,
4662 this->next_temp
* 4);
4663 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4666 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4667 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4668 || inst
->dst
[0].index
< this->next_temp
);
4670 /* First, do any copy propagation possible into the src regs. */
4671 for (int r
= 0; r
< 3; r
++) {
4672 glsl_to_tgsi_instruction
*first
= NULL
;
4674 int acp_base
= inst
->src
[r
].index
* 4;
4676 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4677 inst
->src
[r
].reladdr
||
4678 inst
->src
[r
].reladdr2
)
4681 /* See if we can find entries in the ACP consisting of MOVs
4682 * from the same src register for all the swizzled channels
4683 * of this src register reference.
4685 for (int i
= 0; i
< 4; i
++) {
4686 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4687 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4694 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4699 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4700 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4701 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4702 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4710 /* We've now validated that we can copy-propagate to
4711 * replace this src register reference. Do it.
4713 inst
->src
[r
].file
= first
->src
[0].file
;
4714 inst
->src
[r
].index
= first
->src
[0].index
;
4715 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4716 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4717 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4718 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4721 for (int i
= 0; i
< 4; i
++) {
4722 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4723 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4724 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4726 inst
->src
[r
].swizzle
= swizzle
;
4731 case TGSI_OPCODE_BGNLOOP
:
4732 case TGSI_OPCODE_ENDLOOP
:
4733 /* End of a basic block, clear the ACP entirely. */
4734 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4737 case TGSI_OPCODE_IF
:
4738 case TGSI_OPCODE_UIF
:
4742 case TGSI_OPCODE_ENDIF
:
4743 case TGSI_OPCODE_ELSE
:
4744 /* Clear all channels written inside the block from the ACP, but
4745 * leaving those that were not touched.
4747 for (int r
= 0; r
< this->next_temp
; r
++) {
4748 for (int c
= 0; c
< 4; c
++) {
4749 if (!acp
[4 * r
+ c
])
4752 if (acp_level
[4 * r
+ c
] >= level
)
4753 acp
[4 * r
+ c
] = NULL
;
4756 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4761 /* Continuing the block, clear any written channels from
4764 for (int d
= 0; d
< 2; d
++) {
4765 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4766 /* Any temporary might be written, so no copy propagation
4767 * across this instruction.
4769 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4770 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4771 inst
->dst
[d
].reladdr
) {
4772 /* Any output might be written, so no copy propagation
4773 * from outputs across this instruction.
4775 for (int r
= 0; r
< this->next_temp
; r
++) {
4776 for (int c
= 0; c
< 4; c
++) {
4777 if (!acp
[4 * r
+ c
])
4780 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4781 acp
[4 * r
+ c
] = NULL
;
4784 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4785 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4786 /* Clear where it's used as dst. */
4787 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4788 for (int c
= 0; c
< 4; c
++) {
4789 if (inst
->dst
[d
].writemask
& (1 << c
))
4790 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4794 /* Clear where it's used as src. */
4795 for (int r
= 0; r
< this->next_temp
; r
++) {
4796 for (int c
= 0; c
< 4; c
++) {
4797 if (!acp
[4 * r
+ c
])
4800 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4802 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4803 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4804 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4805 acp
[4 * r
+ c
] = NULL
;
4814 /* If this is a copy, add it to the ACP. */
4815 if (inst
->op
== TGSI_OPCODE_MOV
&&
4816 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4817 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4818 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4819 !inst
->dst
[0].reladdr
&&
4820 !inst
->dst
[0].reladdr2
&&
4822 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4823 !inst
->src
[0].reladdr
&&
4824 !inst
->src
[0].reladdr2
&&
4825 !inst
->src
[0].negate
) {
4826 for (int i
= 0; i
< 4; i
++) {
4827 if (inst
->dst
[0].writemask
& (1 << i
)) {
4828 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4829 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4835 ralloc_free(acp_level
);
4840 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4843 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4844 * will occur. As an example, a TXP production after copy propagation but
4847 * 0: MOV TEMP[1], INPUT[4].xyyy;
4848 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4849 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4851 * and after this pass:
4853 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4856 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4858 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4859 glsl_to_tgsi_instruction
*,
4860 this->next_temp
* 4);
4861 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4865 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4866 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4867 || inst
->dst
[0].index
< this->next_temp
);
4870 case TGSI_OPCODE_BGNLOOP
:
4871 case TGSI_OPCODE_ENDLOOP
:
4872 case TGSI_OPCODE_CONT
:
4873 case TGSI_OPCODE_BRK
:
4874 /* End of a basic block, clear the write array entirely.
4876 * This keeps us from killing dead code when the writes are
4877 * on either side of a loop, even when the register isn't touched
4878 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4879 * dead code of this type, so it shouldn't make a difference as long as
4880 * the dead code elimination pass in the GLSL compiler does its job.
4882 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4885 case TGSI_OPCODE_ENDIF
:
4886 case TGSI_OPCODE_ELSE
:
4887 /* Promote the recorded level of all channels written inside the
4888 * preceding if or else block to the level above the if/else block.
4890 for (int r
= 0; r
< this->next_temp
; r
++) {
4891 for (int c
= 0; c
< 4; c
++) {
4892 if (!writes
[4 * r
+ c
])
4895 if (write_level
[4 * r
+ c
] == level
)
4896 write_level
[4 * r
+ c
] = level
-1;
4899 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4903 case TGSI_OPCODE_IF
:
4904 case TGSI_OPCODE_UIF
:
4906 /* fallthrough to default case to mark the condition as read */
4908 /* Continuing the block, clear any channels from the write array that
4909 * are read by this instruction.
4911 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4912 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4913 /* Any temporary might be read, so no dead code elimination
4914 * across this instruction.
4916 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4917 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4918 /* Clear where it's used as src. */
4919 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4920 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4921 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4922 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4924 for (int c
= 0; c
< 4; c
++) {
4925 if (src_chans
& (1 << c
))
4926 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4930 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4931 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4932 /* Any temporary might be read, so no dead code elimination
4933 * across this instruction.
4935 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4936 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4937 /* Clear where it's used as src. */
4938 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4939 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4940 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4941 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4943 for (int c
= 0; c
< 4; c
++) {
4944 if (src_chans
& (1 << c
))
4945 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4952 /* If this instruction writes to a temporary, add it to the write array.
4953 * If there is already an instruction in the write array for one or more
4954 * of the channels, flag that channel write as dead.
4956 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4957 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4958 !inst
->dst
[i
].reladdr
) {
4959 for (int c
= 0; c
< 4; c
++) {
4960 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4961 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4962 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4965 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4967 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4968 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4975 /* Anything still in the write array at this point is dead code. */
4976 for (int r
= 0; r
< this->next_temp
; r
++) {
4977 for (int c
= 0; c
< 4; c
++) {
4978 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4980 inst
->dead_mask
|= (1 << c
);
4984 /* Now actually remove the instructions that are completely dead and update
4985 * the writemask of other instructions with dead channels.
4987 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4988 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4990 /* No amount of dead masks should remove memory stores */
4991 if (inst
->info
->is_store
)
4994 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4999 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
5000 if (inst
->dead_mask
== WRITEMASK_XY
||
5001 inst
->dead_mask
== WRITEMASK_ZW
)
5002 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5004 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5008 ralloc_free(write_level
);
5009 ralloc_free(writes
);
5014 /* merge DFRACEXP instructions into one. */
5016 glsl_to_tgsi_visitor::merge_two_dsts(void)
5018 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5019 glsl_to_tgsi_instruction
*inst2
;
5021 if (num_inst_dst_regs(inst
) != 2)
5024 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5025 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5028 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5031 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5032 inst
->src
[0].index
== inst2
->src
[0].index
&&
5033 inst
->src
[0].type
== inst2
->src
[0].type
&&
5034 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5036 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5042 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5044 inst
->dst
[0] = inst2
->dst
[0];
5045 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5046 inst
->dst
[1] = inst2
->dst
[1];
5057 /* Merges temporary registers together where possible to reduce the number of
5058 * registers needed to run a program.
5060 * Produces optimal code only after copy propagation and dead code elimination
5063 glsl_to_tgsi_visitor::merge_registers(void)
5065 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5066 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5067 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5069 int num_renames
= 0;
5071 /* Read the indices of the last read and first write to each temp register
5072 * into an array so that we don't have to traverse the instruction list as
5074 for (i
= 0; i
< this->next_temp
; i
++) {
5076 first_writes
[i
] = -1;
5078 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5080 /* Start looking for registers with non-overlapping usages that can be
5081 * merged together. */
5082 for (i
= 0; i
< this->next_temp
; i
++) {
5083 /* Don't touch unused registers. */
5084 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5086 for (j
= 0; j
< this->next_temp
; j
++) {
5087 /* Don't touch unused registers. */
5088 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5090 /* We can merge the two registers if the first write to j is after or
5091 * in the same instruction as the last read from i. Note that the
5092 * register at index i will always be used earlier or at the same time
5093 * as the register at index j. */
5094 if (first_writes
[i
] <= first_writes
[j
] &&
5095 last_reads
[i
] <= first_writes
[j
]) {
5096 renames
[num_renames
].old_reg
= j
;
5097 renames
[num_renames
].new_reg
= i
;
5100 /* Update the first_writes and last_reads arrays with the new
5101 * values for the merged register index, and mark the newly unused
5102 * register index as such. */
5103 assert(last_reads
[j
] >= last_reads
[i
]);
5104 last_reads
[i
] = last_reads
[j
];
5105 first_writes
[j
] = -1;
5111 rename_temp_registers(num_renames
, renames
);
5112 ralloc_free(renames
);
5113 ralloc_free(last_reads
);
5114 ralloc_free(first_writes
);
5117 /* Reassign indices to temporary registers by reusing unused indices created
5118 * by optimization passes. */
5120 glsl_to_tgsi_visitor::renumber_registers(void)
5124 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5125 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5126 int num_renames
= 0;
5127 for (i
= 0; i
< this->next_temp
; i
++) {
5128 first_reads
[i
] = -1;
5130 get_first_temp_read(first_reads
);
5132 for (i
= 0; i
< this->next_temp
; i
++) {
5133 if (first_reads
[i
] < 0) continue;
5134 if (i
!= new_index
) {
5135 renames
[num_renames
].old_reg
= i
;
5136 renames
[num_renames
].new_reg
= new_index
;
5142 rename_temp_registers(num_renames
, renames
);
5143 this->next_temp
= new_index
;
5144 ralloc_free(renames
);
5145 ralloc_free(first_reads
);
5148 /* ------------------------- TGSI conversion stuff -------------------------- */
5150 unsigned branch_target
;
5155 * Intermediate state used during shader translation.
5157 struct st_translate
{
5158 struct ureg_program
*ureg
;
5160 unsigned temps_size
;
5161 struct ureg_dst
*temps
;
5163 struct ureg_dst
*arrays
;
5164 unsigned num_temp_arrays
;
5165 struct ureg_src
*constants
;
5167 struct ureg_src
*immediates
;
5169 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5170 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5171 struct ureg_dst address
[3];
5172 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5173 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5174 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5175 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5176 struct ureg_src shared_memory
;
5177 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5178 unsigned *array_sizes
;
5179 struct array_decl
*input_arrays
;
5180 struct array_decl
*output_arrays
;
5182 const GLuint
*inputMapping
;
5183 const GLuint
*outputMapping
;
5185 /* For every instruction that contains a label (eg CALL), keep
5186 * details so that we can go back afterwards and emit the correct
5187 * tgsi instruction number for each label.
5189 struct label
*labels
;
5190 unsigned labels_size
;
5191 unsigned labels_count
;
5193 /* Keep a record of the tgsi instruction number that each mesa
5194 * instruction starts at, will be used to fix up labels after
5199 unsigned insn_count
;
5201 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5206 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5208 _mesa_sysval_to_semantic(unsigned sysval
)
5212 case SYSTEM_VALUE_VERTEX_ID
:
5213 return TGSI_SEMANTIC_VERTEXID
;
5214 case SYSTEM_VALUE_INSTANCE_ID
:
5215 return TGSI_SEMANTIC_INSTANCEID
;
5216 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5217 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5218 case SYSTEM_VALUE_BASE_VERTEX
:
5219 return TGSI_SEMANTIC_BASEVERTEX
;
5220 case SYSTEM_VALUE_BASE_INSTANCE
:
5221 return TGSI_SEMANTIC_BASEINSTANCE
;
5222 case SYSTEM_VALUE_DRAW_ID
:
5223 return TGSI_SEMANTIC_DRAWID
;
5225 /* Geometry shader */
5226 case SYSTEM_VALUE_INVOCATION_ID
:
5227 return TGSI_SEMANTIC_INVOCATIONID
;
5229 /* Fragment shader */
5230 case SYSTEM_VALUE_FRAG_COORD
:
5231 return TGSI_SEMANTIC_POSITION
;
5232 case SYSTEM_VALUE_FRONT_FACE
:
5233 return TGSI_SEMANTIC_FACE
;
5234 case SYSTEM_VALUE_SAMPLE_ID
:
5235 return TGSI_SEMANTIC_SAMPLEID
;
5236 case SYSTEM_VALUE_SAMPLE_POS
:
5237 return TGSI_SEMANTIC_SAMPLEPOS
;
5238 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5239 return TGSI_SEMANTIC_SAMPLEMASK
;
5240 case SYSTEM_VALUE_HELPER_INVOCATION
:
5241 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5243 /* Tessellation shader */
5244 case SYSTEM_VALUE_TESS_COORD
:
5245 return TGSI_SEMANTIC_TESSCOORD
;
5246 case SYSTEM_VALUE_VERTICES_IN
:
5247 return TGSI_SEMANTIC_VERTICESIN
;
5248 case SYSTEM_VALUE_PRIMITIVE_ID
:
5249 return TGSI_SEMANTIC_PRIMID
;
5250 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5251 return TGSI_SEMANTIC_TESSOUTER
;
5252 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5253 return TGSI_SEMANTIC_TESSINNER
;
5255 /* Compute shader */
5256 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5257 return TGSI_SEMANTIC_THREAD_ID
;
5258 case SYSTEM_VALUE_WORK_GROUP_ID
:
5259 return TGSI_SEMANTIC_BLOCK_ID
;
5260 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5261 return TGSI_SEMANTIC_GRID_SIZE
;
5264 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5265 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5266 case SYSTEM_VALUE_VERTEX_CNT
:
5268 assert(!"Unexpected SYSTEM_VALUE_ enum");
5269 return TGSI_SEMANTIC_COUNT
;
5275 * Make note of a branch to a label in the TGSI code.
5276 * After we've emitted all instructions, we'll go over the list
5277 * of labels built here and patch the TGSI code with the actual
5278 * location of each label.
5280 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5284 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5285 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5286 t
->labels
= (struct label
*)realloc(t
->labels
,
5287 t
->labels_size
* sizeof(struct label
));
5288 if (t
->labels
== NULL
) {
5289 static unsigned dummy
;
5295 i
= t
->labels_count
++;
5296 t
->labels
[i
].branch_target
= branch_target
;
5297 return &t
->labels
[i
].token
;
5301 * Called prior to emitting the TGSI code for each instruction.
5302 * Allocate additional space for instructions if needed.
5303 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5304 * the next TGSI instruction.
5306 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5308 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5309 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5310 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5311 if (t
->insn
== NULL
) {
5317 t
->insn
[t
->insn_count
++] = start
;
5321 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5323 static struct ureg_src
5324 emit_immediate(struct st_translate
*t
,
5325 gl_constant_value values
[4],
5328 struct ureg_program
*ureg
= t
->ureg
;
5333 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5335 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5337 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5338 case GL_UNSIGNED_INT
:
5340 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5342 assert(!"should not get here - type must be float, int, uint, or bool");
5343 return ureg_src_undef();
5348 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5350 static struct ureg_dst
5351 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5357 case PROGRAM_UNDEFINED
:
5358 return ureg_dst_undef();
5360 case PROGRAM_TEMPORARY
:
5361 /* Allocate space for temporaries on demand. */
5362 if (index
>= t
->temps_size
) {
5363 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5365 t
->temps
= (struct ureg_dst
*)
5367 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5369 return ureg_dst_undef();
5371 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5372 t
->temps_size
+= inc
;
5375 if (ureg_dst_is_undef(t
->temps
[index
]))
5376 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5378 return t
->temps
[index
];
5381 array
= index
>> 16;
5383 assert(array
< t
->num_temp_arrays
);
5385 if (ureg_dst_is_undef(t
->arrays
[array
]))
5386 t
->arrays
[array
] = ureg_DECL_array_temporary(
5387 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5389 return ureg_dst_array_offset(t
->arrays
[array
],
5390 (int)(index
& 0xFFFF) - 0x8000);
5392 case PROGRAM_OUTPUT
:
5394 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5395 assert(index
< FRAG_RESULT_MAX
);
5396 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5397 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5398 assert(index
< VARYING_SLOT_TESS_MAX
);
5400 assert(index
< VARYING_SLOT_MAX
);
5402 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5403 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5404 return t
->outputs
[t
->outputMapping
[index
]];
5407 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
5408 unsigned mesa_index
= decl
->mesa_index
;
5409 int slot
= t
->outputMapping
[mesa_index
];
5411 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5412 assert(t
->outputs
[slot
].ArrayID
== array_id
);
5413 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
5416 case PROGRAM_ADDRESS
:
5417 return t
->address
[index
];
5420 assert(!"unknown dst register file");
5421 return ureg_dst_undef();
5426 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5428 static struct ureg_src
5429 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5431 int index
= reg
->index
;
5432 int double_reg2
= reg
->double_reg2
? 1 : 0;
5435 case PROGRAM_UNDEFINED
:
5436 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5438 case PROGRAM_TEMPORARY
:
5440 case PROGRAM_OUTPUT
:
5441 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5443 case PROGRAM_UNIFORM
:
5444 assert(reg
->index
>= 0);
5445 return reg
->index
< t
->num_constants
?
5446 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5447 case PROGRAM_STATE_VAR
:
5448 case PROGRAM_CONSTANT
: /* ie, immediate */
5449 if (reg
->has_index2
)
5450 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5452 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5453 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5455 case PROGRAM_IMMEDIATE
:
5456 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5457 return t
->immediates
[reg
->index
];
5460 /* GLSL inputs are 64-bit containers, so we have to
5461 * map back to the original index and add the offset after
5463 index
-= double_reg2
;
5464 if (!reg
->array_id
) {
5465 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5466 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5467 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5470 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
5471 unsigned mesa_index
= decl
->mesa_index
;
5472 int slot
= t
->inputMapping
[mesa_index
];
5474 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5475 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
5476 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
5479 case PROGRAM_ADDRESS
:
5480 return ureg_src(t
->address
[reg
->index
]);
5482 case PROGRAM_SYSTEM_VALUE
:
5483 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5484 return t
->systemValues
[reg
->index
];
5487 assert(!"unknown src register file");
5488 return ureg_src_undef();
5493 * Create a TGSI ureg_dst register from an st_dst_reg.
5495 static struct ureg_dst
5496 translate_dst(struct st_translate
*t
,
5497 const st_dst_reg
*dst_reg
,
5500 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5503 if (dst
.File
== TGSI_FILE_NULL
)
5506 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5509 dst
= ureg_saturate(dst
);
5511 if (dst_reg
->reladdr
!= NULL
) {
5512 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5513 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5516 if (dst_reg
->has_index2
) {
5517 if (dst_reg
->reladdr2
)
5518 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5521 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5528 * Create a TGSI ureg_src register from an st_src_reg.
5530 static struct ureg_src
5531 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5533 struct ureg_src src
= src_register(t
, src_reg
);
5535 if (src_reg
->has_index2
) {
5536 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5537 * and UBO constant buffers (buffer, position).
5539 if (src_reg
->reladdr2
)
5540 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5543 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5546 src
= ureg_swizzle(src
,
5547 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5548 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5549 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5550 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5552 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5553 src
= ureg_negate(src
);
5555 if (src_reg
->reladdr
!= NULL
) {
5556 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5557 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5563 static struct tgsi_texture_offset
5564 translate_tex_offset(struct st_translate
*t
,
5565 const st_src_reg
*in_offset
, int idx
)
5567 struct tgsi_texture_offset offset
;
5568 struct ureg_src imm_src
;
5569 struct ureg_dst dst
;
5572 switch (in_offset
->file
) {
5573 case PROGRAM_IMMEDIATE
:
5574 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
5575 imm_src
= t
->immediates
[in_offset
->index
];
5577 offset
.File
= imm_src
.File
;
5578 offset
.Index
= imm_src
.Index
;
5579 offset
.SwizzleX
= imm_src
.SwizzleX
;
5580 offset
.SwizzleY
= imm_src
.SwizzleY
;
5581 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
5585 imm_src
= t
->inputs
[t
->inputMapping
[in_offset
->index
]];
5586 offset
.File
= imm_src
.File
;
5587 offset
.Index
= imm_src
.Index
;
5588 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5589 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5590 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5593 case PROGRAM_TEMPORARY
:
5594 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
5595 offset
.File
= imm_src
.File
;
5596 offset
.Index
= imm_src
.Index
;
5597 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5598 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5599 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5603 array
= in_offset
->index
>> 16;
5606 assert(array
< (int)t
->num_temp_arrays
);
5608 dst
= t
->arrays
[array
];
5609 offset
.File
= dst
.File
;
5610 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
5611 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5612 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5613 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5623 compile_tgsi_instruction(struct st_translate
*t
,
5624 const glsl_to_tgsi_instruction
*inst
)
5626 struct ureg_program
*ureg
= t
->ureg
;
5628 struct ureg_dst dst
[2];
5629 struct ureg_src src
[4];
5630 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5634 unsigned tex_target
= 0;
5636 num_dst
= num_inst_dst_regs(inst
);
5637 num_src
= num_inst_src_regs(inst
);
5639 for (i
= 0; i
< num_dst
; i
++)
5640 dst
[i
] = translate_dst(t
,
5644 for (i
= 0; i
< num_src
; i
++)
5645 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5648 case TGSI_OPCODE_BGNLOOP
:
5649 case TGSI_OPCODE_CAL
:
5650 case TGSI_OPCODE_ELSE
:
5651 case TGSI_OPCODE_ENDLOOP
:
5652 case TGSI_OPCODE_IF
:
5653 case TGSI_OPCODE_UIF
:
5654 assert(num_dst
== 0);
5655 ureg_label_insn(ureg
,
5659 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5662 case TGSI_OPCODE_TEX
:
5663 case TGSI_OPCODE_TXB
:
5664 case TGSI_OPCODE_TXD
:
5665 case TGSI_OPCODE_TXL
:
5666 case TGSI_OPCODE_TXP
:
5667 case TGSI_OPCODE_TXQ
:
5668 case TGSI_OPCODE_TXQS
:
5669 case TGSI_OPCODE_TXF
:
5670 case TGSI_OPCODE_TEX2
:
5671 case TGSI_OPCODE_TXB2
:
5672 case TGSI_OPCODE_TXL2
:
5673 case TGSI_OPCODE_TG4
:
5674 case TGSI_OPCODE_LODQ
:
5675 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5676 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5677 if (inst
->sampler
.reladdr
)
5679 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5681 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5682 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5684 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5690 texoffsets
, inst
->tex_offset_num_offset
,
5694 case TGSI_OPCODE_RESQ
:
5695 case TGSI_OPCODE_LOAD
:
5696 case TGSI_OPCODE_ATOMUADD
:
5697 case TGSI_OPCODE_ATOMXCHG
:
5698 case TGSI_OPCODE_ATOMCAS
:
5699 case TGSI_OPCODE_ATOMAND
:
5700 case TGSI_OPCODE_ATOMOR
:
5701 case TGSI_OPCODE_ATOMXOR
:
5702 case TGSI_OPCODE_ATOMUMIN
:
5703 case TGSI_OPCODE_ATOMUMAX
:
5704 case TGSI_OPCODE_ATOMIMIN
:
5705 case TGSI_OPCODE_ATOMIMAX
:
5706 for (i
= num_src
- 1; i
>= 0; i
--)
5707 src
[i
+ 1] = src
[i
];
5709 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5710 src
[0] = t
->shared_memory
;
5711 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5712 src
[0] = t
->buffers
[inst
->buffer
.index
];
5714 src
[0] = t
->images
[inst
->buffer
.index
];
5715 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5717 if (inst
->buffer
.reladdr
)
5718 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5719 assert(src
[0].File
!= TGSI_FILE_NULL
);
5720 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5721 inst
->buffer_access
,
5722 tex_target
, inst
->image_format
);
5725 case TGSI_OPCODE_STORE
:
5726 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5727 dst
[0] = ureg_dst(t
->shared_memory
);
5728 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5729 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5731 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5732 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5734 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5735 if (inst
->buffer
.reladdr
)
5736 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5737 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5738 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5739 inst
->buffer_access
,
5740 tex_target
, inst
->image_format
);
5743 case TGSI_OPCODE_SCS
:
5744 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5745 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5758 * Emit the TGSI instructions for inverting and adjusting WPOS.
5759 * This code is unavoidable because it also depends on whether
5760 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5763 emit_wpos_adjustment(struct gl_context
*ctx
,
5764 struct st_translate
*t
,
5765 int wpos_transform_const
,
5767 GLfloat adjX
, GLfloat adjY
[2])
5769 struct ureg_program
*ureg
= t
->ureg
;
5771 assert(wpos_transform_const
>= 0);
5773 /* Fragment program uses fragment position input.
5774 * Need to replace instances of INPUT[WPOS] with temp T
5775 * where T = INPUT[WPOS] is inverted by Y.
5777 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5778 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5779 struct ureg_src
*wpos
=
5780 ctx
->Const
.GLSLFragCoordIsSysVal
?
5781 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5782 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5783 struct ureg_src wpos_input
= *wpos
;
5785 /* First, apply the coordinate shift: */
5786 if (adjX
|| adjY
[0] || adjY
[1]) {
5787 if (adjY
[0] != adjY
[1]) {
5788 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5789 * depending on whether inversion is actually going to be applied
5790 * or not, which is determined by testing against the inversion
5791 * state variable used below, which will be either +1 or -1.
5793 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5795 ureg_CMP(ureg
, adj_temp
,
5796 ureg_scalar(wpostrans
, invert
? 2 : 0),
5797 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5798 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5799 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5801 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5802 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5804 wpos_input
= ureg_src(wpos_temp
);
5806 /* MOV wpos_temp, input[wpos]
5808 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5811 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5812 * inversion/identity, or the other way around if we're drawing to an FBO.
5815 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5818 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5820 ureg_scalar(wpostrans
, 0),
5821 ureg_scalar(wpostrans
, 1));
5823 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5826 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5828 ureg_scalar(wpostrans
, 2),
5829 ureg_scalar(wpostrans
, 3));
5832 /* Use wpos_temp as position input from here on:
5834 *wpos
= ureg_src(wpos_temp
);
5839 * Emit fragment position/ooordinate code.
5842 emit_wpos(struct st_context
*st
,
5843 struct st_translate
*t
,
5844 const struct gl_program
*program
,
5845 struct ureg_program
*ureg
,
5846 int wpos_transform_const
)
5848 const struct gl_fragment_program
*fp
=
5849 (const struct gl_fragment_program
*) program
;
5850 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5851 GLfloat adjX
= 0.0f
;
5852 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5853 boolean invert
= FALSE
;
5855 /* Query the pixel center conventions supported by the pipe driver and set
5856 * adjX, adjY to help out if it cannot handle the requested one internally.
5858 * The bias of the y-coordinate depends on whether y-inversion takes place
5859 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5860 * drawing to an FBO (causes additional inversion), and whether the the pipe
5861 * driver origin and the requested origin differ (the latter condition is
5862 * stored in the 'invert' variable).
5864 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5866 * center shift only:
5871 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5872 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5873 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5874 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5876 * inversion and center shift:
5877 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5878 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5879 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5880 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5882 if (fp
->OriginUpperLeft
) {
5883 /* Fragment shader wants origin in upper-left */
5884 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5885 /* the driver supports upper-left origin */
5887 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5888 /* the driver supports lower-left origin, need to invert Y */
5889 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5890 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5897 /* Fragment shader wants origin in lower-left */
5898 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5899 /* the driver supports lower-left origin */
5900 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5901 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5902 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5903 /* the driver supports upper-left origin, need to invert Y */
5909 if (fp
->PixelCenterInteger
) {
5910 /* Fragment shader wants pixel center integer */
5911 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5912 /* the driver supports pixel center integer */
5914 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5915 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5917 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5918 /* the driver supports pixel center half integer, need to bias X,Y */
5927 /* Fragment shader wants pixel center half integer */
5928 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5929 /* the driver supports pixel center half integer */
5931 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5932 /* the driver supports pixel center integer, need to bias X,Y */
5933 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5934 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5935 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5941 /* we invert after adjustment so that we avoid the MOV to temporary,
5942 * and reuse the adjustment ADD instead */
5943 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5947 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5948 * TGSI uses +1 for front, -1 for back.
5949 * This function converts the TGSI value to the GL value. Simply clamping/
5950 * saturating the value to [0,1] does the job.
5953 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5955 struct ureg_program
*ureg
= t
->ureg
;
5956 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5957 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5959 if (ctx
->Const
.NativeIntegers
) {
5960 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5963 /* MOV_SAT face_temp, input[face] */
5964 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5967 /* Use face_temp as face input from here on: */
5968 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5972 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5973 unsigned *array_id
, unsigned *array_size
)
5977 for (i
= 0; i
< count
; i
++) {
5978 struct array_decl
*decl
= &arrays
[i
];
5980 if (attr
== decl
->mesa_index
) {
5981 *array_id
= decl
->array_id
;
5982 *array_size
= decl
->array_size
;
5983 assert(*array_size
);
5991 emit_compute_block_size(const struct gl_program
*program
,
5992 struct ureg_program
*ureg
) {
5993 const struct gl_compute_program
*cp
=
5994 (const struct gl_compute_program
*)program
;
5996 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5998 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6000 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6005 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6006 * \param program the program to translate
6007 * \param numInputs number of input registers used
6008 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6010 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6011 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6013 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6014 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
6015 * \param numOutputs number of output registers used
6016 * \param outputMapping maps Mesa fragment program outputs to TGSI
6018 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6019 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6022 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6024 extern "C" enum pipe_error
6025 st_translate_program(
6026 struct gl_context
*ctx
,
6028 struct ureg_program
*ureg
,
6029 glsl_to_tgsi_visitor
*program
,
6030 const struct gl_program
*proginfo
,
6032 const GLuint inputMapping
[],
6033 const GLuint inputSlotToAttr
[],
6034 const ubyte inputSemanticName
[],
6035 const ubyte inputSemanticIndex
[],
6036 const GLuint interpMode
[],
6037 const GLuint interpLocation
[],
6039 const GLuint outputMapping
[],
6040 const GLuint outputSlotToAttr
[],
6041 const ubyte outputSemanticName
[],
6042 const ubyte outputSemanticIndex
[])
6044 struct st_translate
*t
;
6046 struct gl_program_constants
*frag_const
=
6047 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6048 enum pipe_error ret
= PIPE_OK
;
6050 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6051 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6053 t
= CALLOC_STRUCT(st_translate
);
6055 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6059 t
->procType
= procType
;
6060 t
->inputMapping
= inputMapping
;
6061 t
->outputMapping
= outputMapping
;
6063 t
->num_temp_arrays
= program
->next_array
;
6064 if (t
->num_temp_arrays
)
6065 t
->arrays
= (struct ureg_dst
*)
6066 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
6069 * Declare input attributes.
6072 case PIPE_SHADER_FRAGMENT
:
6073 for (i
= 0; i
< numInputs
; i
++) {
6074 unsigned array_id
= 0;
6075 unsigned array_size
;
6077 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6078 program
->num_input_arrays
, &array_id
, &array_size
)) {
6079 /* We've found an array. Declare it so. */
6080 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6081 inputSemanticName
[i
], inputSemanticIndex
[i
],
6082 interpMode
[i
], 0, interpLocation
[i
],
6083 array_id
, array_size
);
6084 i
+= array_size
- 1;
6087 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6088 inputSemanticName
[i
], inputSemanticIndex
[i
],
6089 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
6093 case PIPE_SHADER_GEOMETRY
:
6094 case PIPE_SHADER_TESS_EVAL
:
6095 case PIPE_SHADER_TESS_CTRL
:
6096 for (i
= 0; i
< numInputs
; i
++) {
6097 unsigned array_id
= 0;
6098 unsigned array_size
;
6100 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6101 program
->num_input_arrays
, &array_id
, &array_size
)) {
6102 /* We've found an array. Declare it so. */
6103 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6104 inputSemanticIndex
[i
],
6105 array_id
, array_size
);
6106 i
+= array_size
- 1;
6109 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6110 inputSemanticIndex
[i
], 0, 1);
6114 case PIPE_SHADER_VERTEX
:
6115 for (i
= 0; i
< numInputs
; i
++) {
6116 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6119 case PIPE_SHADER_COMPUTE
:
6126 * Declare output attributes.
6129 case PIPE_SHADER_FRAGMENT
:
6130 case PIPE_SHADER_COMPUTE
:
6132 case PIPE_SHADER_GEOMETRY
:
6133 case PIPE_SHADER_TESS_EVAL
:
6134 case PIPE_SHADER_TESS_CTRL
:
6135 case PIPE_SHADER_VERTEX
:
6136 for (i
= 0; i
< numOutputs
; i
++) {
6137 unsigned array_id
= 0;
6138 unsigned array_size
;
6140 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
6141 program
->num_output_arrays
, &array_id
, &array_size
)) {
6142 /* We've found an array. Declare it so. */
6143 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
6144 outputSemanticName
[i
],
6145 outputSemanticIndex
[i
],
6146 array_id
, array_size
);
6147 i
+= array_size
- 1;
6150 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6151 outputSemanticName
[i
],
6152 outputSemanticIndex
[i
]);
6160 if (procType
== PIPE_SHADER_FRAGMENT
) {
6161 if (program
->shader
->EarlyFragmentTests
)
6162 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6164 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6165 /* Must do this after setting up t->inputs. */
6166 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6167 program
->wpos_transform_const
);
6170 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6171 emit_face_var(ctx
, t
);
6173 for (i
= 0; i
< numOutputs
; i
++) {
6174 switch (outputSemanticName
[i
]) {
6175 case TGSI_SEMANTIC_POSITION
:
6176 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6177 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6178 outputSemanticIndex
[i
]);
6179 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6181 case TGSI_SEMANTIC_STENCIL
:
6182 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6183 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6184 outputSemanticIndex
[i
]);
6185 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6187 case TGSI_SEMANTIC_COLOR
:
6188 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6189 TGSI_SEMANTIC_COLOR
,
6190 outputSemanticIndex
[i
]);
6192 case TGSI_SEMANTIC_SAMPLEMASK
:
6193 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6194 TGSI_SEMANTIC_SAMPLEMASK
,
6195 outputSemanticIndex
[i
]);
6196 /* TODO: If we ever support more than 32 samples, this will have
6197 * to become an array.
6199 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6202 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6203 ret
= PIPE_ERROR_BAD_INPUT
;
6208 else if (procType
== PIPE_SHADER_VERTEX
) {
6209 for (i
= 0; i
< numOutputs
; i
++) {
6210 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6211 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6213 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6214 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6215 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6220 if (procType
== PIPE_SHADER_COMPUTE
) {
6221 emit_compute_block_size(proginfo
, ureg
);
6224 /* Declare address register.
6226 if (program
->num_address_regs
> 0) {
6227 assert(program
->num_address_regs
<= 3);
6228 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6229 t
->address
[i
] = ureg_DECL_address(ureg
);
6232 /* Declare misc input registers
6235 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6237 for (i
= 0; sysInputs
; i
++) {
6238 if (sysInputs
& (1 << i
)) {
6239 unsigned semName
= _mesa_sysval_to_semantic(i
);
6241 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6243 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6244 semName
== TGSI_SEMANTIC_VERTEXID
) {
6245 /* From Gallium perspective, these system values are always
6246 * integer, and require native integer support. However, if
6247 * native integer is supported on the vertex stage but not the
6248 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6249 * assumes these system values are floats. To resolve the
6250 * inconsistency, we insert a U2F.
6252 struct st_context
*st
= st_context(ctx
);
6253 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6254 assert(procType
== PIPE_SHADER_VERTEX
);
6255 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6257 if (!ctx
->Const
.NativeIntegers
) {
6258 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6259 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6260 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6264 if (procType
== PIPE_SHADER_FRAGMENT
&&
6265 semName
== TGSI_SEMANTIC_POSITION
)
6266 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6267 program
->wpos_transform_const
);
6269 sysInputs
&= ~(1 << i
);
6274 t
->array_sizes
= program
->array_sizes
;
6275 t
->input_arrays
= program
->input_arrays
;
6276 t
->output_arrays
= program
->output_arrays
;
6278 /* Emit constants and uniforms. TGSI uses a single index space for these,
6279 * so we put all the translated regs in t->constants.
6281 if (proginfo
->Parameters
) {
6282 t
->constants
= (struct ureg_src
*)
6283 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6284 if (t
->constants
== NULL
) {
6285 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6288 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6290 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6291 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6292 case PROGRAM_STATE_VAR
:
6293 case PROGRAM_UNIFORM
:
6294 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6297 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6298 * addressing of the const buffer.
6299 * FIXME: Be smarter and recognize param arrays:
6300 * indirect addressing is only valid within the referenced
6303 case PROGRAM_CONSTANT
:
6304 if (program
->indirect_addr_consts
)
6305 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6307 t
->constants
[i
] = emit_immediate(t
,
6308 proginfo
->Parameters
->ParameterValues
[i
],
6309 proginfo
->Parameters
->Parameters
[i
].DataType
,
6318 if (program
->shader
) {
6319 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6321 for (i
= 0; i
< num_ubos
; i
++) {
6322 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6323 unsigned num_const_vecs
= (size
+ 15) / 16;
6324 unsigned first
, last
;
6325 assert(num_const_vecs
> 0);
6327 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6328 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6332 /* Emit immediate values.
6334 t
->immediates
= (struct ureg_src
*)
6335 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6336 if (t
->immediates
== NULL
) {
6337 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6340 t
->num_immediates
= program
->num_immediates
;
6343 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6344 assert(i
< program
->num_immediates
);
6345 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6347 assert(i
== program
->num_immediates
);
6349 /* texture samplers */
6350 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6351 if (program
->samplers_used
& (1u << i
)) {
6354 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6356 switch (program
->sampler_types
[i
]) {
6358 type
= TGSI_RETURN_TYPE_SINT
;
6360 case GLSL_TYPE_UINT
:
6361 type
= TGSI_RETURN_TYPE_UINT
;
6363 case GLSL_TYPE_FLOAT
:
6364 type
= TGSI_RETURN_TYPE_FLOAT
;
6367 unreachable("not reached");
6370 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6371 type
, type
, type
, type
);
6375 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6376 if (program
->buffers_used
& (1 << i
)) {
6377 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6381 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6383 if (program
->buffers_used
& (1 << i
)) {
6384 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6388 if (program
->use_shared_memory
)
6389 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6391 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6392 if (program
->images_used
& (1 << i
)) {
6393 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6394 program
->image_targets
[i
],
6395 program
->image_formats
[i
],
6400 /* Emit each instruction in turn:
6402 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6403 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6404 compile_tgsi_instruction(t
, inst
);
6407 /* Fix up all emitted labels:
6409 for (i
= 0; i
< t
->labels_count
; i
++) {
6410 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6411 t
->insn
[t
->labels
[i
].branch_target
]);
6414 /* Set the next shader stage hint for VS and TES. */
6416 case PIPE_SHADER_VERTEX
:
6417 case PIPE_SHADER_TESS_EVAL
:
6418 if (program
->shader_program
->SeparateShader
)
6421 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6422 if (program
->shader_program
->_LinkedShaders
[i
]) {
6426 case MESA_SHADER_TESS_CTRL
:
6427 next
= PIPE_SHADER_TESS_CTRL
;
6429 case MESA_SHADER_TESS_EVAL
:
6430 next
= PIPE_SHADER_TESS_EVAL
;
6432 case MESA_SHADER_GEOMETRY
:
6433 next
= PIPE_SHADER_GEOMETRY
;
6435 case MESA_SHADER_FRAGMENT
:
6436 next
= PIPE_SHADER_FRAGMENT
;
6443 ureg_set_next_shader_processor(ureg
, next
);
6457 t
->num_constants
= 0;
6458 free(t
->immediates
);
6459 t
->num_immediates
= 0;
6462 debug_printf("%s: translate error flag set\n", __func__
);
6470 /* ----------------------------- End TGSI code ------------------------------ */
6474 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6475 * generating Mesa IR.
6477 static struct gl_program
*
6478 get_mesa_program(struct gl_context
*ctx
,
6479 struct gl_shader_program
*shader_program
,
6480 struct gl_shader
*shader
)
6482 glsl_to_tgsi_visitor
* v
;
6483 struct gl_program
*prog
;
6484 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6486 struct gl_shader_compiler_options
*options
=
6487 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
6488 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6489 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6491 validate_ir_tree(shader
->ir
);
6493 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6496 prog
->Parameters
= _mesa_new_parameter_list();
6497 v
= new glsl_to_tgsi_visitor();
6500 v
->shader_program
= shader_program
;
6502 v
->options
= options
;
6503 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6504 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6506 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6507 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6508 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6509 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6511 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6512 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6515 /* Remove reads from output registers. */
6516 lower_output_reads(shader
->Stage
, shader
->ir
);
6518 /* Emit intermediate IR for main(). */
6519 visit_exec_list(shader
->ir
, v
);
6521 /* Now emit bodies for any functions that were used. */
6523 progress
= GL_FALSE
;
6525 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6526 if (!entry
->bgn_inst
) {
6527 v
->current_function
= entry
;
6529 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6530 entry
->bgn_inst
->function
= entry
;
6532 visit_exec_list(&entry
->sig
->body
, v
);
6534 glsl_to_tgsi_instruction
*last
;
6535 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6536 if (last
->op
!= TGSI_OPCODE_RET
)
6537 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6539 glsl_to_tgsi_instruction
*end
;
6540 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6541 end
->function
= entry
;
6549 /* Print out some information (for debugging purposes) used by the
6550 * optimization passes. */
6553 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6554 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6555 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6556 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6558 for (i
= 0; i
< v
->next_temp
; i
++) {
6559 first_writes
[i
] = -1;
6560 first_reads
[i
] = -1;
6561 last_writes
[i
] = -1;
6564 v
->get_first_temp_read(first_reads
);
6565 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6566 v
->get_last_temp_write(last_writes
);
6567 for (i
= 0; i
< v
->next_temp
; i
++)
6568 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6572 ralloc_free(first_writes
);
6573 ralloc_free(first_reads
);
6574 ralloc_free(last_writes
);
6575 ralloc_free(last_reads
);
6579 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6582 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
6583 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
6584 v
->copy_propagate();
6586 while (v
->eliminate_dead_code());
6588 v
->merge_two_dsts();
6589 v
->merge_registers();
6590 v
->renumber_registers();
6592 /* Write the END instruction. */
6593 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6595 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6597 _mesa_log("GLSL IR for linked %s program %d:\n",
6598 _mesa_shader_stage_to_string(shader
->Stage
),
6599 shader_program
->Name
);
6600 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6604 prog
->Instructions
= NULL
;
6605 prog
->NumInstructions
= 0;
6607 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6608 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
6609 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
6610 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
6611 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
6612 count_resources(v
, prog
);
6614 /* The GLSL IR won't be needed anymore. */
6615 ralloc_free(shader
->ir
);
6618 /* This must be done before the uniform storage is associated. */
6619 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
6620 (prog
->InputsRead
& VARYING_BIT_POS
||
6621 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6622 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6623 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6626 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6627 wposTransformState
);
6630 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6632 /* Avoid reallocation of the program parameter list, because the uniform
6633 * storage is only associated with the original parameter list.
6634 * This should be enough for Bitmap and DrawPixels constants.
6636 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6638 /* This has to be done last. Any operation the can cause
6639 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6640 * program constant) has to happen before creating this linkage.
6642 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6643 if (!shader_program
->LinkStatus
) {
6644 free_glsl_to_tgsi_visitor(v
);
6648 struct st_vertex_program
*stvp
;
6649 struct st_fragment_program
*stfp
;
6650 struct st_geometry_program
*stgp
;
6651 struct st_tessctrl_program
*sttcp
;
6652 struct st_tesseval_program
*sttep
;
6653 struct st_compute_program
*stcp
;
6655 switch (shader
->Type
) {
6656 case GL_VERTEX_SHADER
:
6657 stvp
= (struct st_vertex_program
*)prog
;
6658 stvp
->glsl_to_tgsi
= v
;
6660 case GL_FRAGMENT_SHADER
:
6661 stfp
= (struct st_fragment_program
*)prog
;
6662 stfp
->glsl_to_tgsi
= v
;
6664 case GL_GEOMETRY_SHADER
:
6665 stgp
= (struct st_geometry_program
*)prog
;
6666 stgp
->glsl_to_tgsi
= v
;
6668 case GL_TESS_CONTROL_SHADER
:
6669 sttcp
= (struct st_tessctrl_program
*)prog
;
6670 sttcp
->glsl_to_tgsi
= v
;
6672 case GL_TESS_EVALUATION_SHADER
:
6673 sttep
= (struct st_tesseval_program
*)prog
;
6674 sttep
->glsl_to_tgsi
= v
;
6676 case GL_COMPUTE_SHADER
:
6677 stcp
= (struct st_compute_program
*)prog
;
6678 stcp
->glsl_to_tgsi
= v
;
6681 assert(!"should not be reached");
6691 st_dump_program_for_shader_db(struct gl_context
*ctx
,
6692 struct gl_shader_program
*prog
)
6694 /* Dump only successfully compiled and linked shaders to the specified
6695 * file. This is for shader-db.
6697 * These options allow some pre-processing of shaders while dumping,
6698 * because some apps have ill-formed shaders.
6700 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
6701 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
6703 if (dump_filename
&& prog
->Name
!= 0) {
6704 FILE *f
= fopen(dump_filename
, "a");
6707 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
6708 const struct gl_shader
*sh
= prog
->Shaders
[i
];
6710 bool skip_version
= false;
6715 source
= sh
->Source
;
6717 /* This string mustn't be changed. shader-db uses it to find
6718 * where the shader begins.
6720 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
6721 _mesa_shader_stage_to_string(sh
->Stage
),
6724 /* Dump the forced version if set. */
6725 if (ctx
->Const
.ForceGLSLVersion
) {
6726 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
6727 skip_version
= true;
6730 /* Insert directives (optional). */
6731 if (insert_directives
) {
6732 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
6733 fprintf(f
, "#version %i\n", prog
->Version
);
6734 fprintf(f
, "%s\n", insert_directives
);
6735 skip_version
= true;
6738 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
6739 const char *next_line
= strstr(source
, "\n");
6742 source
= next_line
+ 1;
6747 fprintf(f
, "%s", source
);
6757 * Called via ctx->Driver.LinkShader()
6758 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6759 * with code lowering and other optimizations.
6762 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6764 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6765 assert(prog
->LinkStatus
);
6767 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6768 if (prog
->_LinkedShaders
[i
] == NULL
)
6772 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6773 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6774 const struct gl_shader_compiler_options
*options
=
6775 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6776 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6777 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6778 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6779 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6780 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6782 /* If there are forms of indirect addressing that the driver
6783 * cannot handle, perform the lowering pass.
6785 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6786 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6787 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6788 options
->EmitNoIndirectInput
,
6789 options
->EmitNoIndirectOutput
,
6790 options
->EmitNoIndirectTemp
,
6791 options
->EmitNoIndirectUniform
);
6794 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6795 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6796 LOWER_UNPACK_SNORM_2x16
|
6797 LOWER_PACK_UNORM_2x16
|
6798 LOWER_UNPACK_UNORM_2x16
|
6799 LOWER_PACK_SNORM_4x8
|
6800 LOWER_UNPACK_SNORM_4x8
|
6801 LOWER_UNPACK_UNORM_4x8
|
6802 LOWER_PACK_UNORM_4x8
;
6804 if (ctx
->Extensions
.ARB_gpu_shader5
)
6805 lower_inst
|= LOWER_PACK_USE_BFI
|
6807 if (!ctx
->st
->has_half_float_packing
)
6808 lower_inst
|= LOWER_PACK_HALF_2x16
|
6809 LOWER_UNPACK_HALF_2x16
;
6811 lower_packing_builtins(ir
, lower_inst
);
6814 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6815 lower_offset_arrays(ir
);
6816 do_mat_op_to_vec(ir
);
6817 lower_instructions(ir
,
6823 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6826 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6827 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6828 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6829 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6831 do_vec_index_to_cond_assign(ir
);
6832 lower_vector_insert(ir
, true);
6833 lower_quadop_vector(ir
, false);
6835 if (options
->MaxIfDepth
== 0) {
6842 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6844 progress
= do_common_optimization(ir
, true, true, options
,
6845 ctx
->Const
.NativeIntegers
)
6848 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6852 validate_ir_tree(ir
);
6855 build_program_resource_list(ctx
, prog
);
6857 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6858 struct gl_program
*linked_prog
;
6860 if (prog
->_LinkedShaders
[i
] == NULL
)
6863 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6866 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6868 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6869 _mesa_shader_stage_to_program(i
),
6871 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6873 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6878 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6881 st_dump_program_for_shader_db(ctx
, prog
);
6886 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6887 const GLuint outputMapping
[],
6888 struct pipe_stream_output_info
*so
)
6891 struct gl_transform_feedback_info
*info
=
6892 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6894 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6895 so
->output
[i
].register_index
=
6896 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6897 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6898 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6899 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6900 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6901 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6904 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6905 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6907 so
->num_outputs
= info
->NumOutputs
;