2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static int swizzle_for_size(int size
);
71 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
73 unsigned num_elements
= 4;
76 type
= type
->without_array();
77 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
78 num_elements
= type
->vector_elements
;
81 int swizzle
= swizzle_for_size(num_elements
);
82 assert(num_elements
+ component
<= 4);
84 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
89 * This struct is a corresponding struct to TGSI ureg_src.
93 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
94 int component
= 0, unsigned array_id
= 0)
96 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
99 this->swizzle
= swizzle_for_type(type
, component
);
102 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
103 this->reladdr
= NULL
;
104 this->reladdr2
= NULL
;
105 this->has_index2
= false;
106 this->double_reg2
= false;
107 this->array_id
= array_id
;
108 this->is_double_vertex_input
= false;
111 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
113 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
118 this->swizzle
= SWIZZLE_XYZW
;
120 this->reladdr
= NULL
;
121 this->reladdr2
= NULL
;
122 this->has_index2
= false;
123 this->double_reg2
= false;
125 this->is_double_vertex_input
= false;
128 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
130 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
134 this->index2D
= index2D
;
135 this->swizzle
= SWIZZLE_XYZW
;
137 this->reladdr
= NULL
;
138 this->reladdr2
= NULL
;
139 this->has_index2
= false;
140 this->double_reg2
= false;
142 this->is_double_vertex_input
= false;
147 this->type
= GLSL_TYPE_ERROR
;
148 this->file
= PROGRAM_UNDEFINED
;
153 this->reladdr
= NULL
;
154 this->reladdr2
= NULL
;
155 this->has_index2
= false;
156 this->double_reg2
= false;
158 this->is_double_vertex_input
= false;
161 explicit st_src_reg(st_dst_reg reg
);
163 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
165 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
166 int negate
:4; /**< NEGATE_XYZW mask from mesa */
167 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
168 unsigned has_index2
:1;
169 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
171 * Is this the second half of a double register pair?
172 * currently used for input mapping only.
174 unsigned double_reg2
:1;
175 unsigned is_double_vertex_input
:1;
176 unsigned array_id
:10;
178 /** Register index should be offset by the integer in this reg. */
180 st_src_reg
*reladdr2
;
185 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
187 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
191 this->writemask
= writemask
;
192 this->reladdr
= NULL
;
193 this->reladdr2
= NULL
;
194 this->has_index2
= false;
199 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
201 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
205 this->writemask
= writemask
;
206 this->reladdr
= NULL
;
207 this->reladdr2
= NULL
;
208 this->has_index2
= false;
215 this->type
= GLSL_TYPE_ERROR
;
216 this->file
= PROGRAM_UNDEFINED
;
220 this->reladdr
= NULL
;
221 this->reladdr2
= NULL
;
222 this->has_index2
= false;
226 explicit st_dst_reg(st_src_reg reg
);
228 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
230 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
231 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
232 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
233 unsigned has_index2
:1;
234 unsigned array_id
:10;
236 /** Register index should be offset by the integer in this reg. */
238 st_src_reg
*reladdr2
;
241 st_src_reg::st_src_reg(st_dst_reg reg
)
243 this->type
= reg
.type
;
244 this->file
= reg
.file
;
245 this->index
= reg
.index
;
246 this->swizzle
= SWIZZLE_XYZW
;
248 this->reladdr
= reg
.reladdr
;
249 this->index2D
= reg
.index2D
;
250 this->reladdr2
= reg
.reladdr2
;
251 this->has_index2
= reg
.has_index2
;
252 this->double_reg2
= false;
253 this->array_id
= reg
.array_id
;
254 this->is_double_vertex_input
= false;
257 st_dst_reg::st_dst_reg(st_src_reg reg
)
259 this->type
= reg
.type
;
260 this->file
= reg
.file
;
261 this->index
= reg
.index
;
262 this->writemask
= WRITEMASK_XYZW
;
263 this->reladdr
= reg
.reladdr
;
264 this->index2D
= reg
.index2D
;
265 this->reladdr2
= reg
.reladdr2
;
266 this->has_index2
= reg
.has_index2
;
267 this->array_id
= reg
.array_id
;
270 class glsl_to_tgsi_instruction
: public exec_node
{
272 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
276 st_src_reg resource
; /**< sampler or buffer register */
277 st_src_reg
*tex_offsets
;
279 /** Pointer to the ir source this tree came from for debugging */
282 unsigned op
:8; /**< TGSI opcode */
284 unsigned is_64bit_expanded
:1;
285 unsigned sampler_base
:5;
286 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
287 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
288 glsl_base_type tex_type
:4;
289 unsigned tex_shadow
:1;
290 unsigned image_format
:9;
291 unsigned tex_offset_num_offset
:3;
292 unsigned dead_mask
:4; /**< Used in dead code elimination */
293 unsigned buffer_access
:3; /**< buffer access type */
295 const struct tgsi_opcode_info
*info
;
298 class variable_storage
: public exec_node
{
300 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
301 unsigned array_id
= 0)
302 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
304 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
307 gl_register_file file
;
310 /* Explicit component location. This is given in terms of the GLSL-style
311 * swizzles where each double is a single component, i.e. for 64-bit types
312 * it can only be 0 or 1.
315 ir_variable
*var
; /* variable that maps to this, if any */
319 class immediate_storage
: public exec_node
{
321 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
323 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
324 this->size32
= size32
;
328 /* doubles are stored across 2 gl_constant_values */
329 gl_constant_value values
[4];
330 int size32
; /**< Number of 32-bit components (1-4) */
331 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
334 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
335 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
339 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
342 enum glsl_interp_mode interp
;
343 enum glsl_base_type base_type
;
344 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
347 static struct inout_decl
*
348 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
350 assert(array_id
!= 0);
352 for (unsigned i
= 0; i
< count
; i
++) {
353 struct inout_decl
*decl
= &decls
[i
];
355 if (array_id
== decl
->array_id
) {
363 static enum glsl_base_type
364 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
367 return GLSL_TYPE_ERROR
;
368 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
370 return decl
->base_type
;
371 return GLSL_TYPE_ERROR
;
374 struct rename_reg_pair
{
379 struct glsl_to_tgsi_visitor
: public ir_visitor
{
381 glsl_to_tgsi_visitor();
382 ~glsl_to_tgsi_visitor();
384 struct gl_context
*ctx
;
385 struct gl_program
*prog
;
386 struct gl_shader_program
*shader_program
;
387 struct gl_linked_shader
*shader
;
388 struct gl_shader_compiler_options
*options
;
392 unsigned *array_sizes
;
393 unsigned max_num_arrays
;
396 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
398 unsigned num_input_arrays
;
399 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
400 unsigned num_outputs
;
401 unsigned num_output_arrays
;
403 int num_address_regs
;
404 uint32_t samplers_used
;
405 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
406 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
409 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
410 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
411 bool indirect_addr_consts
;
412 int wpos_transform_const
;
415 bool native_integers
;
418 bool use_shared_memory
;
420 variable_storage
*find_variable_storage(ir_variable
*var
);
422 int add_constant(gl_register_file file
, gl_constant_value values
[8],
423 int size
, int datatype
, uint16_t *swizzle_out
);
425 st_src_reg
get_temp(const glsl_type
*type
);
426 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
428 st_src_reg
st_src_reg_for_double(double val
);
429 st_src_reg
st_src_reg_for_float(float val
);
430 st_src_reg
st_src_reg_for_int(int val
);
431 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
434 * \name Visit methods
436 * As typical for the visitor pattern, there must be one \c visit method for
437 * each concrete subclass of \c ir_instruction. Virtual base classes within
438 * the hierarchy should not have \c visit methods.
441 virtual void visit(ir_variable
*);
442 virtual void visit(ir_loop
*);
443 virtual void visit(ir_loop_jump
*);
444 virtual void visit(ir_function_signature
*);
445 virtual void visit(ir_function
*);
446 virtual void visit(ir_expression
*);
447 virtual void visit(ir_swizzle
*);
448 virtual void visit(ir_dereference_variable
*);
449 virtual void visit(ir_dereference_array
*);
450 virtual void visit(ir_dereference_record
*);
451 virtual void visit(ir_assignment
*);
452 virtual void visit(ir_constant
*);
453 virtual void visit(ir_call
*);
454 virtual void visit(ir_return
*);
455 virtual void visit(ir_discard
*);
456 virtual void visit(ir_texture
*);
457 virtual void visit(ir_if
*);
458 virtual void visit(ir_emit_vertex
*);
459 virtual void visit(ir_end_primitive
*);
460 virtual void visit(ir_barrier
*);
463 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
465 void visit_atomic_counter_intrinsic(ir_call
*);
466 void visit_ssbo_intrinsic(ir_call
*);
467 void visit_membar_intrinsic(ir_call
*);
468 void visit_shared_intrinsic(ir_call
*);
469 void visit_image_intrinsic(ir_call
*);
473 /** List of variable_storage */
476 /** List of immediate_storage */
477 exec_list immediates
;
478 unsigned num_immediates
;
480 /** List of glsl_to_tgsi_instruction */
481 exec_list instructions
;
483 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
484 st_dst_reg dst
= undef_dst
,
485 st_src_reg src0
= undef_src
,
486 st_src_reg src1
= undef_src
,
487 st_src_reg src2
= undef_src
,
488 st_src_reg src3
= undef_src
);
490 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
491 st_dst_reg dst
, st_dst_reg dst1
,
492 st_src_reg src0
= undef_src
,
493 st_src_reg src1
= undef_src
,
494 st_src_reg src2
= undef_src
,
495 st_src_reg src3
= undef_src
);
497 unsigned get_opcode(unsigned op
,
499 st_src_reg src0
, st_src_reg src1
);
502 * Emit the correct dot-product instruction for the type of arguments
504 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
510 void emit_scalar(ir_instruction
*ir
, unsigned op
,
511 st_dst_reg dst
, st_src_reg src0
);
513 void emit_scalar(ir_instruction
*ir
, unsigned op
,
514 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
516 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
518 void get_deref_offsets(ir_dereference
*ir
,
519 unsigned *array_size
,
524 void calc_deref_offsets(ir_dereference
*tail
,
525 unsigned *array_elements
,
527 st_src_reg
*indirect
,
529 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
531 bool try_emit_mad(ir_expression
*ir
,
533 bool try_emit_mad_for_and_not(ir_expression
*ir
,
536 void emit_swz(ir_expression
*ir
);
538 bool process_move_condition(ir_rvalue
*ir
);
540 void simplify_cmp(void);
542 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
543 void get_first_temp_read(int *first_reads
);
544 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
545 void get_last_temp_write(int *last_writes
);
547 void copy_propagate(void);
548 int eliminate_dead_code(void);
550 void merge_two_dsts(void);
551 void merge_registers(void);
552 void renumber_registers(void);
554 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
555 st_dst_reg
*l
, st_src_reg
*r
,
556 st_src_reg
*cond
, bool cond_swap
);
561 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
562 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
563 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
566 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
569 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
573 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
576 prog
->data
->LinkStatus
= GL_FALSE
;
580 swizzle_for_size(int size
)
582 static const int size_swizzles
[4] = {
583 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
584 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
585 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
586 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
589 assert((size
>= 1) && (size
<= 4));
590 return size_swizzles
[size
- 1];
594 is_resource_instruction(unsigned opcode
)
597 case TGSI_OPCODE_RESQ
:
598 case TGSI_OPCODE_LOAD
:
599 case TGSI_OPCODE_ATOMUADD
:
600 case TGSI_OPCODE_ATOMXCHG
:
601 case TGSI_OPCODE_ATOMCAS
:
602 case TGSI_OPCODE_ATOMAND
:
603 case TGSI_OPCODE_ATOMOR
:
604 case TGSI_OPCODE_ATOMXOR
:
605 case TGSI_OPCODE_ATOMUMIN
:
606 case TGSI_OPCODE_ATOMUMAX
:
607 case TGSI_OPCODE_ATOMIMIN
:
608 case TGSI_OPCODE_ATOMIMAX
:
616 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
618 return op
->info
->num_dst
;
622 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
624 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
625 op
->info
->num_src
- 1 : op
->info
->num_src
;
628 glsl_to_tgsi_instruction
*
629 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
630 st_dst_reg dst
, st_dst_reg dst1
,
631 st_src_reg src0
, st_src_reg src1
,
632 st_src_reg src2
, st_src_reg src3
)
634 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
635 int num_reladdr
= 0, i
, j
;
636 bool dst_is_64bit
[2];
638 op
= get_opcode(op
, dst
, src0
, src1
);
640 /* If we have to do relative addressing, we want to load the ARL
641 * reg directly for one of the regs, and preload the other reladdr
642 * sources into temps.
644 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
645 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
646 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
647 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
648 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
649 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
651 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
652 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
653 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
654 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
656 if (dst
.reladdr
|| dst
.reladdr2
) {
658 emit_arl(ir
, address_reg
, *dst
.reladdr
);
660 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
664 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
667 assert(num_reladdr
== 0);
669 /* inst->op has only 8 bits. */
670 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
673 inst
->info
= tgsi_get_opcode_info(op
);
680 inst
->is_64bit_expanded
= false;
683 inst
->tex_offsets
= NULL
;
684 inst
->tex_offset_num_offset
= 0;
686 inst
->tex_shadow
= 0;
687 /* default to float, for paths where this is not initialized
688 * (since 0==UINT which is likely wrong):
690 inst
->tex_type
= GLSL_TYPE_FLOAT
;
692 /* Update indirect addressing status used by TGSI */
693 if (dst
.reladdr
|| dst
.reladdr2
) {
695 case PROGRAM_STATE_VAR
:
696 case PROGRAM_CONSTANT
:
697 case PROGRAM_UNIFORM
:
698 this->indirect_addr_consts
= true;
700 case PROGRAM_IMMEDIATE
:
701 assert(!"immediates should not have indirect addressing");
708 for (i
= 0; i
< 4; i
++) {
709 if(inst
->src
[i
].reladdr
) {
710 switch(inst
->src
[i
].file
) {
711 case PROGRAM_STATE_VAR
:
712 case PROGRAM_CONSTANT
:
713 case PROGRAM_UNIFORM
:
714 this->indirect_addr_consts
= true;
716 case PROGRAM_IMMEDIATE
:
717 assert(!"immediates should not have indirect addressing");
727 * This section contains the double processing.
728 * GLSL just represents doubles as single channel values,
729 * however most HW and TGSI represent doubles as pairs of register channels.
731 * so we have to fixup destination writemask/index and src swizzle/indexes.
732 * dest writemasks need to translate from single channel write mask
733 * to a dual-channel writemask, but also need to modify the index,
734 * if we are touching the Z,W fields in the pre-translated writemask.
736 * src channels have similiar index modifications along with swizzle
737 * changes to we pick the XY, ZW pairs from the correct index.
739 * GLSL [0].x -> TGSI [0].xy
740 * GLSL [0].y -> TGSI [0].zw
741 * GLSL [0].z -> TGSI [1].xy
742 * GLSL [0].w -> TGSI [1].zw
744 for (j
= 0; j
< 2; j
++) {
745 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
746 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
747 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
748 if (glsl_base_type_is_64bit(type
))
749 dst_is_64bit
[j
] = true;
753 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
754 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
755 glsl_to_tgsi_instruction
*dinst
= NULL
;
756 int initial_src_swz
[4], initial_src_idx
[4];
757 int initial_dst_idx
[2], initial_dst_writemask
[2];
758 /* select the writemask for dst0 or dst1 */
759 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
761 /* copy out the writemask, index and swizzles for all src/dsts. */
762 for (j
= 0; j
< 2; j
++) {
763 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
764 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
767 for (j
= 0; j
< 4; j
++) {
768 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
769 initial_src_idx
[j
] = inst
->src
[j
].index
;
773 * scan all the components in the dst writemask
774 * generate an instruction for each of them if required.
779 int i
= u_bit_scan(&writemask
);
781 /* before emitting the instruction, see if we have to adjust load / store
783 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
784 addr
.file
== PROGRAM_UNDEFINED
) {
785 /* We have to advance the buffer address by 16 */
786 addr
= get_temp(glsl_type::uint_type
);
787 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
788 inst
->src
[0], st_src_reg_for_int(16));
791 /* first time use previous instruction */
795 /* create a new instructions for subsequent attempts */
796 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
801 this->instructions
.push_tail(dinst
);
802 dinst
->is_64bit_expanded
= true;
804 /* modify the destination if we are splitting */
805 for (j
= 0; j
< 2; j
++) {
806 if (dst_is_64bit
[j
]) {
807 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
808 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
810 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
811 dinst
->src
[0] = addr
;
812 if (dinst
->op
!= TGSI_OPCODE_STORE
)
813 dinst
->dst
[j
].index
++;
816 /* if we aren't writing to a double, just get the bit of the initial writemask
818 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
822 /* modify the src registers */
823 for (j
= 0; j
< 4; j
++) {
824 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
826 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
827 dinst
->src
[j
].index
= initial_src_idx
[j
];
829 dinst
->src
[j
].double_reg2
= true;
830 dinst
->src
[j
].index
++;
834 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
836 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
839 /* some opcodes are special case in what they use as sources
840 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
841 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
842 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
843 op
== TGSI_OPCODE_DLDEXP
||
844 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
845 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
852 this->instructions
.push_tail(inst
);
859 glsl_to_tgsi_instruction
*
860 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
862 st_src_reg src0
, st_src_reg src1
,
863 st_src_reg src2
, st_src_reg src3
)
865 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
869 * Determines whether to use an integer, unsigned integer, or float opcode
870 * based on the operands and input opcode, then emits the result.
873 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
875 st_src_reg src0
, st_src_reg src1
)
877 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
879 if (op
== TGSI_OPCODE_MOV
)
882 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
883 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
884 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
885 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
887 if (is_resource_instruction(op
))
889 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
890 type
= GLSL_TYPE_DOUBLE
;
891 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
892 type
= GLSL_TYPE_FLOAT
;
893 else if (native_integers
)
894 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
896 #define case5(c, f, i, u, d) \
897 case TGSI_OPCODE_##c: \
898 if (type == GLSL_TYPE_DOUBLE) \
899 op = TGSI_OPCODE_##d; \
900 else if (type == GLSL_TYPE_INT) \
901 op = TGSI_OPCODE_##i; \
902 else if (type == GLSL_TYPE_UINT) \
903 op = TGSI_OPCODE_##u; \
905 op = TGSI_OPCODE_##f; \
908 #define case4(c, f, i, u) \
909 case TGSI_OPCODE_##c: \
910 if (type == GLSL_TYPE_INT) \
911 op = TGSI_OPCODE_##i; \
912 else if (type == GLSL_TYPE_UINT) \
913 op = TGSI_OPCODE_##u; \
915 op = TGSI_OPCODE_##f; \
918 #define case3(f, i, u) case4(f, f, i, u)
919 #define case4d(f, i, u, d) case5(f, f, i, u, d)
920 #define case3fid(f, i, d) case5(f, f, i, i, d)
921 #define case2fi(f, i) case4(f, f, i, i)
922 #define case2iu(i, u) case4(i, LAST, i, u)
924 #define casecomp(c, f, i, u, d) \
925 case TGSI_OPCODE_##c: \
926 if (type == GLSL_TYPE_DOUBLE) \
927 op = TGSI_OPCODE_##d; \
928 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
929 op = TGSI_OPCODE_##i; \
930 else if (type == GLSL_TYPE_UINT) \
931 op = TGSI_OPCODE_##u; \
932 else if (native_integers) \
933 op = TGSI_OPCODE_##f; \
935 op = TGSI_OPCODE_##c; \
939 case3fid(ADD
, UADD
, DADD
);
940 case3fid(MUL
, UMUL
, DMUL
);
941 case3fid(MAD
, UMAD
, DMAD
);
942 case3fid(FMA
, UMAD
, DFMA
);
943 case3(DIV
, IDIV
, UDIV
);
944 case4d(MAX
, IMAX
, UMAX
, DMAX
);
945 case4d(MIN
, IMIN
, UMIN
, DMIN
);
948 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
949 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
950 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
951 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
955 case3fid(SSG
, ISSG
, DSSG
);
956 case3fid(ABS
, IABS
, DABS
);
960 case2iu(IMUL_HI
, UMUL_HI
);
962 case3fid(SQRT
, SQRT
, DSQRT
);
964 case3fid(RCP
, RCP
, DRCP
);
965 case3fid(RSQ
, RSQ
, DRSQ
);
967 case3fid(FRC
, FRC
, DFRAC
);
968 case3fid(TRUNC
, TRUNC
, DTRUNC
);
969 case3fid(CEIL
, CEIL
, DCEIL
);
970 case3fid(FLR
, FLR
, DFLR
);
971 case3fid(ROUND
, ROUND
, DROUND
);
973 case2iu(ATOMIMAX
, ATOMUMAX
);
974 case2iu(ATOMIMIN
, ATOMUMIN
);
979 assert(op
!= TGSI_OPCODE_LAST
);
983 glsl_to_tgsi_instruction
*
984 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
985 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
988 static const unsigned dot_opcodes
[] = {
989 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
992 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
996 * Emits TGSI scalar opcodes to produce unique answers across channels.
998 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
999 * channel determines the result across all channels. So to do a vec4
1000 * of this operation, we want to emit a scalar per source channel used
1001 * to produce dest channels.
1004 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1006 st_src_reg orig_src0
, st_src_reg orig_src1
)
1009 int done_mask
= ~dst
.writemask
;
1011 /* TGSI RCP is a scalar operation splatting results to all channels,
1012 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1015 for (i
= 0; i
< 4; i
++) {
1016 GLuint this_mask
= (1 << i
);
1017 st_src_reg src0
= orig_src0
;
1018 st_src_reg src1
= orig_src1
;
1020 if (done_mask
& this_mask
)
1023 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1024 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1025 for (j
= i
+ 1; j
< 4; j
++) {
1026 /* If there is another enabled component in the destination that is
1027 * derived from the same inputs, generate its value on this pass as
1030 if (!(done_mask
& (1 << j
)) &&
1031 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1032 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1033 this_mask
|= (1 << j
);
1036 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1037 src0_swiz
, src0_swiz
);
1038 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1039 src1_swiz
, src1_swiz
);
1041 dst
.writemask
= this_mask
;
1042 emit_asm(ir
, op
, dst
, src0
, src1
);
1043 done_mask
|= this_mask
;
1048 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1049 st_dst_reg dst
, st_src_reg src0
)
1051 st_src_reg undef
= undef_src
;
1053 undef
.swizzle
= SWIZZLE_XXXX
;
1055 emit_scalar(ir
, op
, dst
, src0
, undef
);
1059 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1060 st_dst_reg dst
, st_src_reg src0
)
1062 int op
= TGSI_OPCODE_ARL
;
1064 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1065 op
= TGSI_OPCODE_UARL
;
1067 assert(dst
.file
== PROGRAM_ADDRESS
);
1068 if (dst
.index
>= this->num_address_regs
)
1069 this->num_address_regs
= dst
.index
+ 1;
1071 emit_asm(NULL
, op
, dst
, src0
);
1075 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1076 gl_constant_value values
[8], int size
, int datatype
,
1077 uint16_t *swizzle_out
)
1079 if (file
== PROGRAM_CONSTANT
) {
1080 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1081 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1082 size
, datatype
, &swizzle
);
1084 *swizzle_out
= swizzle
;
1088 assert(file
== PROGRAM_IMMEDIATE
);
1091 immediate_storage
*entry
;
1092 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1095 /* Search immediate storage to see if we already have an identical
1096 * immediate that we can use instead of adding a duplicate entry.
1098 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1099 immediate_storage
*tmp
= entry
;
1101 for (i
= 0; i
* 4 < size32
; i
++) {
1102 int slot_size
= MIN2(size32
- (i
* 4), 4);
1103 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1105 if (memcmp(tmp
->values
, &values
[i
* 4],
1106 slot_size
* sizeof(gl_constant_value
)))
1109 /* Everything matches, keep going until the full size is matched */
1110 tmp
= (immediate_storage
*)tmp
->next
;
1113 /* The full value matched */
1114 if (i
* 4 >= size32
)
1120 for (i
= 0; i
* 4 < size32
; i
++) {
1121 int slot_size
= MIN2(size32
- (i
* 4), 4);
1122 /* Add this immediate to the list. */
1123 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1124 this->immediates
.push_tail(entry
);
1125 this->num_immediates
++;
1131 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1133 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1134 union gl_constant_value uval
;
1137 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1143 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1145 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1146 union gl_constant_value uval
[2];
1148 memcpy(uval
, &val
, sizeof(uval
));
1149 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1150 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1155 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1157 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1158 union gl_constant_value uval
;
1160 assert(native_integers
);
1163 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1169 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1171 if (native_integers
)
1172 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1173 st_src_reg_for_int(val
);
1175 return st_src_reg_for_float(val
);
1179 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1181 return st_glsl_attrib_type_size(type
, is_vs_input
);
1185 type_size(const struct glsl_type
*type
)
1187 return st_glsl_type_size(type
);
1191 * If the given GLSL type is an array or matrix or a structure containing
1192 * an array/matrix member, return true. Else return false.
1194 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1195 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1196 * we have an array that might be indexed with a variable, we need to use
1197 * the later storage type.
1200 type_has_array_or_matrix(const glsl_type
*type
)
1202 if (type
->is_array() || type
->is_matrix())
1205 if (type
->is_record()) {
1206 for (unsigned i
= 0; i
< type
->length
; i
++) {
1207 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1218 * In the initial pass of codegen, we assign temporary numbers to
1219 * intermediate results. (not SSA -- variable assignments will reuse
1223 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1227 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1231 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1232 if (next_array
>= max_num_arrays
) {
1233 max_num_arrays
+= 32;
1234 array_sizes
= (unsigned*)
1235 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1238 src
.file
= PROGRAM_ARRAY
;
1240 src
.array_id
= next_array
+ 1;
1241 array_sizes
[next_array
] = type_size(type
);
1245 src
.file
= PROGRAM_TEMPORARY
;
1246 src
.index
= next_temp
;
1247 next_temp
+= type_size(type
);
1250 if (type
->is_array() || type
->is_record()) {
1251 src
.swizzle
= SWIZZLE_NOOP
;
1253 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1260 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1263 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1264 if (entry
->var
== var
)
1272 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1274 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1275 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1276 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1279 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1281 const ir_state_slot
*const slots
= ir
->get_state_slots();
1282 assert(slots
!= NULL
);
1284 /* Check if this statevar's setup in the STATE file exactly
1285 * matches how we'll want to reference it as a
1286 * struct/array/whatever. If not, then we need to move it into
1287 * temporary storage and hope that it'll get copy-propagated
1290 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1291 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1296 variable_storage
*storage
;
1298 if (i
== ir
->get_num_state_slots()) {
1299 /* We'll set the index later. */
1300 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1301 this->variables
.push_tail(storage
);
1305 /* The variable_storage constructor allocates slots based on the size
1306 * of the type. However, this had better match the number of state
1307 * elements that we're going to copy into the new temporary.
1309 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1311 dst
= st_dst_reg(get_temp(ir
->type
));
1313 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1316 this->variables
.push_tail(storage
);
1320 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1321 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1322 (gl_state_index
*)slots
[i
].tokens
);
1324 if (storage
->file
== PROGRAM_STATE_VAR
) {
1325 if (storage
->index
== -1) {
1326 storage
->index
= index
;
1328 assert(index
== storage
->index
+ (int)i
);
1331 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1332 * the data being moved since MOV does not care about the type of
1333 * data it is moving, and we don't want to declare registers with
1334 * array or struct types.
1336 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1337 src
.swizzle
= slots
[i
].swizzle
;
1338 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1339 /* even a float takes up a whole vec4 reg in a struct/array. */
1344 if (storage
->file
== PROGRAM_TEMPORARY
&&
1345 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1346 fail_link(this->shader_program
,
1347 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1348 ir
->name
, dst
.index
- storage
->index
,
1349 type_size(ir
->type
));
1355 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1357 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1359 visit_exec_list(&ir
->body_instructions
, this);
1361 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1365 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1368 case ir_loop_jump::jump_break
:
1369 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1371 case ir_loop_jump::jump_continue
:
1372 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1379 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1386 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1388 /* Ignore function bodies other than main() -- we shouldn't see calls to
1389 * them since they should all be inlined before we get to glsl_to_tgsi.
1391 if (strcmp(ir
->name
, "main") == 0) {
1392 const ir_function_signature
*sig
;
1395 sig
= ir
->matching_signature(NULL
, &empty
, false);
1399 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1406 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1408 int nonmul_operand
= 1 - mul_operand
;
1410 st_dst_reg result_dst
;
1412 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1413 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1416 expr
->operands
[0]->accept(this);
1418 expr
->operands
[1]->accept(this);
1420 ir
->operands
[nonmul_operand
]->accept(this);
1423 this->result
= get_temp(ir
->type
);
1424 result_dst
= st_dst_reg(this->result
);
1425 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1426 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1432 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1434 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1435 * implemented using multiplication, and logical-or is implemented using
1436 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1437 * As result, the logical expression (a & !b) can be rewritten as:
1441 * - (a * 1) - (a * b)
1445 * This final expression can be implemented as a single MAD(a, -b, a)
1449 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1451 const int other_operand
= 1 - try_operand
;
1454 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1455 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1458 ir
->operands
[other_operand
]->accept(this);
1460 expr
->operands
[0]->accept(this);
1463 b
.negate
= ~b
.negate
;
1465 this->result
= get_temp(ir
->type
);
1466 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1472 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1473 st_src_reg
*reg
, int *num_reladdr
)
1475 if (!reg
->reladdr
&& !reg
->reladdr2
)
1478 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1479 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1481 if (*num_reladdr
!= 1) {
1482 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1484 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1492 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1494 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1496 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1498 if (ir
->operation
== ir_binop_add
) {
1499 if (try_emit_mad(ir
, 1))
1501 if (try_emit_mad(ir
, 0))
1505 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1507 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1508 if (try_emit_mad_for_and_not(ir
, 1))
1510 if (try_emit_mad_for_and_not(ir
, 0))
1514 if (ir
->operation
== ir_quadop_vector
)
1515 assert(!"ir_quadop_vector should have been lowered");
1517 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1518 this->result
.file
= PROGRAM_UNDEFINED
;
1519 ir
->operands
[operand
]->accept(this);
1520 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1521 printf("Failed to get tree for expression operand:\n");
1522 ir
->operands
[operand
]->print();
1526 op
[operand
] = this->result
;
1528 /* Matrix expression operands should have been broken down to vector
1529 * operations already.
1531 assert(!ir
->operands
[operand
]->type
->is_matrix());
1534 visit_expression(ir
, op
);
1537 /* The non-recursive part of the expression visitor lives in a separate
1538 * function and should be prevented from being inlined, to avoid a stack
1539 * explosion when deeply nested expressions are visited.
1542 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1544 st_src_reg result_src
;
1545 st_dst_reg result_dst
;
1547 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1548 if (ir
->operands
[1]) {
1549 vector_elements
= MAX2(vector_elements
,
1550 ir
->operands
[1]->type
->vector_elements
);
1553 this->result
.file
= PROGRAM_UNDEFINED
;
1555 /* Storage for our result. Ideally for an assignment we'd be using
1556 * the actual storage for the result here, instead.
1558 result_src
= get_temp(ir
->type
);
1559 /* convenience for the emit functions below. */
1560 result_dst
= st_dst_reg(result_src
);
1561 /* Limit writes to the channels that will be used by result_src later.
1562 * This does limit this temp's use as a temporary for multi-instruction
1565 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1567 switch (ir
->operation
) {
1568 case ir_unop_logic_not
:
1569 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1570 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1572 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1573 * older GPUs implement SEQ using multiple instructions (i915 uses two
1574 * SGE instructions and a MUL instruction). Since our logic values are
1575 * 0.0 and 1.0, 1-x also implements !x.
1577 op
[0].negate
= ~op
[0].negate
;
1578 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1582 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1583 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1584 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1585 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1587 op
[0].negate
= ~op
[0].negate
;
1591 case ir_unop_subroutine_to_int
:
1592 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1595 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1598 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1601 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1605 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1609 assert(!"not reached: should be handled by ir_explog_to_explog2");
1612 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1615 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1618 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1620 case ir_unop_saturate
: {
1621 glsl_to_tgsi_instruction
*inst
;
1622 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1623 inst
->saturate
= true;
1628 case ir_unop_dFdx_coarse
:
1629 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1631 case ir_unop_dFdx_fine
:
1632 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1635 case ir_unop_dFdy_coarse
:
1636 case ir_unop_dFdy_fine
:
1638 /* The X component contains 1 or -1 depending on whether the framebuffer
1639 * is a FBO or the window system buffer, respectively.
1640 * It is then multiplied with the source operand of DDY.
1642 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1643 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1645 unsigned transform_y_index
=
1646 _mesa_add_state_reference(this->prog
->Parameters
,
1649 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1651 glsl_type::vec4_type
);
1652 transform_y
.swizzle
= SWIZZLE_XXXX
;
1654 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1656 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1657 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1658 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1662 case ir_unop_frexp_sig
:
1663 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1666 case ir_unop_frexp_exp
:
1667 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1670 case ir_unop_noise
: {
1671 /* At some point, a motivated person could add a better
1672 * implementation of noise. Currently not even the nvidia
1673 * binary drivers do anything more than this. In any case, the
1674 * place to do this is in the GL state tracker, not the poor
1677 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1682 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1685 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1689 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1692 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1693 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1695 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1698 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1699 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1701 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1705 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1707 case ir_binop_greater
:
1708 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1710 case ir_binop_lequal
:
1711 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1713 case ir_binop_gequal
:
1714 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1716 case ir_binop_equal
:
1717 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1719 case ir_binop_nequal
:
1720 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1722 case ir_binop_all_equal
:
1723 /* "==" operator producing a scalar boolean. */
1724 if (ir
->operands
[0]->type
->is_vector() ||
1725 ir
->operands
[1]->type
->is_vector()) {
1726 st_src_reg temp
= get_temp(native_integers
?
1727 glsl_type::uvec4_type
:
1728 glsl_type::vec4_type
);
1730 if (native_integers
) {
1731 st_dst_reg temp_dst
= st_dst_reg(temp
);
1732 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1734 if (ir
->operands
[0]->type
->is_boolean() &&
1735 ir
->operands
[1]->as_constant() &&
1736 ir
->operands
[1]->as_constant()->is_one()) {
1737 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1739 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1742 /* Emit 1-3 AND operations to combine the SEQ results. */
1743 switch (ir
->operands
[0]->type
->vector_elements
) {
1747 temp_dst
.writemask
= WRITEMASK_Y
;
1748 temp1
.swizzle
= SWIZZLE_YYYY
;
1749 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1750 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1753 temp_dst
.writemask
= WRITEMASK_X
;
1754 temp1
.swizzle
= SWIZZLE_XXXX
;
1755 temp2
.swizzle
= SWIZZLE_YYYY
;
1756 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1757 temp_dst
.writemask
= WRITEMASK_Y
;
1758 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1759 temp2
.swizzle
= SWIZZLE_WWWW
;
1760 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1763 temp1
.swizzle
= SWIZZLE_XXXX
;
1764 temp2
.swizzle
= SWIZZLE_YYYY
;
1765 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1767 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1769 /* After the dot-product, the value will be an integer on the
1770 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1772 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1774 /* Negating the result of the dot-product gives values on the range
1775 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1776 * This is achieved using SGE.
1778 st_src_reg sge_src
= result_src
;
1779 sge_src
.negate
= ~sge_src
.negate
;
1780 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1783 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1786 case ir_binop_any_nequal
:
1787 /* "!=" operator producing a scalar boolean. */
1788 if (ir
->operands
[0]->type
->is_vector() ||
1789 ir
->operands
[1]->type
->is_vector()) {
1790 st_src_reg temp
= get_temp(native_integers
?
1791 glsl_type::uvec4_type
:
1792 glsl_type::vec4_type
);
1793 if (ir
->operands
[0]->type
->is_boolean() &&
1794 ir
->operands
[1]->as_constant() &&
1795 ir
->operands
[1]->as_constant()->is_zero()) {
1796 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1798 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1801 if (native_integers
) {
1802 st_dst_reg temp_dst
= st_dst_reg(temp
);
1803 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1805 /* Emit 1-3 OR operations to combine the SNE results. */
1806 switch (ir
->operands
[0]->type
->vector_elements
) {
1810 temp_dst
.writemask
= WRITEMASK_Y
;
1811 temp1
.swizzle
= SWIZZLE_YYYY
;
1812 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1813 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1816 temp_dst
.writemask
= WRITEMASK_X
;
1817 temp1
.swizzle
= SWIZZLE_XXXX
;
1818 temp2
.swizzle
= SWIZZLE_YYYY
;
1819 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1820 temp_dst
.writemask
= WRITEMASK_Y
;
1821 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1822 temp2
.swizzle
= SWIZZLE_WWWW
;
1823 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1826 temp1
.swizzle
= SWIZZLE_XXXX
;
1827 temp2
.swizzle
= SWIZZLE_YYYY
;
1828 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1830 /* After the dot-product, the value will be an integer on the
1831 * range [0,4]. Zero stays zero, and positive values become 1.0.
1833 glsl_to_tgsi_instruction
*const dp
=
1834 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1835 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1836 /* The clamping to [0,1] can be done for free in the fragment
1837 * shader with a saturate.
1839 dp
->saturate
= true;
1841 /* Negating the result of the dot-product gives values on the range
1842 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1843 * achieved using SLT.
1845 st_src_reg slt_src
= result_src
;
1846 slt_src
.negate
= ~slt_src
.negate
;
1847 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1851 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1855 case ir_binop_logic_xor
:
1856 if (native_integers
)
1857 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1859 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1862 case ir_binop_logic_or
: {
1863 if (native_integers
) {
1864 /* If integers are used as booleans, we can use an actual "or"
1867 assert(native_integers
);
1868 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1870 /* After the addition, the value will be an integer on the
1871 * range [0,2]. Zero stays zero, and positive values become 1.0.
1873 glsl_to_tgsi_instruction
*add
=
1874 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1875 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1876 /* The clamping to [0,1] can be done for free in the fragment
1877 * shader with a saturate if floats are being used as boolean values.
1879 add
->saturate
= true;
1881 /* Negating the result of the addition gives values on the range
1882 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1883 * is achieved using SLT.
1885 st_src_reg slt_src
= result_src
;
1886 slt_src
.negate
= ~slt_src
.negate
;
1887 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1893 case ir_binop_logic_and
:
1894 /* If native integers are disabled, the bool args are stored as float 0.0
1895 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1896 * actual AND opcode.
1898 if (native_integers
)
1899 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1901 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1905 assert(ir
->operands
[0]->type
->is_vector());
1906 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1907 emit_dp(ir
, result_dst
, op
[0], op
[1],
1908 ir
->operands
[0]->type
->vector_elements
);
1913 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1915 /* This is the only instruction sequence that makes the game "Risen"
1916 * render correctly. ABS is not required for the game, but since GLSL
1917 * declares negative values as "undefined", allowing us to do whatever
1918 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1921 emit_scalar(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1922 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, result_src
);
1923 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1927 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1930 if (native_integers
) {
1931 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1934 /* fallthrough to next case otherwise */
1936 if (native_integers
) {
1937 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1940 /* fallthrough to next case otherwise */
1943 /* Converting between signed and unsigned integers is a no-op. */
1945 result_src
.type
= result_dst
.type
;
1948 if (native_integers
) {
1949 /* Booleans are stored as integers using ~0 for true and 0 for false.
1950 * GLSL requires that int(bool) return 1 for true and 0 for false.
1951 * This conversion is done with AND, but it could be done with NEG.
1953 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1955 /* Booleans and integers are both stored as floats when native
1956 * integers are disabled.
1962 if (native_integers
)
1963 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1965 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1968 if (native_integers
)
1969 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1971 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1973 case ir_unop_bitcast_f2i
:
1974 case ir_unop_bitcast_f2u
:
1975 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1977 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1980 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1983 case ir_unop_bitcast_i2f
:
1984 case ir_unop_bitcast_u2f
:
1986 result_src
.type
= GLSL_TYPE_FLOAT
;
1989 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1992 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1995 if (native_integers
)
1996 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1998 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2001 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2004 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2007 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2009 case ir_unop_round_even
:
2010 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2013 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2017 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2020 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2023 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2026 case ir_unop_bit_not
:
2027 if (native_integers
) {
2028 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2032 if (native_integers
) {
2033 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2036 case ir_binop_lshift
:
2037 if (native_integers
) {
2038 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2041 case ir_binop_rshift
:
2042 if (native_integers
) {
2043 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2046 case ir_binop_bit_and
:
2047 if (native_integers
) {
2048 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2051 case ir_binop_bit_xor
:
2052 if (native_integers
) {
2053 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2056 case ir_binop_bit_or
:
2057 if (native_integers
) {
2058 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2062 assert(!"GLSL 1.30 features unsupported");
2065 case ir_binop_ubo_load
: {
2066 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2067 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2068 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2069 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2070 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2073 cbuf
.type
= ir
->type
->base_type
;
2074 cbuf
.file
= PROGRAM_CONSTANT
;
2076 cbuf
.reladdr
= NULL
;
2079 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2081 if (const_offset_ir
) {
2082 /* Constant index into constant buffer */
2083 cbuf
.reladdr
= NULL
;
2084 cbuf
.index
= const_offset
/ 16;
2087 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2088 st_src_reg offset
= op
[1];
2090 /* The OpenGL spec is written in such a way that accesses with
2091 * non-constant offset are almost always vec4-aligned. The only
2092 * exception to this are members of structs in arrays of structs:
2093 * each struct in an array of structs is at least vec4-aligned,
2094 * but single-element and [ui]vec2 members of the struct may be at
2095 * an offset that is not a multiple of 16 bytes.
2097 * Here, we extract that offset, relying on previous passes to always
2098 * generate offset expressions of the form (+ expr constant_offset).
2100 * Note that the std430 layout, which allows more cases of alignment
2101 * less than vec4 in arrays, is not supported for uniform blocks, so
2102 * we do not have to deal with it here.
2104 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2105 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2106 if (const_offset_ir
) {
2107 const_offset
= const_offset_ir
->value
.u
[0];
2108 cbuf
.index
= const_offset
/ 16;
2109 offset_expr
->operands
[0]->accept(this);
2110 offset
= this->result
;
2114 /* Relative/variable index into constant buffer */
2115 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2116 st_src_reg_for_int(4));
2117 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2118 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2121 if (const_uniform_block
) {
2122 /* Constant constant buffer */
2123 cbuf
.reladdr2
= NULL
;
2124 cbuf
.index2D
= const_block
;
2125 cbuf
.has_index2
= true;
2128 /* Relative/variable constant buffer */
2129 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2131 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2132 cbuf
.has_index2
= true;
2135 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2136 if (glsl_base_type_is_64bit(cbuf
.type
))
2137 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2138 const_offset
% 16 / 8,
2139 const_offset
% 16 / 8,
2140 const_offset
% 16 / 8);
2142 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2143 const_offset
% 16 / 4,
2144 const_offset
% 16 / 4,
2145 const_offset
% 16 / 4);
2147 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2148 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2150 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2155 /* note: we have to reorder the three args here */
2156 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2159 if (this->ctx
->Const
.NativeIntegers
)
2160 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2162 op
[0].negate
= ~op
[0].negate
;
2163 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2166 case ir_triop_bitfield_extract
:
2167 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2169 case ir_quadop_bitfield_insert
:
2170 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2172 case ir_unop_bitfield_reverse
:
2173 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2175 case ir_unop_bit_count
:
2176 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2178 case ir_unop_find_msb
:
2179 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2181 case ir_unop_find_lsb
:
2182 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2184 case ir_binop_imul_high
:
2185 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2188 /* In theory, MAD is incorrect here. */
2190 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2192 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2194 case ir_unop_interpolate_at_centroid
:
2195 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2197 case ir_binop_interpolate_at_offset
: {
2198 /* The y coordinate needs to be flipped for the default fb */
2199 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2200 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2202 unsigned transform_y_index
=
2203 _mesa_add_state_reference(this->prog
->Parameters
,
2206 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2208 glsl_type::vec4_type
);
2209 transform_y
.swizzle
= SWIZZLE_XXXX
;
2211 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2212 st_dst_reg temp_dst
= st_dst_reg(temp
);
2214 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2215 temp_dst
.writemask
= WRITEMASK_Y
;
2216 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2217 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2220 case ir_binop_interpolate_at_sample
:
2221 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2225 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2228 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2231 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2234 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2237 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2240 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2242 case ir_unop_unpack_double_2x32
:
2243 case ir_unop_pack_double_2x32
:
2244 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2247 case ir_binop_ldexp
:
2248 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2249 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2251 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2255 case ir_unop_pack_half_2x16
:
2256 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2258 case ir_unop_unpack_half_2x16
:
2259 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2262 case ir_unop_get_buffer_size
: {
2263 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2266 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2267 (const_offset
? const_offset
->value
.u
[0] : 0),
2269 if (!const_offset
) {
2270 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2271 *buffer
.reladdr
= op
[0];
2272 emit_arl(ir
, sampler_reladdr
, op
[0]);
2274 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2278 case ir_unop_vote_any
:
2279 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2281 case ir_unop_vote_all
:
2282 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2284 case ir_unop_vote_eq
:
2285 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2288 case ir_unop_pack_snorm_2x16
:
2289 case ir_unop_pack_unorm_2x16
:
2290 case ir_unop_pack_snorm_4x8
:
2291 case ir_unop_pack_unorm_4x8
:
2293 case ir_unop_unpack_snorm_2x16
:
2294 case ir_unop_unpack_unorm_2x16
:
2295 case ir_unop_unpack_snorm_4x8
:
2296 case ir_unop_unpack_unorm_4x8
:
2298 case ir_quadop_vector
:
2299 case ir_binop_vector_extract
:
2300 case ir_triop_vector_insert
:
2301 case ir_binop_carry
:
2302 case ir_binop_borrow
:
2303 case ir_unop_ssbo_unsized_array_length
:
2304 /* This operation is not supported, or should have already been handled.
2306 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2310 this->result
= result_src
;
2315 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2321 /* Note that this is only swizzles in expressions, not those on the left
2322 * hand side of an assignment, which do write masking. See ir_assignment
2326 ir
->val
->accept(this);
2328 assert(src
.file
!= PROGRAM_UNDEFINED
);
2329 assert(ir
->type
->vector_elements
> 0);
2331 for (i
= 0; i
< 4; i
++) {
2332 if (i
< ir
->type
->vector_elements
) {
2335 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2338 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2341 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2344 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2348 /* If the type is smaller than a vec4, replicate the last
2351 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2355 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2360 /* Test if the variable is an array. Note that geometry and
2361 * tessellation shader inputs are outputs are always arrays (except
2362 * for patch inputs), so only the array element type is considered.
2365 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2367 const glsl_type
*type
= var
->type
;
2369 *remove_array
= false;
2371 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2372 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2375 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2376 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2377 stage
== MESA_SHADER_TESS_CTRL
) &&
2379 if (!var
->type
->is_array())
2380 return false; /* a system value probably */
2382 type
= var
->type
->fields
.array
;
2383 *remove_array
= true;
2386 return type
->is_array() || type
->is_matrix();
2390 st_translate_interp_loc(ir_variable
*var
)
2392 if (var
->data
.centroid
)
2393 return TGSI_INTERPOLATE_LOC_CENTROID
;
2394 else if (var
->data
.sample
)
2395 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2397 return TGSI_INTERPOLATE_LOC_CENTER
;
2401 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2403 variable_storage
*entry
= find_variable_storage(ir
->var
);
2404 ir_variable
*var
= ir
->var
;
2408 switch (var
->data
.mode
) {
2409 case ir_var_uniform
:
2410 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2411 var
->data
.param_index
);
2412 this->variables
.push_tail(entry
);
2414 case ir_var_shader_in
: {
2415 /* The linker assigns locations for varyings and attributes,
2416 * including deprecated builtins (like gl_Color), user-assign
2417 * generic attributes (glBindVertexLocation), and
2418 * user-defined varyings.
2420 assert(var
->data
.location
!= -1);
2422 const glsl_type
*type_without_array
= var
->type
->without_array();
2423 struct inout_decl
*decl
= &inputs
[num_inputs
];
2424 unsigned component
= var
->data
.location_frac
;
2425 unsigned num_components
;
2428 if (type_without_array
->is_64bit())
2429 component
= component
/ 2;
2430 if (type_without_array
->vector_elements
)
2431 num_components
= type_without_array
->vector_elements
;
2435 decl
->mesa_index
= var
->data
.location
;
2436 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2437 decl
->interp_loc
= st_translate_interp_loc(var
);
2438 decl
->base_type
= type_without_array
->base_type
;
2439 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2441 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2442 decl
->array_id
= num_input_arrays
+ 1;
2449 decl
->size
= type_size(var
->type
->fields
.array
);
2451 decl
->size
= type_size(var
->type
);
2453 entry
= new(mem_ctx
) variable_storage(var
,
2457 entry
->component
= component
;
2459 this->variables
.push_tail(entry
);
2462 case ir_var_shader_out
: {
2463 assert(var
->data
.location
!= -1);
2465 const glsl_type
*type_without_array
= var
->type
->without_array();
2466 struct inout_decl
*decl
= &outputs
[num_outputs
];
2467 unsigned component
= var
->data
.location_frac
;
2468 unsigned num_components
;
2471 if (type_without_array
->is_64bit())
2472 component
= component
/ 2;
2473 if (type_without_array
->vector_elements
)
2474 num_components
= type_without_array
->vector_elements
;
2478 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2479 decl
->base_type
= type_without_array
->base_type
;
2480 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2482 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2483 decl
->array_id
= num_output_arrays
+ 1;
2484 num_output_arrays
++;
2490 decl
->size
= type_size(var
->type
->fields
.array
);
2492 decl
->size
= type_size(var
->type
);
2494 entry
= new(mem_ctx
) variable_storage(var
,
2498 entry
->component
= component
;
2500 this->variables
.push_tail(entry
);
2503 case ir_var_system_value
:
2504 entry
= new(mem_ctx
) variable_storage(var
,
2505 PROGRAM_SYSTEM_VALUE
,
2506 var
->data
.location
);
2509 case ir_var_temporary
:
2510 st_src_reg src
= get_temp(var
->type
);
2512 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2514 this->variables
.push_tail(entry
);
2520 printf("Failed to make storage for %s\n", var
->name
);
2525 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2526 entry
->component
, entry
->array_id
);
2527 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2528 this->result
.is_double_vertex_input
= true;
2529 if (!native_integers
)
2530 this->result
.type
= GLSL_TYPE_FLOAT
;
2534 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2535 GLbitfield64
* usage_mask
,
2536 GLbitfield64 double_usage_mask
,
2537 GLbitfield
* patch_usage_mask
)
2542 /* Fix array declarations by removing unused array elements at both ends
2543 * of the arrays. For example, mat4[3] where only mat[1] is used.
2545 for (i
= 0; i
< count
; i
++) {
2546 struct inout_decl
*decl
= &decls
[i
];
2547 if (!decl
->array_id
)
2550 /* Shrink the beginning. */
2551 for (j
= 0; j
< (int)decl
->size
; j
++) {
2552 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2553 if (*patch_usage_mask
&
2554 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2558 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2560 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2569 /* Shrink the end. */
2570 for (j
= decl
->size
-1; j
>= 0; j
--) {
2571 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2572 if (*patch_usage_mask
&
2573 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2577 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2579 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2586 /* When not all entries of an array are accessed, we mark them as used
2587 * here anyway, to ensure that the input/output mapping logic doesn't get
2590 * TODO This happens when an array isn't used via indirect access, which
2591 * some game ports do (at least eON-based). There is an optimization
2592 * opportunity here by replacing the array declaration with non-array
2593 * declarations of those slots that are actually used.
2595 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2596 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2597 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2599 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2605 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2609 int element_size
= type_size(ir
->type
);
2612 index
= ir
->array_index
->constant_expression_value();
2614 ir
->array
->accept(this);
2617 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2618 switch (this->prog
->Target
) {
2619 case GL_TESS_CONTROL_PROGRAM_NV
:
2620 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2621 !ir
->variable_referenced()->data
.patch
;
2623 case GL_TESS_EVALUATION_PROGRAM_NV
:
2624 is_2D
= src
.file
== PROGRAM_INPUT
&&
2625 !ir
->variable_referenced()->data
.patch
;
2627 case GL_GEOMETRY_PROGRAM_NV
:
2628 is_2D
= src
.file
== PROGRAM_INPUT
;
2638 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2639 src
.file
== PROGRAM_INPUT
)
2640 element_size
= attrib_type_size(ir
->type
, true);
2642 src
.index2D
= index
->value
.i
[0];
2643 src
.has_index2
= true;
2645 src
.index
+= index
->value
.i
[0] * element_size
;
2647 /* Variable index array dereference. It eats the "vec4" of the
2648 * base of the array and an index that offsets the TGSI register
2651 ir
->array_index
->accept(this);
2653 st_src_reg index_reg
;
2655 if (element_size
== 1) {
2656 index_reg
= this->result
;
2658 index_reg
= get_temp(native_integers
?
2659 glsl_type::int_type
: glsl_type::float_type
);
2661 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2662 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2665 /* If there was already a relative address register involved, add the
2666 * new and the old together to get the new offset.
2668 if (!is_2D
&& src
.reladdr
!= NULL
) {
2669 st_src_reg accum_reg
= get_temp(native_integers
?
2670 glsl_type::int_type
: glsl_type::float_type
);
2672 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2673 index_reg
, *src
.reladdr
);
2675 index_reg
= accum_reg
;
2679 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2680 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2682 src
.has_index2
= true;
2684 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2685 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2689 /* Change the register type to the element type of the array. */
2690 src
.type
= ir
->type
->base_type
;
2696 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2699 const glsl_type
*struct_type
= ir
->record
->type
;
2702 ir
->record
->accept(this);
2704 for (i
= 0; i
< struct_type
->length
; i
++) {
2705 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2707 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2710 /* If the type is smaller than a vec4, replicate the last channel out. */
2711 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2712 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2714 this->result
.swizzle
= SWIZZLE_NOOP
;
2716 this->result
.index
+= offset
;
2717 this->result
.type
= ir
->type
->base_type
;
2721 * We want to be careful in assignment setup to hit the actual storage
2722 * instead of potentially using a temporary like we might with the
2723 * ir_dereference handler.
2726 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2728 /* The LHS must be a dereference. If the LHS is a variable indexed array
2729 * access of a vector, it must be separated into a series conditional moves
2730 * before reaching this point (see ir_vec_index_to_cond_assign).
2732 assert(ir
->as_dereference());
2733 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2735 assert(!deref_array
->array
->type
->is_vector());
2738 /* Use the rvalue deref handler for the most part. We write swizzles using
2739 * the writemask, but we do extract the base component for enhanced layouts
2740 * from the source swizzle.
2743 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2744 return st_dst_reg(v
->result
);
2748 * Process the condition of a conditional assignment
2750 * Examines the condition of a conditional assignment to generate the optimal
2751 * first operand of a \c CMP instruction. If the condition is a relational
2752 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2753 * used as the source for the \c CMP instruction. Otherwise the comparison
2754 * is processed to a boolean result, and the boolean result is used as the
2755 * operand to the CMP instruction.
2758 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2760 ir_rvalue
*src_ir
= ir
;
2762 bool switch_order
= false;
2764 ir_expression
*const expr
= ir
->as_expression();
2766 if (native_integers
) {
2767 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2768 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2769 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2770 type
== GLSL_TYPE_BOOL
) {
2771 if (expr
->operation
== ir_binop_equal
) {
2772 if (expr
->operands
[0]->is_zero()) {
2773 src_ir
= expr
->operands
[1];
2774 switch_order
= true;
2776 else if (expr
->operands
[1]->is_zero()) {
2777 src_ir
= expr
->operands
[0];
2778 switch_order
= true;
2781 else if (expr
->operation
== ir_binop_nequal
) {
2782 if (expr
->operands
[0]->is_zero()) {
2783 src_ir
= expr
->operands
[1];
2785 else if (expr
->operands
[1]->is_zero()) {
2786 src_ir
= expr
->operands
[0];
2792 src_ir
->accept(this);
2793 return switch_order
;
2796 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2797 bool zero_on_left
= false;
2799 if (expr
->operands
[0]->is_zero()) {
2800 src_ir
= expr
->operands
[1];
2801 zero_on_left
= true;
2802 } else if (expr
->operands
[1]->is_zero()) {
2803 src_ir
= expr
->operands
[0];
2804 zero_on_left
= false;
2808 * (a < 0) T F F ( a < 0) T F F
2809 * (0 < a) F F T (-a < 0) F F T
2810 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2811 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2812 * (a > 0) F F T (-a < 0) F F T
2813 * (0 > a) T F F ( a < 0) T F F
2814 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2815 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2817 * Note that exchanging the order of 0 and 'a' in the comparison simply
2818 * means that the value of 'a' should be negated.
2821 switch (expr
->operation
) {
2823 switch_order
= false;
2824 negate
= zero_on_left
;
2827 case ir_binop_greater
:
2828 switch_order
= false;
2829 negate
= !zero_on_left
;
2832 case ir_binop_lequal
:
2833 switch_order
= true;
2834 negate
= !zero_on_left
;
2837 case ir_binop_gequal
:
2838 switch_order
= true;
2839 negate
= zero_on_left
;
2843 /* This isn't the right kind of comparison afterall, so make sure
2844 * the whole condition is visited.
2852 src_ir
->accept(this);
2854 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2855 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2856 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2857 * computing the condition.
2860 this->result
.negate
= ~this->result
.negate
;
2862 return switch_order
;
2866 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2867 st_dst_reg
*l
, st_src_reg
*r
,
2868 st_src_reg
*cond
, bool cond_swap
)
2870 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2871 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2872 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2878 if (type
->is_array()) {
2879 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2880 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2885 if (type
->is_matrix()) {
2886 const struct glsl_type
*vec_type
;
2888 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2889 type
->vector_elements
, 1);
2891 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2892 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2897 assert(type
->is_scalar() || type
->is_vector());
2899 l
->type
= type
->base_type
;
2900 r
->type
= type
->base_type
;
2902 st_src_reg l_src
= st_src_reg(*l
);
2903 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2905 if (native_integers
) {
2906 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2907 cond_swap
? l_src
: *r
,
2908 cond_swap
? *r
: l_src
);
2910 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2911 cond_swap
? l_src
: *r
,
2912 cond_swap
? *r
: l_src
);
2915 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2919 if (type
->is_dual_slot()) {
2921 if (r
->is_double_vertex_input
== false)
2927 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2933 ir
->rhs
->accept(this);
2936 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2940 int first_enabled_chan
= 0;
2942 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2944 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2945 variable
->data
.mode
== ir_var_shader_out
&&
2946 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2947 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2948 assert(ir
->lhs
->type
->is_scalar());
2949 assert(ir
->write_mask
== WRITEMASK_X
);
2951 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2952 l
.writemask
= WRITEMASK_Z
;
2954 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2955 l
.writemask
= WRITEMASK_Y
;
2957 } else if (ir
->write_mask
== 0) {
2958 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2960 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2963 l
.writemask
= u_bit_consecutive(0, num_elements
);
2965 /* The type is a struct or an array of (array of) structs. */
2966 l
.writemask
= WRITEMASK_XYZW
;
2969 l
.writemask
= ir
->write_mask
;
2972 for (int i
= 0; i
< 4; i
++) {
2973 if (l
.writemask
& (1 << i
)) {
2974 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2979 l
.writemask
= l
.writemask
<< dst_component
;
2981 /* Swizzle a small RHS vector into the channels being written.
2983 * glsl ir treats write_mask as dictating how many channels are
2984 * present on the RHS while TGSI treats write_mask as just
2985 * showing which channels of the vec4 RHS get written.
2987 for (int i
= 0; i
< 4; i
++) {
2988 if (l
.writemask
& (1 << i
))
2989 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2991 swizzles
[i
] = first_enabled_chan
;
2993 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2994 swizzles
[2], swizzles
[3]);
2997 assert(l
.file
!= PROGRAM_UNDEFINED
);
2998 assert(r
.file
!= PROGRAM_UNDEFINED
);
3000 if (ir
->condition
) {
3001 const bool switch_order
= this->process_move_condition(ir
->condition
);
3002 st_src_reg condition
= this->result
;
3004 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3005 } else if (ir
->rhs
->as_expression() &&
3006 this->instructions
.get_tail() &&
3007 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3008 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3009 type_size(ir
->lhs
->type
) == 1 &&
3010 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3011 /* To avoid emitting an extra MOV when assigning an expression to a
3012 * variable, emit the last instruction of the expression again, but
3013 * replace the destination register with the target of the assignment.
3014 * Dead code elimination will remove the original instruction.
3016 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3017 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3018 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3019 new_inst
->saturate
= inst
->saturate
;
3020 inst
->dead_mask
= inst
->dst
[0].writemask
;
3022 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3028 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3031 GLdouble stack_vals
[4] = { 0 };
3032 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3033 GLenum gl_type
= GL_NONE
;
3035 static int in_array
= 0;
3036 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3038 /* Unfortunately, 4 floats is all we can get into
3039 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3040 * aggregate constant and move each constant value into it. If we
3041 * get lucky, copy propagation will eliminate the extra moves.
3043 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3044 st_src_reg temp_base
= get_temp(ir
->type
);
3045 st_dst_reg temp
= st_dst_reg(temp_base
);
3047 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3048 int size
= type_size(field_value
->type
);
3052 field_value
->accept(this);
3055 for (i
= 0; i
< (unsigned int)size
; i
++) {
3056 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3062 this->result
= temp_base
;
3066 if (ir
->type
->is_array()) {
3067 st_src_reg temp_base
= get_temp(ir
->type
);
3068 st_dst_reg temp
= st_dst_reg(temp_base
);
3069 int size
= type_size(ir
->type
->fields
.array
);
3074 for (i
= 0; i
< ir
->type
->length
; i
++) {
3075 ir
->array_elements
[i
]->accept(this);
3077 for (int j
= 0; j
< size
; j
++) {
3078 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3084 this->result
= temp_base
;
3089 if (ir
->type
->is_matrix()) {
3090 st_src_reg mat
= get_temp(ir
->type
);
3091 st_dst_reg mat_column
= st_dst_reg(mat
);
3093 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3094 switch (ir
->type
->base_type
) {
3095 case GLSL_TYPE_FLOAT
:
3096 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3098 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3099 src
.index
= add_constant(file
,
3101 ir
->type
->vector_elements
,
3104 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3106 case GLSL_TYPE_DOUBLE
:
3107 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3108 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3109 src
.index
= add_constant(file
,
3111 ir
->type
->vector_elements
,
3114 if (ir
->type
->vector_elements
>= 2) {
3115 mat_column
.writemask
= WRITEMASK_XY
;
3116 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3117 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3119 mat_column
.writemask
= WRITEMASK_X
;
3120 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3121 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3124 if (ir
->type
->vector_elements
> 2) {
3125 if (ir
->type
->vector_elements
== 4) {
3126 mat_column
.writemask
= WRITEMASK_ZW
;
3127 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3128 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3130 mat_column
.writemask
= WRITEMASK_Z
;
3131 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3132 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3133 mat_column
.writemask
= WRITEMASK_XYZW
;
3134 src
.swizzle
= SWIZZLE_XYZW
;
3140 unreachable("Illegal matrix constant type.\n");
3149 switch (ir
->type
->base_type
) {
3150 case GLSL_TYPE_FLOAT
:
3152 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3153 values
[i
].f
= ir
->value
.f
[i
];
3156 case GLSL_TYPE_DOUBLE
:
3157 gl_type
= GL_DOUBLE
;
3158 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3159 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3162 case GLSL_TYPE_UINT
:
3163 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3164 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3165 if (native_integers
)
3166 values
[i
].u
= ir
->value
.u
[i
];
3168 values
[i
].f
= ir
->value
.u
[i
];
3172 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3173 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3174 if (native_integers
)
3175 values
[i
].i
= ir
->value
.i
[i
];
3177 values
[i
].f
= ir
->value
.i
[i
];
3180 case GLSL_TYPE_BOOL
:
3181 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3182 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3183 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3187 assert(!"Non-float/uint/int/bool constant");
3190 this->result
= st_src_reg(file
, -1, ir
->type
);
3191 this->result
.index
= add_constant(file
,
3193 ir
->type
->vector_elements
,
3195 &this->result
.swizzle
);
3199 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3201 exec_node
*param
= ir
->actual_parameters
.get_head();
3202 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3203 ir_variable
*location
= deref
->variable_referenced();
3206 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3208 /* Calculate the surface offset */
3210 unsigned array_size
= 0, base
= 0;
3213 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3215 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3216 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3217 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3218 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3219 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3221 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3224 ir
->return_deref
->accept(this);
3225 st_dst_reg
dst(this->result
);
3226 dst
.writemask
= WRITEMASK_X
;
3228 glsl_to_tgsi_instruction
*inst
;
3230 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3231 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3232 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3233 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3234 st_src_reg_for_int(1));
3235 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3236 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3237 st_src_reg_for_int(-1));
3238 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3240 param
= param
->get_next();
3241 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3244 st_src_reg data
= this->result
, data2
= undef_src
;
3246 switch (ir
->callee
->intrinsic_id
) {
3247 case ir_intrinsic_atomic_counter_add
:
3248 opcode
= TGSI_OPCODE_ATOMUADD
;
3250 case ir_intrinsic_atomic_counter_min
:
3251 opcode
= TGSI_OPCODE_ATOMIMIN
;
3253 case ir_intrinsic_atomic_counter_max
:
3254 opcode
= TGSI_OPCODE_ATOMIMAX
;
3256 case ir_intrinsic_atomic_counter_and
:
3257 opcode
= TGSI_OPCODE_ATOMAND
;
3259 case ir_intrinsic_atomic_counter_or
:
3260 opcode
= TGSI_OPCODE_ATOMOR
;
3262 case ir_intrinsic_atomic_counter_xor
:
3263 opcode
= TGSI_OPCODE_ATOMXOR
;
3265 case ir_intrinsic_atomic_counter_exchange
:
3266 opcode
= TGSI_OPCODE_ATOMXCHG
;
3268 case ir_intrinsic_atomic_counter_comp_swap
: {
3269 opcode
= TGSI_OPCODE_ATOMCAS
;
3270 param
= param
->get_next();
3271 val
= ((ir_instruction
*)param
)->as_rvalue();
3273 data2
= this->result
;
3277 assert(!"Unexpected intrinsic");
3281 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3284 inst
->resource
= buffer
;
3288 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3290 exec_node
*param
= ir
->actual_parameters
.get_head();
3292 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3294 param
= param
->get_next();
3295 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3297 ir_constant
*const_block
= block
->as_constant();
3301 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3302 (const_block
? const_block
->value
.u
[0] : 0),
3306 block
->accept(this);
3307 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3308 *buffer
.reladdr
= this->result
;
3309 emit_arl(ir
, sampler_reladdr
, this->result
);
3312 /* Calculate the surface offset */
3313 offset
->accept(this);
3314 st_src_reg off
= this->result
;
3316 st_dst_reg dst
= undef_dst
;
3317 if (ir
->return_deref
) {
3318 ir
->return_deref
->accept(this);
3319 dst
= st_dst_reg(this->result
);
3320 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3323 glsl_to_tgsi_instruction
*inst
;
3325 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3326 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3327 if (dst
.type
== GLSL_TYPE_BOOL
)
3328 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3329 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3330 param
= param
->get_next();
3331 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3334 param
= param
->get_next();
3335 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3337 dst
.writemask
= write_mask
->value
.u
[0];
3339 dst
.type
= this->result
.type
;
3340 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3342 param
= param
->get_next();
3343 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3346 st_src_reg data
= this->result
, data2
= undef_src
;
3348 switch (ir
->callee
->intrinsic_id
) {
3349 case ir_intrinsic_ssbo_atomic_add
:
3350 opcode
= TGSI_OPCODE_ATOMUADD
;
3352 case ir_intrinsic_ssbo_atomic_min
:
3353 opcode
= TGSI_OPCODE_ATOMIMIN
;
3355 case ir_intrinsic_ssbo_atomic_max
:
3356 opcode
= TGSI_OPCODE_ATOMIMAX
;
3358 case ir_intrinsic_ssbo_atomic_and
:
3359 opcode
= TGSI_OPCODE_ATOMAND
;
3361 case ir_intrinsic_ssbo_atomic_or
:
3362 opcode
= TGSI_OPCODE_ATOMOR
;
3364 case ir_intrinsic_ssbo_atomic_xor
:
3365 opcode
= TGSI_OPCODE_ATOMXOR
;
3367 case ir_intrinsic_ssbo_atomic_exchange
:
3368 opcode
= TGSI_OPCODE_ATOMXCHG
;
3370 case ir_intrinsic_ssbo_atomic_comp_swap
:
3371 opcode
= TGSI_OPCODE_ATOMCAS
;
3372 param
= param
->get_next();
3373 val
= ((ir_instruction
*)param
)->as_rvalue();
3375 data2
= this->result
;
3378 assert(!"Unexpected intrinsic");
3382 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3385 param
= param
->get_next();
3386 ir_constant
*access
= NULL
;
3387 if (!param
->is_tail_sentinel()) {
3388 access
= ((ir_instruction
*)param
)->as_constant();
3392 /* The emit_asm() might have actually split the op into pieces, e.g. for
3393 * double stores. We have to go back and fix up all the generated ops.
3395 unsigned op
= inst
->op
;
3397 inst
->resource
= buffer
;
3399 inst
->buffer_access
= access
->value
.u
[0];
3400 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3401 if (inst
->op
== TGSI_OPCODE_UADD
)
3402 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3403 } while (inst
&& inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3407 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3409 switch (ir
->callee
->intrinsic_id
) {
3410 case ir_intrinsic_memory_barrier
:
3411 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3412 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3413 TGSI_MEMBAR_ATOMIC_BUFFER
|
3414 TGSI_MEMBAR_SHADER_IMAGE
|
3415 TGSI_MEMBAR_SHARED
));
3417 case ir_intrinsic_memory_barrier_atomic_counter
:
3418 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3419 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3421 case ir_intrinsic_memory_barrier_buffer
:
3422 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3423 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3425 case ir_intrinsic_memory_barrier_image
:
3426 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3427 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3429 case ir_intrinsic_memory_barrier_shared
:
3430 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3431 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3433 case ir_intrinsic_group_memory_barrier
:
3434 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3435 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3436 TGSI_MEMBAR_ATOMIC_BUFFER
|
3437 TGSI_MEMBAR_SHADER_IMAGE
|
3438 TGSI_MEMBAR_SHARED
|
3439 TGSI_MEMBAR_THREAD_GROUP
));
3442 assert(!"Unexpected memory barrier intrinsic");
3447 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3449 exec_node
*param
= ir
->actual_parameters
.get_head();
3451 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3453 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3455 /* Calculate the surface offset */
3456 offset
->accept(this);
3457 st_src_reg off
= this->result
;
3459 st_dst_reg dst
= undef_dst
;
3460 if (ir
->return_deref
) {
3461 ir
->return_deref
->accept(this);
3462 dst
= st_dst_reg(this->result
);
3463 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3466 glsl_to_tgsi_instruction
*inst
;
3468 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3469 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3470 inst
->resource
= buffer
;
3471 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3472 param
= param
->get_next();
3473 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3476 param
= param
->get_next();
3477 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3479 dst
.writemask
= write_mask
->value
.u
[0];
3481 dst
.type
= this->result
.type
;
3482 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3483 inst
->resource
= buffer
;
3485 param
= param
->get_next();
3486 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3489 st_src_reg data
= this->result
, data2
= undef_src
;
3491 switch (ir
->callee
->intrinsic_id
) {
3492 case ir_intrinsic_shared_atomic_add
:
3493 opcode
= TGSI_OPCODE_ATOMUADD
;
3495 case ir_intrinsic_shared_atomic_min
:
3496 opcode
= TGSI_OPCODE_ATOMIMIN
;
3498 case ir_intrinsic_shared_atomic_max
:
3499 opcode
= TGSI_OPCODE_ATOMIMAX
;
3501 case ir_intrinsic_shared_atomic_and
:
3502 opcode
= TGSI_OPCODE_ATOMAND
;
3504 case ir_intrinsic_shared_atomic_or
:
3505 opcode
= TGSI_OPCODE_ATOMOR
;
3507 case ir_intrinsic_shared_atomic_xor
:
3508 opcode
= TGSI_OPCODE_ATOMXOR
;
3510 case ir_intrinsic_shared_atomic_exchange
:
3511 opcode
= TGSI_OPCODE_ATOMXCHG
;
3513 case ir_intrinsic_shared_atomic_comp_swap
:
3514 opcode
= TGSI_OPCODE_ATOMCAS
;
3515 param
= param
->get_next();
3516 val
= ((ir_instruction
*)param
)->as_rvalue();
3518 data2
= this->result
;
3521 assert(!"Unexpected intrinsic");
3525 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3526 inst
->resource
= buffer
;
3531 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3533 exec_node
*param
= ir
->actual_parameters
.get_head();
3535 ir_dereference
*img
= (ir_dereference
*)param
;
3536 const ir_variable
*imgvar
= img
->variable_referenced();
3537 const glsl_type
*type
= imgvar
->type
->without_array();
3538 unsigned sampler_array_size
= 1, sampler_base
= 0;
3541 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3543 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3544 (uint16_t*)&image
.index
, &reladdr
, true);
3546 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3547 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3548 *image
.reladdr
= reladdr
;
3549 emit_arl(ir
, sampler_reladdr
, reladdr
);
3552 st_dst_reg dst
= undef_dst
;
3553 if (ir
->return_deref
) {
3554 ir
->return_deref
->accept(this);
3555 dst
= st_dst_reg(this->result
);
3556 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3559 glsl_to_tgsi_instruction
*inst
;
3561 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3562 dst
.writemask
= WRITEMASK_XYZ
;
3563 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3564 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3565 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3566 st_dst_reg dstres
= st_dst_reg(res
);
3567 dstres
.writemask
= WRITEMASK_W
;
3568 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3569 res
.swizzle
= SWIZZLE_WWWW
;
3570 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3572 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3574 st_dst_reg coord_dst
;
3575 coord
= get_temp(glsl_type::ivec4_type
);
3576 coord_dst
= st_dst_reg(coord
);
3577 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3578 param
= param
->get_next();
3579 ((ir_dereference
*)param
)->accept(this);
3580 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3581 coord
.swizzle
= SWIZZLE_XXXX
;
3582 switch (type
->coordinate_components()) {
3583 case 4: assert(!"unexpected coord count");
3585 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3587 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3590 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3591 param
= param
->get_next();
3592 ((ir_dereference
*)param
)->accept(this);
3593 st_src_reg sample
= this->result
;
3594 sample
.swizzle
= SWIZZLE_XXXX
;
3595 coord_dst
.writemask
= WRITEMASK_W
;
3596 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3597 coord
.swizzle
|= SWIZZLE_W
<< 9;
3600 param
= param
->get_next();
3601 if (!param
->is_tail_sentinel()) {
3602 ((ir_dereference
*)param
)->accept(this);
3603 arg1
= this->result
;
3604 param
= param
->get_next();
3607 if (!param
->is_tail_sentinel()) {
3608 ((ir_dereference
*)param
)->accept(this);
3609 arg2
= this->result
;
3610 param
= param
->get_next();
3613 assert(param
->is_tail_sentinel());
3616 switch (ir
->callee
->intrinsic_id
) {
3617 case ir_intrinsic_image_load
:
3618 opcode
= TGSI_OPCODE_LOAD
;
3620 case ir_intrinsic_image_store
:
3621 opcode
= TGSI_OPCODE_STORE
;
3623 case ir_intrinsic_image_atomic_add
:
3624 opcode
= TGSI_OPCODE_ATOMUADD
;
3626 case ir_intrinsic_image_atomic_min
:
3627 opcode
= TGSI_OPCODE_ATOMIMIN
;
3629 case ir_intrinsic_image_atomic_max
:
3630 opcode
= TGSI_OPCODE_ATOMIMAX
;
3632 case ir_intrinsic_image_atomic_and
:
3633 opcode
= TGSI_OPCODE_ATOMAND
;
3635 case ir_intrinsic_image_atomic_or
:
3636 opcode
= TGSI_OPCODE_ATOMOR
;
3638 case ir_intrinsic_image_atomic_xor
:
3639 opcode
= TGSI_OPCODE_ATOMXOR
;
3641 case ir_intrinsic_image_atomic_exchange
:
3642 opcode
= TGSI_OPCODE_ATOMXCHG
;
3644 case ir_intrinsic_image_atomic_comp_swap
:
3645 opcode
= TGSI_OPCODE_ATOMCAS
;
3648 assert(!"Unexpected intrinsic");
3652 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3653 if (opcode
== TGSI_OPCODE_STORE
)
3654 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3657 inst
->resource
= image
;
3658 inst
->sampler_array_size
= sampler_array_size
;
3659 inst
->sampler_base
= sampler_base
;
3661 switch (type
->sampler_dimensionality
) {
3662 case GLSL_SAMPLER_DIM_1D
:
3663 inst
->tex_target
= (type
->sampler_array
)
3664 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3666 case GLSL_SAMPLER_DIM_2D
:
3667 inst
->tex_target
= (type
->sampler_array
)
3668 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3670 case GLSL_SAMPLER_DIM_3D
:
3671 inst
->tex_target
= TEXTURE_3D_INDEX
;
3673 case GLSL_SAMPLER_DIM_CUBE
:
3674 inst
->tex_target
= (type
->sampler_array
)
3675 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3677 case GLSL_SAMPLER_DIM_RECT
:
3678 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3680 case GLSL_SAMPLER_DIM_BUF
:
3681 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3683 case GLSL_SAMPLER_DIM_EXTERNAL
:
3684 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3686 case GLSL_SAMPLER_DIM_MS
:
3687 inst
->tex_target
= (type
->sampler_array
)
3688 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3691 assert(!"Should not get here.");
3694 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3695 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3697 if (imgvar
->data
.image_coherent
)
3698 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3699 if (imgvar
->data
.image_restrict
)
3700 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3701 if (imgvar
->data
.image_volatile
)
3702 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3706 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3708 ir_function_signature
*sig
= ir
->callee
;
3710 /* Filter out intrinsics */
3711 switch (sig
->intrinsic_id
) {
3712 case ir_intrinsic_atomic_counter_read
:
3713 case ir_intrinsic_atomic_counter_increment
:
3714 case ir_intrinsic_atomic_counter_predecrement
:
3715 case ir_intrinsic_atomic_counter_add
:
3716 case ir_intrinsic_atomic_counter_min
:
3717 case ir_intrinsic_atomic_counter_max
:
3718 case ir_intrinsic_atomic_counter_and
:
3719 case ir_intrinsic_atomic_counter_or
:
3720 case ir_intrinsic_atomic_counter_xor
:
3721 case ir_intrinsic_atomic_counter_exchange
:
3722 case ir_intrinsic_atomic_counter_comp_swap
:
3723 visit_atomic_counter_intrinsic(ir
);
3726 case ir_intrinsic_ssbo_load
:
3727 case ir_intrinsic_ssbo_store
:
3728 case ir_intrinsic_ssbo_atomic_add
:
3729 case ir_intrinsic_ssbo_atomic_min
:
3730 case ir_intrinsic_ssbo_atomic_max
:
3731 case ir_intrinsic_ssbo_atomic_and
:
3732 case ir_intrinsic_ssbo_atomic_or
:
3733 case ir_intrinsic_ssbo_atomic_xor
:
3734 case ir_intrinsic_ssbo_atomic_exchange
:
3735 case ir_intrinsic_ssbo_atomic_comp_swap
:
3736 visit_ssbo_intrinsic(ir
);
3739 case ir_intrinsic_memory_barrier
:
3740 case ir_intrinsic_memory_barrier_atomic_counter
:
3741 case ir_intrinsic_memory_barrier_buffer
:
3742 case ir_intrinsic_memory_barrier_image
:
3743 case ir_intrinsic_memory_barrier_shared
:
3744 case ir_intrinsic_group_memory_barrier
:
3745 visit_membar_intrinsic(ir
);
3748 case ir_intrinsic_shared_load
:
3749 case ir_intrinsic_shared_store
:
3750 case ir_intrinsic_shared_atomic_add
:
3751 case ir_intrinsic_shared_atomic_min
:
3752 case ir_intrinsic_shared_atomic_max
:
3753 case ir_intrinsic_shared_atomic_and
:
3754 case ir_intrinsic_shared_atomic_or
:
3755 case ir_intrinsic_shared_atomic_xor
:
3756 case ir_intrinsic_shared_atomic_exchange
:
3757 case ir_intrinsic_shared_atomic_comp_swap
:
3758 visit_shared_intrinsic(ir
);
3761 case ir_intrinsic_image_load
:
3762 case ir_intrinsic_image_store
:
3763 case ir_intrinsic_image_atomic_add
:
3764 case ir_intrinsic_image_atomic_min
:
3765 case ir_intrinsic_image_atomic_max
:
3766 case ir_intrinsic_image_atomic_and
:
3767 case ir_intrinsic_image_atomic_or
:
3768 case ir_intrinsic_image_atomic_xor
:
3769 case ir_intrinsic_image_atomic_exchange
:
3770 case ir_intrinsic_image_atomic_comp_swap
:
3771 case ir_intrinsic_image_size
:
3772 case ir_intrinsic_image_samples
:
3773 visit_image_intrinsic(ir
);
3776 case ir_intrinsic_invalid
:
3777 case ir_intrinsic_generic_load
:
3778 case ir_intrinsic_generic_store
:
3779 case ir_intrinsic_generic_atomic_add
:
3780 case ir_intrinsic_generic_atomic_and
:
3781 case ir_intrinsic_generic_atomic_or
:
3782 case ir_intrinsic_generic_atomic_xor
:
3783 case ir_intrinsic_generic_atomic_min
:
3784 case ir_intrinsic_generic_atomic_max
:
3785 case ir_intrinsic_generic_atomic_exchange
:
3786 case ir_intrinsic_generic_atomic_comp_swap
:
3787 case ir_intrinsic_shader_clock
:
3788 unreachable("Invalid intrinsic");
3793 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3794 unsigned *array_elements
,
3796 st_src_reg
*indirect
,
3799 switch (tail
->ir_type
) {
3800 case ir_type_dereference_record
: {
3801 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3802 const glsl_type
*struct_type
= deref_record
->record
->type
;
3803 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3805 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3807 assert(field_index
>= 0);
3808 *location
+= struct_type
->record_location_offset(field_index
);
3812 case ir_type_dereference_array
: {
3813 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3814 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3817 st_src_reg temp_reg
;
3818 st_dst_reg temp_dst
;
3820 temp_reg
= get_temp(glsl_type::uint_type
);
3821 temp_dst
= st_dst_reg(temp_reg
);
3822 temp_dst
.writemask
= 1;
3824 deref_arr
->array_index
->accept(this);
3825 if (*array_elements
!= 1)
3826 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3828 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3830 if (indirect
->file
== PROGRAM_UNDEFINED
)
3831 *indirect
= temp_reg
;
3833 temp_dst
= st_dst_reg(*indirect
);
3834 temp_dst
.writemask
= 1;
3835 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3838 *index
+= array_index
->value
.u
[0] * *array_elements
;
3840 *array_elements
*= deref_arr
->array
->type
->length
;
3842 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3851 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3852 unsigned *array_size
,
3855 st_src_reg
*reladdr
,
3858 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3859 unsigned location
= 0;
3860 ir_variable
*var
= ir
->variable_referenced();
3862 memset(reladdr
, 0, sizeof(*reladdr
));
3863 reladdr
->file
= PROGRAM_UNDEFINED
;
3869 location
= var
->data
.location
;
3870 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3873 * If we end up with no indirect then adjust the base to the index,
3874 * and set the array size to 1.
3876 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3882 assert(location
!= 0xffffffff);
3883 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3884 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3889 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3891 if (offset
.reladdr
|| offset
.reladdr2
) {
3892 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3893 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3894 tmp_dst
.writemask
= WRITEMASK_XY
;
3895 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
3903 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3905 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3906 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3907 st_src_reg levels_src
, reladdr
;
3908 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3909 glsl_to_tgsi_instruction
*inst
= NULL
;
3910 unsigned opcode
= TGSI_OPCODE_NOP
;
3911 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3912 unsigned sampler_array_size
= 1, sampler_base
= 0;
3913 uint16_t sampler_index
= 0;
3914 bool is_cube_array
= false;
3917 /* if we are a cube array sampler */
3918 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3919 sampler_type
->sampler_array
)) {
3920 is_cube_array
= true;
3923 if (ir
->coordinate
) {
3924 ir
->coordinate
->accept(this);
3926 /* Put our coords in a temp. We'll need to modify them for shadow,
3927 * projection, or LOD, so the only case we'd use it as-is is if
3928 * we're doing plain old texturing. The optimization passes on
3929 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3931 coord
= get_temp(glsl_type::vec4_type
);
3932 coord_dst
= st_dst_reg(coord
);
3933 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3934 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3937 if (ir
->projector
) {
3938 ir
->projector
->accept(this);
3939 projector
= this->result
;
3942 /* Storage for our result. Ideally for an assignment we'd be using
3943 * the actual storage for the result here, instead.
3945 result_src
= get_temp(ir
->type
);
3946 result_dst
= st_dst_reg(result_src
);
3950 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3952 ir
->offset
->accept(this);
3953 offset
[0] = this->result
;
3957 if (is_cube_array
||
3958 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3959 opcode
= TGSI_OPCODE_TXB2
;
3962 opcode
= TGSI_OPCODE_TXB
;
3964 ir
->lod_info
.bias
->accept(this);
3965 lod_info
= this->result
;
3967 ir
->offset
->accept(this);
3968 offset
[0] = this->result
;
3972 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3973 ir
->lod_info
.lod
->accept(this);
3974 lod_info
= this->result
;
3976 ir
->offset
->accept(this);
3977 offset
[0] = this->result
;
3981 opcode
= TGSI_OPCODE_TXD
;
3982 ir
->lod_info
.grad
.dPdx
->accept(this);
3984 ir
->lod_info
.grad
.dPdy
->accept(this);
3987 ir
->offset
->accept(this);
3988 offset
[0] = this->result
;
3992 opcode
= TGSI_OPCODE_TXQ
;
3993 ir
->lod_info
.lod
->accept(this);
3994 lod_info
= this->result
;
3996 case ir_query_levels
:
3997 opcode
= TGSI_OPCODE_TXQ
;
3998 lod_info
= undef_src
;
3999 levels_src
= get_temp(ir
->type
);
4002 opcode
= TGSI_OPCODE_TXF
;
4003 ir
->lod_info
.lod
->accept(this);
4004 lod_info
= this->result
;
4006 ir
->offset
->accept(this);
4007 offset
[0] = this->result
;
4011 opcode
= TGSI_OPCODE_TXF
;
4012 ir
->lod_info
.sample_index
->accept(this);
4013 sample_index
= this->result
;
4016 opcode
= TGSI_OPCODE_TG4
;
4017 ir
->lod_info
.component
->accept(this);
4018 component
= this->result
;
4020 ir
->offset
->accept(this);
4021 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4022 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4023 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4024 offset
[i
] = this->result
;
4025 offset
[i
].index
+= i
* type_size(elt_type
);
4026 offset
[i
].type
= elt_type
->base_type
;
4027 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4028 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4031 offset
[0] = canonicalize_gather_offset(this->result
);
4036 opcode
= TGSI_OPCODE_LODQ
;
4038 case ir_texture_samples
:
4039 opcode
= TGSI_OPCODE_TXQS
;
4041 case ir_samples_identical
:
4042 unreachable("Unexpected ir_samples_identical opcode");
4045 if (ir
->projector
) {
4046 if (opcode
== TGSI_OPCODE_TEX
) {
4047 /* Slot the projector in as the last component of the coord. */
4048 coord_dst
.writemask
= WRITEMASK_W
;
4049 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4050 coord_dst
.writemask
= WRITEMASK_XYZW
;
4051 opcode
= TGSI_OPCODE_TXP
;
4053 st_src_reg coord_w
= coord
;
4054 coord_w
.swizzle
= SWIZZLE_WWWW
;
4056 /* For the other TEX opcodes there's no projective version
4057 * since the last slot is taken up by LOD info. Do the
4058 * projective divide now.
4060 coord_dst
.writemask
= WRITEMASK_W
;
4061 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4063 /* In the case where we have to project the coordinates "by hand,"
4064 * the shadow comparator value must also be projected.
4066 st_src_reg tmp_src
= coord
;
4067 if (ir
->shadow_comparitor
) {
4068 /* Slot the shadow value in as the second to last component of the
4071 ir
->shadow_comparitor
->accept(this);
4073 tmp_src
= get_temp(glsl_type::vec4_type
);
4074 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4076 /* Projective division not allowed for array samplers. */
4077 assert(!sampler_type
->sampler_array
);
4079 tmp_dst
.writemask
= WRITEMASK_Z
;
4080 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4082 tmp_dst
.writemask
= WRITEMASK_XY
;
4083 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4086 coord_dst
.writemask
= WRITEMASK_XYZ
;
4087 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4089 coord_dst
.writemask
= WRITEMASK_XYZW
;
4090 coord
.swizzle
= SWIZZLE_XYZW
;
4094 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4095 * comparator was put in the correct place (and projected) by the code,
4096 * above, that handles by-hand projection.
4098 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4099 /* Slot the shadow value in as the second to last component of the
4102 ir
->shadow_comparitor
->accept(this);
4104 if (is_cube_array
) {
4105 cube_sc
= get_temp(glsl_type::float_type
);
4106 cube_sc_dst
= st_dst_reg(cube_sc
);
4107 cube_sc_dst
.writemask
= WRITEMASK_X
;
4108 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4109 cube_sc_dst
.writemask
= WRITEMASK_X
;
4112 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4113 sampler_type
->sampler_array
) ||
4114 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4115 coord_dst
.writemask
= WRITEMASK_W
;
4117 coord_dst
.writemask
= WRITEMASK_Z
;
4119 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4120 coord_dst
.writemask
= WRITEMASK_XYZW
;
4124 if (ir
->op
== ir_txf_ms
) {
4125 coord_dst
.writemask
= WRITEMASK_W
;
4126 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4127 coord_dst
.writemask
= WRITEMASK_XYZW
;
4128 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4129 opcode
== TGSI_OPCODE_TXF
) {
4130 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4131 coord_dst
.writemask
= WRITEMASK_W
;
4132 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4133 coord_dst
.writemask
= WRITEMASK_XYZW
;
4136 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4137 &sampler_index
, &reladdr
, true);
4138 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4139 emit_arl(ir
, sampler_reladdr
, reladdr
);
4141 if (opcode
== TGSI_OPCODE_TXD
)
4142 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4143 else if (opcode
== TGSI_OPCODE_TXQ
) {
4144 if (ir
->op
== ir_query_levels
) {
4145 /* the level is stored in W */
4146 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4147 result_dst
.writemask
= WRITEMASK_X
;
4148 levels_src
.swizzle
= SWIZZLE_WWWW
;
4149 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4151 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4152 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4153 inst
= emit_asm(ir
, opcode
, result_dst
);
4154 } else if (opcode
== TGSI_OPCODE_TXF
) {
4155 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4156 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4157 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4158 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4159 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4160 } else if (opcode
== TGSI_OPCODE_TG4
) {
4161 if (is_cube_array
&& ir
->shadow_comparitor
) {
4162 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4164 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4167 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4169 if (ir
->shadow_comparitor
)
4170 inst
->tex_shadow
= GL_TRUE
;
4172 inst
->resource
.index
= sampler_index
;
4173 inst
->sampler_array_size
= sampler_array_size
;
4174 inst
->sampler_base
= sampler_base
;
4176 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4177 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4178 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4182 if (!inst
->tex_offsets
)
4183 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4185 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4186 inst
->tex_offsets
[i
] = offset
[i
];
4187 inst
->tex_offset_num_offset
= i
;
4190 switch (sampler_type
->sampler_dimensionality
) {
4191 case GLSL_SAMPLER_DIM_1D
:
4192 inst
->tex_target
= (sampler_type
->sampler_array
)
4193 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4195 case GLSL_SAMPLER_DIM_2D
:
4196 inst
->tex_target
= (sampler_type
->sampler_array
)
4197 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4199 case GLSL_SAMPLER_DIM_3D
:
4200 inst
->tex_target
= TEXTURE_3D_INDEX
;
4202 case GLSL_SAMPLER_DIM_CUBE
:
4203 inst
->tex_target
= (sampler_type
->sampler_array
)
4204 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4206 case GLSL_SAMPLER_DIM_RECT
:
4207 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4209 case GLSL_SAMPLER_DIM_BUF
:
4210 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4212 case GLSL_SAMPLER_DIM_EXTERNAL
:
4213 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4215 case GLSL_SAMPLER_DIM_MS
:
4216 inst
->tex_target
= (sampler_type
->sampler_array
)
4217 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4220 assert(!"Should not get here.");
4223 inst
->tex_type
= ir
->type
->base_type
;
4225 this->result
= result_src
;
4229 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4231 assert(!ir
->get_value());
4233 emit_asm(ir
, TGSI_OPCODE_RET
);
4237 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4239 if (ir
->condition
) {
4240 ir
->condition
->accept(this);
4241 st_src_reg condition
= this->result
;
4243 /* Convert the bool condition to a float so we can negate. */
4244 if (native_integers
) {
4245 st_src_reg temp
= get_temp(ir
->condition
->type
);
4246 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4247 condition
, st_src_reg_for_float(1.0));
4251 condition
.negate
= ~condition
.negate
;
4252 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4254 /* unconditional kil */
4255 emit_asm(ir
, TGSI_OPCODE_KILL
);
4260 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4263 glsl_to_tgsi_instruction
*if_inst
;
4265 ir
->condition
->accept(this);
4266 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4268 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4270 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4272 this->instructions
.push_tail(if_inst
);
4274 visit_exec_list(&ir
->then_instructions
, this);
4276 if (!ir
->else_instructions
.is_empty()) {
4277 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4278 visit_exec_list(&ir
->else_instructions
, this);
4281 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4286 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4288 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4290 ir
->stream
->accept(this);
4291 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4295 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4297 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4299 ir
->stream
->accept(this);
4300 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4304 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4306 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4307 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4309 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4312 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4314 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4316 result
.file
= PROGRAM_UNDEFINED
;
4323 num_input_arrays
= 0;
4324 num_output_arrays
= 0;
4326 num_address_regs
= 0;
4330 indirect_addr_consts
= false;
4331 wpos_transform_const
= -1;
4333 native_integers
= false;
4334 mem_ctx
= ralloc_context(NULL
);
4337 shader_program
= NULL
;
4342 use_shared_memory
= false;
4345 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4348 ralloc_free(mem_ctx
);
4351 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4358 * Count resources used by the given gpu program (number of texture
4362 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4364 v
->samplers_used
= 0;
4365 v
->buffers_used
= 0;
4368 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4369 if (inst
->info
->is_tex
) {
4370 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4371 unsigned idx
= inst
->sampler_base
+ i
;
4372 v
->samplers_used
|= 1u << idx
;
4374 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4375 v
->sampler_types
[idx
] = inst
->tex_type
;
4376 v
->sampler_targets
[idx
] =
4377 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4379 if (inst
->tex_shadow
) {
4380 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4385 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4386 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4388 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4389 is_resource_instruction(inst
->op
) ||
4390 inst
->op
== TGSI_OPCODE_STORE
)) {
4391 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4392 v
->buffers_used
|= 1 << inst
->resource
.index
;
4393 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4394 v
->use_shared_memory
= true;
4396 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4397 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4398 unsigned idx
= inst
->sampler_base
+ i
;
4399 v
->images_used
|= 1 << idx
;
4400 v
->image_targets
[idx
] =
4401 st_translate_texture_target(inst
->tex_target
, false);
4402 v
->image_formats
[idx
] = inst
->image_format
;
4407 prog
->SamplersUsed
= v
->samplers_used
;
4409 if (v
->shader_program
!= NULL
)
4410 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4414 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4415 * are read from the given src in this instruction
4418 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4420 int read_mask
= 0, comp
;
4422 /* Now, given the src swizzle and the written channels, find which
4423 * components are actually read
4425 for (comp
= 0; comp
< 4; ++comp
) {
4426 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4428 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4429 read_mask
|= 1 << coord
;
4436 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4437 * instruction is the first instruction to write to register T0. There are
4438 * several lowering passes done in GLSL IR (e.g. branches and
4439 * relative addressing) that create a large number of conditional assignments
4440 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4442 * Here is why this conversion is safe:
4443 * CMP T0, T1 T2 T0 can be expanded to:
4449 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4450 * as the original program. If (T1 < 0.0) evaluates to false, executing
4451 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4452 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4453 * because any instruction that was going to read from T0 after this was going
4454 * to read a garbage value anyway.
4457 glsl_to_tgsi_visitor::simplify_cmp(void)
4459 int tempWritesSize
= 0;
4460 unsigned *tempWrites
= NULL
;
4461 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4463 memset(outputWrites
, 0, sizeof(outputWrites
));
4465 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4466 unsigned prevWriteMask
= 0;
4468 /* Give up if we encounter relative addressing or flow control. */
4469 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4470 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4471 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4472 inst
->op
== TGSI_OPCODE_CONT
||
4473 inst
->op
== TGSI_OPCODE_END
||
4474 inst
->op
== TGSI_OPCODE_RET
) {
4478 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4479 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4480 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4481 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4482 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4483 if (inst
->dst
[0].index
>= tempWritesSize
) {
4484 const int inc
= 4096;
4486 tempWrites
= (unsigned*)
4488 (tempWritesSize
+ inc
) * sizeof(unsigned));
4492 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4493 tempWritesSize
+= inc
;
4496 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4497 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4501 /* For a CMP to be considered a conditional write, the destination
4502 * register and source register two must be the same. */
4503 if (inst
->op
== TGSI_OPCODE_CMP
4504 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4505 && inst
->src
[2].file
== inst
->dst
[0].file
4506 && inst
->src
[2].index
== inst
->dst
[0].index
4507 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4509 inst
->op
= TGSI_OPCODE_MOV
;
4510 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4511 inst
->src
[0] = inst
->src
[1];
4518 /* Replaces all references to a temporary register index with another index. */
4520 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4522 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4525 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4526 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4527 for (k
= 0; k
< num_renames
; k
++)
4528 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4529 inst
->src
[j
].index
= renames
[k
].new_reg
;
4532 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4533 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4534 for (k
= 0; k
< num_renames
; k
++)
4535 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4536 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4539 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4540 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4541 for (k
= 0; k
< num_renames
; k
++)
4542 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4543 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4549 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4551 int depth
= 0; /* loop depth */
4552 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4555 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4556 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4557 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4558 if (first_reads
[inst
->src
[j
].index
] == -1)
4559 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4562 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4563 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4564 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4565 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4568 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4571 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4581 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4583 int depth
= 0; /* loop depth */
4584 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4587 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4588 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4589 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4590 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4592 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4593 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4594 if (first_writes
[inst
->dst
[j
].index
] == -1)
4595 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4596 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4599 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4600 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4601 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4603 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4606 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4609 for (k
= 0; k
< this->next_temp
; k
++) {
4610 if (last_reads
[k
] == -2) {
4622 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4624 int depth
= 0; /* loop depth */
4628 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4629 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4630 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4631 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4634 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4636 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4638 for (k
= 0; k
< this->next_temp
; k
++) {
4639 if (last_writes
[k
] == -2) {
4650 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4651 * channels for copy propagation and updates following instructions to
4652 * use the original versions.
4654 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4655 * will occur. As an example, a TXP production before this pass:
4657 * 0: MOV TEMP[1], INPUT[4].xyyy;
4658 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4659 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4663 * 0: MOV TEMP[1], INPUT[4].xyyy;
4664 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4665 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4667 * which allows for dead code elimination on TEMP[1]'s writes.
4670 glsl_to_tgsi_visitor::copy_propagate(void)
4672 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4673 glsl_to_tgsi_instruction
*,
4674 this->next_temp
* 4);
4675 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4678 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4679 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4680 || inst
->dst
[0].index
< this->next_temp
);
4682 /* First, do any copy propagation possible into the src regs. */
4683 for (int r
= 0; r
< 3; r
++) {
4684 glsl_to_tgsi_instruction
*first
= NULL
;
4686 int acp_base
= inst
->src
[r
].index
* 4;
4688 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4689 inst
->src
[r
].reladdr
||
4690 inst
->src
[r
].reladdr2
)
4693 /* See if we can find entries in the ACP consisting of MOVs
4694 * from the same src register for all the swizzled channels
4695 * of this src register reference.
4697 for (int i
= 0; i
< 4; i
++) {
4698 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4699 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4706 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4711 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4712 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4713 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4714 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4722 /* We've now validated that we can copy-propagate to
4723 * replace this src register reference. Do it.
4725 inst
->src
[r
].file
= first
->src
[0].file
;
4726 inst
->src
[r
].index
= first
->src
[0].index
;
4727 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4728 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4729 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4730 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4733 for (int i
= 0; i
< 4; i
++) {
4734 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4735 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4736 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4738 inst
->src
[r
].swizzle
= swizzle
;
4743 case TGSI_OPCODE_BGNLOOP
:
4744 case TGSI_OPCODE_ENDLOOP
:
4745 /* End of a basic block, clear the ACP entirely. */
4746 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4749 case TGSI_OPCODE_IF
:
4750 case TGSI_OPCODE_UIF
:
4754 case TGSI_OPCODE_ENDIF
:
4755 case TGSI_OPCODE_ELSE
:
4756 /* Clear all channels written inside the block from the ACP, but
4757 * leaving those that were not touched.
4759 for (int r
= 0; r
< this->next_temp
; r
++) {
4760 for (int c
= 0; c
< 4; c
++) {
4761 if (!acp
[4 * r
+ c
])
4764 if (acp_level
[4 * r
+ c
] >= level
)
4765 acp
[4 * r
+ c
] = NULL
;
4768 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4773 /* Continuing the block, clear any written channels from
4776 for (int d
= 0; d
< 2; d
++) {
4777 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4778 /* Any temporary might be written, so no copy propagation
4779 * across this instruction.
4781 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4782 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4783 inst
->dst
[d
].reladdr
) {
4784 /* Any output might be written, so no copy propagation
4785 * from outputs across this instruction.
4787 for (int r
= 0; r
< this->next_temp
; r
++) {
4788 for (int c
= 0; c
< 4; c
++) {
4789 if (!acp
[4 * r
+ c
])
4792 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4793 acp
[4 * r
+ c
] = NULL
;
4796 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4797 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4798 /* Clear where it's used as dst. */
4799 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4800 for (int c
= 0; c
< 4; c
++) {
4801 if (inst
->dst
[d
].writemask
& (1 << c
))
4802 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4806 /* Clear where it's used as src. */
4807 for (int r
= 0; r
< this->next_temp
; r
++) {
4808 for (int c
= 0; c
< 4; c
++) {
4809 if (!acp
[4 * r
+ c
])
4812 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4814 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4815 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4816 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4817 acp
[4 * r
+ c
] = NULL
;
4826 /* If this is a copy, add it to the ACP. */
4827 if (inst
->op
== TGSI_OPCODE_MOV
&&
4828 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4829 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4830 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4831 !inst
->dst
[0].reladdr
&&
4832 !inst
->dst
[0].reladdr2
&&
4834 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4835 !inst
->src
[0].reladdr
&&
4836 !inst
->src
[0].reladdr2
&&
4837 !inst
->src
[0].negate
) {
4838 for (int i
= 0; i
< 4; i
++) {
4839 if (inst
->dst
[0].writemask
& (1 << i
)) {
4840 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4841 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4847 ralloc_free(acp_level
);
4852 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4855 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4856 * will occur. As an example, a TXP production after copy propagation but
4859 * 0: MOV TEMP[1], INPUT[4].xyyy;
4860 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4861 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4863 * and after this pass:
4865 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4868 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4870 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4871 glsl_to_tgsi_instruction
*,
4872 this->next_temp
* 4);
4873 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4877 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4878 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4879 || inst
->dst
[0].index
< this->next_temp
);
4882 case TGSI_OPCODE_BGNLOOP
:
4883 case TGSI_OPCODE_ENDLOOP
:
4884 case TGSI_OPCODE_CONT
:
4885 case TGSI_OPCODE_BRK
:
4886 /* End of a basic block, clear the write array entirely.
4888 * This keeps us from killing dead code when the writes are
4889 * on either side of a loop, even when the register isn't touched
4890 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4891 * dead code of this type, so it shouldn't make a difference as long as
4892 * the dead code elimination pass in the GLSL compiler does its job.
4894 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4897 case TGSI_OPCODE_ENDIF
:
4898 case TGSI_OPCODE_ELSE
:
4899 /* Promote the recorded level of all channels written inside the
4900 * preceding if or else block to the level above the if/else block.
4902 for (int r
= 0; r
< this->next_temp
; r
++) {
4903 for (int c
= 0; c
< 4; c
++) {
4904 if (!writes
[4 * r
+ c
])
4907 if (write_level
[4 * r
+ c
] == level
)
4908 write_level
[4 * r
+ c
] = level
-1;
4911 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4915 case TGSI_OPCODE_IF
:
4916 case TGSI_OPCODE_UIF
:
4918 /* fallthrough to default case to mark the condition as read */
4920 /* Continuing the block, clear any channels from the write array that
4921 * are read by this instruction.
4923 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4924 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4925 /* Any temporary might be read, so no dead code elimination
4926 * across this instruction.
4928 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4929 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4930 /* Clear where it's used as src. */
4931 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4932 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4933 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4934 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4936 for (int c
= 0; c
< 4; c
++) {
4937 if (src_chans
& (1 << c
))
4938 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4942 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4943 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4944 /* Any temporary might be read, so no dead code elimination
4945 * across this instruction.
4947 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4948 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4949 /* Clear where it's used as src. */
4950 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4951 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4952 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4953 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4955 for (int c
= 0; c
< 4; c
++) {
4956 if (src_chans
& (1 << c
))
4957 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4964 /* If this instruction writes to a temporary, add it to the write array.
4965 * If there is already an instruction in the write array for one or more
4966 * of the channels, flag that channel write as dead.
4968 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4969 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4970 !inst
->dst
[i
].reladdr
) {
4971 for (int c
= 0; c
< 4; c
++) {
4972 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4973 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4974 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4977 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4979 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4980 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4987 /* Anything still in the write array at this point is dead code. */
4988 for (int r
= 0; r
< this->next_temp
; r
++) {
4989 for (int c
= 0; c
< 4; c
++) {
4990 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4992 inst
->dead_mask
|= (1 << c
);
4996 /* Now actually remove the instructions that are completely dead and update
4997 * the writemask of other instructions with dead channels.
4999 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5000 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5002 /* No amount of dead masks should remove memory stores */
5003 if (inst
->info
->is_store
)
5006 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5011 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5012 if (inst
->dead_mask
== WRITEMASK_XY
||
5013 inst
->dead_mask
== WRITEMASK_ZW
)
5014 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5016 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5020 ralloc_free(write_level
);
5021 ralloc_free(writes
);
5026 /* merge DFRACEXP instructions into one. */
5028 glsl_to_tgsi_visitor::merge_two_dsts(void)
5030 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5031 glsl_to_tgsi_instruction
*inst2
;
5033 if (num_inst_dst_regs(inst
) != 2)
5036 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5037 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5040 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5043 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5044 inst
->src
[0].index
== inst2
->src
[0].index
&&
5045 inst
->src
[0].type
== inst2
->src
[0].type
&&
5046 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5048 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5054 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5056 inst
->dst
[0] = inst2
->dst
[0];
5057 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5058 inst
->dst
[1] = inst2
->dst
[1];
5069 /* Merges temporary registers together where possible to reduce the number of
5070 * registers needed to run a program.
5072 * Produces optimal code only after copy propagation and dead code elimination
5075 glsl_to_tgsi_visitor::merge_registers(void)
5077 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5078 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5079 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5081 int num_renames
= 0;
5083 /* Read the indices of the last read and first write to each temp register
5084 * into an array so that we don't have to traverse the instruction list as
5086 for (i
= 0; i
< this->next_temp
; i
++) {
5088 first_writes
[i
] = -1;
5090 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5092 /* Start looking for registers with non-overlapping usages that can be
5093 * merged together. */
5094 for (i
= 0; i
< this->next_temp
; i
++) {
5095 /* Don't touch unused registers. */
5096 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5098 for (j
= 0; j
< this->next_temp
; j
++) {
5099 /* Don't touch unused registers. */
5100 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5102 /* We can merge the two registers if the first write to j is after or
5103 * in the same instruction as the last read from i. Note that the
5104 * register at index i will always be used earlier or at the same time
5105 * as the register at index j. */
5106 if (first_writes
[i
] <= first_writes
[j
] &&
5107 last_reads
[i
] <= first_writes
[j
]) {
5108 renames
[num_renames
].old_reg
= j
;
5109 renames
[num_renames
].new_reg
= i
;
5112 /* Update the first_writes and last_reads arrays with the new
5113 * values for the merged register index, and mark the newly unused
5114 * register index as such. */
5115 assert(last_reads
[j
] >= last_reads
[i
]);
5116 last_reads
[i
] = last_reads
[j
];
5117 first_writes
[j
] = -1;
5123 rename_temp_registers(num_renames
, renames
);
5124 ralloc_free(renames
);
5125 ralloc_free(last_reads
);
5126 ralloc_free(first_writes
);
5129 /* Reassign indices to temporary registers by reusing unused indices created
5130 * by optimization passes. */
5132 glsl_to_tgsi_visitor::renumber_registers(void)
5136 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5137 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5138 int num_renames
= 0;
5139 for (i
= 0; i
< this->next_temp
; i
++) {
5140 first_reads
[i
] = -1;
5142 get_first_temp_read(first_reads
);
5144 for (i
= 0; i
< this->next_temp
; i
++) {
5145 if (first_reads
[i
] < 0) continue;
5146 if (i
!= new_index
) {
5147 renames
[num_renames
].old_reg
= i
;
5148 renames
[num_renames
].new_reg
= new_index
;
5154 rename_temp_registers(num_renames
, renames
);
5155 this->next_temp
= new_index
;
5156 ralloc_free(renames
);
5157 ralloc_free(first_reads
);
5160 /* ------------------------- TGSI conversion stuff -------------------------- */
5163 * Intermediate state used during shader translation.
5165 struct st_translate
{
5166 struct ureg_program
*ureg
;
5168 unsigned temps_size
;
5169 struct ureg_dst
*temps
;
5171 struct ureg_dst
*arrays
;
5172 unsigned num_temp_arrays
;
5173 struct ureg_src
*constants
;
5175 struct ureg_src
*immediates
;
5177 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5178 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5179 struct ureg_dst address
[3];
5180 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5181 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5182 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5183 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5184 struct ureg_src shared_memory
;
5185 unsigned *array_sizes
;
5186 struct inout_decl
*input_decls
;
5187 unsigned num_input_decls
;
5188 struct inout_decl
*output_decls
;
5189 unsigned num_output_decls
;
5191 const GLuint
*inputMapping
;
5192 const GLuint
*outputMapping
;
5194 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5197 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5199 _mesa_sysval_to_semantic(unsigned sysval
)
5203 case SYSTEM_VALUE_VERTEX_ID
:
5204 return TGSI_SEMANTIC_VERTEXID
;
5205 case SYSTEM_VALUE_INSTANCE_ID
:
5206 return TGSI_SEMANTIC_INSTANCEID
;
5207 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5208 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5209 case SYSTEM_VALUE_BASE_VERTEX
:
5210 return TGSI_SEMANTIC_BASEVERTEX
;
5211 case SYSTEM_VALUE_BASE_INSTANCE
:
5212 return TGSI_SEMANTIC_BASEINSTANCE
;
5213 case SYSTEM_VALUE_DRAW_ID
:
5214 return TGSI_SEMANTIC_DRAWID
;
5216 /* Geometry shader */
5217 case SYSTEM_VALUE_INVOCATION_ID
:
5218 return TGSI_SEMANTIC_INVOCATIONID
;
5220 /* Fragment shader */
5221 case SYSTEM_VALUE_FRAG_COORD
:
5222 return TGSI_SEMANTIC_POSITION
;
5223 case SYSTEM_VALUE_FRONT_FACE
:
5224 return TGSI_SEMANTIC_FACE
;
5225 case SYSTEM_VALUE_SAMPLE_ID
:
5226 return TGSI_SEMANTIC_SAMPLEID
;
5227 case SYSTEM_VALUE_SAMPLE_POS
:
5228 return TGSI_SEMANTIC_SAMPLEPOS
;
5229 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5230 return TGSI_SEMANTIC_SAMPLEMASK
;
5231 case SYSTEM_VALUE_HELPER_INVOCATION
:
5232 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5234 /* Tessellation shader */
5235 case SYSTEM_VALUE_TESS_COORD
:
5236 return TGSI_SEMANTIC_TESSCOORD
;
5237 case SYSTEM_VALUE_VERTICES_IN
:
5238 return TGSI_SEMANTIC_VERTICESIN
;
5239 case SYSTEM_VALUE_PRIMITIVE_ID
:
5240 return TGSI_SEMANTIC_PRIMID
;
5241 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5242 return TGSI_SEMANTIC_TESSOUTER
;
5243 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5244 return TGSI_SEMANTIC_TESSINNER
;
5246 /* Compute shader */
5247 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5248 return TGSI_SEMANTIC_THREAD_ID
;
5249 case SYSTEM_VALUE_WORK_GROUP_ID
:
5250 return TGSI_SEMANTIC_BLOCK_ID
;
5251 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5252 return TGSI_SEMANTIC_GRID_SIZE
;
5253 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5254 return TGSI_SEMANTIC_BLOCK_SIZE
;
5257 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5258 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5259 case SYSTEM_VALUE_VERTEX_CNT
:
5261 assert(!"Unexpected SYSTEM_VALUE_ enum");
5262 return TGSI_SEMANTIC_COUNT
;
5267 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5269 static struct ureg_src
5270 emit_immediate(struct st_translate
*t
,
5271 gl_constant_value values
[4],
5274 struct ureg_program
*ureg
= t
->ureg
;
5279 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5281 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5283 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5284 case GL_UNSIGNED_INT
:
5286 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5288 assert(!"should not get here - type must be float, int, uint, or bool");
5289 return ureg_src_undef();
5294 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5296 static struct ureg_dst
5297 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5303 case PROGRAM_UNDEFINED
:
5304 return ureg_dst_undef();
5306 case PROGRAM_TEMPORARY
:
5307 /* Allocate space for temporaries on demand. */
5308 if (index
>= t
->temps_size
) {
5309 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5311 t
->temps
= (struct ureg_dst
*)
5313 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5315 return ureg_dst_undef();
5317 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5318 t
->temps_size
+= inc
;
5321 if (ureg_dst_is_undef(t
->temps
[index
]))
5322 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5324 return t
->temps
[index
];
5327 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5328 array
= array_id
- 1;
5330 if (ureg_dst_is_undef(t
->arrays
[array
]))
5331 t
->arrays
[array
] = ureg_DECL_array_temporary(
5332 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5334 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5336 case PROGRAM_OUTPUT
:
5338 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5339 assert(index
< 2 * FRAG_RESULT_MAX
);
5340 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5341 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5342 assert(index
< VARYING_SLOT_TESS_MAX
);
5344 assert(index
< VARYING_SLOT_MAX
);
5346 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5347 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5348 return t
->outputs
[t
->outputMapping
[index
]];
5351 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5352 unsigned mesa_index
= decl
->mesa_index
;
5353 int slot
= t
->outputMapping
[mesa_index
];
5355 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5357 struct ureg_dst dst
= t
->outputs
[slot
];
5358 dst
.ArrayID
= array_id
;
5359 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5362 case PROGRAM_ADDRESS
:
5363 return t
->address
[index
];
5366 assert(!"unknown dst register file");
5367 return ureg_dst_undef();
5372 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5374 static struct ureg_src
5375 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5377 int index
= reg
->index
;
5378 int double_reg2
= reg
->double_reg2
? 1 : 0;
5381 case PROGRAM_UNDEFINED
:
5382 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5384 case PROGRAM_TEMPORARY
:
5386 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5388 case PROGRAM_OUTPUT
: {
5389 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5390 assert(dst
.WriteMask
!= 0);
5391 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5392 return ureg_swizzle(ureg_src(dst
),
5396 MIN2(shift
+ 3, 3));
5399 case PROGRAM_UNIFORM
:
5400 assert(reg
->index
>= 0);
5401 return reg
->index
< t
->num_constants
?
5402 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5403 case PROGRAM_STATE_VAR
:
5404 case PROGRAM_CONSTANT
: /* ie, immediate */
5405 if (reg
->has_index2
)
5406 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5408 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5409 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5411 case PROGRAM_IMMEDIATE
:
5412 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5413 return t
->immediates
[reg
->index
];
5416 /* GLSL inputs are 64-bit containers, so we have to
5417 * map back to the original index and add the offset after
5419 index
-= double_reg2
;
5420 if (!reg
->array_id
) {
5421 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5422 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5423 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5426 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5427 unsigned mesa_index
= decl
->mesa_index
;
5428 int slot
= t
->inputMapping
[mesa_index
];
5430 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5432 struct ureg_src src
= t
->inputs
[slot
];
5433 src
.ArrayID
= reg
->array_id
;
5434 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5437 case PROGRAM_ADDRESS
:
5438 return ureg_src(t
->address
[reg
->index
]);
5440 case PROGRAM_SYSTEM_VALUE
:
5441 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5442 return t
->systemValues
[reg
->index
];
5445 assert(!"unknown src register file");
5446 return ureg_src_undef();
5451 * Create a TGSI ureg_dst register from an st_dst_reg.
5453 static struct ureg_dst
5454 translate_dst(struct st_translate
*t
,
5455 const st_dst_reg
*dst_reg
,
5458 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5461 if (dst
.File
== TGSI_FILE_NULL
)
5464 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5467 dst
= ureg_saturate(dst
);
5469 if (dst_reg
->reladdr
!= NULL
) {
5470 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5471 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5474 if (dst_reg
->has_index2
) {
5475 if (dst_reg
->reladdr2
)
5476 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5479 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5486 * Create a TGSI ureg_src register from an st_src_reg.
5488 static struct ureg_src
5489 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5491 struct ureg_src src
= src_register(t
, src_reg
);
5493 if (src_reg
->has_index2
) {
5494 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5495 * and UBO constant buffers (buffer, position).
5497 if (src_reg
->reladdr2
)
5498 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5501 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5504 src
= ureg_swizzle(src
,
5505 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5506 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5507 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5508 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5510 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5511 src
= ureg_negate(src
);
5513 if (src_reg
->reladdr
!= NULL
) {
5514 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5515 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5521 static struct tgsi_texture_offset
5522 translate_tex_offset(struct st_translate
*t
,
5523 const st_src_reg
*in_offset
)
5525 struct tgsi_texture_offset offset
;
5526 struct ureg_src src
= translate_src(t
, in_offset
);
5528 offset
.File
= src
.File
;
5529 offset
.Index
= src
.Index
;
5530 offset
.SwizzleX
= src
.SwizzleX
;
5531 offset
.SwizzleY
= src
.SwizzleY
;
5532 offset
.SwizzleZ
= src
.SwizzleZ
;
5535 assert(!src
.Indirect
);
5536 assert(!src
.DimIndirect
);
5537 assert(!src
.Dimension
);
5538 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5539 assert(!src
.Negate
);
5545 compile_tgsi_instruction(struct st_translate
*t
,
5546 const glsl_to_tgsi_instruction
*inst
)
5548 struct ureg_program
*ureg
= t
->ureg
;
5550 struct ureg_dst dst
[2];
5551 struct ureg_src src
[4];
5552 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5556 unsigned tex_target
= 0;
5558 num_dst
= num_inst_dst_regs(inst
);
5559 num_src
= num_inst_src_regs(inst
);
5561 for (i
= 0; i
< num_dst
; i
++)
5562 dst
[i
] = translate_dst(t
,
5566 for (i
= 0; i
< num_src
; i
++)
5567 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5570 case TGSI_OPCODE_BGNLOOP
:
5571 case TGSI_OPCODE_ELSE
:
5572 case TGSI_OPCODE_ENDLOOP
:
5573 case TGSI_OPCODE_IF
:
5574 case TGSI_OPCODE_UIF
:
5575 assert(num_dst
== 0);
5576 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5579 case TGSI_OPCODE_TEX
:
5580 case TGSI_OPCODE_TXB
:
5581 case TGSI_OPCODE_TXD
:
5582 case TGSI_OPCODE_TXL
:
5583 case TGSI_OPCODE_TXP
:
5584 case TGSI_OPCODE_TXQ
:
5585 case TGSI_OPCODE_TXQS
:
5586 case TGSI_OPCODE_TXF
:
5587 case TGSI_OPCODE_TEX2
:
5588 case TGSI_OPCODE_TXB2
:
5589 case TGSI_OPCODE_TXL2
:
5590 case TGSI_OPCODE_TG4
:
5591 case TGSI_OPCODE_LODQ
:
5592 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5593 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5594 if (inst
->resource
.reladdr
)
5596 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5598 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5599 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5601 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5607 texoffsets
, inst
->tex_offset_num_offset
,
5611 case TGSI_OPCODE_RESQ
:
5612 case TGSI_OPCODE_LOAD
:
5613 case TGSI_OPCODE_ATOMUADD
:
5614 case TGSI_OPCODE_ATOMXCHG
:
5615 case TGSI_OPCODE_ATOMCAS
:
5616 case TGSI_OPCODE_ATOMAND
:
5617 case TGSI_OPCODE_ATOMOR
:
5618 case TGSI_OPCODE_ATOMXOR
:
5619 case TGSI_OPCODE_ATOMUMIN
:
5620 case TGSI_OPCODE_ATOMUMAX
:
5621 case TGSI_OPCODE_ATOMIMIN
:
5622 case TGSI_OPCODE_ATOMIMAX
:
5623 for (i
= num_src
- 1; i
>= 0; i
--)
5624 src
[i
+ 1] = src
[i
];
5626 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5627 src
[0] = t
->shared_memory
;
5628 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5629 src
[0] = t
->buffers
[inst
->resource
.index
];
5631 src
[0] = t
->images
[inst
->resource
.index
];
5632 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5634 if (inst
->resource
.reladdr
)
5635 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5636 assert(src
[0].File
!= TGSI_FILE_NULL
);
5637 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5638 inst
->buffer_access
,
5639 tex_target
, inst
->image_format
);
5642 case TGSI_OPCODE_STORE
:
5643 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5644 dst
[0] = ureg_dst(t
->shared_memory
);
5645 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5646 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5648 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5649 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5651 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5652 if (inst
->resource
.reladdr
)
5653 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5654 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5655 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5656 inst
->buffer_access
,
5657 tex_target
, inst
->image_format
);
5660 case TGSI_OPCODE_SCS
:
5661 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5662 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5675 * Emit the TGSI instructions for inverting and adjusting WPOS.
5676 * This code is unavoidable because it also depends on whether
5677 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5680 emit_wpos_adjustment(struct gl_context
*ctx
,
5681 struct st_translate
*t
,
5682 int wpos_transform_const
,
5684 GLfloat adjX
, GLfloat adjY
[2])
5686 struct ureg_program
*ureg
= t
->ureg
;
5688 assert(wpos_transform_const
>= 0);
5690 /* Fragment program uses fragment position input.
5691 * Need to replace instances of INPUT[WPOS] with temp T
5692 * where T = INPUT[WPOS] is inverted by Y.
5694 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5695 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5696 struct ureg_src
*wpos
=
5697 ctx
->Const
.GLSLFragCoordIsSysVal
?
5698 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5699 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5700 struct ureg_src wpos_input
= *wpos
;
5702 /* First, apply the coordinate shift: */
5703 if (adjX
|| adjY
[0] || adjY
[1]) {
5704 if (adjY
[0] != adjY
[1]) {
5705 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5706 * depending on whether inversion is actually going to be applied
5707 * or not, which is determined by testing against the inversion
5708 * state variable used below, which will be either +1 or -1.
5710 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5712 ureg_CMP(ureg
, adj_temp
,
5713 ureg_scalar(wpostrans
, invert
? 2 : 0),
5714 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5715 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5716 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5718 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5719 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5721 wpos_input
= ureg_src(wpos_temp
);
5723 /* MOV wpos_temp, input[wpos]
5725 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5728 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5729 * inversion/identity, or the other way around if we're drawing to an FBO.
5732 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5735 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5737 ureg_scalar(wpostrans
, 0),
5738 ureg_scalar(wpostrans
, 1));
5740 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5743 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5745 ureg_scalar(wpostrans
, 2),
5746 ureg_scalar(wpostrans
, 3));
5749 /* Use wpos_temp as position input from here on:
5751 *wpos
= ureg_src(wpos_temp
);
5756 * Emit fragment position/ooordinate code.
5759 emit_wpos(struct st_context
*st
,
5760 struct st_translate
*t
,
5761 const struct gl_program
*program
,
5762 struct ureg_program
*ureg
,
5763 int wpos_transform_const
)
5765 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5766 GLfloat adjX
= 0.0f
;
5767 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5768 boolean invert
= FALSE
;
5770 /* Query the pixel center conventions supported by the pipe driver and set
5771 * adjX, adjY to help out if it cannot handle the requested one internally.
5773 * The bias of the y-coordinate depends on whether y-inversion takes place
5774 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5775 * drawing to an FBO (causes additional inversion), and whether the pipe
5776 * driver origin and the requested origin differ (the latter condition is
5777 * stored in the 'invert' variable).
5779 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5781 * center shift only:
5786 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5787 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5788 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5789 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5791 * inversion and center shift:
5792 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5793 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5794 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5795 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5797 if (program
->OriginUpperLeft
) {
5798 /* Fragment shader wants origin in upper-left */
5799 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5800 /* the driver supports upper-left origin */
5802 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5803 /* the driver supports lower-left origin, need to invert Y */
5804 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5805 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5812 /* Fragment shader wants origin in lower-left */
5813 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5814 /* the driver supports lower-left origin */
5815 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5816 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5817 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5818 /* the driver supports upper-left origin, need to invert Y */
5824 if (program
->PixelCenterInteger
) {
5825 /* Fragment shader wants pixel center integer */
5826 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5827 /* the driver supports pixel center integer */
5829 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5830 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5832 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5833 /* the driver supports pixel center half integer, need to bias X,Y */
5842 /* Fragment shader wants pixel center half integer */
5843 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5844 /* the driver supports pixel center half integer */
5846 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5847 /* the driver supports pixel center integer, need to bias X,Y */
5848 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5849 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5850 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5856 /* we invert after adjustment so that we avoid the MOV to temporary,
5857 * and reuse the adjustment ADD instead */
5858 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5862 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5863 * TGSI uses +1 for front, -1 for back.
5864 * This function converts the TGSI value to the GL value. Simply clamping/
5865 * saturating the value to [0,1] does the job.
5868 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5870 struct ureg_program
*ureg
= t
->ureg
;
5871 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5872 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5874 if (ctx
->Const
.NativeIntegers
) {
5875 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5878 /* MOV_SAT face_temp, input[face] */
5879 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5882 /* Use face_temp as face input from here on: */
5883 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5887 emit_compute_block_size(const struct gl_program
*prog
,
5888 struct ureg_program
*ureg
) {
5889 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5890 prog
->info
.cs
.local_size
[0]);
5891 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
5892 prog
->info
.cs
.local_size
[1]);
5893 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
5894 prog
->info
.cs
.local_size
[2]);
5897 struct sort_inout_decls
{
5898 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
5899 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
5902 const GLuint
*mapping
;
5905 /* Sort the given array of decls by the corresponding slot (TGSI file index).
5907 * This is for the benefit of older drivers which are broken when the
5908 * declarations aren't sorted in this way.
5911 sort_inout_decls_by_slot(struct inout_decl
*decls
,
5913 const GLuint mapping
[])
5915 sort_inout_decls sorter
;
5916 sorter
.mapping
= mapping
;
5917 std::sort(decls
, decls
+ count
, sorter
);
5921 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
5923 switch (glsl_qual
) {
5924 case INTERP_MODE_NONE
:
5925 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
5926 return TGSI_INTERPOLATE_COLOR
;
5927 return TGSI_INTERPOLATE_PERSPECTIVE
;
5928 case INTERP_MODE_SMOOTH
:
5929 return TGSI_INTERPOLATE_PERSPECTIVE
;
5930 case INTERP_MODE_FLAT
:
5931 return TGSI_INTERPOLATE_CONSTANT
;
5932 case INTERP_MODE_NOPERSPECTIVE
:
5933 return TGSI_INTERPOLATE_LINEAR
;
5935 assert(0 && "unexpected interp mode in st_translate_interp()");
5936 return TGSI_INTERPOLATE_PERSPECTIVE
;
5941 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5942 * \param program the program to translate
5943 * \param numInputs number of input registers used
5944 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5946 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5947 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5949 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5950 * \param numOutputs number of output registers used
5951 * \param outputMapping maps Mesa fragment program outputs to TGSI
5953 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5954 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5957 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5959 extern "C" enum pipe_error
5960 st_translate_program(
5961 struct gl_context
*ctx
,
5963 struct ureg_program
*ureg
,
5964 glsl_to_tgsi_visitor
*program
,
5965 const struct gl_program
*proginfo
,
5967 const GLuint inputMapping
[],
5968 const GLuint inputSlotToAttr
[],
5969 const ubyte inputSemanticName
[],
5970 const ubyte inputSemanticIndex
[],
5971 const GLuint interpMode
[],
5973 const GLuint outputMapping
[],
5974 const GLuint outputSlotToAttr
[],
5975 const ubyte outputSemanticName
[],
5976 const ubyte outputSemanticIndex
[])
5978 struct st_translate
*t
;
5980 struct gl_program_constants
*frag_const
=
5981 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
5982 enum pipe_error ret
= PIPE_OK
;
5984 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5985 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5987 t
= CALLOC_STRUCT(st_translate
);
5989 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5993 t
->procType
= procType
;
5994 t
->inputMapping
= inputMapping
;
5995 t
->outputMapping
= outputMapping
;
5997 t
->num_temp_arrays
= program
->next_array
;
5998 if (t
->num_temp_arrays
)
5999 t
->arrays
= (struct ureg_dst
*)
6000 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6003 * Declare input attributes.
6006 case PIPE_SHADER_FRAGMENT
:
6007 case PIPE_SHADER_GEOMETRY
:
6008 case PIPE_SHADER_TESS_EVAL
:
6009 case PIPE_SHADER_TESS_CTRL
:
6010 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6012 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6013 struct inout_decl
*decl
= &program
->inputs
[i
];
6014 unsigned slot
= inputMapping
[decl
->mesa_index
];
6015 struct ureg_src src
;
6016 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6018 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6019 if (tgsi_usage_mask
== 1)
6020 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6021 else if (tgsi_usage_mask
== 2)
6022 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6024 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6027 unsigned interp_mode
= 0;
6028 unsigned interp_location
= 0;
6029 if (procType
== PIPE_SHADER_FRAGMENT
) {
6031 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6033 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6035 interp_location
= decl
->interp_loc
;
6038 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6039 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6040 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6041 decl
->array_id
, decl
->size
);
6043 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6044 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6045 /* The ArrayID is set up in dst_register */
6046 t
->inputs
[slot
+ j
] = src
;
6047 t
->inputs
[slot
+ j
].ArrayID
= 0;
6048 t
->inputs
[slot
+ j
].Index
+= j
;
6053 case PIPE_SHADER_VERTEX
:
6054 for (i
= 0; i
< numInputs
; i
++) {
6055 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6058 case PIPE_SHADER_COMPUTE
:
6065 * Declare output attributes.
6068 case PIPE_SHADER_FRAGMENT
:
6069 case PIPE_SHADER_COMPUTE
:
6071 case PIPE_SHADER_GEOMETRY
:
6072 case PIPE_SHADER_TESS_EVAL
:
6073 case PIPE_SHADER_TESS_CTRL
:
6074 case PIPE_SHADER_VERTEX
:
6075 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6077 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6078 struct inout_decl
*decl
= &program
->outputs
[i
];
6079 unsigned slot
= outputMapping
[decl
->mesa_index
];
6080 struct ureg_dst dst
;
6081 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6083 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6084 if (tgsi_usage_mask
== 1)
6085 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6086 else if (tgsi_usage_mask
== 2)
6087 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6089 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6092 dst
= ureg_DECL_output_layout(ureg
,
6093 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6094 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6096 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6097 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6098 /* The ArrayID is set up in dst_register */
6099 t
->outputs
[slot
+ j
] = dst
;
6100 t
->outputs
[slot
+ j
].ArrayID
= 0;
6101 t
->outputs
[slot
+ j
].Index
+= j
;
6110 if (procType
== PIPE_SHADER_FRAGMENT
) {
6111 if (program
->shader
->info
.EarlyFragmentTests
)
6112 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6114 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6115 /* Must do this after setting up t->inputs. */
6116 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6117 program
->wpos_transform_const
);
6120 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6121 emit_face_var(ctx
, t
);
6123 for (i
= 0; i
< numOutputs
; i
++) {
6124 switch (outputSemanticName
[i
]) {
6125 case TGSI_SEMANTIC_POSITION
:
6126 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6127 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6128 outputSemanticIndex
[i
]);
6129 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6131 case TGSI_SEMANTIC_STENCIL
:
6132 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6133 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6134 outputSemanticIndex
[i
]);
6135 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6137 case TGSI_SEMANTIC_COLOR
:
6138 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6139 TGSI_SEMANTIC_COLOR
,
6140 outputSemanticIndex
[i
]);
6142 case TGSI_SEMANTIC_SAMPLEMASK
:
6143 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6144 TGSI_SEMANTIC_SAMPLEMASK
,
6145 outputSemanticIndex
[i
]);
6146 /* TODO: If we ever support more than 32 samples, this will have
6147 * to become an array.
6149 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6152 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6153 ret
= PIPE_ERROR_BAD_INPUT
;
6158 else if (procType
== PIPE_SHADER_VERTEX
) {
6159 for (i
= 0; i
< numOutputs
; i
++) {
6160 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6161 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6163 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6164 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6165 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6170 if (procType
== PIPE_SHADER_COMPUTE
) {
6171 emit_compute_block_size(proginfo
, ureg
);
6174 /* Declare address register.
6176 if (program
->num_address_regs
> 0) {
6177 assert(program
->num_address_regs
<= 3);
6178 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6179 t
->address
[i
] = ureg_DECL_address(ureg
);
6182 /* Declare misc input registers
6185 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6187 for (i
= 0; sysInputs
; i
++) {
6188 if (sysInputs
& (1 << i
)) {
6189 unsigned semName
= _mesa_sysval_to_semantic(i
);
6191 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6193 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6194 semName
== TGSI_SEMANTIC_VERTEXID
) {
6195 /* From Gallium perspective, these system values are always
6196 * integer, and require native integer support. However, if
6197 * native integer is supported on the vertex stage but not the
6198 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6199 * assumes these system values are floats. To resolve the
6200 * inconsistency, we insert a U2F.
6202 struct st_context
*st
= st_context(ctx
);
6203 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6204 assert(procType
== PIPE_SHADER_VERTEX
);
6205 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6207 if (!ctx
->Const
.NativeIntegers
) {
6208 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6209 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6210 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6214 if (procType
== PIPE_SHADER_FRAGMENT
&&
6215 semName
== TGSI_SEMANTIC_POSITION
)
6216 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6217 program
->wpos_transform_const
);
6219 sysInputs
&= ~(1 << i
);
6224 t
->array_sizes
= program
->array_sizes
;
6225 t
->input_decls
= program
->inputs
;
6226 t
->num_input_decls
= program
->num_inputs
;
6227 t
->output_decls
= program
->outputs
;
6228 t
->num_output_decls
= program
->num_outputs
;
6230 /* Emit constants and uniforms. TGSI uses a single index space for these,
6231 * so we put all the translated regs in t->constants.
6233 if (proginfo
->Parameters
) {
6234 t
->constants
= (struct ureg_src
*)
6235 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6236 if (t
->constants
== NULL
) {
6237 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6240 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6242 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6243 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6244 case PROGRAM_STATE_VAR
:
6245 case PROGRAM_UNIFORM
:
6246 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6249 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6250 * addressing of the const buffer.
6251 * FIXME: Be smarter and recognize param arrays:
6252 * indirect addressing is only valid within the referenced
6255 case PROGRAM_CONSTANT
:
6256 if (program
->indirect_addr_consts
)
6257 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6259 t
->constants
[i
] = emit_immediate(t
,
6260 proginfo
->Parameters
->ParameterValues
[i
],
6261 proginfo
->Parameters
->Parameters
[i
].DataType
,
6270 if (program
->shader
) {
6271 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6273 for (i
= 0; i
< num_ubos
; i
++) {
6274 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6275 unsigned num_const_vecs
= (size
+ 15) / 16;
6276 unsigned first
, last
;
6277 assert(num_const_vecs
> 0);
6279 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6280 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6284 /* Emit immediate values.
6286 t
->immediates
= (struct ureg_src
*)
6287 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6288 if (t
->immediates
== NULL
) {
6289 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6292 t
->num_immediates
= program
->num_immediates
;
6295 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6296 assert(i
< program
->num_immediates
);
6297 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6299 assert(i
== program
->num_immediates
);
6301 /* texture samplers */
6302 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6303 if (program
->samplers_used
& (1u << i
)) {
6306 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6308 switch (program
->sampler_types
[i
]) {
6310 type
= TGSI_RETURN_TYPE_SINT
;
6312 case GLSL_TYPE_UINT
:
6313 type
= TGSI_RETURN_TYPE_UINT
;
6315 case GLSL_TYPE_FLOAT
:
6316 type
= TGSI_RETURN_TYPE_FLOAT
;
6319 unreachable("not reached");
6322 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6323 type
, type
, type
, type
);
6327 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6328 if (program
->buffers_used
& (1 << i
)) {
6329 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6333 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6335 if (program
->buffers_used
& (1 << i
)) {
6336 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6340 if (program
->use_shared_memory
)
6341 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6343 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6344 if (program
->images_used
& (1 << i
)) {
6345 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6346 program
->image_targets
[i
],
6347 program
->image_formats
[i
],
6352 /* Emit each instruction in turn:
6354 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6355 compile_tgsi_instruction(t
, inst
);
6357 /* Set the next shader stage hint for VS and TES. */
6359 case PIPE_SHADER_VERTEX
:
6360 case PIPE_SHADER_TESS_EVAL
:
6361 if (program
->shader_program
->SeparateShader
)
6364 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6365 if (program
->shader_program
->_LinkedShaders
[i
]) {
6369 case MESA_SHADER_TESS_CTRL
:
6370 next
= PIPE_SHADER_TESS_CTRL
;
6372 case MESA_SHADER_TESS_EVAL
:
6373 next
= PIPE_SHADER_TESS_EVAL
;
6375 case MESA_SHADER_GEOMETRY
:
6376 next
= PIPE_SHADER_GEOMETRY
;
6378 case MESA_SHADER_FRAGMENT
:
6379 next
= PIPE_SHADER_FRAGMENT
;
6386 ureg_set_next_shader_processor(ureg
, next
);
6398 t
->num_constants
= 0;
6399 free(t
->immediates
);
6400 t
->num_immediates
= 0;
6406 /* ----------------------------- End TGSI code ------------------------------ */
6410 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6411 * generating Mesa IR.
6413 static struct gl_program
*
6414 get_mesa_program_tgsi(struct gl_context
*ctx
,
6415 struct gl_shader_program
*shader_program
,
6416 struct gl_linked_shader
*shader
)
6418 glsl_to_tgsi_visitor
* v
;
6419 struct gl_program
*prog
;
6420 struct gl_shader_compiler_options
*options
=
6421 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6422 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6423 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6425 validate_ir_tree(shader
->ir
);
6427 prog
= shader
->Program
;
6429 prog
->Parameters
= _mesa_new_parameter_list();
6430 v
= new glsl_to_tgsi_visitor();
6433 v
->shader_program
= shader_program
;
6435 v
->options
= options
;
6436 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6437 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6439 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6440 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6441 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6442 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6444 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6447 /* Remove reads from output registers. */
6448 lower_output_reads(shader
->Stage
, shader
->ir
);
6450 /* Emit intermediate IR for main(). */
6451 visit_exec_list(shader
->ir
, v
);
6454 /* Print out some information (for debugging purposes) used by the
6455 * optimization passes. */
6458 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6459 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6460 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6461 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6463 for (i
= 0; i
< v
->next_temp
; i
++) {
6464 first_writes
[i
] = -1;
6465 first_reads
[i
] = -1;
6466 last_writes
[i
] = -1;
6469 v
->get_first_temp_read(first_reads
);
6470 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6471 v
->get_last_temp_write(last_writes
);
6472 for (i
= 0; i
< v
->next_temp
; i
++)
6473 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6477 ralloc_free(first_writes
);
6478 ralloc_free(first_reads
);
6479 ralloc_free(last_writes
);
6480 ralloc_free(last_reads
);
6484 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6487 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6488 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6489 v
->copy_propagate();
6491 while (v
->eliminate_dead_code());
6493 v
->merge_two_dsts();
6494 v
->merge_registers();
6495 v
->renumber_registers();
6497 /* Write the END instruction. */
6498 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6500 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6502 _mesa_log("GLSL IR for linked %s program %d:\n",
6503 _mesa_shader_stage_to_string(shader
->Stage
),
6504 shader_program
->Name
);
6505 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6509 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6510 _mesa_copy_linked_program_data(shader_program
, shader
);
6511 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6512 &prog
->info
.inputs_read
,
6513 prog
->info
.double_inputs_read
,
6514 &prog
->info
.patch_inputs_read
);
6515 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6516 &prog
->info
.outputs_written
, 0ULL,
6517 &prog
->info
.patch_outputs_written
);
6518 count_resources(v
, prog
);
6520 /* The GLSL IR won't be needed anymore. */
6521 ralloc_free(shader
->ir
);
6524 /* This must be done before the uniform storage is associated. */
6525 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6526 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6527 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6528 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6529 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6532 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6533 wposTransformState
);
6536 /* Avoid reallocation of the program parameter list, because the uniform
6537 * storage is only associated with the original parameter list.
6538 * This should be enough for Bitmap and DrawPixels constants.
6540 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6542 /* This has to be done last. Any operation the can cause
6543 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6544 * program constant) has to happen before creating this linkage.
6546 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6547 if (!shader_program
->data
->LinkStatus
) {
6548 free_glsl_to_tgsi_visitor(v
);
6549 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6553 struct st_vertex_program
*stvp
;
6554 struct st_fragment_program
*stfp
;
6555 struct st_geometry_program
*stgp
;
6556 struct st_tessctrl_program
*sttcp
;
6557 struct st_tesseval_program
*sttep
;
6558 struct st_compute_program
*stcp
;
6560 switch (shader
->Stage
) {
6561 case MESA_SHADER_VERTEX
:
6562 stvp
= (struct st_vertex_program
*)prog
;
6563 stvp
->glsl_to_tgsi
= v
;
6565 case MESA_SHADER_FRAGMENT
:
6566 stfp
= (struct st_fragment_program
*)prog
;
6567 stfp
->glsl_to_tgsi
= v
;
6569 case MESA_SHADER_GEOMETRY
:
6570 stgp
= (struct st_geometry_program
*)prog
;
6571 stgp
->glsl_to_tgsi
= v
;
6573 case MESA_SHADER_TESS_CTRL
:
6574 sttcp
= (struct st_tessctrl_program
*)prog
;
6575 sttcp
->glsl_to_tgsi
= v
;
6577 case MESA_SHADER_TESS_EVAL
:
6578 sttep
= (struct st_tesseval_program
*)prog
;
6579 sttep
->glsl_to_tgsi
= v
;
6581 case MESA_SHADER_COMPUTE
:
6582 stcp
= (struct st_compute_program
*)prog
;
6583 stcp
->glsl_to_tgsi
= v
;
6586 assert(!"should not be reached");
6594 set_affected_state_flags(uint64_t *states
,
6595 struct gl_program
*prog
,
6596 struct gl_linked_shader
*shader
,
6597 uint64_t new_constants
,
6598 uint64_t new_sampler_views
,
6599 uint64_t new_samplers
,
6600 uint64_t new_images
,
6603 uint64_t new_atomics
)
6605 if (prog
->Parameters
->NumParameters
)
6606 *states
|= new_constants
;
6608 if (shader
->num_samplers
)
6609 *states
|= new_sampler_views
| new_samplers
;
6611 if (shader
->NumImages
)
6612 *states
|= new_images
;
6614 if (shader
->NumUniformBlocks
)
6615 *states
|= new_ubos
;
6617 if (shader
->NumShaderStorageBlocks
)
6618 *states
|= new_ssbos
;
6620 if (prog
->info
.num_abos
)
6621 *states
|= new_atomics
;
6624 static struct gl_program
*
6625 get_mesa_program(struct gl_context
*ctx
,
6626 struct gl_shader_program
*shader_program
,
6627 struct gl_linked_shader
*shader
)
6629 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6630 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6631 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6632 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6633 struct gl_program
*prog
= NULL
;
6635 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6636 /* TODO only for GLSL VS/FS for now: */
6637 switch (shader
->Stage
) {
6638 case MESA_SHADER_VERTEX
:
6639 case MESA_SHADER_FRAGMENT
:
6640 prog
= st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6645 prog
= get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6651 /* This determines which states will be updated when the shader is
6654 switch (shader
->Stage
) {
6655 case MESA_SHADER_VERTEX
:
6656 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6658 *states
= ST_NEW_VS_STATE
|
6660 ST_NEW_VERTEX_ARRAYS
;
6662 set_affected_state_flags(states
, prog
, shader
,
6663 ST_NEW_VS_CONSTANTS
,
6664 ST_NEW_VS_SAMPLER_VIEWS
,
6665 ST_NEW_RENDER_SAMPLERS
,
6672 case MESA_SHADER_TESS_CTRL
:
6673 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6675 *states
= ST_NEW_TCS_STATE
;
6677 set_affected_state_flags(states
, prog
, shader
,
6678 ST_NEW_TCS_CONSTANTS
,
6679 ST_NEW_TCS_SAMPLER_VIEWS
,
6680 ST_NEW_RENDER_SAMPLERS
,
6684 ST_NEW_TCS_ATOMICS
);
6687 case MESA_SHADER_TESS_EVAL
:
6688 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6690 *states
= ST_NEW_TES_STATE
|
6693 set_affected_state_flags(states
, prog
, shader
,
6694 ST_NEW_TES_CONSTANTS
,
6695 ST_NEW_TES_SAMPLER_VIEWS
,
6696 ST_NEW_RENDER_SAMPLERS
,
6700 ST_NEW_TES_ATOMICS
);
6703 case MESA_SHADER_GEOMETRY
:
6704 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6706 *states
= ST_NEW_GS_STATE
|
6709 set_affected_state_flags(states
, prog
, shader
,
6710 ST_NEW_GS_CONSTANTS
,
6711 ST_NEW_GS_SAMPLER_VIEWS
,
6712 ST_NEW_RENDER_SAMPLERS
,
6719 case MESA_SHADER_FRAGMENT
:
6720 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6722 /* gl_FragCoord and glDrawPixels always use constants. */
6723 *states
= ST_NEW_FS_STATE
|
6724 ST_NEW_SAMPLE_SHADING
|
6725 ST_NEW_FS_CONSTANTS
;
6727 set_affected_state_flags(states
, prog
, shader
,
6728 ST_NEW_FS_CONSTANTS
,
6729 ST_NEW_FS_SAMPLER_VIEWS
,
6730 ST_NEW_RENDER_SAMPLERS
,
6737 case MESA_SHADER_COMPUTE
:
6738 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6740 *states
= ST_NEW_CS_STATE
;
6742 set_affected_state_flags(states
, prog
, shader
,
6743 ST_NEW_CS_CONSTANTS
,
6744 ST_NEW_CS_SAMPLER_VIEWS
,
6753 unreachable("unhandled shader stage");
6765 * Called via ctx->Driver.LinkShader()
6766 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6767 * with code lowering and other optimizations.
6770 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6772 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6773 assert(prog
->data
->LinkStatus
);
6775 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6776 if (prog
->_LinkedShaders
[i
] == NULL
)
6780 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6781 gl_shader_stage stage
= prog
->_LinkedShaders
[i
]->Stage
;
6782 const struct gl_shader_compiler_options
*options
=
6783 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6784 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6785 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6786 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6787 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6788 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6789 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6790 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6792 /* If there are forms of indirect addressing that the driver
6793 * cannot handle, perform the lowering pass.
6795 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6796 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6797 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6798 options
->EmitNoIndirectInput
,
6799 options
->EmitNoIndirectOutput
,
6800 options
->EmitNoIndirectTemp
,
6801 options
->EmitNoIndirectUniform
);
6804 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6805 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6806 LOWER_UNPACK_SNORM_2x16
|
6807 LOWER_PACK_UNORM_2x16
|
6808 LOWER_UNPACK_UNORM_2x16
|
6809 LOWER_PACK_SNORM_4x8
|
6810 LOWER_UNPACK_SNORM_4x8
|
6811 LOWER_UNPACK_UNORM_4x8
|
6812 LOWER_PACK_UNORM_4x8
;
6814 if (ctx
->Extensions
.ARB_gpu_shader5
)
6815 lower_inst
|= LOWER_PACK_USE_BFI
|
6817 if (!ctx
->st
->has_half_float_packing
)
6818 lower_inst
|= LOWER_PACK_HALF_2x16
|
6819 LOWER_UNPACK_HALF_2x16
;
6821 lower_packing_builtins(ir
, lower_inst
);
6824 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6825 lower_offset_arrays(ir
);
6826 do_mat_op_to_vec(ir
);
6827 lower_instructions(ir
,
6833 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6836 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6837 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6838 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6839 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6840 /* Assume that if ARB_gpu_shader5 is not supported
6841 * then all of the extended integer functions need
6842 * lowering. It may be necessary to add some caps
6843 * for individual instructions.
6845 (!ctx
->Extensions
.ARB_gpu_shader5
6846 ? BIT_COUNT_TO_MATH
|
6850 FIND_LSB_TO_FLOAT_CAST
|
6851 FIND_MSB_TO_FLOAT_CAST
|
6855 do_vec_index_to_cond_assign(ir
);
6856 lower_vector_insert(ir
, true);
6857 lower_quadop_vector(ir
, false);
6859 if (options
->MaxIfDepth
== 0) {
6866 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6868 progress
= do_common_optimization(ir
, true, true, options
,
6869 ctx
->Const
.NativeIntegers
)
6872 progress
= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6873 options
->MaxIfDepth
, if_threshold
) ||
6878 validate_ir_tree(ir
);
6881 build_program_resource_list(ctx
, prog
);
6883 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6884 struct gl_program
*linked_prog
;
6886 if (prog
->_LinkedShaders
[i
] == NULL
)
6889 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6892 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6893 _mesa_shader_stage_to_program(i
),
6895 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6906 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6907 const GLuint outputMapping
[],
6908 struct pipe_stream_output_info
*so
)
6910 struct gl_transform_feedback_info
*info
=
6911 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6912 st_translate_stream_output_info2(info
, outputMapping
, so
);
6916 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
6917 const GLuint outputMapping
[],
6918 struct pipe_stream_output_info
*so
)
6922 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6923 so
->output
[i
].register_index
=
6924 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6925 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6926 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6927 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6928 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6929 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6932 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6933 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6935 so
->num_outputs
= info
->NumOutputs
;