2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
57 #include "st_shader_cache.h"
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
65 #define MAX_GLSL_TEXTURE_OFFSET 4
70 static int swizzle_for_size(int size
);
72 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
74 unsigned num_elements
= 4;
77 type
= type
->without_array();
78 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
79 num_elements
= type
->vector_elements
;
82 int swizzle
= swizzle_for_size(num_elements
);
83 assert(num_elements
+ component
<= 4);
85 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
90 * This struct is a corresponding struct to TGSI ureg_src.
94 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
95 int component
= 0, unsigned array_id
= 0)
97 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
100 this->swizzle
= swizzle_for_type(type
, component
);
104 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
105 this->reladdr
= NULL
;
106 this->reladdr2
= NULL
;
107 this->has_index2
= false;
108 this->double_reg2
= false;
109 this->array_id
= array_id
;
110 this->is_double_vertex_input
= false;
113 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
115 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
120 this->swizzle
= SWIZZLE_XYZW
;
123 this->reladdr
= NULL
;
124 this->reladdr2
= NULL
;
125 this->has_index2
= false;
126 this->double_reg2
= false;
128 this->is_double_vertex_input
= false;
131 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
133 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
137 this->index2D
= index2D
;
138 this->swizzle
= SWIZZLE_XYZW
;
141 this->reladdr
= NULL
;
142 this->reladdr2
= NULL
;
143 this->has_index2
= false;
144 this->double_reg2
= false;
146 this->is_double_vertex_input
= false;
151 this->type
= GLSL_TYPE_ERROR
;
152 this->file
= PROGRAM_UNDEFINED
;
158 this->reladdr
= NULL
;
159 this->reladdr2
= NULL
;
160 this->has_index2
= false;
161 this->double_reg2
= false;
163 this->is_double_vertex_input
= false;
166 explicit st_src_reg(st_dst_reg reg
);
168 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
170 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
171 int negate
:4; /**< NEGATE_XYZW mask from mesa */
173 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
174 unsigned has_index2
:1;
175 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
177 * Is this the second half of a double register pair?
178 * currently used for input mapping only.
180 unsigned double_reg2
:1;
181 unsigned is_double_vertex_input
:1;
182 unsigned array_id
:10;
184 /** Register index should be offset by the integer in this reg. */
186 st_src_reg
*reladdr2
;
190 st_src_reg reg
= *this;
199 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
201 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
205 this->writemask
= writemask
;
206 this->reladdr
= NULL
;
207 this->reladdr2
= NULL
;
208 this->has_index2
= false;
213 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
215 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
219 this->writemask
= writemask
;
220 this->reladdr
= NULL
;
221 this->reladdr2
= NULL
;
222 this->has_index2
= false;
229 this->type
= GLSL_TYPE_ERROR
;
230 this->file
= PROGRAM_UNDEFINED
;
234 this->reladdr
= NULL
;
235 this->reladdr2
= NULL
;
236 this->has_index2
= false;
240 explicit st_dst_reg(st_src_reg reg
);
242 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
244 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
245 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
246 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
247 unsigned has_index2
:1;
248 unsigned array_id
:10;
250 /** Register index should be offset by the integer in this reg. */
252 st_src_reg
*reladdr2
;
255 st_src_reg::st_src_reg(st_dst_reg reg
)
257 this->type
= reg
.type
;
258 this->file
= reg
.file
;
259 this->index
= reg
.index
;
260 this->swizzle
= SWIZZLE_XYZW
;
263 this->reladdr
= reg
.reladdr
;
264 this->index2D
= reg
.index2D
;
265 this->reladdr2
= reg
.reladdr2
;
266 this->has_index2
= reg
.has_index2
;
267 this->double_reg2
= false;
268 this->array_id
= reg
.array_id
;
269 this->is_double_vertex_input
= false;
272 st_dst_reg::st_dst_reg(st_src_reg reg
)
274 this->type
= reg
.type
;
275 this->file
= reg
.file
;
276 this->index
= reg
.index
;
277 this->writemask
= WRITEMASK_XYZW
;
278 this->reladdr
= reg
.reladdr
;
279 this->index2D
= reg
.index2D
;
280 this->reladdr2
= reg
.reladdr2
;
281 this->has_index2
= reg
.has_index2
;
282 this->array_id
= reg
.array_id
;
285 class glsl_to_tgsi_instruction
: public exec_node
{
287 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
291 st_src_reg resource
; /**< sampler or buffer register */
292 st_src_reg
*tex_offsets
;
294 /** Pointer to the ir source this tree came from for debugging */
297 unsigned op
:8; /**< TGSI opcode */
299 unsigned is_64bit_expanded
:1;
300 unsigned sampler_base
:5;
301 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
302 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
303 glsl_base_type tex_type
:5;
304 unsigned tex_shadow
:1;
305 unsigned image_format
:9;
306 unsigned tex_offset_num_offset
:3;
307 unsigned dead_mask
:4; /**< Used in dead code elimination */
308 unsigned buffer_access
:3; /**< buffer access type */
310 const struct tgsi_opcode_info
*info
;
313 class variable_storage
: public exec_node
{
315 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
316 unsigned array_id
= 0)
317 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
319 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
322 gl_register_file file
;
325 /* Explicit component location. This is given in terms of the GLSL-style
326 * swizzles where each double is a single component, i.e. for 64-bit types
327 * it can only be 0 or 1.
330 ir_variable
*var
; /* variable that maps to this, if any */
334 class immediate_storage
: public exec_node
{
336 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
338 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
339 this->size32
= size32
;
343 /* doubles are stored across 2 gl_constant_values */
344 gl_constant_value values
[4];
345 int size32
; /**< Number of 32-bit components (1-4) */
346 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
349 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
350 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
354 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
357 unsigned gs_out_streams
;
358 enum glsl_interp_mode interp
;
359 enum glsl_base_type base_type
;
360 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
363 static struct inout_decl
*
364 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
366 assert(array_id
!= 0);
368 for (unsigned i
= 0; i
< count
; i
++) {
369 struct inout_decl
*decl
= &decls
[i
];
371 if (array_id
== decl
->array_id
) {
379 static enum glsl_base_type
380 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
383 return GLSL_TYPE_ERROR
;
384 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
386 return decl
->base_type
;
387 return GLSL_TYPE_ERROR
;
390 struct rename_reg_pair
{
395 struct glsl_to_tgsi_visitor
: public ir_visitor
{
397 glsl_to_tgsi_visitor();
398 ~glsl_to_tgsi_visitor();
400 struct gl_context
*ctx
;
401 struct gl_program
*prog
;
402 struct gl_shader_program
*shader_program
;
403 struct gl_linked_shader
*shader
;
404 struct gl_shader_compiler_options
*options
;
408 unsigned *array_sizes
;
409 unsigned max_num_arrays
;
412 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
414 unsigned num_input_arrays
;
415 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
416 unsigned num_outputs
;
417 unsigned num_output_arrays
;
419 int num_address_regs
;
420 uint32_t samplers_used
;
421 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
422 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
425 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
426 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
427 bool indirect_addr_consts
;
428 int wpos_transform_const
;
431 bool native_integers
;
434 bool use_shared_memory
;
436 variable_storage
*find_variable_storage(ir_variable
*var
);
438 int add_constant(gl_register_file file
, gl_constant_value values
[8],
439 int size
, int datatype
, uint16_t *swizzle_out
);
441 st_src_reg
get_temp(const glsl_type
*type
);
442 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
444 st_src_reg
st_src_reg_for_double(double val
);
445 st_src_reg
st_src_reg_for_float(float val
);
446 st_src_reg
st_src_reg_for_int(int val
);
447 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
450 * \name Visit methods
452 * As typical for the visitor pattern, there must be one \c visit method for
453 * each concrete subclass of \c ir_instruction. Virtual base classes within
454 * the hierarchy should not have \c visit methods.
457 virtual void visit(ir_variable
*);
458 virtual void visit(ir_loop
*);
459 virtual void visit(ir_loop_jump
*);
460 virtual void visit(ir_function_signature
*);
461 virtual void visit(ir_function
*);
462 virtual void visit(ir_expression
*);
463 virtual void visit(ir_swizzle
*);
464 virtual void visit(ir_dereference_variable
*);
465 virtual void visit(ir_dereference_array
*);
466 virtual void visit(ir_dereference_record
*);
467 virtual void visit(ir_assignment
*);
468 virtual void visit(ir_constant
*);
469 virtual void visit(ir_call
*);
470 virtual void visit(ir_return
*);
471 virtual void visit(ir_discard
*);
472 virtual void visit(ir_texture
*);
473 virtual void visit(ir_if
*);
474 virtual void visit(ir_emit_vertex
*);
475 virtual void visit(ir_end_primitive
*);
476 virtual void visit(ir_barrier
*);
479 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
481 void visit_atomic_counter_intrinsic(ir_call
*);
482 void visit_ssbo_intrinsic(ir_call
*);
483 void visit_membar_intrinsic(ir_call
*);
484 void visit_shared_intrinsic(ir_call
*);
485 void visit_image_intrinsic(ir_call
*);
489 /** List of variable_storage */
492 /** List of immediate_storage */
493 exec_list immediates
;
494 unsigned num_immediates
;
496 /** List of glsl_to_tgsi_instruction */
497 exec_list instructions
;
499 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
500 st_dst_reg dst
= undef_dst
,
501 st_src_reg src0
= undef_src
,
502 st_src_reg src1
= undef_src
,
503 st_src_reg src2
= undef_src
,
504 st_src_reg src3
= undef_src
);
506 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
507 st_dst_reg dst
, st_dst_reg dst1
,
508 st_src_reg src0
= undef_src
,
509 st_src_reg src1
= undef_src
,
510 st_src_reg src2
= undef_src
,
511 st_src_reg src3
= undef_src
);
513 unsigned get_opcode(unsigned op
,
515 st_src_reg src0
, st_src_reg src1
);
518 * Emit the correct dot-product instruction for the type of arguments
520 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
526 void emit_scalar(ir_instruction
*ir
, unsigned op
,
527 st_dst_reg dst
, st_src_reg src0
);
529 void emit_scalar(ir_instruction
*ir
, unsigned op
,
530 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
532 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
534 void get_deref_offsets(ir_dereference
*ir
,
535 unsigned *array_size
,
540 void calc_deref_offsets(ir_dereference
*tail
,
541 unsigned *array_elements
,
543 st_src_reg
*indirect
,
545 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
547 bool try_emit_mad(ir_expression
*ir
,
549 bool try_emit_mad_for_and_not(ir_expression
*ir
,
552 void emit_swz(ir_expression
*ir
);
554 bool process_move_condition(ir_rvalue
*ir
);
556 void simplify_cmp(void);
558 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
559 void get_first_temp_read(int *first_reads
);
560 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
561 void get_last_temp_write(int *last_writes
);
563 void copy_propagate(void);
564 int eliminate_dead_code(void);
566 void merge_two_dsts(void);
567 void merge_registers(void);
568 void renumber_registers(void);
570 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
571 st_dst_reg
*l
, st_src_reg
*r
,
572 st_src_reg
*cond
, bool cond_swap
);
577 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
578 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
579 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
582 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
585 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
589 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
592 prog
->data
->LinkStatus
= linking_failure
;
596 swizzle_for_size(int size
)
598 static const int size_swizzles
[4] = {
599 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
600 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
601 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
602 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
605 assert((size
>= 1) && (size
<= 4));
606 return size_swizzles
[size
- 1];
610 is_resource_instruction(unsigned opcode
)
613 case TGSI_OPCODE_RESQ
:
614 case TGSI_OPCODE_LOAD
:
615 case TGSI_OPCODE_ATOMUADD
:
616 case TGSI_OPCODE_ATOMXCHG
:
617 case TGSI_OPCODE_ATOMCAS
:
618 case TGSI_OPCODE_ATOMAND
:
619 case TGSI_OPCODE_ATOMOR
:
620 case TGSI_OPCODE_ATOMXOR
:
621 case TGSI_OPCODE_ATOMUMIN
:
622 case TGSI_OPCODE_ATOMUMAX
:
623 case TGSI_OPCODE_ATOMIMIN
:
624 case TGSI_OPCODE_ATOMIMAX
:
632 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
634 return op
->info
->num_dst
;
638 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
640 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
641 op
->info
->num_src
- 1 : op
->info
->num_src
;
644 glsl_to_tgsi_instruction
*
645 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
646 st_dst_reg dst
, st_dst_reg dst1
,
647 st_src_reg src0
, st_src_reg src1
,
648 st_src_reg src2
, st_src_reg src3
)
650 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
651 int num_reladdr
= 0, i
, j
;
652 bool dst_is_64bit
[2];
654 op
= get_opcode(op
, dst
, src0
, src1
);
656 /* If we have to do relative addressing, we want to load the ARL
657 * reg directly for one of the regs, and preload the other reladdr
658 * sources into temps.
660 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
661 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
662 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
663 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
664 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
665 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
667 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
668 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
669 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
670 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
672 if (dst
.reladdr
|| dst
.reladdr2
) {
674 emit_arl(ir
, address_reg
, *dst
.reladdr
);
676 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
680 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
683 assert(num_reladdr
== 0);
685 /* inst->op has only 8 bits. */
686 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
689 inst
->info
= tgsi_get_opcode_info(op
);
696 inst
->is_64bit_expanded
= false;
699 inst
->tex_offsets
= NULL
;
700 inst
->tex_offset_num_offset
= 0;
702 inst
->tex_shadow
= 0;
703 /* default to float, for paths where this is not initialized
704 * (since 0==UINT which is likely wrong):
706 inst
->tex_type
= GLSL_TYPE_FLOAT
;
708 /* Update indirect addressing status used by TGSI */
709 if (dst
.reladdr
|| dst
.reladdr2
) {
711 case PROGRAM_STATE_VAR
:
712 case PROGRAM_CONSTANT
:
713 case PROGRAM_UNIFORM
:
714 this->indirect_addr_consts
= true;
716 case PROGRAM_IMMEDIATE
:
717 assert(!"immediates should not have indirect addressing");
724 for (i
= 0; i
< 4; i
++) {
725 if(inst
->src
[i
].reladdr
) {
726 switch(inst
->src
[i
].file
) {
727 case PROGRAM_STATE_VAR
:
728 case PROGRAM_CONSTANT
:
729 case PROGRAM_UNIFORM
:
730 this->indirect_addr_consts
= true;
732 case PROGRAM_IMMEDIATE
:
733 assert(!"immediates should not have indirect addressing");
743 * This section contains the double processing.
744 * GLSL just represents doubles as single channel values,
745 * however most HW and TGSI represent doubles as pairs of register channels.
747 * so we have to fixup destination writemask/index and src swizzle/indexes.
748 * dest writemasks need to translate from single channel write mask
749 * to a dual-channel writemask, but also need to modify the index,
750 * if we are touching the Z,W fields in the pre-translated writemask.
752 * src channels have similiar index modifications along with swizzle
753 * changes to we pick the XY, ZW pairs from the correct index.
755 * GLSL [0].x -> TGSI [0].xy
756 * GLSL [0].y -> TGSI [0].zw
757 * GLSL [0].z -> TGSI [1].xy
758 * GLSL [0].w -> TGSI [1].zw
760 for (j
= 0; j
< 2; j
++) {
761 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
762 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
763 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
764 if (glsl_base_type_is_64bit(type
))
765 dst_is_64bit
[j
] = true;
769 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
770 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
771 glsl_to_tgsi_instruction
*dinst
= NULL
;
772 int initial_src_swz
[4], initial_src_idx
[4];
773 int initial_dst_idx
[2], initial_dst_writemask
[2];
774 /* select the writemask for dst0 or dst1 */
775 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
777 /* copy out the writemask, index and swizzles for all src/dsts. */
778 for (j
= 0; j
< 2; j
++) {
779 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
780 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
783 for (j
= 0; j
< 4; j
++) {
784 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
785 initial_src_idx
[j
] = inst
->src
[j
].index
;
789 * scan all the components in the dst writemask
790 * generate an instruction for each of them if required.
795 int i
= u_bit_scan(&writemask
);
797 /* before emitting the instruction, see if we have to adjust load / store
799 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
800 addr
.file
== PROGRAM_UNDEFINED
) {
801 /* We have to advance the buffer address by 16 */
802 addr
= get_temp(glsl_type::uint_type
);
803 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
804 inst
->src
[0], st_src_reg_for_int(16));
807 /* first time use previous instruction */
811 /* create a new instructions for subsequent attempts */
812 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
817 this->instructions
.push_tail(dinst
);
818 dinst
->is_64bit_expanded
= true;
820 /* modify the destination if we are splitting */
821 for (j
= 0; j
< 2; j
++) {
822 if (dst_is_64bit
[j
]) {
823 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
824 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
826 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
827 dinst
->src
[0] = addr
;
828 if (dinst
->op
!= TGSI_OPCODE_STORE
)
829 dinst
->dst
[j
].index
++;
832 /* if we aren't writing to a double, just get the bit of the initial writemask
834 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
838 /* modify the src registers */
839 for (j
= 0; j
< 4; j
++) {
840 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
842 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
843 dinst
->src
[j
].index
= initial_src_idx
[j
];
845 dinst
->src
[j
].double_reg2
= true;
846 dinst
->src
[j
].index
++;
850 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
852 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
855 /* some opcodes are special case in what they use as sources
856 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
857 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
858 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
859 op
== TGSI_OPCODE_DLDEXP
||
860 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
861 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
868 this->instructions
.push_tail(inst
);
875 glsl_to_tgsi_instruction
*
876 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
878 st_src_reg src0
, st_src_reg src1
,
879 st_src_reg src2
, st_src_reg src3
)
881 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
885 * Determines whether to use an integer, unsigned integer, or float opcode
886 * based on the operands and input opcode, then emits the result.
889 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
891 st_src_reg src0
, st_src_reg src1
)
893 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
895 if (op
== TGSI_OPCODE_MOV
)
898 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
899 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
900 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
901 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
903 if (is_resource_instruction(op
))
905 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
906 type
= GLSL_TYPE_INT64
;
907 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
908 type
= GLSL_TYPE_UINT64
;
909 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
910 type
= GLSL_TYPE_DOUBLE
;
911 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
912 type
= GLSL_TYPE_FLOAT
;
913 else if (native_integers
)
914 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
916 #define case7(c, f, i, u, d, i64, ui64) \
917 case TGSI_OPCODE_##c: \
918 if (type == GLSL_TYPE_UINT64) \
919 op = TGSI_OPCODE_##ui64; \
920 else if (type == GLSL_TYPE_INT64) \
921 op = TGSI_OPCODE_##i64; \
922 else if (type == GLSL_TYPE_DOUBLE) \
923 op = TGSI_OPCODE_##d; \
924 else if (type == GLSL_TYPE_INT) \
925 op = TGSI_OPCODE_##i; \
926 else if (type == GLSL_TYPE_UINT) \
927 op = TGSI_OPCODE_##u; \
929 op = TGSI_OPCODE_##f; \
931 #define case5(c, f, i, u, d) \
932 case TGSI_OPCODE_##c: \
933 if (type == GLSL_TYPE_DOUBLE) \
934 op = TGSI_OPCODE_##d; \
935 else if (type == GLSL_TYPE_INT) \
936 op = TGSI_OPCODE_##i; \
937 else if (type == GLSL_TYPE_UINT) \
938 op = TGSI_OPCODE_##u; \
940 op = TGSI_OPCODE_##f; \
943 #define case4(c, f, i, u) \
944 case TGSI_OPCODE_##c: \
945 if (type == GLSL_TYPE_INT) \
946 op = TGSI_OPCODE_##i; \
947 else if (type == GLSL_TYPE_UINT) \
948 op = TGSI_OPCODE_##u; \
950 op = TGSI_OPCODE_##f; \
953 #define case3(f, i, u) case4(f, f, i, u)
954 #define case6d(f, i, u, d, i64, u64) case7(f, f, i, u, d, i64, u64)
955 #define case3fid(f, i, d) case5(f, f, i, i, d)
956 #define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
957 #define case2fi(f, i) case4(f, f, i, i)
958 #define case2iu(i, u) case4(i, LAST, i, u)
960 #define case2iu64(i, i64) case7(i, LAST, i, i, LAST, i64, i64)
961 #define case4iu64(i, u, i64, u64) case7(i, LAST, i, u, LAST, i64, u64)
963 #define casecomp(c, f, i, u, d, i64, ui64) \
964 case TGSI_OPCODE_##c: \
965 if (type == GLSL_TYPE_INT64) \
966 op = TGSI_OPCODE_##i64; \
967 else if (type == GLSL_TYPE_UINT64) \
968 op = TGSI_OPCODE_##ui64; \
969 else if (type == GLSL_TYPE_DOUBLE) \
970 op = TGSI_OPCODE_##d; \
971 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
972 op = TGSI_OPCODE_##i; \
973 else if (type == GLSL_TYPE_UINT) \
974 op = TGSI_OPCODE_##u; \
975 else if (native_integers) \
976 op = TGSI_OPCODE_##f; \
978 op = TGSI_OPCODE_##c; \
982 case3fid64(ADD
, UADD
, DADD
, U64ADD
);
983 case3fid64(MUL
, UMUL
, DMUL
, U64MUL
);
984 case3fid(MAD
, UMAD
, DMAD
);
985 case3fid(FMA
, UMAD
, DFMA
);
986 case6d(DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
987 case6d(MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
988 case6d(MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
989 case4iu64(MOD
, UMOD
, I64MOD
, U64MOD
);
991 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
992 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
993 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
994 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
996 case2iu64(SHL
, U64SHL
);
997 case4iu64(ISHR
, USHR
, I64SHR
, U64SHR
);
999 case3fid64(SSG
, ISSG
, DSSG
, I64SSG
);
1001 case2iu(IBFE
, UBFE
);
1002 case2iu(IMSB
, UMSB
);
1003 case2iu(IMUL_HI
, UMUL_HI
);
1005 case3fid(SQRT
, SQRT
, DSQRT
);
1007 case3fid(RCP
, RCP
, DRCP
);
1008 case3fid(RSQ
, RSQ
, DRSQ
);
1010 case3fid(FRC
, FRC
, DFRAC
);
1011 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1012 case3fid(CEIL
, CEIL
, DCEIL
);
1013 case3fid(FLR
, FLR
, DFLR
);
1014 case3fid(ROUND
, ROUND
, DROUND
);
1016 case2iu(ATOMIMAX
, ATOMUMAX
);
1017 case2iu(ATOMIMIN
, ATOMUMIN
);
1022 assert(op
!= TGSI_OPCODE_LAST
);
1026 glsl_to_tgsi_instruction
*
1027 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1028 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1031 static const unsigned dot_opcodes
[] = {
1032 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1035 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1039 * Emits TGSI scalar opcodes to produce unique answers across channels.
1041 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1042 * channel determines the result across all channels. So to do a vec4
1043 * of this operation, we want to emit a scalar per source channel used
1044 * to produce dest channels.
1047 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1049 st_src_reg orig_src0
, st_src_reg orig_src1
)
1052 int done_mask
= ~dst
.writemask
;
1054 /* TGSI RCP is a scalar operation splatting results to all channels,
1055 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1058 for (i
= 0; i
< 4; i
++) {
1059 GLuint this_mask
= (1 << i
);
1060 st_src_reg src0
= orig_src0
;
1061 st_src_reg src1
= orig_src1
;
1063 if (done_mask
& this_mask
)
1066 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1067 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1068 for (j
= i
+ 1; j
< 4; j
++) {
1069 /* If there is another enabled component in the destination that is
1070 * derived from the same inputs, generate its value on this pass as
1073 if (!(done_mask
& (1 << j
)) &&
1074 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1075 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1076 this_mask
|= (1 << j
);
1079 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1080 src0_swiz
, src0_swiz
);
1081 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1082 src1_swiz
, src1_swiz
);
1084 dst
.writemask
= this_mask
;
1085 emit_asm(ir
, op
, dst
, src0
, src1
);
1086 done_mask
|= this_mask
;
1091 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1092 st_dst_reg dst
, st_src_reg src0
)
1094 st_src_reg undef
= undef_src
;
1096 undef
.swizzle
= SWIZZLE_XXXX
;
1098 emit_scalar(ir
, op
, dst
, src0
, undef
);
1102 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1103 st_dst_reg dst
, st_src_reg src0
)
1105 int op
= TGSI_OPCODE_ARL
;
1107 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1108 op
= TGSI_OPCODE_UARL
;
1110 assert(dst
.file
== PROGRAM_ADDRESS
);
1111 if (dst
.index
>= this->num_address_regs
)
1112 this->num_address_regs
= dst
.index
+ 1;
1114 emit_asm(NULL
, op
, dst
, src0
);
1118 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1119 gl_constant_value values
[8], int size
, int datatype
,
1120 uint16_t *swizzle_out
)
1122 if (file
== PROGRAM_CONSTANT
) {
1123 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1124 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1125 size
, datatype
, &swizzle
);
1127 *swizzle_out
= swizzle
;
1131 assert(file
== PROGRAM_IMMEDIATE
);
1134 immediate_storage
*entry
;
1135 int size32
= size
* ((datatype
== GL_DOUBLE
||
1136 datatype
== GL_INT64_ARB
||
1137 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1140 /* Search immediate storage to see if we already have an identical
1141 * immediate that we can use instead of adding a duplicate entry.
1143 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1144 immediate_storage
*tmp
= entry
;
1146 for (i
= 0; i
* 4 < size32
; i
++) {
1147 int slot_size
= MIN2(size32
- (i
* 4), 4);
1148 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1150 if (memcmp(tmp
->values
, &values
[i
* 4],
1151 slot_size
* sizeof(gl_constant_value
)))
1154 /* Everything matches, keep going until the full size is matched */
1155 tmp
= (immediate_storage
*)tmp
->next
;
1158 /* The full value matched */
1159 if (i
* 4 >= size32
)
1165 for (i
= 0; i
* 4 < size32
; i
++) {
1166 int slot_size
= MIN2(size32
- (i
* 4), 4);
1167 /* Add this immediate to the list. */
1168 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1169 this->immediates
.push_tail(entry
);
1170 this->num_immediates
++;
1176 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1178 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1179 union gl_constant_value uval
;
1182 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1188 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1190 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1191 union gl_constant_value uval
[2];
1193 memcpy(uval
, &val
, sizeof(uval
));
1194 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1195 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1200 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1202 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1203 union gl_constant_value uval
;
1205 assert(native_integers
);
1208 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1214 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1216 if (native_integers
)
1217 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1218 st_src_reg_for_int(val
);
1220 return st_src_reg_for_float(val
);
1224 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1226 return st_glsl_attrib_type_size(type
, is_vs_input
);
1230 type_size(const struct glsl_type
*type
)
1232 return st_glsl_type_size(type
);
1236 * If the given GLSL type is an array or matrix or a structure containing
1237 * an array/matrix member, return true. Else return false.
1239 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1240 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1241 * we have an array that might be indexed with a variable, we need to use
1242 * the later storage type.
1245 type_has_array_or_matrix(const glsl_type
*type
)
1247 if (type
->is_array() || type
->is_matrix())
1250 if (type
->is_record()) {
1251 for (unsigned i
= 0; i
< type
->length
; i
++) {
1252 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1263 * In the initial pass of codegen, we assign temporary numbers to
1264 * intermediate results. (not SSA -- variable assignments will reuse
1268 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1272 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1277 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1278 if (next_array
>= max_num_arrays
) {
1279 max_num_arrays
+= 32;
1280 array_sizes
= (unsigned*)
1281 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1284 src
.file
= PROGRAM_ARRAY
;
1286 src
.array_id
= next_array
+ 1;
1287 array_sizes
[next_array
] = type_size(type
);
1291 src
.file
= PROGRAM_TEMPORARY
;
1292 src
.index
= next_temp
;
1293 next_temp
+= type_size(type
);
1296 if (type
->is_array() || type
->is_record()) {
1297 src
.swizzle
= SWIZZLE_NOOP
;
1299 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1306 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1309 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1310 if (entry
->var
== var
)
1318 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1320 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1321 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1322 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1325 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1327 const ir_state_slot
*const slots
= ir
->get_state_slots();
1328 assert(slots
!= NULL
);
1330 /* Check if this statevar's setup in the STATE file exactly
1331 * matches how we'll want to reference it as a
1332 * struct/array/whatever. If not, then we need to move it into
1333 * temporary storage and hope that it'll get copy-propagated
1336 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1337 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1342 variable_storage
*storage
;
1344 if (i
== ir
->get_num_state_slots()) {
1345 /* We'll set the index later. */
1346 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1347 this->variables
.push_tail(storage
);
1351 /* The variable_storage constructor allocates slots based on the size
1352 * of the type. However, this had better match the number of state
1353 * elements that we're going to copy into the new temporary.
1355 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1357 dst
= st_dst_reg(get_temp(ir
->type
));
1359 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1362 this->variables
.push_tail(storage
);
1366 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1367 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1368 (gl_state_index
*)slots
[i
].tokens
);
1370 if (storage
->file
== PROGRAM_STATE_VAR
) {
1371 if (storage
->index
== -1) {
1372 storage
->index
= index
;
1374 assert(index
== storage
->index
+ (int)i
);
1377 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1378 * the data being moved since MOV does not care about the type of
1379 * data it is moving, and we don't want to declare registers with
1380 * array or struct types.
1382 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1383 src
.swizzle
= slots
[i
].swizzle
;
1384 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1385 /* even a float takes up a whole vec4 reg in a struct/array. */
1390 if (storage
->file
== PROGRAM_TEMPORARY
&&
1391 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1392 fail_link(this->shader_program
,
1393 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1394 ir
->name
, dst
.index
- storage
->index
,
1395 type_size(ir
->type
));
1401 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1403 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1405 visit_exec_list(&ir
->body_instructions
, this);
1407 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1411 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1414 case ir_loop_jump::jump_break
:
1415 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1417 case ir_loop_jump::jump_continue
:
1418 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1425 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1432 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1434 /* Ignore function bodies other than main() -- we shouldn't see calls to
1435 * them since they should all be inlined before we get to glsl_to_tgsi.
1437 if (strcmp(ir
->name
, "main") == 0) {
1438 const ir_function_signature
*sig
;
1441 sig
= ir
->matching_signature(NULL
, &empty
, false);
1445 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1452 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1454 int nonmul_operand
= 1 - mul_operand
;
1456 st_dst_reg result_dst
;
1458 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1459 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1462 expr
->operands
[0]->accept(this);
1464 expr
->operands
[1]->accept(this);
1466 ir
->operands
[nonmul_operand
]->accept(this);
1469 this->result
= get_temp(ir
->type
);
1470 result_dst
= st_dst_reg(this->result
);
1471 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1472 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1478 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1480 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1481 * implemented using multiplication, and logical-or is implemented using
1482 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1483 * As result, the logical expression (a & !b) can be rewritten as:
1487 * - (a * 1) - (a * b)
1491 * This final expression can be implemented as a single MAD(a, -b, a)
1495 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1497 const int other_operand
= 1 - try_operand
;
1500 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1501 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1504 ir
->operands
[other_operand
]->accept(this);
1506 expr
->operands
[0]->accept(this);
1509 b
.negate
= ~b
.negate
;
1511 this->result
= get_temp(ir
->type
);
1512 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1518 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1519 st_src_reg
*reg
, int *num_reladdr
)
1521 if (!reg
->reladdr
&& !reg
->reladdr2
)
1524 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1525 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1527 if (*num_reladdr
!= 1) {
1528 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1530 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1538 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1540 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1542 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1544 if (ir
->operation
== ir_binop_add
) {
1545 if (try_emit_mad(ir
, 1))
1547 if (try_emit_mad(ir
, 0))
1551 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1553 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1554 if (try_emit_mad_for_and_not(ir
, 1))
1556 if (try_emit_mad_for_and_not(ir
, 0))
1560 if (ir
->operation
== ir_quadop_vector
)
1561 assert(!"ir_quadop_vector should have been lowered");
1563 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1564 this->result
.file
= PROGRAM_UNDEFINED
;
1565 ir
->operands
[operand
]->accept(this);
1566 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1567 printf("Failed to get tree for expression operand:\n");
1568 ir
->operands
[operand
]->print();
1572 op
[operand
] = this->result
;
1574 /* Matrix expression operands should have been broken down to vector
1575 * operations already.
1577 assert(!ir
->operands
[operand
]->type
->is_matrix());
1580 visit_expression(ir
, op
);
1583 /* The non-recursive part of the expression visitor lives in a separate
1584 * function and should be prevented from being inlined, to avoid a stack
1585 * explosion when deeply nested expressions are visited.
1588 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1590 st_src_reg result_src
;
1591 st_dst_reg result_dst
;
1593 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1594 if (ir
->operands
[1]) {
1595 vector_elements
= MAX2(vector_elements
,
1596 ir
->operands
[1]->type
->vector_elements
);
1599 this->result
.file
= PROGRAM_UNDEFINED
;
1601 /* Storage for our result. Ideally for an assignment we'd be using
1602 * the actual storage for the result here, instead.
1604 result_src
= get_temp(ir
->type
);
1605 /* convenience for the emit functions below. */
1606 result_dst
= st_dst_reg(result_src
);
1607 /* Limit writes to the channels that will be used by result_src later.
1608 * This does limit this temp's use as a temporary for multi-instruction
1611 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1613 switch (ir
->operation
) {
1614 case ir_unop_logic_not
:
1615 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1616 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1618 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1619 * older GPUs implement SEQ using multiple instructions (i915 uses two
1620 * SGE instructions and a MUL instruction). Since our logic values are
1621 * 0.0 and 1.0, 1-x also implements !x.
1623 op
[0].negate
= ~op
[0].negate
;
1624 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1628 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1629 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1630 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1631 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1632 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1633 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1635 op
[0].negate
= ~op
[0].negate
;
1639 case ir_unop_subroutine_to_int
:
1640 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1643 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1644 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1645 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1646 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1647 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1648 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1650 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1653 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1656 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1660 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1664 assert(!"not reached: should be handled by ir_explog_to_explog2");
1667 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1670 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1673 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1675 case ir_unop_saturate
: {
1676 glsl_to_tgsi_instruction
*inst
;
1677 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1678 inst
->saturate
= true;
1683 case ir_unop_dFdx_coarse
:
1684 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1686 case ir_unop_dFdx_fine
:
1687 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1690 case ir_unop_dFdy_coarse
:
1691 case ir_unop_dFdy_fine
:
1693 /* The X component contains 1 or -1 depending on whether the framebuffer
1694 * is a FBO or the window system buffer, respectively.
1695 * It is then multiplied with the source operand of DDY.
1697 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1698 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1700 unsigned transform_y_index
=
1701 _mesa_add_state_reference(this->prog
->Parameters
,
1704 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1706 glsl_type::vec4_type
);
1707 transform_y
.swizzle
= SWIZZLE_XXXX
;
1709 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1711 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1712 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1713 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1717 case ir_unop_frexp_sig
:
1718 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1721 case ir_unop_frexp_exp
:
1722 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1725 case ir_unop_noise
: {
1726 /* At some point, a motivated person could add a better
1727 * implementation of noise. Currently not even the nvidia
1728 * binary drivers do anything more than this. In any case, the
1729 * place to do this is in the GL state tracker, not the poor
1732 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1737 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1740 op
[1].negate
= ~op
[1].negate
;
1741 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1745 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1748 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1751 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1752 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1754 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1758 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1760 case ir_binop_greater
:
1761 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1763 case ir_binop_lequal
:
1764 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1766 case ir_binop_gequal
:
1767 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1769 case ir_binop_equal
:
1770 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1772 case ir_binop_nequal
:
1773 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1775 case ir_binop_all_equal
:
1776 /* "==" operator producing a scalar boolean. */
1777 if (ir
->operands
[0]->type
->is_vector() ||
1778 ir
->operands
[1]->type
->is_vector()) {
1779 st_src_reg temp
= get_temp(native_integers
?
1780 glsl_type::uvec4_type
:
1781 glsl_type::vec4_type
);
1783 if (native_integers
) {
1784 st_dst_reg temp_dst
= st_dst_reg(temp
);
1785 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1787 if (ir
->operands
[0]->type
->is_boolean() &&
1788 ir
->operands
[1]->as_constant() &&
1789 ir
->operands
[1]->as_constant()->is_one()) {
1790 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1792 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1795 /* Emit 1-3 AND operations to combine the SEQ results. */
1796 switch (ir
->operands
[0]->type
->vector_elements
) {
1800 temp_dst
.writemask
= WRITEMASK_Y
;
1801 temp1
.swizzle
= SWIZZLE_YYYY
;
1802 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1803 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1806 temp_dst
.writemask
= WRITEMASK_X
;
1807 temp1
.swizzle
= SWIZZLE_XXXX
;
1808 temp2
.swizzle
= SWIZZLE_YYYY
;
1809 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1810 temp_dst
.writemask
= WRITEMASK_Y
;
1811 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1812 temp2
.swizzle
= SWIZZLE_WWWW
;
1813 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1816 temp1
.swizzle
= SWIZZLE_XXXX
;
1817 temp2
.swizzle
= SWIZZLE_YYYY
;
1818 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1820 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1822 /* After the dot-product, the value will be an integer on the
1823 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1825 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1827 /* Negating the result of the dot-product gives values on the range
1828 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1829 * This is achieved using SGE.
1831 st_src_reg sge_src
= result_src
;
1832 sge_src
.negate
= ~sge_src
.negate
;
1833 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1836 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1839 case ir_binop_any_nequal
:
1840 /* "!=" operator producing a scalar boolean. */
1841 if (ir
->operands
[0]->type
->is_vector() ||
1842 ir
->operands
[1]->type
->is_vector()) {
1843 st_src_reg temp
= get_temp(native_integers
?
1844 glsl_type::uvec4_type
:
1845 glsl_type::vec4_type
);
1846 if (ir
->operands
[0]->type
->is_boolean() &&
1847 ir
->operands
[1]->as_constant() &&
1848 ir
->operands
[1]->as_constant()->is_zero()) {
1849 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1851 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1854 if (native_integers
) {
1855 st_dst_reg temp_dst
= st_dst_reg(temp
);
1856 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1858 /* Emit 1-3 OR operations to combine the SNE results. */
1859 switch (ir
->operands
[0]->type
->vector_elements
) {
1863 temp_dst
.writemask
= WRITEMASK_Y
;
1864 temp1
.swizzle
= SWIZZLE_YYYY
;
1865 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1866 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1869 temp_dst
.writemask
= WRITEMASK_X
;
1870 temp1
.swizzle
= SWIZZLE_XXXX
;
1871 temp2
.swizzle
= SWIZZLE_YYYY
;
1872 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1873 temp_dst
.writemask
= WRITEMASK_Y
;
1874 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1875 temp2
.swizzle
= SWIZZLE_WWWW
;
1876 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1879 temp1
.swizzle
= SWIZZLE_XXXX
;
1880 temp2
.swizzle
= SWIZZLE_YYYY
;
1881 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1883 /* After the dot-product, the value will be an integer on the
1884 * range [0,4]. Zero stays zero, and positive values become 1.0.
1886 glsl_to_tgsi_instruction
*const dp
=
1887 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1888 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1889 /* The clamping to [0,1] can be done for free in the fragment
1890 * shader with a saturate.
1892 dp
->saturate
= true;
1894 /* Negating the result of the dot-product gives values on the range
1895 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1896 * achieved using SLT.
1898 st_src_reg slt_src
= result_src
;
1899 slt_src
.negate
= ~slt_src
.negate
;
1900 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1904 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1908 case ir_binop_logic_xor
:
1909 if (native_integers
)
1910 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1912 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1915 case ir_binop_logic_or
: {
1916 if (native_integers
) {
1917 /* If integers are used as booleans, we can use an actual "or"
1920 assert(native_integers
);
1921 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1923 /* After the addition, the value will be an integer on the
1924 * range [0,2]. Zero stays zero, and positive values become 1.0.
1926 glsl_to_tgsi_instruction
*add
=
1927 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1928 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1929 /* The clamping to [0,1] can be done for free in the fragment
1930 * shader with a saturate if floats are being used as boolean values.
1932 add
->saturate
= true;
1934 /* Negating the result of the addition gives values on the range
1935 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1936 * is achieved using SLT.
1938 st_src_reg slt_src
= result_src
;
1939 slt_src
.negate
= ~slt_src
.negate
;
1940 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1946 case ir_binop_logic_and
:
1947 /* If native integers are disabled, the bool args are stored as float 0.0
1948 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1949 * actual AND opcode.
1951 if (native_integers
)
1952 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1954 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1958 assert(ir
->operands
[0]->type
->is_vector());
1959 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1960 emit_dp(ir
, result_dst
, op
[0], op
[1],
1961 ir
->operands
[0]->type
->vector_elements
);
1966 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1968 /* This is the only instruction sequence that makes the game "Risen"
1969 * render correctly. ABS is not required for the game, but since GLSL
1970 * declares negative values as "undefined", allowing us to do whatever
1971 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1974 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1975 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1979 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1982 if (native_integers
) {
1983 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1986 /* fallthrough to next case otherwise */
1988 if (native_integers
) {
1989 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1992 /* fallthrough to next case otherwise */
1995 case ir_unop_i642u64
:
1996 case ir_unop_u642i64
:
1997 /* Converting between signed and unsigned integers is a no-op. */
1999 result_src
.type
= result_dst
.type
;
2002 if (native_integers
) {
2003 /* Booleans are stored as integers using ~0 for true and 0 for false.
2004 * GLSL requires that int(bool) return 1 for true and 0 for false.
2005 * This conversion is done with AND, but it could be done with NEG.
2007 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
2009 /* Booleans and integers are both stored as floats when native
2010 * integers are disabled.
2016 if (native_integers
)
2017 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2019 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2022 if (native_integers
)
2023 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2025 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2027 case ir_unop_bitcast_f2i
:
2028 case ir_unop_bitcast_f2u
:
2029 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2030 if (op
[0].negate
|| op
[0].abs
)
2031 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2034 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2037 case ir_unop_bitcast_i2f
:
2038 case ir_unop_bitcast_u2f
:
2040 result_src
.type
= GLSL_TYPE_FLOAT
;
2043 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2046 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2049 if (native_integers
)
2050 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2052 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2054 case ir_unop_bitcast_u642d
:
2055 case ir_unop_bitcast_i642d
:
2057 result_src
.type
= GLSL_TYPE_DOUBLE
;
2059 case ir_unop_bitcast_d2i64
:
2061 result_src
.type
= GLSL_TYPE_INT64
;
2063 case ir_unop_bitcast_d2u64
:
2065 result_src
.type
= GLSL_TYPE_UINT64
;
2068 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2071 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2074 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2076 case ir_unop_round_even
:
2077 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2080 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2084 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2087 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2090 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2093 case ir_unop_bit_not
:
2094 if (native_integers
) {
2095 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2099 if (native_integers
) {
2100 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2103 case ir_binop_lshift
:
2104 if (native_integers
) {
2105 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2108 case ir_binop_rshift
:
2109 if (native_integers
) {
2110 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2113 case ir_binop_bit_and
:
2114 if (native_integers
) {
2115 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2118 case ir_binop_bit_xor
:
2119 if (native_integers
) {
2120 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2123 case ir_binop_bit_or
:
2124 if (native_integers
) {
2125 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2129 assert(!"GLSL 1.30 features unsupported");
2132 case ir_binop_ubo_load
: {
2133 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2134 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2135 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2136 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2137 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2140 cbuf
.type
= ir
->type
->base_type
;
2141 cbuf
.file
= PROGRAM_CONSTANT
;
2143 cbuf
.reladdr
= NULL
;
2147 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2149 if (const_offset_ir
) {
2150 /* Constant index into constant buffer */
2151 cbuf
.reladdr
= NULL
;
2152 cbuf
.index
= const_offset
/ 16;
2155 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2156 st_src_reg offset
= op
[1];
2158 /* The OpenGL spec is written in such a way that accesses with
2159 * non-constant offset are almost always vec4-aligned. The only
2160 * exception to this are members of structs in arrays of structs:
2161 * each struct in an array of structs is at least vec4-aligned,
2162 * but single-element and [ui]vec2 members of the struct may be at
2163 * an offset that is not a multiple of 16 bytes.
2165 * Here, we extract that offset, relying on previous passes to always
2166 * generate offset expressions of the form (+ expr constant_offset).
2168 * Note that the std430 layout, which allows more cases of alignment
2169 * less than vec4 in arrays, is not supported for uniform blocks, so
2170 * we do not have to deal with it here.
2172 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2173 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2174 if (const_offset_ir
) {
2175 const_offset
= const_offset_ir
->value
.u
[0];
2176 cbuf
.index
= const_offset
/ 16;
2177 offset_expr
->operands
[0]->accept(this);
2178 offset
= this->result
;
2182 /* Relative/variable index into constant buffer */
2183 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2184 st_src_reg_for_int(4));
2185 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2186 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2189 if (const_uniform_block
) {
2190 /* Constant constant buffer */
2191 cbuf
.reladdr2
= NULL
;
2192 cbuf
.index2D
= const_block
;
2193 cbuf
.has_index2
= true;
2196 /* Relative/variable constant buffer */
2197 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2199 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2200 cbuf
.has_index2
= true;
2203 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2204 if (glsl_base_type_is_64bit(cbuf
.type
))
2205 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2206 const_offset
% 16 / 8,
2207 const_offset
% 16 / 8,
2208 const_offset
% 16 / 8);
2210 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2211 const_offset
% 16 / 4,
2212 const_offset
% 16 / 4,
2213 const_offset
% 16 / 4);
2215 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2216 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2218 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2223 /* note: we have to reorder the three args here */
2224 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2227 if (this->ctx
->Const
.NativeIntegers
)
2228 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2230 op
[0].negate
= ~op
[0].negate
;
2231 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2234 case ir_triop_bitfield_extract
:
2235 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2237 case ir_quadop_bitfield_insert
:
2238 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2240 case ir_unop_bitfield_reverse
:
2241 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2243 case ir_unop_bit_count
:
2244 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2246 case ir_unop_find_msb
:
2247 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2249 case ir_unop_find_lsb
:
2250 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2252 case ir_binop_imul_high
:
2253 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2256 /* In theory, MAD is incorrect here. */
2258 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2260 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2262 case ir_unop_interpolate_at_centroid
:
2263 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2265 case ir_binop_interpolate_at_offset
: {
2266 /* The y coordinate needs to be flipped for the default fb */
2267 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2268 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2270 unsigned transform_y_index
=
2271 _mesa_add_state_reference(this->prog
->Parameters
,
2274 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2276 glsl_type::vec4_type
);
2277 transform_y
.swizzle
= SWIZZLE_XXXX
;
2279 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2280 st_dst_reg temp_dst
= st_dst_reg(temp
);
2282 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2283 temp_dst
.writemask
= WRITEMASK_Y
;
2284 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2285 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2288 case ir_binop_interpolate_at_sample
:
2289 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2293 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2296 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2299 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2302 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2305 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2308 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2310 case ir_unop_unpack_double_2x32
:
2311 case ir_unop_pack_double_2x32
:
2312 case ir_unop_unpack_int_2x32
:
2313 case ir_unop_pack_int_2x32
:
2314 case ir_unop_unpack_uint_2x32
:
2315 case ir_unop_pack_uint_2x32
:
2316 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2319 case ir_binop_ldexp
:
2320 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2321 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2323 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2327 case ir_unop_pack_half_2x16
:
2328 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2330 case ir_unop_unpack_half_2x16
:
2331 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2334 case ir_unop_get_buffer_size
: {
2335 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2338 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2339 (const_offset
? const_offset
->value
.u
[0] : 0),
2341 if (!const_offset
) {
2342 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2343 *buffer
.reladdr
= op
[0];
2344 emit_arl(ir
, sampler_reladdr
, op
[0]);
2346 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2350 case ir_unop_vote_any
:
2351 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2353 case ir_unop_vote_all
:
2354 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2356 case ir_unop_vote_eq
:
2357 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2361 case ir_unop_b2i64
: {
2362 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2363 st_dst_reg temp_dst
= st_dst_reg(temp
);
2364 unsigned orig_swz
= op
[0].swizzle
;
2366 * To convert unsigned to 64-bit:
2367 * zero Y channel, copy X channel.
2369 temp_dst
.writemask
= WRITEMASK_Y
;
2370 if (vector_elements
> 1)
2371 temp_dst
.writemask
|= WRITEMASK_W
;
2372 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2373 temp_dst
.writemask
= WRITEMASK_X
;
2374 if (vector_elements
> 1)
2375 temp_dst
.writemask
|= WRITEMASK_Z
;
2376 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2377 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2378 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2379 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2381 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2383 result_src
.type
= GLSL_TYPE_UINT64
;
2384 if (vector_elements
> 2) {
2385 /* Subtle: We rely on the fact that get_temp here returns the next
2386 * TGSI temporary register directly after the temp register used for
2387 * the first two components, so that the result gets picked up
2390 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2391 st_dst_reg temp_dst
= st_dst_reg(temp
);
2392 temp_dst
.writemask
= WRITEMASK_Y
;
2393 if (vector_elements
> 3)
2394 temp_dst
.writemask
|= WRITEMASK_W
;
2395 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2397 temp_dst
.writemask
= WRITEMASK_X
;
2398 if (vector_elements
> 3)
2399 temp_dst
.writemask
|= WRITEMASK_Z
;
2400 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2401 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2402 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2403 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2405 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2412 case ir_unop_i642u
: {
2413 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2414 st_dst_reg temp_dst
= st_dst_reg(temp
);
2415 unsigned orig_swz
= op
[0].swizzle
;
2416 unsigned orig_idx
= op
[0].index
;
2418 temp_dst
.writemask
= WRITEMASK_X
;
2420 for (el
= 0; el
< vector_elements
; el
++) {
2421 unsigned swz
= GET_SWZ(orig_swz
, el
);
2423 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2425 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2427 op
[0].index
= orig_idx
+ 1;
2428 op
[0].type
= GLSL_TYPE_UINT
;
2429 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2430 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2433 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2434 result_src
.type
= GLSL_TYPE_UINT
;
2436 result_src
.type
= GLSL_TYPE_INT
;
2440 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2443 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2446 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2449 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2452 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2455 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2458 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2461 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2464 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2467 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2470 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2472 /* these might be needed */
2473 case ir_unop_pack_snorm_2x16
:
2474 case ir_unop_pack_unorm_2x16
:
2475 case ir_unop_pack_snorm_4x8
:
2476 case ir_unop_pack_unorm_4x8
:
2478 case ir_unop_unpack_snorm_2x16
:
2479 case ir_unop_unpack_unorm_2x16
:
2480 case ir_unop_unpack_snorm_4x8
:
2481 case ir_unop_unpack_unorm_4x8
:
2483 case ir_quadop_vector
:
2484 case ir_binop_vector_extract
:
2485 case ir_triop_vector_insert
:
2486 case ir_binop_carry
:
2487 case ir_binop_borrow
:
2488 case ir_unop_ssbo_unsized_array_length
:
2489 /* This operation is not supported, or should have already been handled.
2491 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2495 this->result
= result_src
;
2500 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2506 /* Note that this is only swizzles in expressions, not those on the left
2507 * hand side of an assignment, which do write masking. See ir_assignment
2511 ir
->val
->accept(this);
2513 assert(src
.file
!= PROGRAM_UNDEFINED
);
2514 assert(ir
->type
->vector_elements
> 0);
2516 for (i
= 0; i
< 4; i
++) {
2517 if (i
< ir
->type
->vector_elements
) {
2520 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2523 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2526 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2529 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2533 /* If the type is smaller than a vec4, replicate the last
2536 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2540 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2545 /* Test if the variable is an array. Note that geometry and
2546 * tessellation shader inputs are outputs are always arrays (except
2547 * for patch inputs), so only the array element type is considered.
2550 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2552 const glsl_type
*type
= var
->type
;
2554 *remove_array
= false;
2556 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2557 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2560 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2561 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2562 stage
== MESA_SHADER_TESS_CTRL
) &&
2564 if (!var
->type
->is_array())
2565 return false; /* a system value probably */
2567 type
= var
->type
->fields
.array
;
2568 *remove_array
= true;
2571 return type
->is_array() || type
->is_matrix();
2575 st_translate_interp_loc(ir_variable
*var
)
2577 if (var
->data
.centroid
)
2578 return TGSI_INTERPOLATE_LOC_CENTROID
;
2579 else if (var
->data
.sample
)
2580 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2582 return TGSI_INTERPOLATE_LOC_CENTER
;
2586 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2588 variable_storage
*entry
= find_variable_storage(ir
->var
);
2589 ir_variable
*var
= ir
->var
;
2593 switch (var
->data
.mode
) {
2594 case ir_var_uniform
:
2595 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2596 var
->data
.param_index
);
2597 this->variables
.push_tail(entry
);
2599 case ir_var_shader_in
: {
2600 /* The linker assigns locations for varyings and attributes,
2601 * including deprecated builtins (like gl_Color), user-assign
2602 * generic attributes (glBindVertexLocation), and
2603 * user-defined varyings.
2605 assert(var
->data
.location
!= -1);
2607 const glsl_type
*type_without_array
= var
->type
->without_array();
2608 struct inout_decl
*decl
= &inputs
[num_inputs
];
2609 unsigned component
= var
->data
.location_frac
;
2610 unsigned num_components
;
2613 if (type_without_array
->is_64bit())
2614 component
= component
/ 2;
2615 if (type_without_array
->vector_elements
)
2616 num_components
= type_without_array
->vector_elements
;
2620 decl
->mesa_index
= var
->data
.location
;
2621 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2622 decl
->interp_loc
= st_translate_interp_loc(var
);
2623 decl
->base_type
= type_without_array
->base_type
;
2624 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2626 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2627 decl
->array_id
= num_input_arrays
+ 1;
2634 decl
->size
= type_size(var
->type
->fields
.array
);
2636 decl
->size
= type_size(var
->type
);
2638 entry
= new(mem_ctx
) variable_storage(var
,
2642 entry
->component
= component
;
2644 this->variables
.push_tail(entry
);
2647 case ir_var_shader_out
: {
2648 assert(var
->data
.location
!= -1);
2650 const glsl_type
*type_without_array
= var
->type
->without_array();
2651 struct inout_decl
*decl
= &outputs
[num_outputs
];
2652 unsigned component
= var
->data
.location_frac
;
2653 unsigned num_components
;
2656 if (type_without_array
->is_64bit())
2657 component
= component
/ 2;
2658 if (type_without_array
->vector_elements
)
2659 num_components
= type_without_array
->vector_elements
;
2663 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2664 decl
->base_type
= type_without_array
->base_type
;
2665 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2666 if (var
->data
.stream
& (1u << 31)) {
2667 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2669 assert(var
->data
.stream
< 4);
2670 decl
->gs_out_streams
= 0;
2671 for (unsigned i
= 0; i
< num_components
; ++i
)
2672 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2675 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2676 decl
->array_id
= num_output_arrays
+ 1;
2677 num_output_arrays
++;
2683 decl
->size
= type_size(var
->type
->fields
.array
);
2685 decl
->size
= type_size(var
->type
);
2687 if (var
->data
.fb_fetch_output
) {
2688 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2689 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2690 var
->type
, component
, decl
->array_id
);
2691 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2692 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2695 entry
= new(mem_ctx
) variable_storage(var
,
2700 entry
->component
= component
;
2702 this->variables
.push_tail(entry
);
2705 case ir_var_system_value
:
2706 entry
= new(mem_ctx
) variable_storage(var
,
2707 PROGRAM_SYSTEM_VALUE
,
2708 var
->data
.location
);
2711 case ir_var_temporary
:
2712 st_src_reg src
= get_temp(var
->type
);
2714 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2716 this->variables
.push_tail(entry
);
2722 printf("Failed to make storage for %s\n", var
->name
);
2727 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2728 entry
->component
, entry
->array_id
);
2729 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2730 this->result
.is_double_vertex_input
= true;
2731 if (!native_integers
)
2732 this->result
.type
= GLSL_TYPE_FLOAT
;
2736 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2737 GLbitfield64
* usage_mask
,
2738 GLbitfield64 double_usage_mask
,
2739 GLbitfield
* patch_usage_mask
)
2744 /* Fix array declarations by removing unused array elements at both ends
2745 * of the arrays. For example, mat4[3] where only mat[1] is used.
2747 for (i
= 0; i
< count
; i
++) {
2748 struct inout_decl
*decl
= &decls
[i
];
2749 if (!decl
->array_id
)
2752 /* Shrink the beginning. */
2753 for (j
= 0; j
< (int)decl
->size
; j
++) {
2754 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2755 if (*patch_usage_mask
&
2756 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2760 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2762 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2771 /* Shrink the end. */
2772 for (j
= decl
->size
-1; j
>= 0; j
--) {
2773 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2774 if (*patch_usage_mask
&
2775 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2779 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2781 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2788 /* When not all entries of an array are accessed, we mark them as used
2789 * here anyway, to ensure that the input/output mapping logic doesn't get
2792 * TODO This happens when an array isn't used via indirect access, which
2793 * some game ports do (at least eON-based). There is an optimization
2794 * opportunity here by replacing the array declaration with non-array
2795 * declarations of those slots that are actually used.
2797 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2798 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2799 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2801 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2807 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2811 int element_size
= type_size(ir
->type
);
2814 index
= ir
->array_index
->constant_expression_value();
2816 ir
->array
->accept(this);
2819 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2820 switch (this->prog
->Target
) {
2821 case GL_TESS_CONTROL_PROGRAM_NV
:
2822 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2823 !ir
->variable_referenced()->data
.patch
;
2825 case GL_TESS_EVALUATION_PROGRAM_NV
:
2826 is_2D
= src
.file
== PROGRAM_INPUT
&&
2827 !ir
->variable_referenced()->data
.patch
;
2829 case GL_GEOMETRY_PROGRAM_NV
:
2830 is_2D
= src
.file
== PROGRAM_INPUT
;
2840 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2841 src
.file
== PROGRAM_INPUT
)
2842 element_size
= attrib_type_size(ir
->type
, true);
2844 src
.index2D
= index
->value
.i
[0];
2845 src
.has_index2
= true;
2847 src
.index
+= index
->value
.i
[0] * element_size
;
2849 /* Variable index array dereference. It eats the "vec4" of the
2850 * base of the array and an index that offsets the TGSI register
2853 ir
->array_index
->accept(this);
2855 st_src_reg index_reg
;
2857 if (element_size
== 1) {
2858 index_reg
= this->result
;
2860 index_reg
= get_temp(native_integers
?
2861 glsl_type::int_type
: glsl_type::float_type
);
2863 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2864 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2867 /* If there was already a relative address register involved, add the
2868 * new and the old together to get the new offset.
2870 if (!is_2D
&& src
.reladdr
!= NULL
) {
2871 st_src_reg accum_reg
= get_temp(native_integers
?
2872 glsl_type::int_type
: glsl_type::float_type
);
2874 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2875 index_reg
, *src
.reladdr
);
2877 index_reg
= accum_reg
;
2881 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2882 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2884 src
.has_index2
= true;
2886 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2887 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2891 /* Change the register type to the element type of the array. */
2892 src
.type
= ir
->type
->base_type
;
2898 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2901 const glsl_type
*struct_type
= ir
->record
->type
;
2904 ir
->record
->accept(this);
2906 for (i
= 0; i
< struct_type
->length
; i
++) {
2907 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2909 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2912 /* If the type is smaller than a vec4, replicate the last channel out. */
2913 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2914 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2916 this->result
.swizzle
= SWIZZLE_NOOP
;
2918 this->result
.index
+= offset
;
2919 this->result
.type
= ir
->type
->base_type
;
2923 * We want to be careful in assignment setup to hit the actual storage
2924 * instead of potentially using a temporary like we might with the
2925 * ir_dereference handler.
2928 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2930 /* The LHS must be a dereference. If the LHS is a variable indexed array
2931 * access of a vector, it must be separated into a series conditional moves
2932 * before reaching this point (see ir_vec_index_to_cond_assign).
2934 assert(ir
->as_dereference());
2935 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2937 assert(!deref_array
->array
->type
->is_vector());
2940 /* Use the rvalue deref handler for the most part. We write swizzles using
2941 * the writemask, but we do extract the base component for enhanced layouts
2942 * from the source swizzle.
2945 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2946 return st_dst_reg(v
->result
);
2950 * Process the condition of a conditional assignment
2952 * Examines the condition of a conditional assignment to generate the optimal
2953 * first operand of a \c CMP instruction. If the condition is a relational
2954 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2955 * used as the source for the \c CMP instruction. Otherwise the comparison
2956 * is processed to a boolean result, and the boolean result is used as the
2957 * operand to the CMP instruction.
2960 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2962 ir_rvalue
*src_ir
= ir
;
2964 bool switch_order
= false;
2966 ir_expression
*const expr
= ir
->as_expression();
2968 if (native_integers
) {
2969 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2970 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2971 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2972 type
== GLSL_TYPE_BOOL
) {
2973 if (expr
->operation
== ir_binop_equal
) {
2974 if (expr
->operands
[0]->is_zero()) {
2975 src_ir
= expr
->operands
[1];
2976 switch_order
= true;
2978 else if (expr
->operands
[1]->is_zero()) {
2979 src_ir
= expr
->operands
[0];
2980 switch_order
= true;
2983 else if (expr
->operation
== ir_binop_nequal
) {
2984 if (expr
->operands
[0]->is_zero()) {
2985 src_ir
= expr
->operands
[1];
2987 else if (expr
->operands
[1]->is_zero()) {
2988 src_ir
= expr
->operands
[0];
2994 src_ir
->accept(this);
2995 return switch_order
;
2998 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2999 bool zero_on_left
= false;
3001 if (expr
->operands
[0]->is_zero()) {
3002 src_ir
= expr
->operands
[1];
3003 zero_on_left
= true;
3004 } else if (expr
->operands
[1]->is_zero()) {
3005 src_ir
= expr
->operands
[0];
3006 zero_on_left
= false;
3010 * (a < 0) T F F ( a < 0) T F F
3011 * (0 < a) F F T (-a < 0) F F T
3012 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3013 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3014 * (a > 0) F F T (-a < 0) F F T
3015 * (0 > a) T F F ( a < 0) T F F
3016 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3017 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3019 * Note that exchanging the order of 0 and 'a' in the comparison simply
3020 * means that the value of 'a' should be negated.
3023 switch (expr
->operation
) {
3025 switch_order
= false;
3026 negate
= zero_on_left
;
3029 case ir_binop_greater
:
3030 switch_order
= false;
3031 negate
= !zero_on_left
;
3034 case ir_binop_lequal
:
3035 switch_order
= true;
3036 negate
= !zero_on_left
;
3039 case ir_binop_gequal
:
3040 switch_order
= true;
3041 negate
= zero_on_left
;
3045 /* This isn't the right kind of comparison afterall, so make sure
3046 * the whole condition is visited.
3054 src_ir
->accept(this);
3056 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3057 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3058 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3059 * computing the condition.
3062 this->result
.negate
= ~this->result
.negate
;
3064 return switch_order
;
3068 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3069 st_dst_reg
*l
, st_src_reg
*r
,
3070 st_src_reg
*cond
, bool cond_swap
)
3072 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
3073 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3074 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3080 if (type
->is_array()) {
3081 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3082 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3087 if (type
->is_matrix()) {
3088 const struct glsl_type
*vec_type
;
3090 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3091 type
->vector_elements
, 1);
3093 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3094 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3099 assert(type
->is_scalar() || type
->is_vector());
3101 l
->type
= type
->base_type
;
3102 r
->type
= type
->base_type
;
3104 st_src_reg l_src
= st_src_reg(*l
);
3105 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3107 if (native_integers
) {
3108 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3109 cond_swap
? l_src
: *r
,
3110 cond_swap
? *r
: l_src
);
3112 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3113 cond_swap
? l_src
: *r
,
3114 cond_swap
? *r
: l_src
);
3117 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3121 if (type
->is_dual_slot()) {
3123 if (r
->is_double_vertex_input
== false)
3129 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3135 ir
->rhs
->accept(this);
3138 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3142 int first_enabled_chan
= 0;
3144 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3146 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3147 variable
->data
.mode
== ir_var_shader_out
&&
3148 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3149 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3150 assert(ir
->lhs
->type
->is_scalar());
3151 assert(ir
->write_mask
== WRITEMASK_X
);
3153 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3154 l
.writemask
= WRITEMASK_Z
;
3156 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3157 l
.writemask
= WRITEMASK_Y
;
3159 } else if (ir
->write_mask
== 0) {
3160 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3162 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3165 l
.writemask
= u_bit_consecutive(0, num_elements
);
3167 /* The type is a struct or an array of (array of) structs. */
3168 l
.writemask
= WRITEMASK_XYZW
;
3171 l
.writemask
= ir
->write_mask
;
3174 for (int i
= 0; i
< 4; i
++) {
3175 if (l
.writemask
& (1 << i
)) {
3176 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3181 l
.writemask
= l
.writemask
<< dst_component
;
3183 /* Swizzle a small RHS vector into the channels being written.
3185 * glsl ir treats write_mask as dictating how many channels are
3186 * present on the RHS while TGSI treats write_mask as just
3187 * showing which channels of the vec4 RHS get written.
3189 for (int i
= 0; i
< 4; i
++) {
3190 if (l
.writemask
& (1 << i
))
3191 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3193 swizzles
[i
] = first_enabled_chan
;
3195 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3196 swizzles
[2], swizzles
[3]);
3199 assert(l
.file
!= PROGRAM_UNDEFINED
);
3200 assert(r
.file
!= PROGRAM_UNDEFINED
);
3202 if (ir
->condition
) {
3203 const bool switch_order
= this->process_move_condition(ir
->condition
);
3204 st_src_reg condition
= this->result
;
3206 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3207 } else if (ir
->rhs
->as_expression() &&
3208 this->instructions
.get_tail() &&
3209 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3210 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3211 type_size(ir
->lhs
->type
) == 1 &&
3212 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3213 /* To avoid emitting an extra MOV when assigning an expression to a
3214 * variable, emit the last instruction of the expression again, but
3215 * replace the destination register with the target of the assignment.
3216 * Dead code elimination will remove the original instruction.
3218 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3219 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3220 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3221 new_inst
->saturate
= inst
->saturate
;
3222 inst
->dead_mask
= inst
->dst
[0].writemask
;
3224 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3230 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3233 GLdouble stack_vals
[4] = { 0 };
3234 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3235 GLenum gl_type
= GL_NONE
;
3237 static int in_array
= 0;
3238 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3240 /* Unfortunately, 4 floats is all we can get into
3241 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3242 * aggregate constant and move each constant value into it. If we
3243 * get lucky, copy propagation will eliminate the extra moves.
3245 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3246 st_src_reg temp_base
= get_temp(ir
->type
);
3247 st_dst_reg temp
= st_dst_reg(temp_base
);
3249 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3250 int size
= type_size(field_value
->type
);
3254 field_value
->accept(this);
3257 for (i
= 0; i
< (unsigned int)size
; i
++) {
3258 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3264 this->result
= temp_base
;
3268 if (ir
->type
->is_array()) {
3269 st_src_reg temp_base
= get_temp(ir
->type
);
3270 st_dst_reg temp
= st_dst_reg(temp_base
);
3271 int size
= type_size(ir
->type
->fields
.array
);
3276 for (i
= 0; i
< ir
->type
->length
; i
++) {
3277 ir
->array_elements
[i
]->accept(this);
3279 for (int j
= 0; j
< size
; j
++) {
3280 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3286 this->result
= temp_base
;
3291 if (ir
->type
->is_matrix()) {
3292 st_src_reg mat
= get_temp(ir
->type
);
3293 st_dst_reg mat_column
= st_dst_reg(mat
);
3295 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3296 switch (ir
->type
->base_type
) {
3297 case GLSL_TYPE_FLOAT
:
3298 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3300 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3301 src
.index
= add_constant(file
,
3303 ir
->type
->vector_elements
,
3306 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3308 case GLSL_TYPE_DOUBLE
:
3309 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3310 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3311 src
.index
= add_constant(file
,
3313 ir
->type
->vector_elements
,
3316 if (ir
->type
->vector_elements
>= 2) {
3317 mat_column
.writemask
= WRITEMASK_XY
;
3318 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3319 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3321 mat_column
.writemask
= WRITEMASK_X
;
3322 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3323 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3326 if (ir
->type
->vector_elements
> 2) {
3327 if (ir
->type
->vector_elements
== 4) {
3328 mat_column
.writemask
= WRITEMASK_ZW
;
3329 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3330 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3332 mat_column
.writemask
= WRITEMASK_Z
;
3333 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3334 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3335 mat_column
.writemask
= WRITEMASK_XYZW
;
3336 src
.swizzle
= SWIZZLE_XYZW
;
3342 unreachable("Illegal matrix constant type.\n");
3351 switch (ir
->type
->base_type
) {
3352 case GLSL_TYPE_FLOAT
:
3354 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3355 values
[i
].f
= ir
->value
.f
[i
];
3358 case GLSL_TYPE_DOUBLE
:
3359 gl_type
= GL_DOUBLE
;
3360 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3361 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3364 case GLSL_TYPE_INT64
:
3365 gl_type
= GL_INT64_ARB
;
3366 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3367 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3370 case GLSL_TYPE_UINT64
:
3371 gl_type
= GL_UNSIGNED_INT64_ARB
;
3372 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3373 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3376 case GLSL_TYPE_UINT
:
3377 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3378 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3379 if (native_integers
)
3380 values
[i
].u
= ir
->value
.u
[i
];
3382 values
[i
].f
= ir
->value
.u
[i
];
3386 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3387 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3388 if (native_integers
)
3389 values
[i
].i
= ir
->value
.i
[i
];
3391 values
[i
].f
= ir
->value
.i
[i
];
3394 case GLSL_TYPE_BOOL
:
3395 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3396 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3397 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3401 assert(!"Non-float/uint/int/bool constant");
3404 this->result
= st_src_reg(file
, -1, ir
->type
);
3405 this->result
.index
= add_constant(file
,
3407 ir
->type
->vector_elements
,
3409 &this->result
.swizzle
);
3413 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3415 exec_node
*param
= ir
->actual_parameters
.get_head();
3416 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3417 ir_variable
*location
= deref
->variable_referenced();
3420 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3422 /* Calculate the surface offset */
3424 unsigned array_size
= 0, base
= 0;
3427 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3429 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3430 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3431 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3432 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3433 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3435 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3438 ir
->return_deref
->accept(this);
3439 st_dst_reg
dst(this->result
);
3440 dst
.writemask
= WRITEMASK_X
;
3442 glsl_to_tgsi_instruction
*inst
;
3444 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3445 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3446 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3447 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3448 st_src_reg_for_int(1));
3449 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3450 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3451 st_src_reg_for_int(-1));
3452 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3454 param
= param
->get_next();
3455 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3458 st_src_reg data
= this->result
, data2
= undef_src
;
3460 switch (ir
->callee
->intrinsic_id
) {
3461 case ir_intrinsic_atomic_counter_add
:
3462 opcode
= TGSI_OPCODE_ATOMUADD
;
3464 case ir_intrinsic_atomic_counter_min
:
3465 opcode
= TGSI_OPCODE_ATOMIMIN
;
3467 case ir_intrinsic_atomic_counter_max
:
3468 opcode
= TGSI_OPCODE_ATOMIMAX
;
3470 case ir_intrinsic_atomic_counter_and
:
3471 opcode
= TGSI_OPCODE_ATOMAND
;
3473 case ir_intrinsic_atomic_counter_or
:
3474 opcode
= TGSI_OPCODE_ATOMOR
;
3476 case ir_intrinsic_atomic_counter_xor
:
3477 opcode
= TGSI_OPCODE_ATOMXOR
;
3479 case ir_intrinsic_atomic_counter_exchange
:
3480 opcode
= TGSI_OPCODE_ATOMXCHG
;
3482 case ir_intrinsic_atomic_counter_comp_swap
: {
3483 opcode
= TGSI_OPCODE_ATOMCAS
;
3484 param
= param
->get_next();
3485 val
= ((ir_instruction
*)param
)->as_rvalue();
3487 data2
= this->result
;
3491 assert(!"Unexpected intrinsic");
3495 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3498 inst
->resource
= buffer
;
3502 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3504 exec_node
*param
= ir
->actual_parameters
.get_head();
3506 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3508 param
= param
->get_next();
3509 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3511 ir_constant
*const_block
= block
->as_constant();
3515 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3516 (const_block
? const_block
->value
.u
[0] : 0),
3520 block
->accept(this);
3521 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3522 *buffer
.reladdr
= this->result
;
3523 emit_arl(ir
, sampler_reladdr
, this->result
);
3526 /* Calculate the surface offset */
3527 offset
->accept(this);
3528 st_src_reg off
= this->result
;
3530 st_dst_reg dst
= undef_dst
;
3531 if (ir
->return_deref
) {
3532 ir
->return_deref
->accept(this);
3533 dst
= st_dst_reg(this->result
);
3534 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3537 glsl_to_tgsi_instruction
*inst
;
3539 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3540 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3541 if (dst
.type
== GLSL_TYPE_BOOL
)
3542 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3543 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3544 param
= param
->get_next();
3545 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3548 param
= param
->get_next();
3549 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3551 dst
.writemask
= write_mask
->value
.u
[0];
3553 dst
.type
= this->result
.type
;
3554 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3556 param
= param
->get_next();
3557 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3560 st_src_reg data
= this->result
, data2
= undef_src
;
3562 switch (ir
->callee
->intrinsic_id
) {
3563 case ir_intrinsic_ssbo_atomic_add
:
3564 opcode
= TGSI_OPCODE_ATOMUADD
;
3566 case ir_intrinsic_ssbo_atomic_min
:
3567 opcode
= TGSI_OPCODE_ATOMIMIN
;
3569 case ir_intrinsic_ssbo_atomic_max
:
3570 opcode
= TGSI_OPCODE_ATOMIMAX
;
3572 case ir_intrinsic_ssbo_atomic_and
:
3573 opcode
= TGSI_OPCODE_ATOMAND
;
3575 case ir_intrinsic_ssbo_atomic_or
:
3576 opcode
= TGSI_OPCODE_ATOMOR
;
3578 case ir_intrinsic_ssbo_atomic_xor
:
3579 opcode
= TGSI_OPCODE_ATOMXOR
;
3581 case ir_intrinsic_ssbo_atomic_exchange
:
3582 opcode
= TGSI_OPCODE_ATOMXCHG
;
3584 case ir_intrinsic_ssbo_atomic_comp_swap
:
3585 opcode
= TGSI_OPCODE_ATOMCAS
;
3586 param
= param
->get_next();
3587 val
= ((ir_instruction
*)param
)->as_rvalue();
3589 data2
= this->result
;
3592 assert(!"Unexpected intrinsic");
3596 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3599 param
= param
->get_next();
3600 ir_constant
*access
= NULL
;
3601 if (!param
->is_tail_sentinel()) {
3602 access
= ((ir_instruction
*)param
)->as_constant();
3606 /* The emit_asm() might have actually split the op into pieces, e.g. for
3607 * double stores. We have to go back and fix up all the generated ops.
3609 unsigned op
= inst
->op
;
3611 inst
->resource
= buffer
;
3613 inst
->buffer_access
= access
->value
.u
[0];
3615 if (inst
== this->instructions
.get_head_raw())
3617 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3619 if (inst
->op
== TGSI_OPCODE_UADD
) {
3620 if (inst
== this->instructions
.get_head_raw())
3622 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3624 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3628 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3630 switch (ir
->callee
->intrinsic_id
) {
3631 case ir_intrinsic_memory_barrier
:
3632 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3633 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3634 TGSI_MEMBAR_ATOMIC_BUFFER
|
3635 TGSI_MEMBAR_SHADER_IMAGE
|
3636 TGSI_MEMBAR_SHARED
));
3638 case ir_intrinsic_memory_barrier_atomic_counter
:
3639 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3640 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3642 case ir_intrinsic_memory_barrier_buffer
:
3643 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3644 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3646 case ir_intrinsic_memory_barrier_image
:
3647 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3648 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3650 case ir_intrinsic_memory_barrier_shared
:
3651 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3652 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3654 case ir_intrinsic_group_memory_barrier
:
3655 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3656 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3657 TGSI_MEMBAR_ATOMIC_BUFFER
|
3658 TGSI_MEMBAR_SHADER_IMAGE
|
3659 TGSI_MEMBAR_SHARED
|
3660 TGSI_MEMBAR_THREAD_GROUP
));
3663 assert(!"Unexpected memory barrier intrinsic");
3668 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3670 exec_node
*param
= ir
->actual_parameters
.get_head();
3672 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3674 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3676 /* Calculate the surface offset */
3677 offset
->accept(this);
3678 st_src_reg off
= this->result
;
3680 st_dst_reg dst
= undef_dst
;
3681 if (ir
->return_deref
) {
3682 ir
->return_deref
->accept(this);
3683 dst
= st_dst_reg(this->result
);
3684 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3687 glsl_to_tgsi_instruction
*inst
;
3689 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3690 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3691 inst
->resource
= buffer
;
3692 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3693 param
= param
->get_next();
3694 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3697 param
= param
->get_next();
3698 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3700 dst
.writemask
= write_mask
->value
.u
[0];
3702 dst
.type
= this->result
.type
;
3703 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3704 inst
->resource
= buffer
;
3706 param
= param
->get_next();
3707 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3710 st_src_reg data
= this->result
, data2
= undef_src
;
3712 switch (ir
->callee
->intrinsic_id
) {
3713 case ir_intrinsic_shared_atomic_add
:
3714 opcode
= TGSI_OPCODE_ATOMUADD
;
3716 case ir_intrinsic_shared_atomic_min
:
3717 opcode
= TGSI_OPCODE_ATOMIMIN
;
3719 case ir_intrinsic_shared_atomic_max
:
3720 opcode
= TGSI_OPCODE_ATOMIMAX
;
3722 case ir_intrinsic_shared_atomic_and
:
3723 opcode
= TGSI_OPCODE_ATOMAND
;
3725 case ir_intrinsic_shared_atomic_or
:
3726 opcode
= TGSI_OPCODE_ATOMOR
;
3728 case ir_intrinsic_shared_atomic_xor
:
3729 opcode
= TGSI_OPCODE_ATOMXOR
;
3731 case ir_intrinsic_shared_atomic_exchange
:
3732 opcode
= TGSI_OPCODE_ATOMXCHG
;
3734 case ir_intrinsic_shared_atomic_comp_swap
:
3735 opcode
= TGSI_OPCODE_ATOMCAS
;
3736 param
= param
->get_next();
3737 val
= ((ir_instruction
*)param
)->as_rvalue();
3739 data2
= this->result
;
3742 assert(!"Unexpected intrinsic");
3746 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3747 inst
->resource
= buffer
;
3752 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3754 exec_node
*param
= ir
->actual_parameters
.get_head();
3756 ir_dereference
*img
= (ir_dereference
*)param
;
3757 const ir_variable
*imgvar
= img
->variable_referenced();
3758 const glsl_type
*type
= imgvar
->type
->without_array();
3759 unsigned sampler_array_size
= 1, sampler_base
= 0;
3762 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3764 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3765 (uint16_t*)&image
.index
, &reladdr
, true);
3767 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3768 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3769 *image
.reladdr
= reladdr
;
3770 emit_arl(ir
, sampler_reladdr
, reladdr
);
3773 st_dst_reg dst
= undef_dst
;
3774 if (ir
->return_deref
) {
3775 ir
->return_deref
->accept(this);
3776 dst
= st_dst_reg(this->result
);
3777 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3780 glsl_to_tgsi_instruction
*inst
;
3782 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3783 dst
.writemask
= WRITEMASK_XYZ
;
3784 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3785 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3786 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3787 st_dst_reg dstres
= st_dst_reg(res
);
3788 dstres
.writemask
= WRITEMASK_W
;
3789 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3790 res
.swizzle
= SWIZZLE_WWWW
;
3791 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3793 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3795 st_dst_reg coord_dst
;
3796 coord
= get_temp(glsl_type::ivec4_type
);
3797 coord_dst
= st_dst_reg(coord
);
3798 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3799 param
= param
->get_next();
3800 ((ir_dereference
*)param
)->accept(this);
3801 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3802 coord
.swizzle
= SWIZZLE_XXXX
;
3803 switch (type
->coordinate_components()) {
3804 case 4: assert(!"unexpected coord count");
3806 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3808 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3811 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3812 param
= param
->get_next();
3813 ((ir_dereference
*)param
)->accept(this);
3814 st_src_reg sample
= this->result
;
3815 sample
.swizzle
= SWIZZLE_XXXX
;
3816 coord_dst
.writemask
= WRITEMASK_W
;
3817 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3818 coord
.swizzle
|= SWIZZLE_W
<< 9;
3821 param
= param
->get_next();
3822 if (!param
->is_tail_sentinel()) {
3823 ((ir_dereference
*)param
)->accept(this);
3824 arg1
= this->result
;
3825 param
= param
->get_next();
3828 if (!param
->is_tail_sentinel()) {
3829 ((ir_dereference
*)param
)->accept(this);
3830 arg2
= this->result
;
3831 param
= param
->get_next();
3834 assert(param
->is_tail_sentinel());
3837 switch (ir
->callee
->intrinsic_id
) {
3838 case ir_intrinsic_image_load
:
3839 opcode
= TGSI_OPCODE_LOAD
;
3841 case ir_intrinsic_image_store
:
3842 opcode
= TGSI_OPCODE_STORE
;
3844 case ir_intrinsic_image_atomic_add
:
3845 opcode
= TGSI_OPCODE_ATOMUADD
;
3847 case ir_intrinsic_image_atomic_min
:
3848 opcode
= TGSI_OPCODE_ATOMIMIN
;
3850 case ir_intrinsic_image_atomic_max
:
3851 opcode
= TGSI_OPCODE_ATOMIMAX
;
3853 case ir_intrinsic_image_atomic_and
:
3854 opcode
= TGSI_OPCODE_ATOMAND
;
3856 case ir_intrinsic_image_atomic_or
:
3857 opcode
= TGSI_OPCODE_ATOMOR
;
3859 case ir_intrinsic_image_atomic_xor
:
3860 opcode
= TGSI_OPCODE_ATOMXOR
;
3862 case ir_intrinsic_image_atomic_exchange
:
3863 opcode
= TGSI_OPCODE_ATOMXCHG
;
3865 case ir_intrinsic_image_atomic_comp_swap
:
3866 opcode
= TGSI_OPCODE_ATOMCAS
;
3869 assert(!"Unexpected intrinsic");
3873 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3874 if (opcode
== TGSI_OPCODE_STORE
)
3875 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3878 inst
->resource
= image
;
3879 inst
->sampler_array_size
= sampler_array_size
;
3880 inst
->sampler_base
= sampler_base
;
3882 switch (type
->sampler_dimensionality
) {
3883 case GLSL_SAMPLER_DIM_1D
:
3884 inst
->tex_target
= (type
->sampler_array
)
3885 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3887 case GLSL_SAMPLER_DIM_2D
:
3888 inst
->tex_target
= (type
->sampler_array
)
3889 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3891 case GLSL_SAMPLER_DIM_3D
:
3892 inst
->tex_target
= TEXTURE_3D_INDEX
;
3894 case GLSL_SAMPLER_DIM_CUBE
:
3895 inst
->tex_target
= (type
->sampler_array
)
3896 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3898 case GLSL_SAMPLER_DIM_RECT
:
3899 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3901 case GLSL_SAMPLER_DIM_BUF
:
3902 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3904 case GLSL_SAMPLER_DIM_EXTERNAL
:
3905 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3907 case GLSL_SAMPLER_DIM_MS
:
3908 inst
->tex_target
= (type
->sampler_array
)
3909 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3912 assert(!"Should not get here.");
3915 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3916 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3918 if (imgvar
->data
.image_coherent
)
3919 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3920 if (imgvar
->data
.image_restrict
)
3921 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3922 if (imgvar
->data
.image_volatile
)
3923 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3927 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3929 ir_function_signature
*sig
= ir
->callee
;
3931 /* Filter out intrinsics */
3932 switch (sig
->intrinsic_id
) {
3933 case ir_intrinsic_atomic_counter_read
:
3934 case ir_intrinsic_atomic_counter_increment
:
3935 case ir_intrinsic_atomic_counter_predecrement
:
3936 case ir_intrinsic_atomic_counter_add
:
3937 case ir_intrinsic_atomic_counter_min
:
3938 case ir_intrinsic_atomic_counter_max
:
3939 case ir_intrinsic_atomic_counter_and
:
3940 case ir_intrinsic_atomic_counter_or
:
3941 case ir_intrinsic_atomic_counter_xor
:
3942 case ir_intrinsic_atomic_counter_exchange
:
3943 case ir_intrinsic_atomic_counter_comp_swap
:
3944 visit_atomic_counter_intrinsic(ir
);
3947 case ir_intrinsic_ssbo_load
:
3948 case ir_intrinsic_ssbo_store
:
3949 case ir_intrinsic_ssbo_atomic_add
:
3950 case ir_intrinsic_ssbo_atomic_min
:
3951 case ir_intrinsic_ssbo_atomic_max
:
3952 case ir_intrinsic_ssbo_atomic_and
:
3953 case ir_intrinsic_ssbo_atomic_or
:
3954 case ir_intrinsic_ssbo_atomic_xor
:
3955 case ir_intrinsic_ssbo_atomic_exchange
:
3956 case ir_intrinsic_ssbo_atomic_comp_swap
:
3957 visit_ssbo_intrinsic(ir
);
3960 case ir_intrinsic_memory_barrier
:
3961 case ir_intrinsic_memory_barrier_atomic_counter
:
3962 case ir_intrinsic_memory_barrier_buffer
:
3963 case ir_intrinsic_memory_barrier_image
:
3964 case ir_intrinsic_memory_barrier_shared
:
3965 case ir_intrinsic_group_memory_barrier
:
3966 visit_membar_intrinsic(ir
);
3969 case ir_intrinsic_shared_load
:
3970 case ir_intrinsic_shared_store
:
3971 case ir_intrinsic_shared_atomic_add
:
3972 case ir_intrinsic_shared_atomic_min
:
3973 case ir_intrinsic_shared_atomic_max
:
3974 case ir_intrinsic_shared_atomic_and
:
3975 case ir_intrinsic_shared_atomic_or
:
3976 case ir_intrinsic_shared_atomic_xor
:
3977 case ir_intrinsic_shared_atomic_exchange
:
3978 case ir_intrinsic_shared_atomic_comp_swap
:
3979 visit_shared_intrinsic(ir
);
3982 case ir_intrinsic_image_load
:
3983 case ir_intrinsic_image_store
:
3984 case ir_intrinsic_image_atomic_add
:
3985 case ir_intrinsic_image_atomic_min
:
3986 case ir_intrinsic_image_atomic_max
:
3987 case ir_intrinsic_image_atomic_and
:
3988 case ir_intrinsic_image_atomic_or
:
3989 case ir_intrinsic_image_atomic_xor
:
3990 case ir_intrinsic_image_atomic_exchange
:
3991 case ir_intrinsic_image_atomic_comp_swap
:
3992 case ir_intrinsic_image_size
:
3993 case ir_intrinsic_image_samples
:
3994 visit_image_intrinsic(ir
);
3997 case ir_intrinsic_invalid
:
3998 case ir_intrinsic_generic_load
:
3999 case ir_intrinsic_generic_store
:
4000 case ir_intrinsic_generic_atomic_add
:
4001 case ir_intrinsic_generic_atomic_and
:
4002 case ir_intrinsic_generic_atomic_or
:
4003 case ir_intrinsic_generic_atomic_xor
:
4004 case ir_intrinsic_generic_atomic_min
:
4005 case ir_intrinsic_generic_atomic_max
:
4006 case ir_intrinsic_generic_atomic_exchange
:
4007 case ir_intrinsic_generic_atomic_comp_swap
:
4008 case ir_intrinsic_shader_clock
:
4009 unreachable("Invalid intrinsic");
4014 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4015 unsigned *array_elements
,
4017 st_src_reg
*indirect
,
4020 switch (tail
->ir_type
) {
4021 case ir_type_dereference_record
: {
4022 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4023 const glsl_type
*struct_type
= deref_record
->record
->type
;
4024 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
4026 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4028 assert(field_index
>= 0);
4029 *location
+= struct_type
->record_location_offset(field_index
);
4033 case ir_type_dereference_array
: {
4034 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4035 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
4038 st_src_reg temp_reg
;
4039 st_dst_reg temp_dst
;
4041 temp_reg
= get_temp(glsl_type::uint_type
);
4042 temp_dst
= st_dst_reg(temp_reg
);
4043 temp_dst
.writemask
= 1;
4045 deref_arr
->array_index
->accept(this);
4046 if (*array_elements
!= 1)
4047 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4049 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4051 if (indirect
->file
== PROGRAM_UNDEFINED
)
4052 *indirect
= temp_reg
;
4054 temp_dst
= st_dst_reg(*indirect
);
4055 temp_dst
.writemask
= 1;
4056 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4059 *index
+= array_index
->value
.u
[0] * *array_elements
;
4061 *array_elements
*= deref_arr
->array
->type
->length
;
4063 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4072 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4073 unsigned *array_size
,
4076 st_src_reg
*reladdr
,
4079 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4080 unsigned location
= 0;
4081 ir_variable
*var
= ir
->variable_referenced();
4083 memset(reladdr
, 0, sizeof(*reladdr
));
4084 reladdr
->file
= PROGRAM_UNDEFINED
;
4090 location
= var
->data
.location
;
4091 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4094 * If we end up with no indirect then adjust the base to the index,
4095 * and set the array size to 1.
4097 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4103 assert(location
!= 0xffffffff);
4104 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4105 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4110 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4112 if (offset
.reladdr
|| offset
.reladdr2
) {
4113 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4114 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4115 tmp_dst
.writemask
= WRITEMASK_XY
;
4116 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4124 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4126 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4127 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4128 st_src_reg levels_src
, reladdr
;
4129 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4130 glsl_to_tgsi_instruction
*inst
= NULL
;
4131 unsigned opcode
= TGSI_OPCODE_NOP
;
4132 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4133 unsigned sampler_array_size
= 1, sampler_base
= 0;
4134 uint16_t sampler_index
= 0;
4135 bool is_cube_array
= false;
4138 /* if we are a cube array sampler */
4139 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
4140 sampler_type
->sampler_array
)) {
4141 is_cube_array
= true;
4144 if (ir
->coordinate
) {
4145 ir
->coordinate
->accept(this);
4147 /* Put our coords in a temp. We'll need to modify them for shadow,
4148 * projection, or LOD, so the only case we'd use it as-is is if
4149 * we're doing plain old texturing. The optimization passes on
4150 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4152 coord
= get_temp(glsl_type::vec4_type
);
4153 coord_dst
= st_dst_reg(coord
);
4154 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4155 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4158 if (ir
->projector
) {
4159 ir
->projector
->accept(this);
4160 projector
= this->result
;
4163 /* Storage for our result. Ideally for an assignment we'd be using
4164 * the actual storage for the result here, instead.
4166 result_src
= get_temp(ir
->type
);
4167 result_dst
= st_dst_reg(result_src
);
4171 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4173 ir
->offset
->accept(this);
4174 offset
[0] = this->result
;
4178 if (is_cube_array
||
4179 sampler_type
== glsl_type::samplerCubeShadow_type
) {
4180 opcode
= TGSI_OPCODE_TXB2
;
4183 opcode
= TGSI_OPCODE_TXB
;
4185 ir
->lod_info
.bias
->accept(this);
4186 lod_info
= this->result
;
4188 ir
->offset
->accept(this);
4189 offset
[0] = this->result
;
4193 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4194 ir
->lod_info
.lod
->accept(this);
4195 lod_info
= this->result
;
4197 ir
->offset
->accept(this);
4198 offset
[0] = this->result
;
4202 opcode
= TGSI_OPCODE_TXD
;
4203 ir
->lod_info
.grad
.dPdx
->accept(this);
4205 ir
->lod_info
.grad
.dPdy
->accept(this);
4208 ir
->offset
->accept(this);
4209 offset
[0] = this->result
;
4213 opcode
= TGSI_OPCODE_TXQ
;
4214 ir
->lod_info
.lod
->accept(this);
4215 lod_info
= this->result
;
4217 case ir_query_levels
:
4218 opcode
= TGSI_OPCODE_TXQ
;
4219 lod_info
= undef_src
;
4220 levels_src
= get_temp(ir
->type
);
4223 opcode
= TGSI_OPCODE_TXF
;
4224 ir
->lod_info
.lod
->accept(this);
4225 lod_info
= this->result
;
4227 ir
->offset
->accept(this);
4228 offset
[0] = this->result
;
4232 opcode
= TGSI_OPCODE_TXF
;
4233 ir
->lod_info
.sample_index
->accept(this);
4234 sample_index
= this->result
;
4237 opcode
= TGSI_OPCODE_TG4
;
4238 ir
->lod_info
.component
->accept(this);
4239 component
= this->result
;
4241 ir
->offset
->accept(this);
4242 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4243 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4244 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4245 offset
[i
] = this->result
;
4246 offset
[i
].index
+= i
* type_size(elt_type
);
4247 offset
[i
].type
= elt_type
->base_type
;
4248 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4249 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4252 offset
[0] = canonicalize_gather_offset(this->result
);
4257 opcode
= TGSI_OPCODE_LODQ
;
4259 case ir_texture_samples
:
4260 opcode
= TGSI_OPCODE_TXQS
;
4262 case ir_samples_identical
:
4263 unreachable("Unexpected ir_samples_identical opcode");
4266 if (ir
->projector
) {
4267 if (opcode
== TGSI_OPCODE_TEX
) {
4268 /* Slot the projector in as the last component of the coord. */
4269 coord_dst
.writemask
= WRITEMASK_W
;
4270 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4271 coord_dst
.writemask
= WRITEMASK_XYZW
;
4272 opcode
= TGSI_OPCODE_TXP
;
4274 st_src_reg coord_w
= coord
;
4275 coord_w
.swizzle
= SWIZZLE_WWWW
;
4277 /* For the other TEX opcodes there's no projective version
4278 * since the last slot is taken up by LOD info. Do the
4279 * projective divide now.
4281 coord_dst
.writemask
= WRITEMASK_W
;
4282 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4284 /* In the case where we have to project the coordinates "by hand,"
4285 * the shadow comparator value must also be projected.
4287 st_src_reg tmp_src
= coord
;
4288 if (ir
->shadow_comparator
) {
4289 /* Slot the shadow value in as the second to last component of the
4292 ir
->shadow_comparator
->accept(this);
4294 tmp_src
= get_temp(glsl_type::vec4_type
);
4295 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4297 /* Projective division not allowed for array samplers. */
4298 assert(!sampler_type
->sampler_array
);
4300 tmp_dst
.writemask
= WRITEMASK_Z
;
4301 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4303 tmp_dst
.writemask
= WRITEMASK_XY
;
4304 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4307 coord_dst
.writemask
= WRITEMASK_XYZ
;
4308 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4310 coord_dst
.writemask
= WRITEMASK_XYZW
;
4311 coord
.swizzle
= SWIZZLE_XYZW
;
4315 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4316 * comparator was put in the correct place (and projected) by the code,
4317 * above, that handles by-hand projection.
4319 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4320 /* Slot the shadow value in as the second to last component of the
4323 ir
->shadow_comparator
->accept(this);
4325 if (is_cube_array
) {
4326 cube_sc
= get_temp(glsl_type::float_type
);
4327 cube_sc_dst
= st_dst_reg(cube_sc
);
4328 cube_sc_dst
.writemask
= WRITEMASK_X
;
4329 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4330 cube_sc_dst
.writemask
= WRITEMASK_X
;
4333 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4334 sampler_type
->sampler_array
) ||
4335 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4336 coord_dst
.writemask
= WRITEMASK_W
;
4338 coord_dst
.writemask
= WRITEMASK_Z
;
4340 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4341 coord_dst
.writemask
= WRITEMASK_XYZW
;
4345 if (ir
->op
== ir_txf_ms
) {
4346 coord_dst
.writemask
= WRITEMASK_W
;
4347 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4348 coord_dst
.writemask
= WRITEMASK_XYZW
;
4349 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4350 opcode
== TGSI_OPCODE_TXF
) {
4351 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4352 coord_dst
.writemask
= WRITEMASK_W
;
4353 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4354 coord_dst
.writemask
= WRITEMASK_XYZW
;
4357 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4358 &sampler_index
, &reladdr
, true);
4359 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4360 emit_arl(ir
, sampler_reladdr
, reladdr
);
4362 if (opcode
== TGSI_OPCODE_TXD
)
4363 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4364 else if (opcode
== TGSI_OPCODE_TXQ
) {
4365 if (ir
->op
== ir_query_levels
) {
4366 /* the level is stored in W */
4367 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4368 result_dst
.writemask
= WRITEMASK_X
;
4369 levels_src
.swizzle
= SWIZZLE_WWWW
;
4370 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4372 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4373 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4374 inst
= emit_asm(ir
, opcode
, result_dst
);
4375 } else if (opcode
== TGSI_OPCODE_TXF
) {
4376 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4377 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4378 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4379 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4380 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4381 } else if (opcode
== TGSI_OPCODE_TG4
) {
4382 if (is_cube_array
&& ir
->shadow_comparator
) {
4383 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4385 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4388 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4390 if (ir
->shadow_comparator
)
4391 inst
->tex_shadow
= GL_TRUE
;
4393 inst
->resource
.index
= sampler_index
;
4394 inst
->sampler_array_size
= sampler_array_size
;
4395 inst
->sampler_base
= sampler_base
;
4397 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4398 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4399 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4403 if (!inst
->tex_offsets
)
4404 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4406 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4407 inst
->tex_offsets
[i
] = offset
[i
];
4408 inst
->tex_offset_num_offset
= i
;
4411 switch (sampler_type
->sampler_dimensionality
) {
4412 case GLSL_SAMPLER_DIM_1D
:
4413 inst
->tex_target
= (sampler_type
->sampler_array
)
4414 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4416 case GLSL_SAMPLER_DIM_2D
:
4417 inst
->tex_target
= (sampler_type
->sampler_array
)
4418 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4420 case GLSL_SAMPLER_DIM_3D
:
4421 inst
->tex_target
= TEXTURE_3D_INDEX
;
4423 case GLSL_SAMPLER_DIM_CUBE
:
4424 inst
->tex_target
= (sampler_type
->sampler_array
)
4425 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4427 case GLSL_SAMPLER_DIM_RECT
:
4428 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4430 case GLSL_SAMPLER_DIM_BUF
:
4431 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4433 case GLSL_SAMPLER_DIM_EXTERNAL
:
4434 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4436 case GLSL_SAMPLER_DIM_MS
:
4437 inst
->tex_target
= (sampler_type
->sampler_array
)
4438 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4441 assert(!"Should not get here.");
4444 inst
->tex_type
= ir
->type
->base_type
;
4446 this->result
= result_src
;
4450 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4452 assert(!ir
->get_value());
4454 emit_asm(ir
, TGSI_OPCODE_RET
);
4458 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4460 if (ir
->condition
) {
4461 ir
->condition
->accept(this);
4462 st_src_reg condition
= this->result
;
4464 /* Convert the bool condition to a float so we can negate. */
4465 if (native_integers
) {
4466 st_src_reg temp
= get_temp(ir
->condition
->type
);
4467 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4468 condition
, st_src_reg_for_float(1.0));
4472 condition
.negate
= ~condition
.negate
;
4473 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4475 /* unconditional kil */
4476 emit_asm(ir
, TGSI_OPCODE_KILL
);
4481 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4484 glsl_to_tgsi_instruction
*if_inst
;
4486 ir
->condition
->accept(this);
4487 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4489 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4491 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4493 this->instructions
.push_tail(if_inst
);
4495 visit_exec_list(&ir
->then_instructions
, this);
4497 if (!ir
->else_instructions
.is_empty()) {
4498 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4499 visit_exec_list(&ir
->else_instructions
, this);
4502 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4507 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4509 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4511 ir
->stream
->accept(this);
4512 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4516 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4518 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4520 ir
->stream
->accept(this);
4521 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4525 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4527 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4528 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4530 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4533 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4535 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4537 result
.file
= PROGRAM_UNDEFINED
;
4544 num_input_arrays
= 0;
4545 num_output_arrays
= 0;
4547 num_address_regs
= 0;
4551 indirect_addr_consts
= false;
4552 wpos_transform_const
= -1;
4554 native_integers
= false;
4555 mem_ctx
= ralloc_context(NULL
);
4558 shader_program
= NULL
;
4563 use_shared_memory
= false;
4566 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4569 ralloc_free(mem_ctx
);
4572 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4579 * Count resources used by the given gpu program (number of texture
4583 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4585 v
->samplers_used
= 0;
4586 v
->buffers_used
= 0;
4589 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4590 if (inst
->info
->is_tex
) {
4591 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4592 unsigned idx
= inst
->sampler_base
+ i
;
4593 v
->samplers_used
|= 1u << idx
;
4595 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4596 v
->sampler_types
[idx
] = inst
->tex_type
;
4597 v
->sampler_targets
[idx
] =
4598 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4600 if (inst
->tex_shadow
) {
4601 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4606 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4607 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4609 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4610 is_resource_instruction(inst
->op
) ||
4611 inst
->op
== TGSI_OPCODE_STORE
)) {
4612 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4613 v
->buffers_used
|= 1 << inst
->resource
.index
;
4614 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4615 v
->use_shared_memory
= true;
4617 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4618 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4619 unsigned idx
= inst
->sampler_base
+ i
;
4620 v
->images_used
|= 1 << idx
;
4621 v
->image_targets
[idx
] =
4622 st_translate_texture_target(inst
->tex_target
, false);
4623 v
->image_formats
[idx
] = inst
->image_format
;
4628 prog
->SamplersUsed
= v
->samplers_used
;
4630 if (v
->shader_program
!= NULL
)
4631 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4635 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4636 * are read from the given src in this instruction
4639 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4641 int read_mask
= 0, comp
;
4643 /* Now, given the src swizzle and the written channels, find which
4644 * components are actually read
4646 for (comp
= 0; comp
< 4; ++comp
) {
4647 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4649 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4650 read_mask
|= 1 << coord
;
4657 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4658 * instruction is the first instruction to write to register T0. There are
4659 * several lowering passes done in GLSL IR (e.g. branches and
4660 * relative addressing) that create a large number of conditional assignments
4661 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4663 * Here is why this conversion is safe:
4664 * CMP T0, T1 T2 T0 can be expanded to:
4670 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4671 * as the original program. If (T1 < 0.0) evaluates to false, executing
4672 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4673 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4674 * because any instruction that was going to read from T0 after this was going
4675 * to read a garbage value anyway.
4678 glsl_to_tgsi_visitor::simplify_cmp(void)
4680 int tempWritesSize
= 0;
4681 unsigned *tempWrites
= NULL
;
4682 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4684 memset(outputWrites
, 0, sizeof(outputWrites
));
4686 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4687 unsigned prevWriteMask
= 0;
4689 /* Give up if we encounter relative addressing or flow control. */
4690 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4691 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4692 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4693 inst
->op
== TGSI_OPCODE_CONT
||
4694 inst
->op
== TGSI_OPCODE_END
||
4695 inst
->op
== TGSI_OPCODE_RET
) {
4699 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4700 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4701 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4702 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4703 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4704 if (inst
->dst
[0].index
>= tempWritesSize
) {
4705 const int inc
= 4096;
4707 tempWrites
= (unsigned*)
4709 (tempWritesSize
+ inc
) * sizeof(unsigned));
4713 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4714 tempWritesSize
+= inc
;
4717 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4718 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4722 /* For a CMP to be considered a conditional write, the destination
4723 * register and source register two must be the same. */
4724 if (inst
->op
== TGSI_OPCODE_CMP
4725 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4726 && inst
->src
[2].file
== inst
->dst
[0].file
4727 && inst
->src
[2].index
== inst
->dst
[0].index
4728 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4730 inst
->op
= TGSI_OPCODE_MOV
;
4731 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4732 inst
->src
[0] = inst
->src
[1];
4739 /* Replaces all references to a temporary register index with another index. */
4741 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4743 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4746 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4747 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4748 for (k
= 0; k
< num_renames
; k
++)
4749 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4750 inst
->src
[j
].index
= renames
[k
].new_reg
;
4753 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4754 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4755 for (k
= 0; k
< num_renames
; k
++)
4756 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4757 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4760 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4761 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4762 for (k
= 0; k
< num_renames
; k
++)
4763 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4764 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4770 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4772 int depth
= 0; /* loop depth */
4773 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4776 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4777 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4778 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4779 if (first_reads
[inst
->src
[j
].index
] == -1)
4780 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4783 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4784 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4785 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4786 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4789 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4792 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4802 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4804 int depth
= 0; /* loop depth */
4805 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4808 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4809 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4810 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4811 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4813 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4814 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4815 if (first_writes
[inst
->dst
[j
].index
] == -1)
4816 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4817 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4820 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4821 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4822 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4824 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4827 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4830 for (k
= 0; k
< this->next_temp
; k
++) {
4831 if (last_reads
[k
] == -2) {
4843 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4845 int depth
= 0; /* loop depth */
4849 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4850 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4851 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4852 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4855 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4857 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4859 for (k
= 0; k
< this->next_temp
; k
++) {
4860 if (last_writes
[k
] == -2) {
4871 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4872 * channels for copy propagation and updates following instructions to
4873 * use the original versions.
4875 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4876 * will occur. As an example, a TXP production before this pass:
4878 * 0: MOV TEMP[1], INPUT[4].xyyy;
4879 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4880 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4884 * 0: MOV TEMP[1], INPUT[4].xyyy;
4885 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4886 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4888 * which allows for dead code elimination on TEMP[1]'s writes.
4891 glsl_to_tgsi_visitor::copy_propagate(void)
4893 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4894 glsl_to_tgsi_instruction
*,
4895 this->next_temp
* 4);
4896 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4899 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4900 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4901 || inst
->dst
[0].index
< this->next_temp
);
4903 /* First, do any copy propagation possible into the src regs. */
4904 for (int r
= 0; r
< 3; r
++) {
4905 glsl_to_tgsi_instruction
*first
= NULL
;
4907 int acp_base
= inst
->src
[r
].index
* 4;
4909 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4910 inst
->src
[r
].reladdr
||
4911 inst
->src
[r
].reladdr2
)
4914 /* See if we can find entries in the ACP consisting of MOVs
4915 * from the same src register for all the swizzled channels
4916 * of this src register reference.
4918 for (int i
= 0; i
< 4; i
++) {
4919 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4920 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4927 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4932 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4933 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4934 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4935 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4943 /* We've now validated that we can copy-propagate to
4944 * replace this src register reference. Do it.
4946 inst
->src
[r
].file
= first
->src
[0].file
;
4947 inst
->src
[r
].index
= first
->src
[0].index
;
4948 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4949 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4950 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4951 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4954 for (int i
= 0; i
< 4; i
++) {
4955 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4956 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4957 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4959 inst
->src
[r
].swizzle
= swizzle
;
4964 case TGSI_OPCODE_BGNLOOP
:
4965 case TGSI_OPCODE_ENDLOOP
:
4966 /* End of a basic block, clear the ACP entirely. */
4967 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4970 case TGSI_OPCODE_IF
:
4971 case TGSI_OPCODE_UIF
:
4975 case TGSI_OPCODE_ENDIF
:
4976 case TGSI_OPCODE_ELSE
:
4977 /* Clear all channels written inside the block from the ACP, but
4978 * leaving those that were not touched.
4980 for (int r
= 0; r
< this->next_temp
; r
++) {
4981 for (int c
= 0; c
< 4; c
++) {
4982 if (!acp
[4 * r
+ c
])
4985 if (acp_level
[4 * r
+ c
] >= level
)
4986 acp
[4 * r
+ c
] = NULL
;
4989 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4994 /* Continuing the block, clear any written channels from
4997 for (int d
= 0; d
< 2; d
++) {
4998 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4999 /* Any temporary might be written, so no copy propagation
5000 * across this instruction.
5002 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5003 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5004 inst
->dst
[d
].reladdr
) {
5005 /* Any output might be written, so no copy propagation
5006 * from outputs across this instruction.
5008 for (int r
= 0; r
< this->next_temp
; r
++) {
5009 for (int c
= 0; c
< 4; c
++) {
5010 if (!acp
[4 * r
+ c
])
5013 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5014 acp
[4 * r
+ c
] = NULL
;
5017 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5018 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5019 /* Clear where it's used as dst. */
5020 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5021 for (int c
= 0; c
< 4; c
++) {
5022 if (inst
->dst
[d
].writemask
& (1 << c
))
5023 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5027 /* Clear where it's used as src. */
5028 for (int r
= 0; r
< this->next_temp
; r
++) {
5029 for (int c
= 0; c
< 4; c
++) {
5030 if (!acp
[4 * r
+ c
])
5033 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5035 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5036 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5037 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5038 acp
[4 * r
+ c
] = NULL
;
5047 /* If this is a copy, add it to the ACP. */
5048 if (inst
->op
== TGSI_OPCODE_MOV
&&
5049 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5050 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5051 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5052 !inst
->dst
[0].reladdr
&&
5053 !inst
->dst
[0].reladdr2
&&
5055 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5056 !inst
->src
[0].reladdr
&&
5057 !inst
->src
[0].reladdr2
&&
5058 !inst
->src
[0].negate
&&
5059 !inst
->src
[0].abs
) {
5060 for (int i
= 0; i
< 4; i
++) {
5061 if (inst
->dst
[0].writemask
& (1 << i
)) {
5062 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5063 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5069 ralloc_free(acp_level
);
5074 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5077 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5078 * will occur. As an example, a TXP production after copy propagation but
5081 * 0: MOV TEMP[1], INPUT[4].xyyy;
5082 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5083 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5085 * and after this pass:
5087 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5090 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5092 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5093 glsl_to_tgsi_instruction
*,
5094 this->next_temp
* 4);
5095 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5099 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5100 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5101 || inst
->dst
[0].index
< this->next_temp
);
5104 case TGSI_OPCODE_BGNLOOP
:
5105 case TGSI_OPCODE_ENDLOOP
:
5106 case TGSI_OPCODE_CONT
:
5107 case TGSI_OPCODE_BRK
:
5108 /* End of a basic block, clear the write array entirely.
5110 * This keeps us from killing dead code when the writes are
5111 * on either side of a loop, even when the register isn't touched
5112 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5113 * dead code of this type, so it shouldn't make a difference as long as
5114 * the dead code elimination pass in the GLSL compiler does its job.
5116 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5119 case TGSI_OPCODE_ENDIF
:
5120 case TGSI_OPCODE_ELSE
:
5121 /* Promote the recorded level of all channels written inside the
5122 * preceding if or else block to the level above the if/else block.
5124 for (int r
= 0; r
< this->next_temp
; r
++) {
5125 for (int c
= 0; c
< 4; c
++) {
5126 if (!writes
[4 * r
+ c
])
5129 if (write_level
[4 * r
+ c
] == level
)
5130 write_level
[4 * r
+ c
] = level
-1;
5133 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5137 case TGSI_OPCODE_IF
:
5138 case TGSI_OPCODE_UIF
:
5140 /* fallthrough to default case to mark the condition as read */
5142 /* Continuing the block, clear any channels from the write array that
5143 * are read by this instruction.
5145 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5146 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5147 /* Any temporary might be read, so no dead code elimination
5148 * across this instruction.
5150 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5151 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5152 /* Clear where it's used as src. */
5153 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5154 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5155 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5156 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5158 for (int c
= 0; c
< 4; c
++) {
5159 if (src_chans
& (1 << c
))
5160 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5164 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5165 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5166 /* Any temporary might be read, so no dead code elimination
5167 * across this instruction.
5169 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5170 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5171 /* Clear where it's used as src. */
5172 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5173 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5174 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5175 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5177 for (int c
= 0; c
< 4; c
++) {
5178 if (src_chans
& (1 << c
))
5179 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5186 /* If this instruction writes to a temporary, add it to the write array.
5187 * If there is already an instruction in the write array for one or more
5188 * of the channels, flag that channel write as dead.
5190 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5191 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5192 !inst
->dst
[i
].reladdr
) {
5193 for (int c
= 0; c
< 4; c
++) {
5194 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5195 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5196 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5199 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5201 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5202 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5209 /* Anything still in the write array at this point is dead code. */
5210 for (int r
= 0; r
< this->next_temp
; r
++) {
5211 for (int c
= 0; c
< 4; c
++) {
5212 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5214 inst
->dead_mask
|= (1 << c
);
5218 /* Now actually remove the instructions that are completely dead and update
5219 * the writemask of other instructions with dead channels.
5221 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5222 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5224 /* No amount of dead masks should remove memory stores */
5225 if (inst
->info
->is_store
)
5228 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5233 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5234 if (inst
->dead_mask
== WRITEMASK_XY
||
5235 inst
->dead_mask
== WRITEMASK_ZW
)
5236 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5238 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5242 ralloc_free(write_level
);
5243 ralloc_free(writes
);
5248 /* merge DFRACEXP instructions into one. */
5250 glsl_to_tgsi_visitor::merge_two_dsts(void)
5252 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5253 glsl_to_tgsi_instruction
*inst2
;
5255 if (num_inst_dst_regs(inst
) != 2)
5258 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5259 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5262 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5265 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5266 inst
->src
[0].index
== inst2
->src
[0].index
&&
5267 inst
->src
[0].type
== inst2
->src
[0].type
&&
5268 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5270 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5276 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5278 inst
->dst
[0] = inst2
->dst
[0];
5279 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5280 inst
->dst
[1] = inst2
->dst
[1];
5291 /* Merges temporary registers together where possible to reduce the number of
5292 * registers needed to run a program.
5294 * Produces optimal code only after copy propagation and dead code elimination
5297 glsl_to_tgsi_visitor::merge_registers(void)
5299 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5300 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5301 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5303 int num_renames
= 0;
5305 /* Read the indices of the last read and first write to each temp register
5306 * into an array so that we don't have to traverse the instruction list as
5308 for (i
= 0; i
< this->next_temp
; i
++) {
5310 first_writes
[i
] = -1;
5312 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5314 /* Start looking for registers with non-overlapping usages that can be
5315 * merged together. */
5316 for (i
= 0; i
< this->next_temp
; i
++) {
5317 /* Don't touch unused registers. */
5318 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5320 for (j
= 0; j
< this->next_temp
; j
++) {
5321 /* Don't touch unused registers. */
5322 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5324 /* We can merge the two registers if the first write to j is after or
5325 * in the same instruction as the last read from i. Note that the
5326 * register at index i will always be used earlier or at the same time
5327 * as the register at index j. */
5328 if (first_writes
[i
] <= first_writes
[j
] &&
5329 last_reads
[i
] <= first_writes
[j
]) {
5330 renames
[num_renames
].old_reg
= j
;
5331 renames
[num_renames
].new_reg
= i
;
5334 /* Update the first_writes and last_reads arrays with the new
5335 * values for the merged register index, and mark the newly unused
5336 * register index as such. */
5337 assert(last_reads
[j
] >= last_reads
[i
]);
5338 last_reads
[i
] = last_reads
[j
];
5339 first_writes
[j
] = -1;
5345 rename_temp_registers(num_renames
, renames
);
5346 ralloc_free(renames
);
5347 ralloc_free(last_reads
);
5348 ralloc_free(first_writes
);
5351 /* Reassign indices to temporary registers by reusing unused indices created
5352 * by optimization passes. */
5354 glsl_to_tgsi_visitor::renumber_registers(void)
5358 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5359 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5360 int num_renames
= 0;
5361 for (i
= 0; i
< this->next_temp
; i
++) {
5362 first_reads
[i
] = -1;
5364 get_first_temp_read(first_reads
);
5366 for (i
= 0; i
< this->next_temp
; i
++) {
5367 if (first_reads
[i
] < 0) continue;
5368 if (i
!= new_index
) {
5369 renames
[num_renames
].old_reg
= i
;
5370 renames
[num_renames
].new_reg
= new_index
;
5376 rename_temp_registers(num_renames
, renames
);
5377 this->next_temp
= new_index
;
5378 ralloc_free(renames
);
5379 ralloc_free(first_reads
);
5382 /* ------------------------- TGSI conversion stuff -------------------------- */
5385 * Intermediate state used during shader translation.
5387 struct st_translate
{
5388 struct ureg_program
*ureg
;
5390 unsigned temps_size
;
5391 struct ureg_dst
*temps
;
5393 struct ureg_dst
*arrays
;
5394 unsigned num_temp_arrays
;
5395 struct ureg_src
*constants
;
5397 struct ureg_src
*immediates
;
5399 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5400 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5401 struct ureg_dst address
[3];
5402 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5403 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5404 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5405 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5406 struct ureg_src shared_memory
;
5407 unsigned *array_sizes
;
5408 struct inout_decl
*input_decls
;
5409 unsigned num_input_decls
;
5410 struct inout_decl
*output_decls
;
5411 unsigned num_output_decls
;
5413 const GLuint
*inputMapping
;
5414 const GLuint
*outputMapping
;
5416 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5419 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5421 _mesa_sysval_to_semantic(unsigned sysval
)
5425 case SYSTEM_VALUE_VERTEX_ID
:
5426 return TGSI_SEMANTIC_VERTEXID
;
5427 case SYSTEM_VALUE_INSTANCE_ID
:
5428 return TGSI_SEMANTIC_INSTANCEID
;
5429 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5430 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5431 case SYSTEM_VALUE_BASE_VERTEX
:
5432 return TGSI_SEMANTIC_BASEVERTEX
;
5433 case SYSTEM_VALUE_BASE_INSTANCE
:
5434 return TGSI_SEMANTIC_BASEINSTANCE
;
5435 case SYSTEM_VALUE_DRAW_ID
:
5436 return TGSI_SEMANTIC_DRAWID
;
5438 /* Geometry shader */
5439 case SYSTEM_VALUE_INVOCATION_ID
:
5440 return TGSI_SEMANTIC_INVOCATIONID
;
5442 /* Fragment shader */
5443 case SYSTEM_VALUE_FRAG_COORD
:
5444 return TGSI_SEMANTIC_POSITION
;
5445 case SYSTEM_VALUE_FRONT_FACE
:
5446 return TGSI_SEMANTIC_FACE
;
5447 case SYSTEM_VALUE_SAMPLE_ID
:
5448 return TGSI_SEMANTIC_SAMPLEID
;
5449 case SYSTEM_VALUE_SAMPLE_POS
:
5450 return TGSI_SEMANTIC_SAMPLEPOS
;
5451 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5452 return TGSI_SEMANTIC_SAMPLEMASK
;
5453 case SYSTEM_VALUE_HELPER_INVOCATION
:
5454 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5456 /* Tessellation shader */
5457 case SYSTEM_VALUE_TESS_COORD
:
5458 return TGSI_SEMANTIC_TESSCOORD
;
5459 case SYSTEM_VALUE_VERTICES_IN
:
5460 return TGSI_SEMANTIC_VERTICESIN
;
5461 case SYSTEM_VALUE_PRIMITIVE_ID
:
5462 return TGSI_SEMANTIC_PRIMID
;
5463 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5464 return TGSI_SEMANTIC_TESSOUTER
;
5465 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5466 return TGSI_SEMANTIC_TESSINNER
;
5468 /* Compute shader */
5469 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5470 return TGSI_SEMANTIC_THREAD_ID
;
5471 case SYSTEM_VALUE_WORK_GROUP_ID
:
5472 return TGSI_SEMANTIC_BLOCK_ID
;
5473 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5474 return TGSI_SEMANTIC_GRID_SIZE
;
5475 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5476 return TGSI_SEMANTIC_BLOCK_SIZE
;
5479 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5480 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5481 case SYSTEM_VALUE_VERTEX_CNT
:
5483 assert(!"Unexpected SYSTEM_VALUE_ enum");
5484 return TGSI_SEMANTIC_COUNT
;
5489 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5491 static struct ureg_src
5492 emit_immediate(struct st_translate
*t
,
5493 gl_constant_value values
[4],
5496 struct ureg_program
*ureg
= t
->ureg
;
5501 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5503 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5505 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5506 case GL_UNSIGNED_INT64_ARB
:
5507 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5509 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5510 case GL_UNSIGNED_INT
:
5512 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5514 assert(!"should not get here - type must be float, int, uint, or bool");
5515 return ureg_src_undef();
5520 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5522 static struct ureg_dst
5523 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5529 case PROGRAM_UNDEFINED
:
5530 return ureg_dst_undef();
5532 case PROGRAM_TEMPORARY
:
5533 /* Allocate space for temporaries on demand. */
5534 if (index
>= t
->temps_size
) {
5535 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5537 t
->temps
= (struct ureg_dst
*)
5539 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5541 return ureg_dst_undef();
5543 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5544 t
->temps_size
+= inc
;
5547 if (ureg_dst_is_undef(t
->temps
[index
]))
5548 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5550 return t
->temps
[index
];
5553 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5554 array
= array_id
- 1;
5556 if (ureg_dst_is_undef(t
->arrays
[array
]))
5557 t
->arrays
[array
] = ureg_DECL_array_temporary(
5558 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5560 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5562 case PROGRAM_OUTPUT
:
5564 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5565 assert(index
< 2 * FRAG_RESULT_MAX
);
5566 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5567 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5568 assert(index
< VARYING_SLOT_TESS_MAX
);
5570 assert(index
< VARYING_SLOT_MAX
);
5572 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5573 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5574 return t
->outputs
[t
->outputMapping
[index
]];
5577 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5578 unsigned mesa_index
= decl
->mesa_index
;
5579 int slot
= t
->outputMapping
[mesa_index
];
5581 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5583 struct ureg_dst dst
= t
->outputs
[slot
];
5584 dst
.ArrayID
= array_id
;
5585 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5588 case PROGRAM_ADDRESS
:
5589 return t
->address
[index
];
5592 assert(!"unknown dst register file");
5593 return ureg_dst_undef();
5598 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5600 static struct ureg_src
5601 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5603 int index
= reg
->index
;
5604 int double_reg2
= reg
->double_reg2
? 1 : 0;
5607 case PROGRAM_UNDEFINED
:
5608 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5610 case PROGRAM_TEMPORARY
:
5612 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5614 case PROGRAM_OUTPUT
: {
5615 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5616 assert(dst
.WriteMask
!= 0);
5617 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5618 return ureg_swizzle(ureg_src(dst
),
5622 MIN2(shift
+ 3, 3));
5625 case PROGRAM_UNIFORM
:
5626 assert(reg
->index
>= 0);
5627 return reg
->index
< t
->num_constants
?
5628 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5629 case PROGRAM_STATE_VAR
:
5630 case PROGRAM_CONSTANT
: /* ie, immediate */
5631 if (reg
->has_index2
)
5632 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5634 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5635 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5637 case PROGRAM_IMMEDIATE
:
5638 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5639 return t
->immediates
[reg
->index
];
5642 /* GLSL inputs are 64-bit containers, so we have to
5643 * map back to the original index and add the offset after
5645 index
-= double_reg2
;
5646 if (!reg
->array_id
) {
5647 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5648 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5649 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5652 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5653 unsigned mesa_index
= decl
->mesa_index
;
5654 int slot
= t
->inputMapping
[mesa_index
];
5656 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5658 struct ureg_src src
= t
->inputs
[slot
];
5659 src
.ArrayID
= reg
->array_id
;
5660 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5663 case PROGRAM_ADDRESS
:
5664 return ureg_src(t
->address
[reg
->index
]);
5666 case PROGRAM_SYSTEM_VALUE
:
5667 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5668 return t
->systemValues
[reg
->index
];
5671 assert(!"unknown src register file");
5672 return ureg_src_undef();
5677 * Create a TGSI ureg_dst register from an st_dst_reg.
5679 static struct ureg_dst
5680 translate_dst(struct st_translate
*t
,
5681 const st_dst_reg
*dst_reg
,
5684 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5687 if (dst
.File
== TGSI_FILE_NULL
)
5690 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5693 dst
= ureg_saturate(dst
);
5695 if (dst_reg
->reladdr
!= NULL
) {
5696 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5697 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5700 if (dst_reg
->has_index2
) {
5701 if (dst_reg
->reladdr2
)
5702 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5705 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5712 * Create a TGSI ureg_src register from an st_src_reg.
5714 static struct ureg_src
5715 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5717 struct ureg_src src
= src_register(t
, src_reg
);
5719 if (src_reg
->has_index2
) {
5720 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5721 * and UBO constant buffers (buffer, position).
5723 if (src_reg
->reladdr2
)
5724 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5727 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5730 src
= ureg_swizzle(src
,
5731 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5732 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5733 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5734 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5737 src
= ureg_abs(src
);
5739 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5740 src
= ureg_negate(src
);
5742 if (src_reg
->reladdr
!= NULL
) {
5743 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5744 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5750 static struct tgsi_texture_offset
5751 translate_tex_offset(struct st_translate
*t
,
5752 const st_src_reg
*in_offset
)
5754 struct tgsi_texture_offset offset
;
5755 struct ureg_src src
= translate_src(t
, in_offset
);
5757 offset
.File
= src
.File
;
5758 offset
.Index
= src
.Index
;
5759 offset
.SwizzleX
= src
.SwizzleX
;
5760 offset
.SwizzleY
= src
.SwizzleY
;
5761 offset
.SwizzleZ
= src
.SwizzleZ
;
5764 assert(!src
.Indirect
);
5765 assert(!src
.DimIndirect
);
5766 assert(!src
.Dimension
);
5767 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5768 assert(!src
.Negate
);
5774 compile_tgsi_instruction(struct st_translate
*t
,
5775 const glsl_to_tgsi_instruction
*inst
)
5777 struct ureg_program
*ureg
= t
->ureg
;
5779 struct ureg_dst dst
[2];
5780 struct ureg_src src
[4];
5781 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5785 unsigned tex_target
= 0;
5787 num_dst
= num_inst_dst_regs(inst
);
5788 num_src
= num_inst_src_regs(inst
);
5790 for (i
= 0; i
< num_dst
; i
++)
5791 dst
[i
] = translate_dst(t
,
5795 for (i
= 0; i
< num_src
; i
++)
5796 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5799 case TGSI_OPCODE_BGNLOOP
:
5800 case TGSI_OPCODE_ELSE
:
5801 case TGSI_OPCODE_ENDLOOP
:
5802 case TGSI_OPCODE_IF
:
5803 case TGSI_OPCODE_UIF
:
5804 assert(num_dst
== 0);
5805 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5808 case TGSI_OPCODE_TEX
:
5809 case TGSI_OPCODE_TXB
:
5810 case TGSI_OPCODE_TXD
:
5811 case TGSI_OPCODE_TXL
:
5812 case TGSI_OPCODE_TXP
:
5813 case TGSI_OPCODE_TXQ
:
5814 case TGSI_OPCODE_TXQS
:
5815 case TGSI_OPCODE_TXF
:
5816 case TGSI_OPCODE_TEX2
:
5817 case TGSI_OPCODE_TXB2
:
5818 case TGSI_OPCODE_TXL2
:
5819 case TGSI_OPCODE_TG4
:
5820 case TGSI_OPCODE_LODQ
:
5821 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5822 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5823 if (inst
->resource
.reladdr
)
5825 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5827 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5828 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5830 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5836 texoffsets
, inst
->tex_offset_num_offset
,
5840 case TGSI_OPCODE_RESQ
:
5841 case TGSI_OPCODE_LOAD
:
5842 case TGSI_OPCODE_ATOMUADD
:
5843 case TGSI_OPCODE_ATOMXCHG
:
5844 case TGSI_OPCODE_ATOMCAS
:
5845 case TGSI_OPCODE_ATOMAND
:
5846 case TGSI_OPCODE_ATOMOR
:
5847 case TGSI_OPCODE_ATOMXOR
:
5848 case TGSI_OPCODE_ATOMUMIN
:
5849 case TGSI_OPCODE_ATOMUMAX
:
5850 case TGSI_OPCODE_ATOMIMIN
:
5851 case TGSI_OPCODE_ATOMIMAX
:
5852 for (i
= num_src
- 1; i
>= 0; i
--)
5853 src
[i
+ 1] = src
[i
];
5855 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5856 src
[0] = t
->shared_memory
;
5857 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5858 src
[0] = t
->buffers
[inst
->resource
.index
];
5860 src
[0] = t
->images
[inst
->resource
.index
];
5861 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5863 if (inst
->resource
.reladdr
)
5864 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5865 assert(src
[0].File
!= TGSI_FILE_NULL
);
5866 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5867 inst
->buffer_access
,
5868 tex_target
, inst
->image_format
);
5871 case TGSI_OPCODE_STORE
:
5872 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5873 dst
[0] = ureg_dst(t
->shared_memory
);
5874 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5875 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5877 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5878 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5880 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5881 if (inst
->resource
.reladdr
)
5882 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5883 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5884 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5885 inst
->buffer_access
,
5886 tex_target
, inst
->image_format
);
5889 case TGSI_OPCODE_SCS
:
5890 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5891 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5904 * Emit the TGSI instructions for inverting and adjusting WPOS.
5905 * This code is unavoidable because it also depends on whether
5906 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5909 emit_wpos_adjustment(struct gl_context
*ctx
,
5910 struct st_translate
*t
,
5911 int wpos_transform_const
,
5913 GLfloat adjX
, GLfloat adjY
[2])
5915 struct ureg_program
*ureg
= t
->ureg
;
5917 assert(wpos_transform_const
>= 0);
5919 /* Fragment program uses fragment position input.
5920 * Need to replace instances of INPUT[WPOS] with temp T
5921 * where T = INPUT[WPOS] is inverted by Y.
5923 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5924 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5925 struct ureg_src
*wpos
=
5926 ctx
->Const
.GLSLFragCoordIsSysVal
?
5927 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5928 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5929 struct ureg_src wpos_input
= *wpos
;
5931 /* First, apply the coordinate shift: */
5932 if (adjX
|| adjY
[0] || adjY
[1]) {
5933 if (adjY
[0] != adjY
[1]) {
5934 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5935 * depending on whether inversion is actually going to be applied
5936 * or not, which is determined by testing against the inversion
5937 * state variable used below, which will be either +1 or -1.
5939 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5941 ureg_CMP(ureg
, adj_temp
,
5942 ureg_scalar(wpostrans
, invert
? 2 : 0),
5943 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5944 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5945 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5947 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5948 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5950 wpos_input
= ureg_src(wpos_temp
);
5952 /* MOV wpos_temp, input[wpos]
5954 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5957 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5958 * inversion/identity, or the other way around if we're drawing to an FBO.
5961 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5964 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5966 ureg_scalar(wpostrans
, 0),
5967 ureg_scalar(wpostrans
, 1));
5969 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5972 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5974 ureg_scalar(wpostrans
, 2),
5975 ureg_scalar(wpostrans
, 3));
5978 /* Use wpos_temp as position input from here on:
5980 *wpos
= ureg_src(wpos_temp
);
5985 * Emit fragment position/ooordinate code.
5988 emit_wpos(struct st_context
*st
,
5989 struct st_translate
*t
,
5990 const struct gl_program
*program
,
5991 struct ureg_program
*ureg
,
5992 int wpos_transform_const
)
5994 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5995 GLfloat adjX
= 0.0f
;
5996 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5997 boolean invert
= FALSE
;
5999 /* Query the pixel center conventions supported by the pipe driver and set
6000 * adjX, adjY to help out if it cannot handle the requested one internally.
6002 * The bias of the y-coordinate depends on whether y-inversion takes place
6003 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6004 * drawing to an FBO (causes additional inversion), and whether the pipe
6005 * driver origin and the requested origin differ (the latter condition is
6006 * stored in the 'invert' variable).
6008 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6010 * center shift only:
6015 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6016 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6017 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6018 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6020 * inversion and center shift:
6021 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6022 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6023 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6024 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6026 if (program
->OriginUpperLeft
) {
6027 /* Fragment shader wants origin in upper-left */
6028 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6029 /* the driver supports upper-left origin */
6031 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6032 /* the driver supports lower-left origin, need to invert Y */
6033 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6034 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6041 /* Fragment shader wants origin in lower-left */
6042 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6043 /* the driver supports lower-left origin */
6044 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6045 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6046 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6047 /* the driver supports upper-left origin, need to invert Y */
6053 if (program
->PixelCenterInteger
) {
6054 /* Fragment shader wants pixel center integer */
6055 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6056 /* the driver supports pixel center integer */
6058 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6059 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6061 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6062 /* the driver supports pixel center half integer, need to bias X,Y */
6071 /* Fragment shader wants pixel center half integer */
6072 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6073 /* the driver supports pixel center half integer */
6075 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6076 /* the driver supports pixel center integer, need to bias X,Y */
6077 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6078 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6079 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6085 /* we invert after adjustment so that we avoid the MOV to temporary,
6086 * and reuse the adjustment ADD instead */
6087 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6091 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6092 * TGSI uses +1 for front, -1 for back.
6093 * This function converts the TGSI value to the GL value. Simply clamping/
6094 * saturating the value to [0,1] does the job.
6097 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6099 struct ureg_program
*ureg
= t
->ureg
;
6100 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6101 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6103 if (ctx
->Const
.NativeIntegers
) {
6104 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6107 /* MOV_SAT face_temp, input[face] */
6108 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6111 /* Use face_temp as face input from here on: */
6112 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6116 emit_compute_block_size(const struct gl_program
*prog
,
6117 struct ureg_program
*ureg
) {
6118 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6119 prog
->info
.cs
.local_size
[0]);
6120 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6121 prog
->info
.cs
.local_size
[1]);
6122 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6123 prog
->info
.cs
.local_size
[2]);
6126 struct sort_inout_decls
{
6127 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6128 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6131 const GLuint
*mapping
;
6134 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6136 * This is for the benefit of older drivers which are broken when the
6137 * declarations aren't sorted in this way.
6140 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6142 const GLuint mapping
[])
6144 sort_inout_decls sorter
;
6145 sorter
.mapping
= mapping
;
6146 std::sort(decls
, decls
+ count
, sorter
);
6150 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6152 switch (glsl_qual
) {
6153 case INTERP_MODE_NONE
:
6154 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6155 return TGSI_INTERPOLATE_COLOR
;
6156 return TGSI_INTERPOLATE_PERSPECTIVE
;
6157 case INTERP_MODE_SMOOTH
:
6158 return TGSI_INTERPOLATE_PERSPECTIVE
;
6159 case INTERP_MODE_FLAT
:
6160 return TGSI_INTERPOLATE_CONSTANT
;
6161 case INTERP_MODE_NOPERSPECTIVE
:
6162 return TGSI_INTERPOLATE_LINEAR
;
6164 assert(0 && "unexpected interp mode in st_translate_interp()");
6165 return TGSI_INTERPOLATE_PERSPECTIVE
;
6170 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6171 * \param program the program to translate
6172 * \param numInputs number of input registers used
6173 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6175 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6176 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6178 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6179 * \param numOutputs number of output registers used
6180 * \param outputMapping maps Mesa fragment program outputs to TGSI
6182 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6183 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6186 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6188 extern "C" enum pipe_error
6189 st_translate_program(
6190 struct gl_context
*ctx
,
6192 struct ureg_program
*ureg
,
6193 glsl_to_tgsi_visitor
*program
,
6194 const struct gl_program
*proginfo
,
6196 const GLuint inputMapping
[],
6197 const GLuint inputSlotToAttr
[],
6198 const ubyte inputSemanticName
[],
6199 const ubyte inputSemanticIndex
[],
6200 const GLuint interpMode
[],
6202 const GLuint outputMapping
[],
6203 const GLuint outputSlotToAttr
[],
6204 const ubyte outputSemanticName
[],
6205 const ubyte outputSemanticIndex
[])
6207 struct st_translate
*t
;
6209 struct gl_program_constants
*frag_const
=
6210 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6211 enum pipe_error ret
= PIPE_OK
;
6213 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6214 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6216 t
= CALLOC_STRUCT(st_translate
);
6218 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6222 t
->procType
= procType
;
6223 t
->inputMapping
= inputMapping
;
6224 t
->outputMapping
= outputMapping
;
6226 t
->num_temp_arrays
= program
->next_array
;
6227 if (t
->num_temp_arrays
)
6228 t
->arrays
= (struct ureg_dst
*)
6229 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6232 * Declare input attributes.
6235 case PIPE_SHADER_FRAGMENT
:
6236 case PIPE_SHADER_GEOMETRY
:
6237 case PIPE_SHADER_TESS_EVAL
:
6238 case PIPE_SHADER_TESS_CTRL
:
6239 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6241 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6242 struct inout_decl
*decl
= &program
->inputs
[i
];
6243 unsigned slot
= inputMapping
[decl
->mesa_index
];
6244 struct ureg_src src
;
6245 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6247 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6248 if (tgsi_usage_mask
== 1)
6249 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6250 else if (tgsi_usage_mask
== 2)
6251 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6253 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6256 unsigned interp_mode
= 0;
6257 unsigned interp_location
= 0;
6258 if (procType
== PIPE_SHADER_FRAGMENT
) {
6260 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6262 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6264 interp_location
= decl
->interp_loc
;
6267 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6268 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6269 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6270 decl
->array_id
, decl
->size
);
6272 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6273 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6274 /* The ArrayID is set up in dst_register */
6275 t
->inputs
[slot
+ j
] = src
;
6276 t
->inputs
[slot
+ j
].ArrayID
= 0;
6277 t
->inputs
[slot
+ j
].Index
+= j
;
6282 case PIPE_SHADER_VERTEX
:
6283 for (i
= 0; i
< numInputs
; i
++) {
6284 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6287 case PIPE_SHADER_COMPUTE
:
6294 * Declare output attributes.
6297 case PIPE_SHADER_FRAGMENT
:
6298 case PIPE_SHADER_COMPUTE
:
6300 case PIPE_SHADER_GEOMETRY
:
6301 case PIPE_SHADER_TESS_EVAL
:
6302 case PIPE_SHADER_TESS_CTRL
:
6303 case PIPE_SHADER_VERTEX
:
6304 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6306 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6307 struct inout_decl
*decl
= &program
->outputs
[i
];
6308 unsigned slot
= outputMapping
[decl
->mesa_index
];
6309 struct ureg_dst dst
;
6310 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6312 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6313 if (tgsi_usage_mask
== 1)
6314 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6315 else if (tgsi_usage_mask
== 2)
6316 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6318 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6321 dst
= ureg_DECL_output_layout(ureg
,
6322 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6323 decl
->gs_out_streams
,
6324 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6326 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6327 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6328 /* The ArrayID is set up in dst_register */
6329 t
->outputs
[slot
+ j
] = dst
;
6330 t
->outputs
[slot
+ j
].ArrayID
= 0;
6331 t
->outputs
[slot
+ j
].Index
+= j
;
6340 if (procType
== PIPE_SHADER_FRAGMENT
) {
6341 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
)
6342 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6344 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6345 /* Must do this after setting up t->inputs. */
6346 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6347 program
->wpos_transform_const
);
6350 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6351 emit_face_var(ctx
, t
);
6353 for (i
= 0; i
< numOutputs
; i
++) {
6354 switch (outputSemanticName
[i
]) {
6355 case TGSI_SEMANTIC_POSITION
:
6356 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6357 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6358 outputSemanticIndex
[i
]);
6359 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6361 case TGSI_SEMANTIC_STENCIL
:
6362 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6363 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6364 outputSemanticIndex
[i
]);
6365 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6367 case TGSI_SEMANTIC_COLOR
:
6368 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6369 TGSI_SEMANTIC_COLOR
,
6370 outputSemanticIndex
[i
]);
6372 case TGSI_SEMANTIC_SAMPLEMASK
:
6373 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6374 TGSI_SEMANTIC_SAMPLEMASK
,
6375 outputSemanticIndex
[i
]);
6376 /* TODO: If we ever support more than 32 samples, this will have
6377 * to become an array.
6379 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6382 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6383 ret
= PIPE_ERROR_BAD_INPUT
;
6388 else if (procType
== PIPE_SHADER_VERTEX
) {
6389 for (i
= 0; i
< numOutputs
; i
++) {
6390 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6391 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6393 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6394 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6395 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6400 if (procType
== PIPE_SHADER_COMPUTE
) {
6401 emit_compute_block_size(proginfo
, ureg
);
6404 /* Declare address register.
6406 if (program
->num_address_regs
> 0) {
6407 assert(program
->num_address_regs
<= 3);
6408 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6409 t
->address
[i
] = ureg_DECL_address(ureg
);
6412 /* Declare misc input registers
6415 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6417 for (i
= 0; sysInputs
; i
++) {
6418 if (sysInputs
& (1 << i
)) {
6419 unsigned semName
= _mesa_sysval_to_semantic(i
);
6421 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6423 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6424 semName
== TGSI_SEMANTIC_VERTEXID
) {
6425 /* From Gallium perspective, these system values are always
6426 * integer, and require native integer support. However, if
6427 * native integer is supported on the vertex stage but not the
6428 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6429 * assumes these system values are floats. To resolve the
6430 * inconsistency, we insert a U2F.
6432 struct st_context
*st
= st_context(ctx
);
6433 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6434 assert(procType
== PIPE_SHADER_VERTEX
);
6435 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6437 if (!ctx
->Const
.NativeIntegers
) {
6438 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6439 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6440 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6444 if (procType
== PIPE_SHADER_FRAGMENT
&&
6445 semName
== TGSI_SEMANTIC_POSITION
)
6446 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6447 program
->wpos_transform_const
);
6449 sysInputs
&= ~(1 << i
);
6454 t
->array_sizes
= program
->array_sizes
;
6455 t
->input_decls
= program
->inputs
;
6456 t
->num_input_decls
= program
->num_inputs
;
6457 t
->output_decls
= program
->outputs
;
6458 t
->num_output_decls
= program
->num_outputs
;
6460 /* Emit constants and uniforms. TGSI uses a single index space for these,
6461 * so we put all the translated regs in t->constants.
6463 if (proginfo
->Parameters
) {
6464 t
->constants
= (struct ureg_src
*)
6465 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6466 if (t
->constants
== NULL
) {
6467 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6470 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6472 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6473 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6474 case PROGRAM_STATE_VAR
:
6475 case PROGRAM_UNIFORM
:
6476 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6479 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6480 * addressing of the const buffer.
6481 * FIXME: Be smarter and recognize param arrays:
6482 * indirect addressing is only valid within the referenced
6485 case PROGRAM_CONSTANT
:
6486 if (program
->indirect_addr_consts
)
6487 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6489 t
->constants
[i
] = emit_immediate(t
,
6490 proginfo
->Parameters
->ParameterValues
[i
],
6491 proginfo
->Parameters
->Parameters
[i
].DataType
,
6500 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6501 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6502 unsigned num_const_vecs
= (size
+ 15) / 16;
6503 unsigned first
, last
;
6504 assert(num_const_vecs
> 0);
6506 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6507 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6510 /* Emit immediate values.
6512 t
->immediates
= (struct ureg_src
*)
6513 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6514 if (t
->immediates
== NULL
) {
6515 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6518 t
->num_immediates
= program
->num_immediates
;
6521 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6522 assert(i
< program
->num_immediates
);
6523 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6525 assert(i
== program
->num_immediates
);
6527 /* texture samplers */
6528 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6529 if (program
->samplers_used
& (1u << i
)) {
6532 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6534 switch (program
->sampler_types
[i
]) {
6536 type
= TGSI_RETURN_TYPE_SINT
;
6538 case GLSL_TYPE_UINT
:
6539 type
= TGSI_RETURN_TYPE_UINT
;
6541 case GLSL_TYPE_FLOAT
:
6542 type
= TGSI_RETURN_TYPE_FLOAT
;
6545 unreachable("not reached");
6548 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6549 type
, type
, type
, type
);
6553 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6554 if (program
->buffers_used
& (1 << i
)) {
6555 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6559 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6561 if (program
->buffers_used
& (1 << i
)) {
6562 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6566 if (program
->use_shared_memory
)
6567 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6569 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6570 if (program
->images_used
& (1 << i
)) {
6571 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6572 program
->image_targets
[i
],
6573 program
->image_formats
[i
],
6578 /* Emit each instruction in turn:
6580 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6581 compile_tgsi_instruction(t
, inst
);
6583 /* Set the next shader stage hint for VS and TES. */
6585 case PIPE_SHADER_VERTEX
:
6586 case PIPE_SHADER_TESS_EVAL
:
6587 if (program
->shader_program
->SeparateShader
)
6590 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6591 if (program
->shader_program
->_LinkedShaders
[i
]) {
6595 case MESA_SHADER_TESS_CTRL
:
6596 next
= PIPE_SHADER_TESS_CTRL
;
6598 case MESA_SHADER_TESS_EVAL
:
6599 next
= PIPE_SHADER_TESS_EVAL
;
6601 case MESA_SHADER_GEOMETRY
:
6602 next
= PIPE_SHADER_GEOMETRY
;
6604 case MESA_SHADER_FRAGMENT
:
6605 next
= PIPE_SHADER_FRAGMENT
;
6612 ureg_set_next_shader_processor(ureg
, next
);
6624 t
->num_constants
= 0;
6625 free(t
->immediates
);
6626 t
->num_immediates
= 0;
6632 /* ----------------------------- End TGSI code ------------------------------ */
6636 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6637 * generating Mesa IR.
6639 static struct gl_program
*
6640 get_mesa_program_tgsi(struct gl_context
*ctx
,
6641 struct gl_shader_program
*shader_program
,
6642 struct gl_linked_shader
*shader
)
6644 glsl_to_tgsi_visitor
* v
;
6645 struct gl_program
*prog
;
6646 struct gl_shader_compiler_options
*options
=
6647 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6648 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6649 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6651 validate_ir_tree(shader
->ir
);
6653 prog
= shader
->Program
;
6655 prog
->Parameters
= _mesa_new_parameter_list();
6656 v
= new glsl_to_tgsi_visitor();
6659 v
->shader_program
= shader_program
;
6661 v
->options
= options
;
6662 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6663 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6665 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6666 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6667 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6668 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6670 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6673 /* Remove reads from output registers. */
6674 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6675 lower_output_reads(shader
->Stage
, shader
->ir
);
6677 /* Emit intermediate IR for main(). */
6678 visit_exec_list(shader
->ir
, v
);
6681 /* Print out some information (for debugging purposes) used by the
6682 * optimization passes. */
6685 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6686 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6687 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6688 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6690 for (i
= 0; i
< v
->next_temp
; i
++) {
6691 first_writes
[i
] = -1;
6692 first_reads
[i
] = -1;
6693 last_writes
[i
] = -1;
6696 v
->get_first_temp_read(first_reads
);
6697 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6698 v
->get_last_temp_write(last_writes
);
6699 for (i
= 0; i
< v
->next_temp
; i
++)
6700 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6704 ralloc_free(first_writes
);
6705 ralloc_free(first_reads
);
6706 ralloc_free(last_writes
);
6707 ralloc_free(last_reads
);
6711 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6714 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6715 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6716 v
->copy_propagate();
6718 while (v
->eliminate_dead_code());
6720 v
->merge_two_dsts();
6721 v
->merge_registers();
6722 v
->renumber_registers();
6724 /* Write the END instruction. */
6725 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6727 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6729 _mesa_log("GLSL IR for linked %s program %d:\n",
6730 _mesa_shader_stage_to_string(shader
->Stage
),
6731 shader_program
->Name
);
6732 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6736 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6737 _mesa_copy_linked_program_data(shader_program
, shader
);
6738 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6739 &prog
->info
.inputs_read
,
6740 prog
->info
.double_inputs_read
,
6741 &prog
->info
.patch_inputs_read
);
6742 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6743 &prog
->info
.outputs_written
, 0ULL,
6744 &prog
->info
.patch_outputs_written
);
6745 count_resources(v
, prog
);
6747 /* The GLSL IR won't be needed anymore. */
6748 ralloc_free(shader
->ir
);
6751 /* This must be done before the uniform storage is associated. */
6752 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6753 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6754 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6755 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6756 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6759 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6760 wposTransformState
);
6763 /* Avoid reallocation of the program parameter list, because the uniform
6764 * storage is only associated with the original parameter list.
6765 * This should be enough for Bitmap and DrawPixels constants.
6767 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6769 /* This has to be done last. Any operation the can cause
6770 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6771 * program constant) has to happen before creating this linkage.
6773 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
,
6775 if (!shader_program
->data
->LinkStatus
) {
6776 free_glsl_to_tgsi_visitor(v
);
6777 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6781 struct st_vertex_program
*stvp
;
6782 struct st_fragment_program
*stfp
;
6783 struct st_geometry_program
*stgp
;
6784 struct st_tessctrl_program
*sttcp
;
6785 struct st_tesseval_program
*sttep
;
6786 struct st_compute_program
*stcp
;
6788 switch (shader
->Stage
) {
6789 case MESA_SHADER_VERTEX
:
6790 stvp
= (struct st_vertex_program
*)prog
;
6791 stvp
->glsl_to_tgsi
= v
;
6793 case MESA_SHADER_FRAGMENT
:
6794 stfp
= (struct st_fragment_program
*)prog
;
6795 stfp
->glsl_to_tgsi
= v
;
6797 case MESA_SHADER_GEOMETRY
:
6798 stgp
= (struct st_geometry_program
*)prog
;
6799 stgp
->glsl_to_tgsi
= v
;
6801 case MESA_SHADER_TESS_CTRL
:
6802 sttcp
= (struct st_tessctrl_program
*)prog
;
6803 sttcp
->glsl_to_tgsi
= v
;
6805 case MESA_SHADER_TESS_EVAL
:
6806 sttep
= (struct st_tesseval_program
*)prog
;
6807 sttep
->glsl_to_tgsi
= v
;
6809 case MESA_SHADER_COMPUTE
:
6810 stcp
= (struct st_compute_program
*)prog
;
6811 stcp
->glsl_to_tgsi
= v
;
6814 assert(!"should not be reached");
6821 /* See if there are unsupported control flow statements. */
6822 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6824 const struct gl_shader_compiler_options
*options
;
6826 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6832 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6834 /* Other functions are skipped (same as glsl_to_tgsi). */
6835 if (strcmp(ir
->name
, "main") == 0)
6836 return visit_continue
;
6838 return visit_continue_with_parent
;
6841 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6843 if (!ir
->callee
->is_intrinsic()) {
6844 unsupported
= true; /* it's a function call */
6847 return visit_continue
;
6850 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6852 if (options
->EmitNoMainReturn
) {
6856 return visit_continue
;
6863 has_unsupported_control_flow(exec_list
*ir
,
6864 const struct gl_shader_compiler_options
*options
)
6866 ir_control_flow_info_visitor
visitor(options
);
6867 visit_list_elements(&visitor
, ir
);
6868 return visitor
.unsupported
;
6875 * Called via ctx->Driver.LinkShader()
6876 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6877 * with code lowering and other optimizations.
6880 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6882 /* Return early if we are loading the shader from on-disk cache */
6883 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6887 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6888 assert(prog
->data
->LinkStatus
);
6890 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6891 if (prog
->_LinkedShaders
[i
] == NULL
)
6894 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6895 exec_list
*ir
= shader
->ir
;
6896 gl_shader_stage stage
= shader
->Stage
;
6897 const struct gl_shader_compiler_options
*options
=
6898 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6899 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6900 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6901 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6902 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6903 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6904 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6905 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6907 /* If there are forms of indirect addressing that the driver
6908 * cannot handle, perform the lowering pass.
6910 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6911 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6912 lower_variable_index_to_cond_assign(stage
, ir
,
6913 options
->EmitNoIndirectInput
,
6914 options
->EmitNoIndirectOutput
,
6915 options
->EmitNoIndirectTemp
,
6916 options
->EmitNoIndirectUniform
);
6919 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6920 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6922 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6923 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6924 LOWER_UNPACK_SNORM_2x16
|
6925 LOWER_PACK_UNORM_2x16
|
6926 LOWER_UNPACK_UNORM_2x16
|
6927 LOWER_PACK_SNORM_4x8
|
6928 LOWER_UNPACK_SNORM_4x8
|
6929 LOWER_UNPACK_UNORM_4x8
|
6930 LOWER_PACK_UNORM_4x8
;
6932 if (ctx
->Extensions
.ARB_gpu_shader5
)
6933 lower_inst
|= LOWER_PACK_USE_BFI
|
6935 if (!ctx
->st
->has_half_float_packing
)
6936 lower_inst
|= LOWER_PACK_HALF_2x16
|
6937 LOWER_UNPACK_HALF_2x16
;
6939 lower_packing_builtins(ir
, lower_inst
);
6942 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6943 lower_offset_arrays(ir
);
6944 do_mat_op_to_vec(ir
);
6946 if (stage
== MESA_SHADER_FRAGMENT
)
6947 lower_blend_equation_advanced(shader
);
6949 lower_instructions(ir
,
6955 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6958 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6959 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6960 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6961 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6962 /* Assume that if ARB_gpu_shader5 is not supported
6963 * then all of the extended integer functions need
6964 * lowering. It may be necessary to add some caps
6965 * for individual instructions.
6967 (!ctx
->Extensions
.ARB_gpu_shader5
6968 ? BIT_COUNT_TO_MATH
|
6972 FIND_LSB_TO_FLOAT_CAST
|
6973 FIND_MSB_TO_FLOAT_CAST
|
6977 do_vec_index_to_cond_assign(ir
);
6978 lower_vector_insert(ir
, true);
6979 lower_quadop_vector(ir
, false);
6981 if (options
->MaxIfDepth
== 0) {
6985 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6986 /* Do it once and repeat only if there's unsupported control flow. */
6988 do_common_optimization(ir
, true, true, options
,
6989 ctx
->Const
.NativeIntegers
);
6990 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6991 options
->MaxIfDepth
, if_threshold
);
6992 } while (has_unsupported_control_flow(ir
, options
));
6994 /* Repeat it until it stops making changes. */
6997 progress
= do_common_optimization(ir
, true, true, options
,
6998 ctx
->Const
.NativeIntegers
);
6999 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7000 options
->MaxIfDepth
, if_threshold
);
7004 validate_ir_tree(ir
);
7007 build_program_resource_list(ctx
, prog
);
7009 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7010 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7014 enum pipe_shader_type ptarget
=
7015 st_shader_stage_to_ptarget(shader
->Stage
);
7016 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7017 pscreen
->get_shader_param(pscreen
, ptarget
,
7018 PIPE_SHADER_CAP_PREFERRED_IR
);
7020 struct gl_program
*linked_prog
= NULL
;
7021 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
7022 /* TODO only for GLSL VS/FS for now: */
7023 switch (shader
->Stage
) {
7024 case MESA_SHADER_VERTEX
:
7025 case MESA_SHADER_FRAGMENT
:
7026 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
7031 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
7035 st_set_prog_affected_state_flags(linked_prog
);
7036 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7037 _mesa_shader_stage_to_program(i
),
7039 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7049 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7050 const GLuint outputMapping
[],
7051 struct pipe_stream_output_info
*so
)
7053 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7056 struct gl_transform_feedback_info
*info
=
7057 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7058 st_translate_stream_output_info2(info
, outputMapping
, so
);
7062 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7063 const GLuint outputMapping
[],
7064 struct pipe_stream_output_info
*so
)
7068 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7069 so
->output
[i
].register_index
=
7070 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7071 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7072 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7073 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7074 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7075 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7078 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7079 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7081 so
->num_outputs
= info
->NumOutputs
;