2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
57 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
58 (1 << PROGRAM_CONSTANT) | \
59 (1 << PROGRAM_UNIFORM))
61 #define MAX_GLSL_TEXTURE_OFFSET 4
66 static int swizzle_for_size(int size
);
69 * This struct is a corresponding struct to TGSI ureg_src.
73 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= SWIZZLE_XYZW
;
83 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
85 this->reladdr2
= NULL
;
86 this->has_index2
= false;
87 this->double_reg2
= false;
89 this->is_double_vertex_input
= false;
92 st_src_reg(gl_register_file file
, int index
, int type
)
98 this->swizzle
= SWIZZLE_XYZW
;
100 this->reladdr
= NULL
;
101 this->reladdr2
= NULL
;
102 this->has_index2
= false;
103 this->double_reg2
= false;
105 this->is_double_vertex_input
= false;
108 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
113 this->index2D
= index2D
;
114 this->swizzle
= SWIZZLE_XYZW
;
116 this->reladdr
= NULL
;
117 this->reladdr2
= NULL
;
118 this->has_index2
= false;
119 this->double_reg2
= false;
121 this->is_double_vertex_input
= false;
126 this->type
= GLSL_TYPE_ERROR
;
127 this->file
= PROGRAM_UNDEFINED
;
132 this->reladdr
= NULL
;
133 this->reladdr2
= NULL
;
134 this->has_index2
= false;
135 this->double_reg2
= false;
137 this->is_double_vertex_input
= false;
140 explicit st_src_reg(st_dst_reg reg
);
142 gl_register_file file
; /**< PROGRAM_* from Mesa */
143 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
145 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
146 int negate
; /**< NEGATE_XYZW mask from mesa */
147 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
148 /** Register index should be offset by the integer in this reg. */
150 st_src_reg
*reladdr2
;
153 * Is this the second half of a double register pair?
154 * currently used for input mapping only.
158 bool is_double_vertex_input
;
163 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
168 this->writemask
= writemask
;
169 this->cond_mask
= COND_TR
;
170 this->reladdr
= NULL
;
171 this->reladdr2
= NULL
;
172 this->has_index2
= false;
177 st_dst_reg(gl_register_file file
, int writemask
, int type
)
182 this->writemask
= writemask
;
183 this->cond_mask
= COND_TR
;
184 this->reladdr
= NULL
;
185 this->reladdr2
= NULL
;
186 this->has_index2
= false;
193 this->type
= GLSL_TYPE_ERROR
;
194 this->file
= PROGRAM_UNDEFINED
;
198 this->cond_mask
= COND_TR
;
199 this->reladdr
= NULL
;
200 this->reladdr2
= NULL
;
201 this->has_index2
= false;
205 explicit st_dst_reg(st_src_reg reg
);
207 gl_register_file file
; /**< PROGRAM_* from Mesa */
208 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
210 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
212 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
213 /** Register index should be offset by the integer in this reg. */
215 st_src_reg
*reladdr2
;
220 st_src_reg::st_src_reg(st_dst_reg reg
)
222 this->type
= reg
.type
;
223 this->file
= reg
.file
;
224 this->index
= reg
.index
;
225 this->swizzle
= SWIZZLE_XYZW
;
227 this->reladdr
= reg
.reladdr
;
228 this->index2D
= reg
.index2D
;
229 this->reladdr2
= reg
.reladdr2
;
230 this->has_index2
= reg
.has_index2
;
231 this->double_reg2
= false;
232 this->array_id
= reg
.array_id
;
233 this->is_double_vertex_input
= false;
236 st_dst_reg::st_dst_reg(st_src_reg reg
)
238 this->type
= reg
.type
;
239 this->file
= reg
.file
;
240 this->index
= reg
.index
;
241 this->writemask
= WRITEMASK_XYZW
;
242 this->cond_mask
= COND_TR
;
243 this->reladdr
= reg
.reladdr
;
244 this->index2D
= reg
.index2D
;
245 this->reladdr2
= reg
.reladdr2
;
246 this->has_index2
= reg
.has_index2
;
247 this->array_id
= reg
.array_id
;
250 class glsl_to_tgsi_instruction
: public exec_node
{
252 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
257 /** Pointer to the ir source this tree came from for debugging */
259 GLboolean cond_update
;
261 st_src_reg sampler
; /**< sampler register */
263 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
264 int tex_target
; /**< One of TEXTURE_*_INDEX */
265 glsl_base_type tex_type
;
266 GLboolean tex_shadow
;
267 unsigned image_format
;
269 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
270 unsigned tex_offset_num_offset
;
271 int dead_mask
; /**< Used in dead code elimination */
273 st_src_reg buffer
; /**< buffer register */
274 unsigned buffer_access
; /**< buffer access type */
276 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
277 const struct tgsi_opcode_info
*info
;
280 class variable_storage
: public exec_node
{
282 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
283 unsigned array_id
= 0)
284 : file(file
), index(index
), var(var
), array_id(array_id
)
289 gl_register_file file
;
291 ir_variable
*var
; /* variable that maps to this, if any */
295 class immediate_storage
: public exec_node
{
297 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
299 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
300 this->size32
= size32
;
304 /* doubles are stored across 2 gl_constant_values */
305 gl_constant_value values
[4];
306 int size32
; /**< Number of 32-bit components (1-4) */
307 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
310 class function_entry
: public exec_node
{
312 ir_function_signature
*sig
;
315 * identifier of this function signature used by the program.
317 * At the point that TGSI instructions for function calls are
318 * generated, we don't know the address of the first instruction of
319 * the function body. So we make the BranchTarget that is called a
320 * small integer and rewrite them during set_branchtargets().
325 * Pointer to first instruction of the function body.
327 * Set during function body emits after main() is processed.
329 glsl_to_tgsi_instruction
*bgn_inst
;
332 * Index of the first instruction of the function body in actual TGSI.
334 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
338 /** Storage for the return value. */
339 st_src_reg return_reg
;
342 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
343 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
353 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
357 for (i
= 0; i
< count
; i
++) {
358 struct array_decl
*decl
= &arrays
[i
];
360 if (array_id
== decl
->array_id
) {
361 return decl
->array_type
;
364 return GLSL_TYPE_ERROR
;
367 struct rename_reg_pair
{
372 struct glsl_to_tgsi_visitor
: public ir_visitor
{
374 glsl_to_tgsi_visitor();
375 ~glsl_to_tgsi_visitor();
377 function_entry
*current_function
;
379 struct gl_context
*ctx
;
380 struct gl_program
*prog
;
381 struct gl_shader_program
*shader_program
;
382 struct gl_shader
*shader
;
383 struct gl_shader_compiler_options
*options
;
387 unsigned *array_sizes
;
388 unsigned max_num_arrays
;
391 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
392 unsigned num_input_arrays
;
393 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
394 unsigned num_output_arrays
;
396 int num_address_regs
;
398 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
399 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
402 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
403 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
404 bool indirect_addr_consts
;
405 int wpos_transform_const
;
408 bool native_integers
;
411 bool use_shared_memory
;
413 variable_storage
*find_variable_storage(ir_variable
*var
);
415 int add_constant(gl_register_file file
, gl_constant_value values
[8],
416 int size
, int datatype
, GLuint
*swizzle_out
);
418 function_entry
*get_function_signature(ir_function_signature
*sig
);
420 st_src_reg
get_temp(const glsl_type
*type
);
421 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
423 st_src_reg
st_src_reg_for_double(double val
);
424 st_src_reg
st_src_reg_for_float(float val
);
425 st_src_reg
st_src_reg_for_int(int val
);
426 st_src_reg
st_src_reg_for_type(int type
, int val
);
429 * \name Visit methods
431 * As typical for the visitor pattern, there must be one \c visit method for
432 * each concrete subclass of \c ir_instruction. Virtual base classes within
433 * the hierarchy should not have \c visit methods.
436 virtual void visit(ir_variable
*);
437 virtual void visit(ir_loop
*);
438 virtual void visit(ir_loop_jump
*);
439 virtual void visit(ir_function_signature
*);
440 virtual void visit(ir_function
*);
441 virtual void visit(ir_expression
*);
442 virtual void visit(ir_swizzle
*);
443 virtual void visit(ir_dereference_variable
*);
444 virtual void visit(ir_dereference_array
*);
445 virtual void visit(ir_dereference_record
*);
446 virtual void visit(ir_assignment
*);
447 virtual void visit(ir_constant
*);
448 virtual void visit(ir_call
*);
449 virtual void visit(ir_return
*);
450 virtual void visit(ir_discard
*);
451 virtual void visit(ir_texture
*);
452 virtual void visit(ir_if
*);
453 virtual void visit(ir_emit_vertex
*);
454 virtual void visit(ir_end_primitive
*);
455 virtual void visit(ir_barrier
*);
458 void visit_atomic_counter_intrinsic(ir_call
*);
459 void visit_ssbo_intrinsic(ir_call
*);
460 void visit_membar_intrinsic(ir_call
*);
461 void visit_shared_intrinsic(ir_call
*);
462 void visit_image_intrinsic(ir_call
*);
466 /** List of variable_storage */
469 /** List of immediate_storage */
470 exec_list immediates
;
471 unsigned num_immediates
;
473 /** List of function_entry */
474 exec_list function_signatures
;
475 int next_signature_id
;
477 /** List of glsl_to_tgsi_instruction */
478 exec_list instructions
;
480 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
481 st_dst_reg dst
= undef_dst
,
482 st_src_reg src0
= undef_src
,
483 st_src_reg src1
= undef_src
,
484 st_src_reg src2
= undef_src
,
485 st_src_reg src3
= undef_src
);
487 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
488 st_dst_reg dst
, st_dst_reg dst1
,
489 st_src_reg src0
= undef_src
,
490 st_src_reg src1
= undef_src
,
491 st_src_reg src2
= undef_src
,
492 st_src_reg src3
= undef_src
);
494 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
496 st_src_reg src0
, st_src_reg src1
);
499 * Emit the correct dot-product instruction for the type of arguments
501 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
507 void emit_scalar(ir_instruction
*ir
, unsigned op
,
508 st_dst_reg dst
, st_src_reg src0
);
510 void emit_scalar(ir_instruction
*ir
, unsigned op
,
511 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
513 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
515 void get_deref_offsets(ir_dereference
*ir
,
516 unsigned *array_size
,
519 st_src_reg
*reladdr
);
520 void calc_deref_offsets(ir_dereference
*head
,
521 ir_dereference
*tail
,
522 unsigned *array_elements
,
525 st_src_reg
*indirect
,
528 bool try_emit_mad(ir_expression
*ir
,
530 bool try_emit_mad_for_and_not(ir_expression
*ir
,
533 void emit_swz(ir_expression
*ir
);
535 bool process_move_condition(ir_rvalue
*ir
);
537 void simplify_cmp(void);
539 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
540 void get_first_temp_read(int *first_reads
);
541 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
542 void get_last_temp_write(int *last_writes
);
544 void copy_propagate(void);
545 int eliminate_dead_code(void);
547 void merge_two_dsts(void);
548 void merge_registers(void);
549 void renumber_registers(void);
551 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
552 st_dst_reg
*l
, st_src_reg
*r
,
553 st_src_reg
*cond
, bool cond_swap
);
558 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
559 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
560 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
563 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
566 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
570 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
573 prog
->LinkStatus
= GL_FALSE
;
577 swizzle_for_size(int size
)
579 static const int size_swizzles
[4] = {
580 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
581 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
582 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
583 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
586 assert((size
>= 1) && (size
<= 4));
587 return size_swizzles
[size
- 1];
591 is_resource_instruction(unsigned opcode
)
594 case TGSI_OPCODE_RESQ
:
595 case TGSI_OPCODE_LOAD
:
596 case TGSI_OPCODE_ATOMUADD
:
597 case TGSI_OPCODE_ATOMXCHG
:
598 case TGSI_OPCODE_ATOMCAS
:
599 case TGSI_OPCODE_ATOMAND
:
600 case TGSI_OPCODE_ATOMOR
:
601 case TGSI_OPCODE_ATOMXOR
:
602 case TGSI_OPCODE_ATOMUMIN
:
603 case TGSI_OPCODE_ATOMUMAX
:
604 case TGSI_OPCODE_ATOMIMIN
:
605 case TGSI_OPCODE_ATOMIMAX
:
613 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
615 return op
->info
->num_dst
;
619 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
621 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
622 op
->info
->num_src
- 1 : op
->info
->num_src
;
625 glsl_to_tgsi_instruction
*
626 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
627 st_dst_reg dst
, st_dst_reg dst1
,
628 st_src_reg src0
, st_src_reg src1
,
629 st_src_reg src2
, st_src_reg src3
)
631 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
632 int num_reladdr
= 0, i
, j
;
633 bool dst_is_double
[2];
635 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
637 /* If we have to do relative addressing, we want to load the ARL
638 * reg directly for one of the regs, and preload the other reladdr
639 * sources into temps.
641 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
642 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
643 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
644 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
645 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
646 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
648 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
649 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
650 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
651 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
653 if (dst
.reladdr
|| dst
.reladdr2
) {
655 emit_arl(ir
, address_reg
, *dst
.reladdr
);
657 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
661 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
664 assert(num_reladdr
== 0);
667 inst
->info
= tgsi_get_opcode_info(op
);
676 /* default to float, for paths where this is not initialized
677 * (since 0==UINT which is likely wrong):
679 inst
->tex_type
= GLSL_TYPE_FLOAT
;
681 inst
->function
= NULL
;
683 /* Update indirect addressing status used by TGSI */
684 if (dst
.reladdr
|| dst
.reladdr2
) {
686 case PROGRAM_STATE_VAR
:
687 case PROGRAM_CONSTANT
:
688 case PROGRAM_UNIFORM
:
689 this->indirect_addr_consts
= true;
691 case PROGRAM_IMMEDIATE
:
692 assert(!"immediates should not have indirect addressing");
699 for (i
= 0; i
< 4; i
++) {
700 if(inst
->src
[i
].reladdr
) {
701 switch(inst
->src
[i
].file
) {
702 case PROGRAM_STATE_VAR
:
703 case PROGRAM_CONSTANT
:
704 case PROGRAM_UNIFORM
:
705 this->indirect_addr_consts
= true;
707 case PROGRAM_IMMEDIATE
:
708 assert(!"immediates should not have indirect addressing");
718 * This section contains the double processing.
719 * GLSL just represents doubles as single channel values,
720 * however most HW and TGSI represent doubles as pairs of register channels.
722 * so we have to fixup destination writemask/index and src swizzle/indexes.
723 * dest writemasks need to translate from single channel write mask
724 * to a dual-channel writemask, but also need to modify the index,
725 * if we are touching the Z,W fields in the pre-translated writemask.
727 * src channels have similiar index modifications along with swizzle
728 * changes to we pick the XY, ZW pairs from the correct index.
730 * GLSL [0].x -> TGSI [0].xy
731 * GLSL [0].y -> TGSI [0].zw
732 * GLSL [0].z -> TGSI [1].xy
733 * GLSL [0].w -> TGSI [1].zw
735 for (j
= 0; j
< 2; j
++) {
736 dst_is_double
[j
] = false;
737 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
738 dst_is_double
[j
] = true;
739 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
740 unsigned type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
741 if (type
== GLSL_TYPE_DOUBLE
)
742 dst_is_double
[j
] = true;
746 if (dst_is_double
[0] || dst_is_double
[1] ||
747 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
748 glsl_to_tgsi_instruction
*dinst
= NULL
;
749 int initial_src_swz
[4], initial_src_idx
[4];
750 int initial_dst_idx
[2], initial_dst_writemask
[2];
751 /* select the writemask for dst0 or dst1 */
752 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
754 /* copy out the writemask, index and swizzles for all src/dsts. */
755 for (j
= 0; j
< 2; j
++) {
756 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
757 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
760 for (j
= 0; j
< 4; j
++) {
761 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
762 initial_src_idx
[j
] = inst
->src
[j
].index
;
766 * scan all the components in the dst writemask
767 * generate an instruction for each of them if required.
772 int i
= u_bit_scan(&writemask
);
774 /* before emitting the instruction, see if we have to adjust store
776 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
777 addr
.file
== PROGRAM_UNDEFINED
) {
778 /* We have to advance the buffer address by 16 */
779 addr
= get_temp(glsl_type::uint_type
);
780 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
781 inst
->src
[0], st_src_reg_for_int(16));
785 /* first time use previous instruction */
789 /* create a new instructions for subsequent attempts */
790 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
795 this->instructions
.push_tail(dinst
);
797 /* modify the destination if we are splitting */
798 for (j
= 0; j
< 2; j
++) {
799 if (dst_is_double
[j
]) {
800 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
801 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
803 if (dinst
->op
== TGSI_OPCODE_STORE
) {
804 dinst
->src
[0] = addr
;
806 dinst
->dst
[j
].index
++;
810 /* if we aren't writing to a double, just get the bit of the initial writemask
812 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
816 /* modify the src registers */
817 for (j
= 0; j
< 4; j
++) {
818 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
820 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
821 dinst
->src
[j
].index
= initial_src_idx
[j
];
823 dinst
->src
[j
].double_reg2
= true;
824 dinst
->src
[j
].index
++;
828 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
830 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
833 /* some opcodes are special case in what they use as sources
834 - F2D is a float src0, DLDEXP is integer src1 */
835 if (op
== TGSI_OPCODE_F2D
||
836 op
== TGSI_OPCODE_DLDEXP
||
837 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
838 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
845 this->instructions
.push_tail(inst
);
852 glsl_to_tgsi_instruction
*
853 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
855 st_src_reg src0
, st_src_reg src1
,
856 st_src_reg src2
, st_src_reg src3
)
858 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
862 * Determines whether to use an integer, unsigned integer, or float opcode
863 * based on the operands and input opcode, then emits the result.
866 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
868 st_src_reg src0
, st_src_reg src1
)
870 int type
= GLSL_TYPE_FLOAT
;
872 if (op
== TGSI_OPCODE_MOV
)
875 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
876 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
877 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
878 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
880 if (is_resource_instruction(op
))
882 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
883 type
= GLSL_TYPE_DOUBLE
;
884 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
885 type
= GLSL_TYPE_FLOAT
;
886 else if (native_integers
)
887 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
889 #define case5(c, f, i, u, d) \
890 case TGSI_OPCODE_##c: \
891 if (type == GLSL_TYPE_DOUBLE) \
892 op = TGSI_OPCODE_##d; \
893 else if (type == GLSL_TYPE_INT) \
894 op = TGSI_OPCODE_##i; \
895 else if (type == GLSL_TYPE_UINT) \
896 op = TGSI_OPCODE_##u; \
898 op = TGSI_OPCODE_##f; \
901 #define case4(c, f, i, u) \
902 case TGSI_OPCODE_##c: \
903 if (type == GLSL_TYPE_INT) \
904 op = TGSI_OPCODE_##i; \
905 else if (type == GLSL_TYPE_UINT) \
906 op = TGSI_OPCODE_##u; \
908 op = TGSI_OPCODE_##f; \
911 #define case3(f, i, u) case4(f, f, i, u)
912 #define case4d(f, i, u, d) case5(f, f, i, u, d)
913 #define case3fid(f, i, d) case5(f, f, i, i, d)
914 #define case2fi(f, i) case4(f, f, i, i)
915 #define case2iu(i, u) case4(i, LAST, i, u)
917 #define casecomp(c, f, i, u, d) \
918 case TGSI_OPCODE_##c: \
919 if (type == GLSL_TYPE_DOUBLE) \
920 op = TGSI_OPCODE_##d; \
921 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
922 op = TGSI_OPCODE_##i; \
923 else if (type == GLSL_TYPE_UINT) \
924 op = TGSI_OPCODE_##u; \
925 else if (native_integers) \
926 op = TGSI_OPCODE_##f; \
928 op = TGSI_OPCODE_##c; \
932 case3fid(ADD
, UADD
, DADD
);
933 case3fid(MUL
, UMUL
, DMUL
);
934 case3fid(MAD
, UMAD
, DMAD
);
935 case3fid(FMA
, UMAD
, DFMA
);
936 case3(DIV
, IDIV
, UDIV
);
937 case4d(MAX
, IMAX
, UMAX
, DMAX
);
938 case4d(MIN
, IMIN
, UMIN
, DMIN
);
941 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
942 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
943 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
944 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
948 case3fid(SSG
, ISSG
, DSSG
);
949 case3fid(ABS
, IABS
, DABS
);
953 case2iu(IMUL_HI
, UMUL_HI
);
955 case3fid(SQRT
, SQRT
, DSQRT
);
957 case3fid(RCP
, RCP
, DRCP
);
958 case3fid(RSQ
, RSQ
, DRSQ
);
960 case3fid(FRC
, FRC
, DFRAC
);
961 case3fid(TRUNC
, TRUNC
, DTRUNC
);
962 case3fid(CEIL
, CEIL
, DCEIL
);
963 case3fid(FLR
, FLR
, DFLR
);
964 case3fid(ROUND
, ROUND
, DROUND
);
966 case2iu(ATOMIMAX
, ATOMUMAX
);
967 case2iu(ATOMIMIN
, ATOMUMIN
);
972 assert(op
!= TGSI_OPCODE_LAST
);
976 glsl_to_tgsi_instruction
*
977 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
978 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
981 static const unsigned dot_opcodes
[] = {
982 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
985 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
989 * Emits TGSI scalar opcodes to produce unique answers across channels.
991 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
992 * channel determines the result across all channels. So to do a vec4
993 * of this operation, we want to emit a scalar per source channel used
994 * to produce dest channels.
997 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
999 st_src_reg orig_src0
, st_src_reg orig_src1
)
1002 int done_mask
= ~dst
.writemask
;
1004 /* TGSI RCP is a scalar operation splatting results to all channels,
1005 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1008 for (i
= 0; i
< 4; i
++) {
1009 GLuint this_mask
= (1 << i
);
1010 st_src_reg src0
= orig_src0
;
1011 st_src_reg src1
= orig_src1
;
1013 if (done_mask
& this_mask
)
1016 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1017 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1018 for (j
= i
+ 1; j
< 4; j
++) {
1019 /* If there is another enabled component in the destination that is
1020 * derived from the same inputs, generate its value on this pass as
1023 if (!(done_mask
& (1 << j
)) &&
1024 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1025 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1026 this_mask
|= (1 << j
);
1029 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1030 src0_swiz
, src0_swiz
);
1031 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1032 src1_swiz
, src1_swiz
);
1034 dst
.writemask
= this_mask
;
1035 emit_asm(ir
, op
, dst
, src0
, src1
);
1036 done_mask
|= this_mask
;
1041 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1042 st_dst_reg dst
, st_src_reg src0
)
1044 st_src_reg undef
= undef_src
;
1046 undef
.swizzle
= SWIZZLE_XXXX
;
1048 emit_scalar(ir
, op
, dst
, src0
, undef
);
1052 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1053 st_dst_reg dst
, st_src_reg src0
)
1055 int op
= TGSI_OPCODE_ARL
;
1057 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1058 op
= TGSI_OPCODE_UARL
;
1060 assert(dst
.file
== PROGRAM_ADDRESS
);
1061 if (dst
.index
>= this->num_address_regs
)
1062 this->num_address_regs
= dst
.index
+ 1;
1064 emit_asm(NULL
, op
, dst
, src0
);
1068 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1069 gl_constant_value values
[8], int size
, int datatype
,
1070 GLuint
*swizzle_out
)
1072 if (file
== PROGRAM_CONSTANT
) {
1073 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1074 size
, datatype
, swizzle_out
);
1077 assert(file
== PROGRAM_IMMEDIATE
);
1080 immediate_storage
*entry
;
1081 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1084 /* Search immediate storage to see if we already have an identical
1085 * immediate that we can use instead of adding a duplicate entry.
1087 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1088 immediate_storage
*tmp
= entry
;
1090 for (i
= 0; i
* 4 < size32
; i
++) {
1091 int slot_size
= MIN2(size32
- (i
* 4), 4);
1092 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1094 if (memcmp(tmp
->values
, &values
[i
* 4],
1095 slot_size
* sizeof(gl_constant_value
)))
1098 /* Everything matches, keep going until the full size is matched */
1099 tmp
= (immediate_storage
*)tmp
->next
;
1102 /* The full value matched */
1103 if (i
* 4 >= size32
)
1109 for (i
= 0; i
* 4 < size32
; i
++) {
1110 int slot_size
= MIN2(size32
- (i
* 4), 4);
1111 /* Add this immediate to the list. */
1112 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1113 this->immediates
.push_tail(entry
);
1114 this->num_immediates
++;
1120 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1122 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1123 union gl_constant_value uval
;
1126 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1132 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1134 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1135 union gl_constant_value uval
[2];
1137 uval
[0].u
= *(uint32_t *)&val
;
1138 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1139 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1145 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1147 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1148 union gl_constant_value uval
;
1150 assert(native_integers
);
1153 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1159 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1161 if (native_integers
)
1162 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1163 st_src_reg_for_int(val
);
1165 return st_src_reg_for_float(val
);
1169 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1174 switch (type
->base_type
) {
1175 case GLSL_TYPE_UINT
:
1177 case GLSL_TYPE_FLOAT
:
1178 case GLSL_TYPE_BOOL
:
1179 if (type
->is_matrix()) {
1180 return type
->matrix_columns
;
1182 /* Regardless of size of vector, it gets a vec4. This is bad
1183 * packing for things like floats, but otherwise arrays become a
1184 * mess. Hopefully a later pass over the code can pack scalars
1185 * down if appropriate.
1190 case GLSL_TYPE_DOUBLE
:
1191 if (type
->is_matrix()) {
1192 if (type
->vector_elements
<= 2 || is_vs_input
)
1193 return type
->matrix_columns
;
1195 return type
->matrix_columns
* 2;
1197 /* For doubles if we have a double or dvec2 they fit in one
1198 * vec4, else they need 2 vec4s.
1200 if (type
->vector_elements
<= 2 || is_vs_input
)
1206 case GLSL_TYPE_ARRAY
:
1207 assert(type
->length
> 0);
1208 return attrib_type_size(type
->fields
.array
, is_vs_input
) * type
->length
;
1209 case GLSL_TYPE_STRUCT
:
1211 for (i
= 0; i
< type
->length
; i
++) {
1212 size
+= attrib_type_size(type
->fields
.structure
[i
].type
, is_vs_input
);
1215 case GLSL_TYPE_SAMPLER
:
1216 case GLSL_TYPE_IMAGE
:
1217 case GLSL_TYPE_SUBROUTINE
:
1218 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1222 case GLSL_TYPE_ATOMIC_UINT
:
1223 case GLSL_TYPE_INTERFACE
:
1224 case GLSL_TYPE_VOID
:
1225 case GLSL_TYPE_ERROR
:
1226 case GLSL_TYPE_FUNCTION
:
1227 assert(!"Invalid type in type_size");
1234 type_size(const struct glsl_type
*type
)
1236 return attrib_type_size(type
, false);
1240 * If the given GLSL type is an array or matrix or a structure containing
1241 * an array/matrix member, return true. Else return false.
1243 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1244 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1245 * we have an array that might be indexed with a variable, we need to use
1246 * the later storage type.
1249 type_has_array_or_matrix(const glsl_type
*type
)
1251 if (type
->is_array() || type
->is_matrix())
1254 if (type
->is_record()) {
1255 for (unsigned i
= 0; i
< type
->length
; i
++) {
1256 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1267 * In the initial pass of codegen, we assign temporary numbers to
1268 * intermediate results. (not SSA -- variable assignments will reuse
1272 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1276 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1280 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1281 if (next_array
>= max_num_arrays
) {
1282 max_num_arrays
+= 32;
1283 array_sizes
= (unsigned*)
1284 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1287 src
.file
= PROGRAM_ARRAY
;
1288 src
.index
= next_array
<< 16 | 0x8000;
1289 array_sizes
[next_array
] = type_size(type
);
1293 src
.file
= PROGRAM_TEMPORARY
;
1294 src
.index
= next_temp
;
1295 next_temp
+= type_size(type
);
1298 if (type
->is_array() || type
->is_record()) {
1299 src
.swizzle
= SWIZZLE_NOOP
;
1301 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1308 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1311 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1312 if (entry
->var
== var
)
1320 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1322 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1323 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1325 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1326 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1329 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1331 const ir_state_slot
*const slots
= ir
->get_state_slots();
1332 assert(slots
!= NULL
);
1334 /* Check if this statevar's setup in the STATE file exactly
1335 * matches how we'll want to reference it as a
1336 * struct/array/whatever. If not, then we need to move it into
1337 * temporary storage and hope that it'll get copy-propagated
1340 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1341 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1346 variable_storage
*storage
;
1348 if (i
== ir
->get_num_state_slots()) {
1349 /* We'll set the index later. */
1350 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1351 this->variables
.push_tail(storage
);
1355 /* The variable_storage constructor allocates slots based on the size
1356 * of the type. However, this had better match the number of state
1357 * elements that we're going to copy into the new temporary.
1359 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1361 dst
= st_dst_reg(get_temp(ir
->type
));
1363 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1365 this->variables
.push_tail(storage
);
1369 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1370 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1371 (gl_state_index
*)slots
[i
].tokens
);
1373 if (storage
->file
== PROGRAM_STATE_VAR
) {
1374 if (storage
->index
== -1) {
1375 storage
->index
= index
;
1377 assert(index
== storage
->index
+ (int)i
);
1380 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1381 * the data being moved since MOV does not care about the type of
1382 * data it is moving, and we don't want to declare registers with
1383 * array or struct types.
1385 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1386 src
.swizzle
= slots
[i
].swizzle
;
1387 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1388 /* even a float takes up a whole vec4 reg in a struct/array. */
1393 if (storage
->file
== PROGRAM_TEMPORARY
&&
1394 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1395 fail_link(this->shader_program
,
1396 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1397 ir
->name
, dst
.index
- storage
->index
,
1398 type_size(ir
->type
));
1404 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1406 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1408 visit_exec_list(&ir
->body_instructions
, this);
1410 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1414 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1417 case ir_loop_jump::jump_break
:
1418 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1420 case ir_loop_jump::jump_continue
:
1421 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1428 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1435 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1437 /* Ignore function bodies other than main() -- we shouldn't see calls to
1438 * them since they should all be inlined before we get to glsl_to_tgsi.
1440 if (strcmp(ir
->name
, "main") == 0) {
1441 const ir_function_signature
*sig
;
1444 sig
= ir
->matching_signature(NULL
, &empty
, false);
1448 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1455 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1457 int nonmul_operand
= 1 - mul_operand
;
1459 st_dst_reg result_dst
;
1461 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1462 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1465 expr
->operands
[0]->accept(this);
1467 expr
->operands
[1]->accept(this);
1469 ir
->operands
[nonmul_operand
]->accept(this);
1472 this->result
= get_temp(ir
->type
);
1473 result_dst
= st_dst_reg(this->result
);
1474 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1475 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1481 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1483 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1484 * implemented using multiplication, and logical-or is implemented using
1485 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1486 * As result, the logical expression (a & !b) can be rewritten as:
1490 * - (a * 1) - (a * b)
1494 * This final expression can be implemented as a single MAD(a, -b, a)
1498 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1500 const int other_operand
= 1 - try_operand
;
1503 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1504 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1507 ir
->operands
[other_operand
]->accept(this);
1509 expr
->operands
[0]->accept(this);
1512 b
.negate
= ~b
.negate
;
1514 this->result
= get_temp(ir
->type
);
1515 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1521 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1522 st_src_reg
*reg
, int *num_reladdr
)
1524 if (!reg
->reladdr
&& !reg
->reladdr2
)
1527 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1528 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1530 if (*num_reladdr
!= 1) {
1531 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1533 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1541 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1543 unsigned int operand
;
1544 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1545 st_src_reg result_src
;
1546 st_dst_reg result_dst
;
1548 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1550 if (ir
->operation
== ir_binop_add
) {
1551 if (try_emit_mad(ir
, 1))
1553 if (try_emit_mad(ir
, 0))
1557 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1559 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1560 if (try_emit_mad_for_and_not(ir
, 1))
1562 if (try_emit_mad_for_and_not(ir
, 0))
1566 if (ir
->operation
== ir_quadop_vector
)
1567 assert(!"ir_quadop_vector should have been lowered");
1569 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1570 this->result
.file
= PROGRAM_UNDEFINED
;
1571 ir
->operands
[operand
]->accept(this);
1572 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1573 printf("Failed to get tree for expression operand:\n");
1574 ir
->operands
[operand
]->print();
1578 op
[operand
] = this->result
;
1580 /* Matrix expression operands should have been broken down to vector
1581 * operations already.
1583 assert(!ir
->operands
[operand
]->type
->is_matrix());
1586 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1587 if (ir
->operands
[1]) {
1588 vector_elements
= MAX2(vector_elements
,
1589 ir
->operands
[1]->type
->vector_elements
);
1592 this->result
.file
= PROGRAM_UNDEFINED
;
1594 /* Storage for our result. Ideally for an assignment we'd be using
1595 * the actual storage for the result here, instead.
1597 result_src
= get_temp(ir
->type
);
1598 /* convenience for the emit functions below. */
1599 result_dst
= st_dst_reg(result_src
);
1600 /* Limit writes to the channels that will be used by result_src later.
1601 * This does limit this temp's use as a temporary for multi-instruction
1604 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1606 switch (ir
->operation
) {
1607 case ir_unop_logic_not
:
1608 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1609 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1611 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1612 * older GPUs implement SEQ using multiple instructions (i915 uses two
1613 * SGE instructions and a MUL instruction). Since our logic values are
1614 * 0.0 and 1.0, 1-x also implements !x.
1616 op
[0].negate
= ~op
[0].negate
;
1617 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1621 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1622 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1623 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1624 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1626 op
[0].negate
= ~op
[0].negate
;
1630 case ir_unop_subroutine_to_int
:
1631 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1634 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1637 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1640 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1644 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1648 assert(!"not reached: should be handled by ir_explog_to_explog2");
1651 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1654 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1657 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1659 case ir_unop_saturate
: {
1660 glsl_to_tgsi_instruction
*inst
;
1661 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1662 inst
->saturate
= true;
1667 case ir_unop_dFdx_coarse
:
1668 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1670 case ir_unop_dFdx_fine
:
1671 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1674 case ir_unop_dFdy_coarse
:
1675 case ir_unop_dFdy_fine
:
1677 /* The X component contains 1 or -1 depending on whether the framebuffer
1678 * is a FBO or the window system buffer, respectively.
1679 * It is then multiplied with the source operand of DDY.
1681 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1682 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1684 unsigned transform_y_index
=
1685 _mesa_add_state_reference(this->prog
->Parameters
,
1688 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1690 glsl_type::vec4_type
);
1691 transform_y
.swizzle
= SWIZZLE_XXXX
;
1693 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1695 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1696 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1697 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1701 case ir_unop_frexp_sig
:
1702 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1705 case ir_unop_frexp_exp
:
1706 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1709 case ir_unop_noise
: {
1710 /* At some point, a motivated person could add a better
1711 * implementation of noise. Currently not even the nvidia
1712 * binary drivers do anything more than this. In any case, the
1713 * place to do this is in the GL state tracker, not the poor
1716 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1721 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1724 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1728 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1731 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1732 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1734 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1737 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1738 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1740 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1744 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1746 case ir_binop_greater
:
1747 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1749 case ir_binop_lequal
:
1750 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1752 case ir_binop_gequal
:
1753 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1755 case ir_binop_equal
:
1756 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1758 case ir_binop_nequal
:
1759 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_all_equal
:
1762 /* "==" operator producing a scalar boolean. */
1763 if (ir
->operands
[0]->type
->is_vector() ||
1764 ir
->operands
[1]->type
->is_vector()) {
1765 st_src_reg temp
= get_temp(native_integers
?
1766 glsl_type::uvec4_type
:
1767 glsl_type::vec4_type
);
1769 if (native_integers
) {
1770 st_dst_reg temp_dst
= st_dst_reg(temp
);
1771 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1773 if (ir
->operands
[0]->type
->is_boolean() &&
1774 ir
->operands
[1]->as_constant() &&
1775 ir
->operands
[1]->as_constant()->is_one()) {
1776 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1778 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1781 /* Emit 1-3 AND operations to combine the SEQ results. */
1782 switch (ir
->operands
[0]->type
->vector_elements
) {
1786 temp_dst
.writemask
= WRITEMASK_Y
;
1787 temp1
.swizzle
= SWIZZLE_YYYY
;
1788 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1789 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1792 temp_dst
.writemask
= WRITEMASK_X
;
1793 temp1
.swizzle
= SWIZZLE_XXXX
;
1794 temp2
.swizzle
= SWIZZLE_YYYY
;
1795 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1796 temp_dst
.writemask
= WRITEMASK_Y
;
1797 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1798 temp2
.swizzle
= SWIZZLE_WWWW
;
1799 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1802 temp1
.swizzle
= SWIZZLE_XXXX
;
1803 temp2
.swizzle
= SWIZZLE_YYYY
;
1804 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1806 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1808 /* After the dot-product, the value will be an integer on the
1809 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1811 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1813 /* Negating the result of the dot-product gives values on the range
1814 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1815 * This is achieved using SGE.
1817 st_src_reg sge_src
= result_src
;
1818 sge_src
.negate
= ~sge_src
.negate
;
1819 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1822 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1825 case ir_binop_any_nequal
:
1826 /* "!=" operator producing a scalar boolean. */
1827 if (ir
->operands
[0]->type
->is_vector() ||
1828 ir
->operands
[1]->type
->is_vector()) {
1829 st_src_reg temp
= get_temp(native_integers
?
1830 glsl_type::uvec4_type
:
1831 glsl_type::vec4_type
);
1832 if (ir
->operands
[0]->type
->is_boolean() &&
1833 ir
->operands
[1]->as_constant() &&
1834 ir
->operands
[1]->as_constant()->is_zero()) {
1835 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1837 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1840 if (native_integers
) {
1841 st_dst_reg temp_dst
= st_dst_reg(temp
);
1842 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1844 /* Emit 1-3 OR operations to combine the SNE results. */
1845 switch (ir
->operands
[0]->type
->vector_elements
) {
1849 temp_dst
.writemask
= WRITEMASK_Y
;
1850 temp1
.swizzle
= SWIZZLE_YYYY
;
1851 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1852 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1855 temp_dst
.writemask
= WRITEMASK_X
;
1856 temp1
.swizzle
= SWIZZLE_XXXX
;
1857 temp2
.swizzle
= SWIZZLE_YYYY
;
1858 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1859 temp_dst
.writemask
= WRITEMASK_Y
;
1860 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1861 temp2
.swizzle
= SWIZZLE_WWWW
;
1862 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1865 temp1
.swizzle
= SWIZZLE_XXXX
;
1866 temp2
.swizzle
= SWIZZLE_YYYY
;
1867 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1869 /* After the dot-product, the value will be an integer on the
1870 * range [0,4]. Zero stays zero, and positive values become 1.0.
1872 glsl_to_tgsi_instruction
*const dp
=
1873 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1874 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1875 /* The clamping to [0,1] can be done for free in the fragment
1876 * shader with a saturate.
1878 dp
->saturate
= true;
1880 /* Negating the result of the dot-product gives values on the range
1881 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1882 * achieved using SLT.
1884 st_src_reg slt_src
= result_src
;
1885 slt_src
.negate
= ~slt_src
.negate
;
1886 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1890 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1894 case ir_binop_logic_xor
:
1895 if (native_integers
)
1896 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1898 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1901 case ir_binop_logic_or
: {
1902 if (native_integers
) {
1903 /* If integers are used as booleans, we can use an actual "or"
1906 assert(native_integers
);
1907 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1909 /* After the addition, the value will be an integer on the
1910 * range [0,2]. Zero stays zero, and positive values become 1.0.
1912 glsl_to_tgsi_instruction
*add
=
1913 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1914 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1915 /* The clamping to [0,1] can be done for free in the fragment
1916 * shader with a saturate if floats are being used as boolean values.
1918 add
->saturate
= true;
1920 /* Negating the result of the addition gives values on the range
1921 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1922 * is achieved using SLT.
1924 st_src_reg slt_src
= result_src
;
1925 slt_src
.negate
= ~slt_src
.negate
;
1926 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1932 case ir_binop_logic_and
:
1933 /* If native integers are disabled, the bool args are stored as float 0.0
1934 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1935 * actual AND opcode.
1937 if (native_integers
)
1938 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1940 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1944 assert(ir
->operands
[0]->type
->is_vector());
1945 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1946 emit_dp(ir
, result_dst
, op
[0], op
[1],
1947 ir
->operands
[0]->type
->vector_elements
);
1952 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1954 /* sqrt(x) = x * rsq(x). */
1955 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1956 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1957 /* For incoming channels <= 0, set the result to 0. */
1958 op
[0].negate
= ~op
[0].negate
;
1959 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1960 op
[0], result_src
, st_src_reg_for_float(0.0));
1964 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1967 if (native_integers
) {
1968 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1971 /* fallthrough to next case otherwise */
1973 if (native_integers
) {
1974 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1977 /* fallthrough to next case otherwise */
1980 /* Converting between signed and unsigned integers is a no-op. */
1982 result_src
.type
= result_dst
.type
;
1985 if (native_integers
) {
1986 /* Booleans are stored as integers using ~0 for true and 0 for false.
1987 * GLSL requires that int(bool) return 1 for true and 0 for false.
1988 * This conversion is done with AND, but it could be done with NEG.
1990 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1992 /* Booleans and integers are both stored as floats when native
1993 * integers are disabled.
1999 if (native_integers
)
2000 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2002 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2005 if (native_integers
)
2006 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2008 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2010 case ir_unop_bitcast_f2i
:
2012 result_src
.type
= GLSL_TYPE_INT
;
2014 case ir_unop_bitcast_f2u
:
2016 result_src
.type
= GLSL_TYPE_UINT
;
2018 case ir_unop_bitcast_i2f
:
2019 case ir_unop_bitcast_u2f
:
2021 result_src
.type
= GLSL_TYPE_FLOAT
;
2024 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2027 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2030 if (native_integers
)
2031 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2033 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2036 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2039 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2042 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2044 case ir_unop_round_even
:
2045 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2048 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2052 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2055 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2058 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2061 case ir_unop_bit_not
:
2062 if (native_integers
) {
2063 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2067 if (native_integers
) {
2068 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2071 case ir_binop_lshift
:
2072 if (native_integers
) {
2073 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2076 case ir_binop_rshift
:
2077 if (native_integers
) {
2078 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2081 case ir_binop_bit_and
:
2082 if (native_integers
) {
2083 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2086 case ir_binop_bit_xor
:
2087 if (native_integers
) {
2088 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2091 case ir_binop_bit_or
:
2092 if (native_integers
) {
2093 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2097 assert(!"GLSL 1.30 features unsupported");
2100 case ir_binop_ubo_load
: {
2101 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2102 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2103 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2104 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2105 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2108 cbuf
.type
= ir
->type
->base_type
;
2109 cbuf
.file
= PROGRAM_CONSTANT
;
2111 cbuf
.reladdr
= NULL
;
2114 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2116 if (const_offset_ir
) {
2117 /* Constant index into constant buffer */
2118 cbuf
.reladdr
= NULL
;
2119 cbuf
.index
= const_offset
/ 16;
2122 /* Relative/variable index into constant buffer */
2123 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2124 st_src_reg_for_int(4));
2125 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2126 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2129 if (const_uniform_block
) {
2130 /* Constant constant buffer */
2131 cbuf
.reladdr2
= NULL
;
2132 cbuf
.index2D
= const_block
;
2133 cbuf
.has_index2
= true;
2136 /* Relative/variable constant buffer */
2137 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2139 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2140 cbuf
.has_index2
= true;
2143 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2144 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2145 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2146 const_offset
% 16 / 8,
2147 const_offset
% 16 / 8,
2148 const_offset
% 16 / 8);
2150 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2151 const_offset
% 16 / 4,
2152 const_offset
% 16 / 4,
2153 const_offset
% 16 / 4);
2155 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2156 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2158 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2163 /* note: we have to reorder the three args here */
2164 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2167 if (this->ctx
->Const
.NativeIntegers
)
2168 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2170 op
[0].negate
= ~op
[0].negate
;
2171 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2174 case ir_triop_bitfield_extract
:
2175 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2177 case ir_quadop_bitfield_insert
:
2178 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2180 case ir_unop_bitfield_reverse
:
2181 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2183 case ir_unop_bit_count
:
2184 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2186 case ir_unop_find_msb
:
2187 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2189 case ir_unop_find_lsb
:
2190 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2192 case ir_binop_imul_high
:
2193 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2196 /* In theory, MAD is incorrect here. */
2198 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2200 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2202 case ir_unop_interpolate_at_centroid
:
2203 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2205 case ir_binop_interpolate_at_offset
:
2206 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2208 case ir_binop_interpolate_at_sample
:
2209 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2213 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2216 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2219 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2222 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2225 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2228 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2230 case ir_unop_unpack_double_2x32
:
2231 case ir_unop_pack_double_2x32
:
2232 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2235 case ir_binop_ldexp
:
2236 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2237 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2239 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2243 case ir_unop_pack_half_2x16
:
2244 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2246 case ir_unop_unpack_half_2x16
:
2247 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2250 case ir_unop_get_buffer_size
: {
2251 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2254 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2255 (const_offset
? const_offset
->value
.u
[0] : 0),
2257 if (!const_offset
) {
2258 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2259 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
2260 emit_arl(ir
, sampler_reladdr
, op
[0]);
2262 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2266 case ir_unop_pack_snorm_2x16
:
2267 case ir_unop_pack_unorm_2x16
:
2268 case ir_unop_pack_snorm_4x8
:
2269 case ir_unop_pack_unorm_4x8
:
2271 case ir_unop_unpack_snorm_2x16
:
2272 case ir_unop_unpack_unorm_2x16
:
2273 case ir_unop_unpack_snorm_4x8
:
2274 case ir_unop_unpack_unorm_4x8
:
2276 case ir_quadop_vector
:
2277 case ir_binop_vector_extract
:
2278 case ir_triop_vector_insert
:
2279 case ir_binop_carry
:
2280 case ir_binop_borrow
:
2281 case ir_unop_ssbo_unsized_array_length
:
2282 /* This operation is not supported, or should have already been handled.
2284 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2288 this->result
= result_src
;
2293 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2299 /* Note that this is only swizzles in expressions, not those on the left
2300 * hand side of an assignment, which do write masking. See ir_assignment
2304 ir
->val
->accept(this);
2306 assert(src
.file
!= PROGRAM_UNDEFINED
);
2307 assert(ir
->type
->vector_elements
> 0);
2309 for (i
= 0; i
< 4; i
++) {
2310 if (i
< ir
->type
->vector_elements
) {
2313 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2316 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2319 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2322 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2326 /* If the type is smaller than a vec4, replicate the last
2329 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2333 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2338 /* Test if the variable is an array. Note that geometry and
2339 * tessellation shader inputs are outputs are always arrays (except
2340 * for patch inputs), so only the array element type is considered.
2343 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2345 const glsl_type
*type
= var
->type
;
2347 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2348 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2353 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2354 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2355 stage
== MESA_SHADER_TESS_CTRL
) &&
2357 if (!var
->type
->is_array())
2358 return false; /* a system value probably */
2360 type
= var
->type
->fields
.array
;
2364 return type
->is_array() || type
->is_matrix();
2368 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2370 variable_storage
*entry
= find_variable_storage(ir
->var
);
2371 ir_variable
*var
= ir
->var
;
2375 switch (var
->data
.mode
) {
2376 case ir_var_uniform
:
2377 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2378 var
->data
.param_index
);
2379 this->variables
.push_tail(entry
);
2381 case ir_var_shader_in
:
2382 /* The linker assigns locations for varyings and attributes,
2383 * including deprecated builtins (like gl_Color), user-assign
2384 * generic attributes (glBindVertexLocation), and
2385 * user-defined varyings.
2387 assert(var
->data
.location
!= -1);
2389 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2390 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2392 decl
->mesa_index
= var
->data
.location
;
2393 decl
->array_id
= num_input_arrays
+ 1;
2395 decl
->array_size
= type_size(var
->type
->fields
.array
);
2396 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2398 decl
->array_size
= type_size(var
->type
);
2399 decl
->array_type
= var
->type
->without_array()->base_type
;
2403 entry
= new(mem_ctx
) variable_storage(var
,
2409 entry
= new(mem_ctx
) variable_storage(var
,
2411 var
->data
.location
);
2413 this->variables
.push_tail(entry
);
2415 case ir_var_shader_out
:
2416 assert(var
->data
.location
!= -1);
2418 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2419 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2421 decl
->mesa_index
= var
->data
.location
;
2422 decl
->array_id
= num_output_arrays
+ 1;
2424 decl
->array_size
= type_size(var
->type
->fields
.array
);
2425 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2427 decl
->array_size
= type_size(var
->type
);
2428 decl
->array_type
= var
->type
->without_array()->base_type
;
2430 num_output_arrays
++;
2432 entry
= new(mem_ctx
) variable_storage(var
,
2438 entry
= new(mem_ctx
) variable_storage(var
,
2443 this->variables
.push_tail(entry
);
2445 case ir_var_system_value
:
2446 entry
= new(mem_ctx
) variable_storage(var
,
2447 PROGRAM_SYSTEM_VALUE
,
2448 var
->data
.location
);
2451 case ir_var_temporary
:
2452 st_src_reg src
= get_temp(var
->type
);
2454 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2455 this->variables
.push_tail(entry
);
2461 printf("Failed to make storage for %s\n", var
->name
);
2466 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2467 this->result
.array_id
= entry
->array_id
;
2468 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2469 this->result
.is_double_vertex_input
= true;
2470 if (!native_integers
)
2471 this->result
.type
= GLSL_TYPE_FLOAT
;
2475 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2476 GLbitfield64 usage_mask
,
2477 GLbitfield64 double_usage_mask
,
2478 GLbitfield patch_usage_mask
)
2482 /* Fix array declarations by removing unused array elements at both ends
2483 * of the arrays. For example, mat4[3] where only mat[1] is used.
2485 for (i
= 0; i
< count
; i
++) {
2486 struct array_decl
*decl
= &arrays
[i
];
2488 /* Shrink the beginning. */
2489 for (j
= 0; j
< decl
->array_size
; j
++) {
2490 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2491 if (patch_usage_mask
&
2492 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2496 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2498 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2507 /* Shrink the end. */
2508 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2509 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2510 if (patch_usage_mask
&
2511 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2515 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2517 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2527 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2531 int element_size
= type_size(ir
->type
);
2534 index
= ir
->array_index
->constant_expression_value();
2536 ir
->array
->accept(this);
2539 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2540 switch (this->prog
->Target
) {
2541 case GL_TESS_CONTROL_PROGRAM_NV
:
2542 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2543 !ir
->variable_referenced()->data
.patch
;
2545 case GL_TESS_EVALUATION_PROGRAM_NV
:
2546 is_2D
= src
.file
== PROGRAM_INPUT
&&
2547 !ir
->variable_referenced()->data
.patch
;
2549 case GL_GEOMETRY_PROGRAM_NV
:
2550 is_2D
= src
.file
== PROGRAM_INPUT
;
2560 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2561 src
.file
== PROGRAM_INPUT
)
2562 element_size
= attrib_type_size(ir
->type
, true);
2564 src
.index2D
= index
->value
.i
[0];
2565 src
.has_index2
= true;
2567 src
.index
+= index
->value
.i
[0] * element_size
;
2569 /* Variable index array dereference. It eats the "vec4" of the
2570 * base of the array and an index that offsets the TGSI register
2573 ir
->array_index
->accept(this);
2575 st_src_reg index_reg
;
2577 if (element_size
== 1) {
2578 index_reg
= this->result
;
2580 index_reg
= get_temp(native_integers
?
2581 glsl_type::int_type
: glsl_type::float_type
);
2583 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2584 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2587 /* If there was already a relative address register involved, add the
2588 * new and the old together to get the new offset.
2590 if (!is_2D
&& src
.reladdr
!= NULL
) {
2591 st_src_reg accum_reg
= get_temp(native_integers
?
2592 glsl_type::int_type
: glsl_type::float_type
);
2594 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2595 index_reg
, *src
.reladdr
);
2597 index_reg
= accum_reg
;
2601 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2602 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2604 src
.has_index2
= true;
2606 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2607 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2611 /* If the type is smaller than a vec4, replicate the last channel out. */
2612 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2613 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2615 src
.swizzle
= SWIZZLE_NOOP
;
2617 /* Change the register type to the element type of the array. */
2618 src
.type
= ir
->type
->base_type
;
2624 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2627 const glsl_type
*struct_type
= ir
->record
->type
;
2630 ir
->record
->accept(this);
2632 for (i
= 0; i
< struct_type
->length
; i
++) {
2633 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2635 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2638 /* If the type is smaller than a vec4, replicate the last channel out. */
2639 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2640 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2642 this->result
.swizzle
= SWIZZLE_NOOP
;
2644 this->result
.index
+= offset
;
2645 this->result
.type
= ir
->type
->base_type
;
2649 * We want to be careful in assignment setup to hit the actual storage
2650 * instead of potentially using a temporary like we might with the
2651 * ir_dereference handler.
2654 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2656 /* The LHS must be a dereference. If the LHS is a variable indexed array
2657 * access of a vector, it must be separated into a series conditional moves
2658 * before reaching this point (see ir_vec_index_to_cond_assign).
2660 assert(ir
->as_dereference());
2661 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2663 assert(!deref_array
->array
->type
->is_vector());
2666 /* Use the rvalue deref handler for the most part. We'll ignore
2667 * swizzles in it and write swizzles using writemask, though.
2670 return st_dst_reg(v
->result
);
2674 * Process the condition of a conditional assignment
2676 * Examines the condition of a conditional assignment to generate the optimal
2677 * first operand of a \c CMP instruction. If the condition is a relational
2678 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2679 * used as the source for the \c CMP instruction. Otherwise the comparison
2680 * is processed to a boolean result, and the boolean result is used as the
2681 * operand to the CMP instruction.
2684 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2686 ir_rvalue
*src_ir
= ir
;
2688 bool switch_order
= false;
2690 ir_expression
*const expr
= ir
->as_expression();
2692 if (native_integers
) {
2693 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2694 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2695 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2696 type
== GLSL_TYPE_BOOL
) {
2697 if (expr
->operation
== ir_binop_equal
) {
2698 if (expr
->operands
[0]->is_zero()) {
2699 src_ir
= expr
->operands
[1];
2700 switch_order
= true;
2702 else if (expr
->operands
[1]->is_zero()) {
2703 src_ir
= expr
->operands
[0];
2704 switch_order
= true;
2707 else if (expr
->operation
== ir_binop_nequal
) {
2708 if (expr
->operands
[0]->is_zero()) {
2709 src_ir
= expr
->operands
[1];
2711 else if (expr
->operands
[1]->is_zero()) {
2712 src_ir
= expr
->operands
[0];
2718 src_ir
->accept(this);
2719 return switch_order
;
2722 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2723 bool zero_on_left
= false;
2725 if (expr
->operands
[0]->is_zero()) {
2726 src_ir
= expr
->operands
[1];
2727 zero_on_left
= true;
2728 } else if (expr
->operands
[1]->is_zero()) {
2729 src_ir
= expr
->operands
[0];
2730 zero_on_left
= false;
2734 * (a < 0) T F F ( a < 0) T F F
2735 * (0 < a) F F T (-a < 0) F F T
2736 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2737 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2738 * (a > 0) F F T (-a < 0) F F T
2739 * (0 > a) T F F ( a < 0) T F F
2740 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2741 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2743 * Note that exchanging the order of 0 and 'a' in the comparison simply
2744 * means that the value of 'a' should be negated.
2747 switch (expr
->operation
) {
2749 switch_order
= false;
2750 negate
= zero_on_left
;
2753 case ir_binop_greater
:
2754 switch_order
= false;
2755 negate
= !zero_on_left
;
2758 case ir_binop_lequal
:
2759 switch_order
= true;
2760 negate
= !zero_on_left
;
2763 case ir_binop_gequal
:
2764 switch_order
= true;
2765 negate
= zero_on_left
;
2769 /* This isn't the right kind of comparison afterall, so make sure
2770 * the whole condition is visited.
2778 src_ir
->accept(this);
2780 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2781 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2782 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2783 * computing the condition.
2786 this->result
.negate
= ~this->result
.negate
;
2788 return switch_order
;
2792 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2793 st_dst_reg
*l
, st_src_reg
*r
,
2794 st_src_reg
*cond
, bool cond_swap
)
2796 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2797 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2798 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2804 if (type
->is_array()) {
2805 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2806 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2811 if (type
->is_matrix()) {
2812 const struct glsl_type
*vec_type
;
2814 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2815 type
->vector_elements
, 1);
2817 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2818 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2823 assert(type
->is_scalar() || type
->is_vector());
2825 r
->type
= type
->base_type
;
2827 st_src_reg l_src
= st_src_reg(*l
);
2828 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2830 if (native_integers
) {
2831 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2832 cond_swap
? l_src
: *r
,
2833 cond_swap
? *r
: l_src
);
2835 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2836 cond_swap
? l_src
: *r
,
2837 cond_swap
? *r
: l_src
);
2840 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2844 if (type
->is_dual_slot_double()) {
2846 if (r
->is_double_vertex_input
== false)
2852 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2857 ir
->rhs
->accept(this);
2860 l
= get_assignment_lhs(ir
->lhs
, this);
2862 /* FINISHME: This should really set to the correct maximal writemask for each
2863 * FINISHME: component written (in the loops below). This case can only
2864 * FINISHME: occur for matrices, arrays, and structures.
2866 if (ir
->write_mask
== 0) {
2867 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2869 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2870 if (ir
->lhs
->type
->without_array()->is_double()) {
2871 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2873 l
.writemask
= WRITEMASK_X
;
2876 l
.writemask
= WRITEMASK_XY
;
2879 l
.writemask
= WRITEMASK_XYZ
;
2882 l
.writemask
= WRITEMASK_XYZW
;
2886 l
.writemask
= WRITEMASK_XYZW
;
2888 } else if (ir
->lhs
->type
->is_scalar() &&
2889 !ir
->lhs
->type
->is_double() &&
2890 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2891 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2892 * FINISHME: W component of fragment shader output zero, work correctly.
2894 l
.writemask
= WRITEMASK_XYZW
;
2897 int first_enabled_chan
= 0;
2900 l
.writemask
= ir
->write_mask
;
2902 for (int i
= 0; i
< 4; i
++) {
2903 if (l
.writemask
& (1 << i
)) {
2904 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2909 /* Swizzle a small RHS vector into the channels being written.
2911 * glsl ir treats write_mask as dictating how many channels are
2912 * present on the RHS while TGSI treats write_mask as just
2913 * showing which channels of the vec4 RHS get written.
2915 for (int i
= 0; i
< 4; i
++) {
2916 if (l
.writemask
& (1 << i
))
2917 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2919 swizzles
[i
] = first_enabled_chan
;
2921 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2922 swizzles
[2], swizzles
[3]);
2925 assert(l
.file
!= PROGRAM_UNDEFINED
);
2926 assert(r
.file
!= PROGRAM_UNDEFINED
);
2928 if (ir
->condition
) {
2929 const bool switch_order
= this->process_move_condition(ir
->condition
);
2930 st_src_reg condition
= this->result
;
2932 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2933 } else if (ir
->rhs
->as_expression() &&
2934 this->instructions
.get_tail() &&
2935 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2936 type_size(ir
->lhs
->type
) == 1 &&
2937 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2938 /* To avoid emitting an extra MOV when assigning an expression to a
2939 * variable, emit the last instruction of the expression again, but
2940 * replace the destination register with the target of the assignment.
2941 * Dead code elimination will remove the original instruction.
2943 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2944 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2945 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2946 new_inst
->saturate
= inst
->saturate
;
2947 inst
->dead_mask
= inst
->dst
[0].writemask
;
2949 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2955 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2958 GLdouble stack_vals
[4] = { 0 };
2959 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2960 GLenum gl_type
= GL_NONE
;
2962 static int in_array
= 0;
2963 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2965 /* Unfortunately, 4 floats is all we can get into
2966 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2967 * aggregate constant and move each constant value into it. If we
2968 * get lucky, copy propagation will eliminate the extra moves.
2970 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2971 st_src_reg temp_base
= get_temp(ir
->type
);
2972 st_dst_reg temp
= st_dst_reg(temp_base
);
2974 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2975 int size
= type_size(field_value
->type
);
2979 field_value
->accept(this);
2982 for (i
= 0; i
< (unsigned int)size
; i
++) {
2983 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2989 this->result
= temp_base
;
2993 if (ir
->type
->is_array()) {
2994 st_src_reg temp_base
= get_temp(ir
->type
);
2995 st_dst_reg temp
= st_dst_reg(temp_base
);
2996 int size
= type_size(ir
->type
->fields
.array
);
3001 for (i
= 0; i
< ir
->type
->length
; i
++) {
3002 ir
->array_elements
[i
]->accept(this);
3004 for (int j
= 0; j
< size
; j
++) {
3005 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3011 this->result
= temp_base
;
3016 if (ir
->type
->is_matrix()) {
3017 st_src_reg mat
= get_temp(ir
->type
);
3018 st_dst_reg mat_column
= st_dst_reg(mat
);
3020 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3021 switch (ir
->type
->base_type
) {
3022 case GLSL_TYPE_FLOAT
:
3023 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3025 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3026 src
.index
= add_constant(file
,
3028 ir
->type
->vector_elements
,
3031 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3033 case GLSL_TYPE_DOUBLE
:
3034 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3035 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3036 src
.index
= add_constant(file
,
3038 ir
->type
->vector_elements
,
3041 if (ir
->type
->vector_elements
>= 2) {
3042 mat_column
.writemask
= WRITEMASK_XY
;
3043 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3044 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3046 mat_column
.writemask
= WRITEMASK_X
;
3047 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3048 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3051 if (ir
->type
->vector_elements
> 2) {
3052 if (ir
->type
->vector_elements
== 4) {
3053 mat_column
.writemask
= WRITEMASK_ZW
;
3054 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3055 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3057 mat_column
.writemask
= WRITEMASK_Z
;
3058 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3059 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3060 mat_column
.writemask
= WRITEMASK_XYZW
;
3061 src
.swizzle
= SWIZZLE_XYZW
;
3067 unreachable("Illegal matrix constant type.\n");
3076 switch (ir
->type
->base_type
) {
3077 case GLSL_TYPE_FLOAT
:
3079 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3080 values
[i
].f
= ir
->value
.f
[i
];
3083 case GLSL_TYPE_DOUBLE
:
3084 gl_type
= GL_DOUBLE
;
3085 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3086 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3087 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3090 case GLSL_TYPE_UINT
:
3091 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3092 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3093 if (native_integers
)
3094 values
[i
].u
= ir
->value
.u
[i
];
3096 values
[i
].f
= ir
->value
.u
[i
];
3100 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3101 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3102 if (native_integers
)
3103 values
[i
].i
= ir
->value
.i
[i
];
3105 values
[i
].f
= ir
->value
.i
[i
];
3108 case GLSL_TYPE_BOOL
:
3109 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3110 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3111 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3115 assert(!"Non-float/uint/int/bool constant");
3118 this->result
= st_src_reg(file
, -1, ir
->type
);
3119 this->result
.index
= add_constant(file
,
3121 ir
->type
->vector_elements
,
3123 &this->result
.swizzle
);
3127 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3129 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3130 if (entry
->sig
== sig
)
3134 entry
= ralloc(mem_ctx
, function_entry
);
3136 entry
->sig_id
= this->next_signature_id
++;
3137 entry
->bgn_inst
= NULL
;
3139 /* Allocate storage for all the parameters. */
3140 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3141 variable_storage
*storage
;
3143 storage
= find_variable_storage(param
);
3146 st_src_reg src
= get_temp(param
->type
);
3148 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3149 this->variables
.push_tail(storage
);
3152 if (!sig
->return_type
->is_void()) {
3153 entry
->return_reg
= get_temp(sig
->return_type
);
3155 entry
->return_reg
= undef_src
;
3158 this->function_signatures
.push_tail(entry
);
3163 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3165 const char *callee
= ir
->callee
->function_name();
3166 ir_dereference
*deref
= static_cast<ir_dereference
*>(
3167 ir
->actual_parameters
.get_head());
3168 ir_variable
*location
= deref
->variable_referenced();
3171 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3173 /* Calculate the surface offset */
3175 unsigned array_size
= 0, base
= 0, index
= 0;
3177 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
);
3179 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3180 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3181 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3182 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3183 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3185 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3188 ir
->return_deref
->accept(this);
3189 st_dst_reg
dst(this->result
);
3190 dst
.writemask
= WRITEMASK_X
;
3192 glsl_to_tgsi_instruction
*inst
;
3194 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3195 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3196 inst
->buffer
= buffer
;
3197 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3198 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3199 st_src_reg_for_int(1));
3200 inst
->buffer
= buffer
;
3201 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3202 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3203 st_src_reg_for_int(-1));
3204 inst
->buffer
= buffer
;
3205 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3210 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3212 const char *callee
= ir
->callee
->function_name();
3213 exec_node
*param
= ir
->actual_parameters
.get_head();
3215 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3217 param
= param
->get_next();
3218 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3220 ir_constant
*const_block
= block
->as_constant();
3224 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3225 (const_block
? const_block
->value
.u
[0] : 0),
3229 block
->accept(this);
3230 emit_arl(ir
, sampler_reladdr
, this->result
);
3231 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3232 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3235 /* Calculate the surface offset */
3236 offset
->accept(this);
3237 st_src_reg off
= this->result
;
3239 st_dst_reg dst
= undef_dst
;
3240 if (ir
->return_deref
) {
3241 ir
->return_deref
->accept(this);
3242 dst
= st_dst_reg(this->result
);
3243 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3246 glsl_to_tgsi_instruction
*inst
;
3248 if (!strcmp("__intrinsic_load_ssbo", callee
)) {
3249 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3250 if (dst
.type
== GLSL_TYPE_BOOL
)
3251 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3252 } else if (!strcmp("__intrinsic_store_ssbo", callee
)) {
3253 param
= param
->get_next();
3254 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3257 param
= param
->get_next();
3258 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3260 dst
.writemask
= write_mask
->value
.u
[0];
3262 dst
.type
= this->result
.type
;
3263 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3265 param
= param
->get_next();
3266 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3269 st_src_reg data
= this->result
, data2
= undef_src
;
3271 if (!strcmp("__intrinsic_atomic_add_ssbo", callee
))
3272 opcode
= TGSI_OPCODE_ATOMUADD
;
3273 else if (!strcmp("__intrinsic_atomic_min_ssbo", callee
))
3274 opcode
= TGSI_OPCODE_ATOMIMIN
;
3275 else if (!strcmp("__intrinsic_atomic_max_ssbo", callee
))
3276 opcode
= TGSI_OPCODE_ATOMIMAX
;
3277 else if (!strcmp("__intrinsic_atomic_and_ssbo", callee
))
3278 opcode
= TGSI_OPCODE_ATOMAND
;
3279 else if (!strcmp("__intrinsic_atomic_or_ssbo", callee
))
3280 opcode
= TGSI_OPCODE_ATOMOR
;
3281 else if (!strcmp("__intrinsic_atomic_xor_ssbo", callee
))
3282 opcode
= TGSI_OPCODE_ATOMXOR
;
3283 else if (!strcmp("__intrinsic_atomic_exchange_ssbo", callee
))
3284 opcode
= TGSI_OPCODE_ATOMXCHG
;
3285 else if (!strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3286 opcode
= TGSI_OPCODE_ATOMCAS
;
3287 param
= param
->get_next();
3288 val
= ((ir_instruction
*)param
)->as_rvalue();
3290 data2
= this->result
;
3292 assert(!"Unexpected intrinsic");
3296 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3299 param
= param
->get_next();
3300 ir_constant
*access
= NULL
;
3301 if (!param
->is_tail_sentinel()) {
3302 access
= ((ir_instruction
*)param
)->as_constant();
3306 /* The emit_asm() might have actually split the op into pieces, e.g. for
3307 * double stores. We have to go back and fix up all the generated ops.
3309 unsigned op
= inst
->op
;
3311 inst
->buffer
= buffer
;
3313 inst
->buffer_access
= access
->value
.u
[0];
3314 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3315 if (inst
->op
== TGSI_OPCODE_UADD
)
3316 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3317 } while (inst
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
&& inst
->op
== op
);
3321 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3323 const char *callee
= ir
->callee
->function_name();
3325 if (!strcmp("__intrinsic_memory_barrier", callee
))
3326 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3327 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3328 TGSI_MEMBAR_ATOMIC_BUFFER
|
3329 TGSI_MEMBAR_SHADER_IMAGE
|
3330 TGSI_MEMBAR_SHARED
));
3331 else if (!strcmp("__intrinsic_memory_barrier_atomic_counter", callee
))
3332 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3333 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3334 else if (!strcmp("__intrinsic_memory_barrier_buffer", callee
))
3335 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3336 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3337 else if (!strcmp("__intrinsic_memory_barrier_image", callee
))
3338 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3339 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3340 else if (!strcmp("__intrinsic_memory_barrier_shared", callee
))
3341 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3342 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3343 else if (!strcmp("__intrinsic_group_memory_barrier", callee
))
3344 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3345 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3346 TGSI_MEMBAR_ATOMIC_BUFFER
|
3347 TGSI_MEMBAR_SHADER_IMAGE
|
3348 TGSI_MEMBAR_SHARED
|
3349 TGSI_MEMBAR_THREAD_GROUP
));
3351 assert(!"Unexpected memory barrier intrinsic");
3355 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3357 const char *callee
= ir
->callee
->function_name();
3358 exec_node
*param
= ir
->actual_parameters
.get_head();
3360 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3362 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3364 /* Calculate the surface offset */
3365 offset
->accept(this);
3366 st_src_reg off
= this->result
;
3368 st_dst_reg dst
= undef_dst
;
3369 if (ir
->return_deref
) {
3370 ir
->return_deref
->accept(this);
3371 dst
= st_dst_reg(this->result
);
3372 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3375 glsl_to_tgsi_instruction
*inst
;
3377 if (!strcmp("__intrinsic_load_shared", callee
)) {
3378 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3379 inst
->buffer
= buffer
;
3380 } else if (!strcmp("__intrinsic_store_shared", callee
)) {
3381 param
= param
->get_next();
3382 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3385 param
= param
->get_next();
3386 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3388 dst
.writemask
= write_mask
->value
.u
[0];
3390 dst
.type
= this->result
.type
;
3391 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3392 inst
->buffer
= buffer
;
3394 param
= param
->get_next();
3395 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3398 st_src_reg data
= this->result
, data2
= undef_src
;
3400 if (!strcmp("__intrinsic_atomic_add_shared", callee
))
3401 opcode
= TGSI_OPCODE_ATOMUADD
;
3402 else if (!strcmp("__intrinsic_atomic_min_shared", callee
))
3403 opcode
= TGSI_OPCODE_ATOMIMIN
;
3404 else if (!strcmp("__intrinsic_atomic_max_shared", callee
))
3405 opcode
= TGSI_OPCODE_ATOMIMAX
;
3406 else if (!strcmp("__intrinsic_atomic_and_shared", callee
))
3407 opcode
= TGSI_OPCODE_ATOMAND
;
3408 else if (!strcmp("__intrinsic_atomic_or_shared", callee
))
3409 opcode
= TGSI_OPCODE_ATOMOR
;
3410 else if (!strcmp("__intrinsic_atomic_xor_shared", callee
))
3411 opcode
= TGSI_OPCODE_ATOMXOR
;
3412 else if (!strcmp("__intrinsic_atomic_exchange_shared", callee
))
3413 opcode
= TGSI_OPCODE_ATOMXCHG
;
3414 else if (!strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3415 opcode
= TGSI_OPCODE_ATOMCAS
;
3416 param
= param
->get_next();
3417 val
= ((ir_instruction
*)param
)->as_rvalue();
3419 data2
= this->result
;
3421 assert(!"Unexpected intrinsic");
3425 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3426 inst
->buffer
= buffer
;
3431 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3433 const char *callee
= ir
->callee
->function_name();
3434 exec_node
*param
= ir
->actual_parameters
.get_head();
3436 ir_dereference
*img
= (ir_dereference
*)param
;
3437 const ir_variable
*imgvar
= img
->variable_referenced();
3438 const glsl_type
*type
= imgvar
->type
->without_array();
3439 unsigned sampler_array_size
= 1, sampler_base
= 0;
3442 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3444 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3445 (unsigned int *)&image
.index
, &reladdr
);
3446 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3447 emit_arl(ir
, sampler_reladdr
, reladdr
);
3448 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3449 memcpy(image
.reladdr
, &sampler_reladdr
, sizeof(reladdr
));
3452 st_dst_reg dst
= undef_dst
;
3453 if (ir
->return_deref
) {
3454 ir
->return_deref
->accept(this);
3455 dst
= st_dst_reg(this->result
);
3456 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3459 glsl_to_tgsi_instruction
*inst
;
3461 if (!strcmp("__intrinsic_image_size", callee
)) {
3462 dst
.writemask
= WRITEMASK_XYZ
;
3463 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3464 } else if (!strcmp("__intrinsic_image_samples", callee
)) {
3465 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3466 st_dst_reg dstres
= st_dst_reg(res
);
3467 dstres
.writemask
= WRITEMASK_W
;
3468 emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3469 res
.swizzle
= SWIZZLE_WWWW
;
3470 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3472 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3474 st_dst_reg coord_dst
;
3475 coord
= get_temp(glsl_type::ivec4_type
);
3476 coord_dst
= st_dst_reg(coord
);
3477 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3478 param
= param
->get_next();
3479 ((ir_dereference
*)param
)->accept(this);
3480 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3481 coord
.swizzle
= SWIZZLE_XXXX
;
3482 switch (type
->coordinate_components()) {
3483 case 4: assert(!"unexpected coord count");
3485 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3487 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3490 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3491 param
= param
->get_next();
3492 ((ir_dereference
*)param
)->accept(this);
3493 st_src_reg sample
= this->result
;
3494 sample
.swizzle
= SWIZZLE_XXXX
;
3495 coord_dst
.writemask
= WRITEMASK_W
;
3496 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3497 coord
.swizzle
|= SWIZZLE_W
<< 9;
3500 param
= param
->get_next();
3501 if (!param
->is_tail_sentinel()) {
3502 ((ir_dereference
*)param
)->accept(this);
3503 arg1
= this->result
;
3504 param
= param
->get_next();
3507 if (!param
->is_tail_sentinel()) {
3508 ((ir_dereference
*)param
)->accept(this);
3509 arg2
= this->result
;
3510 param
= param
->get_next();
3513 assert(param
->is_tail_sentinel());
3516 if (!strcmp("__intrinsic_image_load", callee
))
3517 opcode
= TGSI_OPCODE_LOAD
;
3518 else if (!strcmp("__intrinsic_image_store", callee
))
3519 opcode
= TGSI_OPCODE_STORE
;
3520 else if (!strcmp("__intrinsic_image_atomic_add", callee
))
3521 opcode
= TGSI_OPCODE_ATOMUADD
;
3522 else if (!strcmp("__intrinsic_image_atomic_min", callee
))
3523 opcode
= TGSI_OPCODE_ATOMIMIN
;
3524 else if (!strcmp("__intrinsic_image_atomic_max", callee
))
3525 opcode
= TGSI_OPCODE_ATOMIMAX
;
3526 else if (!strcmp("__intrinsic_image_atomic_and", callee
))
3527 opcode
= TGSI_OPCODE_ATOMAND
;
3528 else if (!strcmp("__intrinsic_image_atomic_or", callee
))
3529 opcode
= TGSI_OPCODE_ATOMOR
;
3530 else if (!strcmp("__intrinsic_image_atomic_xor", callee
))
3531 opcode
= TGSI_OPCODE_ATOMXOR
;
3532 else if (!strcmp("__intrinsic_image_atomic_exchange", callee
))
3533 opcode
= TGSI_OPCODE_ATOMXCHG
;
3534 else if (!strcmp("__intrinsic_image_atomic_comp_swap", callee
))
3535 opcode
= TGSI_OPCODE_ATOMCAS
;
3537 assert(!"Unexpected intrinsic");
3541 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3542 if (opcode
== TGSI_OPCODE_STORE
)
3543 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3546 inst
->buffer
= image
;
3547 inst
->sampler_array_size
= sampler_array_size
;
3548 inst
->sampler_base
= sampler_base
;
3550 switch (type
->sampler_dimensionality
) {
3551 case GLSL_SAMPLER_DIM_1D
:
3552 inst
->tex_target
= (type
->sampler_array
)
3553 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3555 case GLSL_SAMPLER_DIM_2D
:
3556 inst
->tex_target
= (type
->sampler_array
)
3557 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3559 case GLSL_SAMPLER_DIM_3D
:
3560 inst
->tex_target
= TEXTURE_3D_INDEX
;
3562 case GLSL_SAMPLER_DIM_CUBE
:
3563 inst
->tex_target
= (type
->sampler_array
)
3564 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3566 case GLSL_SAMPLER_DIM_RECT
:
3567 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3569 case GLSL_SAMPLER_DIM_BUF
:
3570 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3572 case GLSL_SAMPLER_DIM_EXTERNAL
:
3573 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3575 case GLSL_SAMPLER_DIM_MS
:
3576 inst
->tex_target
= (type
->sampler_array
)
3577 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3580 assert(!"Should not get here.");
3583 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3584 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3588 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3590 glsl_to_tgsi_instruction
*call_inst
;
3591 ir_function_signature
*sig
= ir
->callee
;
3592 const char *callee
= sig
->function_name();
3593 function_entry
*entry
;
3596 /* Filter out intrinsics */
3597 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3598 !strcmp("__intrinsic_atomic_increment", callee
) ||
3599 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
3600 visit_atomic_counter_intrinsic(ir
);
3604 if (!strcmp("__intrinsic_load_ssbo", callee
) ||
3605 !strcmp("__intrinsic_store_ssbo", callee
) ||
3606 !strcmp("__intrinsic_atomic_add_ssbo", callee
) ||
3607 !strcmp("__intrinsic_atomic_min_ssbo", callee
) ||
3608 !strcmp("__intrinsic_atomic_max_ssbo", callee
) ||
3609 !strcmp("__intrinsic_atomic_and_ssbo", callee
) ||
3610 !strcmp("__intrinsic_atomic_or_ssbo", callee
) ||
3611 !strcmp("__intrinsic_atomic_xor_ssbo", callee
) ||
3612 !strcmp("__intrinsic_atomic_exchange_ssbo", callee
) ||
3613 !strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3614 visit_ssbo_intrinsic(ir
);
3618 if (!strcmp("__intrinsic_memory_barrier", callee
) ||
3619 !strcmp("__intrinsic_memory_barrier_atomic_counter", callee
) ||
3620 !strcmp("__intrinsic_memory_barrier_buffer", callee
) ||
3621 !strcmp("__intrinsic_memory_barrier_image", callee
) ||
3622 !strcmp("__intrinsic_memory_barrier_shared", callee
) ||
3623 !strcmp("__intrinsic_group_memory_barrier", callee
)) {
3624 visit_membar_intrinsic(ir
);
3628 if (!strcmp("__intrinsic_load_shared", callee
) ||
3629 !strcmp("__intrinsic_store_shared", callee
) ||
3630 !strcmp("__intrinsic_atomic_add_shared", callee
) ||
3631 !strcmp("__intrinsic_atomic_min_shared", callee
) ||
3632 !strcmp("__intrinsic_atomic_max_shared", callee
) ||
3633 !strcmp("__intrinsic_atomic_and_shared", callee
) ||
3634 !strcmp("__intrinsic_atomic_or_shared", callee
) ||
3635 !strcmp("__intrinsic_atomic_xor_shared", callee
) ||
3636 !strcmp("__intrinsic_atomic_exchange_shared", callee
) ||
3637 !strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3638 visit_shared_intrinsic(ir
);
3642 if (!strcmp("__intrinsic_image_load", callee
) ||
3643 !strcmp("__intrinsic_image_store", callee
) ||
3644 !strcmp("__intrinsic_image_atomic_add", callee
) ||
3645 !strcmp("__intrinsic_image_atomic_min", callee
) ||
3646 !strcmp("__intrinsic_image_atomic_max", callee
) ||
3647 !strcmp("__intrinsic_image_atomic_and", callee
) ||
3648 !strcmp("__intrinsic_image_atomic_or", callee
) ||
3649 !strcmp("__intrinsic_image_atomic_xor", callee
) ||
3650 !strcmp("__intrinsic_image_atomic_exchange", callee
) ||
3651 !strcmp("__intrinsic_image_atomic_comp_swap", callee
) ||
3652 !strcmp("__intrinsic_image_size", callee
) ||
3653 !strcmp("__intrinsic_image_samples", callee
)) {
3654 visit_image_intrinsic(ir
);
3658 entry
= get_function_signature(sig
);
3659 /* Process in parameters. */
3660 foreach_two_lists(formal_node
, &sig
->parameters
,
3661 actual_node
, &ir
->actual_parameters
) {
3662 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3663 ir_variable
*param
= (ir_variable
*) formal_node
;
3665 if (param
->data
.mode
== ir_var_function_in
||
3666 param
->data
.mode
== ir_var_function_inout
) {
3667 variable_storage
*storage
= find_variable_storage(param
);
3670 param_rval
->accept(this);
3671 st_src_reg r
= this->result
;
3674 l
.file
= storage
->file
;
3675 l
.index
= storage
->index
;
3677 l
.writemask
= WRITEMASK_XYZW
;
3678 l
.cond_mask
= COND_TR
;
3680 for (i
= 0; i
< type_size(param
->type
); i
++) {
3681 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3688 /* Emit call instruction */
3689 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3690 call_inst
->function
= entry
;
3692 /* Process out parameters. */
3693 foreach_two_lists(formal_node
, &sig
->parameters
,
3694 actual_node
, &ir
->actual_parameters
) {
3695 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3696 ir_variable
*param
= (ir_variable
*) formal_node
;
3698 if (param
->data
.mode
== ir_var_function_out
||
3699 param
->data
.mode
== ir_var_function_inout
) {
3700 variable_storage
*storage
= find_variable_storage(param
);
3704 r
.file
= storage
->file
;
3705 r
.index
= storage
->index
;
3707 r
.swizzle
= SWIZZLE_NOOP
;
3710 param_rval
->accept(this);
3711 st_dst_reg l
= st_dst_reg(this->result
);
3713 for (i
= 0; i
< type_size(param
->type
); i
++) {
3714 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3721 /* Process return value. */
3722 this->result
= entry
->return_reg
;
3726 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3727 ir_dereference
*tail
,
3728 unsigned *array_elements
,
3731 st_src_reg
*indirect
,
3734 switch (tail
->ir_type
) {
3735 case ir_type_dereference_record
: {
3736 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3737 const glsl_type
*struct_type
= deref_record
->record
->type
;
3738 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3740 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3742 assert(field_index
>= 0);
3743 *location
+= struct_type
->record_location_offset(field_index
);
3747 case ir_type_dereference_array
: {
3748 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3749 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3752 st_src_reg temp_reg
;
3753 st_dst_reg temp_dst
;
3755 temp_reg
= get_temp(glsl_type::uint_type
);
3756 temp_dst
= st_dst_reg(temp_reg
);
3757 temp_dst
.writemask
= 1;
3759 deref_arr
->array_index
->accept(this);
3760 if (*array_elements
!= 1)
3761 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3763 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3765 if (indirect
->file
== PROGRAM_UNDEFINED
)
3766 *indirect
= temp_reg
;
3768 temp_dst
= st_dst_reg(*indirect
);
3769 temp_dst
.writemask
= 1;
3770 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3773 *index
+= array_index
->value
.u
[0] * *array_elements
;
3775 *array_elements
*= deref_arr
->array
->type
->length
;
3777 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3786 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3787 unsigned *array_size
,
3790 st_src_reg
*reladdr
)
3792 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3793 unsigned location
= 0;
3794 ir_variable
*var
= ir
->variable_referenced();
3796 memset(reladdr
, 0, sizeof(*reladdr
));
3797 reladdr
->file
= PROGRAM_UNDEFINED
;
3803 location
= var
->data
.location
;
3804 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3807 * If we end up with no indirect then adjust the base to the index,
3808 * and set the array size to 1.
3810 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3815 if (location
!= 0xffffffff) {
3816 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3817 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3822 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3824 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3825 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3826 st_src_reg levels_src
, reladdr
;
3827 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3828 glsl_to_tgsi_instruction
*inst
= NULL
;
3829 unsigned opcode
= TGSI_OPCODE_NOP
;
3830 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3831 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
3832 bool is_cube_array
= false;
3835 /* if we are a cube array sampler */
3836 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3837 sampler_type
->sampler_array
)) {
3838 is_cube_array
= true;
3841 if (ir
->coordinate
) {
3842 ir
->coordinate
->accept(this);
3844 /* Put our coords in a temp. We'll need to modify them for shadow,
3845 * projection, or LOD, so the only case we'd use it as is is if
3846 * we're doing plain old texturing. The optimization passes on
3847 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3849 coord
= get_temp(glsl_type::vec4_type
);
3850 coord_dst
= st_dst_reg(coord
);
3851 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3852 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3855 if (ir
->projector
) {
3856 ir
->projector
->accept(this);
3857 projector
= this->result
;
3860 /* Storage for our result. Ideally for an assignment we'd be using
3861 * the actual storage for the result here, instead.
3863 result_src
= get_temp(ir
->type
);
3864 result_dst
= st_dst_reg(result_src
);
3868 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3870 ir
->offset
->accept(this);
3871 offset
[0] = this->result
;
3875 if (is_cube_array
||
3876 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3877 opcode
= TGSI_OPCODE_TXB2
;
3880 opcode
= TGSI_OPCODE_TXB
;
3882 ir
->lod_info
.bias
->accept(this);
3883 lod_info
= this->result
;
3885 ir
->offset
->accept(this);
3886 offset
[0] = this->result
;
3890 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3891 ir
->lod_info
.lod
->accept(this);
3892 lod_info
= this->result
;
3894 ir
->offset
->accept(this);
3895 offset
[0] = this->result
;
3899 opcode
= TGSI_OPCODE_TXD
;
3900 ir
->lod_info
.grad
.dPdx
->accept(this);
3902 ir
->lod_info
.grad
.dPdy
->accept(this);
3905 ir
->offset
->accept(this);
3906 offset
[0] = this->result
;
3910 opcode
= TGSI_OPCODE_TXQ
;
3911 ir
->lod_info
.lod
->accept(this);
3912 lod_info
= this->result
;
3914 case ir_query_levels
:
3915 opcode
= TGSI_OPCODE_TXQ
;
3916 lod_info
= undef_src
;
3917 levels_src
= get_temp(ir
->type
);
3920 opcode
= TGSI_OPCODE_TXF
;
3921 ir
->lod_info
.lod
->accept(this);
3922 lod_info
= this->result
;
3924 ir
->offset
->accept(this);
3925 offset
[0] = this->result
;
3929 opcode
= TGSI_OPCODE_TXF
;
3930 ir
->lod_info
.sample_index
->accept(this);
3931 sample_index
= this->result
;
3934 opcode
= TGSI_OPCODE_TG4
;
3935 ir
->lod_info
.component
->accept(this);
3936 component
= this->result
;
3938 ir
->offset
->accept(this);
3939 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3940 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3941 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3942 offset
[i
] = this->result
;
3943 offset
[i
].index
+= i
* type_size(elt_type
);
3944 offset
[i
].type
= elt_type
->base_type
;
3945 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3948 offset
[0] = this->result
;
3953 opcode
= TGSI_OPCODE_LODQ
;
3955 case ir_texture_samples
:
3956 opcode
= TGSI_OPCODE_TXQS
;
3958 case ir_samples_identical
:
3959 unreachable("Unexpected ir_samples_identical opcode");
3962 if (ir
->projector
) {
3963 if (opcode
== TGSI_OPCODE_TEX
) {
3964 /* Slot the projector in as the last component of the coord. */
3965 coord_dst
.writemask
= WRITEMASK_W
;
3966 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3967 coord_dst
.writemask
= WRITEMASK_XYZW
;
3968 opcode
= TGSI_OPCODE_TXP
;
3970 st_src_reg coord_w
= coord
;
3971 coord_w
.swizzle
= SWIZZLE_WWWW
;
3973 /* For the other TEX opcodes there's no projective version
3974 * since the last slot is taken up by LOD info. Do the
3975 * projective divide now.
3977 coord_dst
.writemask
= WRITEMASK_W
;
3978 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3980 /* In the case where we have to project the coordinates "by hand,"
3981 * the shadow comparator value must also be projected.
3983 st_src_reg tmp_src
= coord
;
3984 if (ir
->shadow_comparitor
) {
3985 /* Slot the shadow value in as the second to last component of the
3988 ir
->shadow_comparitor
->accept(this);
3990 tmp_src
= get_temp(glsl_type::vec4_type
);
3991 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3993 /* Projective division not allowed for array samplers. */
3994 assert(!sampler_type
->sampler_array
);
3996 tmp_dst
.writemask
= WRITEMASK_Z
;
3997 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3999 tmp_dst
.writemask
= WRITEMASK_XY
;
4000 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4003 coord_dst
.writemask
= WRITEMASK_XYZ
;
4004 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4006 coord_dst
.writemask
= WRITEMASK_XYZW
;
4007 coord
.swizzle
= SWIZZLE_XYZW
;
4011 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4012 * comparator was put in the correct place (and projected) by the code,
4013 * above, that handles by-hand projection.
4015 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4016 /* Slot the shadow value in as the second to last component of the
4019 ir
->shadow_comparitor
->accept(this);
4021 if (is_cube_array
) {
4022 cube_sc
= get_temp(glsl_type::float_type
);
4023 cube_sc_dst
= st_dst_reg(cube_sc
);
4024 cube_sc_dst
.writemask
= WRITEMASK_X
;
4025 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4026 cube_sc_dst
.writemask
= WRITEMASK_X
;
4029 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4030 sampler_type
->sampler_array
) ||
4031 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4032 coord_dst
.writemask
= WRITEMASK_W
;
4034 coord_dst
.writemask
= WRITEMASK_Z
;
4036 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4037 coord_dst
.writemask
= WRITEMASK_XYZW
;
4041 if (ir
->op
== ir_txf_ms
) {
4042 coord_dst
.writemask
= WRITEMASK_W
;
4043 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4044 coord_dst
.writemask
= WRITEMASK_XYZW
;
4045 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4046 opcode
== TGSI_OPCODE_TXF
) {
4047 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4048 coord_dst
.writemask
= WRITEMASK_W
;
4049 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4050 coord_dst
.writemask
= WRITEMASK_XYZW
;
4053 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4054 &sampler_index
, &reladdr
);
4055 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4056 emit_arl(ir
, sampler_reladdr
, reladdr
);
4058 if (opcode
== TGSI_OPCODE_TXD
)
4059 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4060 else if (opcode
== TGSI_OPCODE_TXQ
) {
4061 if (ir
->op
== ir_query_levels
) {
4062 /* the level is stored in W */
4063 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4064 result_dst
.writemask
= WRITEMASK_X
;
4065 levels_src
.swizzle
= SWIZZLE_WWWW
;
4066 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4068 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4069 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4070 inst
= emit_asm(ir
, opcode
, result_dst
);
4071 } else if (opcode
== TGSI_OPCODE_TXF
) {
4072 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4073 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4074 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4075 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4076 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4077 } else if (opcode
== TGSI_OPCODE_TG4
) {
4078 if (is_cube_array
&& ir
->shadow_comparitor
) {
4079 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4081 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4084 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4086 if (ir
->shadow_comparitor
)
4087 inst
->tex_shadow
= GL_TRUE
;
4089 inst
->sampler
.index
= sampler_index
;
4090 inst
->sampler_array_size
= sampler_array_size
;
4091 inst
->sampler_base
= sampler_base
;
4093 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4094 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4095 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4099 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4100 inst
->tex_offsets
[i
] = offset
[i
];
4101 inst
->tex_offset_num_offset
= i
;
4104 switch (sampler_type
->sampler_dimensionality
) {
4105 case GLSL_SAMPLER_DIM_1D
:
4106 inst
->tex_target
= (sampler_type
->sampler_array
)
4107 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4109 case GLSL_SAMPLER_DIM_2D
:
4110 inst
->tex_target
= (sampler_type
->sampler_array
)
4111 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4113 case GLSL_SAMPLER_DIM_3D
:
4114 inst
->tex_target
= TEXTURE_3D_INDEX
;
4116 case GLSL_SAMPLER_DIM_CUBE
:
4117 inst
->tex_target
= (sampler_type
->sampler_array
)
4118 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4120 case GLSL_SAMPLER_DIM_RECT
:
4121 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4123 case GLSL_SAMPLER_DIM_BUF
:
4124 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4126 case GLSL_SAMPLER_DIM_EXTERNAL
:
4127 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4129 case GLSL_SAMPLER_DIM_MS
:
4130 inst
->tex_target
= (sampler_type
->sampler_array
)
4131 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4134 assert(!"Should not get here.");
4137 inst
->tex_type
= ir
->type
->base_type
;
4139 this->result
= result_src
;
4143 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4145 if (ir
->get_value()) {
4149 assert(current_function
);
4151 ir
->get_value()->accept(this);
4152 st_src_reg r
= this->result
;
4154 l
= st_dst_reg(current_function
->return_reg
);
4156 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4157 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4163 emit_asm(ir
, TGSI_OPCODE_RET
);
4167 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4169 if (ir
->condition
) {
4170 ir
->condition
->accept(this);
4171 st_src_reg condition
= this->result
;
4173 /* Convert the bool condition to a float so we can negate. */
4174 if (native_integers
) {
4175 st_src_reg temp
= get_temp(ir
->condition
->type
);
4176 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4177 condition
, st_src_reg_for_float(1.0));
4181 condition
.negate
= ~condition
.negate
;
4182 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4184 /* unconditional kil */
4185 emit_asm(ir
, TGSI_OPCODE_KILL
);
4190 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4193 glsl_to_tgsi_instruction
*if_inst
;
4195 ir
->condition
->accept(this);
4196 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4198 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4200 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4202 this->instructions
.push_tail(if_inst
);
4204 visit_exec_list(&ir
->then_instructions
, this);
4206 if (!ir
->else_instructions
.is_empty()) {
4207 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4208 visit_exec_list(&ir
->else_instructions
, this);
4211 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4216 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4218 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4220 ir
->stream
->accept(this);
4221 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4225 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4227 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4229 ir
->stream
->accept(this);
4230 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4234 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4236 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4237 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4239 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4242 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4244 result
.file
= PROGRAM_UNDEFINED
;
4249 num_input_arrays
= 0;
4250 num_output_arrays
= 0;
4251 next_signature_id
= 1;
4253 current_function
= NULL
;
4254 num_address_regs
= 0;
4258 indirect_addr_consts
= false;
4259 wpos_transform_const
= -1;
4261 native_integers
= false;
4262 mem_ctx
= ralloc_context(NULL
);
4265 shader_program
= NULL
;
4270 use_shared_memory
= false;
4273 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4276 ralloc_free(mem_ctx
);
4279 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4286 * Count resources used by the given gpu program (number of texture
4290 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4292 v
->samplers_used
= 0;
4293 v
->buffers_used
= 0;
4296 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4297 if (inst
->info
->is_tex
) {
4298 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4299 unsigned idx
= inst
->sampler_base
+ i
;
4300 v
->samplers_used
|= 1 << idx
;
4302 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4303 v
->sampler_types
[idx
] = inst
->tex_type
;
4304 v
->sampler_targets
[idx
] =
4305 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4307 if (inst
->tex_shadow
) {
4308 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4312 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4313 is_resource_instruction(inst
->op
) ||
4314 inst
->op
== TGSI_OPCODE_STORE
)) {
4315 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4316 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4317 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4318 v
->use_shared_memory
= true;
4320 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4321 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4322 unsigned idx
= inst
->sampler_base
+ i
;
4323 v
->images_used
|= 1 << idx
;
4324 v
->image_targets
[idx
] =
4325 st_translate_texture_target(inst
->tex_target
, false);
4326 v
->image_formats
[idx
] = inst
->image_format
;
4331 prog
->SamplersUsed
= v
->samplers_used
;
4333 if (v
->shader_program
!= NULL
)
4334 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4338 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4339 * are read from the given src in this instruction
4342 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4344 int read_mask
= 0, comp
;
4346 /* Now, given the src swizzle and the written channels, find which
4347 * components are actually read
4349 for (comp
= 0; comp
< 4; ++comp
) {
4350 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4352 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4353 read_mask
|= 1 << coord
;
4360 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4361 * instruction is the first instruction to write to register T0. There are
4362 * several lowering passes done in GLSL IR (e.g. branches and
4363 * relative addressing) that create a large number of conditional assignments
4364 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4366 * Here is why this conversion is safe:
4367 * CMP T0, T1 T2 T0 can be expanded to:
4373 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4374 * as the original program. If (T1 < 0.0) evaluates to false, executing
4375 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4376 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4377 * because any instruction that was going to read from T0 after this was going
4378 * to read a garbage value anyway.
4381 glsl_to_tgsi_visitor::simplify_cmp(void)
4383 int tempWritesSize
= 0;
4384 unsigned *tempWrites
= NULL
;
4385 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4387 memset(outputWrites
, 0, sizeof(outputWrites
));
4389 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4390 unsigned prevWriteMask
= 0;
4392 /* Give up if we encounter relative addressing or flow control. */
4393 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4394 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4395 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4396 inst
->op
== TGSI_OPCODE_BGNSUB
||
4397 inst
->op
== TGSI_OPCODE_CONT
||
4398 inst
->op
== TGSI_OPCODE_END
||
4399 inst
->op
== TGSI_OPCODE_ENDSUB
||
4400 inst
->op
== TGSI_OPCODE_RET
) {
4404 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4405 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4406 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4407 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4408 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4409 if (inst
->dst
[0].index
>= tempWritesSize
) {
4410 const int inc
= 4096;
4412 tempWrites
= (unsigned*)
4414 (tempWritesSize
+ inc
) * sizeof(unsigned));
4418 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4419 tempWritesSize
+= inc
;
4422 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4423 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4427 /* For a CMP to be considered a conditional write, the destination
4428 * register and source register two must be the same. */
4429 if (inst
->op
== TGSI_OPCODE_CMP
4430 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4431 && inst
->src
[2].file
== inst
->dst
[0].file
4432 && inst
->src
[2].index
== inst
->dst
[0].index
4433 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4435 inst
->op
= TGSI_OPCODE_MOV
;
4436 inst
->src
[0] = inst
->src
[1];
4443 /* Replaces all references to a temporary register index with another index. */
4445 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4447 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4450 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4451 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4452 for (k
= 0; k
< num_renames
; k
++)
4453 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4454 inst
->src
[j
].index
= renames
[k
].new_reg
;
4457 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4458 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4459 for (k
= 0; k
< num_renames
; k
++)
4460 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4461 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4464 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4465 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4466 for (k
= 0; k
< num_renames
; k
++)
4467 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4468 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4474 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4476 int depth
= 0; /* loop depth */
4477 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4480 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4481 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4482 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4483 if (first_reads
[inst
->src
[j
].index
] == -1)
4484 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4487 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4488 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4489 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4490 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4493 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4496 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4506 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4508 int depth
= 0; /* loop depth */
4509 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4512 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4513 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4514 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4515 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4517 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4518 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4519 if (first_writes
[inst
->dst
[j
].index
] == -1)
4520 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4521 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4524 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4525 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4526 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4528 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4531 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4534 for (k
= 0; k
< this->next_temp
; k
++) {
4535 if (last_reads
[k
] == -2) {
4547 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4549 int depth
= 0; /* loop depth */
4553 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4554 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4555 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4556 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4559 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4561 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4563 for (k
= 0; k
< this->next_temp
; k
++) {
4564 if (last_writes
[k
] == -2) {
4575 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4576 * channels for copy propagation and updates following instructions to
4577 * use the original versions.
4579 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4580 * will occur. As an example, a TXP production before this pass:
4582 * 0: MOV TEMP[1], INPUT[4].xyyy;
4583 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4584 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4588 * 0: MOV TEMP[1], INPUT[4].xyyy;
4589 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4590 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4592 * which allows for dead code elimination on TEMP[1]'s writes.
4595 glsl_to_tgsi_visitor::copy_propagate(void)
4597 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4598 glsl_to_tgsi_instruction
*,
4599 this->next_temp
* 4);
4600 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4603 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4604 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4605 || inst
->dst
[0].index
< this->next_temp
);
4607 /* First, do any copy propagation possible into the src regs. */
4608 for (int r
= 0; r
< 3; r
++) {
4609 glsl_to_tgsi_instruction
*first
= NULL
;
4611 int acp_base
= inst
->src
[r
].index
* 4;
4613 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4614 inst
->src
[r
].reladdr
||
4615 inst
->src
[r
].reladdr2
)
4618 /* See if we can find entries in the ACP consisting of MOVs
4619 * from the same src register for all the swizzled channels
4620 * of this src register reference.
4622 for (int i
= 0; i
< 4; i
++) {
4623 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4624 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4631 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4636 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4637 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4638 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4639 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4647 /* We've now validated that we can copy-propagate to
4648 * replace this src register reference. Do it.
4650 inst
->src
[r
].file
= first
->src
[0].file
;
4651 inst
->src
[r
].index
= first
->src
[0].index
;
4652 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4653 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4654 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4655 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4658 for (int i
= 0; i
< 4; i
++) {
4659 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4660 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4661 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4663 inst
->src
[r
].swizzle
= swizzle
;
4668 case TGSI_OPCODE_BGNLOOP
:
4669 case TGSI_OPCODE_ENDLOOP
:
4670 /* End of a basic block, clear the ACP entirely. */
4671 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4674 case TGSI_OPCODE_IF
:
4675 case TGSI_OPCODE_UIF
:
4679 case TGSI_OPCODE_ENDIF
:
4680 case TGSI_OPCODE_ELSE
:
4681 /* Clear all channels written inside the block from the ACP, but
4682 * leaving those that were not touched.
4684 for (int r
= 0; r
< this->next_temp
; r
++) {
4685 for (int c
= 0; c
< 4; c
++) {
4686 if (!acp
[4 * r
+ c
])
4689 if (acp_level
[4 * r
+ c
] >= level
)
4690 acp
[4 * r
+ c
] = NULL
;
4693 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4698 /* Continuing the block, clear any written channels from
4701 for (int d
= 0; d
< 2; d
++) {
4702 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4703 /* Any temporary might be written, so no copy propagation
4704 * across this instruction.
4706 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4707 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4708 inst
->dst
[d
].reladdr
) {
4709 /* Any output might be written, so no copy propagation
4710 * from outputs across this instruction.
4712 for (int r
= 0; r
< this->next_temp
; r
++) {
4713 for (int c
= 0; c
< 4; c
++) {
4714 if (!acp
[4 * r
+ c
])
4717 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4718 acp
[4 * r
+ c
] = NULL
;
4721 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4722 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4723 /* Clear where it's used as dst. */
4724 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4725 for (int c
= 0; c
< 4; c
++) {
4726 if (inst
->dst
[d
].writemask
& (1 << c
))
4727 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4731 /* Clear where it's used as src. */
4732 for (int r
= 0; r
< this->next_temp
; r
++) {
4733 for (int c
= 0; c
< 4; c
++) {
4734 if (!acp
[4 * r
+ c
])
4737 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4739 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4740 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4741 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4742 acp
[4 * r
+ c
] = NULL
;
4751 /* If this is a copy, add it to the ACP. */
4752 if (inst
->op
== TGSI_OPCODE_MOV
&&
4753 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4754 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4755 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4756 !inst
->dst
[0].reladdr
&&
4757 !inst
->dst
[0].reladdr2
&&
4759 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4760 !inst
->src
[0].reladdr
&&
4761 !inst
->src
[0].reladdr2
&&
4762 !inst
->src
[0].negate
) {
4763 for (int i
= 0; i
< 4; i
++) {
4764 if (inst
->dst
[0].writemask
& (1 << i
)) {
4765 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4766 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4772 ralloc_free(acp_level
);
4777 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4780 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4781 * will occur. As an example, a TXP production after copy propagation but
4784 * 0: MOV TEMP[1], INPUT[4].xyyy;
4785 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4786 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4788 * and after this pass:
4790 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4793 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4795 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4796 glsl_to_tgsi_instruction
*,
4797 this->next_temp
* 4);
4798 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4802 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4803 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4804 || inst
->dst
[0].index
< this->next_temp
);
4807 case TGSI_OPCODE_BGNLOOP
:
4808 case TGSI_OPCODE_ENDLOOP
:
4809 case TGSI_OPCODE_CONT
:
4810 case TGSI_OPCODE_BRK
:
4811 /* End of a basic block, clear the write array entirely.
4813 * This keeps us from killing dead code when the writes are
4814 * on either side of a loop, even when the register isn't touched
4815 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4816 * dead code of this type, so it shouldn't make a difference as long as
4817 * the dead code elimination pass in the GLSL compiler does its job.
4819 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4822 case TGSI_OPCODE_ENDIF
:
4823 case TGSI_OPCODE_ELSE
:
4824 /* Promote the recorded level of all channels written inside the
4825 * preceding if or else block to the level above the if/else block.
4827 for (int r
= 0; r
< this->next_temp
; r
++) {
4828 for (int c
= 0; c
< 4; c
++) {
4829 if (!writes
[4 * r
+ c
])
4832 if (write_level
[4 * r
+ c
] == level
)
4833 write_level
[4 * r
+ c
] = level
-1;
4836 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4840 case TGSI_OPCODE_IF
:
4841 case TGSI_OPCODE_UIF
:
4843 /* fallthrough to default case to mark the condition as read */
4845 /* Continuing the block, clear any channels from the write array that
4846 * are read by this instruction.
4848 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4849 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4850 /* Any temporary might be read, so no dead code elimination
4851 * across this instruction.
4853 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4854 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4855 /* Clear where it's used as src. */
4856 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4857 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4858 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4859 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4861 for (int c
= 0; c
< 4; c
++) {
4862 if (src_chans
& (1 << c
))
4863 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4867 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4868 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4869 /* Any temporary might be read, so no dead code elimination
4870 * across this instruction.
4872 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4873 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4874 /* Clear where it's used as src. */
4875 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4876 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4877 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4878 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4880 for (int c
= 0; c
< 4; c
++) {
4881 if (src_chans
& (1 << c
))
4882 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4889 /* If this instruction writes to a temporary, add it to the write array.
4890 * If there is already an instruction in the write array for one or more
4891 * of the channels, flag that channel write as dead.
4893 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4894 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4895 !inst
->dst
[i
].reladdr
) {
4896 for (int c
= 0; c
< 4; c
++) {
4897 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4898 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4899 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4902 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4904 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4905 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4912 /* Anything still in the write array at this point is dead code. */
4913 for (int r
= 0; r
< this->next_temp
; r
++) {
4914 for (int c
= 0; c
< 4; c
++) {
4915 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4917 inst
->dead_mask
|= (1 << c
);
4921 /* Now actually remove the instructions that are completely dead and update
4922 * the writemask of other instructions with dead channels.
4924 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4925 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4927 /* No amount of dead masks should remove memory stores */
4928 if (inst
->info
->is_store
)
4931 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4936 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4937 if (inst
->dead_mask
== WRITEMASK_XY
||
4938 inst
->dead_mask
== WRITEMASK_ZW
)
4939 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4941 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4945 ralloc_free(write_level
);
4946 ralloc_free(writes
);
4951 /* merge DFRACEXP instructions into one. */
4953 glsl_to_tgsi_visitor::merge_two_dsts(void)
4955 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4956 glsl_to_tgsi_instruction
*inst2
;
4958 if (num_inst_dst_regs(inst
) != 2)
4961 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4962 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4965 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4968 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4969 inst
->src
[0].index
== inst2
->src
[0].index
&&
4970 inst
->src
[0].type
== inst2
->src
[0].type
&&
4971 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4973 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4979 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4981 inst
->dst
[0] = inst2
->dst
[0];
4982 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4983 inst
->dst
[1] = inst2
->dst
[1];
4994 /* Merges temporary registers together where possible to reduce the number of
4995 * registers needed to run a program.
4997 * Produces optimal code only after copy propagation and dead code elimination
5000 glsl_to_tgsi_visitor::merge_registers(void)
5002 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5003 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5004 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5006 int num_renames
= 0;
5008 /* Read the indices of the last read and first write to each temp register
5009 * into an array so that we don't have to traverse the instruction list as
5011 for (i
= 0; i
< this->next_temp
; i
++) {
5013 first_writes
[i
] = -1;
5015 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5017 /* Start looking for registers with non-overlapping usages that can be
5018 * merged together. */
5019 for (i
= 0; i
< this->next_temp
; i
++) {
5020 /* Don't touch unused registers. */
5021 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5023 for (j
= 0; j
< this->next_temp
; j
++) {
5024 /* Don't touch unused registers. */
5025 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5027 /* We can merge the two registers if the first write to j is after or
5028 * in the same instruction as the last read from i. Note that the
5029 * register at index i will always be used earlier or at the same time
5030 * as the register at index j. */
5031 if (first_writes
[i
] <= first_writes
[j
] &&
5032 last_reads
[i
] <= first_writes
[j
]) {
5033 renames
[num_renames
].old_reg
= j
;
5034 renames
[num_renames
].new_reg
= i
;
5037 /* Update the first_writes and last_reads arrays with the new
5038 * values for the merged register index, and mark the newly unused
5039 * register index as such. */
5040 assert(last_reads
[j
] >= last_reads
[i
]);
5041 last_reads
[i
] = last_reads
[j
];
5042 first_writes
[j
] = -1;
5048 rename_temp_registers(num_renames
, renames
);
5049 ralloc_free(renames
);
5050 ralloc_free(last_reads
);
5051 ralloc_free(first_writes
);
5054 /* Reassign indices to temporary registers by reusing unused indices created
5055 * by optimization passes. */
5057 glsl_to_tgsi_visitor::renumber_registers(void)
5061 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5062 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5063 int num_renames
= 0;
5064 for (i
= 0; i
< this->next_temp
; i
++) {
5065 first_reads
[i
] = -1;
5067 get_first_temp_read(first_reads
);
5069 for (i
= 0; i
< this->next_temp
; i
++) {
5070 if (first_reads
[i
] < 0) continue;
5071 if (i
!= new_index
) {
5072 renames
[num_renames
].old_reg
= i
;
5073 renames
[num_renames
].new_reg
= new_index
;
5079 rename_temp_registers(num_renames
, renames
);
5080 this->next_temp
= new_index
;
5081 ralloc_free(renames
);
5082 ralloc_free(first_reads
);
5085 /* ------------------------- TGSI conversion stuff -------------------------- */
5087 unsigned branch_target
;
5092 * Intermediate state used during shader translation.
5094 struct st_translate
{
5095 struct ureg_program
*ureg
;
5097 unsigned temps_size
;
5098 struct ureg_dst
*temps
;
5100 struct ureg_dst
*arrays
;
5101 unsigned num_temp_arrays
;
5102 struct ureg_src
*constants
;
5104 struct ureg_src
*immediates
;
5106 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5107 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5108 struct ureg_dst address
[3];
5109 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5110 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5111 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5112 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5113 struct ureg_src shared_memory
;
5114 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5115 unsigned *array_sizes
;
5116 struct array_decl
*input_arrays
;
5117 struct array_decl
*output_arrays
;
5119 const GLuint
*inputMapping
;
5120 const GLuint
*outputMapping
;
5122 /* For every instruction that contains a label (eg CALL), keep
5123 * details so that we can go back afterwards and emit the correct
5124 * tgsi instruction number for each label.
5126 struct label
*labels
;
5127 unsigned labels_size
;
5128 unsigned labels_count
;
5130 /* Keep a record of the tgsi instruction number that each mesa
5131 * instruction starts at, will be used to fix up labels after
5136 unsigned insn_count
;
5138 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
5143 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5144 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
5147 TGSI_SEMANTIC_VERTEXID
,
5148 TGSI_SEMANTIC_INSTANCEID
,
5149 TGSI_SEMANTIC_VERTEXID_NOBASE
,
5150 TGSI_SEMANTIC_BASEVERTEX
,
5151 TGSI_SEMANTIC_BASEINSTANCE
,
5152 TGSI_SEMANTIC_DRAWID
,
5156 TGSI_SEMANTIC_INVOCATIONID
,
5160 TGSI_SEMANTIC_POSITION
,
5162 TGSI_SEMANTIC_SAMPLEID
,
5163 TGSI_SEMANTIC_SAMPLEPOS
,
5164 TGSI_SEMANTIC_SAMPLEMASK
,
5165 TGSI_SEMANTIC_HELPER_INVOCATION
,
5167 /* Tessellation shaders
5169 TGSI_SEMANTIC_TESSCOORD
,
5170 TGSI_SEMANTIC_VERTICESIN
,
5171 TGSI_SEMANTIC_PRIMID
,
5172 TGSI_SEMANTIC_TESSOUTER
,
5173 TGSI_SEMANTIC_TESSINNER
,
5177 TGSI_SEMANTIC_THREAD_ID
,
5178 TGSI_SEMANTIC_BLOCK_ID
,
5179 TGSI_SEMANTIC_GRID_SIZE
,
5183 * Make note of a branch to a label in the TGSI code.
5184 * After we've emitted all instructions, we'll go over the list
5185 * of labels built here and patch the TGSI code with the actual
5186 * location of each label.
5188 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5192 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5193 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5194 t
->labels
= (struct label
*)realloc(t
->labels
,
5195 t
->labels_size
* sizeof(struct label
));
5196 if (t
->labels
== NULL
) {
5197 static unsigned dummy
;
5203 i
= t
->labels_count
++;
5204 t
->labels
[i
].branch_target
= branch_target
;
5205 return &t
->labels
[i
].token
;
5209 * Called prior to emitting the TGSI code for each instruction.
5210 * Allocate additional space for instructions if needed.
5211 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5212 * the next TGSI instruction.
5214 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5216 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5217 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5218 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5219 if (t
->insn
== NULL
) {
5225 t
->insn
[t
->insn_count
++] = start
;
5229 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5231 static struct ureg_src
5232 emit_immediate(struct st_translate
*t
,
5233 gl_constant_value values
[4],
5236 struct ureg_program
*ureg
= t
->ureg
;
5241 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5243 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5245 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5246 case GL_UNSIGNED_INT
:
5248 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5250 assert(!"should not get here - type must be float, int, uint, or bool");
5251 return ureg_src_undef();
5256 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5258 static struct ureg_dst
5259 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5265 case PROGRAM_UNDEFINED
:
5266 return ureg_dst_undef();
5268 case PROGRAM_TEMPORARY
:
5269 /* Allocate space for temporaries on demand. */
5270 if (index
>= t
->temps_size
) {
5271 const int inc
= 4096;
5273 t
->temps
= (struct ureg_dst
*)
5275 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5277 return ureg_dst_undef();
5279 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5280 t
->temps_size
+= inc
;
5283 if (ureg_dst_is_undef(t
->temps
[index
]))
5284 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5286 return t
->temps
[index
];
5289 array
= index
>> 16;
5291 assert(array
< t
->num_temp_arrays
);
5293 if (ureg_dst_is_undef(t
->arrays
[array
]))
5294 t
->arrays
[array
] = ureg_DECL_array_temporary(
5295 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5297 return ureg_dst_array_offset(t
->arrays
[array
],
5298 (int)(index
& 0xFFFF) - 0x8000);
5300 case PROGRAM_OUTPUT
:
5302 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
5303 assert(index
< FRAG_RESULT_MAX
);
5304 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
5305 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
5306 assert(index
< VARYING_SLOT_TESS_MAX
);
5308 assert(index
< VARYING_SLOT_MAX
);
5310 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5311 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5312 return t
->outputs
[t
->outputMapping
[index
]];
5315 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
5316 unsigned mesa_index
= decl
->mesa_index
;
5317 int slot
= t
->outputMapping
[mesa_index
];
5319 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5320 assert(t
->outputs
[slot
].ArrayID
== array_id
);
5321 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
5324 case PROGRAM_ADDRESS
:
5325 return t
->address
[index
];
5328 assert(!"unknown dst register file");
5329 return ureg_dst_undef();
5334 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5336 static struct ureg_src
5337 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5339 int index
= reg
->index
;
5340 int double_reg2
= reg
->double_reg2
? 1 : 0;
5343 case PROGRAM_UNDEFINED
:
5344 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5346 case PROGRAM_TEMPORARY
:
5348 case PROGRAM_OUTPUT
:
5349 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5351 case PROGRAM_UNIFORM
:
5352 assert(reg
->index
>= 0);
5353 return reg
->index
< t
->num_constants
?
5354 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5355 case PROGRAM_STATE_VAR
:
5356 case PROGRAM_CONSTANT
: /* ie, immediate */
5357 if (reg
->has_index2
)
5358 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5360 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5361 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5363 case PROGRAM_IMMEDIATE
:
5364 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5365 return t
->immediates
[reg
->index
];
5368 /* GLSL inputs are 64-bit containers, so we have to
5369 * map back to the original index and add the offset after
5371 index
-= double_reg2
;
5372 if (!reg
->array_id
) {
5373 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5374 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5375 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5378 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
5379 unsigned mesa_index
= decl
->mesa_index
;
5380 int slot
= t
->inputMapping
[mesa_index
];
5382 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5383 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
5384 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
5387 case PROGRAM_ADDRESS
:
5388 return ureg_src(t
->address
[reg
->index
]);
5390 case PROGRAM_SYSTEM_VALUE
:
5391 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5392 return t
->systemValues
[reg
->index
];
5395 assert(!"unknown src register file");
5396 return ureg_src_undef();
5401 * Create a TGSI ureg_dst register from an st_dst_reg.
5403 static struct ureg_dst
5404 translate_dst(struct st_translate
*t
,
5405 const st_dst_reg
*dst_reg
,
5408 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5411 if (dst
.File
== TGSI_FILE_NULL
)
5414 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5417 dst
= ureg_saturate(dst
);
5419 if (dst_reg
->reladdr
!= NULL
) {
5420 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5421 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5424 if (dst_reg
->has_index2
) {
5425 if (dst_reg
->reladdr2
)
5426 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5429 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5436 * Create a TGSI ureg_src register from an st_src_reg.
5438 static struct ureg_src
5439 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5441 struct ureg_src src
= src_register(t
, src_reg
);
5443 if (src_reg
->has_index2
) {
5444 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5445 * and UBO constant buffers (buffer, position).
5447 if (src_reg
->reladdr2
)
5448 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5451 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5454 src
= ureg_swizzle(src
,
5455 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5456 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5457 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5458 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5460 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5461 src
= ureg_negate(src
);
5463 if (src_reg
->reladdr
!= NULL
) {
5464 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5465 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5471 static struct tgsi_texture_offset
5472 translate_tex_offset(struct st_translate
*t
,
5473 const st_src_reg
*in_offset
, int idx
)
5475 struct tgsi_texture_offset offset
;
5476 struct ureg_src imm_src
;
5477 struct ureg_dst dst
;
5480 switch (in_offset
->file
) {
5481 case PROGRAM_IMMEDIATE
:
5482 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
5483 imm_src
= t
->immediates
[in_offset
->index
];
5485 offset
.File
= imm_src
.File
;
5486 offset
.Index
= imm_src
.Index
;
5487 offset
.SwizzleX
= imm_src
.SwizzleX
;
5488 offset
.SwizzleY
= imm_src
.SwizzleY
;
5489 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
5492 case PROGRAM_TEMPORARY
:
5493 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
5494 offset
.File
= imm_src
.File
;
5495 offset
.Index
= imm_src
.Index
;
5496 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5497 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5498 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5502 array
= in_offset
->index
>> 16;
5505 assert(array
< (int)t
->num_temp_arrays
);
5507 dst
= t
->arrays
[array
];
5508 offset
.File
= dst
.File
;
5509 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
5510 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5511 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5512 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5522 compile_tgsi_instruction(struct st_translate
*t
,
5523 const glsl_to_tgsi_instruction
*inst
)
5525 struct ureg_program
*ureg
= t
->ureg
;
5527 struct ureg_dst dst
[2];
5528 struct ureg_src src
[4];
5529 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5533 unsigned tex_target
;
5535 num_dst
= num_inst_dst_regs(inst
);
5536 num_src
= num_inst_src_regs(inst
);
5538 for (i
= 0; i
< num_dst
; i
++)
5539 dst
[i
] = translate_dst(t
,
5543 for (i
= 0; i
< num_src
; i
++)
5544 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5547 case TGSI_OPCODE_BGNLOOP
:
5548 case TGSI_OPCODE_CAL
:
5549 case TGSI_OPCODE_ELSE
:
5550 case TGSI_OPCODE_ENDLOOP
:
5551 case TGSI_OPCODE_IF
:
5552 case TGSI_OPCODE_UIF
:
5553 assert(num_dst
== 0);
5554 ureg_label_insn(ureg
,
5558 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5561 case TGSI_OPCODE_TEX
:
5562 case TGSI_OPCODE_TXB
:
5563 case TGSI_OPCODE_TXD
:
5564 case TGSI_OPCODE_TXL
:
5565 case TGSI_OPCODE_TXP
:
5566 case TGSI_OPCODE_TXQ
:
5567 case TGSI_OPCODE_TXQS
:
5568 case TGSI_OPCODE_TXF
:
5569 case TGSI_OPCODE_TEX2
:
5570 case TGSI_OPCODE_TXB2
:
5571 case TGSI_OPCODE_TXL2
:
5572 case TGSI_OPCODE_TG4
:
5573 case TGSI_OPCODE_LODQ
:
5574 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5575 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5576 if (inst
->sampler
.reladdr
)
5578 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5580 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5581 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5583 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5589 texoffsets
, inst
->tex_offset_num_offset
,
5593 case TGSI_OPCODE_RESQ
:
5594 case TGSI_OPCODE_LOAD
:
5595 case TGSI_OPCODE_ATOMUADD
:
5596 case TGSI_OPCODE_ATOMXCHG
:
5597 case TGSI_OPCODE_ATOMCAS
:
5598 case TGSI_OPCODE_ATOMAND
:
5599 case TGSI_OPCODE_ATOMOR
:
5600 case TGSI_OPCODE_ATOMXOR
:
5601 case TGSI_OPCODE_ATOMUMIN
:
5602 case TGSI_OPCODE_ATOMUMAX
:
5603 case TGSI_OPCODE_ATOMIMIN
:
5604 case TGSI_OPCODE_ATOMIMAX
:
5605 for (i
= num_src
- 1; i
>= 0; i
--)
5606 src
[i
+ 1] = src
[i
];
5608 if (inst
->buffer
.file
== PROGRAM_MEMORY
)
5609 src
[0] = t
->shared_memory
;
5610 else if (inst
->buffer
.file
== PROGRAM_BUFFER
)
5611 src
[0] = t
->buffers
[inst
->buffer
.index
];
5613 src
[0] = t
->images
[inst
->buffer
.index
];
5614 if (inst
->buffer
.reladdr
)
5615 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5616 assert(src
[0].File
!= TGSI_FILE_NULL
);
5617 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5618 inst
->buffer_access
);
5621 case TGSI_OPCODE_STORE
:
5622 if (inst
->buffer
.file
== PROGRAM_MEMORY
)
5623 dst
[0] = ureg_dst(t
->shared_memory
);
5624 else if (inst
->buffer
.file
== PROGRAM_BUFFER
)
5625 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5627 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5628 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5629 if (inst
->buffer
.reladdr
)
5630 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5631 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5632 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5633 inst
->buffer_access
);
5636 case TGSI_OPCODE_SCS
:
5637 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5638 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5651 * Emit the TGSI instructions for inverting and adjusting WPOS.
5652 * This code is unavoidable because it also depends on whether
5653 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5656 emit_wpos_adjustment(struct gl_context
*ctx
,
5657 struct st_translate
*t
,
5658 int wpos_transform_const
,
5660 GLfloat adjX
, GLfloat adjY
[2])
5662 struct ureg_program
*ureg
= t
->ureg
;
5664 assert(wpos_transform_const
>= 0);
5666 /* Fragment program uses fragment position input.
5667 * Need to replace instances of INPUT[WPOS] with temp T
5668 * where T = INPUT[WPOS] is inverted by Y.
5670 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5671 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5672 struct ureg_src
*wpos
=
5673 ctx
->Const
.GLSLFragCoordIsSysVal
?
5674 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5675 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5676 struct ureg_src wpos_input
= *wpos
;
5678 /* First, apply the coordinate shift: */
5679 if (adjX
|| adjY
[0] || adjY
[1]) {
5680 if (adjY
[0] != adjY
[1]) {
5681 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5682 * depending on whether inversion is actually going to be applied
5683 * or not, which is determined by testing against the inversion
5684 * state variable used below, which will be either +1 or -1.
5686 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5688 ureg_CMP(ureg
, adj_temp
,
5689 ureg_scalar(wpostrans
, invert
? 2 : 0),
5690 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5691 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5692 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5694 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5695 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5697 wpos_input
= ureg_src(wpos_temp
);
5699 /* MOV wpos_temp, input[wpos]
5701 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5704 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5705 * inversion/identity, or the other way around if we're drawing to an FBO.
5708 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5711 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5713 ureg_scalar(wpostrans
, 0),
5714 ureg_scalar(wpostrans
, 1));
5716 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5719 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5721 ureg_scalar(wpostrans
, 2),
5722 ureg_scalar(wpostrans
, 3));
5725 /* Use wpos_temp as position input from here on:
5727 *wpos
= ureg_src(wpos_temp
);
5732 * Emit fragment position/ooordinate code.
5735 emit_wpos(struct st_context
*st
,
5736 struct st_translate
*t
,
5737 const struct gl_program
*program
,
5738 struct ureg_program
*ureg
,
5739 int wpos_transform_const
)
5741 const struct gl_fragment_program
*fp
=
5742 (const struct gl_fragment_program
*) program
;
5743 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5744 GLfloat adjX
= 0.0f
;
5745 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5746 boolean invert
= FALSE
;
5748 /* Query the pixel center conventions supported by the pipe driver and set
5749 * adjX, adjY to help out if it cannot handle the requested one internally.
5751 * The bias of the y-coordinate depends on whether y-inversion takes place
5752 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5753 * drawing to an FBO (causes additional inversion), and whether the the pipe
5754 * driver origin and the requested origin differ (the latter condition is
5755 * stored in the 'invert' variable).
5757 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5759 * center shift only:
5764 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5765 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5766 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5767 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5769 * inversion and center shift:
5770 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5771 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5772 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5773 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5775 if (fp
->OriginUpperLeft
) {
5776 /* Fragment shader wants origin in upper-left */
5777 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5778 /* the driver supports upper-left origin */
5780 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5781 /* the driver supports lower-left origin, need to invert Y */
5782 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5783 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5790 /* Fragment shader wants origin in lower-left */
5791 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5792 /* the driver supports lower-left origin */
5793 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5794 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5795 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5796 /* the driver supports upper-left origin, need to invert Y */
5802 if (fp
->PixelCenterInteger
) {
5803 /* Fragment shader wants pixel center integer */
5804 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5805 /* the driver supports pixel center integer */
5807 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5808 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5810 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5811 /* the driver supports pixel center half integer, need to bias X,Y */
5820 /* Fragment shader wants pixel center half integer */
5821 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5822 /* the driver supports pixel center half integer */
5824 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5825 /* the driver supports pixel center integer, need to bias X,Y */
5826 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5827 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5828 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5834 /* we invert after adjustment so that we avoid the MOV to temporary,
5835 * and reuse the adjustment ADD instead */
5836 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5840 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5841 * TGSI uses +1 for front, -1 for back.
5842 * This function converts the TGSI value to the GL value. Simply clamping/
5843 * saturating the value to [0,1] does the job.
5846 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5848 struct ureg_program
*ureg
= t
->ureg
;
5849 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5850 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5852 if (ctx
->Const
.NativeIntegers
) {
5853 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5856 /* MOV_SAT face_temp, input[face] */
5857 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5860 /* Use face_temp as face input from here on: */
5861 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5865 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5866 unsigned *array_id
, unsigned *array_size
)
5870 for (i
= 0; i
< count
; i
++) {
5871 struct array_decl
*decl
= &arrays
[i
];
5873 if (attr
== decl
->mesa_index
) {
5874 *array_id
= decl
->array_id
;
5875 *array_size
= decl
->array_size
;
5876 assert(*array_size
);
5884 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5885 * \param program the program to translate
5886 * \param numInputs number of input registers used
5887 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5889 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5890 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5892 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5893 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5894 * \param numOutputs number of output registers used
5895 * \param outputMapping maps Mesa fragment program outputs to TGSI
5897 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5898 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5901 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5903 extern "C" enum pipe_error
5904 st_translate_program(
5905 struct gl_context
*ctx
,
5907 struct ureg_program
*ureg
,
5908 glsl_to_tgsi_visitor
*program
,
5909 const struct gl_program
*proginfo
,
5911 const GLuint inputMapping
[],
5912 const GLuint inputSlotToAttr
[],
5913 const ubyte inputSemanticName
[],
5914 const ubyte inputSemanticIndex
[],
5915 const GLuint interpMode
[],
5916 const GLuint interpLocation
[],
5918 const GLuint outputMapping
[],
5919 const GLuint outputSlotToAttr
[],
5920 const ubyte outputSemanticName
[],
5921 const ubyte outputSemanticIndex
[])
5923 struct st_translate
*t
;
5925 struct gl_program_constants
*frag_const
=
5926 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
5927 enum pipe_error ret
= PIPE_OK
;
5929 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5930 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5932 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5933 TGSI_SEMANTIC_FACE
);
5934 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5935 TGSI_SEMANTIC_VERTEXID
);
5936 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5937 TGSI_SEMANTIC_INSTANCEID
);
5938 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5939 TGSI_SEMANTIC_SAMPLEID
);
5940 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5941 TGSI_SEMANTIC_SAMPLEPOS
);
5942 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5943 TGSI_SEMANTIC_SAMPLEMASK
);
5944 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5945 TGSI_SEMANTIC_INVOCATIONID
);
5946 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5947 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5948 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5949 TGSI_SEMANTIC_BASEVERTEX
);
5950 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5951 TGSI_SEMANTIC_TESSCOORD
);
5952 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_HELPER_INVOCATION
] ==
5953 TGSI_SEMANTIC_HELPER_INVOCATION
);
5954 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
] ==
5955 TGSI_SEMANTIC_THREAD_ID
);
5956 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_WORK_GROUP_ID
] ==
5957 TGSI_SEMANTIC_BLOCK_ID
);
5958 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_NUM_WORK_GROUPS
] ==
5959 TGSI_SEMANTIC_GRID_SIZE
);
5961 t
= CALLOC_STRUCT(st_translate
);
5963 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5967 t
->procType
= procType
;
5968 t
->inputMapping
= inputMapping
;
5969 t
->outputMapping
= outputMapping
;
5971 t
->num_temp_arrays
= program
->next_array
;
5972 if (t
->num_temp_arrays
)
5973 t
->arrays
= (struct ureg_dst
*)
5974 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5977 * Declare input attributes.
5980 case TGSI_PROCESSOR_FRAGMENT
:
5981 for (i
= 0; i
< numInputs
; i
++) {
5982 unsigned array_id
= 0;
5983 unsigned array_size
;
5985 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5986 program
->num_input_arrays
, &array_id
, &array_size
)) {
5987 /* We've found an array. Declare it so. */
5988 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5989 inputSemanticName
[i
], inputSemanticIndex
[i
],
5990 interpMode
[i
], 0, interpLocation
[i
],
5991 array_id
, array_size
);
5992 i
+= array_size
- 1;
5995 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5996 inputSemanticName
[i
], inputSemanticIndex
[i
],
5997 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
6001 case TGSI_PROCESSOR_GEOMETRY
:
6002 case TGSI_PROCESSOR_TESS_EVAL
:
6003 case TGSI_PROCESSOR_TESS_CTRL
:
6004 for (i
= 0; i
< numInputs
; i
++) {
6005 unsigned array_id
= 0;
6006 unsigned array_size
;
6008 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6009 program
->num_input_arrays
, &array_id
, &array_size
)) {
6010 /* We've found an array. Declare it so. */
6011 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6012 inputSemanticIndex
[i
],
6013 array_id
, array_size
);
6014 i
+= array_size
- 1;
6017 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6018 inputSemanticIndex
[i
], 0, 1);
6022 case TGSI_PROCESSOR_VERTEX
:
6023 for (i
= 0; i
< numInputs
; i
++) {
6024 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6027 case TGSI_PROCESSOR_COMPUTE
:
6034 * Declare output attributes.
6037 case TGSI_PROCESSOR_FRAGMENT
:
6038 case TGSI_PROCESSOR_COMPUTE
:
6040 case TGSI_PROCESSOR_GEOMETRY
:
6041 case TGSI_PROCESSOR_TESS_EVAL
:
6042 case TGSI_PROCESSOR_TESS_CTRL
:
6043 case TGSI_PROCESSOR_VERTEX
:
6044 for (i
= 0; i
< numOutputs
; i
++) {
6045 unsigned array_id
= 0;
6046 unsigned array_size
;
6048 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
6049 program
->num_output_arrays
, &array_id
, &array_size
)) {
6050 /* We've found an array. Declare it so. */
6051 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
6052 outputSemanticName
[i
],
6053 outputSemanticIndex
[i
],
6054 array_id
, array_size
);
6055 i
+= array_size
- 1;
6058 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6059 outputSemanticName
[i
],
6060 outputSemanticIndex
[i
]);
6068 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
6069 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6070 /* Must do this after setting up t->inputs. */
6071 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6072 program
->wpos_transform_const
);
6075 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6076 emit_face_var(ctx
, t
);
6078 for (i
= 0; i
< numOutputs
; i
++) {
6079 switch (outputSemanticName
[i
]) {
6080 case TGSI_SEMANTIC_POSITION
:
6081 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6082 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6083 outputSemanticIndex
[i
]);
6084 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6086 case TGSI_SEMANTIC_STENCIL
:
6087 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6088 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6089 outputSemanticIndex
[i
]);
6090 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6092 case TGSI_SEMANTIC_COLOR
:
6093 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6094 TGSI_SEMANTIC_COLOR
,
6095 outputSemanticIndex
[i
]);
6097 case TGSI_SEMANTIC_SAMPLEMASK
:
6098 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6099 TGSI_SEMANTIC_SAMPLEMASK
,
6100 outputSemanticIndex
[i
]);
6101 /* TODO: If we ever support more than 32 samples, this will have
6102 * to become an array.
6104 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6107 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6108 ret
= PIPE_ERROR_BAD_INPUT
;
6113 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
6114 for (i
= 0; i
< numOutputs
; i
++) {
6115 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6116 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6118 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6119 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6120 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6125 /* Declare address register.
6127 if (program
->num_address_regs
> 0) {
6128 assert(program
->num_address_regs
<= 3);
6129 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6130 t
->address
[i
] = ureg_DECL_address(ureg
);
6133 /* Declare misc input registers
6136 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6138 for (i
= 0; sysInputs
; i
++) {
6139 if (sysInputs
& (1 << i
)) {
6140 unsigned semName
= _mesa_sysval_to_semantic
[i
];
6142 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6144 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6145 semName
== TGSI_SEMANTIC_VERTEXID
) {
6146 /* From Gallium perspective, these system values are always
6147 * integer, and require native integer support. However, if
6148 * native integer is supported on the vertex stage but not the
6149 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6150 * assumes these system values are floats. To resolve the
6151 * inconsistency, we insert a U2F.
6153 struct st_context
*st
= st_context(ctx
);
6154 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6155 assert(procType
== TGSI_PROCESSOR_VERTEX
);
6156 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6158 if (!ctx
->Const
.NativeIntegers
) {
6159 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6160 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6161 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6165 if (procType
== TGSI_PROCESSOR_FRAGMENT
&&
6166 semName
== TGSI_SEMANTIC_POSITION
)
6167 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6168 program
->wpos_transform_const
);
6170 sysInputs
&= ~(1 << i
);
6175 t
->array_sizes
= program
->array_sizes
;
6176 t
->input_arrays
= program
->input_arrays
;
6177 t
->output_arrays
= program
->output_arrays
;
6179 /* Emit constants and uniforms. TGSI uses a single index space for these,
6180 * so we put all the translated regs in t->constants.
6182 if (proginfo
->Parameters
) {
6183 t
->constants
= (struct ureg_src
*)
6184 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6185 if (t
->constants
== NULL
) {
6186 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6189 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6191 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6192 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6193 case PROGRAM_STATE_VAR
:
6194 case PROGRAM_UNIFORM
:
6195 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6198 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6199 * addressing of the const buffer.
6200 * FIXME: Be smarter and recognize param arrays:
6201 * indirect addressing is only valid within the referenced
6204 case PROGRAM_CONSTANT
:
6205 if (program
->indirect_addr_consts
)
6206 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6208 t
->constants
[i
] = emit_immediate(t
,
6209 proginfo
->Parameters
->ParameterValues
[i
],
6210 proginfo
->Parameters
->Parameters
[i
].DataType
,
6219 if (program
->shader
) {
6220 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6222 for (i
= 0; i
< num_ubos
; i
++) {
6223 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6224 unsigned num_const_vecs
= (size
+ 15) / 16;
6225 unsigned first
, last
;
6226 assert(num_const_vecs
> 0);
6228 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6229 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6233 /* Emit immediate values.
6235 t
->immediates
= (struct ureg_src
*)
6236 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6237 if (t
->immediates
== NULL
) {
6238 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6241 t
->num_immediates
= program
->num_immediates
;
6244 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6245 assert(i
< program
->num_immediates
);
6246 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6248 assert(i
== program
->num_immediates
);
6250 /* texture samplers */
6251 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6252 if (program
->samplers_used
& (1 << i
)) {
6255 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6257 switch (program
->sampler_types
[i
]) {
6259 type
= TGSI_RETURN_TYPE_SINT
;
6261 case GLSL_TYPE_UINT
:
6262 type
= TGSI_RETURN_TYPE_UINT
;
6264 case GLSL_TYPE_FLOAT
:
6265 type
= TGSI_RETURN_TYPE_FLOAT
;
6268 unreachable("not reached");
6271 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6272 type
, type
, type
, type
);
6276 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6277 if (program
->buffers_used
& (1 << i
)) {
6278 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6282 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6284 if (program
->buffers_used
& (1 << i
)) {
6285 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6289 if (program
->use_shared_memory
)
6290 t
->shared_memory
= ureg_DECL_shared_memory(ureg
);
6292 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6293 if (program
->images_used
& (1 << i
)) {
6294 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6295 program
->image_targets
[i
],
6296 program
->image_formats
[i
],
6301 /* Emit each instruction in turn:
6303 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6304 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6305 compile_tgsi_instruction(t
, inst
);
6308 /* Fix up all emitted labels:
6310 for (i
= 0; i
< t
->labels_count
; i
++) {
6311 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6312 t
->insn
[t
->labels
[i
].branch_target
]);
6322 t
->num_constants
= 0;
6323 free(t
->immediates
);
6324 t
->num_immediates
= 0;
6327 debug_printf("%s: translate error flag set\n", __func__
);
6335 /* ----------------------------- End TGSI code ------------------------------ */
6339 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6340 * generating Mesa IR.
6342 static struct gl_program
*
6343 get_mesa_program(struct gl_context
*ctx
,
6344 struct gl_shader_program
*shader_program
,
6345 struct gl_shader
*shader
)
6347 glsl_to_tgsi_visitor
* v
;
6348 struct gl_program
*prog
;
6349 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6351 struct gl_shader_compiler_options
*options
=
6352 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
6353 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6354 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6356 validate_ir_tree(shader
->ir
);
6358 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6361 prog
->Parameters
= _mesa_new_parameter_list();
6362 v
= new glsl_to_tgsi_visitor();
6365 v
->shader_program
= shader_program
;
6367 v
->options
= options
;
6368 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6369 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6371 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6372 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6373 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6374 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6376 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6377 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6380 /* Remove reads from output registers. */
6381 lower_output_reads(shader
->Stage
, shader
->ir
);
6383 /* Emit intermediate IR for main(). */
6384 visit_exec_list(shader
->ir
, v
);
6386 /* Now emit bodies for any functions that were used. */
6388 progress
= GL_FALSE
;
6390 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6391 if (!entry
->bgn_inst
) {
6392 v
->current_function
= entry
;
6394 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6395 entry
->bgn_inst
->function
= entry
;
6397 visit_exec_list(&entry
->sig
->body
, v
);
6399 glsl_to_tgsi_instruction
*last
;
6400 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6401 if (last
->op
!= TGSI_OPCODE_RET
)
6402 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6404 glsl_to_tgsi_instruction
*end
;
6405 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6406 end
->function
= entry
;
6414 /* Print out some information (for debugging purposes) used by the
6415 * optimization passes. */
6418 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6419 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6420 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6421 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6423 for (i
= 0; i
< v
->next_temp
; i
++) {
6424 first_writes
[i
] = -1;
6425 first_reads
[i
] = -1;
6426 last_writes
[i
] = -1;
6429 v
->get_first_temp_read(first_reads
);
6430 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6431 v
->get_last_temp_write(last_writes
);
6432 for (i
= 0; i
< v
->next_temp
; i
++)
6433 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6437 ralloc_free(first_writes
);
6438 ralloc_free(first_reads
);
6439 ralloc_free(last_writes
);
6440 ralloc_free(last_reads
);
6444 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6447 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
6448 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
6449 v
->copy_propagate();
6451 while (v
->eliminate_dead_code());
6453 v
->merge_two_dsts();
6454 v
->merge_registers();
6455 v
->renumber_registers();
6457 /* Write the END instruction. */
6458 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6460 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6462 _mesa_log("GLSL IR for linked %s program %d:\n",
6463 _mesa_shader_stage_to_string(shader
->Stage
),
6464 shader_program
->Name
);
6465 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6469 prog
->Instructions
= NULL
;
6470 prog
->NumInstructions
= 0;
6472 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6473 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
6474 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
6475 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
6476 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
6477 count_resources(v
, prog
);
6479 /* The GLSL IR won't be needed anymore. */
6480 ralloc_free(shader
->ir
);
6483 /* This must be done before the uniform storage is associated. */
6484 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
6485 (prog
->InputsRead
& VARYING_BIT_POS
||
6486 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6487 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6488 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6491 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6492 wposTransformState
);
6495 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6497 /* Avoid reallocation of the program parameter list, because the uniform
6498 * storage is only associated with the original parameter list.
6499 * This should be enough for Bitmap and DrawPixels constants.
6501 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6503 /* This has to be done last. Any operation the can cause
6504 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6505 * program constant) has to happen before creating this linkage.
6507 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6508 if (!shader_program
->LinkStatus
) {
6509 free_glsl_to_tgsi_visitor(v
);
6513 struct st_vertex_program
*stvp
;
6514 struct st_fragment_program
*stfp
;
6515 struct st_geometry_program
*stgp
;
6516 struct st_tessctrl_program
*sttcp
;
6517 struct st_tesseval_program
*sttep
;
6518 struct st_compute_program
*stcp
;
6520 switch (shader
->Type
) {
6521 case GL_VERTEX_SHADER
:
6522 stvp
= (struct st_vertex_program
*)prog
;
6523 stvp
->glsl_to_tgsi
= v
;
6525 case GL_FRAGMENT_SHADER
:
6526 stfp
= (struct st_fragment_program
*)prog
;
6527 stfp
->glsl_to_tgsi
= v
;
6529 case GL_GEOMETRY_SHADER
:
6530 stgp
= (struct st_geometry_program
*)prog
;
6531 stgp
->glsl_to_tgsi
= v
;
6533 case GL_TESS_CONTROL_SHADER
:
6534 sttcp
= (struct st_tessctrl_program
*)prog
;
6535 sttcp
->glsl_to_tgsi
= v
;
6537 case GL_TESS_EVALUATION_SHADER
:
6538 sttep
= (struct st_tesseval_program
*)prog
;
6539 sttep
->glsl_to_tgsi
= v
;
6541 case GL_COMPUTE_SHADER
:
6542 stcp
= (struct st_compute_program
*)prog
;
6543 stcp
->glsl_to_tgsi
= v
;
6546 assert(!"should not be reached");
6556 st_dump_program_for_shader_db(struct gl_context
*ctx
,
6557 struct gl_shader_program
*prog
)
6559 /* Dump only successfully compiled and linked shaders to the specified
6560 * file. This is for shader-db.
6562 * These options allow some pre-processing of shaders while dumping,
6563 * because some apps have ill-formed shaders.
6565 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
6566 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
6568 if (dump_filename
&& prog
->Name
!= 0) {
6569 FILE *f
= fopen(dump_filename
, "a");
6572 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
6573 const struct gl_shader
*sh
= prog
->Shaders
[i
];
6575 bool skip_version
= false;
6580 source
= sh
->Source
;
6582 /* This string mustn't be changed. shader-db uses it to find
6583 * where the shader begins.
6585 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
6586 _mesa_shader_stage_to_string(sh
->Stage
),
6589 /* Dump the forced version if set. */
6590 if (ctx
->Const
.ForceGLSLVersion
) {
6591 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
6592 skip_version
= true;
6595 /* Insert directives (optional). */
6596 if (insert_directives
) {
6597 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
6598 fprintf(f
, "#version %i\n", prog
->Version
);
6599 fprintf(f
, "%s\n", insert_directives
);
6600 skip_version
= true;
6603 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
6604 const char *next_line
= strstr(source
, "\n");
6607 source
= next_line
+ 1;
6612 fprintf(f
, "%s", source
);
6622 * Called via ctx->Driver.LinkShader()
6623 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6624 * with code lowering and other optimizations.
6627 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6629 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6630 assert(prog
->LinkStatus
);
6632 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6633 if (prog
->_LinkedShaders
[i
] == NULL
)
6637 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6638 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6639 const struct gl_shader_compiler_options
*options
=
6640 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6641 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6642 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6643 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6644 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6645 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6647 /* If there are forms of indirect addressing that the driver
6648 * cannot handle, perform the lowering pass.
6650 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6651 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6652 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6653 options
->EmitNoIndirectInput
,
6654 options
->EmitNoIndirectOutput
,
6655 options
->EmitNoIndirectTemp
,
6656 options
->EmitNoIndirectUniform
);
6659 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6660 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6661 LOWER_UNPACK_SNORM_2x16
|
6662 LOWER_PACK_UNORM_2x16
|
6663 LOWER_UNPACK_UNORM_2x16
|
6664 LOWER_PACK_SNORM_4x8
|
6665 LOWER_UNPACK_SNORM_4x8
|
6666 LOWER_UNPACK_UNORM_4x8
|
6667 LOWER_PACK_UNORM_4x8
;
6669 if (ctx
->Extensions
.ARB_gpu_shader5
)
6670 lower_inst
|= LOWER_PACK_USE_BFI
|
6672 if (!ctx
->st
->has_half_float_packing
)
6673 lower_inst
|= LOWER_PACK_HALF_2x16
|
6674 LOWER_UNPACK_HALF_2x16
;
6676 lower_packing_builtins(ir
, lower_inst
);
6679 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6680 lower_offset_arrays(ir
);
6681 do_mat_op_to_vec(ir
);
6682 lower_instructions(ir
,
6688 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6691 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6692 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6693 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6694 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6696 do_vec_index_to_cond_assign(ir
);
6697 lower_vector_insert(ir
, true);
6698 lower_quadop_vector(ir
, false);
6700 if (options
->MaxIfDepth
== 0) {
6707 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6709 progress
= do_common_optimization(ir
, true, true, options
,
6710 ctx
->Const
.NativeIntegers
)
6713 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6717 validate_ir_tree(ir
);
6720 build_program_resource_list(prog
);
6722 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6723 struct gl_program
*linked_prog
;
6725 if (prog
->_LinkedShaders
[i
] == NULL
)
6728 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6731 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6733 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6734 _mesa_shader_stage_to_program(i
),
6736 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6738 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6743 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6746 st_dump_program_for_shader_db(ctx
, prog
);
6751 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6752 const GLuint outputMapping
[],
6753 struct pipe_stream_output_info
*so
)
6756 struct gl_transform_feedback_info
*info
=
6757 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6759 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6760 so
->output
[i
].register_index
=
6761 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6762 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6763 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6764 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6765 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6766 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6769 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6770 so
->stride
[i
] = info
->BufferStride
[i
];
6772 so
->num_outputs
= info
->NumOutputs
;