2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
59 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
60 (1 << PROGRAM_CONSTANT) | \
61 (1 << PROGRAM_UNIFORM))
63 #define MAX_GLSL_TEXTURE_OFFSET 4
68 static int swizzle_for_size(int size
);
70 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
72 unsigned num_elements
= 4;
75 type
= type
->without_array();
76 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
77 num_elements
= type
->vector_elements
;
80 int swizzle
= swizzle_for_size(num_elements
);
81 assert(num_elements
+ component
<= 4);
83 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
88 * This struct is a corresponding struct to TGSI ureg_src.
92 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
93 int component
= 0, unsigned array_id
= 0)
95 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
98 this->swizzle
= swizzle_for_type(type
, component
);
101 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
102 this->reladdr
= NULL
;
103 this->reladdr2
= NULL
;
104 this->has_index2
= false;
105 this->double_reg2
= false;
106 this->array_id
= array_id
;
107 this->is_double_vertex_input
= false;
110 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
112 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
117 this->swizzle
= SWIZZLE_XYZW
;
119 this->reladdr
= NULL
;
120 this->reladdr2
= NULL
;
121 this->has_index2
= false;
122 this->double_reg2
= false;
124 this->is_double_vertex_input
= false;
127 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
129 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
133 this->index2D
= index2D
;
134 this->swizzle
= SWIZZLE_XYZW
;
136 this->reladdr
= NULL
;
137 this->reladdr2
= NULL
;
138 this->has_index2
= false;
139 this->double_reg2
= false;
141 this->is_double_vertex_input
= false;
146 this->type
= GLSL_TYPE_ERROR
;
147 this->file
= PROGRAM_UNDEFINED
;
152 this->reladdr
= NULL
;
153 this->reladdr2
= NULL
;
154 this->has_index2
= false;
155 this->double_reg2
= false;
157 this->is_double_vertex_input
= false;
160 explicit st_src_reg(st_dst_reg reg
);
162 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
164 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
165 int negate
:4; /**< NEGATE_XYZW mask from mesa */
166 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
167 unsigned has_index2
:1;
168 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
170 * Is this the second half of a double register pair?
171 * currently used for input mapping only.
173 unsigned double_reg2
:1;
174 unsigned is_double_vertex_input
:1;
175 unsigned array_id
:10;
177 /** Register index should be offset by the integer in this reg. */
179 st_src_reg
*reladdr2
;
184 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
186 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
190 this->writemask
= writemask
;
191 this->reladdr
= NULL
;
192 this->reladdr2
= NULL
;
193 this->has_index2
= false;
198 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
200 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
204 this->writemask
= writemask
;
205 this->reladdr
= NULL
;
206 this->reladdr2
= NULL
;
207 this->has_index2
= false;
214 this->type
= GLSL_TYPE_ERROR
;
215 this->file
= PROGRAM_UNDEFINED
;
219 this->reladdr
= NULL
;
220 this->reladdr2
= NULL
;
221 this->has_index2
= false;
225 explicit st_dst_reg(st_src_reg reg
);
227 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
229 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
230 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
231 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
232 unsigned has_index2
:1;
233 unsigned array_id
:10;
235 /** Register index should be offset by the integer in this reg. */
237 st_src_reg
*reladdr2
;
240 st_src_reg::st_src_reg(st_dst_reg reg
)
242 this->type
= reg
.type
;
243 this->file
= reg
.file
;
244 this->index
= reg
.index
;
245 this->swizzle
= SWIZZLE_XYZW
;
247 this->reladdr
= reg
.reladdr
;
248 this->index2D
= reg
.index2D
;
249 this->reladdr2
= reg
.reladdr2
;
250 this->has_index2
= reg
.has_index2
;
251 this->double_reg2
= false;
252 this->array_id
= reg
.array_id
;
253 this->is_double_vertex_input
= false;
256 st_dst_reg::st_dst_reg(st_src_reg reg
)
258 this->type
= reg
.type
;
259 this->file
= reg
.file
;
260 this->index
= reg
.index
;
261 this->writemask
= WRITEMASK_XYZW
;
262 this->reladdr
= reg
.reladdr
;
263 this->index2D
= reg
.index2D
;
264 this->reladdr2
= reg
.reladdr2
;
265 this->has_index2
= reg
.has_index2
;
266 this->array_id
= reg
.array_id
;
269 class glsl_to_tgsi_instruction
: public exec_node
{
271 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
275 st_src_reg resource
; /**< sampler or buffer register */
276 st_src_reg
*tex_offsets
;
278 /** Pointer to the ir source this tree came from for debugging */
281 unsigned op
:8; /**< TGSI opcode */
283 unsigned is_64bit_expanded
:1;
284 unsigned sampler_base
:5;
285 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
286 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
287 glsl_base_type tex_type
:4;
288 unsigned tex_shadow
:1;
289 unsigned image_format
:9;
290 unsigned tex_offset_num_offset
:3;
291 unsigned dead_mask
:4; /**< Used in dead code elimination */
292 unsigned buffer_access
:3; /**< buffer access type */
294 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
295 const struct tgsi_opcode_info
*info
;
298 class variable_storage
: public exec_node
{
300 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
301 unsigned array_id
= 0)
302 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
304 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
307 gl_register_file file
;
310 /* Explicit component location. This is given in terms of the GLSL-style
311 * swizzles where each double is a single component, i.e. for 64-bit types
312 * it can only be 0 or 1.
315 ir_variable
*var
; /* variable that maps to this, if any */
319 class immediate_storage
: public exec_node
{
321 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
323 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
324 this->size32
= size32
;
328 /* doubles are stored across 2 gl_constant_values */
329 gl_constant_value values
[4];
330 int size32
; /**< Number of 32-bit components (1-4) */
331 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
334 class function_entry
: public exec_node
{
336 ir_function_signature
*sig
;
339 * identifier of this function signature used by the program.
341 * At the point that TGSI instructions for function calls are
342 * generated, we don't know the address of the first instruction of
343 * the function body. So we make the BranchTarget that is called a
344 * small integer and rewrite them during set_branchtargets().
349 * Pointer to first instruction of the function body.
351 * Set during function body emits after main() is processed.
353 glsl_to_tgsi_instruction
*bgn_inst
;
356 * Index of the first instruction of the function body in actual TGSI.
358 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
362 /** Storage for the return value. */
363 st_src_reg return_reg
;
366 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
367 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
371 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
373 enum glsl_base_type base_type
;
374 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
377 static struct inout_decl
*
378 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
380 assert(array_id
!= 0);
382 for (unsigned i
= 0; i
< count
; i
++) {
383 struct inout_decl
*decl
= &decls
[i
];
385 if (array_id
== decl
->array_id
) {
393 static enum glsl_base_type
394 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
397 return GLSL_TYPE_ERROR
;
398 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
400 return decl
->base_type
;
401 return GLSL_TYPE_ERROR
;
404 struct rename_reg_pair
{
409 struct glsl_to_tgsi_visitor
: public ir_visitor
{
411 glsl_to_tgsi_visitor();
412 ~glsl_to_tgsi_visitor();
414 function_entry
*current_function
;
416 struct gl_context
*ctx
;
417 struct gl_program
*prog
;
418 struct gl_shader_program
*shader_program
;
419 struct gl_linked_shader
*shader
;
420 struct gl_shader_compiler_options
*options
;
424 unsigned *array_sizes
;
425 unsigned max_num_arrays
;
428 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
430 unsigned num_input_arrays
;
431 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
432 unsigned num_outputs
;
433 unsigned num_output_arrays
;
435 int num_address_regs
;
436 uint32_t samplers_used
;
437 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
438 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
441 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
442 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
443 bool indirect_addr_consts
;
444 int wpos_transform_const
;
447 bool native_integers
;
450 bool use_shared_memory
;
452 variable_storage
*find_variable_storage(ir_variable
*var
);
454 int add_constant(gl_register_file file
, gl_constant_value values
[8],
455 int size
, int datatype
, uint16_t *swizzle_out
);
457 function_entry
*get_function_signature(ir_function_signature
*sig
);
459 st_src_reg
get_temp(const glsl_type
*type
);
460 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
462 st_src_reg
st_src_reg_for_double(double val
);
463 st_src_reg
st_src_reg_for_float(float val
);
464 st_src_reg
st_src_reg_for_int(int val
);
465 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
468 * \name Visit methods
470 * As typical for the visitor pattern, there must be one \c visit method for
471 * each concrete subclass of \c ir_instruction. Virtual base classes within
472 * the hierarchy should not have \c visit methods.
475 virtual void visit(ir_variable
*);
476 virtual void visit(ir_loop
*);
477 virtual void visit(ir_loop_jump
*);
478 virtual void visit(ir_function_signature
*);
479 virtual void visit(ir_function
*);
480 virtual void visit(ir_expression
*);
481 virtual void visit(ir_swizzle
*);
482 virtual void visit(ir_dereference_variable
*);
483 virtual void visit(ir_dereference_array
*);
484 virtual void visit(ir_dereference_record
*);
485 virtual void visit(ir_assignment
*);
486 virtual void visit(ir_constant
*);
487 virtual void visit(ir_call
*);
488 virtual void visit(ir_return
*);
489 virtual void visit(ir_discard
*);
490 virtual void visit(ir_texture
*);
491 virtual void visit(ir_if
*);
492 virtual void visit(ir_emit_vertex
*);
493 virtual void visit(ir_end_primitive
*);
494 virtual void visit(ir_barrier
*);
497 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
499 void visit_atomic_counter_intrinsic(ir_call
*);
500 void visit_ssbo_intrinsic(ir_call
*);
501 void visit_membar_intrinsic(ir_call
*);
502 void visit_shared_intrinsic(ir_call
*);
503 void visit_image_intrinsic(ir_call
*);
507 /** List of variable_storage */
510 /** List of immediate_storage */
511 exec_list immediates
;
512 unsigned num_immediates
;
514 /** List of function_entry */
515 exec_list function_signatures
;
516 int next_signature_id
;
518 /** List of glsl_to_tgsi_instruction */
519 exec_list instructions
;
521 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
522 st_dst_reg dst
= undef_dst
,
523 st_src_reg src0
= undef_src
,
524 st_src_reg src1
= undef_src
,
525 st_src_reg src2
= undef_src
,
526 st_src_reg src3
= undef_src
);
528 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
529 st_dst_reg dst
, st_dst_reg dst1
,
530 st_src_reg src0
= undef_src
,
531 st_src_reg src1
= undef_src
,
532 st_src_reg src2
= undef_src
,
533 st_src_reg src3
= undef_src
);
535 unsigned get_opcode(unsigned op
,
537 st_src_reg src0
, st_src_reg src1
);
540 * Emit the correct dot-product instruction for the type of arguments
542 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
548 void emit_scalar(ir_instruction
*ir
, unsigned op
,
549 st_dst_reg dst
, st_src_reg src0
);
551 void emit_scalar(ir_instruction
*ir
, unsigned op
,
552 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
554 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
556 void get_deref_offsets(ir_dereference
*ir
,
557 unsigned *array_size
,
562 void calc_deref_offsets(ir_dereference
*tail
,
563 unsigned *array_elements
,
565 st_src_reg
*indirect
,
567 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
569 bool try_emit_mad(ir_expression
*ir
,
571 bool try_emit_mad_for_and_not(ir_expression
*ir
,
574 void emit_swz(ir_expression
*ir
);
576 bool process_move_condition(ir_rvalue
*ir
);
578 void simplify_cmp(void);
580 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
581 void get_first_temp_read(int *first_reads
);
582 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
583 void get_last_temp_write(int *last_writes
);
585 void copy_propagate(void);
586 int eliminate_dead_code(void);
588 void merge_two_dsts(void);
589 void merge_registers(void);
590 void renumber_registers(void);
592 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
593 st_dst_reg
*l
, st_src_reg
*r
,
594 st_src_reg
*cond
, bool cond_swap
);
599 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
600 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
601 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
604 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
607 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
611 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
614 prog
->LinkStatus
= GL_FALSE
;
618 swizzle_for_size(int size
)
620 static const int size_swizzles
[4] = {
621 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
622 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
623 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
624 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
627 assert((size
>= 1) && (size
<= 4));
628 return size_swizzles
[size
- 1];
632 is_resource_instruction(unsigned opcode
)
635 case TGSI_OPCODE_RESQ
:
636 case TGSI_OPCODE_LOAD
:
637 case TGSI_OPCODE_ATOMUADD
:
638 case TGSI_OPCODE_ATOMXCHG
:
639 case TGSI_OPCODE_ATOMCAS
:
640 case TGSI_OPCODE_ATOMAND
:
641 case TGSI_OPCODE_ATOMOR
:
642 case TGSI_OPCODE_ATOMXOR
:
643 case TGSI_OPCODE_ATOMUMIN
:
644 case TGSI_OPCODE_ATOMUMAX
:
645 case TGSI_OPCODE_ATOMIMIN
:
646 case TGSI_OPCODE_ATOMIMAX
:
654 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
656 return op
->info
->num_dst
;
660 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
662 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
663 op
->info
->num_src
- 1 : op
->info
->num_src
;
666 glsl_to_tgsi_instruction
*
667 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
668 st_dst_reg dst
, st_dst_reg dst1
,
669 st_src_reg src0
, st_src_reg src1
,
670 st_src_reg src2
, st_src_reg src3
)
672 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
673 int num_reladdr
= 0, i
, j
;
674 bool dst_is_64bit
[2];
676 op
= get_opcode(op
, dst
, src0
, src1
);
678 /* If we have to do relative addressing, we want to load the ARL
679 * reg directly for one of the regs, and preload the other reladdr
680 * sources into temps.
682 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
683 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
684 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
685 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
686 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
687 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
689 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
690 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
691 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
692 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
694 if (dst
.reladdr
|| dst
.reladdr2
) {
696 emit_arl(ir
, address_reg
, *dst
.reladdr
);
698 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
702 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
705 assert(num_reladdr
== 0);
707 /* inst->op has only 8 bits. */
708 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
711 inst
->info
= tgsi_get_opcode_info(op
);
718 inst
->is_64bit_expanded
= false;
721 /* default to float, for paths where this is not initialized
722 * (since 0==UINT which is likely wrong):
724 inst
->tex_type
= GLSL_TYPE_FLOAT
;
726 inst
->function
= NULL
;
728 /* Update indirect addressing status used by TGSI */
729 if (dst
.reladdr
|| dst
.reladdr2
) {
731 case PROGRAM_STATE_VAR
:
732 case PROGRAM_CONSTANT
:
733 case PROGRAM_UNIFORM
:
734 this->indirect_addr_consts
= true;
736 case PROGRAM_IMMEDIATE
:
737 assert(!"immediates should not have indirect addressing");
744 for (i
= 0; i
< 4; i
++) {
745 if(inst
->src
[i
].reladdr
) {
746 switch(inst
->src
[i
].file
) {
747 case PROGRAM_STATE_VAR
:
748 case PROGRAM_CONSTANT
:
749 case PROGRAM_UNIFORM
:
750 this->indirect_addr_consts
= true;
752 case PROGRAM_IMMEDIATE
:
753 assert(!"immediates should not have indirect addressing");
763 * This section contains the double processing.
764 * GLSL just represents doubles as single channel values,
765 * however most HW and TGSI represent doubles as pairs of register channels.
767 * so we have to fixup destination writemask/index and src swizzle/indexes.
768 * dest writemasks need to translate from single channel write mask
769 * to a dual-channel writemask, but also need to modify the index,
770 * if we are touching the Z,W fields in the pre-translated writemask.
772 * src channels have similiar index modifications along with swizzle
773 * changes to we pick the XY, ZW pairs from the correct index.
775 * GLSL [0].x -> TGSI [0].xy
776 * GLSL [0].y -> TGSI [0].zw
777 * GLSL [0].z -> TGSI [1].xy
778 * GLSL [0].w -> TGSI [1].zw
780 for (j
= 0; j
< 2; j
++) {
781 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
782 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
783 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
784 if (glsl_base_type_is_64bit(type
))
785 dst_is_64bit
[j
] = true;
789 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
790 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
791 glsl_to_tgsi_instruction
*dinst
= NULL
;
792 int initial_src_swz
[4], initial_src_idx
[4];
793 int initial_dst_idx
[2], initial_dst_writemask
[2];
794 /* select the writemask for dst0 or dst1 */
795 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
797 /* copy out the writemask, index and swizzles for all src/dsts. */
798 for (j
= 0; j
< 2; j
++) {
799 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
800 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
803 for (j
= 0; j
< 4; j
++) {
804 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
805 initial_src_idx
[j
] = inst
->src
[j
].index
;
809 * scan all the components in the dst writemask
810 * generate an instruction for each of them if required.
815 int i
= u_bit_scan(&writemask
);
817 /* before emitting the instruction, see if we have to adjust store
819 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
820 addr
.file
== PROGRAM_UNDEFINED
) {
821 /* We have to advance the buffer address by 16 */
822 addr
= get_temp(glsl_type::uint_type
);
823 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
824 inst
->src
[0], st_src_reg_for_int(16));
828 /* first time use previous instruction */
832 /* create a new instructions for subsequent attempts */
833 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
838 this->instructions
.push_tail(dinst
);
839 dinst
->is_64bit_expanded
= true;
841 /* modify the destination if we are splitting */
842 for (j
= 0; j
< 2; j
++) {
843 if (dst_is_64bit
[j
]) {
844 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
845 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
847 if (dinst
->op
== TGSI_OPCODE_STORE
) {
848 dinst
->src
[0] = addr
;
850 dinst
->dst
[j
].index
++;
854 /* if we aren't writing to a double, just get the bit of the initial writemask
856 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
860 /* modify the src registers */
861 for (j
= 0; j
< 4; j
++) {
862 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
864 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
865 dinst
->src
[j
].index
= initial_src_idx
[j
];
867 dinst
->src
[j
].double_reg2
= true;
868 dinst
->src
[j
].index
++;
872 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
874 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
877 /* some opcodes are special case in what they use as sources
878 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
879 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
880 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
881 op
== TGSI_OPCODE_DLDEXP
||
882 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
883 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
890 this->instructions
.push_tail(inst
);
897 glsl_to_tgsi_instruction
*
898 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
900 st_src_reg src0
, st_src_reg src1
,
901 st_src_reg src2
, st_src_reg src3
)
903 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
907 * Determines whether to use an integer, unsigned integer, or float opcode
908 * based on the operands and input opcode, then emits the result.
911 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
913 st_src_reg src0
, st_src_reg src1
)
915 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
917 if (op
== TGSI_OPCODE_MOV
)
920 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
921 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
922 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
923 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
925 if (is_resource_instruction(op
))
927 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
928 type
= GLSL_TYPE_DOUBLE
;
929 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
930 type
= GLSL_TYPE_FLOAT
;
931 else if (native_integers
)
932 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
934 #define case5(c, f, i, u, d) \
935 case TGSI_OPCODE_##c: \
936 if (type == GLSL_TYPE_DOUBLE) \
937 op = TGSI_OPCODE_##d; \
938 else if (type == GLSL_TYPE_INT) \
939 op = TGSI_OPCODE_##i; \
940 else if (type == GLSL_TYPE_UINT) \
941 op = TGSI_OPCODE_##u; \
943 op = TGSI_OPCODE_##f; \
946 #define case4(c, f, i, u) \
947 case TGSI_OPCODE_##c: \
948 if (type == GLSL_TYPE_INT) \
949 op = TGSI_OPCODE_##i; \
950 else if (type == GLSL_TYPE_UINT) \
951 op = TGSI_OPCODE_##u; \
953 op = TGSI_OPCODE_##f; \
956 #define case3(f, i, u) case4(f, f, i, u)
957 #define case4d(f, i, u, d) case5(f, f, i, u, d)
958 #define case3fid(f, i, d) case5(f, f, i, i, d)
959 #define case2fi(f, i) case4(f, f, i, i)
960 #define case2iu(i, u) case4(i, LAST, i, u)
962 #define casecomp(c, f, i, u, d) \
963 case TGSI_OPCODE_##c: \
964 if (type == GLSL_TYPE_DOUBLE) \
965 op = TGSI_OPCODE_##d; \
966 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
967 op = TGSI_OPCODE_##i; \
968 else if (type == GLSL_TYPE_UINT) \
969 op = TGSI_OPCODE_##u; \
970 else if (native_integers) \
971 op = TGSI_OPCODE_##f; \
973 op = TGSI_OPCODE_##c; \
977 case3fid(ADD
, UADD
, DADD
);
978 case3fid(MUL
, UMUL
, DMUL
);
979 case3fid(MAD
, UMAD
, DMAD
);
980 case3fid(FMA
, UMAD
, DFMA
);
981 case3(DIV
, IDIV
, UDIV
);
982 case4d(MAX
, IMAX
, UMAX
, DMAX
);
983 case4d(MIN
, IMIN
, UMIN
, DMIN
);
986 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
987 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
988 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
989 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
993 case3fid(SSG
, ISSG
, DSSG
);
994 case3fid(ABS
, IABS
, DABS
);
998 case2iu(IMUL_HI
, UMUL_HI
);
1000 case3fid(SQRT
, SQRT
, DSQRT
);
1002 case3fid(RCP
, RCP
, DRCP
);
1003 case3fid(RSQ
, RSQ
, DRSQ
);
1005 case3fid(FRC
, FRC
, DFRAC
);
1006 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1007 case3fid(CEIL
, CEIL
, DCEIL
);
1008 case3fid(FLR
, FLR
, DFLR
);
1009 case3fid(ROUND
, ROUND
, DROUND
);
1011 case2iu(ATOMIMAX
, ATOMUMAX
);
1012 case2iu(ATOMIMIN
, ATOMUMIN
);
1017 assert(op
!= TGSI_OPCODE_LAST
);
1021 glsl_to_tgsi_instruction
*
1022 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1023 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1026 static const unsigned dot_opcodes
[] = {
1027 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1030 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1034 * Emits TGSI scalar opcodes to produce unique answers across channels.
1036 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1037 * channel determines the result across all channels. So to do a vec4
1038 * of this operation, we want to emit a scalar per source channel used
1039 * to produce dest channels.
1042 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1044 st_src_reg orig_src0
, st_src_reg orig_src1
)
1047 int done_mask
= ~dst
.writemask
;
1049 /* TGSI RCP is a scalar operation splatting results to all channels,
1050 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1053 for (i
= 0; i
< 4; i
++) {
1054 GLuint this_mask
= (1 << i
);
1055 st_src_reg src0
= orig_src0
;
1056 st_src_reg src1
= orig_src1
;
1058 if (done_mask
& this_mask
)
1061 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1062 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1063 for (j
= i
+ 1; j
< 4; j
++) {
1064 /* If there is another enabled component in the destination that is
1065 * derived from the same inputs, generate its value on this pass as
1068 if (!(done_mask
& (1 << j
)) &&
1069 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1070 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1071 this_mask
|= (1 << j
);
1074 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1075 src0_swiz
, src0_swiz
);
1076 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1077 src1_swiz
, src1_swiz
);
1079 dst
.writemask
= this_mask
;
1080 emit_asm(ir
, op
, dst
, src0
, src1
);
1081 done_mask
|= this_mask
;
1086 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1087 st_dst_reg dst
, st_src_reg src0
)
1089 st_src_reg undef
= undef_src
;
1091 undef
.swizzle
= SWIZZLE_XXXX
;
1093 emit_scalar(ir
, op
, dst
, src0
, undef
);
1097 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1098 st_dst_reg dst
, st_src_reg src0
)
1100 int op
= TGSI_OPCODE_ARL
;
1102 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1103 op
= TGSI_OPCODE_UARL
;
1105 assert(dst
.file
== PROGRAM_ADDRESS
);
1106 if (dst
.index
>= this->num_address_regs
)
1107 this->num_address_regs
= dst
.index
+ 1;
1109 emit_asm(NULL
, op
, dst
, src0
);
1113 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1114 gl_constant_value values
[8], int size
, int datatype
,
1115 uint16_t *swizzle_out
)
1117 if (file
== PROGRAM_CONSTANT
) {
1118 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1119 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1120 size
, datatype
, &swizzle
);
1122 *swizzle_out
= swizzle
;
1126 assert(file
== PROGRAM_IMMEDIATE
);
1129 immediate_storage
*entry
;
1130 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1133 /* Search immediate storage to see if we already have an identical
1134 * immediate that we can use instead of adding a duplicate entry.
1136 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1137 immediate_storage
*tmp
= entry
;
1139 for (i
= 0; i
* 4 < size32
; i
++) {
1140 int slot_size
= MIN2(size32
- (i
* 4), 4);
1141 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1143 if (memcmp(tmp
->values
, &values
[i
* 4],
1144 slot_size
* sizeof(gl_constant_value
)))
1147 /* Everything matches, keep going until the full size is matched */
1148 tmp
= (immediate_storage
*)tmp
->next
;
1151 /* The full value matched */
1152 if (i
* 4 >= size32
)
1158 for (i
= 0; i
* 4 < size32
; i
++) {
1159 int slot_size
= MIN2(size32
- (i
* 4), 4);
1160 /* Add this immediate to the list. */
1161 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1162 this->immediates
.push_tail(entry
);
1163 this->num_immediates
++;
1169 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1171 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1172 union gl_constant_value uval
;
1175 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1181 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1183 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1184 union gl_constant_value uval
[2];
1186 memcpy(uval
, &val
, sizeof(uval
));
1187 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1188 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1193 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1195 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1196 union gl_constant_value uval
;
1198 assert(native_integers
);
1201 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1207 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1209 if (native_integers
)
1210 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1211 st_src_reg_for_int(val
);
1213 return st_src_reg_for_float(val
);
1217 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1219 return st_glsl_attrib_type_size(type
, is_vs_input
);
1223 type_size(const struct glsl_type
*type
)
1225 return st_glsl_type_size(type
);
1229 * If the given GLSL type is an array or matrix or a structure containing
1230 * an array/matrix member, return true. Else return false.
1232 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1233 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1234 * we have an array that might be indexed with a variable, we need to use
1235 * the later storage type.
1238 type_has_array_or_matrix(const glsl_type
*type
)
1240 if (type
->is_array() || type
->is_matrix())
1243 if (type
->is_record()) {
1244 for (unsigned i
= 0; i
< type
->length
; i
++) {
1245 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1256 * In the initial pass of codegen, we assign temporary numbers to
1257 * intermediate results. (not SSA -- variable assignments will reuse
1261 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1265 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1269 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1270 if (next_array
>= max_num_arrays
) {
1271 max_num_arrays
+= 32;
1272 array_sizes
= (unsigned*)
1273 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1276 src
.file
= PROGRAM_ARRAY
;
1278 src
.array_id
= next_array
+ 1;
1279 array_sizes
[next_array
] = type_size(type
);
1283 src
.file
= PROGRAM_TEMPORARY
;
1284 src
.index
= next_temp
;
1285 next_temp
+= type_size(type
);
1288 if (type
->is_array() || type
->is_record()) {
1289 src
.swizzle
= SWIZZLE_NOOP
;
1291 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1298 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1301 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1302 if (entry
->var
== var
)
1310 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1312 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1313 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1315 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1316 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1319 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1321 const ir_state_slot
*const slots
= ir
->get_state_slots();
1322 assert(slots
!= NULL
);
1324 /* Check if this statevar's setup in the STATE file exactly
1325 * matches how we'll want to reference it as a
1326 * struct/array/whatever. If not, then we need to move it into
1327 * temporary storage and hope that it'll get copy-propagated
1330 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1331 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1336 variable_storage
*storage
;
1338 if (i
== ir
->get_num_state_slots()) {
1339 /* We'll set the index later. */
1340 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1341 this->variables
.push_tail(storage
);
1345 /* The variable_storage constructor allocates slots based on the size
1346 * of the type. However, this had better match the number of state
1347 * elements that we're going to copy into the new temporary.
1349 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1351 dst
= st_dst_reg(get_temp(ir
->type
));
1353 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1356 this->variables
.push_tail(storage
);
1360 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1361 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1362 (gl_state_index
*)slots
[i
].tokens
);
1364 if (storage
->file
== PROGRAM_STATE_VAR
) {
1365 if (storage
->index
== -1) {
1366 storage
->index
= index
;
1368 assert(index
== storage
->index
+ (int)i
);
1371 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1372 * the data being moved since MOV does not care about the type of
1373 * data it is moving, and we don't want to declare registers with
1374 * array or struct types.
1376 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1377 src
.swizzle
= slots
[i
].swizzle
;
1378 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1379 /* even a float takes up a whole vec4 reg in a struct/array. */
1384 if (storage
->file
== PROGRAM_TEMPORARY
&&
1385 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1386 fail_link(this->shader_program
,
1387 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1388 ir
->name
, dst
.index
- storage
->index
,
1389 type_size(ir
->type
));
1395 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1397 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1399 visit_exec_list(&ir
->body_instructions
, this);
1401 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1405 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1408 case ir_loop_jump::jump_break
:
1409 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1411 case ir_loop_jump::jump_continue
:
1412 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1419 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1426 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1428 /* Ignore function bodies other than main() -- we shouldn't see calls to
1429 * them since they should all be inlined before we get to glsl_to_tgsi.
1431 if (strcmp(ir
->name
, "main") == 0) {
1432 const ir_function_signature
*sig
;
1435 sig
= ir
->matching_signature(NULL
, &empty
, false);
1439 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1446 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1448 int nonmul_operand
= 1 - mul_operand
;
1450 st_dst_reg result_dst
;
1452 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1453 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1456 expr
->operands
[0]->accept(this);
1458 expr
->operands
[1]->accept(this);
1460 ir
->operands
[nonmul_operand
]->accept(this);
1463 this->result
= get_temp(ir
->type
);
1464 result_dst
= st_dst_reg(this->result
);
1465 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1466 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1472 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1474 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1475 * implemented using multiplication, and logical-or is implemented using
1476 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1477 * As result, the logical expression (a & !b) can be rewritten as:
1481 * - (a * 1) - (a * b)
1485 * This final expression can be implemented as a single MAD(a, -b, a)
1489 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1491 const int other_operand
= 1 - try_operand
;
1494 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1495 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1498 ir
->operands
[other_operand
]->accept(this);
1500 expr
->operands
[0]->accept(this);
1503 b
.negate
= ~b
.negate
;
1505 this->result
= get_temp(ir
->type
);
1506 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1512 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1513 st_src_reg
*reg
, int *num_reladdr
)
1515 if (!reg
->reladdr
&& !reg
->reladdr2
)
1518 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1519 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1521 if (*num_reladdr
!= 1) {
1522 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1524 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1532 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1534 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1536 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1538 if (ir
->operation
== ir_binop_add
) {
1539 if (try_emit_mad(ir
, 1))
1541 if (try_emit_mad(ir
, 0))
1545 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1547 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1548 if (try_emit_mad_for_and_not(ir
, 1))
1550 if (try_emit_mad_for_and_not(ir
, 0))
1554 if (ir
->operation
== ir_quadop_vector
)
1555 assert(!"ir_quadop_vector should have been lowered");
1557 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1558 this->result
.file
= PROGRAM_UNDEFINED
;
1559 ir
->operands
[operand
]->accept(this);
1560 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1561 printf("Failed to get tree for expression operand:\n");
1562 ir
->operands
[operand
]->print();
1566 op
[operand
] = this->result
;
1568 /* Matrix expression operands should have been broken down to vector
1569 * operations already.
1571 assert(!ir
->operands
[operand
]->type
->is_matrix());
1574 visit_expression(ir
, op
);
1577 /* The non-recursive part of the expression visitor lives in a separate
1578 * function and should be prevented from being inlined, to avoid a stack
1579 * explosion when deeply nested expressions are visited.
1582 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1584 st_src_reg result_src
;
1585 st_dst_reg result_dst
;
1587 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1588 if (ir
->operands
[1]) {
1589 vector_elements
= MAX2(vector_elements
,
1590 ir
->operands
[1]->type
->vector_elements
);
1593 this->result
.file
= PROGRAM_UNDEFINED
;
1595 /* Storage for our result. Ideally for an assignment we'd be using
1596 * the actual storage for the result here, instead.
1598 result_src
= get_temp(ir
->type
);
1599 /* convenience for the emit functions below. */
1600 result_dst
= st_dst_reg(result_src
);
1601 /* Limit writes to the channels that will be used by result_src later.
1602 * This does limit this temp's use as a temporary for multi-instruction
1605 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1607 switch (ir
->operation
) {
1608 case ir_unop_logic_not
:
1609 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1610 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1612 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1613 * older GPUs implement SEQ using multiple instructions (i915 uses two
1614 * SGE instructions and a MUL instruction). Since our logic values are
1615 * 0.0 and 1.0, 1-x also implements !x.
1617 op
[0].negate
= ~op
[0].negate
;
1618 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1622 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1623 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1624 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1625 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1627 op
[0].negate
= ~op
[0].negate
;
1631 case ir_unop_subroutine_to_int
:
1632 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1635 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1638 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1641 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1645 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1649 assert(!"not reached: should be handled by ir_explog_to_explog2");
1652 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1655 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1658 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1660 case ir_unop_saturate
: {
1661 glsl_to_tgsi_instruction
*inst
;
1662 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1663 inst
->saturate
= true;
1668 case ir_unop_dFdx_coarse
:
1669 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1671 case ir_unop_dFdx_fine
:
1672 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1675 case ir_unop_dFdy_coarse
:
1676 case ir_unop_dFdy_fine
:
1678 /* The X component contains 1 or -1 depending on whether the framebuffer
1679 * is a FBO or the window system buffer, respectively.
1680 * It is then multiplied with the source operand of DDY.
1682 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1683 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1685 unsigned transform_y_index
=
1686 _mesa_add_state_reference(this->prog
->Parameters
,
1689 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1691 glsl_type::vec4_type
);
1692 transform_y
.swizzle
= SWIZZLE_XXXX
;
1694 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1696 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1697 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1698 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1702 case ir_unop_frexp_sig
:
1703 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1706 case ir_unop_frexp_exp
:
1707 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1710 case ir_unop_noise
: {
1711 /* At some point, a motivated person could add a better
1712 * implementation of noise. Currently not even the nvidia
1713 * binary drivers do anything more than this. In any case, the
1714 * place to do this is in the GL state tracker, not the poor
1717 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1722 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1725 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1729 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1732 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1733 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1735 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1738 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1739 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1741 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1745 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1747 case ir_binop_greater
:
1748 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1750 case ir_binop_lequal
:
1751 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1753 case ir_binop_gequal
:
1754 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1756 case ir_binop_equal
:
1757 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1759 case ir_binop_nequal
:
1760 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1762 case ir_binop_all_equal
:
1763 /* "==" operator producing a scalar boolean. */
1764 if (ir
->operands
[0]->type
->is_vector() ||
1765 ir
->operands
[1]->type
->is_vector()) {
1766 st_src_reg temp
= get_temp(native_integers
?
1767 glsl_type::uvec4_type
:
1768 glsl_type::vec4_type
);
1770 if (native_integers
) {
1771 st_dst_reg temp_dst
= st_dst_reg(temp
);
1772 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1774 if (ir
->operands
[0]->type
->is_boolean() &&
1775 ir
->operands
[1]->as_constant() &&
1776 ir
->operands
[1]->as_constant()->is_one()) {
1777 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1779 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1782 /* Emit 1-3 AND operations to combine the SEQ results. */
1783 switch (ir
->operands
[0]->type
->vector_elements
) {
1787 temp_dst
.writemask
= WRITEMASK_Y
;
1788 temp1
.swizzle
= SWIZZLE_YYYY
;
1789 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1790 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1793 temp_dst
.writemask
= WRITEMASK_X
;
1794 temp1
.swizzle
= SWIZZLE_XXXX
;
1795 temp2
.swizzle
= SWIZZLE_YYYY
;
1796 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1797 temp_dst
.writemask
= WRITEMASK_Y
;
1798 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1799 temp2
.swizzle
= SWIZZLE_WWWW
;
1800 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1803 temp1
.swizzle
= SWIZZLE_XXXX
;
1804 temp2
.swizzle
= SWIZZLE_YYYY
;
1805 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1807 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1809 /* After the dot-product, the value will be an integer on the
1810 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1812 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1814 /* Negating the result of the dot-product gives values on the range
1815 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1816 * This is achieved using SGE.
1818 st_src_reg sge_src
= result_src
;
1819 sge_src
.negate
= ~sge_src
.negate
;
1820 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1823 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1826 case ir_binop_any_nequal
:
1827 /* "!=" operator producing a scalar boolean. */
1828 if (ir
->operands
[0]->type
->is_vector() ||
1829 ir
->operands
[1]->type
->is_vector()) {
1830 st_src_reg temp
= get_temp(native_integers
?
1831 glsl_type::uvec4_type
:
1832 glsl_type::vec4_type
);
1833 if (ir
->operands
[0]->type
->is_boolean() &&
1834 ir
->operands
[1]->as_constant() &&
1835 ir
->operands
[1]->as_constant()->is_zero()) {
1836 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1838 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1841 if (native_integers
) {
1842 st_dst_reg temp_dst
= st_dst_reg(temp
);
1843 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1845 /* Emit 1-3 OR operations to combine the SNE results. */
1846 switch (ir
->operands
[0]->type
->vector_elements
) {
1850 temp_dst
.writemask
= WRITEMASK_Y
;
1851 temp1
.swizzle
= SWIZZLE_YYYY
;
1852 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1853 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1856 temp_dst
.writemask
= WRITEMASK_X
;
1857 temp1
.swizzle
= SWIZZLE_XXXX
;
1858 temp2
.swizzle
= SWIZZLE_YYYY
;
1859 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1860 temp_dst
.writemask
= WRITEMASK_Y
;
1861 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1862 temp2
.swizzle
= SWIZZLE_WWWW
;
1863 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1866 temp1
.swizzle
= SWIZZLE_XXXX
;
1867 temp2
.swizzle
= SWIZZLE_YYYY
;
1868 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1870 /* After the dot-product, the value will be an integer on the
1871 * range [0,4]. Zero stays zero, and positive values become 1.0.
1873 glsl_to_tgsi_instruction
*const dp
=
1874 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1875 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1876 /* The clamping to [0,1] can be done for free in the fragment
1877 * shader with a saturate.
1879 dp
->saturate
= true;
1881 /* Negating the result of the dot-product gives values on the range
1882 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1883 * achieved using SLT.
1885 st_src_reg slt_src
= result_src
;
1886 slt_src
.negate
= ~slt_src
.negate
;
1887 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1891 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1895 case ir_binop_logic_xor
:
1896 if (native_integers
)
1897 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1899 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1902 case ir_binop_logic_or
: {
1903 if (native_integers
) {
1904 /* If integers are used as booleans, we can use an actual "or"
1907 assert(native_integers
);
1908 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1910 /* After the addition, the value will be an integer on the
1911 * range [0,2]. Zero stays zero, and positive values become 1.0.
1913 glsl_to_tgsi_instruction
*add
=
1914 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1915 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1916 /* The clamping to [0,1] can be done for free in the fragment
1917 * shader with a saturate if floats are being used as boolean values.
1919 add
->saturate
= true;
1921 /* Negating the result of the addition gives values on the range
1922 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1923 * is achieved using SLT.
1925 st_src_reg slt_src
= result_src
;
1926 slt_src
.negate
= ~slt_src
.negate
;
1927 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1933 case ir_binop_logic_and
:
1934 /* If native integers are disabled, the bool args are stored as float 0.0
1935 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1936 * actual AND opcode.
1938 if (native_integers
)
1939 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1941 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1945 assert(ir
->operands
[0]->type
->is_vector());
1946 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1947 emit_dp(ir
, result_dst
, op
[0], op
[1],
1948 ir
->operands
[0]->type
->vector_elements
);
1953 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1955 /* This is the only instruction sequence that makes the game "Risen"
1956 * render correctly. ABS is not required for the game, but since GLSL
1957 * declares negative values as "undefined", allowing us to do whatever
1958 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1961 emit_scalar(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1962 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, result_src
);
1963 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1967 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1970 if (native_integers
) {
1971 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1974 /* fallthrough to next case otherwise */
1976 if (native_integers
) {
1977 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1980 /* fallthrough to next case otherwise */
1983 /* Converting between signed and unsigned integers is a no-op. */
1985 result_src
.type
= result_dst
.type
;
1988 if (native_integers
) {
1989 /* Booleans are stored as integers using ~0 for true and 0 for false.
1990 * GLSL requires that int(bool) return 1 for true and 0 for false.
1991 * This conversion is done with AND, but it could be done with NEG.
1993 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1995 /* Booleans and integers are both stored as floats when native
1996 * integers are disabled.
2002 if (native_integers
)
2003 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2005 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2008 if (native_integers
)
2009 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2011 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2013 case ir_unop_bitcast_f2i
:
2014 case ir_unop_bitcast_f2u
:
2015 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2017 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2020 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2023 case ir_unop_bitcast_i2f
:
2024 case ir_unop_bitcast_u2f
:
2026 result_src
.type
= GLSL_TYPE_FLOAT
;
2029 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2032 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2035 if (native_integers
)
2036 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2038 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2041 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2044 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2047 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2049 case ir_unop_round_even
:
2050 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2053 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2057 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2060 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2063 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2066 case ir_unop_bit_not
:
2067 if (native_integers
) {
2068 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2072 if (native_integers
) {
2073 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2076 case ir_binop_lshift
:
2077 if (native_integers
) {
2078 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2081 case ir_binop_rshift
:
2082 if (native_integers
) {
2083 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2086 case ir_binop_bit_and
:
2087 if (native_integers
) {
2088 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2091 case ir_binop_bit_xor
:
2092 if (native_integers
) {
2093 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2096 case ir_binop_bit_or
:
2097 if (native_integers
) {
2098 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2102 assert(!"GLSL 1.30 features unsupported");
2105 case ir_binop_ubo_load
: {
2106 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2107 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2108 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2109 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2110 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2113 cbuf
.type
= ir
->type
->base_type
;
2114 cbuf
.file
= PROGRAM_CONSTANT
;
2116 cbuf
.reladdr
= NULL
;
2119 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2121 if (const_offset_ir
) {
2122 /* Constant index into constant buffer */
2123 cbuf
.reladdr
= NULL
;
2124 cbuf
.index
= const_offset
/ 16;
2127 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2128 st_src_reg offset
= op
[1];
2130 /* The OpenGL spec is written in such a way that accesses with
2131 * non-constant offset are almost always vec4-aligned. The only
2132 * exception to this are members of structs in arrays of structs:
2133 * each struct in an array of structs is at least vec4-aligned,
2134 * but single-element and [ui]vec2 members of the struct may be at
2135 * an offset that is not a multiple of 16 bytes.
2137 * Here, we extract that offset, relying on previous passes to always
2138 * generate offset expressions of the form (+ expr constant_offset).
2140 * Note that the std430 layout, which allows more cases of alignment
2141 * less than vec4 in arrays, is not supported for uniform blocks, so
2142 * we do not have to deal with it here.
2144 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2145 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2146 if (const_offset_ir
) {
2147 const_offset
= const_offset_ir
->value
.u
[0];
2148 cbuf
.index
= const_offset
/ 16;
2149 offset_expr
->operands
[0]->accept(this);
2150 offset
= this->result
;
2154 /* Relative/variable index into constant buffer */
2155 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2156 st_src_reg_for_int(4));
2157 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2158 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2161 if (const_uniform_block
) {
2162 /* Constant constant buffer */
2163 cbuf
.reladdr2
= NULL
;
2164 cbuf
.index2D
= const_block
;
2165 cbuf
.has_index2
= true;
2168 /* Relative/variable constant buffer */
2169 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2171 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2172 cbuf
.has_index2
= true;
2175 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2176 if (glsl_base_type_is_64bit(cbuf
.type
))
2177 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2178 const_offset
% 16 / 8,
2179 const_offset
% 16 / 8,
2180 const_offset
% 16 / 8);
2182 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2183 const_offset
% 16 / 4,
2184 const_offset
% 16 / 4,
2185 const_offset
% 16 / 4);
2187 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2188 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2190 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2195 /* note: we have to reorder the three args here */
2196 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2199 if (this->ctx
->Const
.NativeIntegers
)
2200 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2202 op
[0].negate
= ~op
[0].negate
;
2203 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2206 case ir_triop_bitfield_extract
:
2207 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2209 case ir_quadop_bitfield_insert
:
2210 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2212 case ir_unop_bitfield_reverse
:
2213 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2215 case ir_unop_bit_count
:
2216 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2218 case ir_unop_find_msb
:
2219 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2221 case ir_unop_find_lsb
:
2222 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2224 case ir_binop_imul_high
:
2225 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2228 /* In theory, MAD is incorrect here. */
2230 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2232 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2234 case ir_unop_interpolate_at_centroid
:
2235 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2237 case ir_binop_interpolate_at_offset
: {
2238 /* The y coordinate needs to be flipped for the default fb */
2239 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2240 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2242 unsigned transform_y_index
=
2243 _mesa_add_state_reference(this->prog
->Parameters
,
2246 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2248 glsl_type::vec4_type
);
2249 transform_y
.swizzle
= SWIZZLE_XXXX
;
2251 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2252 st_dst_reg temp_dst
= st_dst_reg(temp
);
2254 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2255 temp_dst
.writemask
= WRITEMASK_Y
;
2256 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2257 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2260 case ir_binop_interpolate_at_sample
:
2261 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2265 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2268 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2271 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2274 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2277 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2280 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2282 case ir_unop_unpack_double_2x32
:
2283 case ir_unop_pack_double_2x32
:
2284 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2287 case ir_binop_ldexp
:
2288 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2289 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2291 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2295 case ir_unop_pack_half_2x16
:
2296 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2298 case ir_unop_unpack_half_2x16
:
2299 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2302 case ir_unop_get_buffer_size
: {
2303 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2306 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2307 (const_offset
? const_offset
->value
.u
[0] : 0),
2309 if (!const_offset
) {
2310 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2311 *buffer
.reladdr
= op
[0];
2312 emit_arl(ir
, sampler_reladdr
, op
[0]);
2314 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2318 case ir_unop_vote_any
:
2319 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2321 case ir_unop_vote_all
:
2322 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2324 case ir_unop_vote_eq
:
2325 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2328 case ir_unop_pack_snorm_2x16
:
2329 case ir_unop_pack_unorm_2x16
:
2330 case ir_unop_pack_snorm_4x8
:
2331 case ir_unop_pack_unorm_4x8
:
2333 case ir_unop_unpack_snorm_2x16
:
2334 case ir_unop_unpack_unorm_2x16
:
2335 case ir_unop_unpack_snorm_4x8
:
2336 case ir_unop_unpack_unorm_4x8
:
2338 case ir_quadop_vector
:
2339 case ir_binop_vector_extract
:
2340 case ir_triop_vector_insert
:
2341 case ir_binop_carry
:
2342 case ir_binop_borrow
:
2343 case ir_unop_ssbo_unsized_array_length
:
2344 /* This operation is not supported, or should have already been handled.
2346 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2350 this->result
= result_src
;
2355 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2361 /* Note that this is only swizzles in expressions, not those on the left
2362 * hand side of an assignment, which do write masking. See ir_assignment
2366 ir
->val
->accept(this);
2368 assert(src
.file
!= PROGRAM_UNDEFINED
);
2369 assert(ir
->type
->vector_elements
> 0);
2371 for (i
= 0; i
< 4; i
++) {
2372 if (i
< ir
->type
->vector_elements
) {
2375 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2378 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2381 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2384 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2388 /* If the type is smaller than a vec4, replicate the last
2391 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2395 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2400 /* Test if the variable is an array. Note that geometry and
2401 * tessellation shader inputs are outputs are always arrays (except
2402 * for patch inputs), so only the array element type is considered.
2405 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2407 const glsl_type
*type
= var
->type
;
2409 *remove_array
= false;
2411 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2412 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2415 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2416 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2417 stage
== MESA_SHADER_TESS_CTRL
) &&
2419 if (!var
->type
->is_array())
2420 return false; /* a system value probably */
2422 type
= var
->type
->fields
.array
;
2423 *remove_array
= true;
2426 return type
->is_array() || type
->is_matrix();
2430 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2432 variable_storage
*entry
= find_variable_storage(ir
->var
);
2433 ir_variable
*var
= ir
->var
;
2437 switch (var
->data
.mode
) {
2438 case ir_var_uniform
:
2439 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2440 var
->data
.param_index
);
2441 this->variables
.push_tail(entry
);
2443 case ir_var_shader_in
: {
2444 /* The linker assigns locations for varyings and attributes,
2445 * including deprecated builtins (like gl_Color), user-assign
2446 * generic attributes (glBindVertexLocation), and
2447 * user-defined varyings.
2449 assert(var
->data
.location
!= -1);
2451 const glsl_type
*type_without_array
= var
->type
->without_array();
2452 struct inout_decl
*decl
= &inputs
[num_inputs
];
2453 unsigned component
= var
->data
.location_frac
;
2454 unsigned num_components
;
2457 if (type_without_array
->is_64bit())
2458 component
= component
/ 2;
2459 if (type_without_array
->vector_elements
)
2460 num_components
= type_without_array
->vector_elements
;
2464 decl
->mesa_index
= var
->data
.location
;
2465 decl
->base_type
= type_without_array
->base_type
;
2466 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2468 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2469 decl
->array_id
= num_input_arrays
+ 1;
2476 decl
->size
= type_size(var
->type
->fields
.array
);
2478 decl
->size
= type_size(var
->type
);
2480 entry
= new(mem_ctx
) variable_storage(var
,
2484 entry
->component
= component
;
2486 this->variables
.push_tail(entry
);
2489 case ir_var_shader_out
: {
2490 assert(var
->data
.location
!= -1);
2492 const glsl_type
*type_without_array
= var
->type
->without_array();
2493 struct inout_decl
*decl
= &outputs
[num_outputs
];
2494 unsigned component
= var
->data
.location_frac
;
2495 unsigned num_components
;
2498 if (type_without_array
->is_64bit())
2499 component
= component
/ 2;
2500 if (type_without_array
->vector_elements
)
2501 num_components
= type_without_array
->vector_elements
;
2505 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2506 decl
->base_type
= type_without_array
->base_type
;
2507 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2509 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2510 decl
->array_id
= num_output_arrays
+ 1;
2511 num_output_arrays
++;
2517 decl
->size
= type_size(var
->type
->fields
.array
);
2519 decl
->size
= type_size(var
->type
);
2521 entry
= new(mem_ctx
) variable_storage(var
,
2525 entry
->component
= component
;
2527 this->variables
.push_tail(entry
);
2530 case ir_var_system_value
:
2531 entry
= new(mem_ctx
) variable_storage(var
,
2532 PROGRAM_SYSTEM_VALUE
,
2533 var
->data
.location
);
2536 case ir_var_temporary
:
2537 st_src_reg src
= get_temp(var
->type
);
2539 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2541 this->variables
.push_tail(entry
);
2547 printf("Failed to make storage for %s\n", var
->name
);
2552 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2553 entry
->component
, entry
->array_id
);
2554 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2555 this->result
.is_double_vertex_input
= true;
2556 if (!native_integers
)
2557 this->result
.type
= GLSL_TYPE_FLOAT
;
2561 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2562 GLbitfield64
* usage_mask
,
2563 GLbitfield64 double_usage_mask
,
2564 GLbitfield
* patch_usage_mask
)
2569 /* Fix array declarations by removing unused array elements at both ends
2570 * of the arrays. For example, mat4[3] where only mat[1] is used.
2572 for (i
= 0; i
< count
; i
++) {
2573 struct inout_decl
*decl
= &decls
[i
];
2574 if (!decl
->array_id
)
2577 /* Shrink the beginning. */
2578 for (j
= 0; j
< (int)decl
->size
; j
++) {
2579 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2580 if (*patch_usage_mask
&
2581 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2585 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2587 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2596 /* Shrink the end. */
2597 for (j
= decl
->size
-1; j
>= 0; j
--) {
2598 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2599 if (*patch_usage_mask
&
2600 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2604 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2606 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2613 /* When not all entries of an array are accessed, we mark them as used
2614 * here anyway, to ensure that the input/output mapping logic doesn't get
2617 * TODO This happens when an array isn't used via indirect access, which
2618 * some game ports do (at least eON-based). There is an optimization
2619 * opportunity here by replacing the array declaration with non-array
2620 * declarations of those slots that are actually used.
2622 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2623 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2624 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2626 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2632 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2636 int element_size
= type_size(ir
->type
);
2639 index
= ir
->array_index
->constant_expression_value();
2641 ir
->array
->accept(this);
2644 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2645 switch (this->prog
->Target
) {
2646 case GL_TESS_CONTROL_PROGRAM_NV
:
2647 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2648 !ir
->variable_referenced()->data
.patch
;
2650 case GL_TESS_EVALUATION_PROGRAM_NV
:
2651 is_2D
= src
.file
== PROGRAM_INPUT
&&
2652 !ir
->variable_referenced()->data
.patch
;
2654 case GL_GEOMETRY_PROGRAM_NV
:
2655 is_2D
= src
.file
== PROGRAM_INPUT
;
2665 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2666 src
.file
== PROGRAM_INPUT
)
2667 element_size
= attrib_type_size(ir
->type
, true);
2669 src
.index2D
= index
->value
.i
[0];
2670 src
.has_index2
= true;
2672 src
.index
+= index
->value
.i
[0] * element_size
;
2674 /* Variable index array dereference. It eats the "vec4" of the
2675 * base of the array and an index that offsets the TGSI register
2678 ir
->array_index
->accept(this);
2680 st_src_reg index_reg
;
2682 if (element_size
== 1) {
2683 index_reg
= this->result
;
2685 index_reg
= get_temp(native_integers
?
2686 glsl_type::int_type
: glsl_type::float_type
);
2688 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2689 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2692 /* If there was already a relative address register involved, add the
2693 * new and the old together to get the new offset.
2695 if (!is_2D
&& src
.reladdr
!= NULL
) {
2696 st_src_reg accum_reg
= get_temp(native_integers
?
2697 glsl_type::int_type
: glsl_type::float_type
);
2699 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2700 index_reg
, *src
.reladdr
);
2702 index_reg
= accum_reg
;
2706 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2707 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2709 src
.has_index2
= true;
2711 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2712 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2716 /* Change the register type to the element type of the array. */
2717 src
.type
= ir
->type
->base_type
;
2723 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2726 const glsl_type
*struct_type
= ir
->record
->type
;
2729 ir
->record
->accept(this);
2731 for (i
= 0; i
< struct_type
->length
; i
++) {
2732 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2734 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2737 /* If the type is smaller than a vec4, replicate the last channel out. */
2738 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2739 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2741 this->result
.swizzle
= SWIZZLE_NOOP
;
2743 this->result
.index
+= offset
;
2744 this->result
.type
= ir
->type
->base_type
;
2748 * We want to be careful in assignment setup to hit the actual storage
2749 * instead of potentially using a temporary like we might with the
2750 * ir_dereference handler.
2753 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2755 /* The LHS must be a dereference. If the LHS is a variable indexed array
2756 * access of a vector, it must be separated into a series conditional moves
2757 * before reaching this point (see ir_vec_index_to_cond_assign).
2759 assert(ir
->as_dereference());
2760 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2762 assert(!deref_array
->array
->type
->is_vector());
2765 /* Use the rvalue deref handler for the most part. We write swizzles using
2766 * the writemask, but we do extract the base component for enhanced layouts
2767 * from the source swizzle.
2770 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2771 return st_dst_reg(v
->result
);
2775 * Process the condition of a conditional assignment
2777 * Examines the condition of a conditional assignment to generate the optimal
2778 * first operand of a \c CMP instruction. If the condition is a relational
2779 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2780 * used as the source for the \c CMP instruction. Otherwise the comparison
2781 * is processed to a boolean result, and the boolean result is used as the
2782 * operand to the CMP instruction.
2785 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2787 ir_rvalue
*src_ir
= ir
;
2789 bool switch_order
= false;
2791 ir_expression
*const expr
= ir
->as_expression();
2793 if (native_integers
) {
2794 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2795 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2796 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2797 type
== GLSL_TYPE_BOOL
) {
2798 if (expr
->operation
== ir_binop_equal
) {
2799 if (expr
->operands
[0]->is_zero()) {
2800 src_ir
= expr
->operands
[1];
2801 switch_order
= true;
2803 else if (expr
->operands
[1]->is_zero()) {
2804 src_ir
= expr
->operands
[0];
2805 switch_order
= true;
2808 else if (expr
->operation
== ir_binop_nequal
) {
2809 if (expr
->operands
[0]->is_zero()) {
2810 src_ir
= expr
->operands
[1];
2812 else if (expr
->operands
[1]->is_zero()) {
2813 src_ir
= expr
->operands
[0];
2819 src_ir
->accept(this);
2820 return switch_order
;
2823 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2824 bool zero_on_left
= false;
2826 if (expr
->operands
[0]->is_zero()) {
2827 src_ir
= expr
->operands
[1];
2828 zero_on_left
= true;
2829 } else if (expr
->operands
[1]->is_zero()) {
2830 src_ir
= expr
->operands
[0];
2831 zero_on_left
= false;
2835 * (a < 0) T F F ( a < 0) T F F
2836 * (0 < a) F F T (-a < 0) F F T
2837 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2838 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2839 * (a > 0) F F T (-a < 0) F F T
2840 * (0 > a) T F F ( a < 0) T F F
2841 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2842 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2844 * Note that exchanging the order of 0 and 'a' in the comparison simply
2845 * means that the value of 'a' should be negated.
2848 switch (expr
->operation
) {
2850 switch_order
= false;
2851 negate
= zero_on_left
;
2854 case ir_binop_greater
:
2855 switch_order
= false;
2856 negate
= !zero_on_left
;
2859 case ir_binop_lequal
:
2860 switch_order
= true;
2861 negate
= !zero_on_left
;
2864 case ir_binop_gequal
:
2865 switch_order
= true;
2866 negate
= zero_on_left
;
2870 /* This isn't the right kind of comparison afterall, so make sure
2871 * the whole condition is visited.
2879 src_ir
->accept(this);
2881 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2882 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2883 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2884 * computing the condition.
2887 this->result
.negate
= ~this->result
.negate
;
2889 return switch_order
;
2893 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2894 st_dst_reg
*l
, st_src_reg
*r
,
2895 st_src_reg
*cond
, bool cond_swap
)
2897 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2898 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2899 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2905 if (type
->is_array()) {
2906 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2907 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2912 if (type
->is_matrix()) {
2913 const struct glsl_type
*vec_type
;
2915 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2916 type
->vector_elements
, 1);
2918 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2919 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2924 assert(type
->is_scalar() || type
->is_vector());
2926 r
->type
= type
->base_type
;
2928 st_src_reg l_src
= st_src_reg(*l
);
2929 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2931 if (native_integers
) {
2932 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2933 cond_swap
? l_src
: *r
,
2934 cond_swap
? *r
: l_src
);
2936 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2937 cond_swap
? l_src
: *r
,
2938 cond_swap
? *r
: l_src
);
2941 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2945 if (type
->is_dual_slot()) {
2947 if (r
->is_double_vertex_input
== false)
2953 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2959 ir
->rhs
->accept(this);
2962 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2966 int first_enabled_chan
= 0;
2968 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2970 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2971 variable
->data
.mode
== ir_var_shader_out
&&
2972 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2973 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2974 assert(ir
->lhs
->type
->is_scalar());
2975 assert(ir
->write_mask
== WRITEMASK_X
);
2977 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2978 l
.writemask
= WRITEMASK_Z
;
2980 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2981 l
.writemask
= WRITEMASK_Y
;
2983 } else if (ir
->write_mask
== 0) {
2984 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2986 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->is_matrix()) {
2987 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2988 l
.writemask
= u_bit_consecutive(0, num_elements
);
2990 l
.writemask
= WRITEMASK_XYZW
;
2993 l
.writemask
= ir
->write_mask
;
2996 for (int i
= 0; i
< 4; i
++) {
2997 if (l
.writemask
& (1 << i
)) {
2998 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3003 l
.writemask
= l
.writemask
<< dst_component
;
3005 /* Swizzle a small RHS vector into the channels being written.
3007 * glsl ir treats write_mask as dictating how many channels are
3008 * present on the RHS while TGSI treats write_mask as just
3009 * showing which channels of the vec4 RHS get written.
3011 for (int i
= 0; i
< 4; i
++) {
3012 if (l
.writemask
& (1 << i
))
3013 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3015 swizzles
[i
] = first_enabled_chan
;
3017 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3018 swizzles
[2], swizzles
[3]);
3021 assert(l
.file
!= PROGRAM_UNDEFINED
);
3022 assert(r
.file
!= PROGRAM_UNDEFINED
);
3024 if (ir
->condition
) {
3025 const bool switch_order
= this->process_move_condition(ir
->condition
);
3026 st_src_reg condition
= this->result
;
3028 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3029 } else if (ir
->rhs
->as_expression() &&
3030 this->instructions
.get_tail() &&
3031 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3032 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3033 type_size(ir
->lhs
->type
) == 1 &&
3034 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3035 /* To avoid emitting an extra MOV when assigning an expression to a
3036 * variable, emit the last instruction of the expression again, but
3037 * replace the destination register with the target of the assignment.
3038 * Dead code elimination will remove the original instruction.
3040 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3041 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3042 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3043 new_inst
->saturate
= inst
->saturate
;
3044 inst
->dead_mask
= inst
->dst
[0].writemask
;
3046 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3052 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3055 GLdouble stack_vals
[4] = { 0 };
3056 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3057 GLenum gl_type
= GL_NONE
;
3059 static int in_array
= 0;
3060 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3062 /* Unfortunately, 4 floats is all we can get into
3063 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3064 * aggregate constant and move each constant value into it. If we
3065 * get lucky, copy propagation will eliminate the extra moves.
3067 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3068 st_src_reg temp_base
= get_temp(ir
->type
);
3069 st_dst_reg temp
= st_dst_reg(temp_base
);
3071 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3072 int size
= type_size(field_value
->type
);
3076 field_value
->accept(this);
3079 for (i
= 0; i
< (unsigned int)size
; i
++) {
3080 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3086 this->result
= temp_base
;
3090 if (ir
->type
->is_array()) {
3091 st_src_reg temp_base
= get_temp(ir
->type
);
3092 st_dst_reg temp
= st_dst_reg(temp_base
);
3093 int size
= type_size(ir
->type
->fields
.array
);
3098 for (i
= 0; i
< ir
->type
->length
; i
++) {
3099 ir
->array_elements
[i
]->accept(this);
3101 for (int j
= 0; j
< size
; j
++) {
3102 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3108 this->result
= temp_base
;
3113 if (ir
->type
->is_matrix()) {
3114 st_src_reg mat
= get_temp(ir
->type
);
3115 st_dst_reg mat_column
= st_dst_reg(mat
);
3117 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3118 switch (ir
->type
->base_type
) {
3119 case GLSL_TYPE_FLOAT
:
3120 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3122 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3123 src
.index
= add_constant(file
,
3125 ir
->type
->vector_elements
,
3128 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3130 case GLSL_TYPE_DOUBLE
:
3131 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3132 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3133 src
.index
= add_constant(file
,
3135 ir
->type
->vector_elements
,
3138 if (ir
->type
->vector_elements
>= 2) {
3139 mat_column
.writemask
= WRITEMASK_XY
;
3140 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3141 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3143 mat_column
.writemask
= WRITEMASK_X
;
3144 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3145 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3148 if (ir
->type
->vector_elements
> 2) {
3149 if (ir
->type
->vector_elements
== 4) {
3150 mat_column
.writemask
= WRITEMASK_ZW
;
3151 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3152 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3154 mat_column
.writemask
= WRITEMASK_Z
;
3155 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3156 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3157 mat_column
.writemask
= WRITEMASK_XYZW
;
3158 src
.swizzle
= SWIZZLE_XYZW
;
3164 unreachable("Illegal matrix constant type.\n");
3173 switch (ir
->type
->base_type
) {
3174 case GLSL_TYPE_FLOAT
:
3176 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3177 values
[i
].f
= ir
->value
.f
[i
];
3180 case GLSL_TYPE_DOUBLE
:
3181 gl_type
= GL_DOUBLE
;
3182 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3183 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3186 case GLSL_TYPE_UINT
:
3187 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3188 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3189 if (native_integers
)
3190 values
[i
].u
= ir
->value
.u
[i
];
3192 values
[i
].f
= ir
->value
.u
[i
];
3196 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3197 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3198 if (native_integers
)
3199 values
[i
].i
= ir
->value
.i
[i
];
3201 values
[i
].f
= ir
->value
.i
[i
];
3204 case GLSL_TYPE_BOOL
:
3205 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3206 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3207 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3211 assert(!"Non-float/uint/int/bool constant");
3214 this->result
= st_src_reg(file
, -1, ir
->type
);
3215 this->result
.index
= add_constant(file
,
3217 ir
->type
->vector_elements
,
3219 &this->result
.swizzle
);
3223 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3225 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3226 if (entry
->sig
== sig
)
3230 entry
= ralloc(mem_ctx
, function_entry
);
3232 entry
->sig_id
= this->next_signature_id
++;
3233 entry
->bgn_inst
= NULL
;
3235 /* Allocate storage for all the parameters. */
3236 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3237 variable_storage
*storage
;
3239 storage
= find_variable_storage(param
);
3242 st_src_reg src
= get_temp(param
->type
);
3244 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3245 this->variables
.push_tail(storage
);
3248 if (!sig
->return_type
->is_void()) {
3249 entry
->return_reg
= get_temp(sig
->return_type
);
3251 entry
->return_reg
= undef_src
;
3254 this->function_signatures
.push_tail(entry
);
3259 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3261 exec_node
*param
= ir
->actual_parameters
.get_head();
3262 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3263 ir_variable
*location
= deref
->variable_referenced();
3266 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3268 /* Calculate the surface offset */
3270 unsigned array_size
= 0, base
= 0;
3273 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3275 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3276 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3277 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3278 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3279 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3281 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3284 ir
->return_deref
->accept(this);
3285 st_dst_reg
dst(this->result
);
3286 dst
.writemask
= WRITEMASK_X
;
3288 glsl_to_tgsi_instruction
*inst
;
3290 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3291 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3292 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3293 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3294 st_src_reg_for_int(1));
3295 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3296 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3297 st_src_reg_for_int(-1));
3298 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3300 param
= param
->get_next();
3301 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3304 st_src_reg data
= this->result
, data2
= undef_src
;
3306 switch (ir
->callee
->intrinsic_id
) {
3307 case ir_intrinsic_atomic_counter_add
:
3308 opcode
= TGSI_OPCODE_ATOMUADD
;
3310 case ir_intrinsic_atomic_counter_min
:
3311 opcode
= TGSI_OPCODE_ATOMIMIN
;
3313 case ir_intrinsic_atomic_counter_max
:
3314 opcode
= TGSI_OPCODE_ATOMIMAX
;
3316 case ir_intrinsic_atomic_counter_and
:
3317 opcode
= TGSI_OPCODE_ATOMAND
;
3319 case ir_intrinsic_atomic_counter_or
:
3320 opcode
= TGSI_OPCODE_ATOMOR
;
3322 case ir_intrinsic_atomic_counter_xor
:
3323 opcode
= TGSI_OPCODE_ATOMXOR
;
3325 case ir_intrinsic_atomic_counter_exchange
:
3326 opcode
= TGSI_OPCODE_ATOMXCHG
;
3328 case ir_intrinsic_atomic_counter_comp_swap
: {
3329 opcode
= TGSI_OPCODE_ATOMCAS
;
3330 param
= param
->get_next();
3331 val
= ((ir_instruction
*)param
)->as_rvalue();
3333 data2
= this->result
;
3337 assert(!"Unexpected intrinsic");
3341 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3344 inst
->resource
= buffer
;
3348 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3350 exec_node
*param
= ir
->actual_parameters
.get_head();
3352 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3354 param
= param
->get_next();
3355 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3357 ir_constant
*const_block
= block
->as_constant();
3361 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3362 (const_block
? const_block
->value
.u
[0] : 0),
3366 block
->accept(this);
3367 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3368 *buffer
.reladdr
= this->result
;
3369 emit_arl(ir
, sampler_reladdr
, this->result
);
3372 /* Calculate the surface offset */
3373 offset
->accept(this);
3374 st_src_reg off
= this->result
;
3376 st_dst_reg dst
= undef_dst
;
3377 if (ir
->return_deref
) {
3378 ir
->return_deref
->accept(this);
3379 dst
= st_dst_reg(this->result
);
3380 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3383 glsl_to_tgsi_instruction
*inst
;
3385 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3386 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3387 if (dst
.type
== GLSL_TYPE_BOOL
)
3388 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3389 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3390 param
= param
->get_next();
3391 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3394 param
= param
->get_next();
3395 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3397 dst
.writemask
= write_mask
->value
.u
[0];
3399 dst
.type
= this->result
.type
;
3400 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3402 param
= param
->get_next();
3403 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3406 st_src_reg data
= this->result
, data2
= undef_src
;
3408 switch (ir
->callee
->intrinsic_id
) {
3409 case ir_intrinsic_ssbo_atomic_add
:
3410 opcode
= TGSI_OPCODE_ATOMUADD
;
3412 case ir_intrinsic_ssbo_atomic_min
:
3413 opcode
= TGSI_OPCODE_ATOMIMIN
;
3415 case ir_intrinsic_ssbo_atomic_max
:
3416 opcode
= TGSI_OPCODE_ATOMIMAX
;
3418 case ir_intrinsic_ssbo_atomic_and
:
3419 opcode
= TGSI_OPCODE_ATOMAND
;
3421 case ir_intrinsic_ssbo_atomic_or
:
3422 opcode
= TGSI_OPCODE_ATOMOR
;
3424 case ir_intrinsic_ssbo_atomic_xor
:
3425 opcode
= TGSI_OPCODE_ATOMXOR
;
3427 case ir_intrinsic_ssbo_atomic_exchange
:
3428 opcode
= TGSI_OPCODE_ATOMXCHG
;
3430 case ir_intrinsic_ssbo_atomic_comp_swap
:
3431 opcode
= TGSI_OPCODE_ATOMCAS
;
3432 param
= param
->get_next();
3433 val
= ((ir_instruction
*)param
)->as_rvalue();
3435 data2
= this->result
;
3438 assert(!"Unexpected intrinsic");
3442 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3445 param
= param
->get_next();
3446 ir_constant
*access
= NULL
;
3447 if (!param
->is_tail_sentinel()) {
3448 access
= ((ir_instruction
*)param
)->as_constant();
3452 /* The emit_asm() might have actually split the op into pieces, e.g. for
3453 * double stores. We have to go back and fix up all the generated ops.
3455 unsigned op
= inst
->op
;
3457 inst
->resource
= buffer
;
3459 inst
->buffer_access
= access
->value
.u
[0];
3460 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3461 if (inst
->op
== TGSI_OPCODE_UADD
)
3462 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3463 } while (inst
&& inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3467 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3469 switch (ir
->callee
->intrinsic_id
) {
3470 case ir_intrinsic_memory_barrier
:
3471 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3472 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3473 TGSI_MEMBAR_ATOMIC_BUFFER
|
3474 TGSI_MEMBAR_SHADER_IMAGE
|
3475 TGSI_MEMBAR_SHARED
));
3477 case ir_intrinsic_memory_barrier_atomic_counter
:
3478 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3479 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3481 case ir_intrinsic_memory_barrier_buffer
:
3482 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3483 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3485 case ir_intrinsic_memory_barrier_image
:
3486 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3487 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3489 case ir_intrinsic_memory_barrier_shared
:
3490 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3491 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3493 case ir_intrinsic_group_memory_barrier
:
3494 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3495 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3496 TGSI_MEMBAR_ATOMIC_BUFFER
|
3497 TGSI_MEMBAR_SHADER_IMAGE
|
3498 TGSI_MEMBAR_SHARED
|
3499 TGSI_MEMBAR_THREAD_GROUP
));
3502 assert(!"Unexpected memory barrier intrinsic");
3507 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3509 exec_node
*param
= ir
->actual_parameters
.get_head();
3511 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3513 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3515 /* Calculate the surface offset */
3516 offset
->accept(this);
3517 st_src_reg off
= this->result
;
3519 st_dst_reg dst
= undef_dst
;
3520 if (ir
->return_deref
) {
3521 ir
->return_deref
->accept(this);
3522 dst
= st_dst_reg(this->result
);
3523 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3526 glsl_to_tgsi_instruction
*inst
;
3528 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3529 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3530 inst
->resource
= buffer
;
3531 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3532 param
= param
->get_next();
3533 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3536 param
= param
->get_next();
3537 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3539 dst
.writemask
= write_mask
->value
.u
[0];
3541 dst
.type
= this->result
.type
;
3542 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3543 inst
->resource
= buffer
;
3545 param
= param
->get_next();
3546 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3549 st_src_reg data
= this->result
, data2
= undef_src
;
3551 switch (ir
->callee
->intrinsic_id
) {
3552 case ir_intrinsic_shared_atomic_add
:
3553 opcode
= TGSI_OPCODE_ATOMUADD
;
3555 case ir_intrinsic_shared_atomic_min
:
3556 opcode
= TGSI_OPCODE_ATOMIMIN
;
3558 case ir_intrinsic_shared_atomic_max
:
3559 opcode
= TGSI_OPCODE_ATOMIMAX
;
3561 case ir_intrinsic_shared_atomic_and
:
3562 opcode
= TGSI_OPCODE_ATOMAND
;
3564 case ir_intrinsic_shared_atomic_or
:
3565 opcode
= TGSI_OPCODE_ATOMOR
;
3567 case ir_intrinsic_shared_atomic_xor
:
3568 opcode
= TGSI_OPCODE_ATOMXOR
;
3570 case ir_intrinsic_shared_atomic_exchange
:
3571 opcode
= TGSI_OPCODE_ATOMXCHG
;
3573 case ir_intrinsic_shared_atomic_comp_swap
:
3574 opcode
= TGSI_OPCODE_ATOMCAS
;
3575 param
= param
->get_next();
3576 val
= ((ir_instruction
*)param
)->as_rvalue();
3578 data2
= this->result
;
3581 assert(!"Unexpected intrinsic");
3585 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3586 inst
->resource
= buffer
;
3591 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3593 exec_node
*param
= ir
->actual_parameters
.get_head();
3595 ir_dereference
*img
= (ir_dereference
*)param
;
3596 const ir_variable
*imgvar
= img
->variable_referenced();
3597 const glsl_type
*type
= imgvar
->type
->without_array();
3598 unsigned sampler_array_size
= 1, sampler_base
= 0;
3601 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3603 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3604 (uint16_t*)&image
.index
, &reladdr
, true);
3606 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3607 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3608 *image
.reladdr
= reladdr
;
3609 emit_arl(ir
, sampler_reladdr
, reladdr
);
3612 st_dst_reg dst
= undef_dst
;
3613 if (ir
->return_deref
) {
3614 ir
->return_deref
->accept(this);
3615 dst
= st_dst_reg(this->result
);
3616 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3619 glsl_to_tgsi_instruction
*inst
;
3621 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3622 dst
.writemask
= WRITEMASK_XYZ
;
3623 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3624 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3625 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3626 st_dst_reg dstres
= st_dst_reg(res
);
3627 dstres
.writemask
= WRITEMASK_W
;
3628 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3629 res
.swizzle
= SWIZZLE_WWWW
;
3630 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3632 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3634 st_dst_reg coord_dst
;
3635 coord
= get_temp(glsl_type::ivec4_type
);
3636 coord_dst
= st_dst_reg(coord
);
3637 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3638 param
= param
->get_next();
3639 ((ir_dereference
*)param
)->accept(this);
3640 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3641 coord
.swizzle
= SWIZZLE_XXXX
;
3642 switch (type
->coordinate_components()) {
3643 case 4: assert(!"unexpected coord count");
3645 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3647 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3650 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3651 param
= param
->get_next();
3652 ((ir_dereference
*)param
)->accept(this);
3653 st_src_reg sample
= this->result
;
3654 sample
.swizzle
= SWIZZLE_XXXX
;
3655 coord_dst
.writemask
= WRITEMASK_W
;
3656 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3657 coord
.swizzle
|= SWIZZLE_W
<< 9;
3660 param
= param
->get_next();
3661 if (!param
->is_tail_sentinel()) {
3662 ((ir_dereference
*)param
)->accept(this);
3663 arg1
= this->result
;
3664 param
= param
->get_next();
3667 if (!param
->is_tail_sentinel()) {
3668 ((ir_dereference
*)param
)->accept(this);
3669 arg2
= this->result
;
3670 param
= param
->get_next();
3673 assert(param
->is_tail_sentinel());
3676 switch (ir
->callee
->intrinsic_id
) {
3677 case ir_intrinsic_image_load
:
3678 opcode
= TGSI_OPCODE_LOAD
;
3680 case ir_intrinsic_image_store
:
3681 opcode
= TGSI_OPCODE_STORE
;
3683 case ir_intrinsic_image_atomic_add
:
3684 opcode
= TGSI_OPCODE_ATOMUADD
;
3686 case ir_intrinsic_image_atomic_min
:
3687 opcode
= TGSI_OPCODE_ATOMIMIN
;
3689 case ir_intrinsic_image_atomic_max
:
3690 opcode
= TGSI_OPCODE_ATOMIMAX
;
3692 case ir_intrinsic_image_atomic_and
:
3693 opcode
= TGSI_OPCODE_ATOMAND
;
3695 case ir_intrinsic_image_atomic_or
:
3696 opcode
= TGSI_OPCODE_ATOMOR
;
3698 case ir_intrinsic_image_atomic_xor
:
3699 opcode
= TGSI_OPCODE_ATOMXOR
;
3701 case ir_intrinsic_image_atomic_exchange
:
3702 opcode
= TGSI_OPCODE_ATOMXCHG
;
3704 case ir_intrinsic_image_atomic_comp_swap
:
3705 opcode
= TGSI_OPCODE_ATOMCAS
;
3708 assert(!"Unexpected intrinsic");
3712 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3713 if (opcode
== TGSI_OPCODE_STORE
)
3714 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3717 inst
->resource
= image
;
3718 inst
->sampler_array_size
= sampler_array_size
;
3719 inst
->sampler_base
= sampler_base
;
3721 switch (type
->sampler_dimensionality
) {
3722 case GLSL_SAMPLER_DIM_1D
:
3723 inst
->tex_target
= (type
->sampler_array
)
3724 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3726 case GLSL_SAMPLER_DIM_2D
:
3727 inst
->tex_target
= (type
->sampler_array
)
3728 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3730 case GLSL_SAMPLER_DIM_3D
:
3731 inst
->tex_target
= TEXTURE_3D_INDEX
;
3733 case GLSL_SAMPLER_DIM_CUBE
:
3734 inst
->tex_target
= (type
->sampler_array
)
3735 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3737 case GLSL_SAMPLER_DIM_RECT
:
3738 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3740 case GLSL_SAMPLER_DIM_BUF
:
3741 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3743 case GLSL_SAMPLER_DIM_EXTERNAL
:
3744 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3746 case GLSL_SAMPLER_DIM_MS
:
3747 inst
->tex_target
= (type
->sampler_array
)
3748 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3751 assert(!"Should not get here.");
3754 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3755 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3757 if (imgvar
->data
.image_coherent
)
3758 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3759 if (imgvar
->data
.image_restrict
)
3760 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3761 if (imgvar
->data
.image_volatile
)
3762 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3766 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3768 glsl_to_tgsi_instruction
*call_inst
;
3769 ir_function_signature
*sig
= ir
->callee
;
3770 function_entry
*entry
;
3773 /* Filter out intrinsics */
3774 switch (sig
->intrinsic_id
) {
3775 case ir_intrinsic_invalid
:
3778 case ir_intrinsic_atomic_counter_read
:
3779 case ir_intrinsic_atomic_counter_increment
:
3780 case ir_intrinsic_atomic_counter_predecrement
:
3781 case ir_intrinsic_atomic_counter_add
:
3782 case ir_intrinsic_atomic_counter_min
:
3783 case ir_intrinsic_atomic_counter_max
:
3784 case ir_intrinsic_atomic_counter_and
:
3785 case ir_intrinsic_atomic_counter_or
:
3786 case ir_intrinsic_atomic_counter_xor
:
3787 case ir_intrinsic_atomic_counter_exchange
:
3788 case ir_intrinsic_atomic_counter_comp_swap
:
3789 visit_atomic_counter_intrinsic(ir
);
3792 case ir_intrinsic_ssbo_load
:
3793 case ir_intrinsic_ssbo_store
:
3794 case ir_intrinsic_ssbo_atomic_add
:
3795 case ir_intrinsic_ssbo_atomic_min
:
3796 case ir_intrinsic_ssbo_atomic_max
:
3797 case ir_intrinsic_ssbo_atomic_and
:
3798 case ir_intrinsic_ssbo_atomic_or
:
3799 case ir_intrinsic_ssbo_atomic_xor
:
3800 case ir_intrinsic_ssbo_atomic_exchange
:
3801 case ir_intrinsic_ssbo_atomic_comp_swap
:
3802 visit_ssbo_intrinsic(ir
);
3805 case ir_intrinsic_memory_barrier
:
3806 case ir_intrinsic_memory_barrier_atomic_counter
:
3807 case ir_intrinsic_memory_barrier_buffer
:
3808 case ir_intrinsic_memory_barrier_image
:
3809 case ir_intrinsic_memory_barrier_shared
:
3810 case ir_intrinsic_group_memory_barrier
:
3811 visit_membar_intrinsic(ir
);
3814 case ir_intrinsic_shared_load
:
3815 case ir_intrinsic_shared_store
:
3816 case ir_intrinsic_shared_atomic_add
:
3817 case ir_intrinsic_shared_atomic_min
:
3818 case ir_intrinsic_shared_atomic_max
:
3819 case ir_intrinsic_shared_atomic_and
:
3820 case ir_intrinsic_shared_atomic_or
:
3821 case ir_intrinsic_shared_atomic_xor
:
3822 case ir_intrinsic_shared_atomic_exchange
:
3823 case ir_intrinsic_shared_atomic_comp_swap
:
3824 visit_shared_intrinsic(ir
);
3827 case ir_intrinsic_image_load
:
3828 case ir_intrinsic_image_store
:
3829 case ir_intrinsic_image_atomic_add
:
3830 case ir_intrinsic_image_atomic_min
:
3831 case ir_intrinsic_image_atomic_max
:
3832 case ir_intrinsic_image_atomic_and
:
3833 case ir_intrinsic_image_atomic_or
:
3834 case ir_intrinsic_image_atomic_xor
:
3835 case ir_intrinsic_image_atomic_exchange
:
3836 case ir_intrinsic_image_atomic_comp_swap
:
3837 case ir_intrinsic_image_size
:
3838 case ir_intrinsic_image_samples
:
3839 visit_image_intrinsic(ir
);
3842 case ir_intrinsic_generic_load
:
3843 case ir_intrinsic_generic_store
:
3844 case ir_intrinsic_generic_atomic_add
:
3845 case ir_intrinsic_generic_atomic_and
:
3846 case ir_intrinsic_generic_atomic_or
:
3847 case ir_intrinsic_generic_atomic_xor
:
3848 case ir_intrinsic_generic_atomic_min
:
3849 case ir_intrinsic_generic_atomic_max
:
3850 case ir_intrinsic_generic_atomic_exchange
:
3851 case ir_intrinsic_generic_atomic_comp_swap
:
3852 case ir_intrinsic_shader_clock
:
3853 unreachable("Invalid intrinsic");
3856 entry
= get_function_signature(sig
);
3857 /* Process in parameters. */
3858 foreach_two_lists(formal_node
, &sig
->parameters
,
3859 actual_node
, &ir
->actual_parameters
) {
3860 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3861 ir_variable
*param
= (ir_variable
*) formal_node
;
3863 if (param
->data
.mode
== ir_var_function_in
||
3864 param
->data
.mode
== ir_var_function_inout
) {
3865 variable_storage
*storage
= find_variable_storage(param
);
3868 param_rval
->accept(this);
3869 st_src_reg r
= this->result
;
3872 l
.file
= storage
->file
;
3873 l
.index
= storage
->index
;
3875 l
.writemask
= WRITEMASK_XYZW
;
3877 for (i
= 0; i
< type_size(param
->type
); i
++) {
3878 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3885 /* Emit call instruction */
3886 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3887 call_inst
->function
= entry
;
3889 /* Process out parameters. */
3890 foreach_two_lists(formal_node
, &sig
->parameters
,
3891 actual_node
, &ir
->actual_parameters
) {
3892 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3893 ir_variable
*param
= (ir_variable
*) formal_node
;
3895 if (param
->data
.mode
== ir_var_function_out
||
3896 param
->data
.mode
== ir_var_function_inout
) {
3897 variable_storage
*storage
= find_variable_storage(param
);
3901 r
.file
= storage
->file
;
3902 r
.index
= storage
->index
;
3904 r
.swizzle
= SWIZZLE_NOOP
;
3907 param_rval
->accept(this);
3908 st_dst_reg l
= st_dst_reg(this->result
);
3910 for (i
= 0; i
< type_size(param
->type
); i
++) {
3911 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3918 /* Process return value. */
3919 this->result
= entry
->return_reg
;
3923 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3924 unsigned *array_elements
,
3926 st_src_reg
*indirect
,
3929 switch (tail
->ir_type
) {
3930 case ir_type_dereference_record
: {
3931 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3932 const glsl_type
*struct_type
= deref_record
->record
->type
;
3933 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3935 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3937 assert(field_index
>= 0);
3938 *location
+= struct_type
->record_location_offset(field_index
);
3942 case ir_type_dereference_array
: {
3943 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3944 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3947 st_src_reg temp_reg
;
3948 st_dst_reg temp_dst
;
3950 temp_reg
= get_temp(glsl_type::uint_type
);
3951 temp_dst
= st_dst_reg(temp_reg
);
3952 temp_dst
.writemask
= 1;
3954 deref_arr
->array_index
->accept(this);
3955 if (*array_elements
!= 1)
3956 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3958 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3960 if (indirect
->file
== PROGRAM_UNDEFINED
)
3961 *indirect
= temp_reg
;
3963 temp_dst
= st_dst_reg(*indirect
);
3964 temp_dst
.writemask
= 1;
3965 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3968 *index
+= array_index
->value
.u
[0] * *array_elements
;
3970 *array_elements
*= deref_arr
->array
->type
->length
;
3972 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3981 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3982 unsigned *array_size
,
3985 st_src_reg
*reladdr
,
3988 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3989 unsigned location
= 0;
3990 ir_variable
*var
= ir
->variable_referenced();
3992 memset(reladdr
, 0, sizeof(*reladdr
));
3993 reladdr
->file
= PROGRAM_UNDEFINED
;
3999 location
= var
->data
.location
;
4000 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4003 * If we end up with no indirect then adjust the base to the index,
4004 * and set the array size to 1.
4006 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4012 assert(location
!= 0xffffffff);
4013 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
4014 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
4019 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4021 if (offset
.reladdr
|| offset
.reladdr2
) {
4022 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4023 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4024 tmp_dst
.writemask
= WRITEMASK_XY
;
4025 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4033 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4035 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4036 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4037 st_src_reg levels_src
, reladdr
;
4038 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4039 glsl_to_tgsi_instruction
*inst
= NULL
;
4040 unsigned opcode
= TGSI_OPCODE_NOP
;
4041 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4042 unsigned sampler_array_size
= 1, sampler_base
= 0;
4043 uint16_t sampler_index
= 0;
4044 bool is_cube_array
= false;
4047 /* if we are a cube array sampler */
4048 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
4049 sampler_type
->sampler_array
)) {
4050 is_cube_array
= true;
4053 if (ir
->coordinate
) {
4054 ir
->coordinate
->accept(this);
4056 /* Put our coords in a temp. We'll need to modify them for shadow,
4057 * projection, or LOD, so the only case we'd use it as-is is if
4058 * we're doing plain old texturing. The optimization passes on
4059 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4061 coord
= get_temp(glsl_type::vec4_type
);
4062 coord_dst
= st_dst_reg(coord
);
4063 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4064 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4067 if (ir
->projector
) {
4068 ir
->projector
->accept(this);
4069 projector
= this->result
;
4072 /* Storage for our result. Ideally for an assignment we'd be using
4073 * the actual storage for the result here, instead.
4075 result_src
= get_temp(ir
->type
);
4076 result_dst
= st_dst_reg(result_src
);
4080 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4082 ir
->offset
->accept(this);
4083 offset
[0] = this->result
;
4087 if (is_cube_array
||
4088 sampler_type
== glsl_type::samplerCubeShadow_type
) {
4089 opcode
= TGSI_OPCODE_TXB2
;
4092 opcode
= TGSI_OPCODE_TXB
;
4094 ir
->lod_info
.bias
->accept(this);
4095 lod_info
= this->result
;
4097 ir
->offset
->accept(this);
4098 offset
[0] = this->result
;
4102 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4103 ir
->lod_info
.lod
->accept(this);
4104 lod_info
= this->result
;
4106 ir
->offset
->accept(this);
4107 offset
[0] = this->result
;
4111 opcode
= TGSI_OPCODE_TXD
;
4112 ir
->lod_info
.grad
.dPdx
->accept(this);
4114 ir
->lod_info
.grad
.dPdy
->accept(this);
4117 ir
->offset
->accept(this);
4118 offset
[0] = this->result
;
4122 opcode
= TGSI_OPCODE_TXQ
;
4123 ir
->lod_info
.lod
->accept(this);
4124 lod_info
= this->result
;
4126 case ir_query_levels
:
4127 opcode
= TGSI_OPCODE_TXQ
;
4128 lod_info
= undef_src
;
4129 levels_src
= get_temp(ir
->type
);
4132 opcode
= TGSI_OPCODE_TXF
;
4133 ir
->lod_info
.lod
->accept(this);
4134 lod_info
= this->result
;
4136 ir
->offset
->accept(this);
4137 offset
[0] = this->result
;
4141 opcode
= TGSI_OPCODE_TXF
;
4142 ir
->lod_info
.sample_index
->accept(this);
4143 sample_index
= this->result
;
4146 opcode
= TGSI_OPCODE_TG4
;
4147 ir
->lod_info
.component
->accept(this);
4148 component
= this->result
;
4150 ir
->offset
->accept(this);
4151 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4152 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4153 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4154 offset
[i
] = this->result
;
4155 offset
[i
].index
+= i
* type_size(elt_type
);
4156 offset
[i
].type
= elt_type
->base_type
;
4157 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4158 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4161 offset
[0] = canonicalize_gather_offset(this->result
);
4166 opcode
= TGSI_OPCODE_LODQ
;
4168 case ir_texture_samples
:
4169 opcode
= TGSI_OPCODE_TXQS
;
4171 case ir_samples_identical
:
4172 unreachable("Unexpected ir_samples_identical opcode");
4175 if (ir
->projector
) {
4176 if (opcode
== TGSI_OPCODE_TEX
) {
4177 /* Slot the projector in as the last component of the coord. */
4178 coord_dst
.writemask
= WRITEMASK_W
;
4179 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4180 coord_dst
.writemask
= WRITEMASK_XYZW
;
4181 opcode
= TGSI_OPCODE_TXP
;
4183 st_src_reg coord_w
= coord
;
4184 coord_w
.swizzle
= SWIZZLE_WWWW
;
4186 /* For the other TEX opcodes there's no projective version
4187 * since the last slot is taken up by LOD info. Do the
4188 * projective divide now.
4190 coord_dst
.writemask
= WRITEMASK_W
;
4191 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4193 /* In the case where we have to project the coordinates "by hand,"
4194 * the shadow comparator value must also be projected.
4196 st_src_reg tmp_src
= coord
;
4197 if (ir
->shadow_comparitor
) {
4198 /* Slot the shadow value in as the second to last component of the
4201 ir
->shadow_comparitor
->accept(this);
4203 tmp_src
= get_temp(glsl_type::vec4_type
);
4204 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4206 /* Projective division not allowed for array samplers. */
4207 assert(!sampler_type
->sampler_array
);
4209 tmp_dst
.writemask
= WRITEMASK_Z
;
4210 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4212 tmp_dst
.writemask
= WRITEMASK_XY
;
4213 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4216 coord_dst
.writemask
= WRITEMASK_XYZ
;
4217 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4219 coord_dst
.writemask
= WRITEMASK_XYZW
;
4220 coord
.swizzle
= SWIZZLE_XYZW
;
4224 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4225 * comparator was put in the correct place (and projected) by the code,
4226 * above, that handles by-hand projection.
4228 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4229 /* Slot the shadow value in as the second to last component of the
4232 ir
->shadow_comparitor
->accept(this);
4234 if (is_cube_array
) {
4235 cube_sc
= get_temp(glsl_type::float_type
);
4236 cube_sc_dst
= st_dst_reg(cube_sc
);
4237 cube_sc_dst
.writemask
= WRITEMASK_X
;
4238 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4239 cube_sc_dst
.writemask
= WRITEMASK_X
;
4242 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4243 sampler_type
->sampler_array
) ||
4244 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4245 coord_dst
.writemask
= WRITEMASK_W
;
4247 coord_dst
.writemask
= WRITEMASK_Z
;
4249 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4250 coord_dst
.writemask
= WRITEMASK_XYZW
;
4254 if (ir
->op
== ir_txf_ms
) {
4255 coord_dst
.writemask
= WRITEMASK_W
;
4256 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4257 coord_dst
.writemask
= WRITEMASK_XYZW
;
4258 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4259 opcode
== TGSI_OPCODE_TXF
) {
4260 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4261 coord_dst
.writemask
= WRITEMASK_W
;
4262 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4263 coord_dst
.writemask
= WRITEMASK_XYZW
;
4266 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4267 &sampler_index
, &reladdr
, true);
4268 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4269 emit_arl(ir
, sampler_reladdr
, reladdr
);
4271 if (opcode
== TGSI_OPCODE_TXD
)
4272 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4273 else if (opcode
== TGSI_OPCODE_TXQ
) {
4274 if (ir
->op
== ir_query_levels
) {
4275 /* the level is stored in W */
4276 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4277 result_dst
.writemask
= WRITEMASK_X
;
4278 levels_src
.swizzle
= SWIZZLE_WWWW
;
4279 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4281 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4282 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4283 inst
= emit_asm(ir
, opcode
, result_dst
);
4284 } else if (opcode
== TGSI_OPCODE_TXF
) {
4285 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4286 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4287 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4288 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4289 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4290 } else if (opcode
== TGSI_OPCODE_TG4
) {
4291 if (is_cube_array
&& ir
->shadow_comparitor
) {
4292 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4294 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4297 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4299 if (ir
->shadow_comparitor
)
4300 inst
->tex_shadow
= GL_TRUE
;
4302 inst
->resource
.index
= sampler_index
;
4303 inst
->sampler_array_size
= sampler_array_size
;
4304 inst
->sampler_base
= sampler_base
;
4306 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4307 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4308 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4312 if (!inst
->tex_offsets
)
4313 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4315 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4316 inst
->tex_offsets
[i
] = offset
[i
];
4317 inst
->tex_offset_num_offset
= i
;
4320 switch (sampler_type
->sampler_dimensionality
) {
4321 case GLSL_SAMPLER_DIM_1D
:
4322 inst
->tex_target
= (sampler_type
->sampler_array
)
4323 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4325 case GLSL_SAMPLER_DIM_2D
:
4326 inst
->tex_target
= (sampler_type
->sampler_array
)
4327 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4329 case GLSL_SAMPLER_DIM_3D
:
4330 inst
->tex_target
= TEXTURE_3D_INDEX
;
4332 case GLSL_SAMPLER_DIM_CUBE
:
4333 inst
->tex_target
= (sampler_type
->sampler_array
)
4334 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4336 case GLSL_SAMPLER_DIM_RECT
:
4337 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4339 case GLSL_SAMPLER_DIM_BUF
:
4340 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4342 case GLSL_SAMPLER_DIM_EXTERNAL
:
4343 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4345 case GLSL_SAMPLER_DIM_MS
:
4346 inst
->tex_target
= (sampler_type
->sampler_array
)
4347 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4350 assert(!"Should not get here.");
4353 inst
->tex_type
= ir
->type
->base_type
;
4355 this->result
= result_src
;
4359 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4361 if (ir
->get_value()) {
4365 assert(current_function
);
4367 ir
->get_value()->accept(this);
4368 st_src_reg r
= this->result
;
4370 l
= st_dst_reg(current_function
->return_reg
);
4372 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4373 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4379 emit_asm(ir
, TGSI_OPCODE_RET
);
4383 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4385 if (ir
->condition
) {
4386 ir
->condition
->accept(this);
4387 st_src_reg condition
= this->result
;
4389 /* Convert the bool condition to a float so we can negate. */
4390 if (native_integers
) {
4391 st_src_reg temp
= get_temp(ir
->condition
->type
);
4392 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4393 condition
, st_src_reg_for_float(1.0));
4397 condition
.negate
= ~condition
.negate
;
4398 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4400 /* unconditional kil */
4401 emit_asm(ir
, TGSI_OPCODE_KILL
);
4406 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4409 glsl_to_tgsi_instruction
*if_inst
;
4411 ir
->condition
->accept(this);
4412 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4414 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4416 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4418 this->instructions
.push_tail(if_inst
);
4420 visit_exec_list(&ir
->then_instructions
, this);
4422 if (!ir
->else_instructions
.is_empty()) {
4423 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4424 visit_exec_list(&ir
->else_instructions
, this);
4427 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4432 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4434 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4436 ir
->stream
->accept(this);
4437 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4441 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4443 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4445 ir
->stream
->accept(this);
4446 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4450 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4452 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4453 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4455 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4458 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4460 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4462 result
.file
= PROGRAM_UNDEFINED
;
4469 num_input_arrays
= 0;
4470 num_output_arrays
= 0;
4471 next_signature_id
= 1;
4473 current_function
= NULL
;
4474 num_address_regs
= 0;
4478 indirect_addr_consts
= false;
4479 wpos_transform_const
= -1;
4481 native_integers
= false;
4482 mem_ctx
= ralloc_context(NULL
);
4485 shader_program
= NULL
;
4490 use_shared_memory
= false;
4493 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4496 ralloc_free(mem_ctx
);
4499 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4506 * Count resources used by the given gpu program (number of texture
4510 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4512 v
->samplers_used
= 0;
4513 v
->buffers_used
= 0;
4516 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4517 if (inst
->info
->is_tex
) {
4518 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4519 unsigned idx
= inst
->sampler_base
+ i
;
4520 v
->samplers_used
|= 1u << idx
;
4522 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4523 v
->sampler_types
[idx
] = inst
->tex_type
;
4524 v
->sampler_targets
[idx
] =
4525 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4527 if (inst
->tex_shadow
) {
4528 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4533 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4534 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4536 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4537 is_resource_instruction(inst
->op
) ||
4538 inst
->op
== TGSI_OPCODE_STORE
)) {
4539 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4540 v
->buffers_used
|= 1 << inst
->resource
.index
;
4541 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4542 v
->use_shared_memory
= true;
4544 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4545 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4546 unsigned idx
= inst
->sampler_base
+ i
;
4547 v
->images_used
|= 1 << idx
;
4548 v
->image_targets
[idx
] =
4549 st_translate_texture_target(inst
->tex_target
, false);
4550 v
->image_formats
[idx
] = inst
->image_format
;
4555 prog
->SamplersUsed
= v
->samplers_used
;
4557 if (v
->shader_program
!= NULL
)
4558 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4562 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4563 * are read from the given src in this instruction
4566 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4568 int read_mask
= 0, comp
;
4570 /* Now, given the src swizzle and the written channels, find which
4571 * components are actually read
4573 for (comp
= 0; comp
< 4; ++comp
) {
4574 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4576 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4577 read_mask
|= 1 << coord
;
4584 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4585 * instruction is the first instruction to write to register T0. There are
4586 * several lowering passes done in GLSL IR (e.g. branches and
4587 * relative addressing) that create a large number of conditional assignments
4588 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4590 * Here is why this conversion is safe:
4591 * CMP T0, T1 T2 T0 can be expanded to:
4597 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4598 * as the original program. If (T1 < 0.0) evaluates to false, executing
4599 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4600 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4601 * because any instruction that was going to read from T0 after this was going
4602 * to read a garbage value anyway.
4605 glsl_to_tgsi_visitor::simplify_cmp(void)
4607 int tempWritesSize
= 0;
4608 unsigned *tempWrites
= NULL
;
4609 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4611 memset(outputWrites
, 0, sizeof(outputWrites
));
4613 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4614 unsigned prevWriteMask
= 0;
4616 /* Give up if we encounter relative addressing or flow control. */
4617 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4618 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4619 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4620 inst
->op
== TGSI_OPCODE_BGNSUB
||
4621 inst
->op
== TGSI_OPCODE_CONT
||
4622 inst
->op
== TGSI_OPCODE_END
||
4623 inst
->op
== TGSI_OPCODE_ENDSUB
||
4624 inst
->op
== TGSI_OPCODE_RET
) {
4628 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4629 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4630 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4631 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4632 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4633 if (inst
->dst
[0].index
>= tempWritesSize
) {
4634 const int inc
= 4096;
4636 tempWrites
= (unsigned*)
4638 (tempWritesSize
+ inc
) * sizeof(unsigned));
4642 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4643 tempWritesSize
+= inc
;
4646 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4647 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4651 /* For a CMP to be considered a conditional write, the destination
4652 * register and source register two must be the same. */
4653 if (inst
->op
== TGSI_OPCODE_CMP
4654 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4655 && inst
->src
[2].file
== inst
->dst
[0].file
4656 && inst
->src
[2].index
== inst
->dst
[0].index
4657 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4659 inst
->op
= TGSI_OPCODE_MOV
;
4660 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4661 inst
->src
[0] = inst
->src
[1];
4668 /* Replaces all references to a temporary register index with another index. */
4670 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4672 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4675 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4676 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4677 for (k
= 0; k
< num_renames
; k
++)
4678 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4679 inst
->src
[j
].index
= renames
[k
].new_reg
;
4682 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4683 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4684 for (k
= 0; k
< num_renames
; k
++)
4685 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4686 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4689 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4690 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4691 for (k
= 0; k
< num_renames
; k
++)
4692 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4693 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4699 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4701 int depth
= 0; /* loop depth */
4702 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4705 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4706 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4707 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4708 if (first_reads
[inst
->src
[j
].index
] == -1)
4709 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4712 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4713 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4714 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4715 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4718 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4721 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4731 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4733 int depth
= 0; /* loop depth */
4734 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4737 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4738 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4739 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4740 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4742 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4743 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4744 if (first_writes
[inst
->dst
[j
].index
] == -1)
4745 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4746 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4749 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4750 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4751 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4753 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4756 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4759 for (k
= 0; k
< this->next_temp
; k
++) {
4760 if (last_reads
[k
] == -2) {
4772 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4774 int depth
= 0; /* loop depth */
4778 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4779 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4780 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4781 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4784 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4786 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4788 for (k
= 0; k
< this->next_temp
; k
++) {
4789 if (last_writes
[k
] == -2) {
4800 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4801 * channels for copy propagation and updates following instructions to
4802 * use the original versions.
4804 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4805 * will occur. As an example, a TXP production before this pass:
4807 * 0: MOV TEMP[1], INPUT[4].xyyy;
4808 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4809 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4813 * 0: MOV TEMP[1], INPUT[4].xyyy;
4814 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4815 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4817 * which allows for dead code elimination on TEMP[1]'s writes.
4820 glsl_to_tgsi_visitor::copy_propagate(void)
4822 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4823 glsl_to_tgsi_instruction
*,
4824 this->next_temp
* 4);
4825 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4828 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4829 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4830 || inst
->dst
[0].index
< this->next_temp
);
4832 /* First, do any copy propagation possible into the src regs. */
4833 for (int r
= 0; r
< 3; r
++) {
4834 glsl_to_tgsi_instruction
*first
= NULL
;
4836 int acp_base
= inst
->src
[r
].index
* 4;
4838 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4839 inst
->src
[r
].reladdr
||
4840 inst
->src
[r
].reladdr2
)
4843 /* See if we can find entries in the ACP consisting of MOVs
4844 * from the same src register for all the swizzled channels
4845 * of this src register reference.
4847 for (int i
= 0; i
< 4; i
++) {
4848 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4849 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4856 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4861 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4862 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4863 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4864 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4872 /* We've now validated that we can copy-propagate to
4873 * replace this src register reference. Do it.
4875 inst
->src
[r
].file
= first
->src
[0].file
;
4876 inst
->src
[r
].index
= first
->src
[0].index
;
4877 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4878 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4879 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4880 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4883 for (int i
= 0; i
< 4; i
++) {
4884 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4885 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4886 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4888 inst
->src
[r
].swizzle
= swizzle
;
4893 case TGSI_OPCODE_BGNLOOP
:
4894 case TGSI_OPCODE_ENDLOOP
:
4895 /* End of a basic block, clear the ACP entirely. */
4896 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4899 case TGSI_OPCODE_IF
:
4900 case TGSI_OPCODE_UIF
:
4904 case TGSI_OPCODE_ENDIF
:
4905 case TGSI_OPCODE_ELSE
:
4906 /* Clear all channels written inside the block from the ACP, but
4907 * leaving those that were not touched.
4909 for (int r
= 0; r
< this->next_temp
; r
++) {
4910 for (int c
= 0; c
< 4; c
++) {
4911 if (!acp
[4 * r
+ c
])
4914 if (acp_level
[4 * r
+ c
] >= level
)
4915 acp
[4 * r
+ c
] = NULL
;
4918 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4923 /* Continuing the block, clear any written channels from
4926 for (int d
= 0; d
< 2; d
++) {
4927 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4928 /* Any temporary might be written, so no copy propagation
4929 * across this instruction.
4931 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4932 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4933 inst
->dst
[d
].reladdr
) {
4934 /* Any output might be written, so no copy propagation
4935 * from outputs across this instruction.
4937 for (int r
= 0; r
< this->next_temp
; r
++) {
4938 for (int c
= 0; c
< 4; c
++) {
4939 if (!acp
[4 * r
+ c
])
4942 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4943 acp
[4 * r
+ c
] = NULL
;
4946 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4947 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4948 /* Clear where it's used as dst. */
4949 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4950 for (int c
= 0; c
< 4; c
++) {
4951 if (inst
->dst
[d
].writemask
& (1 << c
))
4952 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4956 /* Clear where it's used as src. */
4957 for (int r
= 0; r
< this->next_temp
; r
++) {
4958 for (int c
= 0; c
< 4; c
++) {
4959 if (!acp
[4 * r
+ c
])
4962 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4964 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4965 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4966 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4967 acp
[4 * r
+ c
] = NULL
;
4976 /* If this is a copy, add it to the ACP. */
4977 if (inst
->op
== TGSI_OPCODE_MOV
&&
4978 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4979 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4980 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4981 !inst
->dst
[0].reladdr
&&
4982 !inst
->dst
[0].reladdr2
&&
4984 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4985 !inst
->src
[0].reladdr
&&
4986 !inst
->src
[0].reladdr2
&&
4987 !inst
->src
[0].negate
) {
4988 for (int i
= 0; i
< 4; i
++) {
4989 if (inst
->dst
[0].writemask
& (1 << i
)) {
4990 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4991 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4997 ralloc_free(acp_level
);
5002 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5005 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5006 * will occur. As an example, a TXP production after copy propagation but
5009 * 0: MOV TEMP[1], INPUT[4].xyyy;
5010 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5011 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5013 * and after this pass:
5015 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5018 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5020 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5021 glsl_to_tgsi_instruction
*,
5022 this->next_temp
* 4);
5023 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5027 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5028 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5029 || inst
->dst
[0].index
< this->next_temp
);
5032 case TGSI_OPCODE_BGNLOOP
:
5033 case TGSI_OPCODE_ENDLOOP
:
5034 case TGSI_OPCODE_CONT
:
5035 case TGSI_OPCODE_BRK
:
5036 /* End of a basic block, clear the write array entirely.
5038 * This keeps us from killing dead code when the writes are
5039 * on either side of a loop, even when the register isn't touched
5040 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5041 * dead code of this type, so it shouldn't make a difference as long as
5042 * the dead code elimination pass in the GLSL compiler does its job.
5044 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5047 case TGSI_OPCODE_ENDIF
:
5048 case TGSI_OPCODE_ELSE
:
5049 /* Promote the recorded level of all channels written inside the
5050 * preceding if or else block to the level above the if/else block.
5052 for (int r
= 0; r
< this->next_temp
; r
++) {
5053 for (int c
= 0; c
< 4; c
++) {
5054 if (!writes
[4 * r
+ c
])
5057 if (write_level
[4 * r
+ c
] == level
)
5058 write_level
[4 * r
+ c
] = level
-1;
5061 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5065 case TGSI_OPCODE_IF
:
5066 case TGSI_OPCODE_UIF
:
5068 /* fallthrough to default case to mark the condition as read */
5070 /* Continuing the block, clear any channels from the write array that
5071 * are read by this instruction.
5073 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5074 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5075 /* Any temporary might be read, so no dead code elimination
5076 * across this instruction.
5078 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5079 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5080 /* Clear where it's used as src. */
5081 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5082 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5083 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5084 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5086 for (int c
= 0; c
< 4; c
++) {
5087 if (src_chans
& (1 << c
))
5088 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5092 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5093 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5094 /* Any temporary might be read, so no dead code elimination
5095 * across this instruction.
5097 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5098 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5099 /* Clear where it's used as src. */
5100 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5101 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5102 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5103 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5105 for (int c
= 0; c
< 4; c
++) {
5106 if (src_chans
& (1 << c
))
5107 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5114 /* If this instruction writes to a temporary, add it to the write array.
5115 * If there is already an instruction in the write array for one or more
5116 * of the channels, flag that channel write as dead.
5118 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5119 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5120 !inst
->dst
[i
].reladdr
) {
5121 for (int c
= 0; c
< 4; c
++) {
5122 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5123 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5124 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5127 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5129 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5130 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5137 /* Anything still in the write array at this point is dead code. */
5138 for (int r
= 0; r
< this->next_temp
; r
++) {
5139 for (int c
= 0; c
< 4; c
++) {
5140 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5142 inst
->dead_mask
|= (1 << c
);
5146 /* Now actually remove the instructions that are completely dead and update
5147 * the writemask of other instructions with dead channels.
5149 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5150 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5152 /* No amount of dead masks should remove memory stores */
5153 if (inst
->info
->is_store
)
5156 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5161 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5162 if (inst
->dead_mask
== WRITEMASK_XY
||
5163 inst
->dead_mask
== WRITEMASK_ZW
)
5164 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5166 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5170 ralloc_free(write_level
);
5171 ralloc_free(writes
);
5176 /* merge DFRACEXP instructions into one. */
5178 glsl_to_tgsi_visitor::merge_two_dsts(void)
5180 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5181 glsl_to_tgsi_instruction
*inst2
;
5183 if (num_inst_dst_regs(inst
) != 2)
5186 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5187 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5190 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5193 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5194 inst
->src
[0].index
== inst2
->src
[0].index
&&
5195 inst
->src
[0].type
== inst2
->src
[0].type
&&
5196 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5198 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5204 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5206 inst
->dst
[0] = inst2
->dst
[0];
5207 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5208 inst
->dst
[1] = inst2
->dst
[1];
5219 /* Merges temporary registers together where possible to reduce the number of
5220 * registers needed to run a program.
5222 * Produces optimal code only after copy propagation and dead code elimination
5225 glsl_to_tgsi_visitor::merge_registers(void)
5227 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5228 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5229 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5231 int num_renames
= 0;
5233 /* Read the indices of the last read and first write to each temp register
5234 * into an array so that we don't have to traverse the instruction list as
5236 for (i
= 0; i
< this->next_temp
; i
++) {
5238 first_writes
[i
] = -1;
5240 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5242 /* Start looking for registers with non-overlapping usages that can be
5243 * merged together. */
5244 for (i
= 0; i
< this->next_temp
; i
++) {
5245 /* Don't touch unused registers. */
5246 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5248 for (j
= 0; j
< this->next_temp
; j
++) {
5249 /* Don't touch unused registers. */
5250 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5252 /* We can merge the two registers if the first write to j is after or
5253 * in the same instruction as the last read from i. Note that the
5254 * register at index i will always be used earlier or at the same time
5255 * as the register at index j. */
5256 if (first_writes
[i
] <= first_writes
[j
] &&
5257 last_reads
[i
] <= first_writes
[j
]) {
5258 renames
[num_renames
].old_reg
= j
;
5259 renames
[num_renames
].new_reg
= i
;
5262 /* Update the first_writes and last_reads arrays with the new
5263 * values for the merged register index, and mark the newly unused
5264 * register index as such. */
5265 assert(last_reads
[j
] >= last_reads
[i
]);
5266 last_reads
[i
] = last_reads
[j
];
5267 first_writes
[j
] = -1;
5273 rename_temp_registers(num_renames
, renames
);
5274 ralloc_free(renames
);
5275 ralloc_free(last_reads
);
5276 ralloc_free(first_writes
);
5279 /* Reassign indices to temporary registers by reusing unused indices created
5280 * by optimization passes. */
5282 glsl_to_tgsi_visitor::renumber_registers(void)
5286 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5287 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5288 int num_renames
= 0;
5289 for (i
= 0; i
< this->next_temp
; i
++) {
5290 first_reads
[i
] = -1;
5292 get_first_temp_read(first_reads
);
5294 for (i
= 0; i
< this->next_temp
; i
++) {
5295 if (first_reads
[i
] < 0) continue;
5296 if (i
!= new_index
) {
5297 renames
[num_renames
].old_reg
= i
;
5298 renames
[num_renames
].new_reg
= new_index
;
5304 rename_temp_registers(num_renames
, renames
);
5305 this->next_temp
= new_index
;
5306 ralloc_free(renames
);
5307 ralloc_free(first_reads
);
5310 /* ------------------------- TGSI conversion stuff -------------------------- */
5312 unsigned branch_target
;
5317 * Intermediate state used during shader translation.
5319 struct st_translate
{
5320 struct ureg_program
*ureg
;
5322 unsigned temps_size
;
5323 struct ureg_dst
*temps
;
5325 struct ureg_dst
*arrays
;
5326 unsigned num_temp_arrays
;
5327 struct ureg_src
*constants
;
5329 struct ureg_src
*immediates
;
5331 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5332 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5333 struct ureg_dst address
[3];
5334 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5335 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5336 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5337 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5338 struct ureg_src shared_memory
;
5339 unsigned *array_sizes
;
5340 struct inout_decl
*input_decls
;
5341 unsigned num_input_decls
;
5342 struct inout_decl
*output_decls
;
5343 unsigned num_output_decls
;
5345 const GLuint
*inputMapping
;
5346 const GLuint
*outputMapping
;
5348 /* For every instruction that contains a label (eg CALL), keep
5349 * details so that we can go back afterwards and emit the correct
5350 * tgsi instruction number for each label.
5352 struct label
*labels
;
5353 unsigned labels_size
;
5354 unsigned labels_count
;
5356 /* Keep a record of the tgsi instruction number that each mesa
5357 * instruction starts at, will be used to fix up labels after
5362 unsigned insn_count
;
5364 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5369 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5371 _mesa_sysval_to_semantic(unsigned sysval
)
5375 case SYSTEM_VALUE_VERTEX_ID
:
5376 return TGSI_SEMANTIC_VERTEXID
;
5377 case SYSTEM_VALUE_INSTANCE_ID
:
5378 return TGSI_SEMANTIC_INSTANCEID
;
5379 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5380 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5381 case SYSTEM_VALUE_BASE_VERTEX
:
5382 return TGSI_SEMANTIC_BASEVERTEX
;
5383 case SYSTEM_VALUE_BASE_INSTANCE
:
5384 return TGSI_SEMANTIC_BASEINSTANCE
;
5385 case SYSTEM_VALUE_DRAW_ID
:
5386 return TGSI_SEMANTIC_DRAWID
;
5388 /* Geometry shader */
5389 case SYSTEM_VALUE_INVOCATION_ID
:
5390 return TGSI_SEMANTIC_INVOCATIONID
;
5392 /* Fragment shader */
5393 case SYSTEM_VALUE_FRAG_COORD
:
5394 return TGSI_SEMANTIC_POSITION
;
5395 case SYSTEM_VALUE_FRONT_FACE
:
5396 return TGSI_SEMANTIC_FACE
;
5397 case SYSTEM_VALUE_SAMPLE_ID
:
5398 return TGSI_SEMANTIC_SAMPLEID
;
5399 case SYSTEM_VALUE_SAMPLE_POS
:
5400 return TGSI_SEMANTIC_SAMPLEPOS
;
5401 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5402 return TGSI_SEMANTIC_SAMPLEMASK
;
5403 case SYSTEM_VALUE_HELPER_INVOCATION
:
5404 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5406 /* Tessellation shader */
5407 case SYSTEM_VALUE_TESS_COORD
:
5408 return TGSI_SEMANTIC_TESSCOORD
;
5409 case SYSTEM_VALUE_VERTICES_IN
:
5410 return TGSI_SEMANTIC_VERTICESIN
;
5411 case SYSTEM_VALUE_PRIMITIVE_ID
:
5412 return TGSI_SEMANTIC_PRIMID
;
5413 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5414 return TGSI_SEMANTIC_TESSOUTER
;
5415 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5416 return TGSI_SEMANTIC_TESSINNER
;
5418 /* Compute shader */
5419 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5420 return TGSI_SEMANTIC_THREAD_ID
;
5421 case SYSTEM_VALUE_WORK_GROUP_ID
:
5422 return TGSI_SEMANTIC_BLOCK_ID
;
5423 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5424 return TGSI_SEMANTIC_GRID_SIZE
;
5425 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5426 return TGSI_SEMANTIC_BLOCK_SIZE
;
5429 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5430 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5431 case SYSTEM_VALUE_VERTEX_CNT
:
5433 assert(!"Unexpected SYSTEM_VALUE_ enum");
5434 return TGSI_SEMANTIC_COUNT
;
5440 * Make note of a branch to a label in the TGSI code.
5441 * After we've emitted all instructions, we'll go over the list
5442 * of labels built here and patch the TGSI code with the actual
5443 * location of each label.
5445 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5449 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5450 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5451 t
->labels
= (struct label
*)realloc(t
->labels
,
5452 t
->labels_size
* sizeof(struct label
));
5453 if (t
->labels
== NULL
) {
5454 static unsigned dummy
;
5460 i
= t
->labels_count
++;
5461 t
->labels
[i
].branch_target
= branch_target
;
5462 return &t
->labels
[i
].token
;
5466 * Called prior to emitting the TGSI code for each instruction.
5467 * Allocate additional space for instructions if needed.
5468 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5469 * the next TGSI instruction.
5471 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5473 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5474 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5475 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5476 if (t
->insn
== NULL
) {
5482 t
->insn
[t
->insn_count
++] = start
;
5486 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5488 static struct ureg_src
5489 emit_immediate(struct st_translate
*t
,
5490 gl_constant_value values
[4],
5493 struct ureg_program
*ureg
= t
->ureg
;
5498 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5500 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5502 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5503 case GL_UNSIGNED_INT
:
5505 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5507 assert(!"should not get here - type must be float, int, uint, or bool");
5508 return ureg_src_undef();
5513 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5515 static struct ureg_dst
5516 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5522 case PROGRAM_UNDEFINED
:
5523 return ureg_dst_undef();
5525 case PROGRAM_TEMPORARY
:
5526 /* Allocate space for temporaries on demand. */
5527 if (index
>= t
->temps_size
) {
5528 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5530 t
->temps
= (struct ureg_dst
*)
5532 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5534 return ureg_dst_undef();
5536 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5537 t
->temps_size
+= inc
;
5540 if (ureg_dst_is_undef(t
->temps
[index
]))
5541 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5543 return t
->temps
[index
];
5546 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5547 array
= array_id
- 1;
5549 if (ureg_dst_is_undef(t
->arrays
[array
]))
5550 t
->arrays
[array
] = ureg_DECL_array_temporary(
5551 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5553 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5555 case PROGRAM_OUTPUT
:
5557 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5558 assert(index
< 2 * FRAG_RESULT_MAX
);
5559 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5560 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5561 assert(index
< VARYING_SLOT_TESS_MAX
);
5563 assert(index
< VARYING_SLOT_MAX
);
5565 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5566 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5567 return t
->outputs
[t
->outputMapping
[index
]];
5570 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5571 unsigned mesa_index
= decl
->mesa_index
;
5572 int slot
= t
->outputMapping
[mesa_index
];
5574 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5576 struct ureg_dst dst
= t
->outputs
[slot
];
5577 dst
.ArrayID
= array_id
;
5578 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5581 case PROGRAM_ADDRESS
:
5582 return t
->address
[index
];
5585 assert(!"unknown dst register file");
5586 return ureg_dst_undef();
5591 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5593 static struct ureg_src
5594 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5596 int index
= reg
->index
;
5597 int double_reg2
= reg
->double_reg2
? 1 : 0;
5600 case PROGRAM_UNDEFINED
:
5601 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5603 case PROGRAM_TEMPORARY
:
5605 case PROGRAM_OUTPUT
:
5606 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5608 case PROGRAM_UNIFORM
:
5609 assert(reg
->index
>= 0);
5610 return reg
->index
< t
->num_constants
?
5611 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5612 case PROGRAM_STATE_VAR
:
5613 case PROGRAM_CONSTANT
: /* ie, immediate */
5614 if (reg
->has_index2
)
5615 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5617 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5618 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5620 case PROGRAM_IMMEDIATE
:
5621 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5622 return t
->immediates
[reg
->index
];
5625 /* GLSL inputs are 64-bit containers, so we have to
5626 * map back to the original index and add the offset after
5628 index
-= double_reg2
;
5629 if (!reg
->array_id
) {
5630 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5631 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5632 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5635 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5636 unsigned mesa_index
= decl
->mesa_index
;
5637 int slot
= t
->inputMapping
[mesa_index
];
5639 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5641 struct ureg_src src
= t
->inputs
[slot
];
5642 src
.ArrayID
= reg
->array_id
;
5643 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5646 case PROGRAM_ADDRESS
:
5647 return ureg_src(t
->address
[reg
->index
]);
5649 case PROGRAM_SYSTEM_VALUE
:
5650 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5651 return t
->systemValues
[reg
->index
];
5654 assert(!"unknown src register file");
5655 return ureg_src_undef();
5660 * Create a TGSI ureg_dst register from an st_dst_reg.
5662 static struct ureg_dst
5663 translate_dst(struct st_translate
*t
,
5664 const st_dst_reg
*dst_reg
,
5667 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5670 if (dst
.File
== TGSI_FILE_NULL
)
5673 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5676 dst
= ureg_saturate(dst
);
5678 if (dst_reg
->reladdr
!= NULL
) {
5679 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5680 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5683 if (dst_reg
->has_index2
) {
5684 if (dst_reg
->reladdr2
)
5685 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5688 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5695 * Create a TGSI ureg_src register from an st_src_reg.
5697 static struct ureg_src
5698 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5700 struct ureg_src src
= src_register(t
, src_reg
);
5702 if (src_reg
->has_index2
) {
5703 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5704 * and UBO constant buffers (buffer, position).
5706 if (src_reg
->reladdr2
)
5707 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5710 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5713 src
= ureg_swizzle(src
,
5714 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5715 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5716 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5717 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5719 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5720 src
= ureg_negate(src
);
5722 if (src_reg
->reladdr
!= NULL
) {
5723 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5724 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5730 static struct tgsi_texture_offset
5731 translate_tex_offset(struct st_translate
*t
,
5732 const st_src_reg
*in_offset
)
5734 struct tgsi_texture_offset offset
;
5735 struct ureg_src src
= translate_src(t
, in_offset
);
5737 offset
.File
= src
.File
;
5738 offset
.Index
= src
.Index
;
5739 offset
.SwizzleX
= src
.SwizzleX
;
5740 offset
.SwizzleY
= src
.SwizzleY
;
5741 offset
.SwizzleZ
= src
.SwizzleZ
;
5744 assert(!src
.Indirect
);
5745 assert(!src
.DimIndirect
);
5746 assert(!src
.Dimension
);
5747 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5748 assert(!src
.Negate
);
5754 compile_tgsi_instruction(struct st_translate
*t
,
5755 const glsl_to_tgsi_instruction
*inst
)
5757 struct ureg_program
*ureg
= t
->ureg
;
5759 struct ureg_dst dst
[2];
5760 struct ureg_src src
[4];
5761 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5765 unsigned tex_target
= 0;
5767 num_dst
= num_inst_dst_regs(inst
);
5768 num_src
= num_inst_src_regs(inst
);
5770 for (i
= 0; i
< num_dst
; i
++)
5771 dst
[i
] = translate_dst(t
,
5775 for (i
= 0; i
< num_src
; i
++)
5776 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5779 case TGSI_OPCODE_BGNLOOP
:
5780 case TGSI_OPCODE_CAL
:
5781 case TGSI_OPCODE_ELSE
:
5782 case TGSI_OPCODE_ENDLOOP
:
5783 case TGSI_OPCODE_IF
:
5784 case TGSI_OPCODE_UIF
:
5785 assert(num_dst
== 0);
5786 ureg_label_insn(ureg
,
5790 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5793 case TGSI_OPCODE_TEX
:
5794 case TGSI_OPCODE_TXB
:
5795 case TGSI_OPCODE_TXD
:
5796 case TGSI_OPCODE_TXL
:
5797 case TGSI_OPCODE_TXP
:
5798 case TGSI_OPCODE_TXQ
:
5799 case TGSI_OPCODE_TXQS
:
5800 case TGSI_OPCODE_TXF
:
5801 case TGSI_OPCODE_TEX2
:
5802 case TGSI_OPCODE_TXB2
:
5803 case TGSI_OPCODE_TXL2
:
5804 case TGSI_OPCODE_TG4
:
5805 case TGSI_OPCODE_LODQ
:
5806 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5807 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5808 if (inst
->resource
.reladdr
)
5810 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5812 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5813 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5815 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5821 texoffsets
, inst
->tex_offset_num_offset
,
5825 case TGSI_OPCODE_RESQ
:
5826 case TGSI_OPCODE_LOAD
:
5827 case TGSI_OPCODE_ATOMUADD
:
5828 case TGSI_OPCODE_ATOMXCHG
:
5829 case TGSI_OPCODE_ATOMCAS
:
5830 case TGSI_OPCODE_ATOMAND
:
5831 case TGSI_OPCODE_ATOMOR
:
5832 case TGSI_OPCODE_ATOMXOR
:
5833 case TGSI_OPCODE_ATOMUMIN
:
5834 case TGSI_OPCODE_ATOMUMAX
:
5835 case TGSI_OPCODE_ATOMIMIN
:
5836 case TGSI_OPCODE_ATOMIMAX
:
5837 for (i
= num_src
- 1; i
>= 0; i
--)
5838 src
[i
+ 1] = src
[i
];
5840 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5841 src
[0] = t
->shared_memory
;
5842 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5843 src
[0] = t
->buffers
[inst
->resource
.index
];
5845 src
[0] = t
->images
[inst
->resource
.index
];
5846 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5848 if (inst
->resource
.reladdr
)
5849 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5850 assert(src
[0].File
!= TGSI_FILE_NULL
);
5851 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5852 inst
->buffer_access
,
5853 tex_target
, inst
->image_format
);
5856 case TGSI_OPCODE_STORE
:
5857 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5858 dst
[0] = ureg_dst(t
->shared_memory
);
5859 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5860 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5862 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5863 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5865 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5866 if (inst
->resource
.reladdr
)
5867 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5868 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5869 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5870 inst
->buffer_access
,
5871 tex_target
, inst
->image_format
);
5874 case TGSI_OPCODE_SCS
:
5875 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5876 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5889 * Emit the TGSI instructions for inverting and adjusting WPOS.
5890 * This code is unavoidable because it also depends on whether
5891 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5894 emit_wpos_adjustment(struct gl_context
*ctx
,
5895 struct st_translate
*t
,
5896 int wpos_transform_const
,
5898 GLfloat adjX
, GLfloat adjY
[2])
5900 struct ureg_program
*ureg
= t
->ureg
;
5902 assert(wpos_transform_const
>= 0);
5904 /* Fragment program uses fragment position input.
5905 * Need to replace instances of INPUT[WPOS] with temp T
5906 * where T = INPUT[WPOS] is inverted by Y.
5908 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5909 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5910 struct ureg_src
*wpos
=
5911 ctx
->Const
.GLSLFragCoordIsSysVal
?
5912 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5913 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5914 struct ureg_src wpos_input
= *wpos
;
5916 /* First, apply the coordinate shift: */
5917 if (adjX
|| adjY
[0] || adjY
[1]) {
5918 if (adjY
[0] != adjY
[1]) {
5919 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5920 * depending on whether inversion is actually going to be applied
5921 * or not, which is determined by testing against the inversion
5922 * state variable used below, which will be either +1 or -1.
5924 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5926 ureg_CMP(ureg
, adj_temp
,
5927 ureg_scalar(wpostrans
, invert
? 2 : 0),
5928 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5929 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5930 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5932 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5933 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5935 wpos_input
= ureg_src(wpos_temp
);
5937 /* MOV wpos_temp, input[wpos]
5939 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5942 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5943 * inversion/identity, or the other way around if we're drawing to an FBO.
5946 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5949 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5951 ureg_scalar(wpostrans
, 0),
5952 ureg_scalar(wpostrans
, 1));
5954 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5957 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5959 ureg_scalar(wpostrans
, 2),
5960 ureg_scalar(wpostrans
, 3));
5963 /* Use wpos_temp as position input from here on:
5965 *wpos
= ureg_src(wpos_temp
);
5970 * Emit fragment position/ooordinate code.
5973 emit_wpos(struct st_context
*st
,
5974 struct st_translate
*t
,
5975 const struct gl_program
*program
,
5976 struct ureg_program
*ureg
,
5977 int wpos_transform_const
)
5979 const struct gl_fragment_program
*fp
=
5980 (const struct gl_fragment_program
*) program
;
5981 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5982 GLfloat adjX
= 0.0f
;
5983 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5984 boolean invert
= FALSE
;
5986 /* Query the pixel center conventions supported by the pipe driver and set
5987 * adjX, adjY to help out if it cannot handle the requested one internally.
5989 * The bias of the y-coordinate depends on whether y-inversion takes place
5990 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5991 * drawing to an FBO (causes additional inversion), and whether the pipe
5992 * driver origin and the requested origin differ (the latter condition is
5993 * stored in the 'invert' variable).
5995 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5997 * center shift only:
6002 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6003 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6004 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6005 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6007 * inversion and center shift:
6008 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6009 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6010 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6011 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6013 if (fp
->OriginUpperLeft
) {
6014 /* Fragment shader wants origin in upper-left */
6015 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6016 /* the driver supports upper-left origin */
6018 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6019 /* the driver supports lower-left origin, need to invert Y */
6020 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6021 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6028 /* Fragment shader wants origin in lower-left */
6029 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6030 /* the driver supports lower-left origin */
6031 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6032 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6033 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6034 /* the driver supports upper-left origin, need to invert Y */
6040 if (fp
->PixelCenterInteger
) {
6041 /* Fragment shader wants pixel center integer */
6042 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6043 /* the driver supports pixel center integer */
6045 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6046 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6048 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6049 /* the driver supports pixel center half integer, need to bias X,Y */
6058 /* Fragment shader wants pixel center half integer */
6059 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6060 /* the driver supports pixel center half integer */
6062 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6063 /* the driver supports pixel center integer, need to bias X,Y */
6064 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6065 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6066 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6072 /* we invert after adjustment so that we avoid the MOV to temporary,
6073 * and reuse the adjustment ADD instead */
6074 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6078 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6079 * TGSI uses +1 for front, -1 for back.
6080 * This function converts the TGSI value to the GL value. Simply clamping/
6081 * saturating the value to [0,1] does the job.
6084 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6086 struct ureg_program
*ureg
= t
->ureg
;
6087 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6088 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6090 if (ctx
->Const
.NativeIntegers
) {
6091 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6094 /* MOV_SAT face_temp, input[face] */
6095 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6098 /* Use face_temp as face input from here on: */
6099 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6103 emit_compute_block_size(const struct gl_program
*program
,
6104 struct ureg_program
*ureg
) {
6105 const struct gl_compute_program
*cp
=
6106 (const struct gl_compute_program
*)program
;
6108 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6110 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6112 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6117 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6118 * \param program the program to translate
6119 * \param numInputs number of input registers used
6120 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6122 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6123 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6125 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6126 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
6127 * \param numOutputs number of output registers used
6128 * \param outputMapping maps Mesa fragment program outputs to TGSI
6130 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6131 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6134 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6136 extern "C" enum pipe_error
6137 st_translate_program(
6138 struct gl_context
*ctx
,
6140 struct ureg_program
*ureg
,
6141 glsl_to_tgsi_visitor
*program
,
6142 const struct gl_program
*proginfo
,
6144 const GLuint inputMapping
[],
6145 const GLuint inputSlotToAttr
[],
6146 const ubyte inputSemanticName
[],
6147 const ubyte inputSemanticIndex
[],
6148 const GLuint interpMode
[],
6149 const GLuint interpLocation
[],
6151 const GLuint outputMapping
[],
6152 const GLuint outputSlotToAttr
[],
6153 const ubyte outputSemanticName
[],
6154 const ubyte outputSemanticIndex
[])
6156 struct st_translate
*t
;
6158 struct gl_program_constants
*frag_const
=
6159 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6160 enum pipe_error ret
= PIPE_OK
;
6162 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6163 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6165 t
= CALLOC_STRUCT(st_translate
);
6167 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6171 t
->procType
= procType
;
6172 t
->inputMapping
= inputMapping
;
6173 t
->outputMapping
= outputMapping
;
6175 t
->num_temp_arrays
= program
->next_array
;
6176 if (t
->num_temp_arrays
)
6177 t
->arrays
= (struct ureg_dst
*)
6178 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6181 * Declare input attributes.
6184 case PIPE_SHADER_FRAGMENT
:
6185 case PIPE_SHADER_GEOMETRY
:
6186 case PIPE_SHADER_TESS_EVAL
:
6187 case PIPE_SHADER_TESS_CTRL
:
6188 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6189 struct inout_decl
*decl
= &program
->inputs
[i
];
6190 unsigned slot
= inputMapping
[decl
->mesa_index
];
6191 struct ureg_src src
;
6192 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6194 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6195 if (tgsi_usage_mask
== 1)
6196 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6197 else if (tgsi_usage_mask
== 2)
6198 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6200 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6203 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6204 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6205 interpMode
? interpMode
[slot
] : 0, 0, interpLocation
? interpLocation
[slot
] : 0,
6206 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6208 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6209 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6210 /* The ArrayID is set up in dst_register */
6211 t
->inputs
[slot
+ j
] = src
;
6212 t
->inputs
[slot
+ j
].ArrayID
= 0;
6213 t
->inputs
[slot
+ j
].Index
+= j
;
6218 case PIPE_SHADER_VERTEX
:
6219 for (i
= 0; i
< numInputs
; i
++) {
6220 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6223 case PIPE_SHADER_COMPUTE
:
6230 * Declare output attributes.
6233 case PIPE_SHADER_FRAGMENT
:
6234 case PIPE_SHADER_COMPUTE
:
6236 case PIPE_SHADER_GEOMETRY
:
6237 case PIPE_SHADER_TESS_EVAL
:
6238 case PIPE_SHADER_TESS_CTRL
:
6239 case PIPE_SHADER_VERTEX
:
6240 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6241 struct inout_decl
*decl
= &program
->outputs
[i
];
6242 unsigned slot
= outputMapping
[decl
->mesa_index
];
6243 struct ureg_dst dst
;
6244 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6246 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6247 if (tgsi_usage_mask
== 1)
6248 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6249 else if (tgsi_usage_mask
== 2)
6250 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6252 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6255 dst
= ureg_DECL_output_layout(ureg
,
6256 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6257 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6259 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6260 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6261 /* The ArrayID is set up in dst_register */
6262 t
->outputs
[slot
+ j
] = dst
;
6263 t
->outputs
[slot
+ j
].ArrayID
= 0;
6264 t
->outputs
[slot
+ j
].Index
+= j
;
6273 if (procType
== PIPE_SHADER_FRAGMENT
) {
6274 if (program
->shader
->info
.EarlyFragmentTests
)
6275 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6277 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6278 /* Must do this after setting up t->inputs. */
6279 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6280 program
->wpos_transform_const
);
6283 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6284 emit_face_var(ctx
, t
);
6286 for (i
= 0; i
< numOutputs
; i
++) {
6287 switch (outputSemanticName
[i
]) {
6288 case TGSI_SEMANTIC_POSITION
:
6289 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6290 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6291 outputSemanticIndex
[i
]);
6292 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6294 case TGSI_SEMANTIC_STENCIL
:
6295 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6296 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6297 outputSemanticIndex
[i
]);
6298 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6300 case TGSI_SEMANTIC_COLOR
:
6301 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6302 TGSI_SEMANTIC_COLOR
,
6303 outputSemanticIndex
[i
]);
6305 case TGSI_SEMANTIC_SAMPLEMASK
:
6306 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6307 TGSI_SEMANTIC_SAMPLEMASK
,
6308 outputSemanticIndex
[i
]);
6309 /* TODO: If we ever support more than 32 samples, this will have
6310 * to become an array.
6312 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6315 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6316 ret
= PIPE_ERROR_BAD_INPUT
;
6321 else if (procType
== PIPE_SHADER_VERTEX
) {
6322 for (i
= 0; i
< numOutputs
; i
++) {
6323 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6324 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6326 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6327 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6328 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6333 if (procType
== PIPE_SHADER_COMPUTE
) {
6334 emit_compute_block_size(proginfo
, ureg
);
6337 /* Declare address register.
6339 if (program
->num_address_regs
> 0) {
6340 assert(program
->num_address_regs
<= 3);
6341 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6342 t
->address
[i
] = ureg_DECL_address(ureg
);
6345 /* Declare misc input registers
6348 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6350 for (i
= 0; sysInputs
; i
++) {
6351 if (sysInputs
& (1 << i
)) {
6352 unsigned semName
= _mesa_sysval_to_semantic(i
);
6354 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6356 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6357 semName
== TGSI_SEMANTIC_VERTEXID
) {
6358 /* From Gallium perspective, these system values are always
6359 * integer, and require native integer support. However, if
6360 * native integer is supported on the vertex stage but not the
6361 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6362 * assumes these system values are floats. To resolve the
6363 * inconsistency, we insert a U2F.
6365 struct st_context
*st
= st_context(ctx
);
6366 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6367 assert(procType
== PIPE_SHADER_VERTEX
);
6368 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6370 if (!ctx
->Const
.NativeIntegers
) {
6371 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6372 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6373 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6377 if (procType
== PIPE_SHADER_FRAGMENT
&&
6378 semName
== TGSI_SEMANTIC_POSITION
)
6379 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6380 program
->wpos_transform_const
);
6382 sysInputs
&= ~(1 << i
);
6387 t
->array_sizes
= program
->array_sizes
;
6388 t
->input_decls
= program
->inputs
;
6389 t
->num_input_decls
= program
->num_inputs
;
6390 t
->output_decls
= program
->outputs
;
6391 t
->num_output_decls
= program
->num_outputs
;
6393 /* Emit constants and uniforms. TGSI uses a single index space for these,
6394 * so we put all the translated regs in t->constants.
6396 if (proginfo
->Parameters
) {
6397 t
->constants
= (struct ureg_src
*)
6398 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6399 if (t
->constants
== NULL
) {
6400 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6403 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6405 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6406 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6407 case PROGRAM_STATE_VAR
:
6408 case PROGRAM_UNIFORM
:
6409 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6412 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6413 * addressing of the const buffer.
6414 * FIXME: Be smarter and recognize param arrays:
6415 * indirect addressing is only valid within the referenced
6418 case PROGRAM_CONSTANT
:
6419 if (program
->indirect_addr_consts
)
6420 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6422 t
->constants
[i
] = emit_immediate(t
,
6423 proginfo
->Parameters
->ParameterValues
[i
],
6424 proginfo
->Parameters
->Parameters
[i
].DataType
,
6433 if (program
->shader
) {
6434 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6436 for (i
= 0; i
< num_ubos
; i
++) {
6437 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6438 unsigned num_const_vecs
= (size
+ 15) / 16;
6439 unsigned first
, last
;
6440 assert(num_const_vecs
> 0);
6442 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6443 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6447 /* Emit immediate values.
6449 t
->immediates
= (struct ureg_src
*)
6450 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6451 if (t
->immediates
== NULL
) {
6452 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6455 t
->num_immediates
= program
->num_immediates
;
6458 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6459 assert(i
< program
->num_immediates
);
6460 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6462 assert(i
== program
->num_immediates
);
6464 /* texture samplers */
6465 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6466 if (program
->samplers_used
& (1u << i
)) {
6469 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6471 switch (program
->sampler_types
[i
]) {
6473 type
= TGSI_RETURN_TYPE_SINT
;
6475 case GLSL_TYPE_UINT
:
6476 type
= TGSI_RETURN_TYPE_UINT
;
6478 case GLSL_TYPE_FLOAT
:
6479 type
= TGSI_RETURN_TYPE_FLOAT
;
6482 unreachable("not reached");
6485 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6486 type
, type
, type
, type
);
6490 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6491 if (program
->buffers_used
& (1 << i
)) {
6492 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6496 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6498 if (program
->buffers_used
& (1 << i
)) {
6499 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6503 if (program
->use_shared_memory
)
6504 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6506 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6507 if (program
->images_used
& (1 << i
)) {
6508 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6509 program
->image_targets
[i
],
6510 program
->image_formats
[i
],
6515 /* Emit each instruction in turn:
6517 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6518 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6519 compile_tgsi_instruction(t
, inst
);
6522 /* Fix up all emitted labels:
6524 for (i
= 0; i
< t
->labels_count
; i
++) {
6525 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6526 t
->insn
[t
->labels
[i
].branch_target
]);
6529 /* Set the next shader stage hint for VS and TES. */
6531 case PIPE_SHADER_VERTEX
:
6532 case PIPE_SHADER_TESS_EVAL
:
6533 if (program
->shader_program
->SeparateShader
)
6536 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6537 if (program
->shader_program
->_LinkedShaders
[i
]) {
6541 case MESA_SHADER_TESS_CTRL
:
6542 next
= PIPE_SHADER_TESS_CTRL
;
6544 case MESA_SHADER_TESS_EVAL
:
6545 next
= PIPE_SHADER_TESS_EVAL
;
6547 case MESA_SHADER_GEOMETRY
:
6548 next
= PIPE_SHADER_GEOMETRY
;
6550 case MESA_SHADER_FRAGMENT
:
6551 next
= PIPE_SHADER_FRAGMENT
;
6558 ureg_set_next_shader_processor(ureg
, next
);
6572 t
->num_constants
= 0;
6573 free(t
->immediates
);
6574 t
->num_immediates
= 0;
6577 debug_printf("%s: translate error flag set\n", __func__
);
6585 /* ----------------------------- End TGSI code ------------------------------ */
6589 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6590 * generating Mesa IR.
6592 static struct gl_program
*
6593 get_mesa_program_tgsi(struct gl_context
*ctx
,
6594 struct gl_shader_program
*shader_program
,
6595 struct gl_linked_shader
*shader
)
6597 glsl_to_tgsi_visitor
* v
;
6598 struct gl_program
*prog
;
6599 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6601 struct gl_shader_compiler_options
*options
=
6602 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6603 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6604 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6606 validate_ir_tree(shader
->ir
);
6608 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6611 prog
->Parameters
= _mesa_new_parameter_list();
6612 v
= new glsl_to_tgsi_visitor();
6615 v
->shader_program
= shader_program
;
6617 v
->options
= options
;
6618 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6619 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6621 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6622 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6623 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6624 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6626 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6627 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6630 /* Remove reads from output registers. */
6631 lower_output_reads(shader
->Stage
, shader
->ir
);
6633 /* Emit intermediate IR for main(). */
6634 visit_exec_list(shader
->ir
, v
);
6636 /* Now emit bodies for any functions that were used. */
6638 progress
= GL_FALSE
;
6640 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6641 if (!entry
->bgn_inst
) {
6642 v
->current_function
= entry
;
6644 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6645 entry
->bgn_inst
->function
= entry
;
6647 visit_exec_list(&entry
->sig
->body
, v
);
6649 glsl_to_tgsi_instruction
*last
;
6650 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6651 if (last
->op
!= TGSI_OPCODE_RET
)
6652 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6654 glsl_to_tgsi_instruction
*end
;
6655 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6656 end
->function
= entry
;
6664 /* Print out some information (for debugging purposes) used by the
6665 * optimization passes. */
6668 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6669 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6670 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6671 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6673 for (i
= 0; i
< v
->next_temp
; i
++) {
6674 first_writes
[i
] = -1;
6675 first_reads
[i
] = -1;
6676 last_writes
[i
] = -1;
6679 v
->get_first_temp_read(first_reads
);
6680 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6681 v
->get_last_temp_write(last_writes
);
6682 for (i
= 0; i
< v
->next_temp
; i
++)
6683 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6687 ralloc_free(first_writes
);
6688 ralloc_free(first_reads
);
6689 ralloc_free(last_writes
);
6690 ralloc_free(last_reads
);
6694 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6697 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6698 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6699 v
->copy_propagate();
6701 while (v
->eliminate_dead_code());
6703 v
->merge_two_dsts();
6704 v
->merge_registers();
6705 v
->renumber_registers();
6707 /* Write the END instruction. */
6708 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6710 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6712 _mesa_log("GLSL IR for linked %s program %d:\n",
6713 _mesa_shader_stage_to_string(shader
->Stage
),
6714 shader_program
->Name
);
6715 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6719 prog
->Instructions
= NULL
;
6720 prog
->NumInstructions
= 0;
6722 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6723 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6724 &prog
->InputsRead
, prog
->DoubleInputsRead
, &prog
->PatchInputsRead
);
6725 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6726 &prog
->OutputsWritten
, 0ULL, &prog
->PatchOutputsWritten
);
6727 count_resources(v
, prog
);
6729 /* The GLSL IR won't be needed anymore. */
6730 ralloc_free(shader
->ir
);
6733 /* This must be done before the uniform storage is associated. */
6734 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6735 (prog
->InputsRead
& VARYING_BIT_POS
||
6736 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6737 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6738 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6741 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6742 wposTransformState
);
6745 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6747 /* Avoid reallocation of the program parameter list, because the uniform
6748 * storage is only associated with the original parameter list.
6749 * This should be enough for Bitmap and DrawPixels constants.
6751 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6753 /* This has to be done last. Any operation the can cause
6754 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6755 * program constant) has to happen before creating this linkage.
6757 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6758 if (!shader_program
->LinkStatus
) {
6759 free_glsl_to_tgsi_visitor(v
);
6763 struct st_vertex_program
*stvp
;
6764 struct st_fragment_program
*stfp
;
6765 struct st_geometry_program
*stgp
;
6766 struct st_tessctrl_program
*sttcp
;
6767 struct st_tesseval_program
*sttep
;
6768 struct st_compute_program
*stcp
;
6770 switch (shader
->Stage
) {
6771 case MESA_SHADER_VERTEX
:
6772 stvp
= (struct st_vertex_program
*)prog
;
6773 stvp
->glsl_to_tgsi
= v
;
6775 case MESA_SHADER_FRAGMENT
:
6776 stfp
= (struct st_fragment_program
*)prog
;
6777 stfp
->glsl_to_tgsi
= v
;
6779 case MESA_SHADER_GEOMETRY
:
6780 stgp
= (struct st_geometry_program
*)prog
;
6781 stgp
->glsl_to_tgsi
= v
;
6783 case MESA_SHADER_TESS_CTRL
:
6784 sttcp
= (struct st_tessctrl_program
*)prog
;
6785 sttcp
->glsl_to_tgsi
= v
;
6787 case MESA_SHADER_TESS_EVAL
:
6788 sttep
= (struct st_tesseval_program
*)prog
;
6789 sttep
->glsl_to_tgsi
= v
;
6791 case MESA_SHADER_COMPUTE
:
6792 stcp
= (struct st_compute_program
*)prog
;
6793 stcp
->glsl_to_tgsi
= v
;
6796 assert(!"should not be reached");
6804 set_affected_state_flags(uint64_t *states
,
6805 struct gl_program
*prog
,
6806 struct gl_linked_shader
*shader
,
6807 uint64_t new_constants
,
6808 uint64_t new_sampler_views
,
6809 uint64_t new_samplers
,
6810 uint64_t new_images
,
6813 uint64_t new_atomics
)
6815 if (prog
->Parameters
->NumParameters
)
6816 *states
|= new_constants
;
6818 if (shader
->num_samplers
)
6819 *states
|= new_sampler_views
| new_samplers
;
6821 if (shader
->NumImages
)
6822 *states
|= new_images
;
6824 if (shader
->NumUniformBlocks
)
6825 *states
|= new_ubos
;
6827 if (shader
->NumShaderStorageBlocks
)
6828 *states
|= new_ssbos
;
6830 if (shader
->NumAtomicBuffers
)
6831 *states
|= new_atomics
;
6834 static struct gl_program
*
6835 get_mesa_program(struct gl_context
*ctx
,
6836 struct gl_shader_program
*shader_program
,
6837 struct gl_linked_shader
*shader
)
6839 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6840 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6841 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6842 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6843 struct gl_program
*prog
= NULL
;
6845 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6846 /* TODO only for GLSL VS/FS for now: */
6847 switch (shader
->Stage
) {
6848 case MESA_SHADER_VERTEX
:
6849 case MESA_SHADER_FRAGMENT
:
6850 prog
= st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6855 prog
= get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6861 /* This determines which states will be updated when the shader is
6864 switch (shader
->Stage
) {
6865 case MESA_SHADER_VERTEX
:
6866 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6868 *states
= ST_NEW_VS_STATE
|
6870 ST_NEW_VERTEX_ARRAYS
;
6872 set_affected_state_flags(states
, prog
, shader
,
6873 ST_NEW_VS_CONSTANTS
,
6874 ST_NEW_VS_SAMPLER_VIEWS
,
6875 ST_NEW_RENDER_SAMPLERS
,
6882 case MESA_SHADER_TESS_CTRL
:
6883 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6885 *states
= ST_NEW_TCS_STATE
;
6887 set_affected_state_flags(states
, prog
, shader
,
6888 ST_NEW_TCS_CONSTANTS
,
6889 ST_NEW_TCS_SAMPLER_VIEWS
,
6890 ST_NEW_RENDER_SAMPLERS
,
6894 ST_NEW_TCS_ATOMICS
);
6897 case MESA_SHADER_TESS_EVAL
:
6898 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6900 *states
= ST_NEW_TES_STATE
|
6903 set_affected_state_flags(states
, prog
, shader
,
6904 ST_NEW_TES_CONSTANTS
,
6905 ST_NEW_TES_SAMPLER_VIEWS
,
6906 ST_NEW_RENDER_SAMPLERS
,
6910 ST_NEW_TES_ATOMICS
);
6913 case MESA_SHADER_GEOMETRY
:
6914 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6916 *states
= ST_NEW_GS_STATE
|
6919 set_affected_state_flags(states
, prog
, shader
,
6920 ST_NEW_GS_CONSTANTS
,
6921 ST_NEW_GS_SAMPLER_VIEWS
,
6922 ST_NEW_RENDER_SAMPLERS
,
6929 case MESA_SHADER_FRAGMENT
:
6930 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6932 /* gl_FragCoord and glDrawPixels always use constants. */
6933 *states
= ST_NEW_FS_STATE
|
6934 ST_NEW_SAMPLE_SHADING
|
6935 ST_NEW_FS_CONSTANTS
;
6937 set_affected_state_flags(states
, prog
, shader
,
6938 ST_NEW_FS_CONSTANTS
,
6939 ST_NEW_FS_SAMPLER_VIEWS
,
6940 ST_NEW_RENDER_SAMPLERS
,
6947 case MESA_SHADER_COMPUTE
:
6948 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6950 *states
= ST_NEW_CS_STATE
;
6952 set_affected_state_flags(states
, prog
, shader
,
6953 ST_NEW_CS_CONSTANTS
,
6954 ST_NEW_CS_SAMPLER_VIEWS
,
6963 unreachable("unhandled shader stage");
6975 * Called via ctx->Driver.LinkShader()
6976 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6977 * with code lowering and other optimizations.
6980 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6982 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6983 assert(prog
->LinkStatus
);
6985 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6986 if (prog
->_LinkedShaders
[i
] == NULL
)
6990 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6991 gl_shader_stage stage
= prog
->_LinkedShaders
[i
]->Stage
;
6992 const struct gl_shader_compiler_options
*options
=
6993 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6994 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6995 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6996 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6997 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6998 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7000 /* If there are forms of indirect addressing that the driver
7001 * cannot handle, perform the lowering pass.
7003 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7004 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7005 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
7006 options
->EmitNoIndirectInput
,
7007 options
->EmitNoIndirectOutput
,
7008 options
->EmitNoIndirectTemp
,
7009 options
->EmitNoIndirectUniform
);
7012 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7013 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7014 LOWER_UNPACK_SNORM_2x16
|
7015 LOWER_PACK_UNORM_2x16
|
7016 LOWER_UNPACK_UNORM_2x16
|
7017 LOWER_PACK_SNORM_4x8
|
7018 LOWER_UNPACK_SNORM_4x8
|
7019 LOWER_UNPACK_UNORM_4x8
|
7020 LOWER_PACK_UNORM_4x8
;
7022 if (ctx
->Extensions
.ARB_gpu_shader5
)
7023 lower_inst
|= LOWER_PACK_USE_BFI
|
7025 if (!ctx
->st
->has_half_float_packing
)
7026 lower_inst
|= LOWER_PACK_HALF_2x16
|
7027 LOWER_UNPACK_HALF_2x16
;
7029 lower_packing_builtins(ir
, lower_inst
);
7032 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7033 lower_offset_arrays(ir
);
7034 do_mat_op_to_vec(ir
);
7035 lower_instructions(ir
,
7041 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7044 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7045 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7046 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7047 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7048 /* Assume that if ARB_gpu_shader5 is not supported
7049 * then all of the extended integer functions need
7050 * lowering. It may be necessary to add some caps
7051 * for individual instructions.
7053 (!ctx
->Extensions
.ARB_gpu_shader5
7054 ? BIT_COUNT_TO_MATH
|
7058 FIND_LSB_TO_FLOAT_CAST
|
7059 FIND_MSB_TO_FLOAT_CAST
|
7063 do_vec_index_to_cond_assign(ir
);
7064 lower_vector_insert(ir
, true);
7065 lower_quadop_vector(ir
, false);
7067 if (options
->MaxIfDepth
== 0) {
7074 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
7076 progress
= do_common_optimization(ir
, true, true, options
,
7077 ctx
->Const
.NativeIntegers
)
7080 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
7084 validate_ir_tree(ir
);
7087 build_program_resource_list(ctx
, prog
);
7089 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7090 struct gl_program
*linked_prog
;
7092 if (prog
->_LinkedShaders
[i
] == NULL
)
7095 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
7098 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
7100 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7101 _mesa_shader_stage_to_program(i
),
7103 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
7105 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
7110 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
7117 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7118 const GLuint outputMapping
[],
7119 struct pipe_stream_output_info
*so
)
7121 struct gl_transform_feedback_info
*info
=
7122 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
7123 st_translate_stream_output_info2(info
, outputMapping
, so
);
7127 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7128 const GLuint outputMapping
[],
7129 struct pipe_stream_output_info
*so
)
7133 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7134 so
->output
[i
].register_index
=
7135 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7136 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7137 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7138 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7139 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7140 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7143 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7144 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7146 so
->num_outputs
= info
->NumOutputs
;