2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
57 #include "st_shader_cache.h"
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
65 #define MAX_GLSL_TEXTURE_OFFSET 4
70 static int swizzle_for_size(int size
);
72 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
74 unsigned num_elements
= 4;
77 type
= type
->without_array();
78 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
79 num_elements
= type
->vector_elements
;
82 int swizzle
= swizzle_for_size(num_elements
);
83 assert(num_elements
+ component
<= 4);
85 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
90 * This struct is a corresponding struct to TGSI ureg_src.
94 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
95 int component
= 0, unsigned array_id
= 0)
97 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
100 this->swizzle
= swizzle_for_type(type
, component
);
104 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
105 this->reladdr
= NULL
;
106 this->reladdr2
= NULL
;
107 this->has_index2
= false;
108 this->double_reg2
= false;
109 this->array_id
= array_id
;
110 this->is_double_vertex_input
= false;
113 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
115 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
120 this->swizzle
= SWIZZLE_XYZW
;
123 this->reladdr
= NULL
;
124 this->reladdr2
= NULL
;
125 this->has_index2
= false;
126 this->double_reg2
= false;
128 this->is_double_vertex_input
= false;
131 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
133 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
137 this->index2D
= index2D
;
138 this->swizzle
= SWIZZLE_XYZW
;
141 this->reladdr
= NULL
;
142 this->reladdr2
= NULL
;
143 this->has_index2
= false;
144 this->double_reg2
= false;
146 this->is_double_vertex_input
= false;
151 this->type
= GLSL_TYPE_ERROR
;
152 this->file
= PROGRAM_UNDEFINED
;
158 this->reladdr
= NULL
;
159 this->reladdr2
= NULL
;
160 this->has_index2
= false;
161 this->double_reg2
= false;
163 this->is_double_vertex_input
= false;
166 explicit st_src_reg(st_dst_reg reg
);
168 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
170 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
171 int negate
:4; /**< NEGATE_XYZW mask from mesa */
173 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
174 unsigned has_index2
:1;
175 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
177 * Is this the second half of a double register pair?
178 * currently used for input mapping only.
180 unsigned double_reg2
:1;
181 unsigned is_double_vertex_input
:1;
182 unsigned array_id
:10;
184 /** Register index should be offset by the integer in this reg. */
186 st_src_reg
*reladdr2
;
190 st_src_reg reg
= *this;
199 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
201 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
205 this->writemask
= writemask
;
206 this->reladdr
= NULL
;
207 this->reladdr2
= NULL
;
208 this->has_index2
= false;
213 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
215 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
219 this->writemask
= writemask
;
220 this->reladdr
= NULL
;
221 this->reladdr2
= NULL
;
222 this->has_index2
= false;
229 this->type
= GLSL_TYPE_ERROR
;
230 this->file
= PROGRAM_UNDEFINED
;
234 this->reladdr
= NULL
;
235 this->reladdr2
= NULL
;
236 this->has_index2
= false;
240 explicit st_dst_reg(st_src_reg reg
);
242 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
244 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
245 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
246 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
247 unsigned has_index2
:1;
248 unsigned array_id
:10;
250 /** Register index should be offset by the integer in this reg. */
252 st_src_reg
*reladdr2
;
255 st_src_reg::st_src_reg(st_dst_reg reg
)
257 this->type
= reg
.type
;
258 this->file
= reg
.file
;
259 this->index
= reg
.index
;
260 this->swizzle
= SWIZZLE_XYZW
;
263 this->reladdr
= reg
.reladdr
;
264 this->index2D
= reg
.index2D
;
265 this->reladdr2
= reg
.reladdr2
;
266 this->has_index2
= reg
.has_index2
;
267 this->double_reg2
= false;
268 this->array_id
= reg
.array_id
;
269 this->is_double_vertex_input
= false;
272 st_dst_reg::st_dst_reg(st_src_reg reg
)
274 this->type
= reg
.type
;
275 this->file
= reg
.file
;
276 this->index
= reg
.index
;
277 this->writemask
= WRITEMASK_XYZW
;
278 this->reladdr
= reg
.reladdr
;
279 this->index2D
= reg
.index2D
;
280 this->reladdr2
= reg
.reladdr2
;
281 this->has_index2
= reg
.has_index2
;
282 this->array_id
= reg
.array_id
;
285 class glsl_to_tgsi_instruction
: public exec_node
{
287 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
291 st_src_reg resource
; /**< sampler or buffer register */
292 st_src_reg
*tex_offsets
;
294 /** Pointer to the ir source this tree came from for debugging */
297 unsigned op
:8; /**< TGSI opcode */
299 unsigned is_64bit_expanded
:1;
300 unsigned sampler_base
:5;
301 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
302 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
303 glsl_base_type tex_type
:5;
304 unsigned tex_shadow
:1;
305 unsigned image_format
:9;
306 unsigned tex_offset_num_offset
:3;
307 unsigned dead_mask
:4; /**< Used in dead code elimination */
308 unsigned buffer_access
:3; /**< buffer access type */
310 const struct tgsi_opcode_info
*info
;
313 class variable_storage
: public exec_node
{
315 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
316 unsigned array_id
= 0)
317 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
319 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
322 gl_register_file file
;
325 /* Explicit component location. This is given in terms of the GLSL-style
326 * swizzles where each double is a single component, i.e. for 64-bit types
327 * it can only be 0 or 1.
330 ir_variable
*var
; /* variable that maps to this, if any */
334 class immediate_storage
: public exec_node
{
336 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
338 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
339 this->size32
= size32
;
343 /* doubles are stored across 2 gl_constant_values */
344 gl_constant_value values
[4];
345 int size32
; /**< Number of 32-bit components (1-4) */
346 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
349 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
350 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
354 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
357 unsigned gs_out_streams
;
358 enum glsl_interp_mode interp
;
359 enum glsl_base_type base_type
;
360 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
363 static struct inout_decl
*
364 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
366 assert(array_id
!= 0);
368 for (unsigned i
= 0; i
< count
; i
++) {
369 struct inout_decl
*decl
= &decls
[i
];
371 if (array_id
== decl
->array_id
) {
379 static enum glsl_base_type
380 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
383 return GLSL_TYPE_ERROR
;
384 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
386 return decl
->base_type
;
387 return GLSL_TYPE_ERROR
;
390 struct rename_reg_pair
{
395 struct glsl_to_tgsi_visitor
: public ir_visitor
{
397 glsl_to_tgsi_visitor();
398 ~glsl_to_tgsi_visitor();
400 struct gl_context
*ctx
;
401 struct gl_program
*prog
;
402 struct gl_shader_program
*shader_program
;
403 struct gl_linked_shader
*shader
;
404 struct gl_shader_compiler_options
*options
;
408 unsigned *array_sizes
;
409 unsigned max_num_arrays
;
412 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
414 unsigned num_input_arrays
;
415 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
416 unsigned num_outputs
;
417 unsigned num_output_arrays
;
419 int num_address_regs
;
420 uint32_t samplers_used
;
421 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
422 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
425 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
426 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
427 bool indirect_addr_consts
;
428 int wpos_transform_const
;
431 bool native_integers
;
434 bool use_shared_memory
;
437 variable_storage
*find_variable_storage(ir_variable
*var
);
439 int add_constant(gl_register_file file
, gl_constant_value values
[8],
440 int size
, int datatype
, uint16_t *swizzle_out
);
442 st_src_reg
get_temp(const glsl_type
*type
);
443 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
445 st_src_reg
st_src_reg_for_double(double val
);
446 st_src_reg
st_src_reg_for_float(float val
);
447 st_src_reg
st_src_reg_for_int(int val
);
448 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
451 * \name Visit methods
453 * As typical for the visitor pattern, there must be one \c visit method for
454 * each concrete subclass of \c ir_instruction. Virtual base classes within
455 * the hierarchy should not have \c visit methods.
458 virtual void visit(ir_variable
*);
459 virtual void visit(ir_loop
*);
460 virtual void visit(ir_loop_jump
*);
461 virtual void visit(ir_function_signature
*);
462 virtual void visit(ir_function
*);
463 virtual void visit(ir_expression
*);
464 virtual void visit(ir_swizzle
*);
465 virtual void visit(ir_dereference_variable
*);
466 virtual void visit(ir_dereference_array
*);
467 virtual void visit(ir_dereference_record
*);
468 virtual void visit(ir_assignment
*);
469 virtual void visit(ir_constant
*);
470 virtual void visit(ir_call
*);
471 virtual void visit(ir_return
*);
472 virtual void visit(ir_discard
*);
473 virtual void visit(ir_texture
*);
474 virtual void visit(ir_if
*);
475 virtual void visit(ir_emit_vertex
*);
476 virtual void visit(ir_end_primitive
*);
477 virtual void visit(ir_barrier
*);
480 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
482 void visit_atomic_counter_intrinsic(ir_call
*);
483 void visit_ssbo_intrinsic(ir_call
*);
484 void visit_membar_intrinsic(ir_call
*);
485 void visit_shared_intrinsic(ir_call
*);
486 void visit_image_intrinsic(ir_call
*);
490 /** List of variable_storage */
493 /** List of immediate_storage */
494 exec_list immediates
;
495 unsigned num_immediates
;
497 /** List of glsl_to_tgsi_instruction */
498 exec_list instructions
;
500 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
501 st_dst_reg dst
= undef_dst
,
502 st_src_reg src0
= undef_src
,
503 st_src_reg src1
= undef_src
,
504 st_src_reg src2
= undef_src
,
505 st_src_reg src3
= undef_src
);
507 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
508 st_dst_reg dst
, st_dst_reg dst1
,
509 st_src_reg src0
= undef_src
,
510 st_src_reg src1
= undef_src
,
511 st_src_reg src2
= undef_src
,
512 st_src_reg src3
= undef_src
);
514 unsigned get_opcode(unsigned op
,
516 st_src_reg src0
, st_src_reg src1
);
519 * Emit the correct dot-product instruction for the type of arguments
521 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
527 void emit_scalar(ir_instruction
*ir
, unsigned op
,
528 st_dst_reg dst
, st_src_reg src0
);
530 void emit_scalar(ir_instruction
*ir
, unsigned op
,
531 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
533 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
535 void get_deref_offsets(ir_dereference
*ir
,
536 unsigned *array_size
,
541 void calc_deref_offsets(ir_dereference
*tail
,
542 unsigned *array_elements
,
544 st_src_reg
*indirect
,
546 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
548 bool try_emit_mad(ir_expression
*ir
,
550 bool try_emit_mad_for_and_not(ir_expression
*ir
,
553 void emit_swz(ir_expression
*ir
);
555 bool process_move_condition(ir_rvalue
*ir
);
557 void simplify_cmp(void);
559 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
560 void get_first_temp_read(int *first_reads
);
561 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
562 void get_last_temp_write(int *last_writes
);
564 void copy_propagate(void);
565 int eliminate_dead_code(void);
567 void merge_two_dsts(void);
568 void merge_registers(void);
569 void renumber_registers(void);
571 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
572 st_dst_reg
*l
, st_src_reg
*r
,
573 st_src_reg
*cond
, bool cond_swap
);
578 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
579 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
580 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
583 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
586 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
590 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
593 prog
->data
->LinkStatus
= linking_failure
;
597 swizzle_for_size(int size
)
599 static const int size_swizzles
[4] = {
600 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
601 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
602 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
603 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
606 assert((size
>= 1) && (size
<= 4));
607 return size_swizzles
[size
- 1];
611 is_resource_instruction(unsigned opcode
)
614 case TGSI_OPCODE_RESQ
:
615 case TGSI_OPCODE_LOAD
:
616 case TGSI_OPCODE_ATOMUADD
:
617 case TGSI_OPCODE_ATOMXCHG
:
618 case TGSI_OPCODE_ATOMCAS
:
619 case TGSI_OPCODE_ATOMAND
:
620 case TGSI_OPCODE_ATOMOR
:
621 case TGSI_OPCODE_ATOMXOR
:
622 case TGSI_OPCODE_ATOMUMIN
:
623 case TGSI_OPCODE_ATOMUMAX
:
624 case TGSI_OPCODE_ATOMIMIN
:
625 case TGSI_OPCODE_ATOMIMAX
:
633 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
635 return op
->info
->num_dst
;
639 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
641 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
642 op
->info
->num_src
- 1 : op
->info
->num_src
;
645 glsl_to_tgsi_instruction
*
646 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
647 st_dst_reg dst
, st_dst_reg dst1
,
648 st_src_reg src0
, st_src_reg src1
,
649 st_src_reg src2
, st_src_reg src3
)
651 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
652 int num_reladdr
= 0, i
, j
;
653 bool dst_is_64bit
[2];
655 op
= get_opcode(op
, dst
, src0
, src1
);
657 /* If we have to do relative addressing, we want to load the ARL
658 * reg directly for one of the regs, and preload the other reladdr
659 * sources into temps.
661 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
662 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
663 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
664 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
665 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
666 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
668 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
669 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
670 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
671 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
673 if (dst
.reladdr
|| dst
.reladdr2
) {
675 emit_arl(ir
, address_reg
, *dst
.reladdr
);
677 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
681 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
684 assert(num_reladdr
== 0);
686 /* inst->op has only 8 bits. */
687 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
690 inst
->info
= tgsi_get_opcode_info(op
);
697 inst
->is_64bit_expanded
= false;
700 inst
->tex_offsets
= NULL
;
701 inst
->tex_offset_num_offset
= 0;
703 inst
->tex_shadow
= 0;
704 /* default to float, for paths where this is not initialized
705 * (since 0==UINT which is likely wrong):
707 inst
->tex_type
= GLSL_TYPE_FLOAT
;
709 /* Update indirect addressing status used by TGSI */
710 if (dst
.reladdr
|| dst
.reladdr2
) {
712 case PROGRAM_STATE_VAR
:
713 case PROGRAM_CONSTANT
:
714 case PROGRAM_UNIFORM
:
715 this->indirect_addr_consts
= true;
717 case PROGRAM_IMMEDIATE
:
718 assert(!"immediates should not have indirect addressing");
725 for (i
= 0; i
< 4; i
++) {
726 if(inst
->src
[i
].reladdr
) {
727 switch(inst
->src
[i
].file
) {
728 case PROGRAM_STATE_VAR
:
729 case PROGRAM_CONSTANT
:
730 case PROGRAM_UNIFORM
:
731 this->indirect_addr_consts
= true;
733 case PROGRAM_IMMEDIATE
:
734 assert(!"immediates should not have indirect addressing");
744 * This section contains the double processing.
745 * GLSL just represents doubles as single channel values,
746 * however most HW and TGSI represent doubles as pairs of register channels.
748 * so we have to fixup destination writemask/index and src swizzle/indexes.
749 * dest writemasks need to translate from single channel write mask
750 * to a dual-channel writemask, but also need to modify the index,
751 * if we are touching the Z,W fields in the pre-translated writemask.
753 * src channels have similiar index modifications along with swizzle
754 * changes to we pick the XY, ZW pairs from the correct index.
756 * GLSL [0].x -> TGSI [0].xy
757 * GLSL [0].y -> TGSI [0].zw
758 * GLSL [0].z -> TGSI [1].xy
759 * GLSL [0].w -> TGSI [1].zw
761 for (j
= 0; j
< 2; j
++) {
762 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
763 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
764 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
765 if (glsl_base_type_is_64bit(type
))
766 dst_is_64bit
[j
] = true;
770 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
771 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
772 glsl_to_tgsi_instruction
*dinst
= NULL
;
773 int initial_src_swz
[4], initial_src_idx
[4];
774 int initial_dst_idx
[2], initial_dst_writemask
[2];
775 /* select the writemask for dst0 or dst1 */
776 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
778 /* copy out the writemask, index and swizzles for all src/dsts. */
779 for (j
= 0; j
< 2; j
++) {
780 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
781 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
784 for (j
= 0; j
< 4; j
++) {
785 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
786 initial_src_idx
[j
] = inst
->src
[j
].index
;
790 * scan all the components in the dst writemask
791 * generate an instruction for each of them if required.
796 int i
= u_bit_scan(&writemask
);
798 /* before emitting the instruction, see if we have to adjust load / store
800 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
801 addr
.file
== PROGRAM_UNDEFINED
) {
802 /* We have to advance the buffer address by 16 */
803 addr
= get_temp(glsl_type::uint_type
);
804 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
805 inst
->src
[0], st_src_reg_for_int(16));
808 /* first time use previous instruction */
812 /* create a new instructions for subsequent attempts */
813 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
818 this->instructions
.push_tail(dinst
);
819 dinst
->is_64bit_expanded
= true;
821 /* modify the destination if we are splitting */
822 for (j
= 0; j
< 2; j
++) {
823 if (dst_is_64bit
[j
]) {
824 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
825 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
827 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
828 dinst
->src
[0] = addr
;
829 if (dinst
->op
!= TGSI_OPCODE_STORE
)
830 dinst
->dst
[j
].index
++;
833 /* if we aren't writing to a double, just get the bit of the initial writemask
835 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
839 /* modify the src registers */
840 for (j
= 0; j
< 4; j
++) {
841 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
843 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
844 dinst
->src
[j
].index
= initial_src_idx
[j
];
846 dinst
->src
[j
].double_reg2
= true;
847 dinst
->src
[j
].index
++;
851 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
853 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
856 /* some opcodes are special case in what they use as sources
857 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
858 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
859 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
860 op
== TGSI_OPCODE_DLDEXP
||
861 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
862 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
869 this->instructions
.push_tail(inst
);
876 glsl_to_tgsi_instruction
*
877 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
879 st_src_reg src0
, st_src_reg src1
,
880 st_src_reg src2
, st_src_reg src3
)
882 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
886 * Determines whether to use an integer, unsigned integer, or float opcode
887 * based on the operands and input opcode, then emits the result.
890 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
892 st_src_reg src0
, st_src_reg src1
)
894 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
896 if (op
== TGSI_OPCODE_MOV
)
899 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
900 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
901 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
902 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
904 if (is_resource_instruction(op
))
906 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
907 type
= GLSL_TYPE_INT64
;
908 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
909 type
= GLSL_TYPE_UINT64
;
910 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
911 type
= GLSL_TYPE_DOUBLE
;
912 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
913 type
= GLSL_TYPE_FLOAT
;
914 else if (native_integers
)
915 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
917 #define case7(c, f, i, u, d, i64, ui64) \
918 case TGSI_OPCODE_##c: \
919 if (type == GLSL_TYPE_UINT64) \
920 op = TGSI_OPCODE_##ui64; \
921 else if (type == GLSL_TYPE_INT64) \
922 op = TGSI_OPCODE_##i64; \
923 else if (type == GLSL_TYPE_DOUBLE) \
924 op = TGSI_OPCODE_##d; \
925 else if (type == GLSL_TYPE_INT) \
926 op = TGSI_OPCODE_##i; \
927 else if (type == GLSL_TYPE_UINT) \
928 op = TGSI_OPCODE_##u; \
930 op = TGSI_OPCODE_##f; \
932 #define case5(c, f, i, u, d) \
933 case TGSI_OPCODE_##c: \
934 if (type == GLSL_TYPE_DOUBLE) \
935 op = TGSI_OPCODE_##d; \
936 else if (type == GLSL_TYPE_INT) \
937 op = TGSI_OPCODE_##i; \
938 else if (type == GLSL_TYPE_UINT) \
939 op = TGSI_OPCODE_##u; \
941 op = TGSI_OPCODE_##f; \
944 #define case4(c, f, i, u) \
945 case TGSI_OPCODE_##c: \
946 if (type == GLSL_TYPE_INT) \
947 op = TGSI_OPCODE_##i; \
948 else if (type == GLSL_TYPE_UINT) \
949 op = TGSI_OPCODE_##u; \
951 op = TGSI_OPCODE_##f; \
954 #define case3(f, i, u) case4(f, f, i, u)
955 #define case6d(f, i, u, d, i64, u64) case7(f, f, i, u, d, i64, u64)
956 #define case3fid(f, i, d) case5(f, f, i, i, d)
957 #define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
958 #define case2fi(f, i) case4(f, f, i, i)
959 #define case2iu(i, u) case4(i, LAST, i, u)
961 #define case2iu64(i, i64) case7(i, LAST, i, i, LAST, i64, i64)
962 #define case4iu64(i, u, i64, u64) case7(i, LAST, i, u, LAST, i64, u64)
964 #define casecomp(c, f, i, u, d, i64, ui64) \
965 case TGSI_OPCODE_##c: \
966 if (type == GLSL_TYPE_INT64) \
967 op = TGSI_OPCODE_##i64; \
968 else if (type == GLSL_TYPE_UINT64) \
969 op = TGSI_OPCODE_##ui64; \
970 else if (type == GLSL_TYPE_DOUBLE) \
971 op = TGSI_OPCODE_##d; \
972 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
973 op = TGSI_OPCODE_##i; \
974 else if (type == GLSL_TYPE_UINT) \
975 op = TGSI_OPCODE_##u; \
976 else if (native_integers) \
977 op = TGSI_OPCODE_##f; \
979 op = TGSI_OPCODE_##c; \
983 case3fid64(ADD
, UADD
, DADD
, U64ADD
);
984 case3fid64(MUL
, UMUL
, DMUL
, U64MUL
);
985 case3fid(MAD
, UMAD
, DMAD
);
986 case3fid(FMA
, UMAD
, DFMA
);
987 case6d(DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
988 case6d(MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
989 case6d(MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
990 case4iu64(MOD
, UMOD
, I64MOD
, U64MOD
);
992 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
993 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
994 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
995 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
997 case2iu64(SHL
, U64SHL
);
998 case4iu64(ISHR
, USHR
, I64SHR
, U64SHR
);
1000 case3fid64(SSG
, ISSG
, DSSG
, I64SSG
);
1002 case2iu(IBFE
, UBFE
);
1003 case2iu(IMSB
, UMSB
);
1004 case2iu(IMUL_HI
, UMUL_HI
);
1006 case3fid(SQRT
, SQRT
, DSQRT
);
1008 case3fid(RCP
, RCP
, DRCP
);
1009 case3fid(RSQ
, RSQ
, DRSQ
);
1011 case3fid(FRC
, FRC
, DFRAC
);
1012 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1013 case3fid(CEIL
, CEIL
, DCEIL
);
1014 case3fid(FLR
, FLR
, DFLR
);
1015 case3fid(ROUND
, ROUND
, DROUND
);
1017 case2iu(ATOMIMAX
, ATOMUMAX
);
1018 case2iu(ATOMIMIN
, ATOMUMIN
);
1023 assert(op
!= TGSI_OPCODE_LAST
);
1027 glsl_to_tgsi_instruction
*
1028 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1029 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1032 static const unsigned dot_opcodes
[] = {
1033 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1036 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1040 * Emits TGSI scalar opcodes to produce unique answers across channels.
1042 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1043 * channel determines the result across all channels. So to do a vec4
1044 * of this operation, we want to emit a scalar per source channel used
1045 * to produce dest channels.
1048 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1050 st_src_reg orig_src0
, st_src_reg orig_src1
)
1053 int done_mask
= ~dst
.writemask
;
1055 /* TGSI RCP is a scalar operation splatting results to all channels,
1056 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1059 for (i
= 0; i
< 4; i
++) {
1060 GLuint this_mask
= (1 << i
);
1061 st_src_reg src0
= orig_src0
;
1062 st_src_reg src1
= orig_src1
;
1064 if (done_mask
& this_mask
)
1067 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1068 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1069 for (j
= i
+ 1; j
< 4; j
++) {
1070 /* If there is another enabled component in the destination that is
1071 * derived from the same inputs, generate its value on this pass as
1074 if (!(done_mask
& (1 << j
)) &&
1075 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1076 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1077 this_mask
|= (1 << j
);
1080 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1081 src0_swiz
, src0_swiz
);
1082 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1083 src1_swiz
, src1_swiz
);
1085 dst
.writemask
= this_mask
;
1086 emit_asm(ir
, op
, dst
, src0
, src1
);
1087 done_mask
|= this_mask
;
1092 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1093 st_dst_reg dst
, st_src_reg src0
)
1095 st_src_reg undef
= undef_src
;
1097 undef
.swizzle
= SWIZZLE_XXXX
;
1099 emit_scalar(ir
, op
, dst
, src0
, undef
);
1103 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1104 st_dst_reg dst
, st_src_reg src0
)
1106 int op
= TGSI_OPCODE_ARL
;
1108 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1109 op
= TGSI_OPCODE_UARL
;
1111 assert(dst
.file
== PROGRAM_ADDRESS
);
1112 if (dst
.index
>= this->num_address_regs
)
1113 this->num_address_regs
= dst
.index
+ 1;
1115 emit_asm(NULL
, op
, dst
, src0
);
1119 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1120 gl_constant_value values
[8], int size
, int datatype
,
1121 uint16_t *swizzle_out
)
1123 if (file
== PROGRAM_CONSTANT
) {
1124 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1125 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1126 size
, datatype
, &swizzle
);
1128 *swizzle_out
= swizzle
;
1132 assert(file
== PROGRAM_IMMEDIATE
);
1135 immediate_storage
*entry
;
1136 int size32
= size
* ((datatype
== GL_DOUBLE
||
1137 datatype
== GL_INT64_ARB
||
1138 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1141 /* Search immediate storage to see if we already have an identical
1142 * immediate that we can use instead of adding a duplicate entry.
1144 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1145 immediate_storage
*tmp
= entry
;
1147 for (i
= 0; i
* 4 < size32
; i
++) {
1148 int slot_size
= MIN2(size32
- (i
* 4), 4);
1149 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1151 if (memcmp(tmp
->values
, &values
[i
* 4],
1152 slot_size
* sizeof(gl_constant_value
)))
1155 /* Everything matches, keep going until the full size is matched */
1156 tmp
= (immediate_storage
*)tmp
->next
;
1159 /* The full value matched */
1160 if (i
* 4 >= size32
)
1166 for (i
= 0; i
* 4 < size32
; i
++) {
1167 int slot_size
= MIN2(size32
- (i
* 4), 4);
1168 /* Add this immediate to the list. */
1169 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1170 this->immediates
.push_tail(entry
);
1171 this->num_immediates
++;
1177 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1179 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1180 union gl_constant_value uval
;
1183 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1189 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1191 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1192 union gl_constant_value uval
[2];
1194 memcpy(uval
, &val
, sizeof(uval
));
1195 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1196 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1201 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1203 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1204 union gl_constant_value uval
;
1206 assert(native_integers
);
1209 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1215 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1217 if (native_integers
)
1218 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1219 st_src_reg_for_int(val
);
1221 return st_src_reg_for_float(val
);
1225 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1227 return st_glsl_attrib_type_size(type
, is_vs_input
);
1231 type_size(const struct glsl_type
*type
)
1233 return st_glsl_type_size(type
);
1237 * If the given GLSL type is an array or matrix or a structure containing
1238 * an array/matrix member, return true. Else return false.
1240 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1241 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1242 * we have an array that might be indexed with a variable, we need to use
1243 * the later storage type.
1246 type_has_array_or_matrix(const glsl_type
*type
)
1248 if (type
->is_array() || type
->is_matrix())
1251 if (type
->is_record()) {
1252 for (unsigned i
= 0; i
< type
->length
; i
++) {
1253 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1264 * In the initial pass of codegen, we assign temporary numbers to
1265 * intermediate results. (not SSA -- variable assignments will reuse
1269 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1273 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1278 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1279 if (next_array
>= max_num_arrays
) {
1280 max_num_arrays
+= 32;
1281 array_sizes
= (unsigned*)
1282 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1285 src
.file
= PROGRAM_ARRAY
;
1287 src
.array_id
= next_array
+ 1;
1288 array_sizes
[next_array
] = type_size(type
);
1292 src
.file
= PROGRAM_TEMPORARY
;
1293 src
.index
= next_temp
;
1294 next_temp
+= type_size(type
);
1297 if (type
->is_array() || type
->is_record()) {
1298 src
.swizzle
= SWIZZLE_NOOP
;
1300 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1307 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1310 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1311 if (entry
->var
== var
)
1319 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1321 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1322 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1323 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1326 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1328 const ir_state_slot
*const slots
= ir
->get_state_slots();
1329 assert(slots
!= NULL
);
1331 /* Check if this statevar's setup in the STATE file exactly
1332 * matches how we'll want to reference it as a
1333 * struct/array/whatever. If not, then we need to move it into
1334 * temporary storage and hope that it'll get copy-propagated
1337 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1338 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1343 variable_storage
*storage
;
1345 if (i
== ir
->get_num_state_slots()) {
1346 /* We'll set the index later. */
1347 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1348 this->variables
.push_tail(storage
);
1352 /* The variable_storage constructor allocates slots based on the size
1353 * of the type. However, this had better match the number of state
1354 * elements that we're going to copy into the new temporary.
1356 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1358 dst
= st_dst_reg(get_temp(ir
->type
));
1360 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1363 this->variables
.push_tail(storage
);
1367 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1368 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1369 (gl_state_index
*)slots
[i
].tokens
);
1371 if (storage
->file
== PROGRAM_STATE_VAR
) {
1372 if (storage
->index
== -1) {
1373 storage
->index
= index
;
1375 assert(index
== storage
->index
+ (int)i
);
1378 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1379 * the data being moved since MOV does not care about the type of
1380 * data it is moving, and we don't want to declare registers with
1381 * array or struct types.
1383 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1384 src
.swizzle
= slots
[i
].swizzle
;
1385 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1386 /* even a float takes up a whole vec4 reg in a struct/array. */
1391 if (storage
->file
== PROGRAM_TEMPORARY
&&
1392 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1393 fail_link(this->shader_program
,
1394 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1395 ir
->name
, dst
.index
- storage
->index
,
1396 type_size(ir
->type
));
1402 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1404 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1406 visit_exec_list(&ir
->body_instructions
, this);
1408 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1412 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1415 case ir_loop_jump::jump_break
:
1416 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1418 case ir_loop_jump::jump_continue
:
1419 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1426 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1433 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1435 /* Ignore function bodies other than main() -- we shouldn't see calls to
1436 * them since they should all be inlined before we get to glsl_to_tgsi.
1438 if (strcmp(ir
->name
, "main") == 0) {
1439 const ir_function_signature
*sig
;
1442 sig
= ir
->matching_signature(NULL
, &empty
, false);
1446 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1453 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1455 int nonmul_operand
= 1 - mul_operand
;
1457 st_dst_reg result_dst
;
1459 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1460 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1463 expr
->operands
[0]->accept(this);
1465 expr
->operands
[1]->accept(this);
1467 ir
->operands
[nonmul_operand
]->accept(this);
1470 this->result
= get_temp(ir
->type
);
1471 result_dst
= st_dst_reg(this->result
);
1472 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1473 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1479 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1481 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1482 * implemented using multiplication, and logical-or is implemented using
1483 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1484 * As result, the logical expression (a & !b) can be rewritten as:
1488 * - (a * 1) - (a * b)
1492 * This final expression can be implemented as a single MAD(a, -b, a)
1496 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1498 const int other_operand
= 1 - try_operand
;
1501 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1502 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1505 ir
->operands
[other_operand
]->accept(this);
1507 expr
->operands
[0]->accept(this);
1510 b
.negate
= ~b
.negate
;
1512 this->result
= get_temp(ir
->type
);
1513 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1519 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1520 st_src_reg
*reg
, int *num_reladdr
)
1522 if (!reg
->reladdr
&& !reg
->reladdr2
)
1525 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1526 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1528 if (*num_reladdr
!= 1) {
1529 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1531 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1539 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1541 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1543 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1545 if (ir
->operation
== ir_binop_add
) {
1546 if (try_emit_mad(ir
, 1))
1548 if (try_emit_mad(ir
, 0))
1552 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1554 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1555 if (try_emit_mad_for_and_not(ir
, 1))
1557 if (try_emit_mad_for_and_not(ir
, 0))
1561 if (ir
->operation
== ir_quadop_vector
)
1562 assert(!"ir_quadop_vector should have been lowered");
1564 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1565 this->result
.file
= PROGRAM_UNDEFINED
;
1566 ir
->operands
[operand
]->accept(this);
1567 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1568 printf("Failed to get tree for expression operand:\n");
1569 ir
->operands
[operand
]->print();
1573 op
[operand
] = this->result
;
1575 /* Matrix expression operands should have been broken down to vector
1576 * operations already.
1578 assert(!ir
->operands
[operand
]->type
->is_matrix());
1581 visit_expression(ir
, op
);
1584 /* The non-recursive part of the expression visitor lives in a separate
1585 * function and should be prevented from being inlined, to avoid a stack
1586 * explosion when deeply nested expressions are visited.
1589 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1591 st_src_reg result_src
;
1592 st_dst_reg result_dst
;
1594 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1595 if (ir
->operands
[1]) {
1596 vector_elements
= MAX2(vector_elements
,
1597 ir
->operands
[1]->type
->vector_elements
);
1600 this->result
.file
= PROGRAM_UNDEFINED
;
1602 /* Storage for our result. Ideally for an assignment we'd be using
1603 * the actual storage for the result here, instead.
1605 result_src
= get_temp(ir
->type
);
1606 /* convenience for the emit functions below. */
1607 result_dst
= st_dst_reg(result_src
);
1608 /* Limit writes to the channels that will be used by result_src later.
1609 * This does limit this temp's use as a temporary for multi-instruction
1612 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1614 switch (ir
->operation
) {
1615 case ir_unop_logic_not
:
1616 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1617 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1619 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1620 * older GPUs implement SEQ using multiple instructions (i915 uses two
1621 * SGE instructions and a MUL instruction). Since our logic values are
1622 * 0.0 and 1.0, 1-x also implements !x.
1624 op
[0].negate
= ~op
[0].negate
;
1625 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1629 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1630 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1631 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1632 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1633 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1634 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1636 op
[0].negate
= ~op
[0].negate
;
1640 case ir_unop_subroutine_to_int
:
1641 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1644 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1645 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1646 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1647 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1648 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1649 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1651 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1654 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1657 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1661 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1665 assert(!"not reached: should be handled by ir_explog_to_explog2");
1668 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1671 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1674 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1676 case ir_unop_saturate
: {
1677 glsl_to_tgsi_instruction
*inst
;
1678 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1679 inst
->saturate
= true;
1684 case ir_unop_dFdx_coarse
:
1685 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1687 case ir_unop_dFdx_fine
:
1688 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1691 case ir_unop_dFdy_coarse
:
1692 case ir_unop_dFdy_fine
:
1694 /* The X component contains 1 or -1 depending on whether the framebuffer
1695 * is a FBO or the window system buffer, respectively.
1696 * It is then multiplied with the source operand of DDY.
1698 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1699 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1701 unsigned transform_y_index
=
1702 _mesa_add_state_reference(this->prog
->Parameters
,
1705 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1707 glsl_type::vec4_type
);
1708 transform_y
.swizzle
= SWIZZLE_XXXX
;
1710 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1712 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1713 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1714 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1718 case ir_unop_frexp_sig
:
1719 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1722 case ir_unop_frexp_exp
:
1723 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1726 case ir_unop_noise
: {
1727 /* At some point, a motivated person could add a better
1728 * implementation of noise. Currently not even the nvidia
1729 * binary drivers do anything more than this. In any case, the
1730 * place to do this is in the GL state tracker, not the poor
1733 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1738 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1741 op
[1].negate
= ~op
[1].negate
;
1742 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1746 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1749 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1752 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1753 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1755 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1759 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_greater
:
1762 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1764 case ir_binop_lequal
:
1765 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1767 case ir_binop_gequal
:
1768 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1770 case ir_binop_equal
:
1771 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1773 case ir_binop_nequal
:
1774 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1776 case ir_binop_all_equal
:
1777 /* "==" operator producing a scalar boolean. */
1778 if (ir
->operands
[0]->type
->is_vector() ||
1779 ir
->operands
[1]->type
->is_vector()) {
1780 st_src_reg temp
= get_temp(native_integers
?
1781 glsl_type::uvec4_type
:
1782 glsl_type::vec4_type
);
1784 if (native_integers
) {
1785 st_dst_reg temp_dst
= st_dst_reg(temp
);
1786 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1788 if (ir
->operands
[0]->type
->is_boolean() &&
1789 ir
->operands
[1]->as_constant() &&
1790 ir
->operands
[1]->as_constant()->is_one()) {
1791 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1793 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1796 /* Emit 1-3 AND operations to combine the SEQ results. */
1797 switch (ir
->operands
[0]->type
->vector_elements
) {
1801 temp_dst
.writemask
= WRITEMASK_Y
;
1802 temp1
.swizzle
= SWIZZLE_YYYY
;
1803 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1804 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1807 temp_dst
.writemask
= WRITEMASK_X
;
1808 temp1
.swizzle
= SWIZZLE_XXXX
;
1809 temp2
.swizzle
= SWIZZLE_YYYY
;
1810 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1811 temp_dst
.writemask
= WRITEMASK_Y
;
1812 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1813 temp2
.swizzle
= SWIZZLE_WWWW
;
1814 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1817 temp1
.swizzle
= SWIZZLE_XXXX
;
1818 temp2
.swizzle
= SWIZZLE_YYYY
;
1819 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1821 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1823 /* After the dot-product, the value will be an integer on the
1824 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1826 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1828 /* Negating the result of the dot-product gives values on the range
1829 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1830 * This is achieved using SGE.
1832 st_src_reg sge_src
= result_src
;
1833 sge_src
.negate
= ~sge_src
.negate
;
1834 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1837 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1840 case ir_binop_any_nequal
:
1841 /* "!=" operator producing a scalar boolean. */
1842 if (ir
->operands
[0]->type
->is_vector() ||
1843 ir
->operands
[1]->type
->is_vector()) {
1844 st_src_reg temp
= get_temp(native_integers
?
1845 glsl_type::uvec4_type
:
1846 glsl_type::vec4_type
);
1847 if (ir
->operands
[0]->type
->is_boolean() &&
1848 ir
->operands
[1]->as_constant() &&
1849 ir
->operands
[1]->as_constant()->is_zero()) {
1850 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1852 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1855 if (native_integers
) {
1856 st_dst_reg temp_dst
= st_dst_reg(temp
);
1857 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1859 /* Emit 1-3 OR operations to combine the SNE results. */
1860 switch (ir
->operands
[0]->type
->vector_elements
) {
1864 temp_dst
.writemask
= WRITEMASK_Y
;
1865 temp1
.swizzle
= SWIZZLE_YYYY
;
1866 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1867 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1870 temp_dst
.writemask
= WRITEMASK_X
;
1871 temp1
.swizzle
= SWIZZLE_XXXX
;
1872 temp2
.swizzle
= SWIZZLE_YYYY
;
1873 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1874 temp_dst
.writemask
= WRITEMASK_Y
;
1875 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1876 temp2
.swizzle
= SWIZZLE_WWWW
;
1877 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1880 temp1
.swizzle
= SWIZZLE_XXXX
;
1881 temp2
.swizzle
= SWIZZLE_YYYY
;
1882 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1884 /* After the dot-product, the value will be an integer on the
1885 * range [0,4]. Zero stays zero, and positive values become 1.0.
1887 glsl_to_tgsi_instruction
*const dp
=
1888 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1889 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1890 /* The clamping to [0,1] can be done for free in the fragment
1891 * shader with a saturate.
1893 dp
->saturate
= true;
1895 /* Negating the result of the dot-product gives values on the range
1896 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1897 * achieved using SLT.
1899 st_src_reg slt_src
= result_src
;
1900 slt_src
.negate
= ~slt_src
.negate
;
1901 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1909 case ir_binop_logic_xor
:
1910 if (native_integers
)
1911 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1913 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1916 case ir_binop_logic_or
: {
1917 if (native_integers
) {
1918 /* If integers are used as booleans, we can use an actual "or"
1921 assert(native_integers
);
1922 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1924 /* After the addition, the value will be an integer on the
1925 * range [0,2]. Zero stays zero, and positive values become 1.0.
1927 glsl_to_tgsi_instruction
*add
=
1928 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1929 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1930 /* The clamping to [0,1] can be done for free in the fragment
1931 * shader with a saturate if floats are being used as boolean values.
1933 add
->saturate
= true;
1935 /* Negating the result of the addition gives values on the range
1936 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1937 * is achieved using SLT.
1939 st_src_reg slt_src
= result_src
;
1940 slt_src
.negate
= ~slt_src
.negate
;
1941 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1947 case ir_binop_logic_and
:
1948 /* If native integers are disabled, the bool args are stored as float 0.0
1949 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1950 * actual AND opcode.
1952 if (native_integers
)
1953 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1955 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1959 assert(ir
->operands
[0]->type
->is_vector());
1960 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1961 emit_dp(ir
, result_dst
, op
[0], op
[1],
1962 ir
->operands
[0]->type
->vector_elements
);
1967 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1969 /* This is the only instruction sequence that makes the game "Risen"
1970 * render correctly. ABS is not required for the game, but since GLSL
1971 * declares negative values as "undefined", allowing us to do whatever
1972 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1975 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1976 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1980 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1983 if (native_integers
) {
1984 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1987 /* fallthrough to next case otherwise */
1989 if (native_integers
) {
1990 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1993 /* fallthrough to next case otherwise */
1996 case ir_unop_i642u64
:
1997 case ir_unop_u642i64
:
1998 /* Converting between signed and unsigned integers is a no-op. */
2000 result_src
.type
= result_dst
.type
;
2003 if (native_integers
) {
2004 /* Booleans are stored as integers using ~0 for true and 0 for false.
2005 * GLSL requires that int(bool) return 1 for true and 0 for false.
2006 * This conversion is done with AND, but it could be done with NEG.
2008 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
2010 /* Booleans and integers are both stored as floats when native
2011 * integers are disabled.
2017 if (native_integers
)
2018 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2020 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2023 if (native_integers
)
2024 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2026 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2028 case ir_unop_bitcast_f2i
:
2029 case ir_unop_bitcast_f2u
:
2030 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2031 if (op
[0].negate
|| op
[0].abs
)
2032 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2035 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2038 case ir_unop_bitcast_i2f
:
2039 case ir_unop_bitcast_u2f
:
2041 result_src
.type
= GLSL_TYPE_FLOAT
;
2044 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2047 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2050 if (native_integers
)
2051 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2053 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2055 case ir_unop_bitcast_u642d
:
2056 case ir_unop_bitcast_i642d
:
2058 result_src
.type
= GLSL_TYPE_DOUBLE
;
2060 case ir_unop_bitcast_d2i64
:
2062 result_src
.type
= GLSL_TYPE_INT64
;
2064 case ir_unop_bitcast_d2u64
:
2066 result_src
.type
= GLSL_TYPE_UINT64
;
2069 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2072 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2075 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2077 case ir_unop_round_even
:
2078 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2081 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2085 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2088 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2091 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2094 case ir_unop_bit_not
:
2095 if (native_integers
) {
2096 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2100 if (native_integers
) {
2101 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2104 case ir_binop_lshift
:
2105 if (native_integers
) {
2106 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2109 case ir_binop_rshift
:
2110 if (native_integers
) {
2111 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2114 case ir_binop_bit_and
:
2115 if (native_integers
) {
2116 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2119 case ir_binop_bit_xor
:
2120 if (native_integers
) {
2121 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2124 case ir_binop_bit_or
:
2125 if (native_integers
) {
2126 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2130 assert(!"GLSL 1.30 features unsupported");
2133 case ir_binop_ubo_load
: {
2134 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2135 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2136 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2137 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2138 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2141 cbuf
.type
= ir
->type
->base_type
;
2142 cbuf
.file
= PROGRAM_CONSTANT
;
2144 cbuf
.reladdr
= NULL
;
2148 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2150 if (const_offset_ir
) {
2151 /* Constant index into constant buffer */
2152 cbuf
.reladdr
= NULL
;
2153 cbuf
.index
= const_offset
/ 16;
2156 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2157 st_src_reg offset
= op
[1];
2159 /* The OpenGL spec is written in such a way that accesses with
2160 * non-constant offset are almost always vec4-aligned. The only
2161 * exception to this are members of structs in arrays of structs:
2162 * each struct in an array of structs is at least vec4-aligned,
2163 * but single-element and [ui]vec2 members of the struct may be at
2164 * an offset that is not a multiple of 16 bytes.
2166 * Here, we extract that offset, relying on previous passes to always
2167 * generate offset expressions of the form (+ expr constant_offset).
2169 * Note that the std430 layout, which allows more cases of alignment
2170 * less than vec4 in arrays, is not supported for uniform blocks, so
2171 * we do not have to deal with it here.
2173 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2174 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2175 if (const_offset_ir
) {
2176 const_offset
= const_offset_ir
->value
.u
[0];
2177 cbuf
.index
= const_offset
/ 16;
2178 offset_expr
->operands
[0]->accept(this);
2179 offset
= this->result
;
2183 /* Relative/variable index into constant buffer */
2184 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2185 st_src_reg_for_int(4));
2186 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2187 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2190 if (const_uniform_block
) {
2191 /* Constant constant buffer */
2192 cbuf
.reladdr2
= NULL
;
2193 cbuf
.index2D
= const_block
;
2194 cbuf
.has_index2
= true;
2197 /* Relative/variable constant buffer */
2198 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2200 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2201 cbuf
.has_index2
= true;
2204 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2205 if (glsl_base_type_is_64bit(cbuf
.type
))
2206 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2207 const_offset
% 16 / 8,
2208 const_offset
% 16 / 8,
2209 const_offset
% 16 / 8);
2211 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2212 const_offset
% 16 / 4,
2213 const_offset
% 16 / 4,
2214 const_offset
% 16 / 4);
2216 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2217 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2219 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2224 /* note: we have to reorder the three args here */
2225 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2228 if (this->ctx
->Const
.NativeIntegers
)
2229 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2231 op
[0].negate
= ~op
[0].negate
;
2232 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2235 case ir_triop_bitfield_extract
:
2236 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2238 case ir_quadop_bitfield_insert
:
2239 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2241 case ir_unop_bitfield_reverse
:
2242 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2244 case ir_unop_bit_count
:
2245 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2247 case ir_unop_find_msb
:
2248 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2250 case ir_unop_find_lsb
:
2251 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2253 case ir_binop_imul_high
:
2254 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2257 /* In theory, MAD is incorrect here. */
2259 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2261 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2263 case ir_unop_interpolate_at_centroid
:
2264 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2266 case ir_binop_interpolate_at_offset
: {
2267 /* The y coordinate needs to be flipped for the default fb */
2268 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2269 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2271 unsigned transform_y_index
=
2272 _mesa_add_state_reference(this->prog
->Parameters
,
2275 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2277 glsl_type::vec4_type
);
2278 transform_y
.swizzle
= SWIZZLE_XXXX
;
2280 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2281 st_dst_reg temp_dst
= st_dst_reg(temp
);
2283 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2284 temp_dst
.writemask
= WRITEMASK_Y
;
2285 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2286 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2289 case ir_binop_interpolate_at_sample
:
2290 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2294 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2297 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2300 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2303 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2306 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2309 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2311 case ir_unop_unpack_double_2x32
:
2312 case ir_unop_pack_double_2x32
:
2313 case ir_unop_unpack_int_2x32
:
2314 case ir_unop_pack_int_2x32
:
2315 case ir_unop_unpack_uint_2x32
:
2316 case ir_unop_pack_uint_2x32
:
2317 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2320 case ir_binop_ldexp
:
2321 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2322 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2324 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2328 case ir_unop_pack_half_2x16
:
2329 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2331 case ir_unop_unpack_half_2x16
:
2332 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2335 case ir_unop_get_buffer_size
: {
2336 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2339 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2340 (const_offset
? const_offset
->value
.u
[0] : 0),
2342 if (!const_offset
) {
2343 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2344 *buffer
.reladdr
= op
[0];
2345 emit_arl(ir
, sampler_reladdr
, op
[0]);
2347 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2351 case ir_unop_vote_any
:
2352 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2354 case ir_unop_vote_all
:
2355 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2357 case ir_unop_vote_eq
:
2358 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2362 case ir_unop_b2i64
: {
2363 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2364 st_dst_reg temp_dst
= st_dst_reg(temp
);
2365 unsigned orig_swz
= op
[0].swizzle
;
2367 * To convert unsigned to 64-bit:
2368 * zero Y channel, copy X channel.
2370 temp_dst
.writemask
= WRITEMASK_Y
;
2371 if (vector_elements
> 1)
2372 temp_dst
.writemask
|= WRITEMASK_W
;
2373 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2374 temp_dst
.writemask
= WRITEMASK_X
;
2375 if (vector_elements
> 1)
2376 temp_dst
.writemask
|= WRITEMASK_Z
;
2377 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2378 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2379 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2380 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2382 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2384 result_src
.type
= GLSL_TYPE_UINT64
;
2385 if (vector_elements
> 2) {
2386 /* Subtle: We rely on the fact that get_temp here returns the next
2387 * TGSI temporary register directly after the temp register used for
2388 * the first two components, so that the result gets picked up
2391 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2392 st_dst_reg temp_dst
= st_dst_reg(temp
);
2393 temp_dst
.writemask
= WRITEMASK_Y
;
2394 if (vector_elements
> 3)
2395 temp_dst
.writemask
|= WRITEMASK_W
;
2396 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2398 temp_dst
.writemask
= WRITEMASK_X
;
2399 if (vector_elements
> 3)
2400 temp_dst
.writemask
|= WRITEMASK_Z
;
2401 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2402 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2403 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2404 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2406 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2413 case ir_unop_i642u
: {
2414 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2415 st_dst_reg temp_dst
= st_dst_reg(temp
);
2416 unsigned orig_swz
= op
[0].swizzle
;
2417 unsigned orig_idx
= op
[0].index
;
2419 temp_dst
.writemask
= WRITEMASK_X
;
2421 for (el
= 0; el
< vector_elements
; el
++) {
2422 unsigned swz
= GET_SWZ(orig_swz
, el
);
2424 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2426 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2428 op
[0].index
= orig_idx
+ 1;
2429 op
[0].type
= GLSL_TYPE_UINT
;
2430 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2431 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2434 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2435 result_src
.type
= GLSL_TYPE_UINT
;
2437 result_src
.type
= GLSL_TYPE_INT
;
2441 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2444 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2447 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2450 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2453 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2456 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2459 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2462 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2465 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2468 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2471 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2473 /* these might be needed */
2474 case ir_unop_pack_snorm_2x16
:
2475 case ir_unop_pack_unorm_2x16
:
2476 case ir_unop_pack_snorm_4x8
:
2477 case ir_unop_pack_unorm_4x8
:
2479 case ir_unop_unpack_snorm_2x16
:
2480 case ir_unop_unpack_unorm_2x16
:
2481 case ir_unop_unpack_snorm_4x8
:
2482 case ir_unop_unpack_unorm_4x8
:
2484 case ir_quadop_vector
:
2485 case ir_binop_vector_extract
:
2486 case ir_triop_vector_insert
:
2487 case ir_binop_carry
:
2488 case ir_binop_borrow
:
2489 case ir_unop_ssbo_unsized_array_length
:
2490 /* This operation is not supported, or should have already been handled.
2492 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2496 this->result
= result_src
;
2501 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2507 /* Note that this is only swizzles in expressions, not those on the left
2508 * hand side of an assignment, which do write masking. See ir_assignment
2512 ir
->val
->accept(this);
2514 assert(src
.file
!= PROGRAM_UNDEFINED
);
2515 assert(ir
->type
->vector_elements
> 0);
2517 for (i
= 0; i
< 4; i
++) {
2518 if (i
< ir
->type
->vector_elements
) {
2521 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2524 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2527 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2530 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2534 /* If the type is smaller than a vec4, replicate the last
2537 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2541 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2546 /* Test if the variable is an array. Note that geometry and
2547 * tessellation shader inputs are outputs are always arrays (except
2548 * for patch inputs), so only the array element type is considered.
2551 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2553 const glsl_type
*type
= var
->type
;
2555 *remove_array
= false;
2557 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2558 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2561 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2562 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2563 stage
== MESA_SHADER_TESS_CTRL
) &&
2565 if (!var
->type
->is_array())
2566 return false; /* a system value probably */
2568 type
= var
->type
->fields
.array
;
2569 *remove_array
= true;
2572 return type
->is_array() || type
->is_matrix();
2576 st_translate_interp_loc(ir_variable
*var
)
2578 if (var
->data
.centroid
)
2579 return TGSI_INTERPOLATE_LOC_CENTROID
;
2580 else if (var
->data
.sample
)
2581 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2583 return TGSI_INTERPOLATE_LOC_CENTER
;
2587 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2589 variable_storage
*entry
= find_variable_storage(ir
->var
);
2590 ir_variable
*var
= ir
->var
;
2594 switch (var
->data
.mode
) {
2595 case ir_var_uniform
:
2596 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2597 var
->data
.param_index
);
2598 this->variables
.push_tail(entry
);
2600 case ir_var_shader_in
: {
2601 /* The linker assigns locations for varyings and attributes,
2602 * including deprecated builtins (like gl_Color), user-assign
2603 * generic attributes (glBindVertexLocation), and
2604 * user-defined varyings.
2606 assert(var
->data
.location
!= -1);
2608 const glsl_type
*type_without_array
= var
->type
->without_array();
2609 struct inout_decl
*decl
= &inputs
[num_inputs
];
2610 unsigned component
= var
->data
.location_frac
;
2611 unsigned num_components
;
2614 if (type_without_array
->is_64bit())
2615 component
= component
/ 2;
2616 if (type_without_array
->vector_elements
)
2617 num_components
= type_without_array
->vector_elements
;
2621 decl
->mesa_index
= var
->data
.location
;
2622 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2623 decl
->interp_loc
= st_translate_interp_loc(var
);
2624 decl
->base_type
= type_without_array
->base_type
;
2625 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2627 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2628 decl
->array_id
= num_input_arrays
+ 1;
2635 decl
->size
= type_size(var
->type
->fields
.array
);
2637 decl
->size
= type_size(var
->type
);
2639 entry
= new(mem_ctx
) variable_storage(var
,
2643 entry
->component
= component
;
2645 this->variables
.push_tail(entry
);
2648 case ir_var_shader_out
: {
2649 assert(var
->data
.location
!= -1);
2651 const glsl_type
*type_without_array
= var
->type
->without_array();
2652 struct inout_decl
*decl
= &outputs
[num_outputs
];
2653 unsigned component
= var
->data
.location_frac
;
2654 unsigned num_components
;
2657 if (type_without_array
->is_64bit())
2658 component
= component
/ 2;
2659 if (type_without_array
->vector_elements
)
2660 num_components
= type_without_array
->vector_elements
;
2664 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2665 decl
->base_type
= type_without_array
->base_type
;
2666 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2667 if (var
->data
.stream
& (1u << 31)) {
2668 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2670 assert(var
->data
.stream
< 4);
2671 decl
->gs_out_streams
= 0;
2672 for (unsigned i
= 0; i
< num_components
; ++i
)
2673 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2676 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2677 decl
->array_id
= num_output_arrays
+ 1;
2678 num_output_arrays
++;
2684 decl
->size
= type_size(var
->type
->fields
.array
);
2686 decl
->size
= type_size(var
->type
);
2688 if (var
->data
.fb_fetch_output
) {
2689 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2690 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2691 var
->type
, component
, decl
->array_id
);
2692 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2693 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2696 entry
= new(mem_ctx
) variable_storage(var
,
2701 entry
->component
= component
;
2703 this->variables
.push_tail(entry
);
2706 case ir_var_system_value
:
2707 entry
= new(mem_ctx
) variable_storage(var
,
2708 PROGRAM_SYSTEM_VALUE
,
2709 var
->data
.location
);
2712 case ir_var_temporary
:
2713 st_src_reg src
= get_temp(var
->type
);
2715 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2717 this->variables
.push_tail(entry
);
2723 printf("Failed to make storage for %s\n", var
->name
);
2728 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2729 entry
->component
, entry
->array_id
);
2730 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2731 this->result
.is_double_vertex_input
= true;
2732 if (!native_integers
)
2733 this->result
.type
= GLSL_TYPE_FLOAT
;
2737 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2738 GLbitfield64
* usage_mask
,
2739 GLbitfield64 double_usage_mask
,
2740 GLbitfield
* patch_usage_mask
)
2745 /* Fix array declarations by removing unused array elements at both ends
2746 * of the arrays. For example, mat4[3] where only mat[1] is used.
2748 for (i
= 0; i
< count
; i
++) {
2749 struct inout_decl
*decl
= &decls
[i
];
2750 if (!decl
->array_id
)
2753 /* Shrink the beginning. */
2754 for (j
= 0; j
< (int)decl
->size
; j
++) {
2755 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2756 if (*patch_usage_mask
&
2757 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2761 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2763 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2772 /* Shrink the end. */
2773 for (j
= decl
->size
-1; j
>= 0; j
--) {
2774 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2775 if (*patch_usage_mask
&
2776 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2780 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2782 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2789 /* When not all entries of an array are accessed, we mark them as used
2790 * here anyway, to ensure that the input/output mapping logic doesn't get
2793 * TODO This happens when an array isn't used via indirect access, which
2794 * some game ports do (at least eON-based). There is an optimization
2795 * opportunity here by replacing the array declaration with non-array
2796 * declarations of those slots that are actually used.
2798 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2799 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2800 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2802 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2808 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2812 int element_size
= type_size(ir
->type
);
2815 index
= ir
->array_index
->constant_expression_value();
2817 ir
->array
->accept(this);
2820 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2821 switch (this->prog
->Target
) {
2822 case GL_TESS_CONTROL_PROGRAM_NV
:
2823 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2824 !ir
->variable_referenced()->data
.patch
;
2826 case GL_TESS_EVALUATION_PROGRAM_NV
:
2827 is_2D
= src
.file
== PROGRAM_INPUT
&&
2828 !ir
->variable_referenced()->data
.patch
;
2830 case GL_GEOMETRY_PROGRAM_NV
:
2831 is_2D
= src
.file
== PROGRAM_INPUT
;
2841 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2842 src
.file
== PROGRAM_INPUT
)
2843 element_size
= attrib_type_size(ir
->type
, true);
2845 src
.index2D
= index
->value
.i
[0];
2846 src
.has_index2
= true;
2848 src
.index
+= index
->value
.i
[0] * element_size
;
2850 /* Variable index array dereference. It eats the "vec4" of the
2851 * base of the array and an index that offsets the TGSI register
2854 ir
->array_index
->accept(this);
2856 st_src_reg index_reg
;
2858 if (element_size
== 1) {
2859 index_reg
= this->result
;
2861 index_reg
= get_temp(native_integers
?
2862 glsl_type::int_type
: glsl_type::float_type
);
2864 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2865 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2868 /* If there was already a relative address register involved, add the
2869 * new and the old together to get the new offset.
2871 if (!is_2D
&& src
.reladdr
!= NULL
) {
2872 st_src_reg accum_reg
= get_temp(native_integers
?
2873 glsl_type::int_type
: glsl_type::float_type
);
2875 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2876 index_reg
, *src
.reladdr
);
2878 index_reg
= accum_reg
;
2882 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2883 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2885 src
.has_index2
= true;
2887 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2888 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2892 /* Change the register type to the element type of the array. */
2893 src
.type
= ir
->type
->base_type
;
2899 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2902 const glsl_type
*struct_type
= ir
->record
->type
;
2905 ir
->record
->accept(this);
2907 for (i
= 0; i
< struct_type
->length
; i
++) {
2908 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2910 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2913 /* If the type is smaller than a vec4, replicate the last channel out. */
2914 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2915 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2917 this->result
.swizzle
= SWIZZLE_NOOP
;
2919 this->result
.index
+= offset
;
2920 this->result
.type
= ir
->type
->base_type
;
2924 * We want to be careful in assignment setup to hit the actual storage
2925 * instead of potentially using a temporary like we might with the
2926 * ir_dereference handler.
2929 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2931 /* The LHS must be a dereference. If the LHS is a variable indexed array
2932 * access of a vector, it must be separated into a series conditional moves
2933 * before reaching this point (see ir_vec_index_to_cond_assign).
2935 assert(ir
->as_dereference());
2936 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2938 assert(!deref_array
->array
->type
->is_vector());
2941 /* Use the rvalue deref handler for the most part. We write swizzles using
2942 * the writemask, but we do extract the base component for enhanced layouts
2943 * from the source swizzle.
2946 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2947 return st_dst_reg(v
->result
);
2951 * Process the condition of a conditional assignment
2953 * Examines the condition of a conditional assignment to generate the optimal
2954 * first operand of a \c CMP instruction. If the condition is a relational
2955 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2956 * used as the source for the \c CMP instruction. Otherwise the comparison
2957 * is processed to a boolean result, and the boolean result is used as the
2958 * operand to the CMP instruction.
2961 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2963 ir_rvalue
*src_ir
= ir
;
2965 bool switch_order
= false;
2967 ir_expression
*const expr
= ir
->as_expression();
2969 if (native_integers
) {
2970 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2971 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2972 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2973 type
== GLSL_TYPE_BOOL
) {
2974 if (expr
->operation
== ir_binop_equal
) {
2975 if (expr
->operands
[0]->is_zero()) {
2976 src_ir
= expr
->operands
[1];
2977 switch_order
= true;
2979 else if (expr
->operands
[1]->is_zero()) {
2980 src_ir
= expr
->operands
[0];
2981 switch_order
= true;
2984 else if (expr
->operation
== ir_binop_nequal
) {
2985 if (expr
->operands
[0]->is_zero()) {
2986 src_ir
= expr
->operands
[1];
2988 else if (expr
->operands
[1]->is_zero()) {
2989 src_ir
= expr
->operands
[0];
2995 src_ir
->accept(this);
2996 return switch_order
;
2999 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
3000 bool zero_on_left
= false;
3002 if (expr
->operands
[0]->is_zero()) {
3003 src_ir
= expr
->operands
[1];
3004 zero_on_left
= true;
3005 } else if (expr
->operands
[1]->is_zero()) {
3006 src_ir
= expr
->operands
[0];
3007 zero_on_left
= false;
3011 * (a < 0) T F F ( a < 0) T F F
3012 * (0 < a) F F T (-a < 0) F F T
3013 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3014 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3015 * (a > 0) F F T (-a < 0) F F T
3016 * (0 > a) T F F ( a < 0) T F F
3017 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3018 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3020 * Note that exchanging the order of 0 and 'a' in the comparison simply
3021 * means that the value of 'a' should be negated.
3024 switch (expr
->operation
) {
3026 switch_order
= false;
3027 negate
= zero_on_left
;
3030 case ir_binop_greater
:
3031 switch_order
= false;
3032 negate
= !zero_on_left
;
3035 case ir_binop_lequal
:
3036 switch_order
= true;
3037 negate
= !zero_on_left
;
3040 case ir_binop_gequal
:
3041 switch_order
= true;
3042 negate
= zero_on_left
;
3046 /* This isn't the right kind of comparison afterall, so make sure
3047 * the whole condition is visited.
3055 src_ir
->accept(this);
3057 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3058 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3059 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3060 * computing the condition.
3063 this->result
.negate
= ~this->result
.negate
;
3065 return switch_order
;
3069 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3070 st_dst_reg
*l
, st_src_reg
*r
,
3071 st_src_reg
*cond
, bool cond_swap
)
3073 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
3074 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3075 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3081 if (type
->is_array()) {
3082 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3083 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3088 if (type
->is_matrix()) {
3089 const struct glsl_type
*vec_type
;
3091 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3092 type
->vector_elements
, 1);
3094 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3095 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3100 assert(type
->is_scalar() || type
->is_vector());
3102 l
->type
= type
->base_type
;
3103 r
->type
= type
->base_type
;
3105 st_src_reg l_src
= st_src_reg(*l
);
3106 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3108 if (native_integers
) {
3109 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3110 cond_swap
? l_src
: *r
,
3111 cond_swap
? *r
: l_src
);
3113 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3114 cond_swap
? l_src
: *r
,
3115 cond_swap
? *r
: l_src
);
3118 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3122 if (type
->is_dual_slot()) {
3124 if (r
->is_double_vertex_input
== false)
3130 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3136 ir
->rhs
->accept(this);
3139 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3143 int first_enabled_chan
= 0;
3145 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3147 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3148 variable
->data
.mode
== ir_var_shader_out
&&
3149 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3150 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3151 assert(ir
->lhs
->type
->is_scalar());
3152 assert(ir
->write_mask
== WRITEMASK_X
);
3154 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3155 l
.writemask
= WRITEMASK_Z
;
3157 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3158 l
.writemask
= WRITEMASK_Y
;
3160 } else if (ir
->write_mask
== 0) {
3161 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3163 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3166 l
.writemask
= u_bit_consecutive(0, num_elements
);
3168 /* The type is a struct or an array of (array of) structs. */
3169 l
.writemask
= WRITEMASK_XYZW
;
3172 l
.writemask
= ir
->write_mask
;
3175 for (int i
= 0; i
< 4; i
++) {
3176 if (l
.writemask
& (1 << i
)) {
3177 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3182 l
.writemask
= l
.writemask
<< dst_component
;
3184 /* Swizzle a small RHS vector into the channels being written.
3186 * glsl ir treats write_mask as dictating how many channels are
3187 * present on the RHS while TGSI treats write_mask as just
3188 * showing which channels of the vec4 RHS get written.
3190 for (int i
= 0; i
< 4; i
++) {
3191 if (l
.writemask
& (1 << i
))
3192 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3194 swizzles
[i
] = first_enabled_chan
;
3196 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3197 swizzles
[2], swizzles
[3]);
3200 assert(l
.file
!= PROGRAM_UNDEFINED
);
3201 assert(r
.file
!= PROGRAM_UNDEFINED
);
3203 if (ir
->condition
) {
3204 const bool switch_order
= this->process_move_condition(ir
->condition
);
3205 st_src_reg condition
= this->result
;
3207 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3208 } else if (ir
->rhs
->as_expression() &&
3209 this->instructions
.get_tail() &&
3210 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3211 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3212 type_size(ir
->lhs
->type
) == 1 &&
3213 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3214 /* To avoid emitting an extra MOV when assigning an expression to a
3215 * variable, emit the last instruction of the expression again, but
3216 * replace the destination register with the target of the assignment.
3217 * Dead code elimination will remove the original instruction.
3219 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3220 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3221 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3222 new_inst
->saturate
= inst
->saturate
;
3223 inst
->dead_mask
= inst
->dst
[0].writemask
;
3225 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3231 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3234 GLdouble stack_vals
[4] = { 0 };
3235 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3236 GLenum gl_type
= GL_NONE
;
3238 static int in_array
= 0;
3239 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3241 /* Unfortunately, 4 floats is all we can get into
3242 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3243 * aggregate constant and move each constant value into it. If we
3244 * get lucky, copy propagation will eliminate the extra moves.
3246 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3247 st_src_reg temp_base
= get_temp(ir
->type
);
3248 st_dst_reg temp
= st_dst_reg(temp_base
);
3250 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3251 int size
= type_size(field_value
->type
);
3255 field_value
->accept(this);
3258 for (i
= 0; i
< (unsigned int)size
; i
++) {
3259 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3265 this->result
= temp_base
;
3269 if (ir
->type
->is_array()) {
3270 st_src_reg temp_base
= get_temp(ir
->type
);
3271 st_dst_reg temp
= st_dst_reg(temp_base
);
3272 int size
= type_size(ir
->type
->fields
.array
);
3277 for (i
= 0; i
< ir
->type
->length
; i
++) {
3278 ir
->array_elements
[i
]->accept(this);
3280 for (int j
= 0; j
< size
; j
++) {
3281 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3287 this->result
= temp_base
;
3292 if (ir
->type
->is_matrix()) {
3293 st_src_reg mat
= get_temp(ir
->type
);
3294 st_dst_reg mat_column
= st_dst_reg(mat
);
3296 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3297 switch (ir
->type
->base_type
) {
3298 case GLSL_TYPE_FLOAT
:
3299 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3301 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3302 src
.index
= add_constant(file
,
3304 ir
->type
->vector_elements
,
3307 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3309 case GLSL_TYPE_DOUBLE
:
3310 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3311 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3312 src
.index
= add_constant(file
,
3314 ir
->type
->vector_elements
,
3317 if (ir
->type
->vector_elements
>= 2) {
3318 mat_column
.writemask
= WRITEMASK_XY
;
3319 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3320 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3322 mat_column
.writemask
= WRITEMASK_X
;
3323 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3324 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3327 if (ir
->type
->vector_elements
> 2) {
3328 if (ir
->type
->vector_elements
== 4) {
3329 mat_column
.writemask
= WRITEMASK_ZW
;
3330 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3331 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3333 mat_column
.writemask
= WRITEMASK_Z
;
3334 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3335 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3336 mat_column
.writemask
= WRITEMASK_XYZW
;
3337 src
.swizzle
= SWIZZLE_XYZW
;
3343 unreachable("Illegal matrix constant type.\n");
3352 switch (ir
->type
->base_type
) {
3353 case GLSL_TYPE_FLOAT
:
3355 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3356 values
[i
].f
= ir
->value
.f
[i
];
3359 case GLSL_TYPE_DOUBLE
:
3360 gl_type
= GL_DOUBLE
;
3361 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3362 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3365 case GLSL_TYPE_INT64
:
3366 gl_type
= GL_INT64_ARB
;
3367 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3368 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3371 case GLSL_TYPE_UINT64
:
3372 gl_type
= GL_UNSIGNED_INT64_ARB
;
3373 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3374 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3377 case GLSL_TYPE_UINT
:
3378 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3379 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3380 if (native_integers
)
3381 values
[i
].u
= ir
->value
.u
[i
];
3383 values
[i
].f
= ir
->value
.u
[i
];
3387 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3388 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3389 if (native_integers
)
3390 values
[i
].i
= ir
->value
.i
[i
];
3392 values
[i
].f
= ir
->value
.i
[i
];
3395 case GLSL_TYPE_BOOL
:
3396 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3397 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3398 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3402 assert(!"Non-float/uint/int/bool constant");
3405 this->result
= st_src_reg(file
, -1, ir
->type
);
3406 this->result
.index
= add_constant(file
,
3408 ir
->type
->vector_elements
,
3410 &this->result
.swizzle
);
3414 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3416 exec_node
*param
= ir
->actual_parameters
.get_head();
3417 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3418 ir_variable
*location
= deref
->variable_referenced();
3421 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3423 /* Calculate the surface offset */
3425 unsigned array_size
= 0, base
= 0;
3428 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3430 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3431 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3432 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3433 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3434 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3436 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3439 ir
->return_deref
->accept(this);
3440 st_dst_reg
dst(this->result
);
3441 dst
.writemask
= WRITEMASK_X
;
3443 glsl_to_tgsi_instruction
*inst
;
3445 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3446 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3447 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3448 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3449 st_src_reg_for_int(1));
3450 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3451 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3452 st_src_reg_for_int(-1));
3453 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3455 param
= param
->get_next();
3456 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3459 st_src_reg data
= this->result
, data2
= undef_src
;
3461 switch (ir
->callee
->intrinsic_id
) {
3462 case ir_intrinsic_atomic_counter_add
:
3463 opcode
= TGSI_OPCODE_ATOMUADD
;
3465 case ir_intrinsic_atomic_counter_min
:
3466 opcode
= TGSI_OPCODE_ATOMIMIN
;
3468 case ir_intrinsic_atomic_counter_max
:
3469 opcode
= TGSI_OPCODE_ATOMIMAX
;
3471 case ir_intrinsic_atomic_counter_and
:
3472 opcode
= TGSI_OPCODE_ATOMAND
;
3474 case ir_intrinsic_atomic_counter_or
:
3475 opcode
= TGSI_OPCODE_ATOMOR
;
3477 case ir_intrinsic_atomic_counter_xor
:
3478 opcode
= TGSI_OPCODE_ATOMXOR
;
3480 case ir_intrinsic_atomic_counter_exchange
:
3481 opcode
= TGSI_OPCODE_ATOMXCHG
;
3483 case ir_intrinsic_atomic_counter_comp_swap
: {
3484 opcode
= TGSI_OPCODE_ATOMCAS
;
3485 param
= param
->get_next();
3486 val
= ((ir_instruction
*)param
)->as_rvalue();
3488 data2
= this->result
;
3492 assert(!"Unexpected intrinsic");
3496 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3499 inst
->resource
= buffer
;
3503 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3505 exec_node
*param
= ir
->actual_parameters
.get_head();
3507 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3509 param
= param
->get_next();
3510 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3512 ir_constant
*const_block
= block
->as_constant();
3516 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3517 (const_block
? const_block
->value
.u
[0] : 0),
3521 block
->accept(this);
3522 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3523 *buffer
.reladdr
= this->result
;
3524 emit_arl(ir
, sampler_reladdr
, this->result
);
3527 /* Calculate the surface offset */
3528 offset
->accept(this);
3529 st_src_reg off
= this->result
;
3531 st_dst_reg dst
= undef_dst
;
3532 if (ir
->return_deref
) {
3533 ir
->return_deref
->accept(this);
3534 dst
= st_dst_reg(this->result
);
3535 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3538 glsl_to_tgsi_instruction
*inst
;
3540 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3541 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3542 if (dst
.type
== GLSL_TYPE_BOOL
)
3543 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3544 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3545 param
= param
->get_next();
3546 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3549 param
= param
->get_next();
3550 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3552 dst
.writemask
= write_mask
->value
.u
[0];
3554 dst
.type
= this->result
.type
;
3555 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3557 param
= param
->get_next();
3558 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3561 st_src_reg data
= this->result
, data2
= undef_src
;
3563 switch (ir
->callee
->intrinsic_id
) {
3564 case ir_intrinsic_ssbo_atomic_add
:
3565 opcode
= TGSI_OPCODE_ATOMUADD
;
3567 case ir_intrinsic_ssbo_atomic_min
:
3568 opcode
= TGSI_OPCODE_ATOMIMIN
;
3570 case ir_intrinsic_ssbo_atomic_max
:
3571 opcode
= TGSI_OPCODE_ATOMIMAX
;
3573 case ir_intrinsic_ssbo_atomic_and
:
3574 opcode
= TGSI_OPCODE_ATOMAND
;
3576 case ir_intrinsic_ssbo_atomic_or
:
3577 opcode
= TGSI_OPCODE_ATOMOR
;
3579 case ir_intrinsic_ssbo_atomic_xor
:
3580 opcode
= TGSI_OPCODE_ATOMXOR
;
3582 case ir_intrinsic_ssbo_atomic_exchange
:
3583 opcode
= TGSI_OPCODE_ATOMXCHG
;
3585 case ir_intrinsic_ssbo_atomic_comp_swap
:
3586 opcode
= TGSI_OPCODE_ATOMCAS
;
3587 param
= param
->get_next();
3588 val
= ((ir_instruction
*)param
)->as_rvalue();
3590 data2
= this->result
;
3593 assert(!"Unexpected intrinsic");
3597 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3600 param
= param
->get_next();
3601 ir_constant
*access
= NULL
;
3602 if (!param
->is_tail_sentinel()) {
3603 access
= ((ir_instruction
*)param
)->as_constant();
3607 /* The emit_asm() might have actually split the op into pieces, e.g. for
3608 * double stores. We have to go back and fix up all the generated ops.
3610 unsigned op
= inst
->op
;
3612 inst
->resource
= buffer
;
3614 inst
->buffer_access
= access
->value
.u
[0];
3616 if (inst
== this->instructions
.get_head_raw())
3618 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3620 if (inst
->op
== TGSI_OPCODE_UADD
) {
3621 if (inst
== this->instructions
.get_head_raw())
3623 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3625 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3629 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3631 switch (ir
->callee
->intrinsic_id
) {
3632 case ir_intrinsic_memory_barrier
:
3633 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3634 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3635 TGSI_MEMBAR_ATOMIC_BUFFER
|
3636 TGSI_MEMBAR_SHADER_IMAGE
|
3637 TGSI_MEMBAR_SHARED
));
3639 case ir_intrinsic_memory_barrier_atomic_counter
:
3640 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3641 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3643 case ir_intrinsic_memory_barrier_buffer
:
3644 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3645 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3647 case ir_intrinsic_memory_barrier_image
:
3648 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3649 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3651 case ir_intrinsic_memory_barrier_shared
:
3652 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3653 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3655 case ir_intrinsic_group_memory_barrier
:
3656 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3657 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3658 TGSI_MEMBAR_ATOMIC_BUFFER
|
3659 TGSI_MEMBAR_SHADER_IMAGE
|
3660 TGSI_MEMBAR_SHARED
|
3661 TGSI_MEMBAR_THREAD_GROUP
));
3664 assert(!"Unexpected memory barrier intrinsic");
3669 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3671 exec_node
*param
= ir
->actual_parameters
.get_head();
3673 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3675 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3677 /* Calculate the surface offset */
3678 offset
->accept(this);
3679 st_src_reg off
= this->result
;
3681 st_dst_reg dst
= undef_dst
;
3682 if (ir
->return_deref
) {
3683 ir
->return_deref
->accept(this);
3684 dst
= st_dst_reg(this->result
);
3685 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3688 glsl_to_tgsi_instruction
*inst
;
3690 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3691 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3692 inst
->resource
= buffer
;
3693 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3694 param
= param
->get_next();
3695 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3698 param
= param
->get_next();
3699 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3701 dst
.writemask
= write_mask
->value
.u
[0];
3703 dst
.type
= this->result
.type
;
3704 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3705 inst
->resource
= buffer
;
3707 param
= param
->get_next();
3708 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3711 st_src_reg data
= this->result
, data2
= undef_src
;
3713 switch (ir
->callee
->intrinsic_id
) {
3714 case ir_intrinsic_shared_atomic_add
:
3715 opcode
= TGSI_OPCODE_ATOMUADD
;
3717 case ir_intrinsic_shared_atomic_min
:
3718 opcode
= TGSI_OPCODE_ATOMIMIN
;
3720 case ir_intrinsic_shared_atomic_max
:
3721 opcode
= TGSI_OPCODE_ATOMIMAX
;
3723 case ir_intrinsic_shared_atomic_and
:
3724 opcode
= TGSI_OPCODE_ATOMAND
;
3726 case ir_intrinsic_shared_atomic_or
:
3727 opcode
= TGSI_OPCODE_ATOMOR
;
3729 case ir_intrinsic_shared_atomic_xor
:
3730 opcode
= TGSI_OPCODE_ATOMXOR
;
3732 case ir_intrinsic_shared_atomic_exchange
:
3733 opcode
= TGSI_OPCODE_ATOMXCHG
;
3735 case ir_intrinsic_shared_atomic_comp_swap
:
3736 opcode
= TGSI_OPCODE_ATOMCAS
;
3737 param
= param
->get_next();
3738 val
= ((ir_instruction
*)param
)->as_rvalue();
3740 data2
= this->result
;
3743 assert(!"Unexpected intrinsic");
3747 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3748 inst
->resource
= buffer
;
3753 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3755 exec_node
*param
= ir
->actual_parameters
.get_head();
3757 ir_dereference
*img
= (ir_dereference
*)param
;
3758 const ir_variable
*imgvar
= img
->variable_referenced();
3759 const glsl_type
*type
= imgvar
->type
->without_array();
3760 unsigned sampler_array_size
= 1, sampler_base
= 0;
3763 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3765 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3766 (uint16_t*)&image
.index
, &reladdr
, true);
3768 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3769 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3770 *image
.reladdr
= reladdr
;
3771 emit_arl(ir
, sampler_reladdr
, reladdr
);
3774 st_dst_reg dst
= undef_dst
;
3775 if (ir
->return_deref
) {
3776 ir
->return_deref
->accept(this);
3777 dst
= st_dst_reg(this->result
);
3778 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3781 glsl_to_tgsi_instruction
*inst
;
3783 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3784 dst
.writemask
= WRITEMASK_XYZ
;
3785 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3786 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3787 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3788 st_dst_reg dstres
= st_dst_reg(res
);
3789 dstres
.writemask
= WRITEMASK_W
;
3790 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3791 res
.swizzle
= SWIZZLE_WWWW
;
3792 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3794 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3796 st_dst_reg coord_dst
;
3797 coord
= get_temp(glsl_type::ivec4_type
);
3798 coord_dst
= st_dst_reg(coord
);
3799 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3800 param
= param
->get_next();
3801 ((ir_dereference
*)param
)->accept(this);
3802 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3803 coord
.swizzle
= SWIZZLE_XXXX
;
3804 switch (type
->coordinate_components()) {
3805 case 4: assert(!"unexpected coord count");
3807 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3809 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3812 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3813 param
= param
->get_next();
3814 ((ir_dereference
*)param
)->accept(this);
3815 st_src_reg sample
= this->result
;
3816 sample
.swizzle
= SWIZZLE_XXXX
;
3817 coord_dst
.writemask
= WRITEMASK_W
;
3818 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3819 coord
.swizzle
|= SWIZZLE_W
<< 9;
3822 param
= param
->get_next();
3823 if (!param
->is_tail_sentinel()) {
3824 ((ir_dereference
*)param
)->accept(this);
3825 arg1
= this->result
;
3826 param
= param
->get_next();
3829 if (!param
->is_tail_sentinel()) {
3830 ((ir_dereference
*)param
)->accept(this);
3831 arg2
= this->result
;
3832 param
= param
->get_next();
3835 assert(param
->is_tail_sentinel());
3838 switch (ir
->callee
->intrinsic_id
) {
3839 case ir_intrinsic_image_load
:
3840 opcode
= TGSI_OPCODE_LOAD
;
3842 case ir_intrinsic_image_store
:
3843 opcode
= TGSI_OPCODE_STORE
;
3845 case ir_intrinsic_image_atomic_add
:
3846 opcode
= TGSI_OPCODE_ATOMUADD
;
3848 case ir_intrinsic_image_atomic_min
:
3849 opcode
= TGSI_OPCODE_ATOMIMIN
;
3851 case ir_intrinsic_image_atomic_max
:
3852 opcode
= TGSI_OPCODE_ATOMIMAX
;
3854 case ir_intrinsic_image_atomic_and
:
3855 opcode
= TGSI_OPCODE_ATOMAND
;
3857 case ir_intrinsic_image_atomic_or
:
3858 opcode
= TGSI_OPCODE_ATOMOR
;
3860 case ir_intrinsic_image_atomic_xor
:
3861 opcode
= TGSI_OPCODE_ATOMXOR
;
3863 case ir_intrinsic_image_atomic_exchange
:
3864 opcode
= TGSI_OPCODE_ATOMXCHG
;
3866 case ir_intrinsic_image_atomic_comp_swap
:
3867 opcode
= TGSI_OPCODE_ATOMCAS
;
3870 assert(!"Unexpected intrinsic");
3874 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3875 if (opcode
== TGSI_OPCODE_STORE
)
3876 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3879 inst
->resource
= image
;
3880 inst
->sampler_array_size
= sampler_array_size
;
3881 inst
->sampler_base
= sampler_base
;
3883 inst
->tex_target
= type
->sampler_index();
3884 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3885 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3887 if (imgvar
->data
.image_coherent
)
3888 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3889 if (imgvar
->data
.image_restrict
)
3890 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3891 if (imgvar
->data
.image_volatile
)
3892 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3896 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3898 ir_function_signature
*sig
= ir
->callee
;
3900 /* Filter out intrinsics */
3901 switch (sig
->intrinsic_id
) {
3902 case ir_intrinsic_atomic_counter_read
:
3903 case ir_intrinsic_atomic_counter_increment
:
3904 case ir_intrinsic_atomic_counter_predecrement
:
3905 case ir_intrinsic_atomic_counter_add
:
3906 case ir_intrinsic_atomic_counter_min
:
3907 case ir_intrinsic_atomic_counter_max
:
3908 case ir_intrinsic_atomic_counter_and
:
3909 case ir_intrinsic_atomic_counter_or
:
3910 case ir_intrinsic_atomic_counter_xor
:
3911 case ir_intrinsic_atomic_counter_exchange
:
3912 case ir_intrinsic_atomic_counter_comp_swap
:
3913 visit_atomic_counter_intrinsic(ir
);
3916 case ir_intrinsic_ssbo_load
:
3917 case ir_intrinsic_ssbo_store
:
3918 case ir_intrinsic_ssbo_atomic_add
:
3919 case ir_intrinsic_ssbo_atomic_min
:
3920 case ir_intrinsic_ssbo_atomic_max
:
3921 case ir_intrinsic_ssbo_atomic_and
:
3922 case ir_intrinsic_ssbo_atomic_or
:
3923 case ir_intrinsic_ssbo_atomic_xor
:
3924 case ir_intrinsic_ssbo_atomic_exchange
:
3925 case ir_intrinsic_ssbo_atomic_comp_swap
:
3926 visit_ssbo_intrinsic(ir
);
3929 case ir_intrinsic_memory_barrier
:
3930 case ir_intrinsic_memory_barrier_atomic_counter
:
3931 case ir_intrinsic_memory_barrier_buffer
:
3932 case ir_intrinsic_memory_barrier_image
:
3933 case ir_intrinsic_memory_barrier_shared
:
3934 case ir_intrinsic_group_memory_barrier
:
3935 visit_membar_intrinsic(ir
);
3938 case ir_intrinsic_shared_load
:
3939 case ir_intrinsic_shared_store
:
3940 case ir_intrinsic_shared_atomic_add
:
3941 case ir_intrinsic_shared_atomic_min
:
3942 case ir_intrinsic_shared_atomic_max
:
3943 case ir_intrinsic_shared_atomic_and
:
3944 case ir_intrinsic_shared_atomic_or
:
3945 case ir_intrinsic_shared_atomic_xor
:
3946 case ir_intrinsic_shared_atomic_exchange
:
3947 case ir_intrinsic_shared_atomic_comp_swap
:
3948 visit_shared_intrinsic(ir
);
3951 case ir_intrinsic_image_load
:
3952 case ir_intrinsic_image_store
:
3953 case ir_intrinsic_image_atomic_add
:
3954 case ir_intrinsic_image_atomic_min
:
3955 case ir_intrinsic_image_atomic_max
:
3956 case ir_intrinsic_image_atomic_and
:
3957 case ir_intrinsic_image_atomic_or
:
3958 case ir_intrinsic_image_atomic_xor
:
3959 case ir_intrinsic_image_atomic_exchange
:
3960 case ir_intrinsic_image_atomic_comp_swap
:
3961 case ir_intrinsic_image_size
:
3962 case ir_intrinsic_image_samples
:
3963 visit_image_intrinsic(ir
);
3966 case ir_intrinsic_shader_clock
: {
3967 ir
->return_deref
->accept(this);
3969 st_dst_reg dst
= st_dst_reg(this->result
);
3970 dst
.writemask
= TGSI_WRITEMASK_XY
;
3972 emit_asm(ir
, TGSI_OPCODE_CLOCK
, dst
);
3976 case ir_intrinsic_invalid
:
3977 case ir_intrinsic_generic_load
:
3978 case ir_intrinsic_generic_store
:
3979 case ir_intrinsic_generic_atomic_add
:
3980 case ir_intrinsic_generic_atomic_and
:
3981 case ir_intrinsic_generic_atomic_or
:
3982 case ir_intrinsic_generic_atomic_xor
:
3983 case ir_intrinsic_generic_atomic_min
:
3984 case ir_intrinsic_generic_atomic_max
:
3985 case ir_intrinsic_generic_atomic_exchange
:
3986 case ir_intrinsic_generic_atomic_comp_swap
:
3987 unreachable("Invalid intrinsic");
3992 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3993 unsigned *array_elements
,
3995 st_src_reg
*indirect
,
3998 switch (tail
->ir_type
) {
3999 case ir_type_dereference_record
: {
4000 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4001 const glsl_type
*struct_type
= deref_record
->record
->type
;
4002 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
4004 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4006 assert(field_index
>= 0);
4007 *location
+= struct_type
->record_location_offset(field_index
);
4011 case ir_type_dereference_array
: {
4012 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4013 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
4016 st_src_reg temp_reg
;
4017 st_dst_reg temp_dst
;
4019 temp_reg
= get_temp(glsl_type::uint_type
);
4020 temp_dst
= st_dst_reg(temp_reg
);
4021 temp_dst
.writemask
= 1;
4023 deref_arr
->array_index
->accept(this);
4024 if (*array_elements
!= 1)
4025 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4027 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4029 if (indirect
->file
== PROGRAM_UNDEFINED
)
4030 *indirect
= temp_reg
;
4032 temp_dst
= st_dst_reg(*indirect
);
4033 temp_dst
.writemask
= 1;
4034 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4037 *index
+= array_index
->value
.u
[0] * *array_elements
;
4039 *array_elements
*= deref_arr
->array
->type
->length
;
4041 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4050 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4051 unsigned *array_size
,
4054 st_src_reg
*reladdr
,
4057 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4058 unsigned location
= 0;
4059 ir_variable
*var
= ir
->variable_referenced();
4061 memset(reladdr
, 0, sizeof(*reladdr
));
4062 reladdr
->file
= PROGRAM_UNDEFINED
;
4068 location
= var
->data
.location
;
4069 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4072 * If we end up with no indirect then adjust the base to the index,
4073 * and set the array size to 1.
4075 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4081 assert(location
!= 0xffffffff);
4082 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4083 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4088 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4090 if (offset
.reladdr
|| offset
.reladdr2
) {
4091 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4092 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4093 tmp_dst
.writemask
= WRITEMASK_XY
;
4094 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4102 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4104 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4105 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4106 st_src_reg levels_src
, reladdr
;
4107 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4108 glsl_to_tgsi_instruction
*inst
= NULL
;
4109 unsigned opcode
= TGSI_OPCODE_NOP
;
4110 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4111 unsigned sampler_array_size
= 1, sampler_base
= 0;
4112 uint16_t sampler_index
= 0;
4113 bool is_cube_array
= false, is_cube_shadow
= false;
4116 /* if we are a cube array sampler or a cube shadow */
4117 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4118 is_cube_array
= sampler_type
->sampler_array
;
4119 is_cube_shadow
= sampler_type
->sampler_shadow
;
4122 if (ir
->coordinate
) {
4123 ir
->coordinate
->accept(this);
4125 /* Put our coords in a temp. We'll need to modify them for shadow,
4126 * projection, or LOD, so the only case we'd use it as-is is if
4127 * we're doing plain old texturing. The optimization passes on
4128 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4130 coord
= get_temp(glsl_type::vec4_type
);
4131 coord_dst
= st_dst_reg(coord
);
4132 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4133 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4136 if (ir
->projector
) {
4137 ir
->projector
->accept(this);
4138 projector
= this->result
;
4141 /* Storage for our result. Ideally for an assignment we'd be using
4142 * the actual storage for the result here, instead.
4144 result_src
= get_temp(ir
->type
);
4145 result_dst
= st_dst_reg(result_src
);
4146 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4150 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4152 ir
->offset
->accept(this);
4153 offset
[0] = this->result
;
4157 if (is_cube_array
|| is_cube_shadow
) {
4158 opcode
= TGSI_OPCODE_TXB2
;
4161 opcode
= TGSI_OPCODE_TXB
;
4163 ir
->lod_info
.bias
->accept(this);
4164 lod_info
= this->result
;
4166 ir
->offset
->accept(this);
4167 offset
[0] = this->result
;
4171 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4172 opcode
= TGSI_OPCODE_TEX_LZ
;
4174 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4175 ir
->lod_info
.lod
->accept(this);
4176 lod_info
= this->result
;
4179 ir
->offset
->accept(this);
4180 offset
[0] = this->result
;
4184 opcode
= TGSI_OPCODE_TXD
;
4185 ir
->lod_info
.grad
.dPdx
->accept(this);
4187 ir
->lod_info
.grad
.dPdy
->accept(this);
4190 ir
->offset
->accept(this);
4191 offset
[0] = this->result
;
4195 opcode
= TGSI_OPCODE_TXQ
;
4196 ir
->lod_info
.lod
->accept(this);
4197 lod_info
= this->result
;
4199 case ir_query_levels
:
4200 opcode
= TGSI_OPCODE_TXQ
;
4201 lod_info
= undef_src
;
4202 levels_src
= get_temp(ir
->type
);
4205 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4206 opcode
= TGSI_OPCODE_TXF_LZ
;
4208 opcode
= TGSI_OPCODE_TXF
;
4209 ir
->lod_info
.lod
->accept(this);
4210 lod_info
= this->result
;
4213 ir
->offset
->accept(this);
4214 offset
[0] = this->result
;
4218 opcode
= TGSI_OPCODE_TXF
;
4219 ir
->lod_info
.sample_index
->accept(this);
4220 sample_index
= this->result
;
4223 opcode
= TGSI_OPCODE_TG4
;
4224 ir
->lod_info
.component
->accept(this);
4225 component
= this->result
;
4227 ir
->offset
->accept(this);
4228 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4229 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4230 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4231 offset
[i
] = this->result
;
4232 offset
[i
].index
+= i
* type_size(elt_type
);
4233 offset
[i
].type
= elt_type
->base_type
;
4234 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4235 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4238 offset
[0] = canonicalize_gather_offset(this->result
);
4243 opcode
= TGSI_OPCODE_LODQ
;
4245 case ir_texture_samples
:
4246 opcode
= TGSI_OPCODE_TXQS
;
4248 case ir_samples_identical
:
4249 unreachable("Unexpected ir_samples_identical opcode");
4252 if (ir
->projector
) {
4253 if (opcode
== TGSI_OPCODE_TEX
) {
4254 /* Slot the projector in as the last component of the coord. */
4255 coord_dst
.writemask
= WRITEMASK_W
;
4256 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4257 coord_dst
.writemask
= WRITEMASK_XYZW
;
4258 opcode
= TGSI_OPCODE_TXP
;
4260 st_src_reg coord_w
= coord
;
4261 coord_w
.swizzle
= SWIZZLE_WWWW
;
4263 /* For the other TEX opcodes there's no projective version
4264 * since the last slot is taken up by LOD info. Do the
4265 * projective divide now.
4267 coord_dst
.writemask
= WRITEMASK_W
;
4268 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4270 /* In the case where we have to project the coordinates "by hand,"
4271 * the shadow comparator value must also be projected.
4273 st_src_reg tmp_src
= coord
;
4274 if (ir
->shadow_comparator
) {
4275 /* Slot the shadow value in as the second to last component of the
4278 ir
->shadow_comparator
->accept(this);
4280 tmp_src
= get_temp(glsl_type::vec4_type
);
4281 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4283 /* Projective division not allowed for array samplers. */
4284 assert(!sampler_type
->sampler_array
);
4286 tmp_dst
.writemask
= WRITEMASK_Z
;
4287 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4289 tmp_dst
.writemask
= WRITEMASK_XY
;
4290 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4293 coord_dst
.writemask
= WRITEMASK_XYZ
;
4294 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4296 coord_dst
.writemask
= WRITEMASK_XYZW
;
4297 coord
.swizzle
= SWIZZLE_XYZW
;
4301 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4302 * comparator was put in the correct place (and projected) by the code,
4303 * above, that handles by-hand projection.
4305 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4306 /* Slot the shadow value in as the second to last component of the
4309 ir
->shadow_comparator
->accept(this);
4311 if (is_cube_array
) {
4312 cube_sc
= get_temp(glsl_type::float_type
);
4313 cube_sc_dst
= st_dst_reg(cube_sc
);
4314 cube_sc_dst
.writemask
= WRITEMASK_X
;
4315 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4316 cube_sc_dst
.writemask
= WRITEMASK_X
;
4319 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4320 sampler_type
->sampler_array
) ||
4321 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4322 coord_dst
.writemask
= WRITEMASK_W
;
4324 coord_dst
.writemask
= WRITEMASK_Z
;
4326 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4327 coord_dst
.writemask
= WRITEMASK_XYZW
;
4331 if (ir
->op
== ir_txf_ms
) {
4332 coord_dst
.writemask
= WRITEMASK_W
;
4333 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4334 coord_dst
.writemask
= WRITEMASK_XYZW
;
4335 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4336 opcode
== TGSI_OPCODE_TXF
) {
4337 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4338 coord_dst
.writemask
= WRITEMASK_W
;
4339 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4340 coord_dst
.writemask
= WRITEMASK_XYZW
;
4343 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4344 &sampler_index
, &reladdr
, true);
4345 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4346 emit_arl(ir
, sampler_reladdr
, reladdr
);
4348 if (opcode
== TGSI_OPCODE_TXD
)
4349 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4350 else if (opcode
== TGSI_OPCODE_TXQ
) {
4351 if (ir
->op
== ir_query_levels
) {
4352 /* the level is stored in W */
4353 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4354 result_dst
.writemask
= WRITEMASK_X
;
4355 levels_src
.swizzle
= SWIZZLE_WWWW
;
4356 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4358 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4359 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4360 inst
= emit_asm(ir
, opcode
, result_dst
);
4361 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4362 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4363 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4364 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4365 } else if (opcode
== TGSI_OPCODE_TG4
) {
4366 if (is_cube_array
&& ir
->shadow_comparator
) {
4367 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4369 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4372 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4374 if (ir
->shadow_comparator
)
4375 inst
->tex_shadow
= GL_TRUE
;
4377 inst
->resource
.index
= sampler_index
;
4378 inst
->sampler_array_size
= sampler_array_size
;
4379 inst
->sampler_base
= sampler_base
;
4381 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4382 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4383 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4387 if (!inst
->tex_offsets
)
4388 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4390 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4391 inst
->tex_offsets
[i
] = offset
[i
];
4392 inst
->tex_offset_num_offset
= i
;
4395 inst
->tex_target
= sampler_type
->sampler_index();
4396 inst
->tex_type
= ir
->type
->base_type
;
4398 this->result
= result_src
;
4402 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4404 assert(!ir
->get_value());
4406 emit_asm(ir
, TGSI_OPCODE_RET
);
4410 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4412 if (ir
->condition
) {
4413 ir
->condition
->accept(this);
4414 st_src_reg condition
= this->result
;
4416 /* Convert the bool condition to a float so we can negate. */
4417 if (native_integers
) {
4418 st_src_reg temp
= get_temp(ir
->condition
->type
);
4419 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4420 condition
, st_src_reg_for_float(1.0));
4424 condition
.negate
= ~condition
.negate
;
4425 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4427 /* unconditional kil */
4428 emit_asm(ir
, TGSI_OPCODE_KILL
);
4433 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4436 glsl_to_tgsi_instruction
*if_inst
;
4438 ir
->condition
->accept(this);
4439 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4441 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4443 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4445 this->instructions
.push_tail(if_inst
);
4447 visit_exec_list(&ir
->then_instructions
, this);
4449 if (!ir
->else_instructions
.is_empty()) {
4450 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4451 visit_exec_list(&ir
->else_instructions
, this);
4454 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4459 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4461 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4463 ir
->stream
->accept(this);
4464 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4468 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4470 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4472 ir
->stream
->accept(this);
4473 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4477 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4479 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4480 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4482 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4485 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4487 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4489 result
.file
= PROGRAM_UNDEFINED
;
4496 num_input_arrays
= 0;
4497 num_output_arrays
= 0;
4499 num_address_regs
= 0;
4503 indirect_addr_consts
= false;
4504 wpos_transform_const
= -1;
4506 native_integers
= false;
4507 mem_ctx
= ralloc_context(NULL
);
4510 shader_program
= NULL
;
4515 use_shared_memory
= false;
4516 has_tex_txf_lz
= false;
4519 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4522 ralloc_free(mem_ctx
);
4525 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4532 * Count resources used by the given gpu program (number of texture
4536 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4538 v
->samplers_used
= 0;
4539 v
->buffers_used
= 0;
4542 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4543 if (inst
->info
->is_tex
) {
4544 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4545 unsigned idx
= inst
->sampler_base
+ i
;
4546 v
->samplers_used
|= 1u << idx
;
4548 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4549 v
->sampler_types
[idx
] = inst
->tex_type
;
4550 v
->sampler_targets
[idx
] =
4551 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4553 if (inst
->tex_shadow
) {
4554 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4559 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4560 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4562 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4563 is_resource_instruction(inst
->op
) ||
4564 inst
->op
== TGSI_OPCODE_STORE
)) {
4565 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4566 v
->buffers_used
|= 1 << inst
->resource
.index
;
4567 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4568 v
->use_shared_memory
= true;
4570 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4571 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4572 unsigned idx
= inst
->sampler_base
+ i
;
4573 v
->images_used
|= 1 << idx
;
4574 v
->image_targets
[idx
] =
4575 st_translate_texture_target(inst
->tex_target
, false);
4576 v
->image_formats
[idx
] = inst
->image_format
;
4581 prog
->SamplersUsed
= v
->samplers_used
;
4583 if (v
->shader_program
!= NULL
)
4584 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4588 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4589 * are read from the given src in this instruction
4592 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4594 int read_mask
= 0, comp
;
4596 /* Now, given the src swizzle and the written channels, find which
4597 * components are actually read
4599 for (comp
= 0; comp
< 4; ++comp
) {
4600 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4602 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4603 read_mask
|= 1 << coord
;
4610 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4611 * instruction is the first instruction to write to register T0. There are
4612 * several lowering passes done in GLSL IR (e.g. branches and
4613 * relative addressing) that create a large number of conditional assignments
4614 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4616 * Here is why this conversion is safe:
4617 * CMP T0, T1 T2 T0 can be expanded to:
4623 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4624 * as the original program. If (T1 < 0.0) evaluates to false, executing
4625 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4626 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4627 * because any instruction that was going to read from T0 after this was going
4628 * to read a garbage value anyway.
4631 glsl_to_tgsi_visitor::simplify_cmp(void)
4633 int tempWritesSize
= 0;
4634 unsigned *tempWrites
= NULL
;
4635 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4637 memset(outputWrites
, 0, sizeof(outputWrites
));
4639 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4640 unsigned prevWriteMask
= 0;
4642 /* Give up if we encounter relative addressing or flow control. */
4643 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4644 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4645 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4646 inst
->op
== TGSI_OPCODE_CONT
||
4647 inst
->op
== TGSI_OPCODE_END
||
4648 inst
->op
== TGSI_OPCODE_RET
) {
4652 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4653 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4654 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4655 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4656 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4657 if (inst
->dst
[0].index
>= tempWritesSize
) {
4658 const int inc
= 4096;
4660 tempWrites
= (unsigned*)
4662 (tempWritesSize
+ inc
) * sizeof(unsigned));
4666 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4667 tempWritesSize
+= inc
;
4670 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4671 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4675 /* For a CMP to be considered a conditional write, the destination
4676 * register and source register two must be the same. */
4677 if (inst
->op
== TGSI_OPCODE_CMP
4678 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4679 && inst
->src
[2].file
== inst
->dst
[0].file
4680 && inst
->src
[2].index
== inst
->dst
[0].index
4681 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4683 inst
->op
= TGSI_OPCODE_MOV
;
4684 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4685 inst
->src
[0] = inst
->src
[1];
4692 /* Replaces all references to a temporary register index with another index. */
4694 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4696 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4699 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4700 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4701 for (k
= 0; k
< num_renames
; k
++)
4702 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4703 inst
->src
[j
].index
= renames
[k
].new_reg
;
4706 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4707 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4708 for (k
= 0; k
< num_renames
; k
++)
4709 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4710 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4713 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4714 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4715 for (k
= 0; k
< num_renames
; k
++)
4716 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4717 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4723 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4725 int depth
= 0; /* loop depth */
4726 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4729 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4730 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4731 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4732 if (first_reads
[inst
->src
[j
].index
] == -1)
4733 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4736 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4737 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4738 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4739 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4742 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4745 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4755 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4757 int depth
= 0; /* loop depth */
4758 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4761 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4762 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4763 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4764 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4766 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4767 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4768 if (first_writes
[inst
->dst
[j
].index
] == -1)
4769 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4770 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4773 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4774 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4775 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4777 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4780 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4783 for (k
= 0; k
< this->next_temp
; k
++) {
4784 if (last_reads
[k
] == -2) {
4796 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4798 int depth
= 0; /* loop depth */
4802 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4803 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4804 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4805 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4808 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4810 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4812 for (k
= 0; k
< this->next_temp
; k
++) {
4813 if (last_writes
[k
] == -2) {
4824 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4825 * channels for copy propagation and updates following instructions to
4826 * use the original versions.
4828 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4829 * will occur. As an example, a TXP production before this pass:
4831 * 0: MOV TEMP[1], INPUT[4].xyyy;
4832 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4833 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4837 * 0: MOV TEMP[1], INPUT[4].xyyy;
4838 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4839 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4841 * which allows for dead code elimination on TEMP[1]'s writes.
4844 glsl_to_tgsi_visitor::copy_propagate(void)
4846 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4847 glsl_to_tgsi_instruction
*,
4848 this->next_temp
* 4);
4849 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4852 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4853 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4854 || inst
->dst
[0].index
< this->next_temp
);
4856 /* First, do any copy propagation possible into the src regs. */
4857 for (int r
= 0; r
< 3; r
++) {
4858 glsl_to_tgsi_instruction
*first
= NULL
;
4860 int acp_base
= inst
->src
[r
].index
* 4;
4862 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4863 inst
->src
[r
].reladdr
||
4864 inst
->src
[r
].reladdr2
)
4867 /* See if we can find entries in the ACP consisting of MOVs
4868 * from the same src register for all the swizzled channels
4869 * of this src register reference.
4871 for (int i
= 0; i
< 4; i
++) {
4872 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4873 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4880 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4885 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4886 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4887 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4888 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4896 /* We've now validated that we can copy-propagate to
4897 * replace this src register reference. Do it.
4899 inst
->src
[r
].file
= first
->src
[0].file
;
4900 inst
->src
[r
].index
= first
->src
[0].index
;
4901 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4902 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4903 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4904 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4907 for (int i
= 0; i
< 4; i
++) {
4908 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4909 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4910 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4912 inst
->src
[r
].swizzle
= swizzle
;
4917 case TGSI_OPCODE_BGNLOOP
:
4918 case TGSI_OPCODE_ENDLOOP
:
4919 /* End of a basic block, clear the ACP entirely. */
4920 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4923 case TGSI_OPCODE_IF
:
4924 case TGSI_OPCODE_UIF
:
4928 case TGSI_OPCODE_ENDIF
:
4929 case TGSI_OPCODE_ELSE
:
4930 /* Clear all channels written inside the block from the ACP, but
4931 * leaving those that were not touched.
4933 for (int r
= 0; r
< this->next_temp
; r
++) {
4934 for (int c
= 0; c
< 4; c
++) {
4935 if (!acp
[4 * r
+ c
])
4938 if (acp_level
[4 * r
+ c
] >= level
)
4939 acp
[4 * r
+ c
] = NULL
;
4942 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4947 /* Continuing the block, clear any written channels from
4950 for (int d
= 0; d
< 2; d
++) {
4951 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4952 /* Any temporary might be written, so no copy propagation
4953 * across this instruction.
4955 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4956 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4957 inst
->dst
[d
].reladdr
) {
4958 /* Any output might be written, so no copy propagation
4959 * from outputs across this instruction.
4961 for (int r
= 0; r
< this->next_temp
; r
++) {
4962 for (int c
= 0; c
< 4; c
++) {
4963 if (!acp
[4 * r
+ c
])
4966 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4967 acp
[4 * r
+ c
] = NULL
;
4970 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4971 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4972 /* Clear where it's used as dst. */
4973 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4974 for (int c
= 0; c
< 4; c
++) {
4975 if (inst
->dst
[d
].writemask
& (1 << c
))
4976 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4980 /* Clear where it's used as src. */
4981 for (int r
= 0; r
< this->next_temp
; r
++) {
4982 for (int c
= 0; c
< 4; c
++) {
4983 if (!acp
[4 * r
+ c
])
4986 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4988 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4989 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4990 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4991 acp
[4 * r
+ c
] = NULL
;
5000 /* If this is a copy, add it to the ACP. */
5001 if (inst
->op
== TGSI_OPCODE_MOV
&&
5002 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5003 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5004 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5005 !inst
->dst
[0].reladdr
&&
5006 !inst
->dst
[0].reladdr2
&&
5008 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5009 !inst
->src
[0].reladdr
&&
5010 !inst
->src
[0].reladdr2
&&
5011 !inst
->src
[0].negate
&&
5012 !inst
->src
[0].abs
) {
5013 for (int i
= 0; i
< 4; i
++) {
5014 if (inst
->dst
[0].writemask
& (1 << i
)) {
5015 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5016 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5022 ralloc_free(acp_level
);
5027 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5030 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5031 * will occur. As an example, a TXP production after copy propagation but
5034 * 0: MOV TEMP[1], INPUT[4].xyyy;
5035 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5036 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5038 * and after this pass:
5040 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5043 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5045 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5046 glsl_to_tgsi_instruction
*,
5047 this->next_temp
* 4);
5048 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5052 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5053 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5054 || inst
->dst
[0].index
< this->next_temp
);
5057 case TGSI_OPCODE_BGNLOOP
:
5058 case TGSI_OPCODE_ENDLOOP
:
5059 case TGSI_OPCODE_CONT
:
5060 case TGSI_OPCODE_BRK
:
5061 /* End of a basic block, clear the write array entirely.
5063 * This keeps us from killing dead code when the writes are
5064 * on either side of a loop, even when the register isn't touched
5065 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5066 * dead code of this type, so it shouldn't make a difference as long as
5067 * the dead code elimination pass in the GLSL compiler does its job.
5069 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5072 case TGSI_OPCODE_ENDIF
:
5073 case TGSI_OPCODE_ELSE
:
5074 /* Promote the recorded level of all channels written inside the
5075 * preceding if or else block to the level above the if/else block.
5077 for (int r
= 0; r
< this->next_temp
; r
++) {
5078 for (int c
= 0; c
< 4; c
++) {
5079 if (!writes
[4 * r
+ c
])
5082 if (write_level
[4 * r
+ c
] == level
)
5083 write_level
[4 * r
+ c
] = level
-1;
5086 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5090 case TGSI_OPCODE_IF
:
5091 case TGSI_OPCODE_UIF
:
5093 /* fallthrough to default case to mark the condition as read */
5095 /* Continuing the block, clear any channels from the write array that
5096 * are read by this instruction.
5098 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5099 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5100 /* Any temporary might be read, so no dead code elimination
5101 * across this instruction.
5103 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5104 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5105 /* Clear where it's used as src. */
5106 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5107 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5108 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5109 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5111 for (int c
= 0; c
< 4; c
++) {
5112 if (src_chans
& (1 << c
))
5113 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5117 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5118 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5119 /* Any temporary might be read, so no dead code elimination
5120 * across this instruction.
5122 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5123 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5124 /* Clear where it's used as src. */
5125 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5126 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5127 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5128 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5130 for (int c
= 0; c
< 4; c
++) {
5131 if (src_chans
& (1 << c
))
5132 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5139 /* If this instruction writes to a temporary, add it to the write array.
5140 * If there is already an instruction in the write array for one or more
5141 * of the channels, flag that channel write as dead.
5143 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5144 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5145 !inst
->dst
[i
].reladdr
) {
5146 for (int c
= 0; c
< 4; c
++) {
5147 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5148 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5149 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5152 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5154 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5155 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5162 /* Anything still in the write array at this point is dead code. */
5163 for (int r
= 0; r
< this->next_temp
; r
++) {
5164 for (int c
= 0; c
< 4; c
++) {
5165 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5167 inst
->dead_mask
|= (1 << c
);
5171 /* Now actually remove the instructions that are completely dead and update
5172 * the writemask of other instructions with dead channels.
5174 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5175 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5177 /* No amount of dead masks should remove memory stores */
5178 if (inst
->info
->is_store
)
5181 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5186 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5187 if (inst
->dead_mask
== WRITEMASK_XY
||
5188 inst
->dead_mask
== WRITEMASK_ZW
)
5189 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5191 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5195 ralloc_free(write_level
);
5196 ralloc_free(writes
);
5201 /* merge DFRACEXP instructions into one. */
5203 glsl_to_tgsi_visitor::merge_two_dsts(void)
5205 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5206 glsl_to_tgsi_instruction
*inst2
;
5208 if (num_inst_dst_regs(inst
) != 2)
5211 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5212 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5215 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5218 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5219 inst
->src
[0].index
== inst2
->src
[0].index
&&
5220 inst
->src
[0].type
== inst2
->src
[0].type
&&
5221 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5223 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5229 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5231 inst
->dst
[0] = inst2
->dst
[0];
5232 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5233 inst
->dst
[1] = inst2
->dst
[1];
5244 /* Merges temporary registers together where possible to reduce the number of
5245 * registers needed to run a program.
5247 * Produces optimal code only after copy propagation and dead code elimination
5250 glsl_to_tgsi_visitor::merge_registers(void)
5252 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5253 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5254 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5256 int num_renames
= 0;
5258 /* Read the indices of the last read and first write to each temp register
5259 * into an array so that we don't have to traverse the instruction list as
5261 for (i
= 0; i
< this->next_temp
; i
++) {
5263 first_writes
[i
] = -1;
5265 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5267 /* Start looking for registers with non-overlapping usages that can be
5268 * merged together. */
5269 for (i
= 0; i
< this->next_temp
; i
++) {
5270 /* Don't touch unused registers. */
5271 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5273 for (j
= 0; j
< this->next_temp
; j
++) {
5274 /* Don't touch unused registers. */
5275 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5277 /* We can merge the two registers if the first write to j is after or
5278 * in the same instruction as the last read from i. Note that the
5279 * register at index i will always be used earlier or at the same time
5280 * as the register at index j. */
5281 if (first_writes
[i
] <= first_writes
[j
] &&
5282 last_reads
[i
] <= first_writes
[j
]) {
5283 renames
[num_renames
].old_reg
= j
;
5284 renames
[num_renames
].new_reg
= i
;
5287 /* Update the first_writes and last_reads arrays with the new
5288 * values for the merged register index, and mark the newly unused
5289 * register index as such. */
5290 assert(last_reads
[j
] >= last_reads
[i
]);
5291 last_reads
[i
] = last_reads
[j
];
5292 first_writes
[j
] = -1;
5298 rename_temp_registers(num_renames
, renames
);
5299 ralloc_free(renames
);
5300 ralloc_free(last_reads
);
5301 ralloc_free(first_writes
);
5304 /* Reassign indices to temporary registers by reusing unused indices created
5305 * by optimization passes. */
5307 glsl_to_tgsi_visitor::renumber_registers(void)
5311 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5312 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5313 int num_renames
= 0;
5314 for (i
= 0; i
< this->next_temp
; i
++) {
5315 first_reads
[i
] = -1;
5317 get_first_temp_read(first_reads
);
5319 for (i
= 0; i
< this->next_temp
; i
++) {
5320 if (first_reads
[i
] < 0) continue;
5321 if (i
!= new_index
) {
5322 renames
[num_renames
].old_reg
= i
;
5323 renames
[num_renames
].new_reg
= new_index
;
5329 rename_temp_registers(num_renames
, renames
);
5330 this->next_temp
= new_index
;
5331 ralloc_free(renames
);
5332 ralloc_free(first_reads
);
5335 /* ------------------------- TGSI conversion stuff -------------------------- */
5338 * Intermediate state used during shader translation.
5340 struct st_translate
{
5341 struct ureg_program
*ureg
;
5343 unsigned temps_size
;
5344 struct ureg_dst
*temps
;
5346 struct ureg_dst
*arrays
;
5347 unsigned num_temp_arrays
;
5348 struct ureg_src
*constants
;
5350 struct ureg_src
*immediates
;
5352 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5353 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5354 struct ureg_dst address
[3];
5355 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5356 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5357 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5358 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5359 struct ureg_src shared_memory
;
5360 unsigned *array_sizes
;
5361 struct inout_decl
*input_decls
;
5362 unsigned num_input_decls
;
5363 struct inout_decl
*output_decls
;
5364 unsigned num_output_decls
;
5366 const GLuint
*inputMapping
;
5367 const GLuint
*outputMapping
;
5369 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5372 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5374 _mesa_sysval_to_semantic(unsigned sysval
)
5378 case SYSTEM_VALUE_VERTEX_ID
:
5379 return TGSI_SEMANTIC_VERTEXID
;
5380 case SYSTEM_VALUE_INSTANCE_ID
:
5381 return TGSI_SEMANTIC_INSTANCEID
;
5382 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5383 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5384 case SYSTEM_VALUE_BASE_VERTEX
:
5385 return TGSI_SEMANTIC_BASEVERTEX
;
5386 case SYSTEM_VALUE_BASE_INSTANCE
:
5387 return TGSI_SEMANTIC_BASEINSTANCE
;
5388 case SYSTEM_VALUE_DRAW_ID
:
5389 return TGSI_SEMANTIC_DRAWID
;
5391 /* Geometry shader */
5392 case SYSTEM_VALUE_INVOCATION_ID
:
5393 return TGSI_SEMANTIC_INVOCATIONID
;
5395 /* Fragment shader */
5396 case SYSTEM_VALUE_FRAG_COORD
:
5397 return TGSI_SEMANTIC_POSITION
;
5398 case SYSTEM_VALUE_FRONT_FACE
:
5399 return TGSI_SEMANTIC_FACE
;
5400 case SYSTEM_VALUE_SAMPLE_ID
:
5401 return TGSI_SEMANTIC_SAMPLEID
;
5402 case SYSTEM_VALUE_SAMPLE_POS
:
5403 return TGSI_SEMANTIC_SAMPLEPOS
;
5404 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5405 return TGSI_SEMANTIC_SAMPLEMASK
;
5406 case SYSTEM_VALUE_HELPER_INVOCATION
:
5407 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5409 /* Tessellation shader */
5410 case SYSTEM_VALUE_TESS_COORD
:
5411 return TGSI_SEMANTIC_TESSCOORD
;
5412 case SYSTEM_VALUE_VERTICES_IN
:
5413 return TGSI_SEMANTIC_VERTICESIN
;
5414 case SYSTEM_VALUE_PRIMITIVE_ID
:
5415 return TGSI_SEMANTIC_PRIMID
;
5416 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5417 return TGSI_SEMANTIC_TESSOUTER
;
5418 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5419 return TGSI_SEMANTIC_TESSINNER
;
5421 /* Compute shader */
5422 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5423 return TGSI_SEMANTIC_THREAD_ID
;
5424 case SYSTEM_VALUE_WORK_GROUP_ID
:
5425 return TGSI_SEMANTIC_BLOCK_ID
;
5426 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5427 return TGSI_SEMANTIC_GRID_SIZE
;
5428 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5429 return TGSI_SEMANTIC_BLOCK_SIZE
;
5432 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5433 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5434 case SYSTEM_VALUE_VERTEX_CNT
:
5436 assert(!"Unexpected SYSTEM_VALUE_ enum");
5437 return TGSI_SEMANTIC_COUNT
;
5442 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5444 static struct ureg_src
5445 emit_immediate(struct st_translate
*t
,
5446 gl_constant_value values
[4],
5449 struct ureg_program
*ureg
= t
->ureg
;
5454 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5456 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5458 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5459 case GL_UNSIGNED_INT64_ARB
:
5460 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5462 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5463 case GL_UNSIGNED_INT
:
5465 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5467 assert(!"should not get here - type must be float, int, uint, or bool");
5468 return ureg_src_undef();
5473 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5475 static struct ureg_dst
5476 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5482 case PROGRAM_UNDEFINED
:
5483 return ureg_dst_undef();
5485 case PROGRAM_TEMPORARY
:
5486 /* Allocate space for temporaries on demand. */
5487 if (index
>= t
->temps_size
) {
5488 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5490 t
->temps
= (struct ureg_dst
*)
5492 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5494 return ureg_dst_undef();
5496 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5497 t
->temps_size
+= inc
;
5500 if (ureg_dst_is_undef(t
->temps
[index
]))
5501 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5503 return t
->temps
[index
];
5506 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5507 array
= array_id
- 1;
5509 if (ureg_dst_is_undef(t
->arrays
[array
]))
5510 t
->arrays
[array
] = ureg_DECL_array_temporary(
5511 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5513 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5515 case PROGRAM_OUTPUT
:
5517 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5518 assert(index
< 2 * FRAG_RESULT_MAX
);
5519 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5520 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5521 assert(index
< VARYING_SLOT_TESS_MAX
);
5523 assert(index
< VARYING_SLOT_MAX
);
5525 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5526 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5527 return t
->outputs
[t
->outputMapping
[index
]];
5530 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5531 unsigned mesa_index
= decl
->mesa_index
;
5532 int slot
= t
->outputMapping
[mesa_index
];
5534 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5536 struct ureg_dst dst
= t
->outputs
[slot
];
5537 dst
.ArrayID
= array_id
;
5538 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5541 case PROGRAM_ADDRESS
:
5542 return t
->address
[index
];
5545 assert(!"unknown dst register file");
5546 return ureg_dst_undef();
5551 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5553 static struct ureg_src
5554 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5556 int index
= reg
->index
;
5557 int double_reg2
= reg
->double_reg2
? 1 : 0;
5560 case PROGRAM_UNDEFINED
:
5561 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5563 case PROGRAM_TEMPORARY
:
5565 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5567 case PROGRAM_OUTPUT
: {
5568 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5569 assert(dst
.WriteMask
!= 0);
5570 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5571 return ureg_swizzle(ureg_src(dst
),
5575 MIN2(shift
+ 3, 3));
5578 case PROGRAM_UNIFORM
:
5579 assert(reg
->index
>= 0);
5580 return reg
->index
< t
->num_constants
?
5581 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5582 case PROGRAM_STATE_VAR
:
5583 case PROGRAM_CONSTANT
: /* ie, immediate */
5584 if (reg
->has_index2
)
5585 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5587 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5588 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5590 case PROGRAM_IMMEDIATE
:
5591 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5592 return t
->immediates
[reg
->index
];
5595 /* GLSL inputs are 64-bit containers, so we have to
5596 * map back to the original index and add the offset after
5598 index
-= double_reg2
;
5599 if (!reg
->array_id
) {
5600 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5601 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5602 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5605 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5606 unsigned mesa_index
= decl
->mesa_index
;
5607 int slot
= t
->inputMapping
[mesa_index
];
5609 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5611 struct ureg_src src
= t
->inputs
[slot
];
5612 src
.ArrayID
= reg
->array_id
;
5613 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5616 case PROGRAM_ADDRESS
:
5617 return ureg_src(t
->address
[reg
->index
]);
5619 case PROGRAM_SYSTEM_VALUE
:
5620 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5621 return t
->systemValues
[reg
->index
];
5624 assert(!"unknown src register file");
5625 return ureg_src_undef();
5630 * Create a TGSI ureg_dst register from an st_dst_reg.
5632 static struct ureg_dst
5633 translate_dst(struct st_translate
*t
,
5634 const st_dst_reg
*dst_reg
,
5637 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5640 if (dst
.File
== TGSI_FILE_NULL
)
5643 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5646 dst
= ureg_saturate(dst
);
5648 if (dst_reg
->reladdr
!= NULL
) {
5649 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5650 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5653 if (dst_reg
->has_index2
) {
5654 if (dst_reg
->reladdr2
)
5655 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5658 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5665 * Create a TGSI ureg_src register from an st_src_reg.
5667 static struct ureg_src
5668 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5670 struct ureg_src src
= src_register(t
, src_reg
);
5672 if (src_reg
->has_index2
) {
5673 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5674 * and UBO constant buffers (buffer, position).
5676 if (src_reg
->reladdr2
)
5677 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5680 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5683 src
= ureg_swizzle(src
,
5684 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5685 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5686 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5687 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5690 src
= ureg_abs(src
);
5692 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5693 src
= ureg_negate(src
);
5695 if (src_reg
->reladdr
!= NULL
) {
5696 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5697 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5703 static struct tgsi_texture_offset
5704 translate_tex_offset(struct st_translate
*t
,
5705 const st_src_reg
*in_offset
)
5707 struct tgsi_texture_offset offset
;
5708 struct ureg_src src
= translate_src(t
, in_offset
);
5710 offset
.File
= src
.File
;
5711 offset
.Index
= src
.Index
;
5712 offset
.SwizzleX
= src
.SwizzleX
;
5713 offset
.SwizzleY
= src
.SwizzleY
;
5714 offset
.SwizzleZ
= src
.SwizzleZ
;
5717 assert(!src
.Indirect
);
5718 assert(!src
.DimIndirect
);
5719 assert(!src
.Dimension
);
5720 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5721 assert(!src
.Negate
);
5727 compile_tgsi_instruction(struct st_translate
*t
,
5728 const glsl_to_tgsi_instruction
*inst
)
5730 struct ureg_program
*ureg
= t
->ureg
;
5732 struct ureg_dst dst
[2];
5733 struct ureg_src src
[4];
5734 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5738 unsigned tex_target
= 0;
5740 num_dst
= num_inst_dst_regs(inst
);
5741 num_src
= num_inst_src_regs(inst
);
5743 for (i
= 0; i
< num_dst
; i
++)
5744 dst
[i
] = translate_dst(t
,
5748 for (i
= 0; i
< num_src
; i
++)
5749 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5752 case TGSI_OPCODE_BGNLOOP
:
5753 case TGSI_OPCODE_ELSE
:
5754 case TGSI_OPCODE_ENDLOOP
:
5755 case TGSI_OPCODE_IF
:
5756 case TGSI_OPCODE_UIF
:
5757 assert(num_dst
== 0);
5758 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5761 case TGSI_OPCODE_TEX
:
5762 case TGSI_OPCODE_TEX_LZ
:
5763 case TGSI_OPCODE_TXB
:
5764 case TGSI_OPCODE_TXD
:
5765 case TGSI_OPCODE_TXL
:
5766 case TGSI_OPCODE_TXP
:
5767 case TGSI_OPCODE_TXQ
:
5768 case TGSI_OPCODE_TXQS
:
5769 case TGSI_OPCODE_TXF
:
5770 case TGSI_OPCODE_TXF_LZ
:
5771 case TGSI_OPCODE_TEX2
:
5772 case TGSI_OPCODE_TXB2
:
5773 case TGSI_OPCODE_TXL2
:
5774 case TGSI_OPCODE_TG4
:
5775 case TGSI_OPCODE_LODQ
:
5776 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5777 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5778 if (inst
->resource
.reladdr
)
5780 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5782 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5783 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5785 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5791 texoffsets
, inst
->tex_offset_num_offset
,
5795 case TGSI_OPCODE_RESQ
:
5796 case TGSI_OPCODE_LOAD
:
5797 case TGSI_OPCODE_ATOMUADD
:
5798 case TGSI_OPCODE_ATOMXCHG
:
5799 case TGSI_OPCODE_ATOMCAS
:
5800 case TGSI_OPCODE_ATOMAND
:
5801 case TGSI_OPCODE_ATOMOR
:
5802 case TGSI_OPCODE_ATOMXOR
:
5803 case TGSI_OPCODE_ATOMUMIN
:
5804 case TGSI_OPCODE_ATOMUMAX
:
5805 case TGSI_OPCODE_ATOMIMIN
:
5806 case TGSI_OPCODE_ATOMIMAX
:
5807 for (i
= num_src
- 1; i
>= 0; i
--)
5808 src
[i
+ 1] = src
[i
];
5810 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5811 src
[0] = t
->shared_memory
;
5812 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5813 src
[0] = t
->buffers
[inst
->resource
.index
];
5815 src
[0] = t
->images
[inst
->resource
.index
];
5816 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5818 if (inst
->resource
.reladdr
)
5819 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5820 assert(src
[0].File
!= TGSI_FILE_NULL
);
5821 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5822 inst
->buffer_access
,
5823 tex_target
, inst
->image_format
);
5826 case TGSI_OPCODE_STORE
:
5827 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5828 dst
[0] = ureg_dst(t
->shared_memory
);
5829 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5830 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5832 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5833 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5835 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5836 if (inst
->resource
.reladdr
)
5837 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5838 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5839 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5840 inst
->buffer_access
,
5841 tex_target
, inst
->image_format
);
5844 case TGSI_OPCODE_SCS
:
5845 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5846 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5859 * Emit the TGSI instructions for inverting and adjusting WPOS.
5860 * This code is unavoidable because it also depends on whether
5861 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5864 emit_wpos_adjustment(struct gl_context
*ctx
,
5865 struct st_translate
*t
,
5866 int wpos_transform_const
,
5868 GLfloat adjX
, GLfloat adjY
[2])
5870 struct ureg_program
*ureg
= t
->ureg
;
5872 assert(wpos_transform_const
>= 0);
5874 /* Fragment program uses fragment position input.
5875 * Need to replace instances of INPUT[WPOS] with temp T
5876 * where T = INPUT[WPOS] is inverted by Y.
5878 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5879 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5880 struct ureg_src
*wpos
=
5881 ctx
->Const
.GLSLFragCoordIsSysVal
?
5882 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5883 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5884 struct ureg_src wpos_input
= *wpos
;
5886 /* First, apply the coordinate shift: */
5887 if (adjX
|| adjY
[0] || adjY
[1]) {
5888 if (adjY
[0] != adjY
[1]) {
5889 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5890 * depending on whether inversion is actually going to be applied
5891 * or not, which is determined by testing against the inversion
5892 * state variable used below, which will be either +1 or -1.
5894 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5896 ureg_CMP(ureg
, adj_temp
,
5897 ureg_scalar(wpostrans
, invert
? 2 : 0),
5898 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5899 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5900 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5902 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5903 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5905 wpos_input
= ureg_src(wpos_temp
);
5907 /* MOV wpos_temp, input[wpos]
5909 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5912 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5913 * inversion/identity, or the other way around if we're drawing to an FBO.
5916 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5919 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5921 ureg_scalar(wpostrans
, 0),
5922 ureg_scalar(wpostrans
, 1));
5924 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5927 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5929 ureg_scalar(wpostrans
, 2),
5930 ureg_scalar(wpostrans
, 3));
5933 /* Use wpos_temp as position input from here on:
5935 *wpos
= ureg_src(wpos_temp
);
5940 * Emit fragment position/ooordinate code.
5943 emit_wpos(struct st_context
*st
,
5944 struct st_translate
*t
,
5945 const struct gl_program
*program
,
5946 struct ureg_program
*ureg
,
5947 int wpos_transform_const
)
5949 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5950 GLfloat adjX
= 0.0f
;
5951 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5952 boolean invert
= FALSE
;
5954 /* Query the pixel center conventions supported by the pipe driver and set
5955 * adjX, adjY to help out if it cannot handle the requested one internally.
5957 * The bias of the y-coordinate depends on whether y-inversion takes place
5958 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5959 * drawing to an FBO (causes additional inversion), and whether the pipe
5960 * driver origin and the requested origin differ (the latter condition is
5961 * stored in the 'invert' variable).
5963 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5965 * center shift only:
5970 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5971 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5972 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5973 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5975 * inversion and center shift:
5976 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5977 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5978 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5979 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5981 if (program
->OriginUpperLeft
) {
5982 /* Fragment shader wants origin in upper-left */
5983 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5984 /* the driver supports upper-left origin */
5986 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5987 /* the driver supports lower-left origin, need to invert Y */
5988 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5989 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5996 /* Fragment shader wants origin in lower-left */
5997 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5998 /* the driver supports lower-left origin */
5999 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6000 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6001 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6002 /* the driver supports upper-left origin, need to invert Y */
6008 if (program
->PixelCenterInteger
) {
6009 /* Fragment shader wants pixel center integer */
6010 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6011 /* the driver supports pixel center integer */
6013 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6014 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6016 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6017 /* the driver supports pixel center half integer, need to bias X,Y */
6026 /* Fragment shader wants pixel center half integer */
6027 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6028 /* the driver supports pixel center half integer */
6030 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6031 /* the driver supports pixel center integer, need to bias X,Y */
6032 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6033 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6034 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6040 /* we invert after adjustment so that we avoid the MOV to temporary,
6041 * and reuse the adjustment ADD instead */
6042 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6046 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6047 * TGSI uses +1 for front, -1 for back.
6048 * This function converts the TGSI value to the GL value. Simply clamping/
6049 * saturating the value to [0,1] does the job.
6052 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6054 struct ureg_program
*ureg
= t
->ureg
;
6055 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6056 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6058 if (ctx
->Const
.NativeIntegers
) {
6059 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6062 /* MOV_SAT face_temp, input[face] */
6063 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6066 /* Use face_temp as face input from here on: */
6067 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6071 emit_compute_block_size(const struct gl_program
*prog
,
6072 struct ureg_program
*ureg
) {
6073 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6074 prog
->info
.cs
.local_size
[0]);
6075 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6076 prog
->info
.cs
.local_size
[1]);
6077 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6078 prog
->info
.cs
.local_size
[2]);
6081 struct sort_inout_decls
{
6082 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6083 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6086 const GLuint
*mapping
;
6089 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6091 * This is for the benefit of older drivers which are broken when the
6092 * declarations aren't sorted in this way.
6095 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6097 const GLuint mapping
[])
6099 sort_inout_decls sorter
;
6100 sorter
.mapping
= mapping
;
6101 std::sort(decls
, decls
+ count
, sorter
);
6105 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6107 switch (glsl_qual
) {
6108 case INTERP_MODE_NONE
:
6109 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6110 return TGSI_INTERPOLATE_COLOR
;
6111 return TGSI_INTERPOLATE_PERSPECTIVE
;
6112 case INTERP_MODE_SMOOTH
:
6113 return TGSI_INTERPOLATE_PERSPECTIVE
;
6114 case INTERP_MODE_FLAT
:
6115 return TGSI_INTERPOLATE_CONSTANT
;
6116 case INTERP_MODE_NOPERSPECTIVE
:
6117 return TGSI_INTERPOLATE_LINEAR
;
6119 assert(0 && "unexpected interp mode in st_translate_interp()");
6120 return TGSI_INTERPOLATE_PERSPECTIVE
;
6125 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6126 * \param program the program to translate
6127 * \param numInputs number of input registers used
6128 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6130 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6131 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6133 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6134 * \param numOutputs number of output registers used
6135 * \param outputMapping maps Mesa fragment program outputs to TGSI
6137 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6138 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6141 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6143 extern "C" enum pipe_error
6144 st_translate_program(
6145 struct gl_context
*ctx
,
6147 struct ureg_program
*ureg
,
6148 glsl_to_tgsi_visitor
*program
,
6149 const struct gl_program
*proginfo
,
6151 const GLuint inputMapping
[],
6152 const GLuint inputSlotToAttr
[],
6153 const ubyte inputSemanticName
[],
6154 const ubyte inputSemanticIndex
[],
6155 const GLuint interpMode
[],
6157 const GLuint outputMapping
[],
6158 const GLuint outputSlotToAttr
[],
6159 const ubyte outputSemanticName
[],
6160 const ubyte outputSemanticIndex
[])
6162 struct st_translate
*t
;
6164 struct gl_program_constants
*frag_const
=
6165 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6166 enum pipe_error ret
= PIPE_OK
;
6168 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6169 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6171 t
= CALLOC_STRUCT(st_translate
);
6173 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6177 t
->procType
= procType
;
6178 t
->inputMapping
= inputMapping
;
6179 t
->outputMapping
= outputMapping
;
6181 t
->num_temp_arrays
= program
->next_array
;
6182 if (t
->num_temp_arrays
)
6183 t
->arrays
= (struct ureg_dst
*)
6184 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6187 * Declare input attributes.
6190 case PIPE_SHADER_FRAGMENT
:
6191 case PIPE_SHADER_GEOMETRY
:
6192 case PIPE_SHADER_TESS_EVAL
:
6193 case PIPE_SHADER_TESS_CTRL
:
6194 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6196 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6197 struct inout_decl
*decl
= &program
->inputs
[i
];
6198 unsigned slot
= inputMapping
[decl
->mesa_index
];
6199 struct ureg_src src
;
6200 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6202 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6203 if (tgsi_usage_mask
== 1)
6204 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6205 else if (tgsi_usage_mask
== 2)
6206 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6208 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6211 unsigned interp_mode
= 0;
6212 unsigned interp_location
= 0;
6213 if (procType
== PIPE_SHADER_FRAGMENT
) {
6215 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6217 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6219 interp_location
= decl
->interp_loc
;
6222 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6223 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6224 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6225 decl
->array_id
, decl
->size
);
6227 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6228 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6229 /* The ArrayID is set up in dst_register */
6230 t
->inputs
[slot
+ j
] = src
;
6231 t
->inputs
[slot
+ j
].ArrayID
= 0;
6232 t
->inputs
[slot
+ j
].Index
+= j
;
6237 case PIPE_SHADER_VERTEX
:
6238 for (i
= 0; i
< numInputs
; i
++) {
6239 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6242 case PIPE_SHADER_COMPUTE
:
6249 * Declare output attributes.
6252 case PIPE_SHADER_FRAGMENT
:
6253 case PIPE_SHADER_COMPUTE
:
6255 case PIPE_SHADER_GEOMETRY
:
6256 case PIPE_SHADER_TESS_EVAL
:
6257 case PIPE_SHADER_TESS_CTRL
:
6258 case PIPE_SHADER_VERTEX
:
6259 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6261 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6262 struct inout_decl
*decl
= &program
->outputs
[i
];
6263 unsigned slot
= outputMapping
[decl
->mesa_index
];
6264 struct ureg_dst dst
;
6265 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6267 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6268 if (tgsi_usage_mask
== 1)
6269 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6270 else if (tgsi_usage_mask
== 2)
6271 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6273 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6276 dst
= ureg_DECL_output_layout(ureg
,
6277 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6278 decl
->gs_out_streams
,
6279 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6281 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6282 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6283 /* The ArrayID is set up in dst_register */
6284 t
->outputs
[slot
+ j
] = dst
;
6285 t
->outputs
[slot
+ j
].ArrayID
= 0;
6286 t
->outputs
[slot
+ j
].Index
+= j
;
6295 if (procType
== PIPE_SHADER_FRAGMENT
) {
6296 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
)
6297 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6299 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6300 /* Must do this after setting up t->inputs. */
6301 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6302 program
->wpos_transform_const
);
6305 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6306 emit_face_var(ctx
, t
);
6308 for (i
= 0; i
< numOutputs
; i
++) {
6309 switch (outputSemanticName
[i
]) {
6310 case TGSI_SEMANTIC_POSITION
:
6311 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6312 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6313 outputSemanticIndex
[i
]);
6314 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6316 case TGSI_SEMANTIC_STENCIL
:
6317 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6318 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6319 outputSemanticIndex
[i
]);
6320 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6322 case TGSI_SEMANTIC_COLOR
:
6323 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6324 TGSI_SEMANTIC_COLOR
,
6325 outputSemanticIndex
[i
]);
6327 case TGSI_SEMANTIC_SAMPLEMASK
:
6328 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6329 TGSI_SEMANTIC_SAMPLEMASK
,
6330 outputSemanticIndex
[i
]);
6331 /* TODO: If we ever support more than 32 samples, this will have
6332 * to become an array.
6334 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6337 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6338 ret
= PIPE_ERROR_BAD_INPUT
;
6343 else if (procType
== PIPE_SHADER_VERTEX
) {
6344 for (i
= 0; i
< numOutputs
; i
++) {
6345 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6346 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6348 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6349 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6350 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6355 if (procType
== PIPE_SHADER_COMPUTE
) {
6356 emit_compute_block_size(proginfo
, ureg
);
6359 /* Declare address register.
6361 if (program
->num_address_regs
> 0) {
6362 assert(program
->num_address_regs
<= 3);
6363 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6364 t
->address
[i
] = ureg_DECL_address(ureg
);
6367 /* Declare misc input registers
6370 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6372 for (i
= 0; sysInputs
; i
++) {
6373 if (sysInputs
& (1 << i
)) {
6374 unsigned semName
= _mesa_sysval_to_semantic(i
);
6376 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6378 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6379 semName
== TGSI_SEMANTIC_VERTEXID
) {
6380 /* From Gallium perspective, these system values are always
6381 * integer, and require native integer support. However, if
6382 * native integer is supported on the vertex stage but not the
6383 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6384 * assumes these system values are floats. To resolve the
6385 * inconsistency, we insert a U2F.
6387 struct st_context
*st
= st_context(ctx
);
6388 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6389 assert(procType
== PIPE_SHADER_VERTEX
);
6390 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6392 if (!ctx
->Const
.NativeIntegers
) {
6393 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6394 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6395 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6399 if (procType
== PIPE_SHADER_FRAGMENT
&&
6400 semName
== TGSI_SEMANTIC_POSITION
)
6401 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6402 program
->wpos_transform_const
);
6404 sysInputs
&= ~(1 << i
);
6409 t
->array_sizes
= program
->array_sizes
;
6410 t
->input_decls
= program
->inputs
;
6411 t
->num_input_decls
= program
->num_inputs
;
6412 t
->output_decls
= program
->outputs
;
6413 t
->num_output_decls
= program
->num_outputs
;
6415 /* Emit constants and uniforms. TGSI uses a single index space for these,
6416 * so we put all the translated regs in t->constants.
6418 if (proginfo
->Parameters
) {
6419 t
->constants
= (struct ureg_src
*)
6420 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6421 if (t
->constants
== NULL
) {
6422 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6425 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6427 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6428 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6429 case PROGRAM_STATE_VAR
:
6430 case PROGRAM_UNIFORM
:
6431 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6434 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6435 * addressing of the const buffer.
6436 * FIXME: Be smarter and recognize param arrays:
6437 * indirect addressing is only valid within the referenced
6440 case PROGRAM_CONSTANT
:
6441 if (program
->indirect_addr_consts
)
6442 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6444 t
->constants
[i
] = emit_immediate(t
,
6445 proginfo
->Parameters
->ParameterValues
[i
],
6446 proginfo
->Parameters
->Parameters
[i
].DataType
,
6455 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6456 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6457 unsigned num_const_vecs
= (size
+ 15) / 16;
6458 unsigned first
, last
;
6459 assert(num_const_vecs
> 0);
6461 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6462 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6465 /* Emit immediate values.
6467 t
->immediates
= (struct ureg_src
*)
6468 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6469 if (t
->immediates
== NULL
) {
6470 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6473 t
->num_immediates
= program
->num_immediates
;
6476 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6477 assert(i
< program
->num_immediates
);
6478 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6480 assert(i
== program
->num_immediates
);
6482 /* texture samplers */
6483 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6484 if (program
->samplers_used
& (1u << i
)) {
6487 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6489 switch (program
->sampler_types
[i
]) {
6491 type
= TGSI_RETURN_TYPE_SINT
;
6493 case GLSL_TYPE_UINT
:
6494 type
= TGSI_RETURN_TYPE_UINT
;
6496 case GLSL_TYPE_FLOAT
:
6497 type
= TGSI_RETURN_TYPE_FLOAT
;
6500 unreachable("not reached");
6503 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6504 type
, type
, type
, type
);
6508 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6509 if (program
->buffers_used
& (1 << i
)) {
6510 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6514 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6516 if (program
->buffers_used
& (1 << i
)) {
6517 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6521 if (program
->use_shared_memory
)
6522 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6524 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6525 if (program
->images_used
& (1 << i
)) {
6526 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6527 program
->image_targets
[i
],
6528 program
->image_formats
[i
],
6533 /* Emit each instruction in turn:
6535 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6536 compile_tgsi_instruction(t
, inst
);
6538 /* Set the next shader stage hint for VS and TES. */
6540 case PIPE_SHADER_VERTEX
:
6541 case PIPE_SHADER_TESS_EVAL
:
6542 if (program
->shader_program
->SeparateShader
)
6545 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6546 if (program
->shader_program
->_LinkedShaders
[i
]) {
6550 case MESA_SHADER_TESS_CTRL
:
6551 next
= PIPE_SHADER_TESS_CTRL
;
6553 case MESA_SHADER_TESS_EVAL
:
6554 next
= PIPE_SHADER_TESS_EVAL
;
6556 case MESA_SHADER_GEOMETRY
:
6557 next
= PIPE_SHADER_GEOMETRY
;
6559 case MESA_SHADER_FRAGMENT
:
6560 next
= PIPE_SHADER_FRAGMENT
;
6567 ureg_set_next_shader_processor(ureg
, next
);
6579 t
->num_constants
= 0;
6580 free(t
->immediates
);
6581 t
->num_immediates
= 0;
6587 /* ----------------------------- End TGSI code ------------------------------ */
6591 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6592 * generating Mesa IR.
6594 static struct gl_program
*
6595 get_mesa_program_tgsi(struct gl_context
*ctx
,
6596 struct gl_shader_program
*shader_program
,
6597 struct gl_linked_shader
*shader
)
6599 glsl_to_tgsi_visitor
* v
;
6600 struct gl_program
*prog
;
6601 struct gl_shader_compiler_options
*options
=
6602 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6603 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6604 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6606 validate_ir_tree(shader
->ir
);
6608 prog
= shader
->Program
;
6610 prog
->Parameters
= _mesa_new_parameter_list();
6611 v
= new glsl_to_tgsi_visitor();
6614 v
->shader_program
= shader_program
;
6616 v
->options
= options
;
6617 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6618 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6620 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6621 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6622 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6623 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6624 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6625 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6627 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6630 /* Remove reads from output registers. */
6631 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6632 lower_output_reads(shader
->Stage
, shader
->ir
);
6634 /* Emit intermediate IR for main(). */
6635 visit_exec_list(shader
->ir
, v
);
6638 /* Print out some information (for debugging purposes) used by the
6639 * optimization passes. */
6642 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6643 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6644 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6645 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6647 for (i
= 0; i
< v
->next_temp
; i
++) {
6648 first_writes
[i
] = -1;
6649 first_reads
[i
] = -1;
6650 last_writes
[i
] = -1;
6653 v
->get_first_temp_read(first_reads
);
6654 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6655 v
->get_last_temp_write(last_writes
);
6656 for (i
= 0; i
< v
->next_temp
; i
++)
6657 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6661 ralloc_free(first_writes
);
6662 ralloc_free(first_reads
);
6663 ralloc_free(last_writes
);
6664 ralloc_free(last_reads
);
6668 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6671 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6672 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6673 v
->copy_propagate();
6675 while (v
->eliminate_dead_code());
6677 v
->merge_two_dsts();
6678 v
->merge_registers();
6679 v
->renumber_registers();
6681 /* Write the END instruction. */
6682 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6684 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6686 _mesa_log("GLSL IR for linked %s program %d:\n",
6687 _mesa_shader_stage_to_string(shader
->Stage
),
6688 shader_program
->Name
);
6689 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6693 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6694 _mesa_copy_linked_program_data(shader_program
, shader
);
6695 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6696 &prog
->info
.inputs_read
,
6697 prog
->info
.double_inputs_read
,
6698 &prog
->info
.patch_inputs_read
);
6699 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6700 &prog
->info
.outputs_written
, 0ULL,
6701 &prog
->info
.patch_outputs_written
);
6702 count_resources(v
, prog
);
6704 /* The GLSL IR won't be needed anymore. */
6705 ralloc_free(shader
->ir
);
6708 /* This must be done before the uniform storage is associated. */
6709 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6710 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6711 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6712 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6713 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6716 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6717 wposTransformState
);
6720 /* Avoid reallocation of the program parameter list, because the uniform
6721 * storage is only associated with the original parameter list.
6722 * This should be enough for Bitmap and DrawPixels constants.
6724 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6726 /* This has to be done last. Any operation the can cause
6727 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6728 * program constant) has to happen before creating this linkage.
6730 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
,
6732 if (!shader_program
->data
->LinkStatus
) {
6733 free_glsl_to_tgsi_visitor(v
);
6734 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6738 struct st_vertex_program
*stvp
;
6739 struct st_fragment_program
*stfp
;
6740 struct st_geometry_program
*stgp
;
6741 struct st_tessctrl_program
*sttcp
;
6742 struct st_tesseval_program
*sttep
;
6743 struct st_compute_program
*stcp
;
6745 switch (shader
->Stage
) {
6746 case MESA_SHADER_VERTEX
:
6747 stvp
= (struct st_vertex_program
*)prog
;
6748 stvp
->glsl_to_tgsi
= v
;
6750 case MESA_SHADER_FRAGMENT
:
6751 stfp
= (struct st_fragment_program
*)prog
;
6752 stfp
->glsl_to_tgsi
= v
;
6754 case MESA_SHADER_GEOMETRY
:
6755 stgp
= (struct st_geometry_program
*)prog
;
6756 stgp
->glsl_to_tgsi
= v
;
6758 case MESA_SHADER_TESS_CTRL
:
6759 sttcp
= (struct st_tessctrl_program
*)prog
;
6760 sttcp
->glsl_to_tgsi
= v
;
6762 case MESA_SHADER_TESS_EVAL
:
6763 sttep
= (struct st_tesseval_program
*)prog
;
6764 sttep
->glsl_to_tgsi
= v
;
6766 case MESA_SHADER_COMPUTE
:
6767 stcp
= (struct st_compute_program
*)prog
;
6768 stcp
->glsl_to_tgsi
= v
;
6771 assert(!"should not be reached");
6778 /* See if there are unsupported control flow statements. */
6779 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6781 const struct gl_shader_compiler_options
*options
;
6783 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6789 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6791 /* Other functions are skipped (same as glsl_to_tgsi). */
6792 if (strcmp(ir
->name
, "main") == 0)
6793 return visit_continue
;
6795 return visit_continue_with_parent
;
6798 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6800 if (!ir
->callee
->is_intrinsic()) {
6801 unsupported
= true; /* it's a function call */
6804 return visit_continue
;
6807 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6809 if (options
->EmitNoMainReturn
) {
6813 return visit_continue
;
6820 has_unsupported_control_flow(exec_list
*ir
,
6821 const struct gl_shader_compiler_options
*options
)
6823 ir_control_flow_info_visitor
visitor(options
);
6824 visit_list_elements(&visitor
, ir
);
6825 return visitor
.unsupported
;
6832 * Called via ctx->Driver.LinkShader()
6833 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6834 * with code lowering and other optimizations.
6837 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6839 /* Return early if we are loading the shader from on-disk cache */
6840 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6844 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6845 assert(prog
->data
->LinkStatus
);
6847 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6848 if (prog
->_LinkedShaders
[i
] == NULL
)
6851 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6852 exec_list
*ir
= shader
->ir
;
6853 gl_shader_stage stage
= shader
->Stage
;
6854 const struct gl_shader_compiler_options
*options
=
6855 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6856 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6857 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6858 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6859 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6860 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6861 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6862 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6864 /* If there are forms of indirect addressing that the driver
6865 * cannot handle, perform the lowering pass.
6867 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6868 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6869 lower_variable_index_to_cond_assign(stage
, ir
,
6870 options
->EmitNoIndirectInput
,
6871 options
->EmitNoIndirectOutput
,
6872 options
->EmitNoIndirectTemp
,
6873 options
->EmitNoIndirectUniform
);
6876 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6877 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6879 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6880 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6881 LOWER_UNPACK_SNORM_2x16
|
6882 LOWER_PACK_UNORM_2x16
|
6883 LOWER_UNPACK_UNORM_2x16
|
6884 LOWER_PACK_SNORM_4x8
|
6885 LOWER_UNPACK_SNORM_4x8
|
6886 LOWER_UNPACK_UNORM_4x8
|
6887 LOWER_PACK_UNORM_4x8
;
6889 if (ctx
->Extensions
.ARB_gpu_shader5
)
6890 lower_inst
|= LOWER_PACK_USE_BFI
|
6892 if (!ctx
->st
->has_half_float_packing
)
6893 lower_inst
|= LOWER_PACK_HALF_2x16
|
6894 LOWER_UNPACK_HALF_2x16
;
6896 lower_packing_builtins(ir
, lower_inst
);
6899 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6900 lower_offset_arrays(ir
);
6901 do_mat_op_to_vec(ir
);
6903 if (stage
== MESA_SHADER_FRAGMENT
)
6904 lower_blend_equation_advanced(shader
);
6906 lower_instructions(ir
,
6912 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6915 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6916 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6917 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6918 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6919 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6920 /* Assume that if ARB_gpu_shader5 is not supported
6921 * then all of the extended integer functions need
6922 * lowering. It may be necessary to add some caps
6923 * for individual instructions.
6925 (!ctx
->Extensions
.ARB_gpu_shader5
6926 ? BIT_COUNT_TO_MATH
|
6930 FIND_LSB_TO_FLOAT_CAST
|
6931 FIND_MSB_TO_FLOAT_CAST
|
6935 do_vec_index_to_cond_assign(ir
);
6936 lower_vector_insert(ir
, true);
6937 lower_quadop_vector(ir
, false);
6939 if (options
->MaxIfDepth
== 0) {
6943 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6944 /* Do it once and repeat only if there's unsupported control flow. */
6946 do_common_optimization(ir
, true, true, options
,
6947 ctx
->Const
.NativeIntegers
);
6948 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6949 options
->MaxIfDepth
, if_threshold
);
6950 } while (has_unsupported_control_flow(ir
, options
));
6952 /* Repeat it until it stops making changes. */
6955 progress
= do_common_optimization(ir
, true, true, options
,
6956 ctx
->Const
.NativeIntegers
);
6957 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6958 options
->MaxIfDepth
, if_threshold
);
6962 validate_ir_tree(ir
);
6965 build_program_resource_list(ctx
, prog
);
6967 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6968 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6972 enum pipe_shader_type ptarget
=
6973 st_shader_stage_to_ptarget(shader
->Stage
);
6974 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6975 pscreen
->get_shader_param(pscreen
, ptarget
,
6976 PIPE_SHADER_CAP_PREFERRED_IR
);
6978 struct gl_program
*linked_prog
= NULL
;
6979 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6980 /* TODO only for GLSL VS/FS for now: */
6981 switch (shader
->Stage
) {
6982 case MESA_SHADER_VERTEX
:
6983 case MESA_SHADER_FRAGMENT
:
6984 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6989 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6993 st_set_prog_affected_state_flags(linked_prog
);
6994 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6995 _mesa_shader_stage_to_program(i
),
6997 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7007 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7008 const GLuint outputMapping
[],
7009 struct pipe_stream_output_info
*so
)
7011 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7014 struct gl_transform_feedback_info
*info
=
7015 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7016 st_translate_stream_output_info2(info
, outputMapping
, so
);
7020 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7021 const GLuint outputMapping
[],
7022 struct pipe_stream_output_info
*so
)
7026 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7027 so
->output
[i
].register_index
=
7028 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7029 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7030 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7031 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7032 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7033 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7036 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7037 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7039 so
->num_outputs
= info
->NumOutputs
;