2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
58 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
59 (1 << PROGRAM_CONSTANT) | \
60 (1 << PROGRAM_UNIFORM))
62 #define MAX_GLSL_TEXTURE_OFFSET 4
67 static int swizzle_for_size(int size
);
70 * This struct is a corresponding struct to TGSI ureg_src.
74 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
78 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
79 this->swizzle
= swizzle_for_size(type
->vector_elements
);
81 this->swizzle
= SWIZZLE_XYZW
;
84 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
86 this->reladdr2
= NULL
;
87 this->has_index2
= false;
88 this->double_reg2
= false;
90 this->is_double_vertex_input
= false;
93 st_src_reg(gl_register_file file
, int index
, int type
)
99 this->swizzle
= SWIZZLE_XYZW
;
101 this->reladdr
= NULL
;
102 this->reladdr2
= NULL
;
103 this->has_index2
= false;
104 this->double_reg2
= false;
106 this->is_double_vertex_input
= false;
109 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
114 this->index2D
= index2D
;
115 this->swizzle
= SWIZZLE_XYZW
;
117 this->reladdr
= NULL
;
118 this->reladdr2
= NULL
;
119 this->has_index2
= false;
120 this->double_reg2
= false;
122 this->is_double_vertex_input
= false;
127 this->type
= GLSL_TYPE_ERROR
;
128 this->file
= PROGRAM_UNDEFINED
;
133 this->reladdr
= NULL
;
134 this->reladdr2
= NULL
;
135 this->has_index2
= false;
136 this->double_reg2
= false;
138 this->is_double_vertex_input
= false;
141 explicit st_src_reg(st_dst_reg reg
);
143 gl_register_file file
; /**< PROGRAM_* from Mesa */
144 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
146 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
147 int negate
; /**< NEGATE_XYZW mask from mesa */
148 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
149 /** Register index should be offset by the integer in this reg. */
151 st_src_reg
*reladdr2
;
154 * Is this the second half of a double register pair?
155 * currently used for input mapping only.
159 bool is_double_vertex_input
;
164 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
169 this->writemask
= writemask
;
170 this->reladdr
= NULL
;
171 this->reladdr2
= NULL
;
172 this->has_index2
= false;
177 st_dst_reg(gl_register_file file
, int writemask
, int type
)
182 this->writemask
= writemask
;
183 this->reladdr
= NULL
;
184 this->reladdr2
= NULL
;
185 this->has_index2
= false;
192 this->type
= GLSL_TYPE_ERROR
;
193 this->file
= PROGRAM_UNDEFINED
;
197 this->reladdr
= NULL
;
198 this->reladdr2
= NULL
;
199 this->has_index2
= false;
203 explicit st_dst_reg(st_src_reg reg
);
205 gl_register_file file
; /**< PROGRAM_* from Mesa */
206 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
208 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
209 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
210 /** Register index should be offset by the integer in this reg. */
212 st_src_reg
*reladdr2
;
217 st_src_reg::st_src_reg(st_dst_reg reg
)
219 this->type
= reg
.type
;
220 this->file
= reg
.file
;
221 this->index
= reg
.index
;
222 this->swizzle
= SWIZZLE_XYZW
;
224 this->reladdr
= reg
.reladdr
;
225 this->index2D
= reg
.index2D
;
226 this->reladdr2
= reg
.reladdr2
;
227 this->has_index2
= reg
.has_index2
;
228 this->double_reg2
= false;
229 this->array_id
= reg
.array_id
;
230 this->is_double_vertex_input
= false;
233 st_dst_reg::st_dst_reg(st_src_reg reg
)
235 this->type
= reg
.type
;
236 this->file
= reg
.file
;
237 this->index
= reg
.index
;
238 this->writemask
= WRITEMASK_XYZW
;
239 this->reladdr
= reg
.reladdr
;
240 this->index2D
= reg
.index2D
;
241 this->reladdr2
= reg
.reladdr2
;
242 this->has_index2
= reg
.has_index2
;
243 this->array_id
= reg
.array_id
;
246 class glsl_to_tgsi_instruction
: public exec_node
{
248 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
253 /** Pointer to the ir source this tree came from for debugging */
255 GLboolean cond_update
;
257 st_src_reg sampler
; /**< sampler register */
259 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
260 int tex_target
; /**< One of TEXTURE_*_INDEX */
261 glsl_base_type tex_type
;
262 GLboolean tex_shadow
;
263 unsigned image_format
;
265 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
266 unsigned tex_offset_num_offset
;
267 int dead_mask
; /**< Used in dead code elimination */
269 st_src_reg buffer
; /**< buffer register */
270 unsigned buffer_access
; /**< buffer access type */
272 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
273 const struct tgsi_opcode_info
*info
;
276 class variable_storage
: public exec_node
{
278 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
279 unsigned array_id
= 0)
280 : file(file
), index(index
), var(var
), array_id(array_id
)
285 gl_register_file file
;
287 ir_variable
*var
; /* variable that maps to this, if any */
291 class immediate_storage
: public exec_node
{
293 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
295 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
296 this->size32
= size32
;
300 /* doubles are stored across 2 gl_constant_values */
301 gl_constant_value values
[4];
302 int size32
; /**< Number of 32-bit components (1-4) */
303 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
306 class function_entry
: public exec_node
{
308 ir_function_signature
*sig
;
311 * identifier of this function signature used by the program.
313 * At the point that TGSI instructions for function calls are
314 * generated, we don't know the address of the first instruction of
315 * the function body. So we make the BranchTarget that is called a
316 * small integer and rewrite them during set_branchtargets().
321 * Pointer to first instruction of the function body.
323 * Set during function body emits after main() is processed.
325 glsl_to_tgsi_instruction
*bgn_inst
;
328 * Index of the first instruction of the function body in actual TGSI.
330 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
334 /** Storage for the return value. */
335 st_src_reg return_reg
;
338 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
339 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
349 find_array_type(struct array_decl
*arrays
, unsigned count
, unsigned array_id
)
353 for (i
= 0; i
< count
; i
++) {
354 struct array_decl
*decl
= &arrays
[i
];
356 if (array_id
== decl
->array_id
) {
357 return decl
->array_type
;
360 return GLSL_TYPE_ERROR
;
363 struct rename_reg_pair
{
368 struct glsl_to_tgsi_visitor
: public ir_visitor
{
370 glsl_to_tgsi_visitor();
371 ~glsl_to_tgsi_visitor();
373 function_entry
*current_function
;
375 struct gl_context
*ctx
;
376 struct gl_program
*prog
;
377 struct gl_shader_program
*shader_program
;
378 struct gl_shader
*shader
;
379 struct gl_shader_compiler_options
*options
;
383 unsigned *array_sizes
;
384 unsigned max_num_arrays
;
387 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
388 unsigned num_input_arrays
;
389 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
390 unsigned num_output_arrays
;
392 int num_address_regs
;
393 uint32_t samplers_used
;
394 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
395 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
398 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
399 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
400 bool indirect_addr_consts
;
401 int wpos_transform_const
;
404 bool native_integers
;
407 bool use_shared_memory
;
409 variable_storage
*find_variable_storage(ir_variable
*var
);
411 int add_constant(gl_register_file file
, gl_constant_value values
[8],
412 int size
, int datatype
, GLuint
*swizzle_out
);
414 function_entry
*get_function_signature(ir_function_signature
*sig
);
416 st_src_reg
get_temp(const glsl_type
*type
);
417 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
419 st_src_reg
st_src_reg_for_double(double val
);
420 st_src_reg
st_src_reg_for_float(float val
);
421 st_src_reg
st_src_reg_for_int(int val
);
422 st_src_reg
st_src_reg_for_type(int type
, int val
);
425 * \name Visit methods
427 * As typical for the visitor pattern, there must be one \c visit method for
428 * each concrete subclass of \c ir_instruction. Virtual base classes within
429 * the hierarchy should not have \c visit methods.
432 virtual void visit(ir_variable
*);
433 virtual void visit(ir_loop
*);
434 virtual void visit(ir_loop_jump
*);
435 virtual void visit(ir_function_signature
*);
436 virtual void visit(ir_function
*);
437 virtual void visit(ir_expression
*);
438 virtual void visit(ir_swizzle
*);
439 virtual void visit(ir_dereference_variable
*);
440 virtual void visit(ir_dereference_array
*);
441 virtual void visit(ir_dereference_record
*);
442 virtual void visit(ir_assignment
*);
443 virtual void visit(ir_constant
*);
444 virtual void visit(ir_call
*);
445 virtual void visit(ir_return
*);
446 virtual void visit(ir_discard
*);
447 virtual void visit(ir_texture
*);
448 virtual void visit(ir_if
*);
449 virtual void visit(ir_emit_vertex
*);
450 virtual void visit(ir_end_primitive
*);
451 virtual void visit(ir_barrier
*);
454 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
456 void visit_atomic_counter_intrinsic(ir_call
*);
457 void visit_ssbo_intrinsic(ir_call
*);
458 void visit_membar_intrinsic(ir_call
*);
459 void visit_shared_intrinsic(ir_call
*);
460 void visit_image_intrinsic(ir_call
*);
464 /** List of variable_storage */
467 /** List of immediate_storage */
468 exec_list immediates
;
469 unsigned num_immediates
;
471 /** List of function_entry */
472 exec_list function_signatures
;
473 int next_signature_id
;
475 /** List of glsl_to_tgsi_instruction */
476 exec_list instructions
;
478 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
479 st_dst_reg dst
= undef_dst
,
480 st_src_reg src0
= undef_src
,
481 st_src_reg src1
= undef_src
,
482 st_src_reg src2
= undef_src
,
483 st_src_reg src3
= undef_src
);
485 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
486 st_dst_reg dst
, st_dst_reg dst1
,
487 st_src_reg src0
= undef_src
,
488 st_src_reg src1
= undef_src
,
489 st_src_reg src2
= undef_src
,
490 st_src_reg src3
= undef_src
);
492 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
494 st_src_reg src0
, st_src_reg src1
);
497 * Emit the correct dot-product instruction for the type of arguments
499 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
505 void emit_scalar(ir_instruction
*ir
, unsigned op
,
506 st_dst_reg dst
, st_src_reg src0
);
508 void emit_scalar(ir_instruction
*ir
, unsigned op
,
509 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
511 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
513 void get_deref_offsets(ir_dereference
*ir
,
514 unsigned *array_size
,
517 st_src_reg
*reladdr
);
518 void calc_deref_offsets(ir_dereference
*head
,
519 ir_dereference
*tail
,
520 unsigned *array_elements
,
523 st_src_reg
*indirect
,
526 bool try_emit_mad(ir_expression
*ir
,
528 bool try_emit_mad_for_and_not(ir_expression
*ir
,
531 void emit_swz(ir_expression
*ir
);
533 bool process_move_condition(ir_rvalue
*ir
);
535 void simplify_cmp(void);
537 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
538 void get_first_temp_read(int *first_reads
);
539 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
540 void get_last_temp_write(int *last_writes
);
542 void copy_propagate(void);
543 int eliminate_dead_code(void);
545 void merge_two_dsts(void);
546 void merge_registers(void);
547 void renumber_registers(void);
549 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
550 st_dst_reg
*l
, st_src_reg
*r
,
551 st_src_reg
*cond
, bool cond_swap
);
556 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
557 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
558 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
561 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
564 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
568 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
571 prog
->LinkStatus
= GL_FALSE
;
575 swizzle_for_size(int size
)
577 static const int size_swizzles
[4] = {
578 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
579 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
580 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
581 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
584 assert((size
>= 1) && (size
<= 4));
585 return size_swizzles
[size
- 1];
589 is_resource_instruction(unsigned opcode
)
592 case TGSI_OPCODE_RESQ
:
593 case TGSI_OPCODE_LOAD
:
594 case TGSI_OPCODE_ATOMUADD
:
595 case TGSI_OPCODE_ATOMXCHG
:
596 case TGSI_OPCODE_ATOMCAS
:
597 case TGSI_OPCODE_ATOMAND
:
598 case TGSI_OPCODE_ATOMOR
:
599 case TGSI_OPCODE_ATOMXOR
:
600 case TGSI_OPCODE_ATOMUMIN
:
601 case TGSI_OPCODE_ATOMUMAX
:
602 case TGSI_OPCODE_ATOMIMIN
:
603 case TGSI_OPCODE_ATOMIMAX
:
611 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
613 return op
->info
->num_dst
;
617 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
619 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
620 op
->info
->num_src
- 1 : op
->info
->num_src
;
623 glsl_to_tgsi_instruction
*
624 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
625 st_dst_reg dst
, st_dst_reg dst1
,
626 st_src_reg src0
, st_src_reg src1
,
627 st_src_reg src2
, st_src_reg src3
)
629 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
630 int num_reladdr
= 0, i
, j
;
631 bool dst_is_double
[2];
633 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
635 /* If we have to do relative addressing, we want to load the ARL
636 * reg directly for one of the regs, and preload the other reladdr
637 * sources into temps.
639 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
640 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
641 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
642 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
643 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
644 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
646 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
647 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
648 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
649 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
651 if (dst
.reladdr
|| dst
.reladdr2
) {
653 emit_arl(ir
, address_reg
, *dst
.reladdr
);
655 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
659 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
662 assert(num_reladdr
== 0);
665 inst
->info
= tgsi_get_opcode_info(op
);
674 /* default to float, for paths where this is not initialized
675 * (since 0==UINT which is likely wrong):
677 inst
->tex_type
= GLSL_TYPE_FLOAT
;
679 inst
->function
= NULL
;
681 /* Update indirect addressing status used by TGSI */
682 if (dst
.reladdr
|| dst
.reladdr2
) {
684 case PROGRAM_STATE_VAR
:
685 case PROGRAM_CONSTANT
:
686 case PROGRAM_UNIFORM
:
687 this->indirect_addr_consts
= true;
689 case PROGRAM_IMMEDIATE
:
690 assert(!"immediates should not have indirect addressing");
697 for (i
= 0; i
< 4; i
++) {
698 if(inst
->src
[i
].reladdr
) {
699 switch(inst
->src
[i
].file
) {
700 case PROGRAM_STATE_VAR
:
701 case PROGRAM_CONSTANT
:
702 case PROGRAM_UNIFORM
:
703 this->indirect_addr_consts
= true;
705 case PROGRAM_IMMEDIATE
:
706 assert(!"immediates should not have indirect addressing");
716 * This section contains the double processing.
717 * GLSL just represents doubles as single channel values,
718 * however most HW and TGSI represent doubles as pairs of register channels.
720 * so we have to fixup destination writemask/index and src swizzle/indexes.
721 * dest writemasks need to translate from single channel write mask
722 * to a dual-channel writemask, but also need to modify the index,
723 * if we are touching the Z,W fields in the pre-translated writemask.
725 * src channels have similiar index modifications along with swizzle
726 * changes to we pick the XY, ZW pairs from the correct index.
728 * GLSL [0].x -> TGSI [0].xy
729 * GLSL [0].y -> TGSI [0].zw
730 * GLSL [0].z -> TGSI [1].xy
731 * GLSL [0].w -> TGSI [1].zw
733 for (j
= 0; j
< 2; j
++) {
734 dst_is_double
[j
] = false;
735 if (inst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
)
736 dst_is_double
[j
] = true;
737 else if (inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
738 unsigned type
= find_array_type(this->output_arrays
, this->num_output_arrays
, inst
->dst
[j
].array_id
);
739 if (type
== GLSL_TYPE_DOUBLE
)
740 dst_is_double
[j
] = true;
744 if (dst_is_double
[0] || dst_is_double
[1] ||
745 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
746 glsl_to_tgsi_instruction
*dinst
= NULL
;
747 int initial_src_swz
[4], initial_src_idx
[4];
748 int initial_dst_idx
[2], initial_dst_writemask
[2];
749 /* select the writemask for dst0 or dst1 */
750 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
752 /* copy out the writemask, index and swizzles for all src/dsts. */
753 for (j
= 0; j
< 2; j
++) {
754 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
755 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
758 for (j
= 0; j
< 4; j
++) {
759 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
760 initial_src_idx
[j
] = inst
->src
[j
].index
;
764 * scan all the components in the dst writemask
765 * generate an instruction for each of them if required.
770 int i
= u_bit_scan(&writemask
);
772 /* before emitting the instruction, see if we have to adjust store
774 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
775 addr
.file
== PROGRAM_UNDEFINED
) {
776 /* We have to advance the buffer address by 16 */
777 addr
= get_temp(glsl_type::uint_type
);
778 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
779 inst
->src
[0], st_src_reg_for_int(16));
783 /* first time use previous instruction */
787 /* create a new instructions for subsequent attempts */
788 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
793 this->instructions
.push_tail(dinst
);
795 /* modify the destination if we are splitting */
796 for (j
= 0; j
< 2; j
++) {
797 if (dst_is_double
[j
]) {
798 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
799 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
801 if (dinst
->op
== TGSI_OPCODE_STORE
) {
802 dinst
->src
[0] = addr
;
804 dinst
->dst
[j
].index
++;
808 /* if we aren't writing to a double, just get the bit of the initial writemask
810 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
814 /* modify the src registers */
815 for (j
= 0; j
< 4; j
++) {
816 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
818 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
819 dinst
->src
[j
].index
= initial_src_idx
[j
];
821 dinst
->src
[j
].double_reg2
= true;
822 dinst
->src
[j
].index
++;
826 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
828 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
831 /* some opcodes are special case in what they use as sources
832 - F2D is a float src0, DLDEXP is integer src1 */
833 if (op
== TGSI_OPCODE_F2D
||
834 op
== TGSI_OPCODE_DLDEXP
||
835 (op
== TGSI_OPCODE_UCMP
&& dst_is_double
[0])) {
836 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
843 this->instructions
.push_tail(inst
);
850 glsl_to_tgsi_instruction
*
851 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
853 st_src_reg src0
, st_src_reg src1
,
854 st_src_reg src2
, st_src_reg src3
)
856 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
860 * Determines whether to use an integer, unsigned integer, or float opcode
861 * based on the operands and input opcode, then emits the result.
864 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
866 st_src_reg src0
, st_src_reg src1
)
868 int type
= GLSL_TYPE_FLOAT
;
870 if (op
== TGSI_OPCODE_MOV
)
873 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
874 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
875 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
876 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
878 if (is_resource_instruction(op
))
880 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
881 type
= GLSL_TYPE_DOUBLE
;
882 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
883 type
= GLSL_TYPE_FLOAT
;
884 else if (native_integers
)
885 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
887 #define case5(c, f, i, u, d) \
888 case TGSI_OPCODE_##c: \
889 if (type == GLSL_TYPE_DOUBLE) \
890 op = TGSI_OPCODE_##d; \
891 else if (type == GLSL_TYPE_INT) \
892 op = TGSI_OPCODE_##i; \
893 else if (type == GLSL_TYPE_UINT) \
894 op = TGSI_OPCODE_##u; \
896 op = TGSI_OPCODE_##f; \
899 #define case4(c, f, i, u) \
900 case TGSI_OPCODE_##c: \
901 if (type == GLSL_TYPE_INT) \
902 op = TGSI_OPCODE_##i; \
903 else if (type == GLSL_TYPE_UINT) \
904 op = TGSI_OPCODE_##u; \
906 op = TGSI_OPCODE_##f; \
909 #define case3(f, i, u) case4(f, f, i, u)
910 #define case4d(f, i, u, d) case5(f, f, i, u, d)
911 #define case3fid(f, i, d) case5(f, f, i, i, d)
912 #define case2fi(f, i) case4(f, f, i, i)
913 #define case2iu(i, u) case4(i, LAST, i, u)
915 #define casecomp(c, f, i, u, d) \
916 case TGSI_OPCODE_##c: \
917 if (type == GLSL_TYPE_DOUBLE) \
918 op = TGSI_OPCODE_##d; \
919 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
920 op = TGSI_OPCODE_##i; \
921 else if (type == GLSL_TYPE_UINT) \
922 op = TGSI_OPCODE_##u; \
923 else if (native_integers) \
924 op = TGSI_OPCODE_##f; \
926 op = TGSI_OPCODE_##c; \
930 case3fid(ADD
, UADD
, DADD
);
931 case3fid(MUL
, UMUL
, DMUL
);
932 case3fid(MAD
, UMAD
, DMAD
);
933 case3fid(FMA
, UMAD
, DFMA
);
934 case3(DIV
, IDIV
, UDIV
);
935 case4d(MAX
, IMAX
, UMAX
, DMAX
);
936 case4d(MIN
, IMIN
, UMIN
, DMIN
);
939 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
940 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
941 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
942 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
946 case3fid(SSG
, ISSG
, DSSG
);
947 case3fid(ABS
, IABS
, DABS
);
951 case2iu(IMUL_HI
, UMUL_HI
);
953 case3fid(SQRT
, SQRT
, DSQRT
);
955 case3fid(RCP
, RCP
, DRCP
);
956 case3fid(RSQ
, RSQ
, DRSQ
);
958 case3fid(FRC
, FRC
, DFRAC
);
959 case3fid(TRUNC
, TRUNC
, DTRUNC
);
960 case3fid(CEIL
, CEIL
, DCEIL
);
961 case3fid(FLR
, FLR
, DFLR
);
962 case3fid(ROUND
, ROUND
, DROUND
);
964 case2iu(ATOMIMAX
, ATOMUMAX
);
965 case2iu(ATOMIMIN
, ATOMUMIN
);
970 assert(op
!= TGSI_OPCODE_LAST
);
974 glsl_to_tgsi_instruction
*
975 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
976 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
979 static const unsigned dot_opcodes
[] = {
980 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
983 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
987 * Emits TGSI scalar opcodes to produce unique answers across channels.
989 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
990 * channel determines the result across all channels. So to do a vec4
991 * of this operation, we want to emit a scalar per source channel used
992 * to produce dest channels.
995 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
997 st_src_reg orig_src0
, st_src_reg orig_src1
)
1000 int done_mask
= ~dst
.writemask
;
1002 /* TGSI RCP is a scalar operation splatting results to all channels,
1003 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1006 for (i
= 0; i
< 4; i
++) {
1007 GLuint this_mask
= (1 << i
);
1008 st_src_reg src0
= orig_src0
;
1009 st_src_reg src1
= orig_src1
;
1011 if (done_mask
& this_mask
)
1014 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1015 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1016 for (j
= i
+ 1; j
< 4; j
++) {
1017 /* If there is another enabled component in the destination that is
1018 * derived from the same inputs, generate its value on this pass as
1021 if (!(done_mask
& (1 << j
)) &&
1022 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1023 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1024 this_mask
|= (1 << j
);
1027 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1028 src0_swiz
, src0_swiz
);
1029 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1030 src1_swiz
, src1_swiz
);
1032 dst
.writemask
= this_mask
;
1033 emit_asm(ir
, op
, dst
, src0
, src1
);
1034 done_mask
|= this_mask
;
1039 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1040 st_dst_reg dst
, st_src_reg src0
)
1042 st_src_reg undef
= undef_src
;
1044 undef
.swizzle
= SWIZZLE_XXXX
;
1046 emit_scalar(ir
, op
, dst
, src0
, undef
);
1050 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1051 st_dst_reg dst
, st_src_reg src0
)
1053 int op
= TGSI_OPCODE_ARL
;
1055 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1056 op
= TGSI_OPCODE_UARL
;
1058 assert(dst
.file
== PROGRAM_ADDRESS
);
1059 if (dst
.index
>= this->num_address_regs
)
1060 this->num_address_regs
= dst
.index
+ 1;
1062 emit_asm(NULL
, op
, dst
, src0
);
1066 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1067 gl_constant_value values
[8], int size
, int datatype
,
1068 GLuint
*swizzle_out
)
1070 if (file
== PROGRAM_CONSTANT
) {
1071 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1072 size
, datatype
, swizzle_out
);
1075 assert(file
== PROGRAM_IMMEDIATE
);
1078 immediate_storage
*entry
;
1079 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1082 /* Search immediate storage to see if we already have an identical
1083 * immediate that we can use instead of adding a duplicate entry.
1085 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1086 immediate_storage
*tmp
= entry
;
1088 for (i
= 0; i
* 4 < size32
; i
++) {
1089 int slot_size
= MIN2(size32
- (i
* 4), 4);
1090 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1092 if (memcmp(tmp
->values
, &values
[i
* 4],
1093 slot_size
* sizeof(gl_constant_value
)))
1096 /* Everything matches, keep going until the full size is matched */
1097 tmp
= (immediate_storage
*)tmp
->next
;
1100 /* The full value matched */
1101 if (i
* 4 >= size32
)
1107 for (i
= 0; i
* 4 < size32
; i
++) {
1108 int slot_size
= MIN2(size32
- (i
* 4), 4);
1109 /* Add this immediate to the list. */
1110 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1111 this->immediates
.push_tail(entry
);
1112 this->num_immediates
++;
1118 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1120 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1121 union gl_constant_value uval
;
1124 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1130 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1132 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1133 union gl_constant_value uval
[2];
1135 uval
[0].u
= *(uint32_t *)&val
;
1136 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1137 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1143 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1145 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1146 union gl_constant_value uval
;
1148 assert(native_integers
);
1151 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1157 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1159 if (native_integers
)
1160 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1161 st_src_reg_for_int(val
);
1163 return st_src_reg_for_float(val
);
1167 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1169 return st_glsl_attrib_type_size(type
, is_vs_input
);
1173 type_size(const struct glsl_type
*type
)
1175 return st_glsl_type_size(type
);
1179 * If the given GLSL type is an array or matrix or a structure containing
1180 * an array/matrix member, return true. Else return false.
1182 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1183 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1184 * we have an array that might be indexed with a variable, we need to use
1185 * the later storage type.
1188 type_has_array_or_matrix(const glsl_type
*type
)
1190 if (type
->is_array() || type
->is_matrix())
1193 if (type
->is_record()) {
1194 for (unsigned i
= 0; i
< type
->length
; i
++) {
1195 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1206 * In the initial pass of codegen, we assign temporary numbers to
1207 * intermediate results. (not SSA -- variable assignments will reuse
1211 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1215 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1219 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1220 if (next_array
>= max_num_arrays
) {
1221 max_num_arrays
+= 32;
1222 array_sizes
= (unsigned*)
1223 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1226 src
.file
= PROGRAM_ARRAY
;
1227 src
.index
= next_array
<< 16 | 0x8000;
1228 array_sizes
[next_array
] = type_size(type
);
1232 src
.file
= PROGRAM_TEMPORARY
;
1233 src
.index
= next_temp
;
1234 next_temp
+= type_size(type
);
1237 if (type
->is_array() || type
->is_record()) {
1238 src
.swizzle
= SWIZZLE_NOOP
;
1240 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1247 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1250 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1251 if (entry
->var
== var
)
1259 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1261 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1262 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1264 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1265 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1268 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1270 const ir_state_slot
*const slots
= ir
->get_state_slots();
1271 assert(slots
!= NULL
);
1273 /* Check if this statevar's setup in the STATE file exactly
1274 * matches how we'll want to reference it as a
1275 * struct/array/whatever. If not, then we need to move it into
1276 * temporary storage and hope that it'll get copy-propagated
1279 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1280 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1285 variable_storage
*storage
;
1287 if (i
== ir
->get_num_state_slots()) {
1288 /* We'll set the index later. */
1289 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1290 this->variables
.push_tail(storage
);
1294 /* The variable_storage constructor allocates slots based on the size
1295 * of the type. However, this had better match the number of state
1296 * elements that we're going to copy into the new temporary.
1298 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1300 dst
= st_dst_reg(get_temp(ir
->type
));
1302 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1304 this->variables
.push_tail(storage
);
1308 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1309 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1310 (gl_state_index
*)slots
[i
].tokens
);
1312 if (storage
->file
== PROGRAM_STATE_VAR
) {
1313 if (storage
->index
== -1) {
1314 storage
->index
= index
;
1316 assert(index
== storage
->index
+ (int)i
);
1319 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1320 * the data being moved since MOV does not care about the type of
1321 * data it is moving, and we don't want to declare registers with
1322 * array or struct types.
1324 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1325 src
.swizzle
= slots
[i
].swizzle
;
1326 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1327 /* even a float takes up a whole vec4 reg in a struct/array. */
1332 if (storage
->file
== PROGRAM_TEMPORARY
&&
1333 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1334 fail_link(this->shader_program
,
1335 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1336 ir
->name
, dst
.index
- storage
->index
,
1337 type_size(ir
->type
));
1343 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1345 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1347 visit_exec_list(&ir
->body_instructions
, this);
1349 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1353 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1356 case ir_loop_jump::jump_break
:
1357 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1359 case ir_loop_jump::jump_continue
:
1360 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1367 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1374 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1376 /* Ignore function bodies other than main() -- we shouldn't see calls to
1377 * them since they should all be inlined before we get to glsl_to_tgsi.
1379 if (strcmp(ir
->name
, "main") == 0) {
1380 const ir_function_signature
*sig
;
1383 sig
= ir
->matching_signature(NULL
, &empty
, false);
1387 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1394 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1396 int nonmul_operand
= 1 - mul_operand
;
1398 st_dst_reg result_dst
;
1400 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1401 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1404 expr
->operands
[0]->accept(this);
1406 expr
->operands
[1]->accept(this);
1408 ir
->operands
[nonmul_operand
]->accept(this);
1411 this->result
= get_temp(ir
->type
);
1412 result_dst
= st_dst_reg(this->result
);
1413 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1414 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1420 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1422 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1423 * implemented using multiplication, and logical-or is implemented using
1424 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1425 * As result, the logical expression (a & !b) can be rewritten as:
1429 * - (a * 1) - (a * b)
1433 * This final expression can be implemented as a single MAD(a, -b, a)
1437 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1439 const int other_operand
= 1 - try_operand
;
1442 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1443 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1446 ir
->operands
[other_operand
]->accept(this);
1448 expr
->operands
[0]->accept(this);
1451 b
.negate
= ~b
.negate
;
1453 this->result
= get_temp(ir
->type
);
1454 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1460 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1461 st_src_reg
*reg
, int *num_reladdr
)
1463 if (!reg
->reladdr
&& !reg
->reladdr2
)
1466 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1467 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1469 if (*num_reladdr
!= 1) {
1470 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1472 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1480 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1482 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1484 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1486 if (ir
->operation
== ir_binop_add
) {
1487 if (try_emit_mad(ir
, 1))
1489 if (try_emit_mad(ir
, 0))
1493 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1495 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1496 if (try_emit_mad_for_and_not(ir
, 1))
1498 if (try_emit_mad_for_and_not(ir
, 0))
1502 if (ir
->operation
== ir_quadop_vector
)
1503 assert(!"ir_quadop_vector should have been lowered");
1505 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1506 this->result
.file
= PROGRAM_UNDEFINED
;
1507 ir
->operands
[operand
]->accept(this);
1508 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1509 printf("Failed to get tree for expression operand:\n");
1510 ir
->operands
[operand
]->print();
1514 op
[operand
] = this->result
;
1516 /* Matrix expression operands should have been broken down to vector
1517 * operations already.
1519 assert(!ir
->operands
[operand
]->type
->is_matrix());
1522 visit_expression(ir
, op
);
1525 /* The non-recursive part of the expression visitor lives in a separate
1526 * function and should be prevented from being inlined, to avoid a stack
1527 * explosion when deeply nested expressions are visited.
1530 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1532 st_src_reg result_src
;
1533 st_dst_reg result_dst
;
1535 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1536 if (ir
->operands
[1]) {
1537 vector_elements
= MAX2(vector_elements
,
1538 ir
->operands
[1]->type
->vector_elements
);
1541 this->result
.file
= PROGRAM_UNDEFINED
;
1543 /* Storage for our result. Ideally for an assignment we'd be using
1544 * the actual storage for the result here, instead.
1546 result_src
= get_temp(ir
->type
);
1547 /* convenience for the emit functions below. */
1548 result_dst
= st_dst_reg(result_src
);
1549 /* Limit writes to the channels that will be used by result_src later.
1550 * This does limit this temp's use as a temporary for multi-instruction
1553 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1555 switch (ir
->operation
) {
1556 case ir_unop_logic_not
:
1557 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1558 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1560 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1561 * older GPUs implement SEQ using multiple instructions (i915 uses two
1562 * SGE instructions and a MUL instruction). Since our logic values are
1563 * 0.0 and 1.0, 1-x also implements !x.
1565 op
[0].negate
= ~op
[0].negate
;
1566 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1570 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1571 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1572 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1573 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1575 op
[0].negate
= ~op
[0].negate
;
1579 case ir_unop_subroutine_to_int
:
1580 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1583 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1586 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1589 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1593 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1597 assert(!"not reached: should be handled by ir_explog_to_explog2");
1600 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1603 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1606 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1608 case ir_unop_saturate
: {
1609 glsl_to_tgsi_instruction
*inst
;
1610 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1611 inst
->saturate
= true;
1616 case ir_unop_dFdx_coarse
:
1617 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1619 case ir_unop_dFdx_fine
:
1620 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1623 case ir_unop_dFdy_coarse
:
1624 case ir_unop_dFdy_fine
:
1626 /* The X component contains 1 or -1 depending on whether the framebuffer
1627 * is a FBO or the window system buffer, respectively.
1628 * It is then multiplied with the source operand of DDY.
1630 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1631 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1633 unsigned transform_y_index
=
1634 _mesa_add_state_reference(this->prog
->Parameters
,
1637 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1639 glsl_type::vec4_type
);
1640 transform_y
.swizzle
= SWIZZLE_XXXX
;
1642 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1644 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1645 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1646 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1650 case ir_unop_frexp_sig
:
1651 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1654 case ir_unop_frexp_exp
:
1655 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1658 case ir_unop_noise
: {
1659 /* At some point, a motivated person could add a better
1660 * implementation of noise. Currently not even the nvidia
1661 * binary drivers do anything more than this. In any case, the
1662 * place to do this is in the GL state tracker, not the poor
1665 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1670 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1673 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1677 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1680 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1681 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1683 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1686 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1687 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1689 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1693 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1695 case ir_binop_greater
:
1696 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1698 case ir_binop_lequal
:
1699 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1701 case ir_binop_gequal
:
1702 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1704 case ir_binop_equal
:
1705 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1707 case ir_binop_nequal
:
1708 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1710 case ir_binop_all_equal
:
1711 /* "==" operator producing a scalar boolean. */
1712 if (ir
->operands
[0]->type
->is_vector() ||
1713 ir
->operands
[1]->type
->is_vector()) {
1714 st_src_reg temp
= get_temp(native_integers
?
1715 glsl_type::uvec4_type
:
1716 glsl_type::vec4_type
);
1718 if (native_integers
) {
1719 st_dst_reg temp_dst
= st_dst_reg(temp
);
1720 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1722 if (ir
->operands
[0]->type
->is_boolean() &&
1723 ir
->operands
[1]->as_constant() &&
1724 ir
->operands
[1]->as_constant()->is_one()) {
1725 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1727 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1730 /* Emit 1-3 AND operations to combine the SEQ results. */
1731 switch (ir
->operands
[0]->type
->vector_elements
) {
1735 temp_dst
.writemask
= WRITEMASK_Y
;
1736 temp1
.swizzle
= SWIZZLE_YYYY
;
1737 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1738 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1741 temp_dst
.writemask
= WRITEMASK_X
;
1742 temp1
.swizzle
= SWIZZLE_XXXX
;
1743 temp2
.swizzle
= SWIZZLE_YYYY
;
1744 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1745 temp_dst
.writemask
= WRITEMASK_Y
;
1746 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1747 temp2
.swizzle
= SWIZZLE_WWWW
;
1748 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1751 temp1
.swizzle
= SWIZZLE_XXXX
;
1752 temp2
.swizzle
= SWIZZLE_YYYY
;
1753 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1755 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1757 /* After the dot-product, the value will be an integer on the
1758 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1760 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1762 /* Negating the result of the dot-product gives values on the range
1763 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1764 * This is achieved using SGE.
1766 st_src_reg sge_src
= result_src
;
1767 sge_src
.negate
= ~sge_src
.negate
;
1768 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1771 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1774 case ir_binop_any_nequal
:
1775 /* "!=" operator producing a scalar boolean. */
1776 if (ir
->operands
[0]->type
->is_vector() ||
1777 ir
->operands
[1]->type
->is_vector()) {
1778 st_src_reg temp
= get_temp(native_integers
?
1779 glsl_type::uvec4_type
:
1780 glsl_type::vec4_type
);
1781 if (ir
->operands
[0]->type
->is_boolean() &&
1782 ir
->operands
[1]->as_constant() &&
1783 ir
->operands
[1]->as_constant()->is_zero()) {
1784 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1786 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1789 if (native_integers
) {
1790 st_dst_reg temp_dst
= st_dst_reg(temp
);
1791 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1793 /* Emit 1-3 OR operations to combine the SNE results. */
1794 switch (ir
->operands
[0]->type
->vector_elements
) {
1798 temp_dst
.writemask
= WRITEMASK_Y
;
1799 temp1
.swizzle
= SWIZZLE_YYYY
;
1800 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1801 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1804 temp_dst
.writemask
= WRITEMASK_X
;
1805 temp1
.swizzle
= SWIZZLE_XXXX
;
1806 temp2
.swizzle
= SWIZZLE_YYYY
;
1807 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1808 temp_dst
.writemask
= WRITEMASK_Y
;
1809 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1810 temp2
.swizzle
= SWIZZLE_WWWW
;
1811 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1814 temp1
.swizzle
= SWIZZLE_XXXX
;
1815 temp2
.swizzle
= SWIZZLE_YYYY
;
1816 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1818 /* After the dot-product, the value will be an integer on the
1819 * range [0,4]. Zero stays zero, and positive values become 1.0.
1821 glsl_to_tgsi_instruction
*const dp
=
1822 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1823 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1824 /* The clamping to [0,1] can be done for free in the fragment
1825 * shader with a saturate.
1827 dp
->saturate
= true;
1829 /* Negating the result of the dot-product gives values on the range
1830 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1831 * achieved using SLT.
1833 st_src_reg slt_src
= result_src
;
1834 slt_src
.negate
= ~slt_src
.negate
;
1835 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1839 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1843 case ir_binop_logic_xor
:
1844 if (native_integers
)
1845 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1847 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1850 case ir_binop_logic_or
: {
1851 if (native_integers
) {
1852 /* If integers are used as booleans, we can use an actual "or"
1855 assert(native_integers
);
1856 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1858 /* After the addition, the value will be an integer on the
1859 * range [0,2]. Zero stays zero, and positive values become 1.0.
1861 glsl_to_tgsi_instruction
*add
=
1862 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1863 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1864 /* The clamping to [0,1] can be done for free in the fragment
1865 * shader with a saturate if floats are being used as boolean values.
1867 add
->saturate
= true;
1869 /* Negating the result of the addition gives values on the range
1870 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1871 * is achieved using SLT.
1873 st_src_reg slt_src
= result_src
;
1874 slt_src
.negate
= ~slt_src
.negate
;
1875 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1881 case ir_binop_logic_and
:
1882 /* If native integers are disabled, the bool args are stored as float 0.0
1883 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1884 * actual AND opcode.
1886 if (native_integers
)
1887 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1889 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1893 assert(ir
->operands
[0]->type
->is_vector());
1894 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1895 emit_dp(ir
, result_dst
, op
[0], op
[1],
1896 ir
->operands
[0]->type
->vector_elements
);
1901 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1903 /* sqrt(x) = x * rsq(x). */
1904 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1905 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1906 /* For incoming channels <= 0, set the result to 0. */
1907 op
[0].negate
= ~op
[0].negate
;
1908 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1909 op
[0], result_src
, st_src_reg_for_float(0.0));
1913 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1916 if (native_integers
) {
1917 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1920 /* fallthrough to next case otherwise */
1922 if (native_integers
) {
1923 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1926 /* fallthrough to next case otherwise */
1929 /* Converting between signed and unsigned integers is a no-op. */
1931 result_src
.type
= result_dst
.type
;
1934 if (native_integers
) {
1935 /* Booleans are stored as integers using ~0 for true and 0 for false.
1936 * GLSL requires that int(bool) return 1 for true and 0 for false.
1937 * This conversion is done with AND, but it could be done with NEG.
1939 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1941 /* Booleans and integers are both stored as floats when native
1942 * integers are disabled.
1948 if (native_integers
)
1949 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1951 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1954 if (native_integers
)
1955 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1957 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1959 case ir_unop_bitcast_f2i
:
1961 result_src
.type
= GLSL_TYPE_INT
;
1963 case ir_unop_bitcast_f2u
:
1965 result_src
.type
= GLSL_TYPE_UINT
;
1967 case ir_unop_bitcast_i2f
:
1968 case ir_unop_bitcast_u2f
:
1970 result_src
.type
= GLSL_TYPE_FLOAT
;
1973 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1976 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1979 if (native_integers
)
1980 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1982 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1985 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1988 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1991 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1993 case ir_unop_round_even
:
1994 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1997 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2001 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2004 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2007 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2010 case ir_unop_bit_not
:
2011 if (native_integers
) {
2012 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2016 if (native_integers
) {
2017 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2020 case ir_binop_lshift
:
2021 if (native_integers
) {
2022 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2025 case ir_binop_rshift
:
2026 if (native_integers
) {
2027 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2030 case ir_binop_bit_and
:
2031 if (native_integers
) {
2032 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2035 case ir_binop_bit_xor
:
2036 if (native_integers
) {
2037 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2040 case ir_binop_bit_or
:
2041 if (native_integers
) {
2042 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2046 assert(!"GLSL 1.30 features unsupported");
2049 case ir_binop_ubo_load
: {
2050 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2051 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2052 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2053 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2054 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2057 cbuf
.type
= ir
->type
->base_type
;
2058 cbuf
.file
= PROGRAM_CONSTANT
;
2060 cbuf
.reladdr
= NULL
;
2063 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2065 if (const_offset_ir
) {
2066 /* Constant index into constant buffer */
2067 cbuf
.reladdr
= NULL
;
2068 cbuf
.index
= const_offset
/ 16;
2071 /* Relative/variable index into constant buffer */
2072 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2073 st_src_reg_for_int(4));
2074 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2075 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2078 if (const_uniform_block
) {
2079 /* Constant constant buffer */
2080 cbuf
.reladdr2
= NULL
;
2081 cbuf
.index2D
= const_block
;
2082 cbuf
.has_index2
= true;
2085 /* Relative/variable constant buffer */
2086 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2088 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2089 cbuf
.has_index2
= true;
2092 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2093 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2094 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2095 const_offset
% 16 / 8,
2096 const_offset
% 16 / 8,
2097 const_offset
% 16 / 8);
2099 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2100 const_offset
% 16 / 4,
2101 const_offset
% 16 / 4,
2102 const_offset
% 16 / 4);
2104 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2105 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2107 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2112 /* note: we have to reorder the three args here */
2113 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2116 if (this->ctx
->Const
.NativeIntegers
)
2117 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2119 op
[0].negate
= ~op
[0].negate
;
2120 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2123 case ir_triop_bitfield_extract
:
2124 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2126 case ir_quadop_bitfield_insert
:
2127 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2129 case ir_unop_bitfield_reverse
:
2130 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2132 case ir_unop_bit_count
:
2133 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2135 case ir_unop_find_msb
:
2136 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2138 case ir_unop_find_lsb
:
2139 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2141 case ir_binop_imul_high
:
2142 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2145 /* In theory, MAD is incorrect here. */
2147 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2149 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2151 case ir_unop_interpolate_at_centroid
:
2152 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2154 case ir_binop_interpolate_at_offset
:
2155 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2157 case ir_binop_interpolate_at_sample
:
2158 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2162 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2165 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2168 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2171 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2174 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2177 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2179 case ir_unop_unpack_double_2x32
:
2180 case ir_unop_pack_double_2x32
:
2181 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2184 case ir_binop_ldexp
:
2185 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2186 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2188 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2192 case ir_unop_pack_half_2x16
:
2193 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2195 case ir_unop_unpack_half_2x16
:
2196 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2199 case ir_unop_get_buffer_size
: {
2200 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2203 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2204 (const_offset
? const_offset
->value
.u
[0] : 0),
2206 if (!const_offset
) {
2207 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2208 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
2209 emit_arl(ir
, sampler_reladdr
, op
[0]);
2211 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2215 case ir_unop_pack_snorm_2x16
:
2216 case ir_unop_pack_unorm_2x16
:
2217 case ir_unop_pack_snorm_4x8
:
2218 case ir_unop_pack_unorm_4x8
:
2220 case ir_unop_unpack_snorm_2x16
:
2221 case ir_unop_unpack_unorm_2x16
:
2222 case ir_unop_unpack_snorm_4x8
:
2223 case ir_unop_unpack_unorm_4x8
:
2225 case ir_quadop_vector
:
2226 case ir_binop_vector_extract
:
2227 case ir_triop_vector_insert
:
2228 case ir_binop_carry
:
2229 case ir_binop_borrow
:
2230 case ir_unop_ssbo_unsized_array_length
:
2231 /* This operation is not supported, or should have already been handled.
2233 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2237 this->result
= result_src
;
2242 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2248 /* Note that this is only swizzles in expressions, not those on the left
2249 * hand side of an assignment, which do write masking. See ir_assignment
2253 ir
->val
->accept(this);
2255 assert(src
.file
!= PROGRAM_UNDEFINED
);
2256 assert(ir
->type
->vector_elements
> 0);
2258 for (i
= 0; i
< 4; i
++) {
2259 if (i
< ir
->type
->vector_elements
) {
2262 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2265 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2268 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2271 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2275 /* If the type is smaller than a vec4, replicate the last
2278 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2282 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2287 /* Test if the variable is an array. Note that geometry and
2288 * tessellation shader inputs are outputs are always arrays (except
2289 * for patch inputs), so only the array element type is considered.
2292 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2294 const glsl_type
*type
= var
->type
;
2296 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2297 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2302 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2303 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2304 stage
== MESA_SHADER_TESS_CTRL
) &&
2306 if (!var
->type
->is_array())
2307 return false; /* a system value probably */
2309 type
= var
->type
->fields
.array
;
2313 return type
->is_array() || type
->is_matrix();
2317 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2319 variable_storage
*entry
= find_variable_storage(ir
->var
);
2320 ir_variable
*var
= ir
->var
;
2324 switch (var
->data
.mode
) {
2325 case ir_var_uniform
:
2326 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2327 var
->data
.param_index
);
2328 this->variables
.push_tail(entry
);
2330 case ir_var_shader_in
:
2331 /* The linker assigns locations for varyings and attributes,
2332 * including deprecated builtins (like gl_Color), user-assign
2333 * generic attributes (glBindVertexLocation), and
2334 * user-defined varyings.
2336 assert(var
->data
.location
!= -1);
2338 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2339 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2341 decl
->mesa_index
= var
->data
.location
;
2342 decl
->array_id
= num_input_arrays
+ 1;
2344 decl
->array_size
= type_size(var
->type
->fields
.array
);
2345 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2347 decl
->array_size
= type_size(var
->type
);
2348 decl
->array_type
= var
->type
->without_array()->base_type
;
2352 entry
= new(mem_ctx
) variable_storage(var
,
2358 entry
= new(mem_ctx
) variable_storage(var
,
2360 var
->data
.location
);
2362 this->variables
.push_tail(entry
);
2364 case ir_var_shader_out
:
2365 assert(var
->data
.location
!= -1);
2367 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2368 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2370 decl
->mesa_index
= var
->data
.location
;
2371 decl
->array_id
= num_output_arrays
+ 1;
2373 decl
->array_size
= type_size(var
->type
->fields
.array
);
2374 decl
->array_type
= var
->type
->fields
.array
->without_array()->base_type
;
2376 decl
->array_size
= type_size(var
->type
);
2377 decl
->array_type
= var
->type
->without_array()->base_type
;
2379 num_output_arrays
++;
2381 entry
= new(mem_ctx
) variable_storage(var
,
2387 entry
= new(mem_ctx
) variable_storage(var
,
2392 this->variables
.push_tail(entry
);
2394 case ir_var_system_value
:
2395 entry
= new(mem_ctx
) variable_storage(var
,
2396 PROGRAM_SYSTEM_VALUE
,
2397 var
->data
.location
);
2400 case ir_var_temporary
:
2401 st_src_reg src
= get_temp(var
->type
);
2403 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2404 this->variables
.push_tail(entry
);
2410 printf("Failed to make storage for %s\n", var
->name
);
2415 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2416 this->result
.array_id
= entry
->array_id
;
2417 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2418 this->result
.is_double_vertex_input
= true;
2419 if (!native_integers
)
2420 this->result
.type
= GLSL_TYPE_FLOAT
;
2424 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2425 GLbitfield64 usage_mask
,
2426 GLbitfield64 double_usage_mask
,
2427 GLbitfield patch_usage_mask
)
2431 /* Fix array declarations by removing unused array elements at both ends
2432 * of the arrays. For example, mat4[3] where only mat[1] is used.
2434 for (i
= 0; i
< count
; i
++) {
2435 struct array_decl
*decl
= &arrays
[i
];
2437 /* Shrink the beginning. */
2438 for (j
= 0; j
< decl
->array_size
; j
++) {
2439 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2440 if (patch_usage_mask
&
2441 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2445 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2447 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2456 /* Shrink the end. */
2457 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2458 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2459 if (patch_usage_mask
&
2460 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2464 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2466 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2476 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2480 int element_size
= type_size(ir
->type
);
2483 index
= ir
->array_index
->constant_expression_value();
2485 ir
->array
->accept(this);
2488 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2489 switch (this->prog
->Target
) {
2490 case GL_TESS_CONTROL_PROGRAM_NV
:
2491 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2492 !ir
->variable_referenced()->data
.patch
;
2494 case GL_TESS_EVALUATION_PROGRAM_NV
:
2495 is_2D
= src
.file
== PROGRAM_INPUT
&&
2496 !ir
->variable_referenced()->data
.patch
;
2498 case GL_GEOMETRY_PROGRAM_NV
:
2499 is_2D
= src
.file
== PROGRAM_INPUT
;
2509 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2510 src
.file
== PROGRAM_INPUT
)
2511 element_size
= attrib_type_size(ir
->type
, true);
2513 src
.index2D
= index
->value
.i
[0];
2514 src
.has_index2
= true;
2516 src
.index
+= index
->value
.i
[0] * element_size
;
2518 /* Variable index array dereference. It eats the "vec4" of the
2519 * base of the array and an index that offsets the TGSI register
2522 ir
->array_index
->accept(this);
2524 st_src_reg index_reg
;
2526 if (element_size
== 1) {
2527 index_reg
= this->result
;
2529 index_reg
= get_temp(native_integers
?
2530 glsl_type::int_type
: glsl_type::float_type
);
2532 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2533 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2536 /* If there was already a relative address register involved, add the
2537 * new and the old together to get the new offset.
2539 if (!is_2D
&& src
.reladdr
!= NULL
) {
2540 st_src_reg accum_reg
= get_temp(native_integers
?
2541 glsl_type::int_type
: glsl_type::float_type
);
2543 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2544 index_reg
, *src
.reladdr
);
2546 index_reg
= accum_reg
;
2550 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2551 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2553 src
.has_index2
= true;
2555 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2556 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2560 /* If the type is smaller than a vec4, replicate the last channel out. */
2561 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2562 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2564 src
.swizzle
= SWIZZLE_NOOP
;
2566 /* Change the register type to the element type of the array. */
2567 src
.type
= ir
->type
->base_type
;
2573 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2576 const glsl_type
*struct_type
= ir
->record
->type
;
2579 ir
->record
->accept(this);
2581 for (i
= 0; i
< struct_type
->length
; i
++) {
2582 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2584 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2587 /* If the type is smaller than a vec4, replicate the last channel out. */
2588 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2589 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2591 this->result
.swizzle
= SWIZZLE_NOOP
;
2593 this->result
.index
+= offset
;
2594 this->result
.type
= ir
->type
->base_type
;
2598 * We want to be careful in assignment setup to hit the actual storage
2599 * instead of potentially using a temporary like we might with the
2600 * ir_dereference handler.
2603 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2605 /* The LHS must be a dereference. If the LHS is a variable indexed array
2606 * access of a vector, it must be separated into a series conditional moves
2607 * before reaching this point (see ir_vec_index_to_cond_assign).
2609 assert(ir
->as_dereference());
2610 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2612 assert(!deref_array
->array
->type
->is_vector());
2615 /* Use the rvalue deref handler for the most part. We'll ignore
2616 * swizzles in it and write swizzles using writemask, though.
2619 return st_dst_reg(v
->result
);
2623 * Process the condition of a conditional assignment
2625 * Examines the condition of a conditional assignment to generate the optimal
2626 * first operand of a \c CMP instruction. If the condition is a relational
2627 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2628 * used as the source for the \c CMP instruction. Otherwise the comparison
2629 * is processed to a boolean result, and the boolean result is used as the
2630 * operand to the CMP instruction.
2633 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2635 ir_rvalue
*src_ir
= ir
;
2637 bool switch_order
= false;
2639 ir_expression
*const expr
= ir
->as_expression();
2641 if (native_integers
) {
2642 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2643 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2644 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2645 type
== GLSL_TYPE_BOOL
) {
2646 if (expr
->operation
== ir_binop_equal
) {
2647 if (expr
->operands
[0]->is_zero()) {
2648 src_ir
= expr
->operands
[1];
2649 switch_order
= true;
2651 else if (expr
->operands
[1]->is_zero()) {
2652 src_ir
= expr
->operands
[0];
2653 switch_order
= true;
2656 else if (expr
->operation
== ir_binop_nequal
) {
2657 if (expr
->operands
[0]->is_zero()) {
2658 src_ir
= expr
->operands
[1];
2660 else if (expr
->operands
[1]->is_zero()) {
2661 src_ir
= expr
->operands
[0];
2667 src_ir
->accept(this);
2668 return switch_order
;
2671 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2672 bool zero_on_left
= false;
2674 if (expr
->operands
[0]->is_zero()) {
2675 src_ir
= expr
->operands
[1];
2676 zero_on_left
= true;
2677 } else if (expr
->operands
[1]->is_zero()) {
2678 src_ir
= expr
->operands
[0];
2679 zero_on_left
= false;
2683 * (a < 0) T F F ( a < 0) T F F
2684 * (0 < a) F F T (-a < 0) F F T
2685 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2686 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2687 * (a > 0) F F T (-a < 0) F F T
2688 * (0 > a) T F F ( a < 0) T F F
2689 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2690 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2692 * Note that exchanging the order of 0 and 'a' in the comparison simply
2693 * means that the value of 'a' should be negated.
2696 switch (expr
->operation
) {
2698 switch_order
= false;
2699 negate
= zero_on_left
;
2702 case ir_binop_greater
:
2703 switch_order
= false;
2704 negate
= !zero_on_left
;
2707 case ir_binop_lequal
:
2708 switch_order
= true;
2709 negate
= !zero_on_left
;
2712 case ir_binop_gequal
:
2713 switch_order
= true;
2714 negate
= zero_on_left
;
2718 /* This isn't the right kind of comparison afterall, so make sure
2719 * the whole condition is visited.
2727 src_ir
->accept(this);
2729 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2730 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2731 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2732 * computing the condition.
2735 this->result
.negate
= ~this->result
.negate
;
2737 return switch_order
;
2741 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2742 st_dst_reg
*l
, st_src_reg
*r
,
2743 st_src_reg
*cond
, bool cond_swap
)
2745 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2746 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2747 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2753 if (type
->is_array()) {
2754 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2755 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2760 if (type
->is_matrix()) {
2761 const struct glsl_type
*vec_type
;
2763 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2764 type
->vector_elements
, 1);
2766 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2767 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2772 assert(type
->is_scalar() || type
->is_vector());
2774 r
->type
= type
->base_type
;
2776 st_src_reg l_src
= st_src_reg(*l
);
2777 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2779 if (native_integers
) {
2780 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2781 cond_swap
? l_src
: *r
,
2782 cond_swap
? *r
: l_src
);
2784 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2785 cond_swap
? l_src
: *r
,
2786 cond_swap
? *r
: l_src
);
2789 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2793 if (type
->is_dual_slot_double()) {
2795 if (r
->is_double_vertex_input
== false)
2801 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2806 ir
->rhs
->accept(this);
2809 l
= get_assignment_lhs(ir
->lhs
, this);
2811 /* FINISHME: This should really set to the correct maximal writemask for each
2812 * FINISHME: component written (in the loops below). This case can only
2813 * FINISHME: occur for matrices, arrays, and structures.
2815 if (ir
->write_mask
== 0) {
2816 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2818 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->without_array()->is_matrix()) {
2819 if (ir
->lhs
->type
->without_array()->is_double()) {
2820 switch (ir
->lhs
->type
->without_array()->vector_elements
) {
2822 l
.writemask
= WRITEMASK_X
;
2825 l
.writemask
= WRITEMASK_XY
;
2828 l
.writemask
= WRITEMASK_XYZ
;
2831 l
.writemask
= WRITEMASK_XYZW
;
2835 l
.writemask
= WRITEMASK_XYZW
;
2837 } else if (ir
->lhs
->type
->is_scalar() &&
2838 !ir
->lhs
->type
->is_double() &&
2839 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2840 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2841 * FINISHME: W component of fragment shader output zero, work correctly.
2843 l
.writemask
= WRITEMASK_XYZW
;
2846 int first_enabled_chan
= 0;
2849 l
.writemask
= ir
->write_mask
;
2851 for (int i
= 0; i
< 4; i
++) {
2852 if (l
.writemask
& (1 << i
)) {
2853 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2858 /* Swizzle a small RHS vector into the channels being written.
2860 * glsl ir treats write_mask as dictating how many channels are
2861 * present on the RHS while TGSI treats write_mask as just
2862 * showing which channels of the vec4 RHS get written.
2864 for (int i
= 0; i
< 4; i
++) {
2865 if (l
.writemask
& (1 << i
))
2866 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2868 swizzles
[i
] = first_enabled_chan
;
2870 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2871 swizzles
[2], swizzles
[3]);
2874 assert(l
.file
!= PROGRAM_UNDEFINED
);
2875 assert(r
.file
!= PROGRAM_UNDEFINED
);
2877 if (ir
->condition
) {
2878 const bool switch_order
= this->process_move_condition(ir
->condition
);
2879 st_src_reg condition
= this->result
;
2881 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2882 } else if (ir
->rhs
->as_expression() &&
2883 this->instructions
.get_tail() &&
2884 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2885 type_size(ir
->lhs
->type
) == 1 &&
2886 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2887 /* To avoid emitting an extra MOV when assigning an expression to a
2888 * variable, emit the last instruction of the expression again, but
2889 * replace the destination register with the target of the assignment.
2890 * Dead code elimination will remove the original instruction.
2892 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2893 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2894 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
2895 new_inst
->saturate
= inst
->saturate
;
2896 inst
->dead_mask
= inst
->dst
[0].writemask
;
2898 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2904 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2907 GLdouble stack_vals
[4] = { 0 };
2908 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2909 GLenum gl_type
= GL_NONE
;
2911 static int in_array
= 0;
2912 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2914 /* Unfortunately, 4 floats is all we can get into
2915 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2916 * aggregate constant and move each constant value into it. If we
2917 * get lucky, copy propagation will eliminate the extra moves.
2919 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2920 st_src_reg temp_base
= get_temp(ir
->type
);
2921 st_dst_reg temp
= st_dst_reg(temp_base
);
2923 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2924 int size
= type_size(field_value
->type
);
2928 field_value
->accept(this);
2931 for (i
= 0; i
< (unsigned int)size
; i
++) {
2932 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2938 this->result
= temp_base
;
2942 if (ir
->type
->is_array()) {
2943 st_src_reg temp_base
= get_temp(ir
->type
);
2944 st_dst_reg temp
= st_dst_reg(temp_base
);
2945 int size
= type_size(ir
->type
->fields
.array
);
2950 for (i
= 0; i
< ir
->type
->length
; i
++) {
2951 ir
->array_elements
[i
]->accept(this);
2953 for (int j
= 0; j
< size
; j
++) {
2954 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2960 this->result
= temp_base
;
2965 if (ir
->type
->is_matrix()) {
2966 st_src_reg mat
= get_temp(ir
->type
);
2967 st_dst_reg mat_column
= st_dst_reg(mat
);
2969 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2970 switch (ir
->type
->base_type
) {
2971 case GLSL_TYPE_FLOAT
:
2972 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2974 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2975 src
.index
= add_constant(file
,
2977 ir
->type
->vector_elements
,
2980 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2982 case GLSL_TYPE_DOUBLE
:
2983 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
2984 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2985 src
.index
= add_constant(file
,
2987 ir
->type
->vector_elements
,
2990 if (ir
->type
->vector_elements
>= 2) {
2991 mat_column
.writemask
= WRITEMASK_XY
;
2992 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
2993 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2995 mat_column
.writemask
= WRITEMASK_X
;
2996 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2997 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3000 if (ir
->type
->vector_elements
> 2) {
3001 if (ir
->type
->vector_elements
== 4) {
3002 mat_column
.writemask
= WRITEMASK_ZW
;
3003 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3004 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3006 mat_column
.writemask
= WRITEMASK_Z
;
3007 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3008 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3009 mat_column
.writemask
= WRITEMASK_XYZW
;
3010 src
.swizzle
= SWIZZLE_XYZW
;
3016 unreachable("Illegal matrix constant type.\n");
3025 switch (ir
->type
->base_type
) {
3026 case GLSL_TYPE_FLOAT
:
3028 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3029 values
[i
].f
= ir
->value
.f
[i
];
3032 case GLSL_TYPE_DOUBLE
:
3033 gl_type
= GL_DOUBLE
;
3034 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3035 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
3036 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
3039 case GLSL_TYPE_UINT
:
3040 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3041 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3042 if (native_integers
)
3043 values
[i
].u
= ir
->value
.u
[i
];
3045 values
[i
].f
= ir
->value
.u
[i
];
3049 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3050 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3051 if (native_integers
)
3052 values
[i
].i
= ir
->value
.i
[i
];
3054 values
[i
].f
= ir
->value
.i
[i
];
3057 case GLSL_TYPE_BOOL
:
3058 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3059 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3060 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3064 assert(!"Non-float/uint/int/bool constant");
3067 this->result
= st_src_reg(file
, -1, ir
->type
);
3068 this->result
.index
= add_constant(file
,
3070 ir
->type
->vector_elements
,
3072 &this->result
.swizzle
);
3076 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3078 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3079 if (entry
->sig
== sig
)
3083 entry
= ralloc(mem_ctx
, function_entry
);
3085 entry
->sig_id
= this->next_signature_id
++;
3086 entry
->bgn_inst
= NULL
;
3088 /* Allocate storage for all the parameters. */
3089 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3090 variable_storage
*storage
;
3092 storage
= find_variable_storage(param
);
3095 st_src_reg src
= get_temp(param
->type
);
3097 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3098 this->variables
.push_tail(storage
);
3101 if (!sig
->return_type
->is_void()) {
3102 entry
->return_reg
= get_temp(sig
->return_type
);
3104 entry
->return_reg
= undef_src
;
3107 this->function_signatures
.push_tail(entry
);
3112 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3114 const char *callee
= ir
->callee
->function_name();
3115 exec_node
*param
= ir
->actual_parameters
.get_head();
3116 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3117 ir_variable
*location
= deref
->variable_referenced();
3120 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3122 /* Calculate the surface offset */
3124 unsigned array_size
= 0, base
= 0, index
= 0;
3126 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
);
3128 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3129 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3130 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3131 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3132 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3134 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3137 ir
->return_deref
->accept(this);
3138 st_dst_reg
dst(this->result
);
3139 dst
.writemask
= WRITEMASK_X
;
3141 glsl_to_tgsi_instruction
*inst
;
3143 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3144 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3145 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3146 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3147 st_src_reg_for_int(1));
3148 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3149 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3150 st_src_reg_for_int(-1));
3151 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3153 param
= param
->get_next();
3154 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3157 st_src_reg data
= this->result
, data2
= undef_src
;
3159 if (!strcmp("__intrinsic_atomic_add", callee
))
3160 opcode
= TGSI_OPCODE_ATOMUADD
;
3161 else if (!strcmp("__intrinsic_atomic_min", callee
))
3162 opcode
= TGSI_OPCODE_ATOMIMIN
;
3163 else if (!strcmp("__intrinsic_atomic_max", callee
))
3164 opcode
= TGSI_OPCODE_ATOMIMAX
;
3165 else if (!strcmp("__intrinsic_atomic_and", callee
))
3166 opcode
= TGSI_OPCODE_ATOMAND
;
3167 else if (!strcmp("__intrinsic_atomic_or", callee
))
3168 opcode
= TGSI_OPCODE_ATOMOR
;
3169 else if (!strcmp("__intrinsic_atomic_xor", callee
))
3170 opcode
= TGSI_OPCODE_ATOMXOR
;
3171 else if (!strcmp("__intrinsic_atomic_exchange", callee
))
3172 opcode
= TGSI_OPCODE_ATOMXCHG
;
3173 else if (!strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3174 opcode
= TGSI_OPCODE_ATOMCAS
;
3175 param
= param
->get_next();
3176 val
= ((ir_instruction
*)param
)->as_rvalue();
3178 data2
= this->result
;
3179 } else if (!strcmp("__intrinsic_atomic_sub", callee
)) {
3180 opcode
= TGSI_OPCODE_ATOMUADD
;
3181 st_src_reg res
= get_temp(glsl_type::uvec4_type
);
3182 st_dst_reg dstres
= st_dst_reg(res
);
3183 dstres
.writemask
= dst
.writemask
;
3184 emit_asm(ir
, TGSI_OPCODE_INEG
, dstres
, data
);
3187 assert(!"Unexpected intrinsic");
3191 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3194 inst
->buffer
= buffer
;
3198 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3200 const char *callee
= ir
->callee
->function_name();
3201 exec_node
*param
= ir
->actual_parameters
.get_head();
3203 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3205 param
= param
->get_next();
3206 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3208 ir_constant
*const_block
= block
->as_constant();
3212 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3213 (const_block
? const_block
->value
.u
[0] : 0),
3217 block
->accept(this);
3218 emit_arl(ir
, sampler_reladdr
, this->result
);
3219 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3220 memcpy(buffer
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3223 /* Calculate the surface offset */
3224 offset
->accept(this);
3225 st_src_reg off
= this->result
;
3227 st_dst_reg dst
= undef_dst
;
3228 if (ir
->return_deref
) {
3229 ir
->return_deref
->accept(this);
3230 dst
= st_dst_reg(this->result
);
3231 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3234 glsl_to_tgsi_instruction
*inst
;
3236 if (!strcmp("__intrinsic_load_ssbo", callee
)) {
3237 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3238 if (dst
.type
== GLSL_TYPE_BOOL
)
3239 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3240 } else if (!strcmp("__intrinsic_store_ssbo", callee
)) {
3241 param
= param
->get_next();
3242 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3245 param
= param
->get_next();
3246 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3248 dst
.writemask
= write_mask
->value
.u
[0];
3250 dst
.type
= this->result
.type
;
3251 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3253 param
= param
->get_next();
3254 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3257 st_src_reg data
= this->result
, data2
= undef_src
;
3259 if (!strcmp("__intrinsic_atomic_add_ssbo", callee
))
3260 opcode
= TGSI_OPCODE_ATOMUADD
;
3261 else if (!strcmp("__intrinsic_atomic_min_ssbo", callee
))
3262 opcode
= TGSI_OPCODE_ATOMIMIN
;
3263 else if (!strcmp("__intrinsic_atomic_max_ssbo", callee
))
3264 opcode
= TGSI_OPCODE_ATOMIMAX
;
3265 else if (!strcmp("__intrinsic_atomic_and_ssbo", callee
))
3266 opcode
= TGSI_OPCODE_ATOMAND
;
3267 else if (!strcmp("__intrinsic_atomic_or_ssbo", callee
))
3268 opcode
= TGSI_OPCODE_ATOMOR
;
3269 else if (!strcmp("__intrinsic_atomic_xor_ssbo", callee
))
3270 opcode
= TGSI_OPCODE_ATOMXOR
;
3271 else if (!strcmp("__intrinsic_atomic_exchange_ssbo", callee
))
3272 opcode
= TGSI_OPCODE_ATOMXCHG
;
3273 else if (!strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3274 opcode
= TGSI_OPCODE_ATOMCAS
;
3275 param
= param
->get_next();
3276 val
= ((ir_instruction
*)param
)->as_rvalue();
3278 data2
= this->result
;
3280 assert(!"Unexpected intrinsic");
3284 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3287 param
= param
->get_next();
3288 ir_constant
*access
= NULL
;
3289 if (!param
->is_tail_sentinel()) {
3290 access
= ((ir_instruction
*)param
)->as_constant();
3294 /* The emit_asm() might have actually split the op into pieces, e.g. for
3295 * double stores. We have to go back and fix up all the generated ops.
3297 unsigned op
= inst
->op
;
3299 inst
->buffer
= buffer
;
3301 inst
->buffer_access
= access
->value
.u
[0];
3302 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3303 if (inst
->op
== TGSI_OPCODE_UADD
)
3304 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3305 } while (inst
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
&& inst
->op
== op
);
3309 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3311 const char *callee
= ir
->callee
->function_name();
3313 if (!strcmp("__intrinsic_memory_barrier", callee
))
3314 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3315 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3316 TGSI_MEMBAR_ATOMIC_BUFFER
|
3317 TGSI_MEMBAR_SHADER_IMAGE
|
3318 TGSI_MEMBAR_SHARED
));
3319 else if (!strcmp("__intrinsic_memory_barrier_atomic_counter", callee
))
3320 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3321 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3322 else if (!strcmp("__intrinsic_memory_barrier_buffer", callee
))
3323 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3324 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3325 else if (!strcmp("__intrinsic_memory_barrier_image", callee
))
3326 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3327 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3328 else if (!strcmp("__intrinsic_memory_barrier_shared", callee
))
3329 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3330 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3331 else if (!strcmp("__intrinsic_group_memory_barrier", callee
))
3332 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3333 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3334 TGSI_MEMBAR_ATOMIC_BUFFER
|
3335 TGSI_MEMBAR_SHADER_IMAGE
|
3336 TGSI_MEMBAR_SHARED
|
3337 TGSI_MEMBAR_THREAD_GROUP
));
3339 assert(!"Unexpected memory barrier intrinsic");
3343 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3345 const char *callee
= ir
->callee
->function_name();
3346 exec_node
*param
= ir
->actual_parameters
.get_head();
3348 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3350 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3352 /* Calculate the surface offset */
3353 offset
->accept(this);
3354 st_src_reg off
= this->result
;
3356 st_dst_reg dst
= undef_dst
;
3357 if (ir
->return_deref
) {
3358 ir
->return_deref
->accept(this);
3359 dst
= st_dst_reg(this->result
);
3360 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3363 glsl_to_tgsi_instruction
*inst
;
3365 if (!strcmp("__intrinsic_load_shared", callee
)) {
3366 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3367 inst
->buffer
= buffer
;
3368 } else if (!strcmp("__intrinsic_store_shared", callee
)) {
3369 param
= param
->get_next();
3370 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3373 param
= param
->get_next();
3374 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3376 dst
.writemask
= write_mask
->value
.u
[0];
3378 dst
.type
= this->result
.type
;
3379 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3380 inst
->buffer
= buffer
;
3382 param
= param
->get_next();
3383 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3386 st_src_reg data
= this->result
, data2
= undef_src
;
3388 if (!strcmp("__intrinsic_atomic_add_shared", callee
))
3389 opcode
= TGSI_OPCODE_ATOMUADD
;
3390 else if (!strcmp("__intrinsic_atomic_min_shared", callee
))
3391 opcode
= TGSI_OPCODE_ATOMIMIN
;
3392 else if (!strcmp("__intrinsic_atomic_max_shared", callee
))
3393 opcode
= TGSI_OPCODE_ATOMIMAX
;
3394 else if (!strcmp("__intrinsic_atomic_and_shared", callee
))
3395 opcode
= TGSI_OPCODE_ATOMAND
;
3396 else if (!strcmp("__intrinsic_atomic_or_shared", callee
))
3397 opcode
= TGSI_OPCODE_ATOMOR
;
3398 else if (!strcmp("__intrinsic_atomic_xor_shared", callee
))
3399 opcode
= TGSI_OPCODE_ATOMXOR
;
3400 else if (!strcmp("__intrinsic_atomic_exchange_shared", callee
))
3401 opcode
= TGSI_OPCODE_ATOMXCHG
;
3402 else if (!strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3403 opcode
= TGSI_OPCODE_ATOMCAS
;
3404 param
= param
->get_next();
3405 val
= ((ir_instruction
*)param
)->as_rvalue();
3407 data2
= this->result
;
3409 assert(!"Unexpected intrinsic");
3413 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3414 inst
->buffer
= buffer
;
3419 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3421 const char *callee
= ir
->callee
->function_name();
3422 exec_node
*param
= ir
->actual_parameters
.get_head();
3424 ir_dereference
*img
= (ir_dereference
*)param
;
3425 const ir_variable
*imgvar
= img
->variable_referenced();
3426 const glsl_type
*type
= imgvar
->type
->without_array();
3427 unsigned sampler_array_size
= 1, sampler_base
= 0;
3430 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3432 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3433 (unsigned int *)&image
.index
, &reladdr
);
3434 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3435 emit_arl(ir
, sampler_reladdr
, reladdr
);
3436 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3437 memcpy(image
.reladdr
, &sampler_reladdr
, sizeof(reladdr
));
3440 st_dst_reg dst
= undef_dst
;
3441 if (ir
->return_deref
) {
3442 ir
->return_deref
->accept(this);
3443 dst
= st_dst_reg(this->result
);
3444 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3447 glsl_to_tgsi_instruction
*inst
;
3449 if (!strcmp("__intrinsic_image_size", callee
)) {
3450 dst
.writemask
= WRITEMASK_XYZ
;
3451 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3452 } else if (!strcmp("__intrinsic_image_samples", callee
)) {
3453 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3454 st_dst_reg dstres
= st_dst_reg(res
);
3455 dstres
.writemask
= WRITEMASK_W
;
3456 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3457 res
.swizzle
= SWIZZLE_WWWW
;
3458 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3460 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3462 st_dst_reg coord_dst
;
3463 coord
= get_temp(glsl_type::ivec4_type
);
3464 coord_dst
= st_dst_reg(coord
);
3465 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3466 param
= param
->get_next();
3467 ((ir_dereference
*)param
)->accept(this);
3468 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3469 coord
.swizzle
= SWIZZLE_XXXX
;
3470 switch (type
->coordinate_components()) {
3471 case 4: assert(!"unexpected coord count");
3473 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3475 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3478 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3479 param
= param
->get_next();
3480 ((ir_dereference
*)param
)->accept(this);
3481 st_src_reg sample
= this->result
;
3482 sample
.swizzle
= SWIZZLE_XXXX
;
3483 coord_dst
.writemask
= WRITEMASK_W
;
3484 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3485 coord
.swizzle
|= SWIZZLE_W
<< 9;
3488 param
= param
->get_next();
3489 if (!param
->is_tail_sentinel()) {
3490 ((ir_dereference
*)param
)->accept(this);
3491 arg1
= this->result
;
3492 param
= param
->get_next();
3495 if (!param
->is_tail_sentinel()) {
3496 ((ir_dereference
*)param
)->accept(this);
3497 arg2
= this->result
;
3498 param
= param
->get_next();
3501 assert(param
->is_tail_sentinel());
3504 if (!strcmp("__intrinsic_image_load", callee
))
3505 opcode
= TGSI_OPCODE_LOAD
;
3506 else if (!strcmp("__intrinsic_image_store", callee
))
3507 opcode
= TGSI_OPCODE_STORE
;
3508 else if (!strcmp("__intrinsic_image_atomic_add", callee
))
3509 opcode
= TGSI_OPCODE_ATOMUADD
;
3510 else if (!strcmp("__intrinsic_image_atomic_min", callee
))
3511 opcode
= TGSI_OPCODE_ATOMIMIN
;
3512 else if (!strcmp("__intrinsic_image_atomic_max", callee
))
3513 opcode
= TGSI_OPCODE_ATOMIMAX
;
3514 else if (!strcmp("__intrinsic_image_atomic_and", callee
))
3515 opcode
= TGSI_OPCODE_ATOMAND
;
3516 else if (!strcmp("__intrinsic_image_atomic_or", callee
))
3517 opcode
= TGSI_OPCODE_ATOMOR
;
3518 else if (!strcmp("__intrinsic_image_atomic_xor", callee
))
3519 opcode
= TGSI_OPCODE_ATOMXOR
;
3520 else if (!strcmp("__intrinsic_image_atomic_exchange", callee
))
3521 opcode
= TGSI_OPCODE_ATOMXCHG
;
3522 else if (!strcmp("__intrinsic_image_atomic_comp_swap", callee
))
3523 opcode
= TGSI_OPCODE_ATOMCAS
;
3525 assert(!"Unexpected intrinsic");
3529 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3530 if (opcode
== TGSI_OPCODE_STORE
)
3531 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3534 inst
->buffer
= image
;
3535 inst
->sampler_array_size
= sampler_array_size
;
3536 inst
->sampler_base
= sampler_base
;
3538 switch (type
->sampler_dimensionality
) {
3539 case GLSL_SAMPLER_DIM_1D
:
3540 inst
->tex_target
= (type
->sampler_array
)
3541 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3543 case GLSL_SAMPLER_DIM_2D
:
3544 inst
->tex_target
= (type
->sampler_array
)
3545 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3547 case GLSL_SAMPLER_DIM_3D
:
3548 inst
->tex_target
= TEXTURE_3D_INDEX
;
3550 case GLSL_SAMPLER_DIM_CUBE
:
3551 inst
->tex_target
= (type
->sampler_array
)
3552 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3554 case GLSL_SAMPLER_DIM_RECT
:
3555 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3557 case GLSL_SAMPLER_DIM_BUF
:
3558 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3560 case GLSL_SAMPLER_DIM_EXTERNAL
:
3561 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3563 case GLSL_SAMPLER_DIM_MS
:
3564 inst
->tex_target
= (type
->sampler_array
)
3565 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3568 assert(!"Should not get here.");
3571 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3572 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3574 if (imgvar
->data
.image_coherent
)
3575 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3576 if (imgvar
->data
.image_restrict
)
3577 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3578 if (imgvar
->data
.image_volatile
)
3579 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3583 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3585 glsl_to_tgsi_instruction
*call_inst
;
3586 ir_function_signature
*sig
= ir
->callee
;
3587 const char *callee
= sig
->function_name();
3588 function_entry
*entry
;
3591 /* Filter out intrinsics */
3592 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3593 !strcmp("__intrinsic_atomic_increment", callee
) ||
3594 !strcmp("__intrinsic_atomic_predecrement", callee
) ||
3595 !strcmp("__intrinsic_atomic_add", callee
) ||
3596 !strcmp("__intrinsic_atomic_sub", callee
) ||
3597 !strcmp("__intrinsic_atomic_min", callee
) ||
3598 !strcmp("__intrinsic_atomic_max", callee
) ||
3599 !strcmp("__intrinsic_atomic_and", callee
) ||
3600 !strcmp("__intrinsic_atomic_or", callee
) ||
3601 !strcmp("__intrinsic_atomic_xor", callee
) ||
3602 !strcmp("__intrinsic_atomic_exchange", callee
) ||
3603 !strcmp("__intrinsic_atomic_comp_swap", callee
)) {
3604 visit_atomic_counter_intrinsic(ir
);
3608 if (!strcmp("__intrinsic_load_ssbo", callee
) ||
3609 !strcmp("__intrinsic_store_ssbo", callee
) ||
3610 !strcmp("__intrinsic_atomic_add_ssbo", callee
) ||
3611 !strcmp("__intrinsic_atomic_min_ssbo", callee
) ||
3612 !strcmp("__intrinsic_atomic_max_ssbo", callee
) ||
3613 !strcmp("__intrinsic_atomic_and_ssbo", callee
) ||
3614 !strcmp("__intrinsic_atomic_or_ssbo", callee
) ||
3615 !strcmp("__intrinsic_atomic_xor_ssbo", callee
) ||
3616 !strcmp("__intrinsic_atomic_exchange_ssbo", callee
) ||
3617 !strcmp("__intrinsic_atomic_comp_swap_ssbo", callee
)) {
3618 visit_ssbo_intrinsic(ir
);
3622 if (!strcmp("__intrinsic_memory_barrier", callee
) ||
3623 !strcmp("__intrinsic_memory_barrier_atomic_counter", callee
) ||
3624 !strcmp("__intrinsic_memory_barrier_buffer", callee
) ||
3625 !strcmp("__intrinsic_memory_barrier_image", callee
) ||
3626 !strcmp("__intrinsic_memory_barrier_shared", callee
) ||
3627 !strcmp("__intrinsic_group_memory_barrier", callee
)) {
3628 visit_membar_intrinsic(ir
);
3632 if (!strcmp("__intrinsic_load_shared", callee
) ||
3633 !strcmp("__intrinsic_store_shared", callee
) ||
3634 !strcmp("__intrinsic_atomic_add_shared", callee
) ||
3635 !strcmp("__intrinsic_atomic_min_shared", callee
) ||
3636 !strcmp("__intrinsic_atomic_max_shared", callee
) ||
3637 !strcmp("__intrinsic_atomic_and_shared", callee
) ||
3638 !strcmp("__intrinsic_atomic_or_shared", callee
) ||
3639 !strcmp("__intrinsic_atomic_xor_shared", callee
) ||
3640 !strcmp("__intrinsic_atomic_exchange_shared", callee
) ||
3641 !strcmp("__intrinsic_atomic_comp_swap_shared", callee
)) {
3642 visit_shared_intrinsic(ir
);
3646 if (!strcmp("__intrinsic_image_load", callee
) ||
3647 !strcmp("__intrinsic_image_store", callee
) ||
3648 !strcmp("__intrinsic_image_atomic_add", callee
) ||
3649 !strcmp("__intrinsic_image_atomic_min", callee
) ||
3650 !strcmp("__intrinsic_image_atomic_max", callee
) ||
3651 !strcmp("__intrinsic_image_atomic_and", callee
) ||
3652 !strcmp("__intrinsic_image_atomic_or", callee
) ||
3653 !strcmp("__intrinsic_image_atomic_xor", callee
) ||
3654 !strcmp("__intrinsic_image_atomic_exchange", callee
) ||
3655 !strcmp("__intrinsic_image_atomic_comp_swap", callee
) ||
3656 !strcmp("__intrinsic_image_size", callee
) ||
3657 !strcmp("__intrinsic_image_samples", callee
)) {
3658 visit_image_intrinsic(ir
);
3662 entry
= get_function_signature(sig
);
3663 /* Process in parameters. */
3664 foreach_two_lists(formal_node
, &sig
->parameters
,
3665 actual_node
, &ir
->actual_parameters
) {
3666 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3667 ir_variable
*param
= (ir_variable
*) formal_node
;
3669 if (param
->data
.mode
== ir_var_function_in
||
3670 param
->data
.mode
== ir_var_function_inout
) {
3671 variable_storage
*storage
= find_variable_storage(param
);
3674 param_rval
->accept(this);
3675 st_src_reg r
= this->result
;
3678 l
.file
= storage
->file
;
3679 l
.index
= storage
->index
;
3681 l
.writemask
= WRITEMASK_XYZW
;
3683 for (i
= 0; i
< type_size(param
->type
); i
++) {
3684 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3691 /* Emit call instruction */
3692 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3693 call_inst
->function
= entry
;
3695 /* Process out parameters. */
3696 foreach_two_lists(formal_node
, &sig
->parameters
,
3697 actual_node
, &ir
->actual_parameters
) {
3698 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3699 ir_variable
*param
= (ir_variable
*) formal_node
;
3701 if (param
->data
.mode
== ir_var_function_out
||
3702 param
->data
.mode
== ir_var_function_inout
) {
3703 variable_storage
*storage
= find_variable_storage(param
);
3707 r
.file
= storage
->file
;
3708 r
.index
= storage
->index
;
3710 r
.swizzle
= SWIZZLE_NOOP
;
3713 param_rval
->accept(this);
3714 st_dst_reg l
= st_dst_reg(this->result
);
3716 for (i
= 0; i
< type_size(param
->type
); i
++) {
3717 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3724 /* Process return value. */
3725 this->result
= entry
->return_reg
;
3729 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3730 ir_dereference
*tail
,
3731 unsigned *array_elements
,
3734 st_src_reg
*indirect
,
3737 switch (tail
->ir_type
) {
3738 case ir_type_dereference_record
: {
3739 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3740 const glsl_type
*struct_type
= deref_record
->record
->type
;
3741 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3743 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3745 assert(field_index
>= 0);
3746 *location
+= struct_type
->record_location_offset(field_index
);
3750 case ir_type_dereference_array
: {
3751 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3752 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3755 st_src_reg temp_reg
;
3756 st_dst_reg temp_dst
;
3758 temp_reg
= get_temp(glsl_type::uint_type
);
3759 temp_dst
= st_dst_reg(temp_reg
);
3760 temp_dst
.writemask
= 1;
3762 deref_arr
->array_index
->accept(this);
3763 if (*array_elements
!= 1)
3764 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3766 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3768 if (indirect
->file
== PROGRAM_UNDEFINED
)
3769 *indirect
= temp_reg
;
3771 temp_dst
= st_dst_reg(*indirect
);
3772 temp_dst
.writemask
= 1;
3773 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3776 *index
+= array_index
->value
.u
[0] * *array_elements
;
3778 *array_elements
*= deref_arr
->array
->type
->length
;
3780 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3789 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3790 unsigned *array_size
,
3793 st_src_reg
*reladdr
)
3795 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3796 unsigned location
= 0;
3797 ir_variable
*var
= ir
->variable_referenced();
3799 memset(reladdr
, 0, sizeof(*reladdr
));
3800 reladdr
->file
= PROGRAM_UNDEFINED
;
3806 location
= var
->data
.location
;
3807 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3810 * If we end up with no indirect then adjust the base to the index,
3811 * and set the array size to 1.
3813 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3818 if (location
!= 0xffffffff) {
3819 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3820 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
3825 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3827 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3828 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3829 st_src_reg levels_src
, reladdr
;
3830 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3831 glsl_to_tgsi_instruction
*inst
= NULL
;
3832 unsigned opcode
= TGSI_OPCODE_NOP
;
3833 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3834 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
3835 bool is_cube_array
= false;
3838 /* if we are a cube array sampler */
3839 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3840 sampler_type
->sampler_array
)) {
3841 is_cube_array
= true;
3844 if (ir
->coordinate
) {
3845 ir
->coordinate
->accept(this);
3847 /* Put our coords in a temp. We'll need to modify them for shadow,
3848 * projection, or LOD, so the only case we'd use it as is is if
3849 * we're doing plain old texturing. The optimization passes on
3850 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3852 coord
= get_temp(glsl_type::vec4_type
);
3853 coord_dst
= st_dst_reg(coord
);
3854 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3855 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3858 if (ir
->projector
) {
3859 ir
->projector
->accept(this);
3860 projector
= this->result
;
3863 /* Storage for our result. Ideally for an assignment we'd be using
3864 * the actual storage for the result here, instead.
3866 result_src
= get_temp(ir
->type
);
3867 result_dst
= st_dst_reg(result_src
);
3871 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3873 ir
->offset
->accept(this);
3874 offset
[0] = this->result
;
3878 if (is_cube_array
||
3879 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3880 opcode
= TGSI_OPCODE_TXB2
;
3883 opcode
= TGSI_OPCODE_TXB
;
3885 ir
->lod_info
.bias
->accept(this);
3886 lod_info
= this->result
;
3888 ir
->offset
->accept(this);
3889 offset
[0] = this->result
;
3893 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3894 ir
->lod_info
.lod
->accept(this);
3895 lod_info
= this->result
;
3897 ir
->offset
->accept(this);
3898 offset
[0] = this->result
;
3902 opcode
= TGSI_OPCODE_TXD
;
3903 ir
->lod_info
.grad
.dPdx
->accept(this);
3905 ir
->lod_info
.grad
.dPdy
->accept(this);
3908 ir
->offset
->accept(this);
3909 offset
[0] = this->result
;
3913 opcode
= TGSI_OPCODE_TXQ
;
3914 ir
->lod_info
.lod
->accept(this);
3915 lod_info
= this->result
;
3917 case ir_query_levels
:
3918 opcode
= TGSI_OPCODE_TXQ
;
3919 lod_info
= undef_src
;
3920 levels_src
= get_temp(ir
->type
);
3923 opcode
= TGSI_OPCODE_TXF
;
3924 ir
->lod_info
.lod
->accept(this);
3925 lod_info
= this->result
;
3927 ir
->offset
->accept(this);
3928 offset
[0] = this->result
;
3932 opcode
= TGSI_OPCODE_TXF
;
3933 ir
->lod_info
.sample_index
->accept(this);
3934 sample_index
= this->result
;
3937 opcode
= TGSI_OPCODE_TG4
;
3938 ir
->lod_info
.component
->accept(this);
3939 component
= this->result
;
3941 ir
->offset
->accept(this);
3942 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3943 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3944 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3945 offset
[i
] = this->result
;
3946 offset
[i
].index
+= i
* type_size(elt_type
);
3947 offset
[i
].type
= elt_type
->base_type
;
3948 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3951 offset
[0] = this->result
;
3956 opcode
= TGSI_OPCODE_LODQ
;
3958 case ir_texture_samples
:
3959 opcode
= TGSI_OPCODE_TXQS
;
3961 case ir_samples_identical
:
3962 unreachable("Unexpected ir_samples_identical opcode");
3965 if (ir
->projector
) {
3966 if (opcode
== TGSI_OPCODE_TEX
) {
3967 /* Slot the projector in as the last component of the coord. */
3968 coord_dst
.writemask
= WRITEMASK_W
;
3969 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3970 coord_dst
.writemask
= WRITEMASK_XYZW
;
3971 opcode
= TGSI_OPCODE_TXP
;
3973 st_src_reg coord_w
= coord
;
3974 coord_w
.swizzle
= SWIZZLE_WWWW
;
3976 /* For the other TEX opcodes there's no projective version
3977 * since the last slot is taken up by LOD info. Do the
3978 * projective divide now.
3980 coord_dst
.writemask
= WRITEMASK_W
;
3981 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3983 /* In the case where we have to project the coordinates "by hand,"
3984 * the shadow comparator value must also be projected.
3986 st_src_reg tmp_src
= coord
;
3987 if (ir
->shadow_comparitor
) {
3988 /* Slot the shadow value in as the second to last component of the
3991 ir
->shadow_comparitor
->accept(this);
3993 tmp_src
= get_temp(glsl_type::vec4_type
);
3994 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3996 /* Projective division not allowed for array samplers. */
3997 assert(!sampler_type
->sampler_array
);
3999 tmp_dst
.writemask
= WRITEMASK_Z
;
4000 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4002 tmp_dst
.writemask
= WRITEMASK_XY
;
4003 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4006 coord_dst
.writemask
= WRITEMASK_XYZ
;
4007 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4009 coord_dst
.writemask
= WRITEMASK_XYZW
;
4010 coord
.swizzle
= SWIZZLE_XYZW
;
4014 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4015 * comparator was put in the correct place (and projected) by the code,
4016 * above, that handles by-hand projection.
4018 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4019 /* Slot the shadow value in as the second to last component of the
4022 ir
->shadow_comparitor
->accept(this);
4024 if (is_cube_array
) {
4025 cube_sc
= get_temp(glsl_type::float_type
);
4026 cube_sc_dst
= st_dst_reg(cube_sc
);
4027 cube_sc_dst
.writemask
= WRITEMASK_X
;
4028 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4029 cube_sc_dst
.writemask
= WRITEMASK_X
;
4032 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4033 sampler_type
->sampler_array
) ||
4034 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4035 coord_dst
.writemask
= WRITEMASK_W
;
4037 coord_dst
.writemask
= WRITEMASK_Z
;
4039 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4040 coord_dst
.writemask
= WRITEMASK_XYZW
;
4044 if (ir
->op
== ir_txf_ms
) {
4045 coord_dst
.writemask
= WRITEMASK_W
;
4046 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4047 coord_dst
.writemask
= WRITEMASK_XYZW
;
4048 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4049 opcode
== TGSI_OPCODE_TXF
) {
4050 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4051 coord_dst
.writemask
= WRITEMASK_W
;
4052 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4053 coord_dst
.writemask
= WRITEMASK_XYZW
;
4056 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4057 &sampler_index
, &reladdr
);
4058 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4059 emit_arl(ir
, sampler_reladdr
, reladdr
);
4061 if (opcode
== TGSI_OPCODE_TXD
)
4062 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4063 else if (opcode
== TGSI_OPCODE_TXQ
) {
4064 if (ir
->op
== ir_query_levels
) {
4065 /* the level is stored in W */
4066 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4067 result_dst
.writemask
= WRITEMASK_X
;
4068 levels_src
.swizzle
= SWIZZLE_WWWW
;
4069 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4071 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4072 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4073 inst
= emit_asm(ir
, opcode
, result_dst
);
4074 } else if (opcode
== TGSI_OPCODE_TXF
) {
4075 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4076 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4077 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4078 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4079 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4080 } else if (opcode
== TGSI_OPCODE_TG4
) {
4081 if (is_cube_array
&& ir
->shadow_comparitor
) {
4082 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4084 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4087 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4089 if (ir
->shadow_comparitor
)
4090 inst
->tex_shadow
= GL_TRUE
;
4092 inst
->sampler
.index
= sampler_index
;
4093 inst
->sampler_array_size
= sampler_array_size
;
4094 inst
->sampler_base
= sampler_base
;
4096 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4097 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4098 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4102 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4103 inst
->tex_offsets
[i
] = offset
[i
];
4104 inst
->tex_offset_num_offset
= i
;
4107 switch (sampler_type
->sampler_dimensionality
) {
4108 case GLSL_SAMPLER_DIM_1D
:
4109 inst
->tex_target
= (sampler_type
->sampler_array
)
4110 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4112 case GLSL_SAMPLER_DIM_2D
:
4113 inst
->tex_target
= (sampler_type
->sampler_array
)
4114 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4116 case GLSL_SAMPLER_DIM_3D
:
4117 inst
->tex_target
= TEXTURE_3D_INDEX
;
4119 case GLSL_SAMPLER_DIM_CUBE
:
4120 inst
->tex_target
= (sampler_type
->sampler_array
)
4121 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4123 case GLSL_SAMPLER_DIM_RECT
:
4124 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4126 case GLSL_SAMPLER_DIM_BUF
:
4127 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4129 case GLSL_SAMPLER_DIM_EXTERNAL
:
4130 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4132 case GLSL_SAMPLER_DIM_MS
:
4133 inst
->tex_target
= (sampler_type
->sampler_array
)
4134 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4137 assert(!"Should not get here.");
4140 inst
->tex_type
= ir
->type
->base_type
;
4142 this->result
= result_src
;
4146 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4148 if (ir
->get_value()) {
4152 assert(current_function
);
4154 ir
->get_value()->accept(this);
4155 st_src_reg r
= this->result
;
4157 l
= st_dst_reg(current_function
->return_reg
);
4159 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4160 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4166 emit_asm(ir
, TGSI_OPCODE_RET
);
4170 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4172 if (ir
->condition
) {
4173 ir
->condition
->accept(this);
4174 st_src_reg condition
= this->result
;
4176 /* Convert the bool condition to a float so we can negate. */
4177 if (native_integers
) {
4178 st_src_reg temp
= get_temp(ir
->condition
->type
);
4179 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4180 condition
, st_src_reg_for_float(1.0));
4184 condition
.negate
= ~condition
.negate
;
4185 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4187 /* unconditional kil */
4188 emit_asm(ir
, TGSI_OPCODE_KILL
);
4193 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4196 glsl_to_tgsi_instruction
*if_inst
;
4198 ir
->condition
->accept(this);
4199 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4201 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4203 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4205 this->instructions
.push_tail(if_inst
);
4207 visit_exec_list(&ir
->then_instructions
, this);
4209 if (!ir
->else_instructions
.is_empty()) {
4210 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4211 visit_exec_list(&ir
->else_instructions
, this);
4214 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4219 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4221 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4223 ir
->stream
->accept(this);
4224 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4228 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4230 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4232 ir
->stream
->accept(this);
4233 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4237 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4239 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4240 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4242 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4245 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4247 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4249 result
.file
= PROGRAM_UNDEFINED
;
4254 num_input_arrays
= 0;
4255 num_output_arrays
= 0;
4256 next_signature_id
= 1;
4258 current_function
= NULL
;
4259 num_address_regs
= 0;
4263 indirect_addr_consts
= false;
4264 wpos_transform_const
= -1;
4266 native_integers
= false;
4267 mem_ctx
= ralloc_context(NULL
);
4270 shader_program
= NULL
;
4275 use_shared_memory
= false;
4278 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4281 ralloc_free(mem_ctx
);
4284 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4291 * Count resources used by the given gpu program (number of texture
4295 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4297 v
->samplers_used
= 0;
4298 v
->buffers_used
= 0;
4301 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4302 if (inst
->info
->is_tex
) {
4303 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4304 unsigned idx
= inst
->sampler_base
+ i
;
4305 v
->samplers_used
|= 1u << idx
;
4307 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4308 v
->sampler_types
[idx
] = inst
->tex_type
;
4309 v
->sampler_targets
[idx
] =
4310 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4312 if (inst
->tex_shadow
) {
4313 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4317 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4318 is_resource_instruction(inst
->op
) ||
4319 inst
->op
== TGSI_OPCODE_STORE
)) {
4320 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4321 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4322 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4323 v
->use_shared_memory
= true;
4325 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4326 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4327 unsigned idx
= inst
->sampler_base
+ i
;
4328 v
->images_used
|= 1 << idx
;
4329 v
->image_targets
[idx
] =
4330 st_translate_texture_target(inst
->tex_target
, false);
4331 v
->image_formats
[idx
] = inst
->image_format
;
4336 prog
->SamplersUsed
= v
->samplers_used
;
4338 if (v
->shader_program
!= NULL
)
4339 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4343 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4344 * are read from the given src in this instruction
4347 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4349 int read_mask
= 0, comp
;
4351 /* Now, given the src swizzle and the written channels, find which
4352 * components are actually read
4354 for (comp
= 0; comp
< 4; ++comp
) {
4355 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4357 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4358 read_mask
|= 1 << coord
;
4365 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4366 * instruction is the first instruction to write to register T0. There are
4367 * several lowering passes done in GLSL IR (e.g. branches and
4368 * relative addressing) that create a large number of conditional assignments
4369 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4371 * Here is why this conversion is safe:
4372 * CMP T0, T1 T2 T0 can be expanded to:
4378 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4379 * as the original program. If (T1 < 0.0) evaluates to false, executing
4380 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4381 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4382 * because any instruction that was going to read from T0 after this was going
4383 * to read a garbage value anyway.
4386 glsl_to_tgsi_visitor::simplify_cmp(void)
4388 int tempWritesSize
= 0;
4389 unsigned *tempWrites
= NULL
;
4390 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4392 memset(outputWrites
, 0, sizeof(outputWrites
));
4394 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4395 unsigned prevWriteMask
= 0;
4397 /* Give up if we encounter relative addressing or flow control. */
4398 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4399 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4400 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4401 inst
->op
== TGSI_OPCODE_BGNSUB
||
4402 inst
->op
== TGSI_OPCODE_CONT
||
4403 inst
->op
== TGSI_OPCODE_END
||
4404 inst
->op
== TGSI_OPCODE_ENDSUB
||
4405 inst
->op
== TGSI_OPCODE_RET
) {
4409 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4410 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4411 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4412 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4413 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4414 if (inst
->dst
[0].index
>= tempWritesSize
) {
4415 const int inc
= 4096;
4417 tempWrites
= (unsigned*)
4419 (tempWritesSize
+ inc
) * sizeof(unsigned));
4423 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4424 tempWritesSize
+= inc
;
4427 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4428 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4432 /* For a CMP to be considered a conditional write, the destination
4433 * register and source register two must be the same. */
4434 if (inst
->op
== TGSI_OPCODE_CMP
4435 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4436 && inst
->src
[2].file
== inst
->dst
[0].file
4437 && inst
->src
[2].index
== inst
->dst
[0].index
4438 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4440 inst
->op
= TGSI_OPCODE_MOV
;
4441 inst
->src
[0] = inst
->src
[1];
4448 /* Replaces all references to a temporary register index with another index. */
4450 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4452 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4455 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4456 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4457 for (k
= 0; k
< num_renames
; k
++)
4458 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4459 inst
->src
[j
].index
= renames
[k
].new_reg
;
4462 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4463 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4464 for (k
= 0; k
< num_renames
; k
++)
4465 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4466 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4469 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4470 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4471 for (k
= 0; k
< num_renames
; k
++)
4472 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4473 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4479 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4481 int depth
= 0; /* loop depth */
4482 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4485 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4486 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4487 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4488 if (first_reads
[inst
->src
[j
].index
] == -1)
4489 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4492 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4493 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4494 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4495 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4498 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4501 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4511 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4513 int depth
= 0; /* loop depth */
4514 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4517 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4518 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4519 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4520 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4522 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4523 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4524 if (first_writes
[inst
->dst
[j
].index
] == -1)
4525 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4526 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4529 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4530 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4531 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4533 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4536 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4539 for (k
= 0; k
< this->next_temp
; k
++) {
4540 if (last_reads
[k
] == -2) {
4552 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4554 int depth
= 0; /* loop depth */
4558 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4559 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4560 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4561 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4564 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4566 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4568 for (k
= 0; k
< this->next_temp
; k
++) {
4569 if (last_writes
[k
] == -2) {
4580 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4581 * channels for copy propagation and updates following instructions to
4582 * use the original versions.
4584 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4585 * will occur. As an example, a TXP production before this pass:
4587 * 0: MOV TEMP[1], INPUT[4].xyyy;
4588 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4589 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4593 * 0: MOV TEMP[1], INPUT[4].xyyy;
4594 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4595 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4597 * which allows for dead code elimination on TEMP[1]'s writes.
4600 glsl_to_tgsi_visitor::copy_propagate(void)
4602 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4603 glsl_to_tgsi_instruction
*,
4604 this->next_temp
* 4);
4605 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4608 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4609 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4610 || inst
->dst
[0].index
< this->next_temp
);
4612 /* First, do any copy propagation possible into the src regs. */
4613 for (int r
= 0; r
< 3; r
++) {
4614 glsl_to_tgsi_instruction
*first
= NULL
;
4616 int acp_base
= inst
->src
[r
].index
* 4;
4618 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4619 inst
->src
[r
].reladdr
||
4620 inst
->src
[r
].reladdr2
)
4623 /* See if we can find entries in the ACP consisting of MOVs
4624 * from the same src register for all the swizzled channels
4625 * of this src register reference.
4627 for (int i
= 0; i
< 4; i
++) {
4628 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4629 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4636 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4641 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4642 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4643 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4644 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4652 /* We've now validated that we can copy-propagate to
4653 * replace this src register reference. Do it.
4655 inst
->src
[r
].file
= first
->src
[0].file
;
4656 inst
->src
[r
].index
= first
->src
[0].index
;
4657 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4658 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4659 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4660 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4663 for (int i
= 0; i
< 4; i
++) {
4664 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4665 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4666 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4668 inst
->src
[r
].swizzle
= swizzle
;
4673 case TGSI_OPCODE_BGNLOOP
:
4674 case TGSI_OPCODE_ENDLOOP
:
4675 /* End of a basic block, clear the ACP entirely. */
4676 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4679 case TGSI_OPCODE_IF
:
4680 case TGSI_OPCODE_UIF
:
4684 case TGSI_OPCODE_ENDIF
:
4685 case TGSI_OPCODE_ELSE
:
4686 /* Clear all channels written inside the block from the ACP, but
4687 * leaving those that were not touched.
4689 for (int r
= 0; r
< this->next_temp
; r
++) {
4690 for (int c
= 0; c
< 4; c
++) {
4691 if (!acp
[4 * r
+ c
])
4694 if (acp_level
[4 * r
+ c
] >= level
)
4695 acp
[4 * r
+ c
] = NULL
;
4698 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4703 /* Continuing the block, clear any written channels from
4706 for (int d
= 0; d
< 2; d
++) {
4707 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4708 /* Any temporary might be written, so no copy propagation
4709 * across this instruction.
4711 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4712 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4713 inst
->dst
[d
].reladdr
) {
4714 /* Any output might be written, so no copy propagation
4715 * from outputs across this instruction.
4717 for (int r
= 0; r
< this->next_temp
; r
++) {
4718 for (int c
= 0; c
< 4; c
++) {
4719 if (!acp
[4 * r
+ c
])
4722 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4723 acp
[4 * r
+ c
] = NULL
;
4726 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4727 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4728 /* Clear where it's used as dst. */
4729 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4730 for (int c
= 0; c
< 4; c
++) {
4731 if (inst
->dst
[d
].writemask
& (1 << c
))
4732 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4736 /* Clear where it's used as src. */
4737 for (int r
= 0; r
< this->next_temp
; r
++) {
4738 for (int c
= 0; c
< 4; c
++) {
4739 if (!acp
[4 * r
+ c
])
4742 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4744 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4745 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4746 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4747 acp
[4 * r
+ c
] = NULL
;
4756 /* If this is a copy, add it to the ACP. */
4757 if (inst
->op
== TGSI_OPCODE_MOV
&&
4758 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4759 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4760 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4761 !inst
->dst
[0].reladdr
&&
4762 !inst
->dst
[0].reladdr2
&&
4764 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4765 !inst
->src
[0].reladdr
&&
4766 !inst
->src
[0].reladdr2
&&
4767 !inst
->src
[0].negate
) {
4768 for (int i
= 0; i
< 4; i
++) {
4769 if (inst
->dst
[0].writemask
& (1 << i
)) {
4770 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4771 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4777 ralloc_free(acp_level
);
4782 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4785 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4786 * will occur. As an example, a TXP production after copy propagation but
4789 * 0: MOV TEMP[1], INPUT[4].xyyy;
4790 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4791 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4793 * and after this pass:
4795 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4798 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4800 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4801 glsl_to_tgsi_instruction
*,
4802 this->next_temp
* 4);
4803 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4807 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4808 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4809 || inst
->dst
[0].index
< this->next_temp
);
4812 case TGSI_OPCODE_BGNLOOP
:
4813 case TGSI_OPCODE_ENDLOOP
:
4814 case TGSI_OPCODE_CONT
:
4815 case TGSI_OPCODE_BRK
:
4816 /* End of a basic block, clear the write array entirely.
4818 * This keeps us from killing dead code when the writes are
4819 * on either side of a loop, even when the register isn't touched
4820 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4821 * dead code of this type, so it shouldn't make a difference as long as
4822 * the dead code elimination pass in the GLSL compiler does its job.
4824 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4827 case TGSI_OPCODE_ENDIF
:
4828 case TGSI_OPCODE_ELSE
:
4829 /* Promote the recorded level of all channels written inside the
4830 * preceding if or else block to the level above the if/else block.
4832 for (int r
= 0; r
< this->next_temp
; r
++) {
4833 for (int c
= 0; c
< 4; c
++) {
4834 if (!writes
[4 * r
+ c
])
4837 if (write_level
[4 * r
+ c
] == level
)
4838 write_level
[4 * r
+ c
] = level
-1;
4841 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4845 case TGSI_OPCODE_IF
:
4846 case TGSI_OPCODE_UIF
:
4848 /* fallthrough to default case to mark the condition as read */
4850 /* Continuing the block, clear any channels from the write array that
4851 * are read by this instruction.
4853 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4854 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4855 /* Any temporary might be read, so no dead code elimination
4856 * across this instruction.
4858 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4859 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4860 /* Clear where it's used as src. */
4861 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4862 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4863 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4864 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4866 for (int c
= 0; c
< 4; c
++) {
4867 if (src_chans
& (1 << c
))
4868 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4872 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4873 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4874 /* Any temporary might be read, so no dead code elimination
4875 * across this instruction.
4877 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4878 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4879 /* Clear where it's used as src. */
4880 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4881 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4882 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4883 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4885 for (int c
= 0; c
< 4; c
++) {
4886 if (src_chans
& (1 << c
))
4887 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4894 /* If this instruction writes to a temporary, add it to the write array.
4895 * If there is already an instruction in the write array for one or more
4896 * of the channels, flag that channel write as dead.
4898 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4899 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4900 !inst
->dst
[i
].reladdr
) {
4901 for (int c
= 0; c
< 4; c
++) {
4902 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4903 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4904 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4907 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4909 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4910 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4917 /* Anything still in the write array at this point is dead code. */
4918 for (int r
= 0; r
< this->next_temp
; r
++) {
4919 for (int c
= 0; c
< 4; c
++) {
4920 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4922 inst
->dead_mask
|= (1 << c
);
4926 /* Now actually remove the instructions that are completely dead and update
4927 * the writemask of other instructions with dead channels.
4929 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4930 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4932 /* No amount of dead masks should remove memory stores */
4933 if (inst
->info
->is_store
)
4936 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4941 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4942 if (inst
->dead_mask
== WRITEMASK_XY
||
4943 inst
->dead_mask
== WRITEMASK_ZW
)
4944 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4946 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4950 ralloc_free(write_level
);
4951 ralloc_free(writes
);
4956 /* merge DFRACEXP instructions into one. */
4958 glsl_to_tgsi_visitor::merge_two_dsts(void)
4960 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4961 glsl_to_tgsi_instruction
*inst2
;
4963 if (num_inst_dst_regs(inst
) != 2)
4966 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4967 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4970 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4973 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4974 inst
->src
[0].index
== inst2
->src
[0].index
&&
4975 inst
->src
[0].type
== inst2
->src
[0].type
&&
4976 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4978 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4984 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4986 inst
->dst
[0] = inst2
->dst
[0];
4987 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4988 inst
->dst
[1] = inst2
->dst
[1];
4999 /* Merges temporary registers together where possible to reduce the number of
5000 * registers needed to run a program.
5002 * Produces optimal code only after copy propagation and dead code elimination
5005 glsl_to_tgsi_visitor::merge_registers(void)
5007 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5008 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5009 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5011 int num_renames
= 0;
5013 /* Read the indices of the last read and first write to each temp register
5014 * into an array so that we don't have to traverse the instruction list as
5016 for (i
= 0; i
< this->next_temp
; i
++) {
5018 first_writes
[i
] = -1;
5020 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5022 /* Start looking for registers with non-overlapping usages that can be
5023 * merged together. */
5024 for (i
= 0; i
< this->next_temp
; i
++) {
5025 /* Don't touch unused registers. */
5026 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5028 for (j
= 0; j
< this->next_temp
; j
++) {
5029 /* Don't touch unused registers. */
5030 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5032 /* We can merge the two registers if the first write to j is after or
5033 * in the same instruction as the last read from i. Note that the
5034 * register at index i will always be used earlier or at the same time
5035 * as the register at index j. */
5036 if (first_writes
[i
] <= first_writes
[j
] &&
5037 last_reads
[i
] <= first_writes
[j
]) {
5038 renames
[num_renames
].old_reg
= j
;
5039 renames
[num_renames
].new_reg
= i
;
5042 /* Update the first_writes and last_reads arrays with the new
5043 * values for the merged register index, and mark the newly unused
5044 * register index as such. */
5045 assert(last_reads
[j
] >= last_reads
[i
]);
5046 last_reads
[i
] = last_reads
[j
];
5047 first_writes
[j
] = -1;
5053 rename_temp_registers(num_renames
, renames
);
5054 ralloc_free(renames
);
5055 ralloc_free(last_reads
);
5056 ralloc_free(first_writes
);
5059 /* Reassign indices to temporary registers by reusing unused indices created
5060 * by optimization passes. */
5062 glsl_to_tgsi_visitor::renumber_registers(void)
5066 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5067 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5068 int num_renames
= 0;
5069 for (i
= 0; i
< this->next_temp
; i
++) {
5070 first_reads
[i
] = -1;
5072 get_first_temp_read(first_reads
);
5074 for (i
= 0; i
< this->next_temp
; i
++) {
5075 if (first_reads
[i
] < 0) continue;
5076 if (i
!= new_index
) {
5077 renames
[num_renames
].old_reg
= i
;
5078 renames
[num_renames
].new_reg
= new_index
;
5084 rename_temp_registers(num_renames
, renames
);
5085 this->next_temp
= new_index
;
5086 ralloc_free(renames
);
5087 ralloc_free(first_reads
);
5090 /* ------------------------- TGSI conversion stuff -------------------------- */
5092 unsigned branch_target
;
5097 * Intermediate state used during shader translation.
5099 struct st_translate
{
5100 struct ureg_program
*ureg
;
5102 unsigned temps_size
;
5103 struct ureg_dst
*temps
;
5105 struct ureg_dst
*arrays
;
5106 unsigned num_temp_arrays
;
5107 struct ureg_src
*constants
;
5109 struct ureg_src
*immediates
;
5111 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5112 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5113 struct ureg_dst address
[3];
5114 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5115 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5116 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5117 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5118 struct ureg_src shared_memory
;
5119 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5120 unsigned *array_sizes
;
5121 struct array_decl
*input_arrays
;
5122 struct array_decl
*output_arrays
;
5124 const GLuint
*inputMapping
;
5125 const GLuint
*outputMapping
;
5127 /* For every instruction that contains a label (eg CALL), keep
5128 * details so that we can go back afterwards and emit the correct
5129 * tgsi instruction number for each label.
5131 struct label
*labels
;
5132 unsigned labels_size
;
5133 unsigned labels_count
;
5135 /* Keep a record of the tgsi instruction number that each mesa
5136 * instruction starts at, will be used to fix up labels after
5141 unsigned insn_count
;
5143 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5148 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5150 _mesa_sysval_to_semantic(unsigned sysval
)
5154 case SYSTEM_VALUE_VERTEX_ID
:
5155 return TGSI_SEMANTIC_VERTEXID
;
5156 case SYSTEM_VALUE_INSTANCE_ID
:
5157 return TGSI_SEMANTIC_INSTANCEID
;
5158 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5159 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5160 case SYSTEM_VALUE_BASE_VERTEX
:
5161 return TGSI_SEMANTIC_BASEVERTEX
;
5162 case SYSTEM_VALUE_BASE_INSTANCE
:
5163 return TGSI_SEMANTIC_BASEINSTANCE
;
5164 case SYSTEM_VALUE_DRAW_ID
:
5165 return TGSI_SEMANTIC_DRAWID
;
5167 /* Geometry shader */
5168 case SYSTEM_VALUE_INVOCATION_ID
:
5169 return TGSI_SEMANTIC_INVOCATIONID
;
5171 /* Fragment shader */
5172 case SYSTEM_VALUE_FRAG_COORD
:
5173 return TGSI_SEMANTIC_POSITION
;
5174 case SYSTEM_VALUE_FRONT_FACE
:
5175 return TGSI_SEMANTIC_FACE
;
5176 case SYSTEM_VALUE_SAMPLE_ID
:
5177 return TGSI_SEMANTIC_SAMPLEID
;
5178 case SYSTEM_VALUE_SAMPLE_POS
:
5179 return TGSI_SEMANTIC_SAMPLEPOS
;
5180 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5181 return TGSI_SEMANTIC_SAMPLEMASK
;
5182 case SYSTEM_VALUE_HELPER_INVOCATION
:
5183 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5185 /* Tessellation shader */
5186 case SYSTEM_VALUE_TESS_COORD
:
5187 return TGSI_SEMANTIC_TESSCOORD
;
5188 case SYSTEM_VALUE_VERTICES_IN
:
5189 return TGSI_SEMANTIC_VERTICESIN
;
5190 case SYSTEM_VALUE_PRIMITIVE_ID
:
5191 return TGSI_SEMANTIC_PRIMID
;
5192 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5193 return TGSI_SEMANTIC_TESSOUTER
;
5194 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5195 return TGSI_SEMANTIC_TESSINNER
;
5197 /* Compute shader */
5198 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5199 return TGSI_SEMANTIC_THREAD_ID
;
5200 case SYSTEM_VALUE_WORK_GROUP_ID
:
5201 return TGSI_SEMANTIC_BLOCK_ID
;
5202 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5203 return TGSI_SEMANTIC_GRID_SIZE
;
5206 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5207 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5208 case SYSTEM_VALUE_VERTEX_CNT
:
5210 assert(!"Unexpected SYSTEM_VALUE_ enum");
5211 return TGSI_SEMANTIC_COUNT
;
5217 * Make note of a branch to a label in the TGSI code.
5218 * After we've emitted all instructions, we'll go over the list
5219 * of labels built here and patch the TGSI code with the actual
5220 * location of each label.
5222 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5226 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5227 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5228 t
->labels
= (struct label
*)realloc(t
->labels
,
5229 t
->labels_size
* sizeof(struct label
));
5230 if (t
->labels
== NULL
) {
5231 static unsigned dummy
;
5237 i
= t
->labels_count
++;
5238 t
->labels
[i
].branch_target
= branch_target
;
5239 return &t
->labels
[i
].token
;
5243 * Called prior to emitting the TGSI code for each instruction.
5244 * Allocate additional space for instructions if needed.
5245 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5246 * the next TGSI instruction.
5248 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5250 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5251 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5252 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5253 if (t
->insn
== NULL
) {
5259 t
->insn
[t
->insn_count
++] = start
;
5263 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5265 static struct ureg_src
5266 emit_immediate(struct st_translate
*t
,
5267 gl_constant_value values
[4],
5270 struct ureg_program
*ureg
= t
->ureg
;
5275 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5277 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5279 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5280 case GL_UNSIGNED_INT
:
5282 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5284 assert(!"should not get here - type must be float, int, uint, or bool");
5285 return ureg_src_undef();
5290 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5292 static struct ureg_dst
5293 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5299 case PROGRAM_UNDEFINED
:
5300 return ureg_dst_undef();
5302 case PROGRAM_TEMPORARY
:
5303 /* Allocate space for temporaries on demand. */
5304 if (index
>= t
->temps_size
) {
5305 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5307 t
->temps
= (struct ureg_dst
*)
5309 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5311 return ureg_dst_undef();
5313 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5314 t
->temps_size
+= inc
;
5317 if (ureg_dst_is_undef(t
->temps
[index
]))
5318 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5320 return t
->temps
[index
];
5323 array
= index
>> 16;
5325 assert(array
< t
->num_temp_arrays
);
5327 if (ureg_dst_is_undef(t
->arrays
[array
]))
5328 t
->arrays
[array
] = ureg_DECL_array_temporary(
5329 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5331 return ureg_dst_array_offset(t
->arrays
[array
],
5332 (int)(index
& 0xFFFF) - 0x8000);
5334 case PROGRAM_OUTPUT
:
5336 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5337 assert(index
< FRAG_RESULT_MAX
);
5338 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5339 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5340 assert(index
< VARYING_SLOT_TESS_MAX
);
5342 assert(index
< VARYING_SLOT_MAX
);
5344 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5345 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5346 return t
->outputs
[t
->outputMapping
[index
]];
5349 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
5350 unsigned mesa_index
= decl
->mesa_index
;
5351 int slot
= t
->outputMapping
[mesa_index
];
5353 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5354 assert(t
->outputs
[slot
].ArrayID
== array_id
);
5355 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
5358 case PROGRAM_ADDRESS
:
5359 return t
->address
[index
];
5362 assert(!"unknown dst register file");
5363 return ureg_dst_undef();
5368 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5370 static struct ureg_src
5371 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5373 int index
= reg
->index
;
5374 int double_reg2
= reg
->double_reg2
? 1 : 0;
5377 case PROGRAM_UNDEFINED
:
5378 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5380 case PROGRAM_TEMPORARY
:
5382 case PROGRAM_OUTPUT
:
5383 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5385 case PROGRAM_UNIFORM
:
5386 assert(reg
->index
>= 0);
5387 return reg
->index
< t
->num_constants
?
5388 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5389 case PROGRAM_STATE_VAR
:
5390 case PROGRAM_CONSTANT
: /* ie, immediate */
5391 if (reg
->has_index2
)
5392 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5394 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5395 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5397 case PROGRAM_IMMEDIATE
:
5398 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5399 return t
->immediates
[reg
->index
];
5402 /* GLSL inputs are 64-bit containers, so we have to
5403 * map back to the original index and add the offset after
5405 index
-= double_reg2
;
5406 if (!reg
->array_id
) {
5407 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5408 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5409 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5412 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
5413 unsigned mesa_index
= decl
->mesa_index
;
5414 int slot
= t
->inputMapping
[mesa_index
];
5416 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5417 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
5418 return ureg_src_array_offset(t
->inputs
[slot
], index
+ double_reg2
- mesa_index
);
5421 case PROGRAM_ADDRESS
:
5422 return ureg_src(t
->address
[reg
->index
]);
5424 case PROGRAM_SYSTEM_VALUE
:
5425 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5426 return t
->systemValues
[reg
->index
];
5429 assert(!"unknown src register file");
5430 return ureg_src_undef();
5435 * Create a TGSI ureg_dst register from an st_dst_reg.
5437 static struct ureg_dst
5438 translate_dst(struct st_translate
*t
,
5439 const st_dst_reg
*dst_reg
,
5442 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5445 if (dst
.File
== TGSI_FILE_NULL
)
5448 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5451 dst
= ureg_saturate(dst
);
5453 if (dst_reg
->reladdr
!= NULL
) {
5454 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5455 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5458 if (dst_reg
->has_index2
) {
5459 if (dst_reg
->reladdr2
)
5460 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5463 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5470 * Create a TGSI ureg_src register from an st_src_reg.
5472 static struct ureg_src
5473 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5475 struct ureg_src src
= src_register(t
, src_reg
);
5477 if (src_reg
->has_index2
) {
5478 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5479 * and UBO constant buffers (buffer, position).
5481 if (src_reg
->reladdr2
)
5482 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5485 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5488 src
= ureg_swizzle(src
,
5489 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5490 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5491 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5492 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5494 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5495 src
= ureg_negate(src
);
5497 if (src_reg
->reladdr
!= NULL
) {
5498 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5499 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5505 static struct tgsi_texture_offset
5506 translate_tex_offset(struct st_translate
*t
,
5507 const st_src_reg
*in_offset
, int idx
)
5509 struct tgsi_texture_offset offset
;
5510 struct ureg_src imm_src
;
5511 struct ureg_dst dst
;
5514 switch (in_offset
->file
) {
5515 case PROGRAM_IMMEDIATE
:
5516 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
5517 imm_src
= t
->immediates
[in_offset
->index
];
5519 offset
.File
= imm_src
.File
;
5520 offset
.Index
= imm_src
.Index
;
5521 offset
.SwizzleX
= imm_src
.SwizzleX
;
5522 offset
.SwizzleY
= imm_src
.SwizzleY
;
5523 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
5527 imm_src
= t
->inputs
[t
->inputMapping
[in_offset
->index
]];
5528 offset
.File
= imm_src
.File
;
5529 offset
.Index
= imm_src
.Index
;
5530 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5531 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5532 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5535 case PROGRAM_TEMPORARY
:
5536 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
5537 offset
.File
= imm_src
.File
;
5538 offset
.Index
= imm_src
.Index
;
5539 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5540 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5541 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5545 array
= in_offset
->index
>> 16;
5548 assert(array
< (int)t
->num_temp_arrays
);
5550 dst
= t
->arrays
[array
];
5551 offset
.File
= dst
.File
;
5552 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
5553 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
5554 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
5555 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
5565 compile_tgsi_instruction(struct st_translate
*t
,
5566 const glsl_to_tgsi_instruction
*inst
)
5568 struct ureg_program
*ureg
= t
->ureg
;
5570 struct ureg_dst dst
[2];
5571 struct ureg_src src
[4];
5572 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5576 unsigned tex_target
= 0;
5578 num_dst
= num_inst_dst_regs(inst
);
5579 num_src
= num_inst_src_regs(inst
);
5581 for (i
= 0; i
< num_dst
; i
++)
5582 dst
[i
] = translate_dst(t
,
5586 for (i
= 0; i
< num_src
; i
++)
5587 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5590 case TGSI_OPCODE_BGNLOOP
:
5591 case TGSI_OPCODE_CAL
:
5592 case TGSI_OPCODE_ELSE
:
5593 case TGSI_OPCODE_ENDLOOP
:
5594 case TGSI_OPCODE_IF
:
5595 case TGSI_OPCODE_UIF
:
5596 assert(num_dst
== 0);
5597 ureg_label_insn(ureg
,
5601 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5604 case TGSI_OPCODE_TEX
:
5605 case TGSI_OPCODE_TXB
:
5606 case TGSI_OPCODE_TXD
:
5607 case TGSI_OPCODE_TXL
:
5608 case TGSI_OPCODE_TXP
:
5609 case TGSI_OPCODE_TXQ
:
5610 case TGSI_OPCODE_TXQS
:
5611 case TGSI_OPCODE_TXF
:
5612 case TGSI_OPCODE_TEX2
:
5613 case TGSI_OPCODE_TXB2
:
5614 case TGSI_OPCODE_TXL2
:
5615 case TGSI_OPCODE_TG4
:
5616 case TGSI_OPCODE_LODQ
:
5617 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5618 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5619 if (inst
->sampler
.reladdr
)
5621 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5623 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5624 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5626 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5632 texoffsets
, inst
->tex_offset_num_offset
,
5636 case TGSI_OPCODE_RESQ
:
5637 case TGSI_OPCODE_LOAD
:
5638 case TGSI_OPCODE_ATOMUADD
:
5639 case TGSI_OPCODE_ATOMXCHG
:
5640 case TGSI_OPCODE_ATOMCAS
:
5641 case TGSI_OPCODE_ATOMAND
:
5642 case TGSI_OPCODE_ATOMOR
:
5643 case TGSI_OPCODE_ATOMXOR
:
5644 case TGSI_OPCODE_ATOMUMIN
:
5645 case TGSI_OPCODE_ATOMUMAX
:
5646 case TGSI_OPCODE_ATOMIMIN
:
5647 case TGSI_OPCODE_ATOMIMAX
:
5648 for (i
= num_src
- 1; i
>= 0; i
--)
5649 src
[i
+ 1] = src
[i
];
5651 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5652 src
[0] = t
->shared_memory
;
5653 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5654 src
[0] = t
->buffers
[inst
->buffer
.index
];
5656 src
[0] = t
->images
[inst
->buffer
.index
];
5657 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5659 if (inst
->buffer
.reladdr
)
5660 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5661 assert(src
[0].File
!= TGSI_FILE_NULL
);
5662 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5663 inst
->buffer_access
,
5664 tex_target
, inst
->image_format
);
5667 case TGSI_OPCODE_STORE
:
5668 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5669 dst
[0] = ureg_dst(t
->shared_memory
);
5670 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5671 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5673 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5674 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5676 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5677 if (inst
->buffer
.reladdr
)
5678 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5679 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5680 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5681 inst
->buffer_access
,
5682 tex_target
, inst
->image_format
);
5685 case TGSI_OPCODE_SCS
:
5686 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5687 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5700 * Emit the TGSI instructions for inverting and adjusting WPOS.
5701 * This code is unavoidable because it also depends on whether
5702 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5705 emit_wpos_adjustment(struct gl_context
*ctx
,
5706 struct st_translate
*t
,
5707 int wpos_transform_const
,
5709 GLfloat adjX
, GLfloat adjY
[2])
5711 struct ureg_program
*ureg
= t
->ureg
;
5713 assert(wpos_transform_const
>= 0);
5715 /* Fragment program uses fragment position input.
5716 * Need to replace instances of INPUT[WPOS] with temp T
5717 * where T = INPUT[WPOS] is inverted by Y.
5719 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5720 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5721 struct ureg_src
*wpos
=
5722 ctx
->Const
.GLSLFragCoordIsSysVal
?
5723 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5724 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5725 struct ureg_src wpos_input
= *wpos
;
5727 /* First, apply the coordinate shift: */
5728 if (adjX
|| adjY
[0] || adjY
[1]) {
5729 if (adjY
[0] != adjY
[1]) {
5730 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5731 * depending on whether inversion is actually going to be applied
5732 * or not, which is determined by testing against the inversion
5733 * state variable used below, which will be either +1 or -1.
5735 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5737 ureg_CMP(ureg
, adj_temp
,
5738 ureg_scalar(wpostrans
, invert
? 2 : 0),
5739 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5740 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5741 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5743 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5744 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5746 wpos_input
= ureg_src(wpos_temp
);
5748 /* MOV wpos_temp, input[wpos]
5750 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5753 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5754 * inversion/identity, or the other way around if we're drawing to an FBO.
5757 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5760 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5762 ureg_scalar(wpostrans
, 0),
5763 ureg_scalar(wpostrans
, 1));
5765 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5768 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5770 ureg_scalar(wpostrans
, 2),
5771 ureg_scalar(wpostrans
, 3));
5774 /* Use wpos_temp as position input from here on:
5776 *wpos
= ureg_src(wpos_temp
);
5781 * Emit fragment position/ooordinate code.
5784 emit_wpos(struct st_context
*st
,
5785 struct st_translate
*t
,
5786 const struct gl_program
*program
,
5787 struct ureg_program
*ureg
,
5788 int wpos_transform_const
)
5790 const struct gl_fragment_program
*fp
=
5791 (const struct gl_fragment_program
*) program
;
5792 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5793 GLfloat adjX
= 0.0f
;
5794 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5795 boolean invert
= FALSE
;
5797 /* Query the pixel center conventions supported by the pipe driver and set
5798 * adjX, adjY to help out if it cannot handle the requested one internally.
5800 * The bias of the y-coordinate depends on whether y-inversion takes place
5801 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5802 * drawing to an FBO (causes additional inversion), and whether the the pipe
5803 * driver origin and the requested origin differ (the latter condition is
5804 * stored in the 'invert' variable).
5806 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5808 * center shift only:
5813 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5814 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5815 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5816 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5818 * inversion and center shift:
5819 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5820 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5821 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5822 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5824 if (fp
->OriginUpperLeft
) {
5825 /* Fragment shader wants origin in upper-left */
5826 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5827 /* the driver supports upper-left origin */
5829 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5830 /* the driver supports lower-left origin, need to invert Y */
5831 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5832 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5839 /* Fragment shader wants origin in lower-left */
5840 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5841 /* the driver supports lower-left origin */
5842 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5843 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5844 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5845 /* the driver supports upper-left origin, need to invert Y */
5851 if (fp
->PixelCenterInteger
) {
5852 /* Fragment shader wants pixel center integer */
5853 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5854 /* the driver supports pixel center integer */
5856 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5857 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5859 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5860 /* the driver supports pixel center half integer, need to bias X,Y */
5869 /* Fragment shader wants pixel center half integer */
5870 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5871 /* the driver supports pixel center half integer */
5873 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5874 /* the driver supports pixel center integer, need to bias X,Y */
5875 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5876 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5877 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5883 /* we invert after adjustment so that we avoid the MOV to temporary,
5884 * and reuse the adjustment ADD instead */
5885 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5889 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5890 * TGSI uses +1 for front, -1 for back.
5891 * This function converts the TGSI value to the GL value. Simply clamping/
5892 * saturating the value to [0,1] does the job.
5895 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5897 struct ureg_program
*ureg
= t
->ureg
;
5898 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5899 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5901 if (ctx
->Const
.NativeIntegers
) {
5902 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5905 /* MOV_SAT face_temp, input[face] */
5906 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5909 /* Use face_temp as face input from here on: */
5910 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5914 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5915 unsigned *array_id
, unsigned *array_size
)
5919 for (i
= 0; i
< count
; i
++) {
5920 struct array_decl
*decl
= &arrays
[i
];
5922 if (attr
== decl
->mesa_index
) {
5923 *array_id
= decl
->array_id
;
5924 *array_size
= decl
->array_size
;
5925 assert(*array_size
);
5933 emit_compute_block_size(const struct gl_program
*program
,
5934 struct ureg_program
*ureg
) {
5935 const struct gl_compute_program
*cp
=
5936 (const struct gl_compute_program
*)program
;
5938 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5940 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
5942 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
5947 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5948 * \param program the program to translate
5949 * \param numInputs number of input registers used
5950 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5952 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5953 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5955 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5956 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5957 * \param numOutputs number of output registers used
5958 * \param outputMapping maps Mesa fragment program outputs to TGSI
5960 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5961 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5964 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5966 extern "C" enum pipe_error
5967 st_translate_program(
5968 struct gl_context
*ctx
,
5970 struct ureg_program
*ureg
,
5971 glsl_to_tgsi_visitor
*program
,
5972 const struct gl_program
*proginfo
,
5974 const GLuint inputMapping
[],
5975 const GLuint inputSlotToAttr
[],
5976 const ubyte inputSemanticName
[],
5977 const ubyte inputSemanticIndex
[],
5978 const GLuint interpMode
[],
5979 const GLuint interpLocation
[],
5981 const GLuint outputMapping
[],
5982 const GLuint outputSlotToAttr
[],
5983 const ubyte outputSemanticName
[],
5984 const ubyte outputSemanticIndex
[])
5986 struct st_translate
*t
;
5988 struct gl_program_constants
*frag_const
=
5989 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
5990 enum pipe_error ret
= PIPE_OK
;
5992 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5993 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5995 t
= CALLOC_STRUCT(st_translate
);
5997 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6001 t
->procType
= procType
;
6002 t
->inputMapping
= inputMapping
;
6003 t
->outputMapping
= outputMapping
;
6005 t
->num_temp_arrays
= program
->next_array
;
6006 if (t
->num_temp_arrays
)
6007 t
->arrays
= (struct ureg_dst
*)
6008 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
6011 * Declare input attributes.
6014 case PIPE_SHADER_FRAGMENT
:
6015 for (i
= 0; i
< numInputs
; i
++) {
6016 unsigned array_id
= 0;
6017 unsigned array_size
;
6019 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6020 program
->num_input_arrays
, &array_id
, &array_size
)) {
6021 /* We've found an array. Declare it so. */
6022 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6023 inputSemanticName
[i
], inputSemanticIndex
[i
],
6024 interpMode
[i
], 0, interpLocation
[i
],
6025 array_id
, array_size
);
6026 i
+= array_size
- 1;
6029 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
6030 inputSemanticName
[i
], inputSemanticIndex
[i
],
6031 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
6035 case PIPE_SHADER_GEOMETRY
:
6036 case PIPE_SHADER_TESS_EVAL
:
6037 case PIPE_SHADER_TESS_CTRL
:
6038 for (i
= 0; i
< numInputs
; i
++) {
6039 unsigned array_id
= 0;
6040 unsigned array_size
;
6042 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
6043 program
->num_input_arrays
, &array_id
, &array_size
)) {
6044 /* We've found an array. Declare it so. */
6045 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6046 inputSemanticIndex
[i
],
6047 array_id
, array_size
);
6048 i
+= array_size
- 1;
6051 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
6052 inputSemanticIndex
[i
], 0, 1);
6056 case PIPE_SHADER_VERTEX
:
6057 for (i
= 0; i
< numInputs
; i
++) {
6058 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6061 case PIPE_SHADER_COMPUTE
:
6068 * Declare output attributes.
6071 case PIPE_SHADER_FRAGMENT
:
6072 case PIPE_SHADER_COMPUTE
:
6074 case PIPE_SHADER_GEOMETRY
:
6075 case PIPE_SHADER_TESS_EVAL
:
6076 case PIPE_SHADER_TESS_CTRL
:
6077 case PIPE_SHADER_VERTEX
:
6078 for (i
= 0; i
< numOutputs
; i
++) {
6079 unsigned array_id
= 0;
6080 unsigned array_size
;
6082 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
6083 program
->num_output_arrays
, &array_id
, &array_size
)) {
6084 /* We've found an array. Declare it so. */
6085 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
6086 outputSemanticName
[i
],
6087 outputSemanticIndex
[i
],
6088 array_id
, array_size
);
6089 i
+= array_size
- 1;
6092 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6093 outputSemanticName
[i
],
6094 outputSemanticIndex
[i
]);
6102 if (procType
== PIPE_SHADER_FRAGMENT
) {
6103 if (program
->shader
->EarlyFragmentTests
)
6104 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6106 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6107 /* Must do this after setting up t->inputs. */
6108 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6109 program
->wpos_transform_const
);
6112 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6113 emit_face_var(ctx
, t
);
6115 for (i
= 0; i
< numOutputs
; i
++) {
6116 switch (outputSemanticName
[i
]) {
6117 case TGSI_SEMANTIC_POSITION
:
6118 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6119 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6120 outputSemanticIndex
[i
]);
6121 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6123 case TGSI_SEMANTIC_STENCIL
:
6124 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6125 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6126 outputSemanticIndex
[i
]);
6127 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6129 case TGSI_SEMANTIC_COLOR
:
6130 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6131 TGSI_SEMANTIC_COLOR
,
6132 outputSemanticIndex
[i
]);
6134 case TGSI_SEMANTIC_SAMPLEMASK
:
6135 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6136 TGSI_SEMANTIC_SAMPLEMASK
,
6137 outputSemanticIndex
[i
]);
6138 /* TODO: If we ever support more than 32 samples, this will have
6139 * to become an array.
6141 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6144 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6145 ret
= PIPE_ERROR_BAD_INPUT
;
6150 else if (procType
== PIPE_SHADER_VERTEX
) {
6151 for (i
= 0; i
< numOutputs
; i
++) {
6152 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6153 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6155 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6156 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6157 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6162 if (procType
== PIPE_SHADER_COMPUTE
) {
6163 emit_compute_block_size(proginfo
, ureg
);
6166 /* Declare address register.
6168 if (program
->num_address_regs
> 0) {
6169 assert(program
->num_address_regs
<= 3);
6170 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6171 t
->address
[i
] = ureg_DECL_address(ureg
);
6174 /* Declare misc input registers
6177 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6179 for (i
= 0; sysInputs
; i
++) {
6180 if (sysInputs
& (1 << i
)) {
6181 unsigned semName
= _mesa_sysval_to_semantic(i
);
6183 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6185 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6186 semName
== TGSI_SEMANTIC_VERTEXID
) {
6187 /* From Gallium perspective, these system values are always
6188 * integer, and require native integer support. However, if
6189 * native integer is supported on the vertex stage but not the
6190 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6191 * assumes these system values are floats. To resolve the
6192 * inconsistency, we insert a U2F.
6194 struct st_context
*st
= st_context(ctx
);
6195 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6196 assert(procType
== PIPE_SHADER_VERTEX
);
6197 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6199 if (!ctx
->Const
.NativeIntegers
) {
6200 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6201 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6202 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6206 if (procType
== PIPE_SHADER_FRAGMENT
&&
6207 semName
== TGSI_SEMANTIC_POSITION
)
6208 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6209 program
->wpos_transform_const
);
6211 sysInputs
&= ~(1 << i
);
6216 t
->array_sizes
= program
->array_sizes
;
6217 t
->input_arrays
= program
->input_arrays
;
6218 t
->output_arrays
= program
->output_arrays
;
6220 /* Emit constants and uniforms. TGSI uses a single index space for these,
6221 * so we put all the translated regs in t->constants.
6223 if (proginfo
->Parameters
) {
6224 t
->constants
= (struct ureg_src
*)
6225 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6226 if (t
->constants
== NULL
) {
6227 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6230 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6232 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6233 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6234 case PROGRAM_STATE_VAR
:
6235 case PROGRAM_UNIFORM
:
6236 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6239 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6240 * addressing of the const buffer.
6241 * FIXME: Be smarter and recognize param arrays:
6242 * indirect addressing is only valid within the referenced
6245 case PROGRAM_CONSTANT
:
6246 if (program
->indirect_addr_consts
)
6247 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6249 t
->constants
[i
] = emit_immediate(t
,
6250 proginfo
->Parameters
->ParameterValues
[i
],
6251 proginfo
->Parameters
->Parameters
[i
].DataType
,
6260 if (program
->shader
) {
6261 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6263 for (i
= 0; i
< num_ubos
; i
++) {
6264 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6265 unsigned num_const_vecs
= (size
+ 15) / 16;
6266 unsigned first
, last
;
6267 assert(num_const_vecs
> 0);
6269 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6270 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6274 /* Emit immediate values.
6276 t
->immediates
= (struct ureg_src
*)
6277 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6278 if (t
->immediates
== NULL
) {
6279 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6282 t
->num_immediates
= program
->num_immediates
;
6285 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6286 assert(i
< program
->num_immediates
);
6287 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6289 assert(i
== program
->num_immediates
);
6291 /* texture samplers */
6292 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6293 if (program
->samplers_used
& (1u << i
)) {
6296 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6298 switch (program
->sampler_types
[i
]) {
6300 type
= TGSI_RETURN_TYPE_SINT
;
6302 case GLSL_TYPE_UINT
:
6303 type
= TGSI_RETURN_TYPE_UINT
;
6305 case GLSL_TYPE_FLOAT
:
6306 type
= TGSI_RETURN_TYPE_FLOAT
;
6309 unreachable("not reached");
6312 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6313 type
, type
, type
, type
);
6317 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6318 if (program
->buffers_used
& (1 << i
)) {
6319 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6323 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6325 if (program
->buffers_used
& (1 << i
)) {
6326 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6330 if (program
->use_shared_memory
)
6331 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6333 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6334 if (program
->images_used
& (1 << i
)) {
6335 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6336 program
->image_targets
[i
],
6337 program
->image_formats
[i
],
6342 /* Emit each instruction in turn:
6344 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6345 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6346 compile_tgsi_instruction(t
, inst
);
6349 /* Fix up all emitted labels:
6351 for (i
= 0; i
< t
->labels_count
; i
++) {
6352 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6353 t
->insn
[t
->labels
[i
].branch_target
]);
6356 /* Set the next shader stage hint for VS and TES. */
6358 case PIPE_SHADER_VERTEX
:
6359 case PIPE_SHADER_TESS_EVAL
:
6360 if (program
->shader_program
->SeparateShader
)
6363 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6364 if (program
->shader_program
->_LinkedShaders
[i
]) {
6368 case MESA_SHADER_TESS_CTRL
:
6369 next
= PIPE_SHADER_TESS_CTRL
;
6371 case MESA_SHADER_TESS_EVAL
:
6372 next
= PIPE_SHADER_TESS_EVAL
;
6374 case MESA_SHADER_GEOMETRY
:
6375 next
= PIPE_SHADER_GEOMETRY
;
6377 case MESA_SHADER_FRAGMENT
:
6378 next
= PIPE_SHADER_FRAGMENT
;
6385 ureg_set_next_shader_processor(ureg
, next
);
6399 t
->num_constants
= 0;
6400 free(t
->immediates
);
6401 t
->num_immediates
= 0;
6404 debug_printf("%s: translate error flag set\n", __func__
);
6412 /* ----------------------------- End TGSI code ------------------------------ */
6416 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6417 * generating Mesa IR.
6419 static struct gl_program
*
6420 get_mesa_program(struct gl_context
*ctx
,
6421 struct gl_shader_program
*shader_program
,
6422 struct gl_shader
*shader
)
6424 glsl_to_tgsi_visitor
* v
;
6425 struct gl_program
*prog
;
6426 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6428 struct gl_shader_compiler_options
*options
=
6429 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
6430 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6431 unsigned ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6433 validate_ir_tree(shader
->ir
);
6435 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6438 prog
->Parameters
= _mesa_new_parameter_list();
6439 v
= new glsl_to_tgsi_visitor();
6442 v
->shader_program
= shader_program
;
6444 v
->options
= options
;
6445 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6446 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6448 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6449 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6450 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6451 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6453 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6454 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6457 /* Remove reads from output registers. */
6458 lower_output_reads(shader
->Stage
, shader
->ir
);
6460 /* Emit intermediate IR for main(). */
6461 visit_exec_list(shader
->ir
, v
);
6463 /* Now emit bodies for any functions that were used. */
6465 progress
= GL_FALSE
;
6467 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6468 if (!entry
->bgn_inst
) {
6469 v
->current_function
= entry
;
6471 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6472 entry
->bgn_inst
->function
= entry
;
6474 visit_exec_list(&entry
->sig
->body
, v
);
6476 glsl_to_tgsi_instruction
*last
;
6477 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6478 if (last
->op
!= TGSI_OPCODE_RET
)
6479 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6481 glsl_to_tgsi_instruction
*end
;
6482 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6483 end
->function
= entry
;
6491 /* Print out some information (for debugging purposes) used by the
6492 * optimization passes. */
6495 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6496 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6497 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6498 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6500 for (i
= 0; i
< v
->next_temp
; i
++) {
6501 first_writes
[i
] = -1;
6502 first_reads
[i
] = -1;
6503 last_writes
[i
] = -1;
6506 v
->get_first_temp_read(first_reads
);
6507 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6508 v
->get_last_temp_write(last_writes
);
6509 for (i
= 0; i
< v
->next_temp
; i
++)
6510 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6514 ralloc_free(first_writes
);
6515 ralloc_free(first_reads
);
6516 ralloc_free(last_writes
);
6517 ralloc_free(last_reads
);
6521 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6524 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
6525 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
6526 v
->copy_propagate();
6528 while (v
->eliminate_dead_code());
6530 v
->merge_two_dsts();
6531 v
->merge_registers();
6532 v
->renumber_registers();
6534 /* Write the END instruction. */
6535 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6537 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6539 _mesa_log("GLSL IR for linked %s program %d:\n",
6540 _mesa_shader_stage_to_string(shader
->Stage
),
6541 shader_program
->Name
);
6542 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6546 prog
->Instructions
= NULL
;
6547 prog
->NumInstructions
= 0;
6549 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6550 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
6551 prog
->InputsRead
, prog
->DoubleInputsRead
, prog
->PatchInputsRead
);
6552 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
6553 prog
->OutputsWritten
, 0ULL, prog
->PatchOutputsWritten
);
6554 count_resources(v
, prog
);
6556 /* The GLSL IR won't be needed anymore. */
6557 ralloc_free(shader
->ir
);
6560 /* This must be done before the uniform storage is associated. */
6561 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
6562 (prog
->InputsRead
& VARYING_BIT_POS
||
6563 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6564 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6565 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6568 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6569 wposTransformState
);
6572 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6574 /* Avoid reallocation of the program parameter list, because the uniform
6575 * storage is only associated with the original parameter list.
6576 * This should be enough for Bitmap and DrawPixels constants.
6578 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6580 /* This has to be done last. Any operation the can cause
6581 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6582 * program constant) has to happen before creating this linkage.
6584 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6585 if (!shader_program
->LinkStatus
) {
6586 free_glsl_to_tgsi_visitor(v
);
6590 struct st_vertex_program
*stvp
;
6591 struct st_fragment_program
*stfp
;
6592 struct st_geometry_program
*stgp
;
6593 struct st_tessctrl_program
*sttcp
;
6594 struct st_tesseval_program
*sttep
;
6595 struct st_compute_program
*stcp
;
6597 switch (shader
->Type
) {
6598 case GL_VERTEX_SHADER
:
6599 stvp
= (struct st_vertex_program
*)prog
;
6600 stvp
->glsl_to_tgsi
= v
;
6602 case GL_FRAGMENT_SHADER
:
6603 stfp
= (struct st_fragment_program
*)prog
;
6604 stfp
->glsl_to_tgsi
= v
;
6606 case GL_GEOMETRY_SHADER
:
6607 stgp
= (struct st_geometry_program
*)prog
;
6608 stgp
->glsl_to_tgsi
= v
;
6610 case GL_TESS_CONTROL_SHADER
:
6611 sttcp
= (struct st_tessctrl_program
*)prog
;
6612 sttcp
->glsl_to_tgsi
= v
;
6614 case GL_TESS_EVALUATION_SHADER
:
6615 sttep
= (struct st_tesseval_program
*)prog
;
6616 sttep
->glsl_to_tgsi
= v
;
6618 case GL_COMPUTE_SHADER
:
6619 stcp
= (struct st_compute_program
*)prog
;
6620 stcp
->glsl_to_tgsi
= v
;
6623 assert(!"should not be reached");
6633 st_dump_program_for_shader_db(struct gl_context
*ctx
,
6634 struct gl_shader_program
*prog
)
6636 /* Dump only successfully compiled and linked shaders to the specified
6637 * file. This is for shader-db.
6639 * These options allow some pre-processing of shaders while dumping,
6640 * because some apps have ill-formed shaders.
6642 const char *dump_filename
= os_get_option("ST_DUMP_SHADERS");
6643 const char *insert_directives
= os_get_option("ST_DUMP_INSERT");
6645 if (dump_filename
&& prog
->Name
!= 0) {
6646 FILE *f
= fopen(dump_filename
, "a");
6649 for (unsigned i
= 0; i
< prog
->NumShaders
; i
++) {
6650 const struct gl_shader
*sh
= prog
->Shaders
[i
];
6652 bool skip_version
= false;
6657 source
= sh
->Source
;
6659 /* This string mustn't be changed. shader-db uses it to find
6660 * where the shader begins.
6662 fprintf(f
, "GLSL %s shader %d source for linked program %d:\n",
6663 _mesa_shader_stage_to_string(sh
->Stage
),
6666 /* Dump the forced version if set. */
6667 if (ctx
->Const
.ForceGLSLVersion
) {
6668 fprintf(f
, "#version %i\n", ctx
->Const
.ForceGLSLVersion
);
6669 skip_version
= true;
6672 /* Insert directives (optional). */
6673 if (insert_directives
) {
6674 if (!ctx
->Const
.ForceGLSLVersion
&& prog
->Version
)
6675 fprintf(f
, "#version %i\n", prog
->Version
);
6676 fprintf(f
, "%s\n", insert_directives
);
6677 skip_version
= true;
6680 if (skip_version
&& strncmp(source
, "#version ", 9) == 0) {
6681 const char *next_line
= strstr(source
, "\n");
6684 source
= next_line
+ 1;
6689 fprintf(f
, "%s", source
);
6699 * Called via ctx->Driver.LinkShader()
6700 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6701 * with code lowering and other optimizations.
6704 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6706 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6707 assert(prog
->LinkStatus
);
6709 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6710 if (prog
->_LinkedShaders
[i
] == NULL
)
6714 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6715 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
6716 const struct gl_shader_compiler_options
*options
=
6717 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6718 unsigned ptarget
= st_shader_stage_to_ptarget(stage
);
6719 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6720 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6721 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6722 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6724 /* If there are forms of indirect addressing that the driver
6725 * cannot handle, perform the lowering pass.
6727 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6728 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6729 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6730 options
->EmitNoIndirectInput
,
6731 options
->EmitNoIndirectOutput
,
6732 options
->EmitNoIndirectTemp
,
6733 options
->EmitNoIndirectUniform
);
6736 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6737 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6738 LOWER_UNPACK_SNORM_2x16
|
6739 LOWER_PACK_UNORM_2x16
|
6740 LOWER_UNPACK_UNORM_2x16
|
6741 LOWER_PACK_SNORM_4x8
|
6742 LOWER_UNPACK_SNORM_4x8
|
6743 LOWER_UNPACK_UNORM_4x8
|
6744 LOWER_PACK_UNORM_4x8
;
6746 if (ctx
->Extensions
.ARB_gpu_shader5
)
6747 lower_inst
|= LOWER_PACK_USE_BFI
|
6749 if (!ctx
->st
->has_half_float_packing
)
6750 lower_inst
|= LOWER_PACK_HALF_2x16
|
6751 LOWER_UNPACK_HALF_2x16
;
6753 lower_packing_builtins(ir
, lower_inst
);
6756 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6757 lower_offset_arrays(ir
);
6758 do_mat_op_to_vec(ir
);
6759 lower_instructions(ir
,
6765 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6768 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6769 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6770 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6771 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
6773 do_vec_index_to_cond_assign(ir
);
6774 lower_vector_insert(ir
, true);
6775 lower_quadop_vector(ir
, false);
6777 if (options
->MaxIfDepth
== 0) {
6784 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
6786 progress
= do_common_optimization(ir
, true, true, options
,
6787 ctx
->Const
.NativeIntegers
)
6790 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
6794 validate_ir_tree(ir
);
6797 build_program_resource_list(ctx
, prog
);
6799 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6800 struct gl_program
*linked_prog
;
6802 if (prog
->_LinkedShaders
[i
] == NULL
)
6805 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6808 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6810 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6811 _mesa_shader_stage_to_program(i
),
6813 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6815 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6820 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6823 st_dump_program_for_shader_db(ctx
, prog
);
6828 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6829 const GLuint outputMapping
[],
6830 struct pipe_stream_output_info
*so
)
6833 struct gl_transform_feedback_info
*info
=
6834 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6836 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6837 so
->output
[i
].register_index
=
6838 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6839 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6840 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6841 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6842 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6843 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6846 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6847 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
6849 so
->num_outputs
= info
->NumOutputs
;